hal_internal.h 55 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_INTERNAL_H_
  20. #define _HAL_INTERNAL_H_
  21. #include "qdf_types.h"
  22. #include "qdf_atomic.h"
  23. #include "qdf_lock.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include "pld_common.h"
  27. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  28. #include "qdf_defer.h"
  29. #include "qdf_timer.h"
  30. #endif
  31. #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params)
  32. #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params)
  33. #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params)
  34. #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HAL, params)
  35. #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params)
  36. #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params)
  37. #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params)
  38. #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params)
  39. #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params)
  40. #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params)
  41. #ifdef ENABLE_VERBOSE_DEBUG
  42. extern bool is_hal_verbose_debug_enabled;
  43. #define hal_verbose_debug(params...) \
  44. if (unlikely(is_hal_verbose_debug_enabled)) \
  45. do {\
  46. QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \
  47. } while (0)
  48. #define hal_verbose_hex_dump(params...) \
  49. if (unlikely(is_hal_verbose_debug_enabled)) \
  50. do {\
  51. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \
  52. QDF_TRACE_LEVEL_DEBUG, \
  53. params); \
  54. } while (0)
  55. #else
  56. #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params)
  57. #define hal_verbose_hex_dump(params...) \
  58. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \
  59. params)
  60. #endif
  61. /*
  62. * Given the offset of a field in bytes, returns uint8_t *
  63. */
  64. #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \
  65. (((uint8_t *)(_ptr)) + (_off_in_bytes))
  66. /*
  67. * Given the offset of a field in bytes, returns uint32_t *
  68. */
  69. #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \
  70. (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2))
  71. /*
  72. * Given the offset of a field in bytes, returns uint64_t *
  73. */
  74. #define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \
  75. (((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3))
  76. #define _HAL_MS(_word, _mask, _shift) \
  77. (((_word) & (_mask)) >> (_shift))
  78. /*
  79. * Get number of QWORDS possible for num.
  80. * Its the caller's duty to make sure num is a multiple of QWORD (8)
  81. */
  82. #define HAL_GET_NUM_QWORDS(num) ((num) >> 3)
  83. /*
  84. * Get number of DWORDS possible for num.
  85. * Its the caller's duty to make sure num is a multiple of DWORD (8)
  86. */
  87. #define HAL_GET_NUM_DWORDS(num) ((num) >> 2)
  88. struct hal_hw_cc_config {
  89. uint32_t lut_base_addr_31_0;
  90. uint32_t cc_global_en:1,
  91. page_4k_align:1,
  92. cookie_offset_msb:5,
  93. cookie_page_msb:5,
  94. lut_base_addr_39_32:8,
  95. wbm2sw6_cc_en:1,
  96. wbm2sw5_cc_en:1,
  97. wbm2sw4_cc_en:1,
  98. wbm2sw3_cc_en:1,
  99. wbm2sw2_cc_en:1,
  100. wbm2sw1_cc_en:1,
  101. wbm2sw0_cc_en:1,
  102. wbm2fw_cc_en:1,
  103. error_path_cookie_conv_en:1,
  104. release_path_cookie_conv_en:1,
  105. reserved:2;
  106. };
  107. struct hal_soc_handle;
  108. /*
  109. * typedef hal_soc_handle_t - opaque handle for DP HAL soc
  110. */
  111. typedef struct hal_soc_handle *hal_soc_handle_t;
  112. struct hal_ring_desc;
  113. /*
  114. * typedef hal_ring_desc_t - opaque handle for DP ring descriptor
  115. */
  116. typedef struct hal_ring_desc *hal_ring_desc_t;
  117. struct hal_link_desc;
  118. /*
  119. * typedef hal_link_desc_t - opaque handle for DP link descriptor
  120. */
  121. typedef struct hal_link_desc *hal_link_desc_t;
  122. struct hal_rxdma_desc;
  123. /*
  124. * typedef hal_rxdma_desc_t - opaque handle for DP rxdma dst ring descriptor
  125. */
  126. typedef struct hal_rxdma_desc *hal_rxdma_desc_t;
  127. struct hal_buff_addrinfo;
  128. /*
  129. * typedef hal_buff_addrinfo_t - opaque handle for DP buffer address info
  130. */
  131. typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
  132. struct hal_rx_mon_desc_info;
  133. /*
  134. * typedef hal_rx_mon_desc_info_t - opaque handle for sw monitor ring desc info
  135. */
  136. typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t;
  137. struct hal_buf_info;
  138. /*
  139. * typedef hal_buf_info_t - opaque handle for HAL buffer info
  140. */
  141. typedef struct hal_buf_info *hal_buf_info_t;
  142. struct rx_msdu_desc_info;
  143. /*
  144. * typedef rx_msdu_desc_info_t - opaque handle for rx MSDU descriptor info
  145. */
  146. typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t;
  147. /*
  148. * Opaque handler for PPE VP config.
  149. */
  150. union hal_tx_ppe_vp_config;
  151. union hal_tx_cmn_config_ppe;
  152. union hal_tx_bank_config;
  153. union hal_tx_ppe_idx_map_config;
  154. #ifndef WLAN_SOFTUMAC_SUPPORT
  155. /* TBD: This should be movded to shared HW header file */
  156. enum hal_srng_ring_id {
  157. /* UMAC rings */
  158. HAL_SRNG_REO2SW0 = 0,
  159. HAL_SRNG_REO2SW1 = 1,
  160. HAL_SRNG_REO2SW2 = 2,
  161. HAL_SRNG_REO2SW3 = 3,
  162. HAL_SRNG_REO2SW4 = 4,
  163. HAL_SRNG_REO2SW5 = 5,
  164. HAL_SRNG_REO2SW6 = 6,
  165. HAL_SRNG_REO2SW7 = 7,
  166. HAL_SRNG_REO2SW8 = 8,
  167. HAL_SRNG_REO2TCL = 9,
  168. HAL_SRNG_REO2PPE = 10,
  169. /* 11-15 unused */
  170. HAL_SRNG_SW2REO = 16,
  171. HAL_SRNG_SW2REO1 = 17,
  172. HAL_SRNG_SW2REO2 = 18,
  173. HAL_SRNG_SW2REO3 = 19,
  174. HAL_SRNG_REO_CMD = 20,
  175. HAL_SRNG_REO_STATUS = 21,
  176. /* 22-23 unused */
  177. HAL_SRNG_SW2TCL1 = 24,
  178. HAL_SRNG_SW2TCL2 = 25,
  179. HAL_SRNG_SW2TCL3 = 26,
  180. HAL_SRNG_SW2TCL4 = 27,
  181. HAL_SRNG_SW2TCL5 = 28,
  182. HAL_SRNG_SW2TCL6 = 29,
  183. HAL_SRNG_PPE2TCL1 = 30,
  184. /* 31-39 unused */
  185. HAL_SRNG_SW2TCL_CMD = 40,
  186. HAL_SRNG_TCL_STATUS = 41,
  187. HAL_SRNG_SW2TCL_CREDIT = 42,
  188. /* 43-63 unused */
  189. HAL_SRNG_CE_0_SRC = 64,
  190. HAL_SRNG_CE_1_SRC = 65,
  191. HAL_SRNG_CE_2_SRC = 66,
  192. HAL_SRNG_CE_3_SRC = 67,
  193. HAL_SRNG_CE_4_SRC = 68,
  194. HAL_SRNG_CE_5_SRC = 69,
  195. HAL_SRNG_CE_6_SRC = 70,
  196. HAL_SRNG_CE_7_SRC = 71,
  197. HAL_SRNG_CE_8_SRC = 72,
  198. HAL_SRNG_CE_9_SRC = 73,
  199. HAL_SRNG_CE_10_SRC = 74,
  200. HAL_SRNG_CE_11_SRC = 75,
  201. HAL_SRNG_CE_12_SRC = 76,
  202. HAL_SRNG_CE_13_SRC = 77,
  203. HAL_SRNG_CE_14_SRC = 78,
  204. HAL_SRNG_CE_15_SRC = 79,
  205. /* 80 */
  206. HAL_SRNG_CE_0_DST = 81,
  207. HAL_SRNG_CE_1_DST = 82,
  208. HAL_SRNG_CE_2_DST = 83,
  209. HAL_SRNG_CE_3_DST = 84,
  210. HAL_SRNG_CE_4_DST = 85,
  211. HAL_SRNG_CE_5_DST = 86,
  212. HAL_SRNG_CE_6_DST = 87,
  213. HAL_SRNG_CE_7_DST = 89,
  214. HAL_SRNG_CE_8_DST = 90,
  215. HAL_SRNG_CE_9_DST = 91,
  216. HAL_SRNG_CE_10_DST = 92,
  217. HAL_SRNG_CE_11_DST = 93,
  218. HAL_SRNG_CE_12_DST = 94,
  219. HAL_SRNG_CE_13_DST = 95,
  220. HAL_SRNG_CE_14_DST = 96,
  221. HAL_SRNG_CE_15_DST = 97,
  222. /* 98-99 unused */
  223. HAL_SRNG_CE_0_DST_STATUS = 100,
  224. HAL_SRNG_CE_1_DST_STATUS = 101,
  225. HAL_SRNG_CE_2_DST_STATUS = 102,
  226. HAL_SRNG_CE_3_DST_STATUS = 103,
  227. HAL_SRNG_CE_4_DST_STATUS = 104,
  228. HAL_SRNG_CE_5_DST_STATUS = 105,
  229. HAL_SRNG_CE_6_DST_STATUS = 106,
  230. HAL_SRNG_CE_7_DST_STATUS = 107,
  231. HAL_SRNG_CE_8_DST_STATUS = 108,
  232. HAL_SRNG_CE_9_DST_STATUS = 109,
  233. HAL_SRNG_CE_10_DST_STATUS = 110,
  234. HAL_SRNG_CE_11_DST_STATUS = 111,
  235. HAL_SRNG_CE_12_DST_STATUS = 112,
  236. HAL_SRNG_CE_13_DST_STATUS = 113,
  237. HAL_SRNG_CE_14_DST_STATUS = 114,
  238. HAL_SRNG_CE_15_DST_STATUS = 115,
  239. /* 116-119 unused */
  240. HAL_SRNG_WBM_IDLE_LINK = 120,
  241. HAL_SRNG_WBM_SW_RELEASE = 121,
  242. HAL_SRNG_WBM_SW1_RELEASE = 122,
  243. HAL_SRNG_WBM_PPE_RELEASE = 123,
  244. /* 124-127 unused */
  245. HAL_SRNG_WBM2SW0_RELEASE = 128,
  246. HAL_SRNG_WBM2SW1_RELEASE = 129,
  247. HAL_SRNG_WBM2SW2_RELEASE = 130,
  248. HAL_SRNG_WBM2SW3_RELEASE = 131,
  249. HAL_SRNG_WBM2SW4_RELEASE = 132,
  250. HAL_SRNG_WBM2SW5_RELEASE = 133,
  251. HAL_SRNG_WBM2SW6_RELEASE = 134,
  252. HAL_SRNG_WBM_ERROR_RELEASE = 135,
  253. /* 136-158 unused */
  254. HAL_SRNG_UMAC_ID_END = 159,
  255. /* Common DMAC rings shared by all LMACs */
  256. HAL_SRNG_SW2RXDMA_BUF0 = 160,
  257. HAL_SRNG_SW2RXDMA_BUF1 = 161,
  258. HAL_SRNG_SW2RXDMA_BUF2 = 162,
  259. /* 163-167 unused */
  260. HAL_SRNG_SW2RXMON_BUF0 = 168,
  261. /* 169-175 unused */
  262. /* 177-183 unused */
  263. HAL_SRNG_DMAC_CMN_ID_END = 183,
  264. /* LMAC rings - The following set will be replicated for each LMAC */
  265. HAL_SRNG_LMAC1_ID_START = 184,
  266. HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
  267. HAL_SRNG_WMAC1_SW2RXDMA1_BUF,
  268. #ifdef IPA_OFFLOAD
  269. HAL_SRNG_WMAC1_SW2RXDMA0_BUF1,
  270. #ifdef IPA_WDI3_VLAN_SUPPORT
  271. HAL_SRNG_WMAC1_SW2RXDMA0_BUF2,
  272. #endif
  273. #endif
  274. #ifdef FEATURE_DIRECT_LINK
  275. HAL_SRNG_WMAC1_RX_DIRECT_LINK_SW_REFILL_RING,
  276. #endif
  277. HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  278. HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF,
  279. HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  280. HAL_SRNG_WMAC1_RXDMA2SW0,
  281. HAL_SRNG_WMAC1_RXDMA2SW1,
  282. HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1,
  283. HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  284. #ifdef WLAN_FEATURE_CIF_CFR
  285. HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  286. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  287. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1,
  288. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING2,
  289. #else
  290. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  291. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1,
  292. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING2,
  293. #endif
  294. HAL_SRNG_WMAC1_TXMON2SW0,
  295. HAL_SRNG_SW2TXMON_BUF0,
  296. HAL_SRNG_LMAC1_ID_END = (HAL_SRNG_SW2TXMON_BUF0 + 2),
  297. };
  298. #else
  299. /* lmac rings are remains same for evros */
  300. enum hal_srng_ring_id {
  301. HAL_SRNG_LMAC1_ID_START,
  302. HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
  303. HAL_SRNG_WMAC1_SW2RXDMA1_BUF,
  304. #ifdef IPA_OFFLOAD
  305. HAL_SRNG_WMAC1_SW2RXDMA0_BUF1,
  306. #ifdef IPA_WDI3_VLAN_SUPPORT
  307. HAL_SRNG_WMAC1_SW2RXDMA0_BUF2,
  308. #endif
  309. #endif
  310. #ifdef FEATURE_DIRECT_LINK
  311. HAL_SRNG_WMAC1_RX_DIRECT_LINK_SW_REFILL_RING,
  312. #endif
  313. HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  314. HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF,
  315. HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  316. HAL_SRNG_WMAC1_RXDMA2SW0,
  317. HAL_SRNG_WMAC1_RXDMA2SW1,
  318. HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1,
  319. HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  320. #ifdef WLAN_FEATURE_CIF_CFR
  321. HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  322. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  323. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1,
  324. #else
  325. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  326. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1,
  327. #endif
  328. HAL_SRNG_WMAC1_TXMON2SW0,
  329. HAL_SRNG_SW2TXMON_BUF0,
  330. HAL_SRNG_WMAC1_SW2RXDMA_LINK_RING = HAL_SRNG_SW2TXMON_BUF0 + 2,
  331. HAL_SRNG_LMAC1_ID_END = HAL_SRNG_WMAC1_SW2RXDMA_LINK_RING,
  332. };
  333. #define HAL_SRNG_DMAC_CMN_ID_END 0
  334. #define HAL_SRNG_WBM_IDLE_LINK 120
  335. #endif
  336. #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
  337. #define HAL_MAX_LMACS 3
  338. #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
  339. #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
  340. #define HAL_SRNG_ID_MAX (HAL_SRNG_DMAC_CMN_ID_END + HAL_MAX_LMAC_RINGS)
  341. /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */
  342. enum hal_ring_type {
  343. REO_DST = 0,
  344. REO_EXCEPTION = 1,
  345. REO_REINJECT = 2,
  346. REO_CMD = 3,
  347. REO_STATUS = 4,
  348. TCL_DATA = 5,
  349. TCL_CMD_CREDIT = 6,
  350. TCL_STATUS = 7,
  351. CE_SRC = 8,
  352. CE_DST = 9,
  353. CE_DST_STATUS = 10,
  354. WBM_IDLE_LINK = 11,
  355. SW2WBM_RELEASE = 12,
  356. WBM2SW_RELEASE = 13,
  357. RXDMA_BUF = 14,
  358. RXDMA_DST = 15,
  359. RXDMA_MONITOR_BUF = 16,
  360. RXDMA_MONITOR_STATUS = 17,
  361. RXDMA_MONITOR_DST = 18,
  362. RXDMA_MONITOR_DESC = 19,
  363. DIR_BUF_RX_DMA_SRC = 20,
  364. #ifdef WLAN_FEATURE_CIF_CFR
  365. WIFI_POS_SRC,
  366. #endif
  367. REO2PPE,
  368. PPE2TCL,
  369. PPE_RELEASE,
  370. TX_MONITOR_BUF,
  371. TX_MONITOR_DST,
  372. SW2RXDMA_NEW,
  373. SW2RXDMA_LINK_RELEASE,
  374. MAX_RING_TYPES
  375. };
  376. enum SRNG_REGISTERS {
  377. DST_HP = 0,
  378. DST_TP,
  379. DST_ID,
  380. DST_MISC,
  381. DST_HP_ADDR_LSB,
  382. DST_HP_ADDR_MSB,
  383. DST_MSI1_BASE_LSB,
  384. DST_MSI1_BASE_MSB,
  385. DST_MSI1_DATA,
  386. DST_MISC_1,
  387. #ifdef CONFIG_BERYLLIUM
  388. DST_MSI2_BASE_LSB,
  389. DST_MSI2_BASE_MSB,
  390. DST_MSI2_DATA,
  391. #endif
  392. DST_BASE_LSB,
  393. DST_BASE_MSB,
  394. DST_PRODUCER_INT_SETUP,
  395. #ifdef CONFIG_BERYLLIUM
  396. DST_PRODUCER_INT2_SETUP,
  397. #endif
  398. SRC_HP,
  399. SRC_TP,
  400. SRC_ID,
  401. SRC_MISC,
  402. SRC_TP_ADDR_LSB,
  403. SRC_TP_ADDR_MSB,
  404. SRC_MSI1_BASE_LSB,
  405. SRC_MSI1_BASE_MSB,
  406. SRC_MSI1_DATA,
  407. SRC_BASE_LSB,
  408. SRC_BASE_MSB,
  409. SRC_CONSUMER_INT_SETUP_IX0,
  410. SRC_CONSUMER_INT_SETUP_IX1,
  411. #ifdef DP_UMAC_HW_RESET_SUPPORT
  412. SRC_CONSUMER_PREFETCH_TIMER,
  413. #endif
  414. SRNG_REGISTER_MAX,
  415. };
  416. enum hal_srng_dir {
  417. HAL_SRNG_SRC_RING,
  418. HAL_SRNG_DST_RING
  419. };
  420. /**
  421. * enum hal_reo_remap_reg - REO remap registers
  422. * @HAL_REO_REMAP_REG_IX0: reo remap reg IX0
  423. * @HAL_REO_REMAP_REG_IX1: reo remap reg IX1
  424. * @HAL_REO_REMAP_REG_IX2: reo remap reg IX2
  425. * @HAL_REO_REMAP_REG_IX3: reo remap reg IX3
  426. */
  427. enum hal_reo_remap_reg {
  428. HAL_REO_REMAP_REG_IX0,
  429. HAL_REO_REMAP_REG_IX1,
  430. HAL_REO_REMAP_REG_IX2,
  431. HAL_REO_REMAP_REG_IX3
  432. };
  433. /* Lock wrappers for SRNG */
  434. #define hal_srng_lock_t qdf_spinlock_t
  435. #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock)
  436. #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock)
  437. #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock)
  438. #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock)
  439. #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock)
  440. struct hal_soc;
  441. struct hal_ring_handle;
  442. /*
  443. * typedef hal_ring_handle_t - opaque handle for DP HAL SRNG
  444. */
  445. typedef struct hal_ring_handle *hal_ring_handle_t;
  446. #define MAX_SRNG_REG_GROUPS 2
  447. /* Hal Srng bit mask
  448. * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down
  449. */
  450. #define HAL_SRNG_FLUSH_EVENT BIT(0)
  451. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  452. /**
  453. * struct hal_reg_write_q_elem - delayed register write queue element
  454. * @srng: hal_srng queued for a delayed write
  455. * @addr: iomem address of the register
  456. * @enqueue_val: register value at the time of delayed write enqueue
  457. * @dequeue_val: register value at the time of delayed write dequeue
  458. * @valid: whether this entry is valid or not
  459. * @enqueue_time: enqueue time (qdf_log_timestamp)
  460. * @work_scheduled_time: work scheduled time (qdf_log_timestamp)
  461. * @dequeue_time: dequeue time (qdf_log_timestamp)
  462. * @cpu_id: record cpuid when schedule work
  463. * @ring_id: record srng id
  464. */
  465. struct hal_reg_write_q_elem {
  466. struct hal_srng *srng;
  467. void __iomem *addr;
  468. uint32_t enqueue_val;
  469. uint32_t dequeue_val;
  470. uint8_t valid;
  471. qdf_time_t enqueue_time;
  472. qdf_time_t work_scheduled_time;
  473. qdf_time_t dequeue_time;
  474. int cpu_id;
  475. int ring_id;
  476. };
  477. /**
  478. * struct hal_reg_write_srng_stats - srng stats to keep track of register writes
  479. * @enqueues: writes enqueued to delayed work
  480. * @dequeues: writes dequeued from delayed work (not written yet)
  481. * @coalesces: writes not enqueued since srng is already queued up
  482. * @direct: writes not enqueued and written to register directly
  483. * @dequeue_delay: dequeue operation be delayed
  484. * @pending: number of buffers pending in delay reg write
  485. */
  486. struct hal_reg_write_srng_stats {
  487. uint32_t enqueues;
  488. uint32_t dequeues;
  489. uint32_t coalesces;
  490. uint32_t direct;
  491. uint32_t dequeue_delay;
  492. qdf_atomic_t pending;
  493. };
  494. /**
  495. * enum hal_reg_sched_delay - ENUM for write sched delay histogram
  496. * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us
  497. * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us
  498. * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us
  499. * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us
  500. * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array)
  501. */
  502. enum hal_reg_sched_delay {
  503. REG_WRITE_SCHED_DELAY_SUB_100us,
  504. REG_WRITE_SCHED_DELAY_SUB_1000us,
  505. REG_WRITE_SCHED_DELAY_SUB_5000us,
  506. REG_WRITE_SCHED_DELAY_GT_5000us,
  507. REG_WRITE_SCHED_DELAY_HIST_MAX,
  508. };
  509. /**
  510. * struct hal_reg_write_soc_stats - soc stats to keep track of register writes
  511. * @enqueues: writes enqueued to delayed work
  512. * @dequeues: writes dequeued from delayed work (not written yet)
  513. * @coalesces: writes not enqueued since srng is already queued up
  514. * @direct: writes not enqueud and writted to register directly
  515. * @prevent_l1_fails: prevent l1 API failed
  516. * @q_depth: current queue depth in delayed register write queue
  517. * @max_q_depth: maximum queue for delayed register write queue
  518. * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram
  519. * @dequeue_delay: dequeue operation be delayed
  520. */
  521. struct hal_reg_write_soc_stats {
  522. qdf_atomic_t enqueues;
  523. uint32_t dequeues;
  524. qdf_atomic_t coalesces;
  525. qdf_atomic_t direct;
  526. uint32_t prevent_l1_fails;
  527. qdf_atomic_t q_depth;
  528. uint32_t max_q_depth;
  529. uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX];
  530. uint32_t dequeue_delay;
  531. };
  532. #endif
  533. struct hal_offload_info {
  534. uint8_t lro_eligible;
  535. uint8_t tcp_proto;
  536. uint8_t tcp_pure_ack;
  537. uint8_t ipv6_proto;
  538. uint8_t tcp_offset;
  539. uint16_t tcp_csum;
  540. uint16_t tcp_win;
  541. uint32_t tcp_seq_num;
  542. uint32_t tcp_ack_num;
  543. uint32_t flow_id;
  544. };
  545. #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING
  546. /**
  547. * enum hal_srng_high_wm_bin - BIN for SRNG high watermark
  548. * @HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT: <50% SRNG entries used
  549. * @HAL_SRNG_HIGH_WM_BIN_50_to_60: 50-60% SRNG entries used
  550. * @HAL_SRNG_HIGH_WM_BIN_60_to_70: 60-70% SRNG entries used
  551. * @HAL_SRNG_HIGH_WM_BIN_70_to_80: 70-80% SRNG entries used
  552. * @HAL_SRNG_HIGH_WM_BIN_80_to_90: 80-90% SRNG entries used
  553. * @HAL_SRNG_HIGH_WM_BIN_90_to_100: 90-100% SRNG entries used
  554. * @HAL_SRNG_HIGH_WM_BIN_MAX: maximum enumeration
  555. */
  556. enum hal_srng_high_wm_bin {
  557. HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT,
  558. HAL_SRNG_HIGH_WM_BIN_50_to_60,
  559. HAL_SRNG_HIGH_WM_BIN_60_to_70,
  560. HAL_SRNG_HIGH_WM_BIN_70_to_80,
  561. HAL_SRNG_HIGH_WM_BIN_80_to_90,
  562. HAL_SRNG_HIGH_WM_BIN_90_to_100,
  563. HAL_SRNG_HIGH_WM_BIN_MAX,
  564. };
  565. /**
  566. * struct hal_srng_high_wm_info - SRNG usage high watermark info
  567. * @val: highest number of entries used in SRNG
  568. * @timestamp: Timestamp when the max num entries were in used for a SRNG
  569. * @bin_thresh: threshold for each bins
  570. * @bins: Bins for srng usage
  571. */
  572. struct hal_srng_high_wm_info {
  573. uint32_t val;
  574. uint64_t timestamp;
  575. uint32_t bin_thresh[HAL_SRNG_HIGH_WM_BIN_MAX];
  576. uint32_t bins[HAL_SRNG_HIGH_WM_BIN_MAX];
  577. };
  578. #endif
  579. #define DEFAULT_TSF_ID 1
  580. /**
  581. * enum hal_scratch_reg_enum - Enum to indicate scratch register values
  582. * @PMM_QTIMER_GLOBAL_OFFSET_LO_US: QTIMER GLOBAL OFFSET LOW
  583. * @PMM_QTIMER_GLOBAL_OFFSET_HI_US: QTIMER GLOBAL OFFSET HIGH
  584. * @PMM_MAC0_TSF1_OFFSET_LO_US: MAC0 TSF1 OFFSET LOW
  585. * @PMM_MAC0_TSF1_OFFSET_HI_US: MAC0 TSF1 OFFSET HIGH
  586. * @PMM_MAC0_TSF2_OFFSET_LO_US: MAC0 TSF2 OFFSET LOW
  587. * @PMM_MAC0_TSF2_OFFSET_HI_US: MAC0 TSF2 OFFSET HIGH
  588. * @PMM_MAC1_TSF1_OFFSET_LO_US: MAC1 TSF1 OFFSET LOW
  589. * @PMM_MAC1_TSF1_OFFSET_HI_US: MAC1 TSF1 OFFSET HIGH
  590. * @PMM_MAC1_TSF2_OFFSET_LO_US: MAC1 TSF2 OFFSET LOW
  591. * @PMM_MAC1_TSF2_OFFSET_HI_US: MAC1 TSF2 OFFSET HIGH
  592. * @PMM_MLO_OFFSET_LO_US: MLO OFFSET LOW
  593. * @PMM_MLO_OFFSET_HI_US: MLO OFFSET HIGH
  594. * @PMM_TQM_CLOCK_OFFSET_LO_US: TQM CLOCK OFFSET LOW
  595. * @PMM_TQM_CLOCK_OFFSET_HI_US: TQM CLOCK OFFSET HIGH
  596. * @PMM_Q6_CRASH_REASON: Q6 CRASH REASON
  597. * @PMM_SCRATCH_TWT_OFFSET: TWT OFFSET
  598. * @PMM_PMM_REG_MAX: Max PMM REG value
  599. */
  600. enum hal_scratch_reg_enum {
  601. PMM_QTIMER_GLOBAL_OFFSET_LO_US,
  602. PMM_QTIMER_GLOBAL_OFFSET_HI_US,
  603. PMM_MAC0_TSF1_OFFSET_LO_US,
  604. PMM_MAC0_TSF1_OFFSET_HI_US,
  605. PMM_MAC0_TSF2_OFFSET_LO_US,
  606. PMM_MAC0_TSF2_OFFSET_HI_US,
  607. PMM_MAC1_TSF1_OFFSET_LO_US,
  608. PMM_MAC1_TSF1_OFFSET_HI_US,
  609. PMM_MAC1_TSF2_OFFSET_LO_US,
  610. PMM_MAC1_TSF2_OFFSET_HI_US,
  611. PMM_MLO_OFFSET_LO_US,
  612. PMM_MLO_OFFSET_HI_US,
  613. PMM_TQM_CLOCK_OFFSET_LO_US,
  614. PMM_TQM_CLOCK_OFFSET_HI_US,
  615. PMM_Q6_CRASH_REASON,
  616. PMM_SCRATCH_TWT_OFFSET,
  617. PMM_PMM_REG_MAX
  618. };
  619. /**
  620. * hal_get_tsf_enum(): API to get the enum corresponding to the mac and tsf id
  621. *
  622. * @tsf_id: tsf id
  623. * @mac_id: mac id
  624. * @tsf_enum_low: Pointer to update low scratch register
  625. * @tsf_enum_hi: Pointer to update hi scratch register
  626. *
  627. * Return: void
  628. */
  629. static inline void
  630. hal_get_tsf_enum(uint32_t tsf_id, uint32_t mac_id,
  631. enum hal_scratch_reg_enum *tsf_enum_low,
  632. enum hal_scratch_reg_enum *tsf_enum_hi)
  633. {
  634. if (mac_id == 0) {
  635. if (tsf_id == 0) {
  636. *tsf_enum_low = PMM_MAC0_TSF1_OFFSET_LO_US;
  637. *tsf_enum_hi = PMM_MAC0_TSF1_OFFSET_HI_US;
  638. } else if (tsf_id == 1) {
  639. *tsf_enum_low = PMM_MAC0_TSF2_OFFSET_LO_US;
  640. *tsf_enum_hi = PMM_MAC0_TSF2_OFFSET_HI_US;
  641. }
  642. } else if (mac_id == 1) {
  643. if (tsf_id == 0) {
  644. *tsf_enum_low = PMM_MAC1_TSF1_OFFSET_LO_US;
  645. *tsf_enum_hi = PMM_MAC1_TSF1_OFFSET_HI_US;
  646. } else if (tsf_id == 1) {
  647. *tsf_enum_low = PMM_MAC1_TSF2_OFFSET_LO_US;
  648. *tsf_enum_hi = PMM_MAC1_TSF2_OFFSET_HI_US;
  649. }
  650. }
  651. }
  652. #ifdef HAL_SRNG_REG_HIS_DEBUG
  653. #define HAL_SRNG_REG_MAX_ENTRIES 64
  654. /**
  655. * struct hal_srng_reg_his_entry - history entry for single srng pointer
  656. * register update
  657. * @write_time: register write timestamp
  658. * @write_value: register write value
  659. */
  660. struct hal_srng_reg_his_entry {
  661. qdf_time_t write_time;
  662. uint32_t write_value;
  663. };
  664. /**
  665. * struct hal_srng_reg_his_ctx - context for srng pointer writing history
  666. * @current_idx: the index which has recorded srng pointer writing
  667. * @reg_his_arr: array to record the history
  668. */
  669. struct hal_srng_reg_his_ctx {
  670. qdf_atomic_t current_idx;
  671. struct hal_srng_reg_his_entry reg_his_arr[HAL_SRNG_REG_MAX_ENTRIES];
  672. };
  673. #endif
  674. /* Common SRNG ring structure for source and destination rings */
  675. struct hal_srng {
  676. /* Unique SRNG ring ID */
  677. uint8_t ring_id;
  678. /* Ring initialization done */
  679. uint8_t initialized;
  680. /* Interrupt/MSI value assigned to this ring */
  681. int irq;
  682. /* Physical base address of the ring */
  683. qdf_dma_addr_t ring_base_paddr;
  684. /* Virtual base address of the ring */
  685. uint32_t *ring_base_vaddr;
  686. /* virtual address end */
  687. uint32_t *ring_vaddr_end;
  688. /* Number of entries in ring */
  689. uint32_t num_entries;
  690. /* Ring size */
  691. uint32_t ring_size;
  692. /* Ring size mask */
  693. uint32_t ring_size_mask;
  694. /* Size of ring entry */
  695. uint32_t entry_size;
  696. /* Interrupt timer threshold – in micro seconds */
  697. uint32_t intr_timer_thres_us;
  698. /* Interrupt batch counter threshold – in number of ring entries */
  699. uint32_t intr_batch_cntr_thres_entries;
  700. /* Applicable only for CE dest ring */
  701. uint32_t prefetch_timer;
  702. /* MSI Address */
  703. qdf_dma_addr_t msi_addr;
  704. /* MSI data */
  705. uint32_t msi_data;
  706. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  707. /* MSI2 Address */
  708. qdf_dma_addr_t msi2_addr;
  709. /* MSI2 data */
  710. uint32_t msi2_data;
  711. #endif
  712. /* Misc flags */
  713. uint32_t flags;
  714. /* Lock for serializing ring index updates */
  715. hal_srng_lock_t lock;
  716. /* Start offset of SRNG register groups for this ring
  717. * TBD: See if this is required - register address can be derived
  718. * from ring ID
  719. */
  720. void *hwreg_base[MAX_SRNG_REG_GROUPS];
  721. /* Ring type/name */
  722. enum hal_ring_type ring_type;
  723. /* Source or Destination ring */
  724. enum hal_srng_dir ring_dir;
  725. union {
  726. struct {
  727. /* SW tail pointer */
  728. uint32_t tp;
  729. /* Shadow head pointer location to be updated by HW */
  730. uint32_t *hp_addr;
  731. /* Cached head pointer */
  732. uint32_t cached_hp;
  733. /* Tail pointer location to be updated by SW – This
  734. * will be a register address and need not be
  735. * accessed through SW structure */
  736. uint32_t *tp_addr;
  737. /* Current SW loop cnt */
  738. uint32_t loop_cnt;
  739. /* max transfer size */
  740. uint16_t max_buffer_length;
  741. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  742. /* near full IRQ supported */
  743. uint16_t nf_irq_support;
  744. /* High threshold for Near full IRQ */
  745. uint16_t high_thresh;
  746. #endif
  747. } dst_ring;
  748. struct {
  749. /* SW head pointer */
  750. uint32_t hp;
  751. /* SW reap head pointer */
  752. uint32_t reap_hp;
  753. /* Shadow tail pointer location to be updated by HW */
  754. uint32_t *tp_addr;
  755. /* Cached tail pointer */
  756. uint32_t cached_tp;
  757. /* Head pointer location to be updated by SW – This
  758. * will be a register address and need not be accessed
  759. * through SW structure */
  760. uint32_t *hp_addr;
  761. /* Low threshold – in number of ring entries */
  762. uint32_t low_threshold;
  763. } src_ring;
  764. } u;
  765. struct hal_soc *hal_soc;
  766. /* Number of times hp/tp updated in runtime resume */
  767. uint32_t flush_count;
  768. /* hal srng event flag*/
  769. unsigned long srng_event;
  770. /* last flushed time stamp */
  771. uint64_t last_flush_ts;
  772. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  773. /* last ring desc entry cleared */
  774. uint32_t last_desc_cleared;
  775. #endif
  776. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  777. /* flag to indicate whether srng is already queued for delayed write */
  778. uint8_t reg_write_in_progress;
  779. /* last dequeue elem time stamp */
  780. qdf_time_t last_dequeue_time;
  781. /* srng specific delayed write stats */
  782. struct hal_reg_write_srng_stats wstats;
  783. #endif
  784. #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING
  785. struct hal_srng_high_wm_info high_wm;
  786. #endif
  787. /* Timer threshold to issue ring pointer update - in micro seconds */
  788. uint16_t pointer_timer_threshold;
  789. /* Number threshold of ring entries to issue pointer update */
  790. uint8_t pointer_num_threshold;
  791. #ifdef HAL_SRNG_REG_HIS_DEBUG
  792. /* pointer register writing history for this srng */
  793. struct hal_srng_reg_his_ctx *reg_his_ctx;
  794. #endif
  795. };
  796. #ifdef HAL_SRNG_REG_HIS_DEBUG
  797. /**
  798. * hal_srng_reg_his_init() - SRNG register history context initialize
  799. *
  800. * @srng: SRNG handle pointer
  801. *
  802. * Return: None
  803. */
  804. static inline
  805. void hal_srng_reg_his_init(struct hal_srng *srng)
  806. {
  807. qdf_atomic_set(&srng->reg_his_ctx->current_idx, -1);
  808. }
  809. /**
  810. * hal_srng_reg_his_add() - add pointer writing history to SRNG
  811. *
  812. * @srng: SRNG handle pointer
  813. * @reg_val: pointer value to write
  814. *
  815. * Return: None
  816. */
  817. static inline
  818. void hal_srng_reg_his_add(struct hal_srng *srng, uint32_t reg_val)
  819. {
  820. uint32_t write_idx;
  821. struct hal_srng_reg_his_entry *reg_his_entry;
  822. write_idx = qdf_atomic_inc_return(&srng->reg_his_ctx->current_idx);
  823. write_idx = write_idx & (HAL_SRNG_REG_MAX_ENTRIES - 1);
  824. reg_his_entry = &srng->reg_his_ctx->reg_his_arr[write_idx];
  825. reg_his_entry->write_time = qdf_get_log_timestamp();
  826. reg_his_entry->write_value = reg_val;
  827. }
  828. #else
  829. static inline
  830. void hal_srng_reg_his_init(struct hal_srng *srng)
  831. {
  832. }
  833. static inline
  834. void hal_srng_reg_his_add(struct hal_srng *srng, uint32_t reg_val)
  835. {
  836. }
  837. #endif
  838. /* HW SRNG configuration table */
  839. struct hal_hw_srng_config {
  840. int start_ring_id;
  841. uint16_t max_rings;
  842. uint16_t entry_size;
  843. uint32_t reg_start[MAX_SRNG_REG_GROUPS];
  844. uint16_t reg_size[MAX_SRNG_REG_GROUPS];
  845. uint8_t lmac_ring;
  846. enum hal_srng_dir ring_dir;
  847. uint32_t max_size;
  848. bool nf_irq_support;
  849. bool dmac_cmn_ring;
  850. };
  851. #define MAX_SHADOW_REGISTERS 40
  852. #define MAX_GENERIC_SHADOW_REG 5
  853. /**
  854. * struct shadow_reg_config - Hal soc structure that contains
  855. * the list of generic shadow registers
  856. * @target_register: target reg offset
  857. * @shadow_config_index: shadow config index in shadow config
  858. * list sent to FW
  859. * @va: virtual addr of shadow reg
  860. *
  861. * This structure holds the generic registers that are mapped to
  862. * the shadow region and holds the mapping of the target
  863. * register offset to shadow config index provided to FW during
  864. * init
  865. */
  866. struct shadow_reg_config {
  867. uint32_t target_register;
  868. int shadow_config_index;
  869. uint64_t va;
  870. };
  871. /* REO parameters to be passed to hal_reo_setup */
  872. struct hal_reo_params {
  873. /** rx hash steering enabled or disabled */
  874. bool rx_hash_enabled;
  875. /** reo remap 0 register */
  876. uint32_t remap0;
  877. /** reo remap 1 register */
  878. uint32_t remap1;
  879. /** reo remap 2 register */
  880. uint32_t remap2;
  881. /** fragment destination ring */
  882. uint8_t frag_dst_ring;
  883. /* Destination for alternate */
  884. uint8_t alt_dst_ind_0;
  885. /* reo_qref struct for mlo and non mlo table */
  886. struct reo_queue_ref_table *reo_qref;
  887. };
  888. /**
  889. * enum hal_reo_cmd_type: Enum for REO command type
  890. * @CMD_GET_QUEUE_STATS: Get REO queue status/stats
  891. * @CMD_FLUSH_QUEUE: Flush all frames in REO queue
  892. * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache
  893. * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked
  894. * earlier with a ‘REO_FLUSH_CACHE’ command
  895. * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
  896. * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings
  897. */
  898. enum hal_reo_cmd_type {
  899. CMD_GET_QUEUE_STATS = 0,
  900. CMD_FLUSH_QUEUE = 1,
  901. CMD_FLUSH_CACHE = 2,
  902. CMD_UNBLOCK_CACHE = 3,
  903. CMD_FLUSH_TIMEOUT_LIST = 4,
  904. CMD_UPDATE_RX_REO_QUEUE = 5
  905. };
  906. /**
  907. * enum hal_tx_mcast_mlo_reinject_notify
  908. * @HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY: MLO Mcast reinject routed to FW
  909. * @HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY: MLO Mcast reinject routed to TQM
  910. */
  911. enum hal_tx_mcast_mlo_reinject_notify {
  912. HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY = 0,
  913. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY,
  914. };
  915. /**
  916. * enum hal_tx_vdev_mismatch_notify
  917. * @HAL_TX_VDEV_MISMATCH_TQM_NOTIFY: vdev mismatch exception routed to TQM
  918. * @HAL_TX_VDEV_MISMATCH_FW_NOTIFY: vdev mismatch exception routed to FW
  919. */
  920. enum hal_tx_vdev_mismatch_notify {
  921. HAL_TX_VDEV_MISMATCH_TQM_NOTIFY = 0,
  922. HAL_TX_VDEV_MISMATCH_FW_NOTIFY,
  923. };
  924. struct hal_rx_pkt_capture_flags {
  925. uint8_t encrypt_type;
  926. uint8_t fragment_flag;
  927. uint8_t fcs_err;
  928. uint32_t chan_freq;
  929. uint32_t rssi_comb;
  930. uint64_t tsft;
  931. };
  932. /**
  933. * struct reo_queue_ref_table - Reo qref LUT addr
  934. * @mlo_reo_qref_table_vaddr: MLO table vaddr
  935. * @non_mlo_reo_qref_table_vaddr: Non MLO table vaddr
  936. * @mlo_reo_qref_table_paddr: MLO table paddr
  937. * @non_mlo_reo_qref_table_paddr: Non MLO table paddr
  938. * @reo_qref_table_en: Enable flag
  939. */
  940. struct reo_queue_ref_table {
  941. uint64_t *mlo_reo_qref_table_vaddr;
  942. uint64_t *non_mlo_reo_qref_table_vaddr;
  943. qdf_dma_addr_t mlo_reo_qref_table_paddr;
  944. qdf_dma_addr_t non_mlo_reo_qref_table_paddr;
  945. uint8_t reo_qref_table_en;
  946. };
  947. struct hal_hw_txrx_ops {
  948. /* init and setup */
  949. void (*hal_srng_dst_hw_init)(struct hal_soc *hal,
  950. struct hal_srng *srng, bool idle_check,
  951. uint32_t idx);
  952. void (*hal_srng_src_hw_init)(struct hal_soc *hal,
  953. struct hal_srng *srng, bool idle_check,
  954. uint32_t idx);
  955. void (*hal_srng_hw_disable)(struct hal_soc *hal,
  956. struct hal_srng *srng);
  957. void (*hal_get_hw_hptp)(struct hal_soc *hal,
  958. hal_ring_handle_t hal_ring_hdl,
  959. uint32_t *headp, uint32_t *tailp,
  960. uint8_t ring_type);
  961. void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams,
  962. int qref_reset);
  963. void (*hal_setup_link_idle_list)(
  964. struct hal_soc *hal_soc,
  965. qdf_dma_addr_t scatter_bufs_base_paddr[],
  966. void *scatter_bufs_base_vaddr[],
  967. uint32_t num_scatter_bufs,
  968. uint32_t scatter_buf_size,
  969. uint32_t last_buf_end_offset,
  970. uint32_t num_entries);
  971. qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc,
  972. qdf_iomem_t addr);
  973. void (*hal_reo_set_err_dst_remap)(void *hal_soc);
  974. uint8_t (*hal_reo_enable_pn_in_dest)(void *hal_soc);
  975. void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid,
  976. uint32_t ba_window_size,
  977. uint32_t start_seq, void *hw_qdesc_vaddr,
  978. qdf_dma_addr_t hw_qdesc_paddr,
  979. int pn_type, uint8_t vdev_stats_id);
  980. uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg,
  981. uint8_t *ix0_map);
  982. /* tx */
  983. void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id);
  984. void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map,
  985. uint8_t id);
  986. void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid,
  987. uint8_t id,
  988. uint8_t dscp);
  989. void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id);
  990. void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr,
  991. uint8_t pool_id, uint32_t desc_id,
  992. uint8_t type);
  993. void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type);
  994. void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index);
  995. void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index);
  996. void (*hal_tx_comp_get_status)(void *desc, void *ts,
  997. struct hal_soc *hal);
  998. uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc);
  999. uint8_t (*hal_get_wbm_internal_error)(void *hal_desc);
  1000. void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en);
  1001. void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl,
  1002. hal_ring_handle_t hal_ring_hdl);
  1003. uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc);
  1004. uint32_t (*hal_tx_get_num_ppe_vp_tbl_entries)(
  1005. hal_soc_handle_t hal_soc_hdl);
  1006. void (*hal_reo_config_reo2ppe_dest_info)(hal_soc_handle_t hal_soc_hdl);
  1007. void (*hal_tx_set_ppe_cmn_cfg)(hal_soc_handle_t hal_soc_hdl,
  1008. union hal_tx_cmn_config_ppe *cmn_cfg);
  1009. void (*hal_tx_set_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl,
  1010. union hal_tx_ppe_vp_config *vp_cfg,
  1011. int ppe_vp_idx);
  1012. void (*hal_ppeds_cfg_ast_override_map_reg)(hal_soc_handle_t hal_soc_hdl,
  1013. uint8_t idx, union hal_tx_ppe_idx_map_config *ppeds_idx_map);
  1014. void (*hal_tx_set_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl,
  1015. uint32_t val,
  1016. uint8_t map_no);
  1017. void (*hal_tx_update_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl,
  1018. uint8_t pri,
  1019. uint8_t tid);
  1020. void (*hal_tx_dump_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl);
  1021. void (*hal_tx_enable_pri2tid_map)(hal_soc_handle_t hal_soc_hdl,
  1022. bool value, uint8_t ppe_vp_idx);
  1023. void (*hal_tx_config_rbm_mapping_be)(hal_soc_handle_t hal_soc_hdl,
  1024. hal_ring_handle_t hal_ring_hdl,
  1025. uint8_t rbm_id);
  1026. /* rx */
  1027. uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);
  1028. void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr,
  1029. struct mon_rx_status *rs);
  1030. uint8_t (*hal_rx_get_tlv)(void *rx_tlv);
  1031. void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr,
  1032. void *ppdu_info_handle);
  1033. void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level);
  1034. void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end,
  1035. uint8_t dbg_level);
  1036. uint32_t (*hal_get_link_desc_size)(void);
  1037. uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf);
  1038. uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf);
  1039. uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf);
  1040. void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr);
  1041. void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr);
  1042. void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b,
  1043. void *h);
  1044. uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr,
  1045. void *ppdu_info,
  1046. hal_soc_handle_t hal_soc_hdl,
  1047. qdf_nbuf_t nbuf);
  1048. void (*hal_rx_wbm_rel_buf_paddr_get)(hal_ring_desc_t rx_desc,
  1049. struct hal_buf_info *buf_info);
  1050. void (*hal_rx_wbm_err_info_get)(void *wbm_desc,
  1051. void *wbm_er_info);
  1052. void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart,
  1053. uint8_t dbg_level);
  1054. void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map);
  1055. void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp,
  1056. uint8_t id);
  1057. void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio);
  1058. /* rx */
  1059. uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf);
  1060. uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf);
  1061. uint8_t (*hal_rx_msdu_end_is_tkip_mic_err)(uint8_t *buf);
  1062. uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf);
  1063. uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf);
  1064. uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr);
  1065. uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf);
  1066. uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf);
  1067. void (*hal_rx_print_pn)(uint8_t *buf);
  1068. uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf);
  1069. uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf);
  1070. uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf);
  1071. bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf);
  1072. uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf);
  1073. uint32_t (*hal_rx_tlv_peer_meta_data_get)(uint8_t *buf);
  1074. uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf);
  1075. uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf);
  1076. uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf);
  1077. QDF_STATUS
  1078. (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr);
  1079. QDF_STATUS
  1080. (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr);
  1081. QDF_STATUS
  1082. (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr);
  1083. QDF_STATUS
  1084. (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr);
  1085. uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf);
  1086. bool (*hal_rx_is_unicast)(uint8_t *buf);
  1087. uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf);
  1088. uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr,
  1089. void *rxdma_dst_ring_desc);
  1090. uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf);
  1091. uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf);
  1092. void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr);
  1093. void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0);
  1094. void * (*hal_ent_mpdu_desc_info)(void *hw_addr);
  1095. void * (*hal_dst_mpdu_desc_info)(void *hw_addr);
  1096. uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf);
  1097. uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf);
  1098. uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf);
  1099. uint8_t (*hal_rx_get_filter_category)(uint8_t *buf);
  1100. uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf);
  1101. void (*hal_reo_config)(struct hal_soc *soc,
  1102. uint32_t reg_val,
  1103. struct hal_reo_params *reo_params);
  1104. uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf);
  1105. bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf);
  1106. bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf);
  1107. uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf);
  1108. bool (*hal_rx_msdu_cce_match_get)(uint8_t *buf);
  1109. uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf);
  1110. void
  1111. (*hal_rx_msdu_get_flow_params)(
  1112. uint8_t *buf,
  1113. bool *flow_invalid,
  1114. bool *flow_timeout,
  1115. uint32_t *flow_index);
  1116. uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf);
  1117. uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf);
  1118. void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle);
  1119. void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle);
  1120. void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf,
  1121. void *msdu_pkt_metadata);
  1122. uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf);
  1123. uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf);
  1124. bool (*hal_rx_get_udp_proto)(uint8_t *buf);
  1125. bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf);
  1126. uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf);
  1127. bool (*hal_rx_get_fisa_timeout)(uint8_t *buf);
  1128. uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr);
  1129. void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc,
  1130. hal_rx_mon_desc_info_t mon_desc_info);
  1131. uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc);
  1132. uint32_t (*hal_rx_msdu_end_offset_get)(void);
  1133. uint32_t (*hal_rx_attn_offset_get)(void);
  1134. uint32_t (*hal_rx_msdu_start_offset_get)(void);
  1135. uint32_t (*hal_rx_mpdu_start_offset_get)(void);
  1136. uint32_t (*hal_rx_mpdu_end_offset_get)(void);
  1137. uint32_t (*hal_rx_pkt_tlv_offset_get)(void);
  1138. uint32_t (*hal_rx_msdu_end_wmask_get)(void);
  1139. uint32_t (*hal_rx_mpdu_start_wmask_get)(void);
  1140. void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst,
  1141. uint32_t table_offset,
  1142. uint8_t *rx_flow);
  1143. void * (*hal_rx_flow_get_tuple_info)(uint8_t *rx_fst,
  1144. uint32_t hal_hash,
  1145. uint8_t *tuple_info);
  1146. QDF_STATUS (*hal_rx_flow_delete_entry)(uint8_t *fst,
  1147. void *fse);
  1148. uint32_t (*hal_rx_fst_get_fse_size)(void);
  1149. void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring,
  1150. uint32_t num_rings,
  1151. uint32_t *remap1,
  1152. uint32_t *remap2);
  1153. void (*hal_compute_reo_remap_ix0)(uint32_t *remap0);
  1154. uint32_t (*hal_rx_flow_setup_cmem_fse)(
  1155. struct hal_soc *soc, uint32_t cmem_ba,
  1156. uint32_t table_offset, uint8_t *rx_flow);
  1157. uint32_t (*hal_rx_flow_get_cmem_fse_ts)(struct hal_soc *soc,
  1158. uint32_t fse_offset);
  1159. void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc,
  1160. uint32_t fse_offset,
  1161. uint32_t *fse, qdf_size_t len);
  1162. void (*hal_cmem_write)(hal_soc_handle_t hal_soc_hdl, uint32_t offset,
  1163. uint32_t value);
  1164. void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf,
  1165. uint32_t *reo_destination_indication);
  1166. uint8_t (*hal_tx_get_num_tcl_banks)(void);
  1167. uint32_t (*hal_get_reo_qdesc_size)(uint32_t ba_window_size, int tid);
  1168. uint16_t (*hal_get_rx_max_ba_window)(int tid);
  1169. void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie,
  1170. qdf_dma_addr_t link_desc_paddr,
  1171. uint8_t bm_id);
  1172. void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl,
  1173. hal_ring_handle_t hal_ring_hdl);
  1174. void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr);
  1175. void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl,
  1176. uint8_t ac, uint32_t *value);
  1177. void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl,
  1178. uint8_t ac, uint32_t value);
  1179. uint32_t (*hal_get_reo_reg_base_offset)(void);
  1180. void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size,
  1181. uint16_t *rx_mon_pkt_tlv_size);
  1182. uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf);
  1183. uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr);
  1184. void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl,
  1185. uint8_t *buf, uint8_t dbg_level);
  1186. int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv,
  1187. struct hal_offload_info *offload_info);
  1188. uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf);
  1189. uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf);
  1190. uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf);
  1191. uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf);
  1192. int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params);
  1193. int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset,
  1194. uint32_t *l4_hdr_offset);
  1195. uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf);
  1196. uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf);
  1197. void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num);
  1198. void (*hal_rx_reo_prev_pn_get)(void *ring_desc, uint64_t *prev_pn);
  1199. uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf);
  1200. uint32_t (*hal_rx_msdu_reo_dst_ind_get)(hal_soc_handle_t hal_soc_hdl,
  1201. void *msdu_link_desc);
  1202. void (*hal_msdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl,
  1203. void *msdu_desc_info, uint32_t dst_ind,
  1204. uint32_t nbuf_len);
  1205. void (*hal_mpdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl,
  1206. void *ent_desc,
  1207. void *mpdu_desc_info,
  1208. uint32_t seq_no);
  1209. #ifdef DP_UMAC_HW_RESET_SUPPORT
  1210. void (*hal_unregister_reo_send_cmd)(struct hal_soc *hal_soc);
  1211. void (*hal_register_reo_send_cmd)(struct hal_soc *hal_soc);
  1212. void (*hal_reset_rx_reo_tid_q)(struct hal_soc *hal_soc,
  1213. void *hw_qdesc_vaddr, uint32_t size);
  1214. #endif
  1215. uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf);
  1216. uint32_t (*hal_rx_tlv_get_freq)(uint8_t *buf);
  1217. uint8_t (*hal_rx_msdu_get_keyid)(uint8_t *buf);
  1218. uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf);
  1219. uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf);
  1220. uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf);
  1221. uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf);
  1222. uint32_t (*hal_rx_tlv_get_is_decrypted)(uint8_t *buf);
  1223. uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc);
  1224. uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc);
  1225. void (*hal_rx_msdu_link_desc_set)(hal_soc_handle_t hal_soc_hdl,
  1226. void *src_srng_desc,
  1227. hal_buff_addrinfo_t buf_addr_info,
  1228. uint8_t bm_action);
  1229. void (*hal_rx_buf_cookie_rbm_get)(uint32_t *buf_addr_info_hdl,
  1230. hal_buf_info_t buf_info_hdl);
  1231. void (*hal_rx_reo_buf_paddr_get)(hal_ring_desc_t rx_desc,
  1232. struct hal_buf_info *buf_info);
  1233. void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry,
  1234. qdf_dma_addr_t paddr,
  1235. uint32_t cookie, uint8_t manager);
  1236. uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl);
  1237. uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc);
  1238. void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr,
  1239. uint32_t *ip_csum_err,
  1240. uint32_t *tcp_udp_csum_err);
  1241. void (*hal_rx_mpdu_desc_info_get)(void *desc_addr,
  1242. void *mpdu_desc_info_hdl);
  1243. uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc);
  1244. uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc);
  1245. bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf);
  1246. uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr);
  1247. uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr);
  1248. void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr,
  1249. struct hal_rx_pkt_capture_flags *flags);
  1250. uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr);
  1251. uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr);
  1252. void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf,
  1253. uint8_t *priv_data,
  1254. uint32_t len);
  1255. void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf,
  1256. uint8_t *priv_data,
  1257. uint32_t len);
  1258. void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len);
  1259. void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf,
  1260. void *mpdu_desc_info_hdl);
  1261. uint8_t *(*hal_get_reo_ent_desc_qdesc_addr)(uint8_t *desc);
  1262. uint64_t (*hal_rx_get_qdesc_addr)(uint8_t *dst_ring_desc,
  1263. uint8_t *buf);
  1264. uint8_t (*hal_rx_get_phy_ppdu_id_size)(void);
  1265. void (*hal_set_reo_ent_desc_reo_dest_ind)(uint8_t *desc,
  1266. uint32_t dst_ind);
  1267. QDF_STATUS
  1268. (*hal_rx_reo_ent_get_src_link_id)(hal_rxdma_desc_t rx_desc,
  1269. uint8_t *src_link_id);
  1270. /* REO CMD and STATUS */
  1271. int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl,
  1272. hal_ring_handle_t hal_ring_hdl,
  1273. enum hal_reo_cmd_type cmd,
  1274. void *params);
  1275. QDF_STATUS (*hal_reo_status_update)(hal_soc_handle_t hal_soc_hdl,
  1276. hal_ring_desc_t reo_desc,
  1277. void *st_handle,
  1278. uint32_t tlv, int *num_ref);
  1279. uint8_t (*hal_get_tlv_hdr_size)(void);
  1280. uint8_t (*hal_get_idle_link_bm_id)(uint8_t chip_id);
  1281. bool (*hal_txmon_is_mon_buf_addr_tlv)(void *tx_tlv_hdr);
  1282. void (*hal_txmon_populate_packet_info)(void *tx_tlv_hdr,
  1283. void *pkt_info);
  1284. /* TX MONITOR */
  1285. #ifdef WLAN_PKT_CAPTURE_TX_2_0
  1286. uint32_t (*hal_txmon_status_parse_tlv)(void *data_ppdu_info,
  1287. void *prot_ppdu_info,
  1288. void *data_status_info,
  1289. void *prot_status_info,
  1290. void *tx_tlv_hdr,
  1291. qdf_frag_t status_frag);
  1292. uint32_t (*hal_txmon_status_get_num_users)(void *tx_tlv_hdr,
  1293. uint8_t *num_users);
  1294. void (*hal_txmon_get_word_mask)(void *wmask);
  1295. #endif /* WLAN_PKT_CAPTURE_TX_2_0 */
  1296. QDF_STATUS (*hal_reo_shared_qaddr_setup)(hal_soc_handle_t hal_soc_hdl,
  1297. struct reo_queue_ref_table
  1298. *reo_qref);
  1299. void (*hal_reo_shared_qaddr_init)(hal_soc_handle_t hal_soc_hdl,
  1300. int qref_reset);
  1301. void (*hal_reo_shared_qaddr_detach)(hal_soc_handle_t hal_soc_hdl);
  1302. void (*hal_reo_shared_qaddr_write)(hal_soc_handle_t hal_soc_hdl,
  1303. uint16_t peer_id,
  1304. int tid,
  1305. qdf_dma_addr_t hw_qdesc_paddr);
  1306. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  1307. uint8_t (*hal_get_first_wow_wakeup_packet)(uint8_t *buf);
  1308. #endif
  1309. void (*hal_reo_shared_qaddr_cache_clear)(hal_soc_handle_t hal_soc_hdl);
  1310. uint32_t (*hal_rx_tlv_l3_type_get)(uint8_t *buf);
  1311. void (*hal_tx_vdev_mismatch_routing_set)(hal_soc_handle_t hal_soc_hdl,
  1312. enum hal_tx_vdev_mismatch_notify config);
  1313. void (*hal_tx_mcast_mlo_reinject_routing_set)(
  1314. hal_soc_handle_t hal_soc_hdl,
  1315. enum hal_tx_mcast_mlo_reinject_notify config);
  1316. void (*hal_cookie_conversion_reg_cfg_be)(hal_soc_handle_t hal_soc_hdl,
  1317. struct hal_hw_cc_config
  1318. *cc_cfg);
  1319. void (*hal_tx_populate_bank_register)(hal_soc_handle_t hal_soc_hdl,
  1320. union hal_tx_bank_config *config,
  1321. uint8_t bank_id);
  1322. void (*hal_tx_vdev_mcast_ctrl_set)(hal_soc_handle_t hal_soc_hdl,
  1323. uint8_t vdev_id,
  1324. uint8_t mcast_ctrl_val);
  1325. void (*hal_get_tsf_time)(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
  1326. uint32_t mac_id, uint64_t *tsf,
  1327. uint64_t *tsf_sync_soc_time);
  1328. void (*hal_get_tsf2_scratch_reg)(hal_soc_handle_t hal_soc_hdl,
  1329. uint8_t mac_id, uint64_t *value);
  1330. void (*hal_get_tqm_scratch_reg)(hal_soc_handle_t hal_soc_hdl,
  1331. uint64_t *value);
  1332. #ifdef FEATURE_DIRECT_LINK
  1333. QDF_STATUS (*hal_srng_set_msi_config)(hal_ring_handle_t ring_hdl,
  1334. void *ring_params);
  1335. #endif
  1336. void (*hal_tx_ring_halt_set)(hal_soc_handle_t hal_soc_hdl);
  1337. void (*hal_tx_ring_halt_reset)(hal_soc_handle_t hal_soc_hdl);
  1338. bool (*hal_tx_ring_halt_poll)(hal_soc_handle_t hal_soc_hdl);
  1339. uint32_t (*hal_tx_get_num_ppe_vp_search_idx_tbl_entries)(
  1340. hal_soc_handle_t hal_soc_hdl);
  1341. uint32_t (*hal_tx_ring_halt_get)(hal_soc_handle_t hal_soc_hdl);
  1342. bool (*hal_rx_en_mcast_fp_data_filter)(void);
  1343. };
  1344. /**
  1345. * struct hal_soc_stats - Hal layer stats
  1346. * @reg_write_fail: number of failed register writes
  1347. * @wstats: delayed register write stats
  1348. * @shadow_reg_write_fail: shadow reg write failure stats
  1349. * @shadow_reg_write_succ: shadow reg write success stats
  1350. *
  1351. * This structure holds all the statistics at HAL layer.
  1352. */
  1353. struct hal_soc_stats {
  1354. uint32_t reg_write_fail;
  1355. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  1356. struct hal_reg_write_soc_stats wstats;
  1357. #endif
  1358. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  1359. uint32_t shadow_reg_write_fail;
  1360. uint32_t shadow_reg_write_succ;
  1361. #endif
  1362. };
  1363. #ifdef ENABLE_HAL_REG_WR_HISTORY
  1364. /* The history size should always be a power of 2 */
  1365. #define HAL_REG_WRITE_HIST_SIZE 8
  1366. /**
  1367. * struct hal_reg_write_fail_entry - Record of
  1368. * register write which failed.
  1369. * @timestamp: timestamp of reg write failure
  1370. * @reg_offset: offset of register where the write failed
  1371. * @write_val: the value which was to be written
  1372. * @read_val: the value read back from the register after write
  1373. */
  1374. struct hal_reg_write_fail_entry {
  1375. uint64_t timestamp;
  1376. uint32_t reg_offset;
  1377. uint32_t write_val;
  1378. uint32_t read_val;
  1379. };
  1380. /**
  1381. * struct hal_reg_write_fail_history - Hal layer history
  1382. * of all the register write failures.
  1383. * @index: index to add the new record
  1384. * @record: array of all the records in history
  1385. *
  1386. * This structure holds the history of register write
  1387. * failures at HAL layer.
  1388. */
  1389. struct hal_reg_write_fail_history {
  1390. qdf_atomic_t index;
  1391. struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE];
  1392. };
  1393. #endif
  1394. /**
  1395. * union hal_shadow_reg_cfg - Shadow register config
  1396. * @addr: Place holder where shadow address is saved
  1397. * @v2: shadow config v2 format
  1398. * @v3: shadow config v3 format
  1399. */
  1400. union hal_shadow_reg_cfg {
  1401. uint32_t addr;
  1402. struct pld_shadow_reg_v2_cfg v2;
  1403. #ifdef CONFIG_SHADOW_V3
  1404. struct pld_shadow_reg_v3_cfg v3;
  1405. #endif
  1406. };
  1407. #ifdef HAL_RECORD_SUSPEND_WRITE
  1408. #define HAL_SUSPEND_WRITE_HISTORY_MAX 256
  1409. struct hal_suspend_write_record {
  1410. uint64_t ts;
  1411. uint8_t ring_id;
  1412. uit32_t value;
  1413. uint32_t direct_wcount;
  1414. };
  1415. struct hal_suspend_write_history {
  1416. qdf_atomic_t index;
  1417. struct hal_suspend_write_record record[HAL_SUSPEND_WRITE_HISTORY_MAX];
  1418. };
  1419. #endif
  1420. /**
  1421. * struct hal_soc - HAL context to be used to access SRNG APIs
  1422. * (currently used by data path and
  1423. * transport (CE) modules)
  1424. * @hif_handle: HIF handle to access HW registers
  1425. * @qdf_dev: QDF device handle
  1426. * @dev_base_addr: Device base address
  1427. * @dev_base_addr_ce: Device base address for ce - qca5018 target
  1428. * @dev_base_addr_cmem: Device base address for CMEM
  1429. * @dev_base_addr_pmm: Device base address for PMM
  1430. * @srng_list: HAL internal state for all SRNG rings
  1431. * @shadow_rdptr_mem_vaddr: Remote pointer memory for HW/FW updates (virtual)
  1432. * @shadow_rdptr_mem_paddr: Remote pointer memory for HW/FW updates (physical)
  1433. * @shadow_wrptr_mem_vaddr: Shared memory for ring pointer updates from host
  1434. * to FW (virtual)
  1435. * @shadow_wrptr_mem_paddr: Shared memory for ring pointer updates from host
  1436. * to FW (physical)
  1437. * @reo_res_bitmap: REO blocking resource index
  1438. * @index:
  1439. * @target_type:
  1440. * @version:
  1441. * @shadow_config: shadow register configuration
  1442. * @num_shadow_registers_configured:
  1443. * @use_register_windowing:
  1444. * @register_window:
  1445. * @register_access_lock:
  1446. * @static_window_map: Static window map configuration for multiple window write
  1447. * @hw_srng_table: srng table
  1448. * @hal_hw_reg_offset:
  1449. * @ops: TXRX operations
  1450. * @init_phase: Indicate srngs initialization
  1451. * @stats: Hal level stats
  1452. * @reg_wr_fail_hist: write failure history
  1453. * @reg_write_queue: queue(array) to hold register writes
  1454. * @reg_write_work: delayed work to be queued into workqueue
  1455. * @reg_write_wq: workqueue for delayed register writes
  1456. * @write_idx: write index used by caller to enqueue delayed work
  1457. * @read_idx: read index used by worker thread to dequeue/write registers
  1458. * @active_work_cnt:
  1459. * @list_shadow_reg_config: array of generic regs mapped to
  1460. * shadow regs
  1461. * @num_generic_shadow_regs_configured: number of generic regs
  1462. * mapped to shadow regs
  1463. * @dmac_cmn_src_rxbuf_ring: flag to indicate cmn dmac rings in beryllium
  1464. * @reo_qref: Reo queue ref table items
  1465. */
  1466. struct hal_soc {
  1467. struct hif_opaque_softc *hif_handle;
  1468. qdf_device_t qdf_dev;
  1469. void *dev_base_addr;
  1470. void *dev_base_addr_ce;
  1471. void *dev_base_addr_cmem;
  1472. void *dev_base_addr_pmm;
  1473. struct hal_srng srng_list[HAL_SRNG_ID_MAX];
  1474. uint32_t *shadow_rdptr_mem_vaddr;
  1475. qdf_dma_addr_t shadow_rdptr_mem_paddr;
  1476. uint32_t *shadow_wrptr_mem_vaddr;
  1477. qdf_dma_addr_t shadow_wrptr_mem_paddr;
  1478. uint8_t reo_res_bitmap;
  1479. uint8_t index;
  1480. uint32_t target_type;
  1481. uint32_t version;
  1482. union hal_shadow_reg_cfg shadow_config[MAX_SHADOW_REGISTERS];
  1483. int num_shadow_registers_configured;
  1484. bool use_register_windowing;
  1485. uint32_t register_window;
  1486. qdf_spinlock_t register_access_lock;
  1487. bool static_window_map;
  1488. struct hal_hw_srng_config *hw_srng_table;
  1489. int32_t hal_hw_reg_offset[SRNG_REGISTER_MAX];
  1490. struct hal_hw_txrx_ops *ops;
  1491. bool init_phase;
  1492. struct hal_soc_stats stats;
  1493. #ifdef ENABLE_HAL_REG_WR_HISTORY
  1494. struct hal_reg_write_fail_history *reg_wr_fail_hist;
  1495. #endif
  1496. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  1497. struct hal_reg_write_q_elem *reg_write_queue;
  1498. qdf_work_t reg_write_work;
  1499. qdf_workqueue_t *reg_write_wq;
  1500. qdf_atomic_t write_idx;
  1501. uint32_t read_idx;
  1502. #endif /*FEATURE_HAL_DELAYED_REG_WRITE */
  1503. qdf_atomic_t active_work_cnt;
  1504. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  1505. struct shadow_reg_config
  1506. list_shadow_reg_config[MAX_GENERIC_SHADOW_REG];
  1507. int num_generic_shadow_regs_configured;
  1508. #endif
  1509. bool dmac_cmn_src_rxbuf_ring;
  1510. struct reo_queue_ref_table reo_qref;
  1511. };
  1512. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  1513. /**
  1514. * hal_delayed_reg_write() - delayed register write
  1515. * @hal_soc: HAL soc handle
  1516. * @srng: hal srng
  1517. * @addr: iomem address
  1518. * @value: value to be written
  1519. *
  1520. * Return: none
  1521. */
  1522. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  1523. struct hal_srng *srng,
  1524. void __iomem *addr,
  1525. uint32_t value);
  1526. #endif
  1527. void hal_qca6750_attach(struct hal_soc *hal_soc);
  1528. void hal_qca6490_attach(struct hal_soc *hal_soc);
  1529. void hal_qca6390_attach(struct hal_soc *hal_soc);
  1530. void hal_qca6290_attach(struct hal_soc *hal_soc);
  1531. void hal_qca8074_attach(struct hal_soc *hal_soc);
  1532. /**
  1533. * hal_kiwi_attach() - Attach kiwi target specific hal_soc ops,
  1534. * offset and srng table
  1535. * @hal_soc: HAL soc
  1536. */
  1537. void hal_kiwi_attach(struct hal_soc *hal_soc);
  1538. void hal_qcn9224v2_attach(struct hal_soc *hal_soc);
  1539. void hal_wcn6450_attach(struct hal_soc *hal_soc);
  1540. /**
  1541. * hal_soc_to_hal_soc_handle() - API to convert hal_soc to opaque
  1542. * hal_soc_handle_t type
  1543. * @hal_soc: hal_soc type
  1544. *
  1545. * Return: hal_soc_handle_t type
  1546. */
  1547. static inline
  1548. hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc)
  1549. {
  1550. return (hal_soc_handle_t)hal_soc;
  1551. }
  1552. /**
  1553. * hal_srng_to_hal_ring_handle() - API to convert hal_srng to opaque
  1554. * hal_ring handle_t type
  1555. * @hal_srng: hal_srng type
  1556. *
  1557. * Return: hal_ring_handle_t type
  1558. */
  1559. static inline
  1560. hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng)
  1561. {
  1562. return (hal_ring_handle_t)hal_srng;
  1563. }
  1564. /**
  1565. * hal_ring_handle_to_hal_srng() - API to convert hal_ring_handle_t to hal_srng
  1566. * @hal_ring: hal_ring_handle_t type
  1567. *
  1568. * Return: hal_srng pointer type
  1569. */
  1570. static inline
  1571. struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring)
  1572. {
  1573. return (struct hal_srng *)hal_ring;
  1574. }
  1575. /* Size of REO queue reference table in Host
  1576. * 2k peers * 17 tids * 8bytes(rx_reo_queue_reference)
  1577. * = 278528 bytes
  1578. */
  1579. #define REO_QUEUE_REF_NON_ML_TABLE_SIZE 278528
  1580. /* Calculated based on 512 MLO peers */
  1581. #define REO_QUEUE_REF_ML_TABLE_SIZE 69632
  1582. #define HAL_ML_PEER_ID_START 0x2000
  1583. #define HAL_PEER_ID_IS_MLO(peer_id) ((peer_id) & HAL_ML_PEER_ID_START)
  1584. /*
  1585. * REO2PPE destination indication
  1586. */
  1587. #define REO2PPE_DST_IND 6
  1588. #define REO2PPE_DST_RING 11
  1589. #define REO2PPE_RULE_FAIL_FB 0x2000
  1590. /**
  1591. * enum hal_pkt_type - Type of packet type reported by HW
  1592. * @HAL_DOT11A: 802.11a PPDU type
  1593. * @HAL_DOT11B: 802.11b PPDU type
  1594. * @HAL_DOT11N_MM: 802.11n Mixed Mode PPDU type
  1595. * @HAL_DOT11AC: 802.11ac PPDU type
  1596. * @HAL_DOT11AX: 802.11ax PPDU type
  1597. * @HAL_DOT11BA: 802.11ba (WUR) PPDU type
  1598. * @HAL_DOT11BE: 802.11be PPDU type
  1599. * @HAL_DOT11AZ: 802.11az (ranging) PPDU type
  1600. * @HAL_DOT11N_GF: 802.11n Green Field PPDU type
  1601. * @HAL_DOT11_MAX: Maximum enumeration
  1602. *
  1603. * Enum indicating the packet type reported by HW in rx_pkt_tlvs (RX data)
  1604. * or WBM2SW ring entry's descriptor (TX data completion)
  1605. */
  1606. enum hal_pkt_type {
  1607. HAL_DOT11A = 0,
  1608. HAL_DOT11B = 1,
  1609. HAL_DOT11N_MM = 2,
  1610. HAL_DOT11AC = 3,
  1611. HAL_DOT11AX = 4,
  1612. HAL_DOT11BA = 5,
  1613. HAL_DOT11BE = 6,
  1614. HAL_DOT11AZ = 7,
  1615. HAL_DOT11N_GF = 8,
  1616. HAL_DOT11_MAX,
  1617. };
  1618. #endif /* _HAL_INTERNAL_H_ */