dp_tx.c 110 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "enet.h"
  34. #include "dp_internal.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. /* TODO Add support in TSO */
  42. #define DP_DESC_NUM_FRAG(x) 0
  43. /* disable TQM_BYPASS */
  44. #define TQM_BYPASS_WAR 0
  45. /* invalid peer id for reinject*/
  46. #define DP_INVALID_PEER 0XFFFE
  47. /*mapping between hal encrypt type and cdp_sec_type*/
  48. #define MAX_CDP_SEC_TYPE 12
  49. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  50. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  51. HAL_TX_ENCRYPT_TYPE_WEP_128,
  52. HAL_TX_ENCRYPT_TYPE_WEP_104,
  53. HAL_TX_ENCRYPT_TYPE_WEP_40,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  56. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_WAPI,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  62. #ifdef QCA_TX_LIMIT_CHECK
  63. /**
  64. * dp_tx_limit_check - Check if allocated tx descriptors reached
  65. * soc max limit and pdev max limit
  66. * @vdev: DP vdev handle
  67. *
  68. * Return: true if allocated tx descriptors reached max configured value, else
  69. * false
  70. */
  71. static inline bool
  72. dp_tx_limit_check(struct dp_vdev *vdev)
  73. {
  74. struct dp_pdev *pdev = vdev->pdev;
  75. struct dp_soc *soc = pdev->soc;
  76. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  77. soc->num_tx_allowed) {
  78. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  79. "%s: queued packets are more than max tx, drop the frame",
  80. __func__);
  81. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  82. return true;
  83. }
  84. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  85. pdev->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. return false;
  93. }
  94. /**
  95. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  96. * @vdev: DP pdev handle
  97. *
  98. * Return: void
  99. */
  100. static inline void
  101. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  102. {
  103. struct dp_soc *soc = pdev->soc;
  104. qdf_atomic_inc(&pdev->num_tx_outstanding);
  105. qdf_atomic_inc(&soc->num_tx_outstanding);
  106. }
  107. /**
  108. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  109. * @vdev: DP pdev handle
  110. *
  111. * Return: void
  112. */
  113. static inline void
  114. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  115. {
  116. struct dp_soc *soc = pdev->soc;
  117. qdf_atomic_dec(&pdev->num_tx_outstanding);
  118. qdf_atomic_dec(&soc->num_tx_outstanding);
  119. }
  120. #else //QCA_TX_LIMIT_CHECK
  121. static inline bool
  122. dp_tx_limit_check(struct dp_vdev *vdev)
  123. {
  124. return false;
  125. }
  126. static inline void
  127. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  128. {
  129. }
  130. static inline void
  131. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  132. {
  133. }
  134. #endif //QCA_TX_LIMIT_CHECK
  135. #if defined(FEATURE_TSO)
  136. /**
  137. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  138. *
  139. * @soc - core txrx main context
  140. * @seg_desc - tso segment descriptor
  141. * @num_seg_desc - tso number segment descriptor
  142. */
  143. static void dp_tx_tso_unmap_segment(
  144. struct dp_soc *soc,
  145. struct qdf_tso_seg_elem_t *seg_desc,
  146. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  147. {
  148. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  149. if (qdf_unlikely(!seg_desc)) {
  150. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  151. __func__, __LINE__);
  152. qdf_assert(0);
  153. } else if (qdf_unlikely(!num_seg_desc)) {
  154. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  155. __func__, __LINE__);
  156. qdf_assert(0);
  157. } else {
  158. bool is_last_seg;
  159. /* no tso segment left to do dma unmap */
  160. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  161. return;
  162. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  163. true : false;
  164. qdf_nbuf_unmap_tso_segment(soc->osdev,
  165. seg_desc, is_last_seg);
  166. num_seg_desc->num_seg.tso_cmn_num_seg--;
  167. }
  168. }
  169. /**
  170. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  171. * back to the freelist
  172. *
  173. * @soc - soc device handle
  174. * @tx_desc - Tx software descriptor
  175. */
  176. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  177. struct dp_tx_desc_s *tx_desc)
  178. {
  179. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  180. if (qdf_unlikely(!tx_desc->tso_desc)) {
  181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  182. "%s %d TSO desc is NULL!",
  183. __func__, __LINE__);
  184. qdf_assert(0);
  185. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  186. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  187. "%s %d TSO num desc is NULL!",
  188. __func__, __LINE__);
  189. qdf_assert(0);
  190. } else {
  191. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  192. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  193. /* Add the tso num segment into the free list */
  194. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  195. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  196. tx_desc->tso_num_desc);
  197. tx_desc->tso_num_desc = NULL;
  198. }
  199. /* Add the tso segment into the free list*/
  200. dp_tx_tso_desc_free(soc,
  201. tx_desc->pool_id, tx_desc->tso_desc);
  202. tx_desc->tso_desc = NULL;
  203. }
  204. }
  205. #else
  206. static void dp_tx_tso_unmap_segment(
  207. struct dp_soc *soc,
  208. struct qdf_tso_seg_elem_t *seg_desc,
  209. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  210. {
  211. }
  212. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  213. struct dp_tx_desc_s *tx_desc)
  214. {
  215. }
  216. #endif
  217. /**
  218. * dp_tx_desc_release() - Release Tx Descriptor
  219. * @tx_desc : Tx Descriptor
  220. * @desc_pool_id: Descriptor Pool ID
  221. *
  222. * Deallocate all resources attached to Tx descriptor and free the Tx
  223. * descriptor.
  224. *
  225. * Return:
  226. */
  227. static void
  228. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  229. {
  230. struct dp_pdev *pdev = tx_desc->pdev;
  231. struct dp_soc *soc;
  232. uint8_t comp_status = 0;
  233. qdf_assert(pdev);
  234. soc = pdev->soc;
  235. if (tx_desc->frm_type == dp_tx_frm_tso)
  236. dp_tx_tso_desc_release(soc, tx_desc);
  237. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  238. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  239. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  240. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  241. dp_tx_outstanding_dec(pdev);
  242. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  243. qdf_atomic_dec(&pdev->num_tx_exception);
  244. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  245. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  246. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  247. soc->hal_soc);
  248. else
  249. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  250. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  251. "Tx Completion Release desc %d status %d outstanding %d",
  252. tx_desc->id, comp_status,
  253. qdf_atomic_read(&pdev->num_tx_outstanding));
  254. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  255. return;
  256. }
  257. /**
  258. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  259. * @vdev: DP vdev Handle
  260. * @nbuf: skb
  261. * @msdu_info: msdu_info required to create HTT metadata
  262. *
  263. * Prepares and fills HTT metadata in the frame pre-header for special frames
  264. * that should be transmitted using varying transmit parameters.
  265. * There are 2 VDEV modes that currently needs this special metadata -
  266. * 1) Mesh Mode
  267. * 2) DSRC Mode
  268. *
  269. * Return: HTT metadata size
  270. *
  271. */
  272. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  273. struct dp_tx_msdu_info_s *msdu_info)
  274. {
  275. uint32_t *meta_data = msdu_info->meta_data;
  276. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  277. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  278. uint8_t htt_desc_size;
  279. /* Size rounded of multiple of 8 bytes */
  280. uint8_t htt_desc_size_aligned;
  281. uint8_t *hdr = NULL;
  282. /*
  283. * Metadata - HTT MSDU Extension header
  284. */
  285. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  286. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  287. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer) {
  288. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  289. htt_desc_size_aligned)) {
  290. DP_STATS_INC(vdev,
  291. tx_i.dropped.headroom_insufficient, 1);
  292. return 0;
  293. }
  294. /* Fill and add HTT metaheader */
  295. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  296. if (!hdr) {
  297. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  298. "Error in filling HTT metadata");
  299. return 0;
  300. }
  301. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  302. } else if (vdev->opmode == wlan_op_mode_ocb) {
  303. /* Todo - Add support for DSRC */
  304. }
  305. return htt_desc_size_aligned;
  306. }
  307. /**
  308. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  309. * @tso_seg: TSO segment to process
  310. * @ext_desc: Pointer to MSDU extension descriptor
  311. *
  312. * Return: void
  313. */
  314. #if defined(FEATURE_TSO)
  315. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  316. void *ext_desc)
  317. {
  318. uint8_t num_frag;
  319. uint32_t tso_flags;
  320. /*
  321. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  322. * tcp_flag_mask
  323. *
  324. * Checksum enable flags are set in TCL descriptor and not in Extension
  325. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  326. */
  327. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  328. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  329. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  330. tso_seg->tso_flags.ip_len);
  331. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  332. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  333. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  334. uint32_t lo = 0;
  335. uint32_t hi = 0;
  336. qdf_dmaaddr_to_32s(
  337. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  338. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  339. tso_seg->tso_frags[num_frag].length);
  340. }
  341. return;
  342. }
  343. #else
  344. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  345. void *ext_desc)
  346. {
  347. return;
  348. }
  349. #endif
  350. #if defined(FEATURE_TSO)
  351. /**
  352. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  353. * allocated and free them
  354. *
  355. * @soc: soc handle
  356. * @free_seg: list of tso segments
  357. * @msdu_info: msdu descriptor
  358. *
  359. * Return - void
  360. */
  361. static void dp_tx_free_tso_seg_list(
  362. struct dp_soc *soc,
  363. struct qdf_tso_seg_elem_t *free_seg,
  364. struct dp_tx_msdu_info_s *msdu_info)
  365. {
  366. struct qdf_tso_seg_elem_t *next_seg;
  367. while (free_seg) {
  368. next_seg = free_seg->next;
  369. dp_tx_tso_desc_free(soc,
  370. msdu_info->tx_queue.desc_pool_id,
  371. free_seg);
  372. free_seg = next_seg;
  373. }
  374. }
  375. /**
  376. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  377. * allocated and free them
  378. *
  379. * @soc: soc handle
  380. * @free_num_seg: list of tso number segments
  381. * @msdu_info: msdu descriptor
  382. * Return - void
  383. */
  384. static void dp_tx_free_tso_num_seg_list(
  385. struct dp_soc *soc,
  386. struct qdf_tso_num_seg_elem_t *free_num_seg,
  387. struct dp_tx_msdu_info_s *msdu_info)
  388. {
  389. struct qdf_tso_num_seg_elem_t *next_num_seg;
  390. while (free_num_seg) {
  391. next_num_seg = free_num_seg->next;
  392. dp_tso_num_seg_free(soc,
  393. msdu_info->tx_queue.desc_pool_id,
  394. free_num_seg);
  395. free_num_seg = next_num_seg;
  396. }
  397. }
  398. /**
  399. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  400. * do dma unmap for each segment
  401. *
  402. * @soc: soc handle
  403. * @free_seg: list of tso segments
  404. * @num_seg_desc: tso number segment descriptor
  405. *
  406. * Return - void
  407. */
  408. static void dp_tx_unmap_tso_seg_list(
  409. struct dp_soc *soc,
  410. struct qdf_tso_seg_elem_t *free_seg,
  411. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  412. {
  413. struct qdf_tso_seg_elem_t *next_seg;
  414. if (qdf_unlikely(!num_seg_desc)) {
  415. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  416. return;
  417. }
  418. while (free_seg) {
  419. next_seg = free_seg->next;
  420. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  421. free_seg = next_seg;
  422. }
  423. }
  424. /**
  425. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  426. * free the tso segments descriptor and
  427. * tso num segments descriptor
  428. *
  429. * @soc: soc handle
  430. * @msdu_info: msdu descriptor
  431. * @tso_seg_unmap: flag to show if dma unmap is necessary
  432. *
  433. * Return - void
  434. */
  435. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  436. struct dp_tx_msdu_info_s *msdu_info,
  437. bool tso_seg_unmap)
  438. {
  439. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  440. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  441. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  442. tso_info->tso_num_seg_list;
  443. /* do dma unmap for each segment */
  444. if (tso_seg_unmap)
  445. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  446. /* free all tso number segment descriptor though looks only have 1 */
  447. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  448. /* free all tso segment descriptor */
  449. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  450. }
  451. /**
  452. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  453. * @vdev: virtual device handle
  454. * @msdu: network buffer
  455. * @msdu_info: meta data associated with the msdu
  456. *
  457. * Return: QDF_STATUS_SUCCESS success
  458. */
  459. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  460. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  461. {
  462. struct qdf_tso_seg_elem_t *tso_seg;
  463. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  464. struct dp_soc *soc = vdev->pdev->soc;
  465. struct qdf_tso_info_t *tso_info;
  466. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  467. tso_info = &msdu_info->u.tso_info;
  468. tso_info->curr_seg = NULL;
  469. tso_info->tso_seg_list = NULL;
  470. tso_info->num_segs = num_seg;
  471. msdu_info->frm_type = dp_tx_frm_tso;
  472. tso_info->tso_num_seg_list = NULL;
  473. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  474. while (num_seg) {
  475. tso_seg = dp_tx_tso_desc_alloc(
  476. soc, msdu_info->tx_queue.desc_pool_id);
  477. if (tso_seg) {
  478. tso_seg->next = tso_info->tso_seg_list;
  479. tso_info->tso_seg_list = tso_seg;
  480. num_seg--;
  481. } else {
  482. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  483. __func__);
  484. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  485. return QDF_STATUS_E_NOMEM;
  486. }
  487. }
  488. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  489. tso_num_seg = dp_tso_num_seg_alloc(soc,
  490. msdu_info->tx_queue.desc_pool_id);
  491. if (tso_num_seg) {
  492. tso_num_seg->next = tso_info->tso_num_seg_list;
  493. tso_info->tso_num_seg_list = tso_num_seg;
  494. } else {
  495. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  496. __func__);
  497. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  498. return QDF_STATUS_E_NOMEM;
  499. }
  500. msdu_info->num_seg =
  501. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  502. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  503. msdu_info->num_seg);
  504. if (!(msdu_info->num_seg)) {
  505. /*
  506. * Free allocated TSO seg desc and number seg desc,
  507. * do unmap for segments if dma map has done.
  508. */
  509. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  510. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  511. return QDF_STATUS_E_INVAL;
  512. }
  513. tso_info->curr_seg = tso_info->tso_seg_list;
  514. return QDF_STATUS_SUCCESS;
  515. }
  516. #else
  517. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  518. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  519. {
  520. return QDF_STATUS_E_NOMEM;
  521. }
  522. #endif
  523. /**
  524. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  525. * @vdev: DP Vdev handle
  526. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  527. * @desc_pool_id: Descriptor Pool ID
  528. *
  529. * Return:
  530. */
  531. static
  532. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  533. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  534. {
  535. uint8_t i;
  536. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  537. struct dp_tx_seg_info_s *seg_info;
  538. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  539. struct dp_soc *soc = vdev->pdev->soc;
  540. /* Allocate an extension descriptor */
  541. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  542. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  543. if (!msdu_ext_desc) {
  544. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  545. return NULL;
  546. }
  547. if (msdu_info->exception_fw &&
  548. qdf_unlikely(vdev->mesh_vdev)) {
  549. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  550. &msdu_info->meta_data[0],
  551. sizeof(struct htt_tx_msdu_desc_ext2_t));
  552. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  553. }
  554. switch (msdu_info->frm_type) {
  555. case dp_tx_frm_sg:
  556. case dp_tx_frm_me:
  557. case dp_tx_frm_raw:
  558. seg_info = msdu_info->u.sg_info.curr_seg;
  559. /* Update the buffer pointers in MSDU Extension Descriptor */
  560. for (i = 0; i < seg_info->frag_cnt; i++) {
  561. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  562. seg_info->frags[i].paddr_lo,
  563. seg_info->frags[i].paddr_hi,
  564. seg_info->frags[i].len);
  565. }
  566. break;
  567. case dp_tx_frm_tso:
  568. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  569. &cached_ext_desc[0]);
  570. break;
  571. default:
  572. break;
  573. }
  574. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  575. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  576. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  577. msdu_ext_desc->vaddr);
  578. return msdu_ext_desc;
  579. }
  580. /**
  581. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  582. *
  583. * @skb: skb to be traced
  584. * @msdu_id: msdu_id of the packet
  585. * @vdev_id: vdev_id of the packet
  586. *
  587. * Return: None
  588. */
  589. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  590. uint8_t vdev_id)
  591. {
  592. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  593. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  594. DPTRACE(qdf_dp_trace_ptr(skb,
  595. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  596. QDF_TRACE_DEFAULT_PDEV_ID,
  597. qdf_nbuf_data_addr(skb),
  598. sizeof(qdf_nbuf_data(skb)),
  599. msdu_id, vdev_id));
  600. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  601. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  602. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  603. msdu_id, QDF_TX));
  604. }
  605. /**
  606. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  607. * @vdev: DP vdev handle
  608. * @nbuf: skb
  609. * @desc_pool_id: Descriptor pool ID
  610. * @meta_data: Metadata to the fw
  611. * @tx_exc_metadata: Handle that holds exception path metadata
  612. * Allocate and prepare Tx descriptor with msdu information.
  613. *
  614. * Return: Pointer to Tx Descriptor on success,
  615. * NULL on failure
  616. */
  617. static
  618. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  619. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  620. struct dp_tx_msdu_info_s *msdu_info,
  621. struct cdp_tx_exception_metadata *tx_exc_metadata)
  622. {
  623. uint8_t align_pad;
  624. uint8_t is_exception = 0;
  625. uint8_t htt_hdr_size;
  626. qdf_ether_header_t *eh;
  627. struct dp_tx_desc_s *tx_desc;
  628. struct dp_pdev *pdev = vdev->pdev;
  629. struct dp_soc *soc = pdev->soc;
  630. if (dp_tx_limit_check(vdev))
  631. return NULL;
  632. /* Allocate software Tx descriptor */
  633. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  634. if (qdf_unlikely(!tx_desc)) {
  635. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  636. return NULL;
  637. }
  638. dp_tx_outstanding_inc(pdev);
  639. /* Initialize the SW tx descriptor */
  640. tx_desc->nbuf = nbuf;
  641. tx_desc->frm_type = dp_tx_frm_std;
  642. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  643. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  644. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  645. tx_desc->vdev = vdev;
  646. tx_desc->pdev = pdev;
  647. tx_desc->msdu_ext_desc = NULL;
  648. tx_desc->pkt_offset = 0;
  649. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  650. /*
  651. * For special modes (vdev_type == ocb or mesh), data frames should be
  652. * transmitted using varying transmit parameters (tx spec) which include
  653. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  654. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  655. * These frames are sent as exception packets to firmware.
  656. *
  657. * HW requirement is that metadata should always point to a
  658. * 8-byte aligned address. So we add alignment pad to start of buffer.
  659. * HTT Metadata should be ensured to be multiple of 8-bytes,
  660. * to get 8-byte aligned start address along with align_pad added
  661. *
  662. * |-----------------------------|
  663. * | |
  664. * |-----------------------------| <-----Buffer Pointer Address given
  665. * | | ^ in HW descriptor (aligned)
  666. * | HTT Metadata | |
  667. * | | |
  668. * | | | Packet Offset given in descriptor
  669. * | | |
  670. * |-----------------------------| |
  671. * | Alignment Pad | v
  672. * |-----------------------------| <----- Actual buffer start address
  673. * | SKB Data | (Unaligned)
  674. * | |
  675. * | |
  676. * | |
  677. * | |
  678. * | |
  679. * |-----------------------------|
  680. */
  681. if (qdf_unlikely((msdu_info->exception_fw)) ||
  682. (vdev->opmode == wlan_op_mode_ocb) ||
  683. (tx_exc_metadata &&
  684. tx_exc_metadata->is_tx_sniffer)) {
  685. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  686. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  687. DP_STATS_INC(vdev,
  688. tx_i.dropped.headroom_insufficient, 1);
  689. goto failure;
  690. }
  691. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  692. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  693. "qdf_nbuf_push_head failed");
  694. goto failure;
  695. }
  696. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  697. msdu_info);
  698. if (htt_hdr_size == 0)
  699. goto failure;
  700. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  701. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  702. is_exception = 1;
  703. }
  704. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  705. qdf_nbuf_map(soc->osdev, nbuf,
  706. QDF_DMA_TO_DEVICE))) {
  707. /* Handle failure */
  708. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  709. "qdf_nbuf_map failed");
  710. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  711. goto failure;
  712. }
  713. if (qdf_unlikely(vdev->nawds_enabled)) {
  714. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  715. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  716. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  717. is_exception = 1;
  718. }
  719. }
  720. #if !TQM_BYPASS_WAR
  721. if (is_exception || tx_exc_metadata)
  722. #endif
  723. {
  724. /* Temporary WAR due to TQM VP issues */
  725. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  726. qdf_atomic_inc(&pdev->num_tx_exception);
  727. }
  728. return tx_desc;
  729. failure:
  730. dp_tx_desc_release(tx_desc, desc_pool_id);
  731. return NULL;
  732. }
  733. /**
  734. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  735. * @vdev: DP vdev handle
  736. * @nbuf: skb
  737. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  738. * @desc_pool_id : Descriptor Pool ID
  739. *
  740. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  741. * information. For frames wth fragments, allocate and prepare
  742. * an MSDU extension descriptor
  743. *
  744. * Return: Pointer to Tx Descriptor on success,
  745. * NULL on failure
  746. */
  747. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  748. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  749. uint8_t desc_pool_id)
  750. {
  751. struct dp_tx_desc_s *tx_desc;
  752. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  753. struct dp_pdev *pdev = vdev->pdev;
  754. struct dp_soc *soc = pdev->soc;
  755. if (dp_tx_limit_check(vdev))
  756. return NULL;
  757. /* Allocate software Tx descriptor */
  758. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  759. if (!tx_desc) {
  760. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  761. return NULL;
  762. }
  763. dp_tx_outstanding_inc(pdev);
  764. /* Initialize the SW tx descriptor */
  765. tx_desc->nbuf = nbuf;
  766. tx_desc->frm_type = msdu_info->frm_type;
  767. tx_desc->tx_encap_type = vdev->tx_encap_type;
  768. tx_desc->vdev = vdev;
  769. tx_desc->pdev = pdev;
  770. tx_desc->pkt_offset = 0;
  771. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  772. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  773. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  774. /* Handle scattered frames - TSO/SG/ME */
  775. /* Allocate and prepare an extension descriptor for scattered frames */
  776. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  777. if (!msdu_ext_desc) {
  778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  779. "%s Tx Extension Descriptor Alloc Fail",
  780. __func__);
  781. goto failure;
  782. }
  783. #if TQM_BYPASS_WAR
  784. /* Temporary WAR due to TQM VP issues */
  785. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  786. qdf_atomic_inc(&pdev->num_tx_exception);
  787. #endif
  788. if (qdf_unlikely(msdu_info->exception_fw))
  789. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  790. tx_desc->msdu_ext_desc = msdu_ext_desc;
  791. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  792. return tx_desc;
  793. failure:
  794. dp_tx_desc_release(tx_desc, desc_pool_id);
  795. return NULL;
  796. }
  797. /**
  798. * dp_tx_prepare_raw() - Prepare RAW packet TX
  799. * @vdev: DP vdev handle
  800. * @nbuf: buffer pointer
  801. * @seg_info: Pointer to Segment info Descriptor to be prepared
  802. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  803. * descriptor
  804. *
  805. * Return:
  806. */
  807. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  808. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  809. {
  810. qdf_nbuf_t curr_nbuf = NULL;
  811. uint16_t total_len = 0;
  812. qdf_dma_addr_t paddr;
  813. int32_t i;
  814. int32_t mapped_buf_num = 0;
  815. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  816. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  817. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  818. /* Continue only if frames are of DATA type */
  819. if (!DP_FRAME_IS_DATA(qos_wh)) {
  820. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  822. "Pkt. recd is of not data type");
  823. goto error;
  824. }
  825. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  826. if (vdev->raw_mode_war &&
  827. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  828. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  829. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  830. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  831. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  832. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  833. QDF_DMA_TO_DEVICE)) {
  834. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  835. "%s dma map error ", __func__);
  836. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  837. mapped_buf_num = i;
  838. goto error;
  839. }
  840. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  841. seg_info->frags[i].paddr_lo = paddr;
  842. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  843. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  844. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  845. total_len += qdf_nbuf_len(curr_nbuf);
  846. }
  847. seg_info->frag_cnt = i;
  848. seg_info->total_len = total_len;
  849. seg_info->next = NULL;
  850. sg_info->curr_seg = seg_info;
  851. msdu_info->frm_type = dp_tx_frm_raw;
  852. msdu_info->num_seg = 1;
  853. return nbuf;
  854. error:
  855. i = 0;
  856. while (nbuf) {
  857. curr_nbuf = nbuf;
  858. if (i < mapped_buf_num) {
  859. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  860. i++;
  861. }
  862. nbuf = qdf_nbuf_next(nbuf);
  863. qdf_nbuf_free(curr_nbuf);
  864. }
  865. return NULL;
  866. }
  867. /**
  868. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  869. * @soc: DP soc handle
  870. * @nbuf: Buffer pointer
  871. *
  872. * unmap the chain of nbufs that belong to this RAW frame.
  873. *
  874. * Return: None
  875. */
  876. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  877. qdf_nbuf_t nbuf)
  878. {
  879. qdf_nbuf_t cur_nbuf = nbuf;
  880. do {
  881. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  882. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  883. } while (cur_nbuf);
  884. }
  885. /**
  886. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  887. * @soc: DP Soc Handle
  888. * @vdev: DP vdev handle
  889. * @tx_desc: Tx Descriptor Handle
  890. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  891. * @fw_metadata: Metadata to send to Target Firmware along with frame
  892. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  893. * @tx_exc_metadata: Handle that holds exception path meta data
  894. *
  895. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  896. * from software Tx descriptor
  897. *
  898. * Return:
  899. */
  900. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  901. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  902. uint16_t fw_metadata, uint8_t ring_id,
  903. struct cdp_tx_exception_metadata
  904. *tx_exc_metadata)
  905. {
  906. uint8_t type;
  907. uint16_t length;
  908. void *hal_tx_desc, *hal_tx_desc_cached;
  909. qdf_dma_addr_t dma_addr;
  910. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  911. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  912. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  913. tx_exc_metadata->sec_type : vdev->sec_type);
  914. /* Return Buffer Manager ID */
  915. uint8_t bm_id = ring_id;
  916. hal_ring_handle_t hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  917. hal_tx_desc_cached = (void *) cached_desc;
  918. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  919. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  920. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  921. type = HAL_TX_BUF_TYPE_EXT_DESC;
  922. dma_addr = tx_desc->msdu_ext_desc->paddr;
  923. } else {
  924. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  925. type = HAL_TX_BUF_TYPE_BUFFER;
  926. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  927. }
  928. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  929. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  930. dma_addr, bm_id, tx_desc->id,
  931. type, soc->hal_soc);
  932. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  933. return QDF_STATUS_E_RESOURCES;
  934. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  935. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  936. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  937. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  938. vdev->pdev->lmac_id);
  939. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  940. vdev->search_type);
  941. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  942. vdev->bss_ast_hash);
  943. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  944. vdev->dscp_tid_map_id);
  945. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  946. sec_type_map[sec_type]);
  947. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  948. length, type, (uint64_t)dma_addr,
  949. tx_desc->pkt_offset, tx_desc->id);
  950. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  951. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  952. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  953. vdev->hal_desc_addr_search_flags);
  954. /* verify checksum offload configuration*/
  955. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  956. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  957. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  958. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  959. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  960. }
  961. if (tid != HTT_TX_EXT_TID_INVALID)
  962. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  963. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  964. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  965. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  966. /* Sync cached descriptor with HW */
  967. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  968. if (!hal_tx_desc) {
  969. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  970. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  971. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  972. return QDF_STATUS_E_RESOURCES;
  973. }
  974. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  975. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  976. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  977. return QDF_STATUS_SUCCESS;
  978. }
  979. /**
  980. * dp_cce_classify() - Classify the frame based on CCE rules
  981. * @vdev: DP vdev handle
  982. * @nbuf: skb
  983. *
  984. * Classify frames based on CCE rules
  985. * Return: bool( true if classified,
  986. * else false)
  987. */
  988. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  989. {
  990. qdf_ether_header_t *eh = NULL;
  991. uint16_t ether_type;
  992. qdf_llc_t *llcHdr;
  993. qdf_nbuf_t nbuf_clone = NULL;
  994. qdf_dot3_qosframe_t *qos_wh = NULL;
  995. /* for mesh packets don't do any classification */
  996. if (qdf_unlikely(vdev->mesh_vdev))
  997. return false;
  998. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  999. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1000. ether_type = eh->ether_type;
  1001. llcHdr = (qdf_llc_t *)(nbuf->data +
  1002. sizeof(qdf_ether_header_t));
  1003. } else {
  1004. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1005. /* For encrypted packets don't do any classification */
  1006. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1007. return false;
  1008. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1009. if (qdf_unlikely(
  1010. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1011. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1012. ether_type = *(uint16_t *)(nbuf->data
  1013. + QDF_IEEE80211_4ADDR_HDR_LEN
  1014. + sizeof(qdf_llc_t)
  1015. - sizeof(ether_type));
  1016. llcHdr = (qdf_llc_t *)(nbuf->data +
  1017. QDF_IEEE80211_4ADDR_HDR_LEN);
  1018. } else {
  1019. ether_type = *(uint16_t *)(nbuf->data
  1020. + QDF_IEEE80211_3ADDR_HDR_LEN
  1021. + sizeof(qdf_llc_t)
  1022. - sizeof(ether_type));
  1023. llcHdr = (qdf_llc_t *)(nbuf->data +
  1024. QDF_IEEE80211_3ADDR_HDR_LEN);
  1025. }
  1026. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1027. && (ether_type ==
  1028. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1029. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1030. return true;
  1031. }
  1032. }
  1033. return false;
  1034. }
  1035. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1036. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1037. sizeof(*llcHdr));
  1038. nbuf_clone = qdf_nbuf_clone(nbuf);
  1039. if (qdf_unlikely(nbuf_clone)) {
  1040. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1041. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1042. qdf_nbuf_pull_head(nbuf_clone,
  1043. sizeof(qdf_net_vlanhdr_t));
  1044. }
  1045. }
  1046. } else {
  1047. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1048. nbuf_clone = qdf_nbuf_clone(nbuf);
  1049. if (qdf_unlikely(nbuf_clone)) {
  1050. qdf_nbuf_pull_head(nbuf_clone,
  1051. sizeof(qdf_net_vlanhdr_t));
  1052. }
  1053. }
  1054. }
  1055. if (qdf_unlikely(nbuf_clone))
  1056. nbuf = nbuf_clone;
  1057. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1058. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1059. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1060. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1061. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1062. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1063. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1064. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1065. if (qdf_unlikely(nbuf_clone))
  1066. qdf_nbuf_free(nbuf_clone);
  1067. return true;
  1068. }
  1069. if (qdf_unlikely(nbuf_clone))
  1070. qdf_nbuf_free(nbuf_clone);
  1071. return false;
  1072. }
  1073. /**
  1074. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1075. * @vdev: DP vdev handle
  1076. * @nbuf: skb
  1077. *
  1078. * Extract the DSCP or PCP information from frame and map into TID value.
  1079. *
  1080. * Return: void
  1081. */
  1082. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1083. struct dp_tx_msdu_info_s *msdu_info)
  1084. {
  1085. uint8_t tos = 0, dscp_tid_override = 0;
  1086. uint8_t *hdr_ptr, *L3datap;
  1087. uint8_t is_mcast = 0;
  1088. qdf_ether_header_t *eh = NULL;
  1089. qdf_ethervlan_header_t *evh = NULL;
  1090. uint16_t ether_type;
  1091. qdf_llc_t *llcHdr;
  1092. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1093. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1094. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1095. eh = (qdf_ether_header_t *)nbuf->data;
  1096. hdr_ptr = eh->ether_dhost;
  1097. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1098. } else {
  1099. qdf_dot3_qosframe_t *qos_wh =
  1100. (qdf_dot3_qosframe_t *) nbuf->data;
  1101. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1102. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1103. return;
  1104. }
  1105. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1106. ether_type = eh->ether_type;
  1107. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1108. /*
  1109. * Check if packet is dot3 or eth2 type.
  1110. */
  1111. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1112. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1113. sizeof(*llcHdr));
  1114. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1115. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1116. sizeof(*llcHdr);
  1117. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1118. + sizeof(*llcHdr) +
  1119. sizeof(qdf_net_vlanhdr_t));
  1120. } else {
  1121. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1122. sizeof(*llcHdr);
  1123. }
  1124. } else {
  1125. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1126. evh = (qdf_ethervlan_header_t *) eh;
  1127. ether_type = evh->ether_type;
  1128. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1129. }
  1130. }
  1131. /*
  1132. * Find priority from IP TOS DSCP field
  1133. */
  1134. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1135. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1136. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1137. /* Only for unicast frames */
  1138. if (!is_mcast) {
  1139. /* send it on VO queue */
  1140. msdu_info->tid = DP_VO_TID;
  1141. }
  1142. } else {
  1143. /*
  1144. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1145. * from TOS byte.
  1146. */
  1147. tos = ip->ip_tos;
  1148. dscp_tid_override = 1;
  1149. }
  1150. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1151. /* TODO
  1152. * use flowlabel
  1153. *igmpmld cases to be handled in phase 2
  1154. */
  1155. unsigned long ver_pri_flowlabel;
  1156. unsigned long pri;
  1157. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1158. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1159. DP_IPV6_PRIORITY_SHIFT;
  1160. tos = pri;
  1161. dscp_tid_override = 1;
  1162. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1163. msdu_info->tid = DP_VO_TID;
  1164. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1165. /* Only for unicast frames */
  1166. if (!is_mcast) {
  1167. /* send ucast arp on VO queue */
  1168. msdu_info->tid = DP_VO_TID;
  1169. }
  1170. }
  1171. /*
  1172. * Assign all MCAST packets to BE
  1173. */
  1174. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1175. if (is_mcast) {
  1176. tos = 0;
  1177. dscp_tid_override = 1;
  1178. }
  1179. }
  1180. if (dscp_tid_override == 1) {
  1181. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1182. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1183. }
  1184. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1185. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1186. return;
  1187. }
  1188. /**
  1189. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1190. * @vdev: DP vdev handle
  1191. * @nbuf: skb
  1192. *
  1193. * Software based TID classification is required when more than 2 DSCP-TID
  1194. * mapping tables are needed.
  1195. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1196. *
  1197. * Return: void
  1198. */
  1199. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1200. struct dp_tx_msdu_info_s *msdu_info)
  1201. {
  1202. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1203. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1204. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1205. return;
  1206. /* for mesh packets don't do any classification */
  1207. if (qdf_unlikely(vdev->mesh_vdev))
  1208. return;
  1209. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1210. }
  1211. #ifdef FEATURE_WLAN_TDLS
  1212. /**
  1213. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1214. * @tx_desc: TX descriptor
  1215. *
  1216. * Return: None
  1217. */
  1218. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1219. {
  1220. if (tx_desc->vdev) {
  1221. if (tx_desc->vdev->is_tdls_frame) {
  1222. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1223. tx_desc->vdev->is_tdls_frame = false;
  1224. }
  1225. }
  1226. }
  1227. /**
  1228. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1229. * @tx_desc: TX descriptor
  1230. * @vdev: datapath vdev handle
  1231. *
  1232. * Return: None
  1233. */
  1234. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1235. struct dp_vdev *vdev)
  1236. {
  1237. struct hal_tx_completion_status ts = {0};
  1238. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1239. if (qdf_unlikely(!vdev)) {
  1240. dp_err("vdev is null!");
  1241. return;
  1242. }
  1243. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1244. if (vdev->tx_non_std_data_callback.func) {
  1245. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1246. vdev->tx_non_std_data_callback.func(
  1247. vdev->tx_non_std_data_callback.ctxt,
  1248. nbuf, ts.status);
  1249. return;
  1250. }
  1251. }
  1252. #else
  1253. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1254. {
  1255. }
  1256. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1257. struct dp_vdev *vdev)
  1258. {
  1259. }
  1260. #endif
  1261. /**
  1262. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1263. * @vdev: DP vdev handle
  1264. * @nbuf: skb
  1265. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1266. * @meta_data: Metadata to the fw
  1267. * @tx_q: Tx queue to be used for this Tx frame
  1268. * @peer_id: peer_id of the peer in case of NAWDS frames
  1269. * @tx_exc_metadata: Handle that holds exception path metadata
  1270. *
  1271. * Return: NULL on success,
  1272. * nbuf when it fails to send
  1273. */
  1274. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1275. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1276. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1277. {
  1278. struct dp_pdev *pdev = vdev->pdev;
  1279. struct dp_soc *soc = pdev->soc;
  1280. struct dp_tx_desc_s *tx_desc;
  1281. QDF_STATUS status;
  1282. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1283. hal_ring_handle_t hal_ring_hdl =
  1284. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1285. uint16_t htt_tcl_metadata = 0;
  1286. uint8_t tid = msdu_info->tid;
  1287. struct cdp_tid_tx_stats *tid_stats = NULL;
  1288. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1289. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1290. msdu_info, tx_exc_metadata);
  1291. if (!tx_desc) {
  1292. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1293. vdev, tx_q->desc_pool_id);
  1294. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1295. tid_stats = &pdev->stats.tid_stats.
  1296. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1297. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1298. return nbuf;
  1299. }
  1300. if (qdf_unlikely(soc->cce_disable)) {
  1301. if (dp_cce_classify(vdev, nbuf) == true) {
  1302. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1303. tid = DP_VO_TID;
  1304. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1305. }
  1306. }
  1307. dp_tx_update_tdls_flags(tx_desc);
  1308. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1309. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1310. "%s %d : HAL RING Access Failed -- %pK",
  1311. __func__, __LINE__, hal_ring_hdl);
  1312. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1313. tid_stats = &pdev->stats.tid_stats.
  1314. tid_tx_stats[tx_q->ring_id][tid];
  1315. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1316. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1317. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1318. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1319. goto fail_return;
  1320. }
  1321. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1322. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1323. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1324. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1325. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1326. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1327. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1328. peer_id);
  1329. } else
  1330. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1331. if (msdu_info->exception_fw) {
  1332. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1333. }
  1334. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1335. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1336. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1337. if (status != QDF_STATUS_SUCCESS) {
  1338. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1339. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1340. __func__, tx_desc, tx_q->ring_id);
  1341. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1342. tid_stats = &pdev->stats.tid_stats.
  1343. tid_tx_stats[tx_q->ring_id][tid];
  1344. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1345. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1346. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1347. goto fail_return;
  1348. }
  1349. nbuf = NULL;
  1350. fail_return:
  1351. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1352. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1353. hif_pm_runtime_put(soc->hif_handle);
  1354. } else {
  1355. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1356. }
  1357. return nbuf;
  1358. }
  1359. /**
  1360. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1361. * @vdev: DP vdev handle
  1362. * @nbuf: skb
  1363. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1364. *
  1365. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1366. *
  1367. * Return: NULL on success,
  1368. * nbuf when it fails to send
  1369. */
  1370. #if QDF_LOCK_STATS
  1371. noinline
  1372. #else
  1373. #endif
  1374. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1375. struct dp_tx_msdu_info_s *msdu_info)
  1376. {
  1377. uint8_t i;
  1378. struct dp_pdev *pdev = vdev->pdev;
  1379. struct dp_soc *soc = pdev->soc;
  1380. struct dp_tx_desc_s *tx_desc;
  1381. bool is_cce_classified = false;
  1382. QDF_STATUS status;
  1383. uint16_t htt_tcl_metadata = 0;
  1384. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1385. hal_ring_handle_t hal_ring_hdl =
  1386. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1387. struct cdp_tid_tx_stats *tid_stats = NULL;
  1388. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1389. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1390. "%s %d : HAL RING Access Failed -- %pK",
  1391. __func__, __LINE__, hal_ring_hdl);
  1392. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1393. tid_stats = &pdev->stats.tid_stats.
  1394. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1395. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1396. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1397. return nbuf;
  1398. }
  1399. if (qdf_unlikely(soc->cce_disable)) {
  1400. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1401. if (is_cce_classified) {
  1402. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1403. msdu_info->tid = DP_VO_TID;
  1404. }
  1405. }
  1406. if (msdu_info->frm_type == dp_tx_frm_me)
  1407. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1408. i = 0;
  1409. /* Print statement to track i and num_seg */
  1410. /*
  1411. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1412. * descriptors using information in msdu_info
  1413. */
  1414. while (i < msdu_info->num_seg) {
  1415. /*
  1416. * Setup Tx descriptor for an MSDU, and MSDU extension
  1417. * descriptor
  1418. */
  1419. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1420. tx_q->desc_pool_id);
  1421. if (!tx_desc) {
  1422. if (msdu_info->frm_type == dp_tx_frm_me) {
  1423. dp_tx_me_free_buf(pdev,
  1424. (void *)(msdu_info->u.sg_info
  1425. .curr_seg->frags[0].vaddr));
  1426. }
  1427. goto done;
  1428. }
  1429. if (msdu_info->frm_type == dp_tx_frm_me) {
  1430. tx_desc->me_buffer =
  1431. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1432. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1433. }
  1434. if (is_cce_classified)
  1435. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1436. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1437. if (msdu_info->exception_fw) {
  1438. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1439. }
  1440. /*
  1441. * Enqueue the Tx MSDU descriptor to HW for transmit
  1442. */
  1443. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1444. htt_tcl_metadata, tx_q->ring_id, NULL);
  1445. if (status != QDF_STATUS_SUCCESS) {
  1446. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1447. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1448. __func__, tx_desc, tx_q->ring_id);
  1449. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1450. tid_stats = &pdev->stats.tid_stats.
  1451. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1452. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1453. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1454. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1455. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1456. goto done;
  1457. }
  1458. /*
  1459. * TODO
  1460. * if tso_info structure can be modified to have curr_seg
  1461. * as first element, following 2 blocks of code (for TSO and SG)
  1462. * can be combined into 1
  1463. */
  1464. /*
  1465. * For frames with multiple segments (TSO, ME), jump to next
  1466. * segment.
  1467. */
  1468. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1469. if (msdu_info->u.tso_info.curr_seg->next) {
  1470. msdu_info->u.tso_info.curr_seg =
  1471. msdu_info->u.tso_info.curr_seg->next;
  1472. /*
  1473. * If this is a jumbo nbuf, then increment the number of
  1474. * nbuf users for each additional segment of the msdu.
  1475. * This will ensure that the skb is freed only after
  1476. * receiving tx completion for all segments of an nbuf
  1477. */
  1478. qdf_nbuf_inc_users(nbuf);
  1479. /* Check with MCL if this is needed */
  1480. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1481. }
  1482. }
  1483. /*
  1484. * For Multicast-Unicast converted packets,
  1485. * each converted frame (for a client) is represented as
  1486. * 1 segment
  1487. */
  1488. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1489. (msdu_info->frm_type == dp_tx_frm_me)) {
  1490. if (msdu_info->u.sg_info.curr_seg->next) {
  1491. msdu_info->u.sg_info.curr_seg =
  1492. msdu_info->u.sg_info.curr_seg->next;
  1493. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1494. }
  1495. }
  1496. i++;
  1497. }
  1498. nbuf = NULL;
  1499. done:
  1500. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1501. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1502. hif_pm_runtime_put(soc->hif_handle);
  1503. } else {
  1504. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1505. }
  1506. return nbuf;
  1507. }
  1508. /**
  1509. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1510. * for SG frames
  1511. * @vdev: DP vdev handle
  1512. * @nbuf: skb
  1513. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1514. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1515. *
  1516. * Return: NULL on success,
  1517. * nbuf when it fails to send
  1518. */
  1519. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1520. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1521. {
  1522. uint32_t cur_frag, nr_frags;
  1523. qdf_dma_addr_t paddr;
  1524. struct dp_tx_sg_info_s *sg_info;
  1525. sg_info = &msdu_info->u.sg_info;
  1526. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1527. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1528. QDF_DMA_TO_DEVICE)) {
  1529. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1530. "dma map error");
  1531. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1532. qdf_nbuf_free(nbuf);
  1533. return NULL;
  1534. }
  1535. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1536. seg_info->frags[0].paddr_lo = paddr;
  1537. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1538. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1539. seg_info->frags[0].vaddr = (void *) nbuf;
  1540. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1541. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1542. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1543. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1544. "frag dma map error");
  1545. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1546. qdf_nbuf_free(nbuf);
  1547. return NULL;
  1548. }
  1549. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1550. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1551. seg_info->frags[cur_frag + 1].paddr_hi =
  1552. ((uint64_t) paddr) >> 32;
  1553. seg_info->frags[cur_frag + 1].len =
  1554. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1555. }
  1556. seg_info->frag_cnt = (cur_frag + 1);
  1557. seg_info->total_len = qdf_nbuf_len(nbuf);
  1558. seg_info->next = NULL;
  1559. sg_info->curr_seg = seg_info;
  1560. msdu_info->frm_type = dp_tx_frm_sg;
  1561. msdu_info->num_seg = 1;
  1562. return nbuf;
  1563. }
  1564. /**
  1565. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1566. * @vdev: DP vdev handle
  1567. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1568. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1569. *
  1570. * Return: NULL on failure,
  1571. * nbuf when extracted successfully
  1572. */
  1573. static
  1574. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1575. struct dp_tx_msdu_info_s *msdu_info,
  1576. uint16_t ppdu_cookie)
  1577. {
  1578. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1579. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1580. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1581. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1582. (msdu_info->meta_data[5], 1);
  1583. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1584. (msdu_info->meta_data[5], 1);
  1585. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1586. (msdu_info->meta_data[6], ppdu_cookie);
  1587. msdu_info->exception_fw = 1;
  1588. msdu_info->is_tx_sniffer = 1;
  1589. }
  1590. #ifdef MESH_MODE_SUPPORT
  1591. /**
  1592. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1593. and prepare msdu_info for mesh frames.
  1594. * @vdev: DP vdev handle
  1595. * @nbuf: skb
  1596. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1597. *
  1598. * Return: NULL on failure,
  1599. * nbuf when extracted successfully
  1600. */
  1601. static
  1602. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1603. struct dp_tx_msdu_info_s *msdu_info)
  1604. {
  1605. struct meta_hdr_s *mhdr;
  1606. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1607. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1608. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1609. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1610. msdu_info->exception_fw = 0;
  1611. goto remove_meta_hdr;
  1612. }
  1613. msdu_info->exception_fw = 1;
  1614. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1615. meta_data->host_tx_desc_pool = 1;
  1616. meta_data->update_peer_cache = 1;
  1617. meta_data->learning_frame = 1;
  1618. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1619. meta_data->power = mhdr->power;
  1620. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1621. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1622. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1623. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1624. meta_data->dyn_bw = 1;
  1625. meta_data->valid_pwr = 1;
  1626. meta_data->valid_mcs_mask = 1;
  1627. meta_data->valid_nss_mask = 1;
  1628. meta_data->valid_preamble_type = 1;
  1629. meta_data->valid_retries = 1;
  1630. meta_data->valid_bw_info = 1;
  1631. }
  1632. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1633. meta_data->encrypt_type = 0;
  1634. meta_data->valid_encrypt_type = 1;
  1635. meta_data->learning_frame = 0;
  1636. }
  1637. meta_data->valid_key_flags = 1;
  1638. meta_data->key_flags = (mhdr->keyix & 0x3);
  1639. remove_meta_hdr:
  1640. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1641. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1642. "qdf_nbuf_pull_head failed");
  1643. qdf_nbuf_free(nbuf);
  1644. return NULL;
  1645. }
  1646. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1647. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1648. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1649. " tid %d to_fw %d",
  1650. __func__, msdu_info->meta_data[0],
  1651. msdu_info->meta_data[1],
  1652. msdu_info->meta_data[2],
  1653. msdu_info->meta_data[3],
  1654. msdu_info->meta_data[4],
  1655. msdu_info->meta_data[5],
  1656. msdu_info->tid, msdu_info->exception_fw);
  1657. return nbuf;
  1658. }
  1659. #else
  1660. static
  1661. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1662. struct dp_tx_msdu_info_s *msdu_info)
  1663. {
  1664. return nbuf;
  1665. }
  1666. #endif
  1667. /**
  1668. * dp_check_exc_metadata() - Checks if parameters are valid
  1669. * @tx_exc - holds all exception path parameters
  1670. *
  1671. * Returns true when all the parameters are valid else false
  1672. *
  1673. */
  1674. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1675. {
  1676. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1677. HTT_INVALID_TID);
  1678. bool invalid_encap_type =
  1679. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1680. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1681. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1682. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1683. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1684. tx_exc->ppdu_cookie == 0);
  1685. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1686. invalid_cookie) {
  1687. return false;
  1688. }
  1689. return true;
  1690. }
  1691. /**
  1692. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1693. * @vap_dev: DP vdev handle
  1694. * @nbuf: skb
  1695. * @tx_exc_metadata: Handle that holds exception path meta data
  1696. *
  1697. * Entry point for Core Tx layer (DP_TX) invoked from
  1698. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1699. *
  1700. * Return: NULL on success,
  1701. * nbuf when it fails to send
  1702. */
  1703. qdf_nbuf_t
  1704. dp_tx_send_exception(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf,
  1705. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1706. {
  1707. qdf_ether_header_t *eh = NULL;
  1708. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1709. struct dp_tx_msdu_info_s msdu_info;
  1710. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1711. if (!tx_exc_metadata)
  1712. goto fail;
  1713. msdu_info.tid = tx_exc_metadata->tid;
  1714. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1715. dp_verbose_debug("skb %pM", nbuf->data);
  1716. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1717. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1718. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1719. "Invalid parameters in exception path");
  1720. goto fail;
  1721. }
  1722. /* Basic sanity checks for unsupported packets */
  1723. /* MESH mode */
  1724. if (qdf_unlikely(vdev->mesh_vdev)) {
  1725. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1726. "Mesh mode is not supported in exception path");
  1727. goto fail;
  1728. }
  1729. /* TSO or SG */
  1730. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1731. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1732. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1733. "TSO and SG are not supported in exception path");
  1734. goto fail;
  1735. }
  1736. /* RAW */
  1737. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1738. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1739. "Raw frame is not supported in exception path");
  1740. goto fail;
  1741. }
  1742. /* Mcast enhancement*/
  1743. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1744. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1745. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1746. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1747. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1748. }
  1749. }
  1750. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1751. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1752. qdf_nbuf_len(nbuf));
  1753. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1754. tx_exc_metadata->ppdu_cookie);
  1755. }
  1756. /*
  1757. * Get HW Queue to use for this frame.
  1758. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1759. * dedicated for data and 1 for command.
  1760. * "queue_id" maps to one hardware ring.
  1761. * With each ring, we also associate a unique Tx descriptor pool
  1762. * to minimize lock contention for these resources.
  1763. */
  1764. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1765. /* Single linear frame */
  1766. /*
  1767. * If nbuf is a simple linear frame, use send_single function to
  1768. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1769. * SRNG. There is no need to setup a MSDU extension descriptor.
  1770. */
  1771. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1772. tx_exc_metadata->peer_id, tx_exc_metadata);
  1773. return nbuf;
  1774. fail:
  1775. dp_verbose_debug("pkt send failed");
  1776. return nbuf;
  1777. }
  1778. /**
  1779. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1780. * @vap_dev: DP vdev handle
  1781. * @nbuf: skb
  1782. *
  1783. * Entry point for Core Tx layer (DP_TX) invoked from
  1784. * hard_start_xmit in OSIF/HDD
  1785. *
  1786. * Return: NULL on success,
  1787. * nbuf when it fails to send
  1788. */
  1789. #ifdef MESH_MODE_SUPPORT
  1790. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1791. {
  1792. struct meta_hdr_s *mhdr;
  1793. qdf_nbuf_t nbuf_mesh = NULL;
  1794. qdf_nbuf_t nbuf_clone = NULL;
  1795. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1796. uint8_t no_enc_frame = 0;
  1797. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1798. if (!nbuf_mesh) {
  1799. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1800. "qdf_nbuf_unshare failed");
  1801. return nbuf;
  1802. }
  1803. nbuf = nbuf_mesh;
  1804. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1805. if ((vdev->sec_type != cdp_sec_type_none) &&
  1806. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1807. no_enc_frame = 1;
  1808. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1809. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1810. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1811. !no_enc_frame) {
  1812. nbuf_clone = qdf_nbuf_clone(nbuf);
  1813. if (!nbuf_clone) {
  1814. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1815. "qdf_nbuf_clone failed");
  1816. return nbuf;
  1817. }
  1818. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1819. }
  1820. if (nbuf_clone) {
  1821. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1822. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1823. } else {
  1824. qdf_nbuf_free(nbuf_clone);
  1825. }
  1826. }
  1827. if (no_enc_frame)
  1828. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1829. else
  1830. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1831. nbuf = dp_tx_send(vap_dev, nbuf);
  1832. if ((!nbuf) && no_enc_frame) {
  1833. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1834. }
  1835. return nbuf;
  1836. }
  1837. #else
  1838. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1839. {
  1840. return dp_tx_send(vap_dev, nbuf);
  1841. }
  1842. #endif
  1843. /**
  1844. * dp_tx_send() - Transmit a frame on a given VAP
  1845. * @vap_dev: DP vdev handle
  1846. * @nbuf: skb
  1847. *
  1848. * Entry point for Core Tx layer (DP_TX) invoked from
  1849. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1850. * cases
  1851. *
  1852. * Return: NULL on success,
  1853. * nbuf when it fails to send
  1854. */
  1855. qdf_nbuf_t dp_tx_send(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1856. {
  1857. qdf_ether_header_t *eh = NULL;
  1858. struct dp_tx_msdu_info_s msdu_info;
  1859. struct dp_tx_seg_info_s seg_info;
  1860. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1861. uint16_t peer_id = HTT_INVALID_PEER;
  1862. qdf_nbuf_t nbuf_mesh = NULL;
  1863. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1864. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1865. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1866. dp_verbose_debug("skb %pM", nbuf->data);
  1867. /*
  1868. * Set Default Host TID value to invalid TID
  1869. * (TID override disabled)
  1870. */
  1871. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1872. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1873. if (qdf_unlikely(vdev->mesh_vdev)) {
  1874. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1875. &msdu_info);
  1876. if (!nbuf_mesh) {
  1877. dp_verbose_debug("Extracting mesh metadata failed");
  1878. return nbuf;
  1879. }
  1880. nbuf = nbuf_mesh;
  1881. }
  1882. /*
  1883. * Get HW Queue to use for this frame.
  1884. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1885. * dedicated for data and 1 for command.
  1886. * "queue_id" maps to one hardware ring.
  1887. * With each ring, we also associate a unique Tx descriptor pool
  1888. * to minimize lock contention for these resources.
  1889. */
  1890. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1891. /*
  1892. * TCL H/W supports 2 DSCP-TID mapping tables.
  1893. * Table 1 - Default DSCP-TID mapping table
  1894. * Table 2 - 1 DSCP-TID override table
  1895. *
  1896. * If we need a different DSCP-TID mapping for this vap,
  1897. * call tid_classify to extract DSCP/ToS from frame and
  1898. * map to a TID and store in msdu_info. This is later used
  1899. * to fill in TCL Input descriptor (per-packet TID override).
  1900. */
  1901. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1902. /*
  1903. * Classify the frame and call corresponding
  1904. * "prepare" function which extracts the segment (TSO)
  1905. * and fragmentation information (for TSO , SG, ME, or Raw)
  1906. * into MSDU_INFO structure which is later used to fill
  1907. * SW and HW descriptors.
  1908. */
  1909. if (qdf_nbuf_is_tso(nbuf)) {
  1910. dp_verbose_debug("TSO frame %pK", vdev);
  1911. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1912. qdf_nbuf_len(nbuf));
  1913. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1914. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1915. qdf_nbuf_len(nbuf));
  1916. return nbuf;
  1917. }
  1918. goto send_multiple;
  1919. }
  1920. /* SG */
  1921. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1922. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1923. if (!nbuf)
  1924. return NULL;
  1925. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1926. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1927. qdf_nbuf_len(nbuf));
  1928. goto send_multiple;
  1929. }
  1930. #ifdef ATH_SUPPORT_IQUE
  1931. /* Mcast to Ucast Conversion*/
  1932. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1933. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1934. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1935. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1936. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1937. DP_STATS_INC_PKT(vdev,
  1938. tx_i.mcast_en.mcast_pkt, 1,
  1939. qdf_nbuf_len(nbuf));
  1940. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1941. QDF_STATUS_SUCCESS) {
  1942. return NULL;
  1943. }
  1944. }
  1945. }
  1946. #endif
  1947. /* RAW */
  1948. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1949. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1950. if (!nbuf)
  1951. return NULL;
  1952. dp_verbose_debug("Raw frame %pK", vdev);
  1953. goto send_multiple;
  1954. }
  1955. /* Single linear frame */
  1956. /*
  1957. * If nbuf is a simple linear frame, use send_single function to
  1958. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1959. * SRNG. There is no need to setup a MSDU extension descriptor.
  1960. */
  1961. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1962. return nbuf;
  1963. send_multiple:
  1964. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1965. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  1966. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  1967. return nbuf;
  1968. }
  1969. /**
  1970. * dp_tx_reinject_handler() - Tx Reinject Handler
  1971. * @tx_desc: software descriptor head pointer
  1972. * @status : Tx completion status from HTT descriptor
  1973. *
  1974. * This function reinjects frames back to Target.
  1975. * Todo - Host queue needs to be added
  1976. *
  1977. * Return: none
  1978. */
  1979. static
  1980. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1981. {
  1982. struct dp_vdev *vdev;
  1983. struct dp_peer *peer = NULL;
  1984. uint32_t peer_id = HTT_INVALID_PEER;
  1985. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1986. qdf_nbuf_t nbuf_copy = NULL;
  1987. struct dp_tx_msdu_info_s msdu_info;
  1988. struct dp_peer *sa_peer = NULL;
  1989. struct dp_ast_entry *ast_entry = NULL;
  1990. struct dp_soc *soc = NULL;
  1991. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1992. #ifdef WDS_VENDOR_EXTENSION
  1993. int is_mcast = 0, is_ucast = 0;
  1994. int num_peers_3addr = 0;
  1995. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1996. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1997. #endif
  1998. vdev = tx_desc->vdev;
  1999. soc = vdev->pdev->soc;
  2000. qdf_assert(vdev);
  2001. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2002. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2003. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2004. "%s Tx reinject path", __func__);
  2005. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2006. qdf_nbuf_len(tx_desc->nbuf));
  2007. qdf_spin_lock_bh(&(soc->ast_lock));
  2008. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2009. (soc,
  2010. (uint8_t *)(eh->ether_shost),
  2011. vdev->pdev->pdev_id);
  2012. if (ast_entry)
  2013. sa_peer = ast_entry->peer;
  2014. qdf_spin_unlock_bh(&(soc->ast_lock));
  2015. #ifdef WDS_VENDOR_EXTENSION
  2016. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2017. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2018. } else {
  2019. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2020. }
  2021. is_ucast = !is_mcast;
  2022. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2023. if (peer->bss_peer)
  2024. continue;
  2025. /* Detect wds peers that use 3-addr framing for mcast.
  2026. * if there are any, the bss_peer is used to send the
  2027. * the mcast frame using 3-addr format. all wds enabled
  2028. * peers that use 4-addr framing for mcast frames will
  2029. * be duplicated and sent as 4-addr frames below.
  2030. */
  2031. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2032. num_peers_3addr = 1;
  2033. break;
  2034. }
  2035. }
  2036. #endif
  2037. if (qdf_unlikely(vdev->mesh_vdev)) {
  2038. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2039. } else {
  2040. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2041. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2042. #ifdef WDS_VENDOR_EXTENSION
  2043. /*
  2044. * . if 3-addr STA, then send on BSS Peer
  2045. * . if Peer WDS enabled and accept 4-addr mcast,
  2046. * send mcast on that peer only
  2047. * . if Peer WDS enabled and accept 4-addr ucast,
  2048. * send ucast on that peer only
  2049. */
  2050. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2051. (peer->wds_enabled &&
  2052. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2053. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2054. #else
  2055. ((peer->bss_peer &&
  2056. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2057. peer->nawds_enabled)) {
  2058. #endif
  2059. peer_id = DP_INVALID_PEER;
  2060. if (peer->nawds_enabled) {
  2061. peer_id = peer->peer_ids[0];
  2062. if (sa_peer == peer) {
  2063. QDF_TRACE(
  2064. QDF_MODULE_ID_DP,
  2065. QDF_TRACE_LEVEL_DEBUG,
  2066. " %s: multicast packet",
  2067. __func__);
  2068. DP_STATS_INC(peer,
  2069. tx.nawds_mcast_drop, 1);
  2070. continue;
  2071. }
  2072. }
  2073. nbuf_copy = qdf_nbuf_copy(nbuf);
  2074. if (!nbuf_copy) {
  2075. QDF_TRACE(QDF_MODULE_ID_DP,
  2076. QDF_TRACE_LEVEL_DEBUG,
  2077. FL("nbuf copy failed"));
  2078. break;
  2079. }
  2080. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2081. nbuf_copy,
  2082. &msdu_info,
  2083. peer_id,
  2084. NULL);
  2085. if (nbuf_copy) {
  2086. QDF_TRACE(QDF_MODULE_ID_DP,
  2087. QDF_TRACE_LEVEL_DEBUG,
  2088. FL("pkt send failed"));
  2089. qdf_nbuf_free(nbuf_copy);
  2090. } else {
  2091. if (peer_id != DP_INVALID_PEER)
  2092. DP_STATS_INC_PKT(peer,
  2093. tx.nawds_mcast,
  2094. 1, qdf_nbuf_len(nbuf));
  2095. }
  2096. }
  2097. }
  2098. }
  2099. if (vdev->nawds_enabled) {
  2100. peer_id = DP_INVALID_PEER;
  2101. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2102. 1, qdf_nbuf_len(nbuf));
  2103. nbuf = dp_tx_send_msdu_single(vdev,
  2104. nbuf,
  2105. &msdu_info,
  2106. peer_id, NULL);
  2107. if (nbuf) {
  2108. QDF_TRACE(QDF_MODULE_ID_DP,
  2109. QDF_TRACE_LEVEL_DEBUG,
  2110. FL("pkt send failed"));
  2111. qdf_nbuf_free(nbuf);
  2112. }
  2113. } else
  2114. qdf_nbuf_free(nbuf);
  2115. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2116. }
  2117. /**
  2118. * dp_tx_inspect_handler() - Tx Inspect Handler
  2119. * @tx_desc: software descriptor head pointer
  2120. * @status : Tx completion status from HTT descriptor
  2121. *
  2122. * Handles Tx frames sent back to Host for inspection
  2123. * (ProxyARP)
  2124. *
  2125. * Return: none
  2126. */
  2127. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2128. {
  2129. struct dp_soc *soc;
  2130. struct dp_pdev *pdev = tx_desc->pdev;
  2131. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2132. "%s Tx inspect path",
  2133. __func__);
  2134. qdf_assert(pdev);
  2135. soc = pdev->soc;
  2136. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2137. qdf_nbuf_len(tx_desc->nbuf));
  2138. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2139. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2140. }
  2141. #ifdef FEATURE_PERPKT_INFO
  2142. /**
  2143. * dp_get_completion_indication_for_stack() - send completion to stack
  2144. * @soc : dp_soc handle
  2145. * @pdev: dp_pdev handle
  2146. * @peer: dp peer handle
  2147. * @ts: transmit completion status structure
  2148. * @netbuf: Buffer pointer for free
  2149. *
  2150. * This function is used for indication whether buffer needs to be
  2151. * sent to stack for freeing or not
  2152. */
  2153. QDF_STATUS
  2154. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2155. struct dp_pdev *pdev,
  2156. struct dp_peer *peer,
  2157. struct hal_tx_completion_status *ts,
  2158. qdf_nbuf_t netbuf,
  2159. uint64_t time_latency)
  2160. {
  2161. struct tx_capture_hdr *ppdu_hdr;
  2162. uint16_t peer_id = ts->peer_id;
  2163. uint32_t ppdu_id = ts->ppdu_id;
  2164. uint8_t first_msdu = ts->first_msdu;
  2165. uint8_t last_msdu = ts->last_msdu;
  2166. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2167. !pdev->latency_capture_enable))
  2168. return QDF_STATUS_E_NOSUPPORT;
  2169. if (!peer) {
  2170. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2171. FL("Peer Invalid"));
  2172. return QDF_STATUS_E_INVAL;
  2173. }
  2174. if (pdev->mcopy_mode) {
  2175. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2176. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2177. return QDF_STATUS_E_INVAL;
  2178. }
  2179. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2180. pdev->m_copy_id.tx_peer_id = peer_id;
  2181. }
  2182. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2183. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2184. FL("No headroom"));
  2185. return QDF_STATUS_E_NOMEM;
  2186. }
  2187. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2188. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2189. QDF_MAC_ADDR_SIZE);
  2190. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2191. QDF_MAC_ADDR_SIZE);
  2192. ppdu_hdr->ppdu_id = ppdu_id;
  2193. ppdu_hdr->peer_id = peer_id;
  2194. ppdu_hdr->first_msdu = first_msdu;
  2195. ppdu_hdr->last_msdu = last_msdu;
  2196. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2197. ppdu_hdr->tsf = ts->tsf;
  2198. ppdu_hdr->time_latency = time_latency;
  2199. }
  2200. return QDF_STATUS_SUCCESS;
  2201. }
  2202. /**
  2203. * dp_send_completion_to_stack() - send completion to stack
  2204. * @soc : dp_soc handle
  2205. * @pdev: dp_pdev handle
  2206. * @peer_id: peer_id of the peer for which completion came
  2207. * @ppdu_id: ppdu_id
  2208. * @netbuf: Buffer pointer for free
  2209. *
  2210. * This function is used to send completion to stack
  2211. * to free buffer
  2212. */
  2213. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2214. uint16_t peer_id, uint32_t ppdu_id,
  2215. qdf_nbuf_t netbuf)
  2216. {
  2217. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2218. netbuf, peer_id,
  2219. WDI_NO_VAL, pdev->pdev_id);
  2220. }
  2221. #else
  2222. static QDF_STATUS
  2223. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2224. struct dp_pdev *pdev,
  2225. struct dp_peer *peer,
  2226. struct hal_tx_completion_status *ts,
  2227. qdf_nbuf_t netbuf,
  2228. uint64_t time_latency)
  2229. {
  2230. return QDF_STATUS_E_NOSUPPORT;
  2231. }
  2232. static void
  2233. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2234. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2235. {
  2236. }
  2237. #endif
  2238. /**
  2239. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2240. * @soc: Soc handle
  2241. * @desc: software Tx descriptor to be processed
  2242. *
  2243. * Return: none
  2244. */
  2245. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2246. struct dp_tx_desc_s *desc)
  2247. {
  2248. struct dp_vdev *vdev = desc->vdev;
  2249. qdf_nbuf_t nbuf = desc->nbuf;
  2250. /* nbuf already freed in vdev detach path */
  2251. if (!nbuf)
  2252. return;
  2253. /* If it is TDLS mgmt, don't unmap or free the frame */
  2254. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2255. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2256. /* 0 : MSDU buffer, 1 : MLE */
  2257. if (desc->msdu_ext_desc) {
  2258. /* TSO free */
  2259. if (hal_tx_ext_desc_get_tso_enable(
  2260. desc->msdu_ext_desc->vaddr)) {
  2261. /* unmap eash TSO seg before free the nbuf */
  2262. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2263. desc->tso_num_desc);
  2264. qdf_nbuf_free(nbuf);
  2265. return;
  2266. }
  2267. }
  2268. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2269. if (qdf_unlikely(!vdev)) {
  2270. qdf_nbuf_free(nbuf);
  2271. return;
  2272. }
  2273. if (qdf_likely(!vdev->mesh_vdev))
  2274. qdf_nbuf_free(nbuf);
  2275. else {
  2276. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2277. qdf_nbuf_free(nbuf);
  2278. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2279. } else
  2280. vdev->osif_tx_free_ext((nbuf));
  2281. }
  2282. }
  2283. #ifdef MESH_MODE_SUPPORT
  2284. /**
  2285. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2286. * in mesh meta header
  2287. * @tx_desc: software descriptor head pointer
  2288. * @ts: pointer to tx completion stats
  2289. * Return: none
  2290. */
  2291. static
  2292. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2293. struct hal_tx_completion_status *ts)
  2294. {
  2295. struct meta_hdr_s *mhdr;
  2296. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2297. if (!tx_desc->msdu_ext_desc) {
  2298. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2299. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2300. "netbuf %pK offset %d",
  2301. netbuf, tx_desc->pkt_offset);
  2302. return;
  2303. }
  2304. }
  2305. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2306. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2307. "netbuf %pK offset %lu", netbuf,
  2308. sizeof(struct meta_hdr_s));
  2309. return;
  2310. }
  2311. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2312. mhdr->rssi = ts->ack_frame_rssi;
  2313. mhdr->channel = tx_desc->pdev->operating_channel;
  2314. }
  2315. #else
  2316. static
  2317. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2318. struct hal_tx_completion_status *ts)
  2319. {
  2320. }
  2321. #endif
  2322. /**
  2323. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2324. * to pass in correct fields
  2325. *
  2326. * @vdev: pdev handle
  2327. * @tx_desc: tx descriptor
  2328. * @tid: tid value
  2329. * @ring_id: TCL or WBM ring number for transmit path
  2330. * Return: none
  2331. */
  2332. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2333. struct dp_tx_desc_s *tx_desc,
  2334. uint8_t tid, uint8_t ring_id)
  2335. {
  2336. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2337. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2338. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2339. return;
  2340. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2341. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2342. timestamp_hw_enqueue = tx_desc->timestamp;
  2343. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2344. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2345. timestamp_hw_enqueue);
  2346. interframe_delay = (uint32_t)(timestamp_ingress -
  2347. vdev->prev_tx_enq_tstamp);
  2348. /*
  2349. * Delay in software enqueue
  2350. */
  2351. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2352. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2353. /*
  2354. * Delay between packet enqueued to HW and Tx completion
  2355. */
  2356. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2357. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2358. /*
  2359. * Update interframe delay stats calculated at hardstart receive point.
  2360. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2361. * interframe delay will not be calculate correctly for 1st frame.
  2362. * On the other side, this will help in avoiding extra per packet check
  2363. * of !vdev->prev_tx_enq_tstamp.
  2364. */
  2365. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2366. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2367. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2368. }
  2369. /**
  2370. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2371. * per wbm ring
  2372. *
  2373. * @tx_desc: software descriptor head pointer
  2374. * @ts: Tx completion status
  2375. * @peer: peer handle
  2376. * @ring_id: ring number
  2377. *
  2378. * Return: None
  2379. */
  2380. static inline void
  2381. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2382. struct hal_tx_completion_status *ts,
  2383. struct dp_peer *peer, uint8_t ring_id)
  2384. {
  2385. struct dp_pdev *pdev = peer->vdev->pdev;
  2386. struct dp_soc *soc = NULL;
  2387. uint8_t mcs, pkt_type;
  2388. uint8_t tid = ts->tid;
  2389. uint32_t length;
  2390. struct cdp_tid_tx_stats *tid_stats;
  2391. if (!pdev)
  2392. return;
  2393. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2394. tid = CDP_MAX_DATA_TIDS - 1;
  2395. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2396. soc = pdev->soc;
  2397. mcs = ts->mcs;
  2398. pkt_type = ts->pkt_type;
  2399. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2400. dp_err("Release source is not from TQM");
  2401. return;
  2402. }
  2403. length = qdf_nbuf_len(tx_desc->nbuf);
  2404. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2405. if (qdf_unlikely(pdev->delay_stats_flag))
  2406. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2407. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2408. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2409. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2410. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2411. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2412. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2413. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2414. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2415. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2416. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2417. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2418. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2419. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2420. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2421. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2422. tid_stats->comp_fail_cnt++;
  2423. return;
  2424. }
  2425. tid_stats->success_cnt++;
  2426. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2427. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2428. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2429. /*
  2430. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2431. * Return from here if HTT PPDU events are enabled.
  2432. */
  2433. if (!(soc->process_tx_status))
  2434. return;
  2435. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2436. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2437. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2438. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2439. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2440. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2441. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2442. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2443. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2444. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2445. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2446. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2447. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2448. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2449. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2450. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2451. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2452. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2453. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2454. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2455. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2456. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2457. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2458. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2459. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2460. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2461. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2462. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2463. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2464. &peer->stats, ts->peer_id,
  2465. UPDATE_PEER_STATS, pdev->pdev_id);
  2466. #endif
  2467. }
  2468. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2469. /**
  2470. * dp_tx_flow_pool_lock() - take flow pool lock
  2471. * @soc: core txrx main context
  2472. * @tx_desc: tx desc
  2473. *
  2474. * Return: None
  2475. */
  2476. static inline
  2477. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2478. struct dp_tx_desc_s *tx_desc)
  2479. {
  2480. struct dp_tx_desc_pool_s *pool;
  2481. uint8_t desc_pool_id;
  2482. desc_pool_id = tx_desc->pool_id;
  2483. pool = &soc->tx_desc[desc_pool_id];
  2484. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2485. }
  2486. /**
  2487. * dp_tx_flow_pool_unlock() - release flow pool lock
  2488. * @soc: core txrx main context
  2489. * @tx_desc: tx desc
  2490. *
  2491. * Return: None
  2492. */
  2493. static inline
  2494. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2495. struct dp_tx_desc_s *tx_desc)
  2496. {
  2497. struct dp_tx_desc_pool_s *pool;
  2498. uint8_t desc_pool_id;
  2499. desc_pool_id = tx_desc->pool_id;
  2500. pool = &soc->tx_desc[desc_pool_id];
  2501. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2502. }
  2503. #else
  2504. static inline
  2505. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2506. {
  2507. }
  2508. static inline
  2509. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2510. {
  2511. }
  2512. #endif
  2513. /**
  2514. * dp_tx_notify_completion() - Notify tx completion for this desc
  2515. * @soc: core txrx main context
  2516. * @tx_desc: tx desc
  2517. * @netbuf: buffer
  2518. *
  2519. * Return: none
  2520. */
  2521. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2522. struct dp_tx_desc_s *tx_desc,
  2523. qdf_nbuf_t netbuf)
  2524. {
  2525. void *osif_dev;
  2526. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2527. qdf_assert(tx_desc);
  2528. dp_tx_flow_pool_lock(soc, tx_desc);
  2529. if (!tx_desc->vdev ||
  2530. !tx_desc->vdev->osif_vdev) {
  2531. dp_tx_flow_pool_unlock(soc, tx_desc);
  2532. return;
  2533. }
  2534. osif_dev = tx_desc->vdev->osif_vdev;
  2535. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2536. dp_tx_flow_pool_unlock(soc, tx_desc);
  2537. if (tx_compl_cbk)
  2538. tx_compl_cbk(netbuf, osif_dev);
  2539. }
  2540. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2541. * @pdev: pdev handle
  2542. * @tid: tid value
  2543. * @txdesc_ts: timestamp from txdesc
  2544. * @ppdu_id: ppdu id
  2545. *
  2546. * Return: none
  2547. */
  2548. #ifdef FEATURE_PERPKT_INFO
  2549. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2550. struct dp_peer *peer,
  2551. uint8_t tid,
  2552. uint64_t txdesc_ts,
  2553. uint32_t ppdu_id)
  2554. {
  2555. uint64_t delta_ms;
  2556. struct cdp_tx_sojourn_stats *sojourn_stats;
  2557. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2558. return;
  2559. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2560. tid >= CDP_DATA_TID_MAX))
  2561. return;
  2562. if (qdf_unlikely(!pdev->sojourn_buf))
  2563. return;
  2564. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2565. qdf_nbuf_data(pdev->sojourn_buf);
  2566. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2567. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2568. txdesc_ts;
  2569. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2570. delta_ms);
  2571. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2572. sojourn_stats->num_msdus[tid] = 1;
  2573. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2574. peer->avg_sojourn_msdu[tid].internal;
  2575. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2576. pdev->sojourn_buf, HTT_INVALID_PEER,
  2577. WDI_NO_VAL, pdev->pdev_id);
  2578. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2579. sojourn_stats->num_msdus[tid] = 0;
  2580. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2581. }
  2582. #else
  2583. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2584. uint8_t tid,
  2585. uint64_t txdesc_ts,
  2586. uint32_t ppdu_id)
  2587. {
  2588. }
  2589. #endif
  2590. /**
  2591. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2592. * @soc: DP Soc handle
  2593. * @tx_desc: software Tx descriptor
  2594. * @ts : Tx completion status from HAL/HTT descriptor
  2595. *
  2596. * Return: none
  2597. */
  2598. static inline void
  2599. dp_tx_comp_process_desc(struct dp_soc *soc,
  2600. struct dp_tx_desc_s *desc,
  2601. struct hal_tx_completion_status *ts,
  2602. struct dp_peer *peer)
  2603. {
  2604. uint64_t time_latency = 0;
  2605. /*
  2606. * m_copy/tx_capture modes are not supported for
  2607. * scatter gather packets
  2608. */
  2609. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2610. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2611. desc->timestamp);
  2612. }
  2613. if (!(desc->msdu_ext_desc)) {
  2614. if (QDF_STATUS_SUCCESS ==
  2615. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2616. return;
  2617. }
  2618. if (QDF_STATUS_SUCCESS ==
  2619. dp_get_completion_indication_for_stack(soc,
  2620. desc->pdev,
  2621. peer, ts,
  2622. desc->nbuf,
  2623. time_latency)) {
  2624. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2625. QDF_DMA_TO_DEVICE);
  2626. dp_send_completion_to_stack(soc,
  2627. desc->pdev,
  2628. ts->peer_id,
  2629. ts->ppdu_id,
  2630. desc->nbuf);
  2631. return;
  2632. }
  2633. }
  2634. dp_tx_comp_free_buf(soc, desc);
  2635. }
  2636. /**
  2637. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2638. * @tx_desc: software descriptor head pointer
  2639. * @ts: Tx completion status
  2640. * @peer: peer handle
  2641. * @ring_id: ring number
  2642. *
  2643. * Return: none
  2644. */
  2645. static inline
  2646. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2647. struct hal_tx_completion_status *ts,
  2648. struct dp_peer *peer, uint8_t ring_id)
  2649. {
  2650. uint32_t length;
  2651. qdf_ether_header_t *eh;
  2652. struct dp_soc *soc = NULL;
  2653. struct dp_vdev *vdev = tx_desc->vdev;
  2654. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2655. if (!vdev || !nbuf) {
  2656. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2657. "invalid tx descriptor. vdev or nbuf NULL");
  2658. goto out;
  2659. }
  2660. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2661. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2662. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2663. QDF_TRACE_DEFAULT_PDEV_ID,
  2664. qdf_nbuf_data_addr(nbuf),
  2665. sizeof(qdf_nbuf_data(nbuf)),
  2666. tx_desc->id,
  2667. ts->status));
  2668. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2669. "-------------------- \n"
  2670. "Tx Completion Stats: \n"
  2671. "-------------------- \n"
  2672. "ack_frame_rssi = %d \n"
  2673. "first_msdu = %d \n"
  2674. "last_msdu = %d \n"
  2675. "msdu_part_of_amsdu = %d \n"
  2676. "rate_stats valid = %d \n"
  2677. "bw = %d \n"
  2678. "pkt_type = %d \n"
  2679. "stbc = %d \n"
  2680. "ldpc = %d \n"
  2681. "sgi = %d \n"
  2682. "mcs = %d \n"
  2683. "ofdma = %d \n"
  2684. "tones_in_ru = %d \n"
  2685. "tsf = %d \n"
  2686. "ppdu_id = %d \n"
  2687. "transmit_cnt = %d \n"
  2688. "tid = %d \n"
  2689. "peer_id = %d\n",
  2690. ts->ack_frame_rssi, ts->first_msdu,
  2691. ts->last_msdu, ts->msdu_part_of_amsdu,
  2692. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2693. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2694. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2695. ts->transmit_cnt, ts->tid, ts->peer_id);
  2696. soc = vdev->pdev->soc;
  2697. /* Update SoC level stats */
  2698. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2699. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2700. /* Update per-packet stats for mesh mode */
  2701. if (qdf_unlikely(vdev->mesh_vdev) &&
  2702. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2703. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2704. length = qdf_nbuf_len(nbuf);
  2705. /* Update peer level stats */
  2706. if (!peer) {
  2707. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2708. "peer is null or deletion in progress");
  2709. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2710. goto out;
  2711. }
  2712. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2713. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2714. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2715. if ((peer->vdev->tx_encap_type ==
  2716. htt_cmn_pkt_type_ethernet) &&
  2717. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2718. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2719. }
  2720. }
  2721. } else {
  2722. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2723. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2724. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2725. }
  2726. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2727. #ifdef QCA_SUPPORT_RDK_STATS
  2728. if (soc->wlanstats_enabled)
  2729. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2730. tx_desc->timestamp,
  2731. ts->ppdu_id);
  2732. #endif
  2733. out:
  2734. return;
  2735. }
  2736. /**
  2737. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2738. * @soc: core txrx main context
  2739. * @comp_head: software descriptor head pointer
  2740. * @ring_id: ring number
  2741. *
  2742. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2743. * and release the software descriptors after processing is complete
  2744. *
  2745. * Return: none
  2746. */
  2747. static void
  2748. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2749. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2750. {
  2751. struct dp_tx_desc_s *desc;
  2752. struct dp_tx_desc_s *next;
  2753. struct hal_tx_completion_status ts = {0};
  2754. struct dp_peer *peer;
  2755. qdf_nbuf_t netbuf;
  2756. desc = comp_head;
  2757. while (desc) {
  2758. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2759. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2760. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2761. netbuf = desc->nbuf;
  2762. /* check tx complete notification */
  2763. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2764. dp_tx_notify_completion(soc, desc, netbuf);
  2765. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2766. if (peer)
  2767. dp_peer_unref_del_find_by_id(peer);
  2768. next = desc->next;
  2769. dp_tx_desc_release(desc, desc->pool_id);
  2770. desc = next;
  2771. }
  2772. }
  2773. /**
  2774. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2775. * @tx_desc: software descriptor head pointer
  2776. * @status : Tx completion status from HTT descriptor
  2777. * @ring_id: ring number
  2778. *
  2779. * This function will process HTT Tx indication messages from Target
  2780. *
  2781. * Return: none
  2782. */
  2783. static
  2784. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2785. uint8_t ring_id)
  2786. {
  2787. uint8_t tx_status;
  2788. struct dp_pdev *pdev;
  2789. struct dp_vdev *vdev;
  2790. struct dp_soc *soc;
  2791. struct hal_tx_completion_status ts = {0};
  2792. uint32_t *htt_desc = (uint32_t *)status;
  2793. struct dp_peer *peer;
  2794. struct cdp_tid_tx_stats *tid_stats = NULL;
  2795. struct htt_soc *htt_handle;
  2796. qdf_assert(tx_desc->pdev);
  2797. pdev = tx_desc->pdev;
  2798. vdev = tx_desc->vdev;
  2799. soc = pdev->soc;
  2800. if (!vdev)
  2801. return;
  2802. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2803. htt_handle = (struct htt_soc *)soc->htt_handle;
  2804. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2805. switch (tx_status) {
  2806. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2807. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2808. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2809. {
  2810. uint8_t tid;
  2811. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2812. ts.peer_id =
  2813. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2814. htt_desc[2]);
  2815. ts.tid =
  2816. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2817. htt_desc[2]);
  2818. } else {
  2819. ts.peer_id = HTT_INVALID_PEER;
  2820. ts.tid = HTT_INVALID_TID;
  2821. }
  2822. ts.ppdu_id =
  2823. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2824. htt_desc[1]);
  2825. ts.ack_frame_rssi =
  2826. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2827. htt_desc[1]);
  2828. ts.first_msdu = 1;
  2829. ts.last_msdu = 1;
  2830. tid = ts.tid;
  2831. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2832. tid = CDP_MAX_DATA_TIDS - 1;
  2833. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2834. if (qdf_unlikely(pdev->delay_stats_flag))
  2835. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2836. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2837. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2838. tid_stats->comp_fail_cnt++;
  2839. } else {
  2840. tid_stats->success_cnt++;
  2841. }
  2842. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2843. if (qdf_likely(peer))
  2844. dp_peer_unref_del_find_by_id(peer);
  2845. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2846. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2847. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2848. break;
  2849. }
  2850. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2851. {
  2852. dp_tx_reinject_handler(tx_desc, status);
  2853. break;
  2854. }
  2855. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2856. {
  2857. dp_tx_inspect_handler(tx_desc, status);
  2858. break;
  2859. }
  2860. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2861. {
  2862. dp_tx_mec_handler(vdev, status);
  2863. break;
  2864. }
  2865. default:
  2866. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2867. "%s Invalid HTT tx_status %d\n",
  2868. __func__, tx_status);
  2869. break;
  2870. }
  2871. }
  2872. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2873. static inline
  2874. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2875. {
  2876. bool limit_hit = false;
  2877. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2878. limit_hit =
  2879. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2880. if (limit_hit)
  2881. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2882. return limit_hit;
  2883. }
  2884. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2885. {
  2886. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2887. }
  2888. #else
  2889. static inline
  2890. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2891. {
  2892. return false;
  2893. }
  2894. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2895. {
  2896. return false;
  2897. }
  2898. #endif
  2899. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2900. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  2901. uint32_t quota)
  2902. {
  2903. void *tx_comp_hal_desc;
  2904. uint8_t buffer_src;
  2905. uint8_t pool_id;
  2906. uint32_t tx_desc_id;
  2907. struct dp_tx_desc_s *tx_desc = NULL;
  2908. struct dp_tx_desc_s *head_desc = NULL;
  2909. struct dp_tx_desc_s *tail_desc = NULL;
  2910. uint32_t num_processed = 0;
  2911. uint32_t count = 0;
  2912. bool force_break = false;
  2913. DP_HIST_INIT();
  2914. more_data:
  2915. /* Re-initialize local variables to be re-used */
  2916. head_desc = NULL;
  2917. tail_desc = NULL;
  2918. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  2919. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2920. "%s %d : HAL RING Access Failed -- %pK",
  2921. __func__, __LINE__, hal_ring_hdl);
  2922. return 0;
  2923. }
  2924. /* Find head descriptor from completion ring */
  2925. while (qdf_likely(tx_comp_hal_desc =
  2926. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  2927. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2928. /* If this buffer was not released by TQM or FW, then it is not
  2929. * Tx completion indication, assert */
  2930. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2931. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2932. QDF_TRACE(QDF_MODULE_ID_DP,
  2933. QDF_TRACE_LEVEL_FATAL,
  2934. "Tx comp release_src != TQM | FW but from %d",
  2935. buffer_src);
  2936. hal_dump_comp_desc(tx_comp_hal_desc);
  2937. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2938. qdf_assert_always(0);
  2939. }
  2940. /* Get descriptor id */
  2941. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2942. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2943. DP_TX_DESC_ID_POOL_OS;
  2944. /* Find Tx descriptor */
  2945. tx_desc = dp_tx_desc_find(soc, pool_id,
  2946. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2947. DP_TX_DESC_ID_PAGE_OS,
  2948. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2949. DP_TX_DESC_ID_OFFSET_OS);
  2950. /*
  2951. * If the descriptor is already freed in vdev_detach,
  2952. * continue to next descriptor
  2953. */
  2954. if (!tx_desc->vdev && !tx_desc->flags) {
  2955. QDF_TRACE(QDF_MODULE_ID_DP,
  2956. QDF_TRACE_LEVEL_INFO,
  2957. "Descriptor freed in vdev_detach %d",
  2958. tx_desc_id);
  2959. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2960. count++;
  2961. continue;
  2962. }
  2963. /*
  2964. * If the release source is FW, process the HTT status
  2965. */
  2966. if (qdf_unlikely(buffer_src ==
  2967. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2968. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2969. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2970. htt_tx_status);
  2971. dp_tx_process_htt_completion(tx_desc,
  2972. htt_tx_status, ring_id);
  2973. } else {
  2974. /* Pool id is not matching. Error */
  2975. if (tx_desc->pool_id != pool_id) {
  2976. QDF_TRACE(QDF_MODULE_ID_DP,
  2977. QDF_TRACE_LEVEL_FATAL,
  2978. "Tx Comp pool id %d not matched %d",
  2979. pool_id, tx_desc->pool_id);
  2980. qdf_assert_always(0);
  2981. }
  2982. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2983. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2984. QDF_TRACE(QDF_MODULE_ID_DP,
  2985. QDF_TRACE_LEVEL_FATAL,
  2986. "Txdesc invalid, flgs = %x,id = %d",
  2987. tx_desc->flags, tx_desc_id);
  2988. qdf_assert_always(0);
  2989. }
  2990. /* First ring descriptor on the cycle */
  2991. if (!head_desc) {
  2992. head_desc = tx_desc;
  2993. tail_desc = tx_desc;
  2994. }
  2995. tail_desc->next = tx_desc;
  2996. tx_desc->next = NULL;
  2997. tail_desc = tx_desc;
  2998. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  2999. /* Collect hw completion contents */
  3000. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3001. &tx_desc->comp, 1);
  3002. }
  3003. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3004. /*
  3005. * Processed packet count is more than given quota
  3006. * stop to processing
  3007. */
  3008. if (num_processed >= quota) {
  3009. force_break = true;
  3010. break;
  3011. }
  3012. count++;
  3013. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3014. break;
  3015. }
  3016. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3017. /* Process the reaped descriptors */
  3018. if (head_desc)
  3019. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3020. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3021. if (!force_break &&
  3022. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3023. hal_ring_hdl)) {
  3024. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3025. if (!hif_exec_should_yield(soc->hif_handle,
  3026. int_ctx->dp_intr_id))
  3027. goto more_data;
  3028. }
  3029. }
  3030. DP_TX_HIST_STATS_PER_PDEV();
  3031. return num_processed;
  3032. }
  3033. #ifdef FEATURE_WLAN_TDLS
  3034. /**
  3035. * dp_tx_non_std() - Allow the control-path SW to send data frames
  3036. *
  3037. * @data_vdev - which vdev should transmit the tx data frames
  3038. * @tx_spec - what non-standard handling to apply to the tx data frames
  3039. * @msdu_list - NULL-terminated list of tx MSDUs
  3040. *
  3041. * Return: NULL on success,
  3042. * nbuf when it fails to send
  3043. */
  3044. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  3045. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3046. {
  3047. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3048. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3049. vdev->is_tdls_frame = true;
  3050. return dp_tx_send(vdev_handle, msdu_list);
  3051. }
  3052. #endif
  3053. /**
  3054. * dp_tx_vdev_attach() - attach vdev to dp tx
  3055. * @vdev: virtual device instance
  3056. *
  3057. * Return: QDF_STATUS_SUCCESS: success
  3058. * QDF_STATUS_E_RESOURCES: Error return
  3059. */
  3060. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3061. {
  3062. /*
  3063. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3064. */
  3065. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3066. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3067. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3068. vdev->vdev_id);
  3069. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3070. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3071. /*
  3072. * Set HTT Extension Valid bit to 0 by default
  3073. */
  3074. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3075. dp_tx_vdev_update_search_flags(vdev);
  3076. return QDF_STATUS_SUCCESS;
  3077. }
  3078. #ifndef FEATURE_WDS
  3079. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3080. {
  3081. return false;
  3082. }
  3083. #endif
  3084. /**
  3085. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3086. * @vdev: virtual device instance
  3087. *
  3088. * Return: void
  3089. *
  3090. */
  3091. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3092. {
  3093. struct dp_soc *soc = vdev->pdev->soc;
  3094. /*
  3095. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3096. * for TDLS link
  3097. *
  3098. * Enable AddrY (SA based search) only for non-WDS STA and
  3099. * ProxySTA VAP (in HKv1) modes.
  3100. *
  3101. * In all other VAP modes, only DA based search should be
  3102. * enabled
  3103. */
  3104. if (vdev->opmode == wlan_op_mode_sta &&
  3105. vdev->tdls_link_connected)
  3106. vdev->hal_desc_addr_search_flags =
  3107. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3108. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3109. !dp_tx_da_search_override(vdev))
  3110. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3111. else
  3112. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3113. /* Set search type only when peer map v2 messaging is enabled
  3114. * as we will have the search index (AST hash) only when v2 is
  3115. * enabled
  3116. */
  3117. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3118. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3119. else
  3120. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3121. }
  3122. static inline bool
  3123. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3124. struct dp_vdev *vdev,
  3125. struct dp_tx_desc_s *tx_desc)
  3126. {
  3127. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3128. return false;
  3129. /*
  3130. * if vdev is given, then only check whether desc
  3131. * vdev match. if vdev is NULL, then check whether
  3132. * desc pdev match.
  3133. */
  3134. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3135. }
  3136. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3137. /**
  3138. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3139. *
  3140. * @soc: Handle to DP SoC structure
  3141. * @tx_desc: pointer of one TX desc
  3142. * @desc_pool_id: TX Desc pool id
  3143. */
  3144. static inline void
  3145. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3146. uint8_t desc_pool_id)
  3147. {
  3148. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3149. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3150. tx_desc->vdev = NULL;
  3151. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3152. }
  3153. /**
  3154. * dp_tx_desc_flush() - release resources associated
  3155. * to TX Desc
  3156. *
  3157. * @dp_pdev: Handle to DP pdev structure
  3158. * @vdev: virtual device instance
  3159. * NULL: no specific Vdev is required and check all allcated TX desc
  3160. * on this pdev.
  3161. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3162. *
  3163. * @force_free:
  3164. * true: flush the TX desc.
  3165. * false: only reset the Vdev in each allocated TX desc
  3166. * that associated to current Vdev.
  3167. *
  3168. * This function will go through the TX desc pool to flush
  3169. * the outstanding TX data or reset Vdev to NULL in associated TX
  3170. * Desc.
  3171. */
  3172. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3173. struct dp_vdev *vdev,
  3174. bool force_free)
  3175. {
  3176. uint8_t i;
  3177. uint32_t j;
  3178. uint32_t num_desc, page_id, offset;
  3179. uint16_t num_desc_per_page;
  3180. struct dp_soc *soc = pdev->soc;
  3181. struct dp_tx_desc_s *tx_desc = NULL;
  3182. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3183. if (!vdev && !force_free) {
  3184. dp_err("Reset TX desc vdev, Vdev param is required!");
  3185. return;
  3186. }
  3187. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3188. tx_desc_pool = &soc->tx_desc[i];
  3189. if (!(tx_desc_pool->pool_size) ||
  3190. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3191. !(tx_desc_pool->desc_pages.cacheable_pages))
  3192. continue;
  3193. num_desc = tx_desc_pool->pool_size;
  3194. num_desc_per_page =
  3195. tx_desc_pool->desc_pages.num_element_per_page;
  3196. for (j = 0; j < num_desc; j++) {
  3197. page_id = j / num_desc_per_page;
  3198. offset = j % num_desc_per_page;
  3199. if (qdf_unlikely(!(tx_desc_pool->
  3200. desc_pages.cacheable_pages)))
  3201. break;
  3202. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3203. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3204. /*
  3205. * Free TX desc if force free is
  3206. * required, otherwise only reset vdev
  3207. * in this TX desc.
  3208. */
  3209. if (force_free) {
  3210. dp_tx_comp_free_buf(soc, tx_desc);
  3211. dp_tx_desc_release(tx_desc, i);
  3212. } else {
  3213. dp_tx_desc_reset_vdev(soc, tx_desc,
  3214. i);
  3215. }
  3216. }
  3217. }
  3218. }
  3219. }
  3220. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3221. static inline void
  3222. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3223. uint8_t desc_pool_id)
  3224. {
  3225. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3226. tx_desc->vdev = NULL;
  3227. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3228. }
  3229. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3230. struct dp_vdev *vdev,
  3231. bool force_free)
  3232. {
  3233. uint8_t i, num_pool;
  3234. uint32_t j;
  3235. uint32_t num_desc, page_id, offset;
  3236. uint16_t num_desc_per_page;
  3237. struct dp_soc *soc = pdev->soc;
  3238. struct dp_tx_desc_s *tx_desc = NULL;
  3239. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3240. if (!vdev && !force_free) {
  3241. dp_err("Reset TX desc vdev, Vdev param is required!");
  3242. return;
  3243. }
  3244. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3245. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3246. for (i = 0; i < num_pool; i++) {
  3247. tx_desc_pool = &soc->tx_desc[i];
  3248. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3249. continue;
  3250. num_desc_per_page =
  3251. tx_desc_pool->desc_pages.num_element_per_page;
  3252. for (j = 0; j < num_desc; j++) {
  3253. page_id = j / num_desc_per_page;
  3254. offset = j % num_desc_per_page;
  3255. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3256. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3257. if (force_free) {
  3258. dp_tx_comp_free_buf(soc, tx_desc);
  3259. dp_tx_desc_release(tx_desc, i);
  3260. } else {
  3261. dp_tx_desc_reset_vdev(soc, tx_desc,
  3262. i);
  3263. }
  3264. }
  3265. }
  3266. }
  3267. }
  3268. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3269. /**
  3270. * dp_tx_vdev_detach() - detach vdev from dp tx
  3271. * @vdev: virtual device instance
  3272. *
  3273. * Return: QDF_STATUS_SUCCESS: success
  3274. * QDF_STATUS_E_RESOURCES: Error return
  3275. */
  3276. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3277. {
  3278. struct dp_pdev *pdev = vdev->pdev;
  3279. /* Reset TX desc associated to this Vdev as NULL */
  3280. dp_tx_desc_flush(pdev, vdev, false);
  3281. return QDF_STATUS_SUCCESS;
  3282. }
  3283. /**
  3284. * dp_tx_pdev_attach() - attach pdev to dp tx
  3285. * @pdev: physical device instance
  3286. *
  3287. * Return: QDF_STATUS_SUCCESS: success
  3288. * QDF_STATUS_E_RESOURCES: Error return
  3289. */
  3290. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3291. {
  3292. struct dp_soc *soc = pdev->soc;
  3293. /* Initialize Flow control counters */
  3294. qdf_atomic_init(&pdev->num_tx_exception);
  3295. qdf_atomic_init(&pdev->num_tx_outstanding);
  3296. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3297. /* Initialize descriptors in TCL Ring */
  3298. hal_tx_init_data_ring(soc->hal_soc,
  3299. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3300. }
  3301. return QDF_STATUS_SUCCESS;
  3302. }
  3303. /**
  3304. * dp_tx_pdev_detach() - detach pdev from dp tx
  3305. * @pdev: physical device instance
  3306. *
  3307. * Return: QDF_STATUS_SUCCESS: success
  3308. * QDF_STATUS_E_RESOURCES: Error return
  3309. */
  3310. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3311. {
  3312. /* flush TX outstanding data per pdev */
  3313. dp_tx_desc_flush(pdev, NULL, true);
  3314. dp_tx_me_exit(pdev);
  3315. return QDF_STATUS_SUCCESS;
  3316. }
  3317. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3318. /* Pools will be allocated dynamically */
  3319. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3320. int num_desc)
  3321. {
  3322. uint8_t i;
  3323. for (i = 0; i < num_pool; i++) {
  3324. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3325. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3326. }
  3327. return 0;
  3328. }
  3329. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3330. {
  3331. uint8_t i;
  3332. for (i = 0; i < num_pool; i++)
  3333. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3334. }
  3335. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3336. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3337. int num_desc)
  3338. {
  3339. uint8_t i;
  3340. /* Allocate software Tx descriptor pools */
  3341. for (i = 0; i < num_pool; i++) {
  3342. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3343. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3344. "%s Tx Desc Pool alloc %d failed %pK",
  3345. __func__, i, soc);
  3346. return ENOMEM;
  3347. }
  3348. }
  3349. return 0;
  3350. }
  3351. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3352. {
  3353. uint8_t i;
  3354. for (i = 0; i < num_pool; i++) {
  3355. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3356. if (dp_tx_desc_pool_free(soc, i)) {
  3357. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3358. "%s Tx Desc Pool Free failed", __func__);
  3359. }
  3360. }
  3361. }
  3362. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3363. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3364. /**
  3365. * dp_tso_attach_wifi3() - TSO attach handler
  3366. * @txrx_soc: Opaque Dp handle
  3367. *
  3368. * Reserve TSO descriptor buffers
  3369. *
  3370. * Return: QDF_STATUS_E_FAILURE on failure or
  3371. * QDF_STATUS_SUCCESS on success
  3372. */
  3373. static
  3374. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3375. {
  3376. return dp_tso_soc_attach(txrx_soc);
  3377. }
  3378. /**
  3379. * dp_tso_detach_wifi3() - TSO Detach handler
  3380. * @txrx_soc: Opaque Dp handle
  3381. *
  3382. * Deallocate TSO descriptor buffers
  3383. *
  3384. * Return: QDF_STATUS_E_FAILURE on failure or
  3385. * QDF_STATUS_SUCCESS on success
  3386. */
  3387. static
  3388. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3389. {
  3390. return dp_tso_soc_detach(txrx_soc);
  3391. }
  3392. #else
  3393. static
  3394. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3395. {
  3396. return QDF_STATUS_SUCCESS;
  3397. }
  3398. static
  3399. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3400. {
  3401. return QDF_STATUS_SUCCESS;
  3402. }
  3403. #endif
  3404. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3405. {
  3406. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3407. uint8_t i;
  3408. uint8_t num_pool;
  3409. uint32_t num_desc;
  3410. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3411. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3412. for (i = 0; i < num_pool; i++)
  3413. dp_tx_tso_desc_pool_free(soc, i);
  3414. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3415. __func__, num_pool, num_desc);
  3416. for (i = 0; i < num_pool; i++)
  3417. dp_tx_tso_num_seg_pool_free(soc, i);
  3418. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3419. __func__, num_pool, num_desc);
  3420. return QDF_STATUS_SUCCESS;
  3421. }
  3422. /**
  3423. * dp_tso_attach() - TSO attach handler
  3424. * @txrx_soc: Opaque Dp handle
  3425. *
  3426. * Reserve TSO descriptor buffers
  3427. *
  3428. * Return: QDF_STATUS_E_FAILURE on failure or
  3429. * QDF_STATUS_SUCCESS on success
  3430. */
  3431. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3432. {
  3433. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3434. uint8_t i;
  3435. uint8_t num_pool;
  3436. uint32_t num_desc;
  3437. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3438. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3439. for (i = 0; i < num_pool; i++) {
  3440. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3441. dp_err("TSO Desc Pool alloc %d failed %pK",
  3442. i, soc);
  3443. return QDF_STATUS_E_FAILURE;
  3444. }
  3445. }
  3446. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3447. __func__, num_pool, num_desc);
  3448. for (i = 0; i < num_pool; i++) {
  3449. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3450. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3451. i, soc);
  3452. return QDF_STATUS_E_FAILURE;
  3453. }
  3454. }
  3455. return QDF_STATUS_SUCCESS;
  3456. }
  3457. /**
  3458. * dp_tx_soc_detach() - detach soc from dp tx
  3459. * @soc: core txrx main context
  3460. *
  3461. * This function will detach dp tx into main device context
  3462. * will free dp tx resource and initialize resources
  3463. *
  3464. * Return: QDF_STATUS_SUCCESS: success
  3465. * QDF_STATUS_E_RESOURCES: Error return
  3466. */
  3467. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3468. {
  3469. uint8_t num_pool;
  3470. uint16_t num_desc;
  3471. uint16_t num_ext_desc;
  3472. uint8_t i;
  3473. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3474. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3475. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3476. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3477. dp_tx_flow_control_deinit(soc);
  3478. dp_tx_delete_static_pools(soc, num_pool);
  3479. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3480. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3481. __func__, num_pool, num_desc);
  3482. for (i = 0; i < num_pool; i++) {
  3483. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3484. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3485. "%s Tx Ext Desc Pool Free failed",
  3486. __func__);
  3487. return QDF_STATUS_E_RESOURCES;
  3488. }
  3489. }
  3490. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3491. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3492. __func__, num_pool, num_ext_desc);
  3493. status = dp_tso_detach_wifi3(soc);
  3494. if (status != QDF_STATUS_SUCCESS)
  3495. return status;
  3496. return QDF_STATUS_SUCCESS;
  3497. }
  3498. /**
  3499. * dp_tx_soc_attach() - attach soc to dp tx
  3500. * @soc: core txrx main context
  3501. *
  3502. * This function will attach dp tx into main device context
  3503. * will allocate dp tx resource and initialize resources
  3504. *
  3505. * Return: QDF_STATUS_SUCCESS: success
  3506. * QDF_STATUS_E_RESOURCES: Error return
  3507. */
  3508. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3509. {
  3510. uint8_t i;
  3511. uint8_t num_pool;
  3512. uint32_t num_desc;
  3513. uint32_t num_ext_desc;
  3514. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3515. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3516. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3517. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3518. if (num_pool > MAX_TXDESC_POOLS)
  3519. goto fail;
  3520. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3521. goto fail;
  3522. dp_tx_flow_control_init(soc);
  3523. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3524. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3525. __func__, num_pool, num_desc);
  3526. /* Allocate extension tx descriptor pools */
  3527. for (i = 0; i < num_pool; i++) {
  3528. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3529. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3530. "MSDU Ext Desc Pool alloc %d failed %pK",
  3531. i, soc);
  3532. goto fail;
  3533. }
  3534. }
  3535. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3536. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3537. __func__, num_pool, num_ext_desc);
  3538. status = dp_tso_attach_wifi3((void *)soc);
  3539. if (status != QDF_STATUS_SUCCESS)
  3540. goto fail;
  3541. /* Initialize descriptors in TCL Rings */
  3542. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3543. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3544. hal_tx_init_data_ring(soc->hal_soc,
  3545. soc->tcl_data_ring[i].hal_srng);
  3546. }
  3547. }
  3548. /*
  3549. * todo - Add a runtime config option to enable this.
  3550. */
  3551. /*
  3552. * Due to multiple issues on NPR EMU, enable it selectively
  3553. * only for NPR EMU, should be removed, once NPR platforms
  3554. * are stable.
  3555. */
  3556. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3557. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3558. "%s HAL Tx init Success", __func__);
  3559. return QDF_STATUS_SUCCESS;
  3560. fail:
  3561. /* Detach will take care of freeing only allocated resources */
  3562. dp_tx_soc_detach(soc);
  3563. return QDF_STATUS_E_RESOURCES;
  3564. }