hal_be_generic_api.h 103 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_GENERIC_API_H_
  20. #define _HAL_BE_GENERIC_API_H_
  21. #include <hal_be_hw_headers.h>
  22. #include "hal_be_tx.h"
  23. #include "hal_be_reo.h"
  24. #include <hal_api_mon.h>
  25. #include <hal_generic_api.h>
  26. #include <hal_be_api_mon.h>
  27. #include "txmon_tlvs.h"
  28. /**
  29. * Debug macro to print the TLV header tag
  30. */
  31. #define SHOW_DEFINED(x) do {} while (0)
  32. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  33. static inline void
  34. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  35. struct hal_tx_completion_status *ts)
  36. {
  37. ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  38. BUFFER_TIMESTAMP);
  39. }
  40. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */
  41. static inline void
  42. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  43. struct hal_tx_completion_status *ts)
  44. {
  45. }
  46. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */
  47. /**
  48. * hal_tx_comp_get_status() - TQM Release reason
  49. * @hal_desc: completion ring Tx status
  50. *
  51. * This function will parse the WBM completion descriptor and populate in
  52. * HAL structure
  53. *
  54. * Return: none
  55. */
  56. static inline void
  57. hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
  58. struct hal_soc *hal)
  59. {
  60. uint8_t rate_stats_valid = 0;
  61. uint32_t rate_stats = 0;
  62. struct hal_tx_completion_status *ts =
  63. (struct hal_tx_completion_status *)ts1;
  64. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  65. TQM_STATUS_NUMBER);
  66. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  67. ACK_FRAME_RSSI);
  68. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  69. FIRST_MSDU);
  70. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  71. LAST_MSDU);
  72. #if 0
  73. // TODO - This has to be calculated form first and last msdu
  74. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc,
  75. WBM2SW_COMPLETION_RING_TX,
  76. MSDU_PART_OF_AMSDU);
  77. #endif
  78. ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  79. SW_PEER_ID);
  80. ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID);
  81. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  82. TRANSMIT_COUNT);
  83. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  84. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO,
  85. TX_RATE_STATS_INFO_VALID, rate_stats);
  86. ts->valid = rate_stats_valid;
  87. if (rate_stats_valid) {
  88. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW,
  89. rate_stats);
  90. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO,
  91. TRANSMIT_PKT_TYPE, rate_stats);
  92. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO,
  93. TRANSMIT_STBC, rate_stats);
  94. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC,
  95. rate_stats);
  96. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI,
  97. rate_stats);
  98. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS,
  99. rate_stats);
  100. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION,
  101. rate_stats);
  102. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU,
  103. rate_stats);
  104. }
  105. ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc);
  106. ts->status = hal_tx_comp_get_release_reason(
  107. desc,
  108. hal_soc_to_hal_soc_handle(hal));
  109. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  110. TX_RATE_STATS_INFO_TX_RATE_STATS);
  111. hal_tx_comp_get_buffer_timestamp_be(desc, ts);
  112. }
  113. /**
  114. * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
  115. * @soc: HAL SoC context
  116. * @map: PCP-TID mapping table
  117. *
  118. * PCP are mapped to 8 TID values using TID values programmed
  119. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  120. * The mapping register has TID mapping for 8 PCP values
  121. *
  122. * Return: none
  123. */
  124. static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map)
  125. {
  126. uint32_t addr, value;
  127. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  128. MAC_TCL_REG_REG_BASE);
  129. value = (map[0] |
  130. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  131. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  132. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  133. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  134. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  135. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  136. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  137. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  138. }
  139. /**
  140. * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with
  141. * value received from user-space
  142. * @soc: HAL SoC context
  143. * @pcp: pcp value
  144. * @tid : tid value
  145. *
  146. * Return: void
  147. */
  148. static void
  149. hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc,
  150. uint8_t pcp, uint8_t tid)
  151. {
  152. uint32_t addr, value, regval;
  153. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  154. MAC_TCL_REG_REG_BASE);
  155. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  156. /* Read back previous PCP TID config and update
  157. * with new config.
  158. */
  159. regval = HAL_REG_READ(soc, addr);
  160. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  161. regval |= value;
  162. HAL_REG_WRITE(soc, addr,
  163. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  164. }
  165. /**
  166. * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority
  167. * @soc: HAL SoC context
  168. * @val: priority value
  169. *
  170. * Return: void
  171. */
  172. static
  173. void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value)
  174. {
  175. uint32_t addr;
  176. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  177. MAC_TCL_REG_REG_BASE);
  178. HAL_REG_WRITE(soc, addr,
  179. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  180. }
  181. /**
  182. * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size
  183. * @rx_pkt_tlv_size: TLV size for regular RX packets
  184. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  185. *
  186. * Return: size of rx pkt tlv before the actual data
  187. */
  188. static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size,
  189. uint16_t *rx_mon_pkt_tlv_size)
  190. {
  191. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  192. /* For now mon pkt tlv is same as rx pkt tlv */
  193. *rx_mon_pkt_tlv_size = MON_RX_PKT_TLVS_LEN;
  194. }
  195. /**
  196. * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST
  197. * @fst: Pointer to the Rx Flow Search Table
  198. * @hal_hash: HAL 5 tuple hash
  199. * @tuple_info: 5-tuple info of the flow returned to the caller
  200. *
  201. * Return: Success/Failure
  202. */
  203. static void *
  204. hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash,
  205. uint8_t *flow_tuple_info)
  206. {
  207. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  208. void *hal_fse = NULL;
  209. struct hal_flow_tuple_info *tuple_info
  210. = (struct hal_flow_tuple_info *)flow_tuple_info;
  211. hal_fse = (uint8_t *)fst->base_vaddr +
  212. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  213. if (!hal_fse || !tuple_info)
  214. return NULL;
  215. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID))
  216. return NULL;
  217. tuple_info->src_ip_127_96 =
  218. qdf_ntohl(HAL_GET_FLD(hal_fse,
  219. RX_FLOW_SEARCH_ENTRY,
  220. SRC_IP_127_96));
  221. tuple_info->src_ip_95_64 =
  222. qdf_ntohl(HAL_GET_FLD(hal_fse,
  223. RX_FLOW_SEARCH_ENTRY,
  224. SRC_IP_95_64));
  225. tuple_info->src_ip_63_32 =
  226. qdf_ntohl(HAL_GET_FLD(hal_fse,
  227. RX_FLOW_SEARCH_ENTRY,
  228. SRC_IP_63_32));
  229. tuple_info->src_ip_31_0 =
  230. qdf_ntohl(HAL_GET_FLD(hal_fse,
  231. RX_FLOW_SEARCH_ENTRY,
  232. SRC_IP_31_0));
  233. tuple_info->dest_ip_127_96 =
  234. qdf_ntohl(HAL_GET_FLD(hal_fse,
  235. RX_FLOW_SEARCH_ENTRY,
  236. DEST_IP_127_96));
  237. tuple_info->dest_ip_95_64 =
  238. qdf_ntohl(HAL_GET_FLD(hal_fse,
  239. RX_FLOW_SEARCH_ENTRY,
  240. DEST_IP_95_64));
  241. tuple_info->dest_ip_63_32 =
  242. qdf_ntohl(HAL_GET_FLD(hal_fse,
  243. RX_FLOW_SEARCH_ENTRY,
  244. DEST_IP_63_32));
  245. tuple_info->dest_ip_31_0 =
  246. qdf_ntohl(HAL_GET_FLD(hal_fse,
  247. RX_FLOW_SEARCH_ENTRY,
  248. DEST_IP_31_0));
  249. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  250. RX_FLOW_SEARCH_ENTRY,
  251. DEST_PORT);
  252. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  253. RX_FLOW_SEARCH_ENTRY,
  254. SRC_PORT);
  255. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  256. RX_FLOW_SEARCH_ENTRY,
  257. L4_PROTOCOL);
  258. return hal_fse;
  259. }
  260. /**
  261. * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST
  262. * @fst: Pointer to the Rx Flow Search Table
  263. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  264. *
  265. * Return: Success/Failure
  266. */
  267. static QDF_STATUS
  268. hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse)
  269. {
  270. uint8_t *fse = (uint8_t *)hal_rx_fse;
  271. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID))
  272. return QDF_STATUS_E_NOENT;
  273. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  274. return QDF_STATUS_SUCCESS;
  275. }
  276. /**
  277. * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST
  278. *
  279. * Return: size of each entry/flow in Rx FST
  280. */
  281. static inline uint32_t
  282. hal_rx_fst_get_fse_size_be(void)
  283. {
  284. return HAL_RX_FST_ENTRY_SIZE;
  285. }
  286. /*
  287. * TX MONITOR
  288. */
  289. #ifdef QCA_MONITOR_2_0_SUPPORT
  290. /**
  291. * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv
  292. * @tx_tlv: pointer to TLV header
  293. *
  294. * Return: bool based on tlv tag matches monitor buffer address tlv
  295. */
  296. static inline bool
  297. hal_txmon_is_mon_buf_addr_tlv_generic_be(void *tx_tlv_hdr)
  298. {
  299. uint32_t tlv_tag;
  300. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr);
  301. if (WIFIMON_BUFFER_ADDR_E == tlv_tag)
  302. return true;
  303. return false;
  304. }
  305. /**
  306. * hal_txmon_populate_packet_info_generic_be() - api to populate packet info
  307. * @tx_tlv: pointer to TLV header
  308. * @packet_info: place holder for packet info
  309. *
  310. * Return: Address to void
  311. */
  312. static inline void
  313. hal_txmon_populate_packet_info_generic_be(void *tx_tlv, void *packet_info)
  314. {
  315. struct hal_mon_packet_info *pkt_info;
  316. struct mon_buffer_addr *addr = (struct mon_buffer_addr *)tx_tlv;
  317. pkt_info = (struct hal_mon_packet_info *)packet_info;
  318. pkt_info->sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) |
  319. (addr->buffer_virt_addr_31_0));
  320. pkt_info->dma_length = addr->dma_length + 1;
  321. pkt_info->msdu_continuation = addr->msdu_continuation;
  322. pkt_info->truncated = addr->truncated;
  323. }
  324. #if defined(TX_MONITOR_WORD_MASK)
  325. /**
  326. * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv
  327. *
  328. * @tx_tlv: pointer to tx_fes_setup tlv header
  329. *
  330. * Return: number of users
  331. */
  332. static inline uint8_t
  333. hal_txmon_get_num_users(void *tx_tlv)
  334. {
  335. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  336. return tx_fes_setup->number_of_users;
  337. }
  338. /**
  339. * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv
  340. *
  341. * @tx_tlv: pointer to tx_fes_setup tlv header
  342. * @ppdu_info: pointer to hal_tx_ppdu_info
  343. *
  344. * Return: void
  345. */
  346. static inline void
  347. hal_txmon_parse_tx_fes_setup(void *tx_tlv,
  348. struct hal_tx_ppdu_info *tx_ppdu_info)
  349. {
  350. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  351. tx_ppdu_info->num_users = tx_fes_setup->number_of_users;
  352. if (tx_ppdu_info->num_users == 0)
  353. tx_ppdu_info->num_users = 1;
  354. TXMON_HAL(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id;
  355. TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id;
  356. }
  357. /**
  358. * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv
  359. *
  360. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  361. * @data_status_info: pointer to data hal_tx_status_info
  362. * @prot_status_info: pointer to protection hal_tx_status_info
  363. *
  364. * Return: void
  365. */
  366. static inline void
  367. hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv,
  368. struct hal_tx_status_info *data_status_info,
  369. struct hal_tx_status_info *prot_status_info)
  370. {
  371. }
  372. /**
  373. * hal_txmon_parse_peer_entry() - parse peer entry tlv
  374. *
  375. * @tx_tlv: pointer to peer_entry tlv header
  376. * @user_id: user_id
  377. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  378. * @tx_status_info: pointer to hal_tx_status_info
  379. *
  380. * Return: void
  381. */
  382. static inline void
  383. hal_txmon_parse_peer_entry(void *tx_tlv,
  384. uint8_t user_id,
  385. struct hal_tx_ppdu_info *tx_ppdu_info,
  386. struct hal_tx_status_info *tx_status_info)
  387. {
  388. }
  389. /**
  390. * hal_txmon_parse_queue_exten() - parse queue exten tlv
  391. *
  392. * @tx_tlv: pointer to queue exten tlv header
  393. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  394. *
  395. * Return: void
  396. */
  397. static inline void
  398. hal_txmon_parse_queue_exten(void *tx_tlv,
  399. struct hal_tx_ppdu_info *tx_ppdu_info)
  400. {
  401. }
  402. /**
  403. * hal_txmon_parse_mpdu_start() - parse mpdu start tlv
  404. *
  405. * @tx_tlv: pointer to mpdu start tlv header
  406. * @user_id: user id
  407. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  408. *
  409. * Return: void
  410. */
  411. static inline void
  412. hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id,
  413. struct hal_tx_ppdu_info *tx_ppdu_info)
  414. {
  415. }
  416. #else
  417. /**
  418. * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv
  419. *
  420. * @tx_tlv: pointer to tx_fes_setup tlv header
  421. *
  422. * Return: number of users
  423. */
  424. static inline uint8_t
  425. hal_txmon_get_num_users(void *tx_tlv)
  426. {
  427. uint8_t num_users = HAL_TX_DESC_GET_64(tx_tlv,
  428. TX_FES_SETUP, NUMBER_OF_USERS);
  429. return num_users;
  430. }
  431. /**
  432. * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv
  433. *
  434. * @tx_tlv: pointer to tx_fes_setup tlv header
  435. * @ppdu_info: pointer to hal_tx_ppdu_info
  436. *
  437. * Return: void
  438. */
  439. static inline void
  440. hal_txmon_parse_tx_fes_setup(void *tx_tlv,
  441. struct hal_tx_ppdu_info *tx_ppdu_info)
  442. {
  443. uint32_t num_users = 0;
  444. uint32_t ppdu_id = 0;
  445. num_users = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, NUMBER_OF_USERS);
  446. ppdu_id = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, SCHEDULE_ID);
  447. if (num_users == 0)
  448. num_users = 1;
  449. tx_ppdu_info->num_users = num_users;
  450. TXMON_HAL(tx_ppdu_info, ppdu_id) = ppdu_id;
  451. TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = ppdu_id;
  452. }
  453. /**
  454. * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv
  455. *
  456. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  457. * @data_status_info: pointer to data hal_tx_status_info
  458. * @prot_status_info: pointer to protection hal_tx_status_info
  459. *
  460. * Return: void
  461. */
  462. static inline void
  463. hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv,
  464. struct hal_tx_status_info *data_status_info,
  465. struct hal_tx_status_info *prot_status_info)
  466. {
  467. prot_status_info->protection_addr =
  468. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  469. USE_ADDRESS_FIELDS_FOR_PROTECTION);
  470. /* protection frame address 1 */
  471. *(uint32_t *)&prot_status_info->addr1[0] =
  472. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  473. PROTECTION_FRAME_AD1_31_0);
  474. *(uint32_t *)&prot_status_info->addr1[4] =
  475. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  476. PROTECTION_FRAME_AD1_47_32);
  477. /* protection frame address 2 */
  478. *(uint32_t *)&prot_status_info->addr2[0] =
  479. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  480. PROTECTION_FRAME_AD2_15_0);
  481. *(uint32_t *)&prot_status_info->addr2[2] =
  482. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  483. PROTECTION_FRAME_AD2_47_16);
  484. /* protection frame address 3 */
  485. *(uint32_t *)&prot_status_info->addr3[0] =
  486. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  487. PROTECTION_FRAME_AD3_31_0);
  488. *(uint32_t *)&prot_status_info->addr3[4] =
  489. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  490. PROTECTION_FRAME_AD3_47_32);
  491. /* protection frame address 4 */
  492. *(uint32_t *)&prot_status_info->addr4[0] =
  493. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  494. PROTECTION_FRAME_AD4_15_0);
  495. *(uint32_t *)&prot_status_info->addr4[2] =
  496. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  497. PROTECTION_FRAME_AD4_47_16);
  498. }
  499. /**
  500. * hal_txmon_parse_peer_entry() - parse peer entry tlv
  501. *
  502. * @tx_tlv: pointer to peer_entry tlv header
  503. * @user_id: user_id
  504. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  505. * @tx_status_info: pointer to hal_tx_status_info
  506. *
  507. * Return: void
  508. */
  509. static inline void
  510. hal_txmon_parse_peer_entry(void *tx_tlv,
  511. uint8_t user_id,
  512. struct hal_tx_ppdu_info *tx_ppdu_info,
  513. struct hal_tx_status_info *tx_status_info)
  514. {
  515. *(uint32_t *)&tx_status_info->addr1[0] =
  516. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_31_0);
  517. *(uint32_t *)&tx_status_info->addr1[4] =
  518. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_47_32);
  519. *(uint32_t *)&tx_status_info->addr2[0] =
  520. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_15_0);
  521. *(uint32_t *)&tx_status_info->addr2[2] =
  522. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_47_16);
  523. TXMON_HAL_USER(tx_ppdu_info, user_id, sw_peer_id) =
  524. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, SW_PEER_ID);
  525. }
  526. /**
  527. * hal_txmon_parse_queue_exten() - parse queue exten tlv
  528. *
  529. * @tx_tlv: pointer to queue exten tlv header
  530. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  531. *
  532. * Return: void
  533. */
  534. static inline void
  535. hal_txmon_parse_queue_exten(void *tx_tlv,
  536. struct hal_tx_ppdu_info *tx_ppdu_info)
  537. {
  538. TXMON_HAL_STATUS(tx_ppdu_info, frame_control) =
  539. HAL_TX_DESC_GET_64(tx_tlv, TX_QUEUE_EXTENSION,
  540. FRAME_CTL);
  541. TXMON_HAL_STATUS(tx_ppdu_info, frame_control_info_valid) = true;
  542. }
  543. /**
  544. * hal_txmon_parse_mpdu_start() - parse mpdu start tlv
  545. *
  546. * @tx_tlv: pointer to mpdu start tlv header
  547. * @user_id: user id
  548. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  549. *
  550. * Return: void
  551. */
  552. static inline void
  553. hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id,
  554. struct hal_tx_ppdu_info *tx_ppdu_info)
  555. {
  556. TXMON_HAL_USER(tx_ppdu_info, user_id,
  557. start_seq) = HAL_TX_DESC_GET_64(tx_tlv, TX_MPDU_START,
  558. MPDU_SEQUENCE_NUMBER);
  559. TXMON_HAL(tx_ppdu_info, cur_usr_idx) = user_id;
  560. }
  561. #endif
  562. /**
  563. * get_ru_offset_from_start_index() - api to get ru offset from ru index
  564. *
  565. * @ru_size: RU size
  566. * @start_idx: Start index
  567. *
  568. * Return: uint8_t ru allocation offset
  569. */
  570. static inline
  571. uint8_t get_ru_offset_from_start_index(uint8_t ru_size, uint8_t start_idx)
  572. {
  573. uint8_t ru_alloc_offset[HAL_MAX_DL_MU_USERS][HAL_MAX_RU_INDEX] = {
  574. {0, 0, 0, 0, 0, 0, 0},
  575. {1, 0, 0, 0, 0, 0, 0},
  576. {2, 1, 0, 0, 0, 0, 0},
  577. {3, 1, 0, 0, 0, 0, 0},
  578. {4, 0, 0, 0, 0, 0, 0},
  579. {5, 2, 1, 0, 0, 0, 0},
  580. {6, 2, 1, 0, 0, 0, 0},
  581. {7, 3, 1, 0, 0, 0, 0},
  582. {8, 3, 1, 0, 0, 0, 0},
  583. {9, 4, 2, 1, 0, 0, 0},
  584. {10, 4, 2, 1, 0, 0, 0},
  585. {11, 5, 2, 1, 0, 0, 0},
  586. {12, 5, 2, 1, 0, 0, 0},
  587. {13, 0, 0, 1, 0, 0, 0},
  588. {14, 6, 3, 1, 0, 0, 0},
  589. {15, 6, 3, 1, 0, 0, 0},
  590. {16, 7, 3, 1, 0, 0, 0},
  591. {17, 7, 3, 1, 0, 0, 0},
  592. {18, 0, 0, 0, 0, 0, 0},
  593. {19, 8, 4, 2, 1, 0, 0},
  594. {20, 8, 4, 2, 1, 0, 0},
  595. {21, 9, 4, 2, 1, 0, 0},
  596. {22, 9, 4, 2, 1, 0, 0},
  597. {23, 0, 0, 2, 1, 0, 0},
  598. {24, 10, 5, 2, 1, 0, 0},
  599. {25, 10, 5, 2, 1, 0, 0},
  600. {26, 11, 5, 2, 1, 0, 0},
  601. {27, 11, 5, 2, 1, 0, 0},
  602. {28, 12, 6, 3, 1, 0, 0},
  603. {29, 12, 6, 3, 1, 0, 0},
  604. {30, 13, 6, 3, 1, 0, 0},
  605. {31, 13, 6, 3, 1, 0, 0},
  606. {32, 0, 0, 3, 1, 0, 0},
  607. {33, 14, 7, 3, 1, 0, 0},
  608. {34, 14, 7, 3, 1, 0, 0},
  609. {35, 15, 7, 3, 1, 0, 0},
  610. {36, 15, 7, 3, 1, 0, 0},
  611. };
  612. if (start_idx >= HAL_MAX_UL_MU_USERS || ru_size >= HAL_MAX_RU_INDEX)
  613. return 0;
  614. return ru_alloc_offset[start_idx][ru_size];
  615. }
  616. /**
  617. * hal_txmon_parse_fw2sw() - parse firmware to software tlv
  618. *
  619. * @tx_tlv: pointer to firmware to software tlvmpdu start tlv header
  620. * @type: place where this tlv is generated
  621. * @tx_status_info: pointer to hal_tx_status_info
  622. *
  623. * Return: void
  624. */
  625. static inline void
  626. hal_txmon_parse_fw2sw(void *tx_tlv, uint8_t type,
  627. struct hal_tx_status_info *status_info)
  628. {
  629. uint32_t *msg = (uint32_t *)tx_tlv;
  630. switch (type) {
  631. case TXMON_FW2SW_TYPE_FES_SETUP:
  632. {
  633. uint32_t schedule_id;
  634. uint16_t c_freq1;
  635. uint16_t c_freq2;
  636. uint16_t freq_mhz;
  637. uint8_t phy_mode;
  638. c_freq1 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_GET(*msg);
  639. c_freq2 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_GET(*msg);
  640. msg++;
  641. phy_mode = TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_GET(*msg);
  642. freq_mhz = TXMON_FW2SW_MON_FES_SETUP_MHZ_GET(*msg);
  643. msg++;
  644. schedule_id = TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_GET(*msg);
  645. TXMON_STATUS_INFO(status_info, band_center_freq1) = c_freq1;
  646. TXMON_STATUS_INFO(status_info, band_center_freq2) = c_freq2;
  647. TXMON_STATUS_INFO(status_info, freq) = freq_mhz;
  648. TXMON_STATUS_INFO(status_info, phy_mode) = phy_mode;
  649. TXMON_STATUS_INFO(status_info, schedule_id) = schedule_id;
  650. break;
  651. }
  652. case TXMON_FW2SW_TYPE_FES_SETUP_USER:
  653. {
  654. break;
  655. }
  656. case TXMON_FW2SW_TYPE_FES_SETUP_EXT:
  657. {
  658. break;
  659. }
  660. };
  661. }
  662. /**
  663. * hal_txmon_status_get_num_users_generic_be() - api to get num users
  664. * from start of fes window
  665. *
  666. * @tx_tlv_hdr: pointer to TLV header
  667. * @num_users: reference to number of user
  668. *
  669. * Return: status
  670. */
  671. static inline uint32_t
  672. hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users)
  673. {
  674. uint32_t tlv_tag, user_id, tlv_len;
  675. uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  676. void *tx_tlv;
  677. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr);
  678. user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr);
  679. tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr);
  680. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  681. /* window starts with either initiator or response */
  682. switch (tlv_tag) {
  683. case WIFITX_FES_SETUP_E:
  684. {
  685. *num_users = hal_txmon_get_num_users(tx_tlv);
  686. if (*num_users == 0)
  687. *num_users = 1;
  688. tlv_status = HAL_MON_TX_FES_SETUP;
  689. break;
  690. }
  691. case WIFIRX_RESPONSE_REQUIRED_INFO_E:
  692. {
  693. *num_users = HAL_TX_DESC_GET_64(tx_tlv,
  694. RX_RESPONSE_REQUIRED_INFO,
  695. RESPONSE_STA_COUNT);
  696. if (*num_users == 0)
  697. *num_users = 1;
  698. tlv_status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  699. break;
  700. }
  701. };
  702. return tlv_status;
  703. }
  704. /**
  705. * hal_tx_get_ppdu_info() - api to get tx ppdu info
  706. * @pdev_handle: DP_PDEV handle
  707. * @prot_ppdu_info: populate dp_ppdu_info protection
  708. * @tx_data_ppdu_info: populate dp_ppdu_info data
  709. * @tlv_tag: Tag
  710. *
  711. * Return: dp_tx_ppdu_info pointer
  712. */
  713. static inline void *
  714. hal_tx_get_ppdu_info(void *data_info, void *prot_info, uint32_t tlv_tag)
  715. {
  716. struct hal_tx_ppdu_info *prot_ppdu_info = prot_info;
  717. switch (tlv_tag) {
  718. case WIFITX_FES_SETUP_E:/* DOWNSTREAM */
  719. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  720. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */
  721. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */
  722. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */
  723. case WIFITX_MPDU_START_E:/* DOWNSTREAM */
  724. case WIFITX_MSDU_START_E:/* DOWNSTREAM */
  725. case WIFITX_DATA_E:/* DOWNSTREAM */
  726. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  727. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  728. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  729. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  730. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  731. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  732. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  733. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  734. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  735. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  736. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  737. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  738. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  739. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  740. case WIFITX_FES_STATUS_START_PPDU_E:/* UPSTREAM */
  741. {
  742. return data_info;
  743. }
  744. }
  745. /*
  746. * check current prot_tlv_status is start protection
  747. * check current tlv_tag is either start protection or end protection
  748. */
  749. if (TXMON_HAL(prot_ppdu_info,
  750. prot_tlv_status) == WIFITX_FES_STATUS_START_PROT_E) {
  751. return prot_info;
  752. } else if (tlv_tag == WIFITX_FES_STATUS_PROT_E ||
  753. tlv_tag == WIFITX_FES_STATUS_START_PROT_E) {
  754. TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag;
  755. return prot_info;
  756. }
  757. return data_info;
  758. }
  759. /**
  760. * hal_txmon_status_parse_tlv_generic_be() - api to parse status tlv.
  761. * @data_ppdu_info: hal_txmon data ppdu info
  762. * @prot_ppdu_info: hal_txmon prot ppdu info
  763. * @data_status_info: pointer to data status info
  764. * @prot_status_info: pointer to prot status info
  765. * @tx_tlv_hdr: fragment of tx_tlv_hdr
  766. * @status_frag: qdf_frag_t buffer
  767. *
  768. * Return: status
  769. */
  770. static inline uint32_t
  771. hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info,
  772. void *prot_ppdu_info,
  773. void *data_status_info,
  774. void *prot_status_info,
  775. void *tx_tlv_hdr,
  776. qdf_frag_t status_frag)
  777. {
  778. struct hal_tx_ppdu_info *ppdu_info;
  779. struct hal_tx_status_info *tx_status_info;
  780. struct hal_mon_packet_info *packet_info = NULL;
  781. uint32_t tlv_tag, user_id, tlv_len, tlv_user_id;
  782. uint32_t status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  783. void *tx_tlv;
  784. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr);
  785. tlv_user_id = HAL_RX_GET_USER_TLV64_USERID(tx_tlv_hdr);
  786. tlv_len = HAL_RX_GET_USER_TLV64_LEN(tx_tlv_hdr);
  787. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  788. /* parse tlv and populate tx_ppdu_info */
  789. ppdu_info = hal_tx_get_ppdu_info(data_ppdu_info,
  790. prot_ppdu_info, tlv_tag);
  791. tx_status_info = (ppdu_info->is_data ? data_status_info :
  792. prot_status_info);
  793. user_id = (tlv_user_id > ppdu_info->num_users ? 0 : tlv_user_id);
  794. switch (tlv_tag) {
  795. /* start of initiator FES window */
  796. case WIFITX_FES_SETUP_E:/* DOWNSTREAM */
  797. {
  798. /* initiator PPDU window start */
  799. hal_txmon_parse_tx_fes_setup(tx_tlv, ppdu_info);
  800. status = HAL_MON_TX_FES_SETUP;
  801. SHOW_DEFINED(WIFITX_FES_SETUP_E);
  802. break;
  803. }
  804. /* end of initiator FES window */
  805. case WIFITX_FES_STATUS_END_E:/* UPSTREAM */
  806. {
  807. /* initiator PPDU window end */
  808. uint32_t ppdu_timestamp_start = 0;
  809. uint32_t ppdu_timestamp_end = 0;
  810. uint16_t phy_abort_reason = 0;
  811. uint8_t phy_abort_is_valid = 0;
  812. uint8_t abort_usr_id = 0;
  813. uint8_t response_type = 0;
  814. uint8_t r2r_end_status_follow = 0;
  815. status = HAL_MON_TX_FES_STATUS_END;
  816. ppdu_timestamp_start =
  817. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  818. START_OF_FRAME_TIMESTAMP_15_0) |
  819. (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  820. START_OF_FRAME_TIMESTAMP_31_16) <<
  821. HAL_TX_LSB(TX_FES_STATUS_END,
  822. START_OF_FRAME_TIMESTAMP_31_16));
  823. ppdu_timestamp_end =
  824. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  825. END_OF_FRAME_TIMESTAMP_15_0) |
  826. (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  827. END_OF_FRAME_TIMESTAMP_31_16) <<
  828. HAL_TX_LSB(TX_FES_STATUS_END,
  829. END_OF_FRAME_TIMESTAMP_31_16));
  830. response_type = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  831. RESPONSE_TYPE);
  832. /*
  833. * r2r end status follow to inform whether to look for
  834. * rx_response_required_info
  835. */
  836. r2r_end_status_follow =
  837. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  838. R2R_END_STATUS_TO_FOLLOW);
  839. phy_abort_is_valid =
  840. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  841. PHYTX_ABORT_REQUEST_INFO_VALID);
  842. if (phy_abort_is_valid) {
  843. phy_abort_reason =
  844. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  845. PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON);
  846. abort_usr_id =
  847. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  848. PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER);
  849. TXMON_STATUS_INFO(tx_status_info,
  850. phy_abort_reason) = phy_abort_reason;
  851. TXMON_STATUS_INFO(tx_status_info,
  852. phy_abort_user_number) = abort_usr_id;
  853. }
  854. TXMON_STATUS_INFO(tx_status_info,
  855. response_type) = response_type;
  856. TXMON_STATUS_INFO(tx_status_info,
  857. r2r_to_follow) = r2r_end_status_follow;
  858. /* update phy timestamp to ppdu timestamp */
  859. TXMON_HAL_STATUS(ppdu_info,
  860. ppdu_timestamp) = ppdu_timestamp_start;
  861. SHOW_DEFINED(WIFITX_FES_STATUS_END_E);
  862. break;
  863. }
  864. /* response window open */
  865. case WIFIRX_RESPONSE_REQUIRED_INFO_E:/* UPSTREAM */
  866. {
  867. /* response PPDU window start */
  868. uint32_t ppdu_id = 0;
  869. uint8_t reception_type = 0;
  870. uint8_t response_sta_count = 0;
  871. status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  872. ppdu_id = HAL_TX_DESC_GET_64(tx_tlv,
  873. RX_RESPONSE_REQUIRED_INFO,
  874. PHY_PPDU_ID);
  875. reception_type =
  876. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  877. SU_OR_UPLINK_MU_RECEPTION);
  878. response_sta_count =
  879. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  880. RESPONSE_STA_COUNT);
  881. /* get mac address */
  882. *(uint32_t *)&tx_status_info->addr1[0] =
  883. HAL_TX_DESC_GET_64(tx_tlv,
  884. RX_RESPONSE_REQUIRED_INFO,
  885. ADDR1_31_0);
  886. *(uint32_t *)&tx_status_info->addr1[4] =
  887. HAL_TX_DESC_GET_64(tx_tlv,
  888. RX_RESPONSE_REQUIRED_INFO,
  889. ADDR1_47_32);
  890. *(uint32_t *)&tx_status_info->addr2[0] =
  891. HAL_TX_DESC_GET_64(tx_tlv,
  892. RX_RESPONSE_REQUIRED_INFO,
  893. ADDR2_15_0);
  894. *(uint32_t *)&tx_status_info->addr2[2] =
  895. HAL_TX_DESC_GET_64(tx_tlv,
  896. RX_RESPONSE_REQUIRED_INFO,
  897. ADDR2_47_16);
  898. TXMON_HAL(ppdu_info, ppdu_id) = ppdu_id;
  899. TXMON_HAL_STATUS(ppdu_info, ppdu_id) = ppdu_id;
  900. if (response_sta_count == 0)
  901. response_sta_count = 1;
  902. TXMON_HAL(ppdu_info, num_users) = response_sta_count;
  903. if (reception_type)
  904. TXMON_STATUS_INFO(tx_status_info,
  905. transmission_type) =
  906. TXMON_SU_TRANSMISSION;
  907. else
  908. TXMON_STATUS_INFO(tx_status_info,
  909. transmission_type) =
  910. TXMON_MU_TRANSMISSION;
  911. SHOW_DEFINED(WIFIRX_RESPONSE_REQUIRED_INFO_E);
  912. break;
  913. }
  914. /* Response window close */
  915. case WIFIRESPONSE_END_STATUS_E:/* UPSTREAM */
  916. {
  917. /* response PPDU window end */
  918. uint8_t generated_response = 0;
  919. uint32_t bandwidth = 0;
  920. uint32_t ppdu_timestamp_start = 0;
  921. uint32_t ppdu_timestamp_end = 0;
  922. uint32_t mba_usr_cnt = 0;
  923. uint32_t mba_fake_bitmap_cnt = 0;
  924. status = HAL_MON_RESPONSE_END_STATUS_INFO;
  925. generated_response = HAL_TX_DESC_GET_64(tx_tlv,
  926. RESPONSE_END_STATUS,
  927. GENERATED_RESPONSE);
  928. mba_usr_cnt = HAL_TX_DESC_GET_64(tx_tlv,
  929. RESPONSE_END_STATUS,
  930. MBA_USER_COUNT);
  931. mba_fake_bitmap_cnt = HAL_TX_DESC_GET_64(tx_tlv,
  932. RESPONSE_END_STATUS,
  933. MBA_FAKE_BITMAP_COUNT);
  934. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  935. COEX_BASED_TX_BW);
  936. /* 32 bits TSF */
  937. ppdu_timestamp_start =
  938. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  939. START_OF_FRAME_TIMESTAMP_15_0) |
  940. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  941. START_OF_FRAME_TIMESTAMP_31_16) <<
  942. 16));
  943. ppdu_timestamp_end =
  944. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  945. END_OF_FRAME_TIMESTAMP_15_0) |
  946. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  947. END_OF_FRAME_TIMESTAMP_31_16) <<
  948. 16));
  949. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  950. /* update phy timestamp to ppdu timestamp */
  951. TXMON_HAL_STATUS(ppdu_info,
  952. ppdu_timestamp) = ppdu_timestamp_start;
  953. TXMON_STATUS_INFO(tx_status_info,
  954. generated_response) = generated_response;
  955. TXMON_STATUS_INFO(tx_status_info, mba_count) = mba_usr_cnt;
  956. TXMON_STATUS_INFO(tx_status_info,
  957. mba_fake_bitmap_count) = mba_fake_bitmap_cnt;
  958. SHOW_DEFINED(WIFIRESPONSE_END_STATUS_E);
  959. break;
  960. }
  961. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  962. {
  963. SHOW_DEFINED(WIFITX_FLUSH_E);
  964. break;
  965. }
  966. /* Downstream tlv */
  967. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */
  968. {
  969. hal_txmon_parse_pcu_ppdu_setup_init(tx_tlv, data_status_info,
  970. prot_status_info);
  971. status = HAL_MON_TX_PCU_PPDU_SETUP_INIT;
  972. SHOW_DEFINED(WIFIPCU_PPDU_SETUP_INIT_E);
  973. break;
  974. }
  975. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */
  976. {
  977. hal_txmon_parse_peer_entry(tx_tlv, user_id,
  978. ppdu_info, tx_status_info);
  979. SHOW_DEFINED(WIFITX_PEER_ENTRY_E);
  980. break;
  981. }
  982. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */
  983. {
  984. status = HAL_MON_TX_QUEUE_EXTENSION;
  985. hal_txmon_parse_queue_exten(tx_tlv, ppdu_info);
  986. SHOW_DEFINED(WIFITX_QUEUE_EXTENSION_E);
  987. break;
  988. }
  989. /* payload and data frame handling */
  990. case WIFITX_MPDU_START_E:/* DOWNSTREAM */
  991. {
  992. hal_txmon_parse_mpdu_start(tx_tlv, user_id, ppdu_info);
  993. status = HAL_MON_TX_MPDU_START;
  994. SHOW_DEFINED(WIFITX_MPDU_START_E);
  995. break;
  996. }
  997. case WIFITX_MSDU_START_E:/* DOWNSTREAM */
  998. {
  999. /* compacted */
  1000. /* we expect frame to be 802.11 frame type */
  1001. status = HAL_MON_TX_MSDU_START;
  1002. SHOW_DEFINED(WIFITX_MSDU_START_E);
  1003. break;
  1004. }
  1005. case WIFITX_DATA_E:/* DOWNSTREAM */
  1006. {
  1007. status = HAL_MON_TX_DATA;
  1008. /*
  1009. * TODO: do we need a conversion api to convert
  1010. * user_id from hw to get host user_index
  1011. */
  1012. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1013. TXMON_STATUS_INFO(tx_status_info,
  1014. buffer) = (void *)status_frag;
  1015. TXMON_STATUS_INFO(tx_status_info,
  1016. offset) = ((void *)tx_tlv -
  1017. (void *)status_frag);
  1018. TXMON_STATUS_INFO(tx_status_info,
  1019. length) = tlv_len;
  1020. /*
  1021. * reference of the status buffer will be held in
  1022. * dp_tx_update_ppdu_info_status()
  1023. */
  1024. status = HAL_MON_TX_DATA;
  1025. SHOW_DEFINED(WIFITX_DATA_E);
  1026. break;
  1027. }
  1028. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  1029. {
  1030. packet_info = &ppdu_info->packet_info;
  1031. status = HAL_MON_TX_BUFFER_ADDR;
  1032. /*
  1033. * TODO: do we need a conversion api to convert
  1034. * user_id from hw to get host user_index
  1035. */
  1036. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1037. hal_txmon_populate_packet_info_generic_be(tx_tlv, packet_info);
  1038. SHOW_DEFINED(WIFIMON_BUFFER_ADDR_E);
  1039. break;
  1040. }
  1041. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  1042. {
  1043. /* no tlv content */
  1044. SHOW_DEFINED(WIFITX_MPDU_END_E);
  1045. break;
  1046. }
  1047. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  1048. {
  1049. /* no tlv content */
  1050. SHOW_DEFINED(WIFITX_MSDU_END_E);
  1051. break;
  1052. }
  1053. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  1054. {
  1055. /* no tlv content */
  1056. SHOW_DEFINED(WIFITX_LAST_MPDU_FETCHED_E);
  1057. break;
  1058. }
  1059. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  1060. {
  1061. /* no tlv content */
  1062. SHOW_DEFINED(WIFITX_LAST_MPDU_END_E);
  1063. break;
  1064. }
  1065. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  1066. {
  1067. /*
  1068. * transmitting power
  1069. * minimum transmitting power
  1070. * desired nss
  1071. * tx chain mask
  1072. * desired bw
  1073. * duration of transmit and response
  1074. *
  1075. * since most of the field we are deriving from other tlv
  1076. * we don't need to enable this in our tlv.
  1077. */
  1078. SHOW_DEFINED(WIFICOEX_TX_REQ_E);
  1079. break;
  1080. }
  1081. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  1082. {
  1083. /* user tlv */
  1084. /*
  1085. * All Tx monitor will have 802.11 hdr
  1086. * we don't need to enable this TLV
  1087. */
  1088. SHOW_DEFINED(WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E);
  1089. break;
  1090. }
  1091. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  1092. {
  1093. /*
  1094. * no tlv content
  1095. *
  1096. * TLV that indicates to TXPCU that preamble phase for the NDP
  1097. * frame transmission is now over
  1098. */
  1099. SHOW_DEFINED(WIFINDP_PREAMBLE_DONE_E);
  1100. break;
  1101. }
  1102. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  1103. {
  1104. /*
  1105. * no tlv content
  1106. *
  1107. * TLV indicates to the SCH that all timing critical TLV
  1108. * has been passed on to the transmit path
  1109. */
  1110. SHOW_DEFINED(WIFISCH_CRITICAL_TLV_REFERENCE_E);
  1111. break;
  1112. }
  1113. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  1114. {
  1115. /*
  1116. * Loopback specific setup info - not needed for Tx monitor
  1117. */
  1118. SHOW_DEFINED(WIFITX_LOOPBACK_SETUP_E);
  1119. break;
  1120. }
  1121. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  1122. {
  1123. /*
  1124. * no tlv content
  1125. *
  1126. * TLV indicates that other modules besides the scheduler can
  1127. * now also start generating TLV's
  1128. * prevent colliding or generating TLV's out of order
  1129. */
  1130. SHOW_DEFINED(WIFITX_FES_SETUP_COMPLETE_E);
  1131. break;
  1132. }
  1133. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  1134. {
  1135. /*
  1136. * no tlv content
  1137. *
  1138. * TLV indicates to SCH that a burst of MPDU info will
  1139. * start to come in over the TLV
  1140. */
  1141. SHOW_DEFINED(WIFITQM_MPDU_GLOBAL_START_E);
  1142. break;
  1143. }
  1144. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  1145. {
  1146. SHOW_DEFINED(WIFITX_WUR_DATA_E);
  1147. break;
  1148. }
  1149. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  1150. {
  1151. /*
  1152. * no tlv content
  1153. *
  1154. * TLV indicates END of all TLV's within the scheduler TLV
  1155. */
  1156. SHOW_DEFINED(WIFISCHEDULER_END_E);
  1157. break;
  1158. }
  1159. /* Upstream tlv */
  1160. case WIFIPDG_TX_REQ_E:
  1161. {
  1162. SHOW_DEFINED(WIFIPDG_TX_REQ_E);
  1163. break;
  1164. }
  1165. case WIFITX_FES_STATUS_START_E:
  1166. {
  1167. /*
  1168. * TLV indicating that first transmission on the medium
  1169. */
  1170. uint8_t medium_prot_type = 0;
  1171. status = HAL_MON_TX_FES_STATUS_START;
  1172. medium_prot_type = HAL_TX_DESC_GET_64(tx_tlv,
  1173. TX_FES_STATUS_START,
  1174. MEDIUM_PROT_TYPE);
  1175. ppdu_info = (struct hal_tx_ppdu_info *)prot_ppdu_info;
  1176. /* update what type of medium protection frame */
  1177. TXMON_STATUS_INFO(tx_status_info,
  1178. medium_prot_type) = medium_prot_type;
  1179. SHOW_DEFINED(WIFITX_FES_STATUS_START_E);
  1180. break;
  1181. }
  1182. case WIFITX_FES_STATUS_PROT_E:
  1183. {
  1184. uint32_t start_timestamp = 0;
  1185. uint32_t end_timestamp = 0;
  1186. /*
  1187. * generated by TXPCU to indicate the result of having
  1188. * received of the expected protection frame
  1189. */
  1190. status = HAL_MON_TX_FES_STATUS_PROT;
  1191. start_timestamp =
  1192. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT,
  1193. START_OF_FRAME_TIMESTAMP_15_0);
  1194. start_timestamp |=
  1195. (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT,
  1196. START_OF_FRAME_TIMESTAMP_31_16) <<
  1197. 15);
  1198. end_timestamp = HAL_TX_DESC_GET_64(tx_tlv,
  1199. TX_FES_STATUS_PROT,
  1200. END_OF_FRAME_TIMESTAMP_15_0);
  1201. end_timestamp |=
  1202. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT,
  1203. END_OF_FRAME_TIMESTAMP_31_16) << 15;
  1204. /* ppdu timestamp as phy timestamp */
  1205. TXMON_HAL_STATUS(ppdu_info,
  1206. ppdu_timestamp) = start_timestamp;
  1207. SHOW_DEFINED(WIFITX_FES_STATUS_PROT_E);
  1208. break;
  1209. }
  1210. case WIFITX_FES_STATUS_START_PROT_E:
  1211. {
  1212. uint64_t tsft_64;
  1213. uint32_t response_type;
  1214. status = HAL_MON_TX_FES_STATUS_START_PROT;
  1215. TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag;
  1216. /* timestamp */
  1217. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1218. TX_FES_STATUS_START_PROT,
  1219. PROT_TIMESTAMP_LOWER_32);
  1220. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1221. TX_FES_STATUS_START_PROT,
  1222. PROT_TIMESTAMP_UPPER_32) << 32);
  1223. response_type = HAL_TX_DESC_GET_64(tx_tlv,
  1224. TX_FES_STATUS_START_PROT,
  1225. RESPONSE_TYPE);
  1226. TXMON_STATUS_INFO(tx_status_info,
  1227. response_type) = response_type;
  1228. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1229. SHOW_DEFINED(WIFITX_FES_STATUS_START_PROT_E);
  1230. break;
  1231. }
  1232. case WIFIPROT_TX_END_E:
  1233. {
  1234. /*
  1235. * no tlv content
  1236. *
  1237. * generated by TXPCU the moment that protection frame
  1238. * transmission has finished on the medium
  1239. */
  1240. SHOW_DEFINED(WIFIPROT_TX_END_E);
  1241. break;
  1242. }
  1243. case WIFITX_FES_STATUS_START_PPDU_E:
  1244. {
  1245. uint64_t tsft_64;
  1246. uint8_t ndp_frame;
  1247. status = HAL_MON_TX_FES_STATUS_START_PPDU;
  1248. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1249. TX_FES_STATUS_START_PPDU,
  1250. PPDU_TIMESTAMP_LOWER_32);
  1251. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1252. TX_FES_STATUS_START_PPDU,
  1253. PPDU_TIMESTAMP_UPPER_32) << 32);
  1254. ndp_frame = HAL_TX_DESC_GET_64(tx_tlv,
  1255. TX_FES_STATUS_START_PPDU,
  1256. NDP_FRAME);
  1257. TXMON_STATUS_INFO(tx_status_info, ndp_frame) = ndp_frame;
  1258. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1259. SHOW_DEFINED(WIFITX_FES_STATUS_START_PPDU_E);
  1260. break;
  1261. }
  1262. case WIFITX_FES_STATUS_USER_PPDU_E:
  1263. {
  1264. /* user tlv */
  1265. uint16_t duration;
  1266. uint8_t transmitted_tid;
  1267. duration = HAL_TX_DESC_GET_64(tx_tlv,
  1268. TX_FES_STATUS_USER_PPDU,
  1269. DURATION);
  1270. transmitted_tid = HAL_TX_DESC_GET_64(tx_tlv,
  1271. TX_FES_STATUS_USER_PPDU,
  1272. TRANSMITTED_TID);
  1273. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1274. TXMON_HAL_USER(ppdu_info, user_id, tid) = transmitted_tid;
  1275. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  1276. status = HAL_MON_TX_FES_STATUS_USER_PPDU;
  1277. SHOW_DEFINED(WIFITX_FES_STATUS_USER_PPDU_E);
  1278. break;
  1279. }
  1280. case WIFIPPDU_TX_END_E:
  1281. {
  1282. /*
  1283. * no tlv content
  1284. *
  1285. * generated by TXPCU the moment that PPDU transmission has
  1286. * finished on the medium
  1287. */
  1288. SHOW_DEFINED(WIFIPPDU_TX_END_E);
  1289. break;
  1290. }
  1291. case WIFITX_FES_STATUS_USER_RESPONSE_E:
  1292. {
  1293. /*
  1294. * TLV contains the FES transmit result of the each
  1295. * of the MAC users. TLV are forwarded to HWSCH
  1296. */
  1297. SHOW_DEFINED(WIFITX_FES_STATUS_USER_RESPONSE_E);
  1298. break;
  1299. }
  1300. case WIFITX_FES_STATUS_ACK_OR_BA_E:
  1301. {
  1302. /* user tlv */
  1303. /*
  1304. * TLV generated by RXPCU and provide information related to
  1305. * the received BA or ACK frame
  1306. */
  1307. SHOW_DEFINED(WIFITX_FES_STATUS_ACK_OR_BA_E);
  1308. break;
  1309. }
  1310. case WIFITX_FES_STATUS_1K_BA_E:
  1311. {
  1312. /* user tlv */
  1313. /*
  1314. * TLV generated by RXPCU and providing information related
  1315. * to the received BA frame in case of 512/1024 bitmaps
  1316. */
  1317. SHOW_DEFINED(WIFITX_FES_STATUS_1K_BA_E);
  1318. break;
  1319. }
  1320. case WIFIRECEIVED_RESPONSE_USER_7_0_E:
  1321. {
  1322. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_7_0_E);
  1323. break;
  1324. }
  1325. case WIFIRECEIVED_RESPONSE_USER_15_8_E:
  1326. {
  1327. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_15_8_E);
  1328. break;
  1329. }
  1330. case WIFIRECEIVED_RESPONSE_USER_23_16_E:
  1331. {
  1332. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_23_16_E);
  1333. break;
  1334. }
  1335. case WIFIRECEIVED_RESPONSE_USER_31_24_E:
  1336. {
  1337. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_31_24_E);
  1338. break;
  1339. }
  1340. case WIFIRECEIVED_RESPONSE_USER_36_32_E:
  1341. {
  1342. /*
  1343. * RXPCU generates this TLV when it receives a response frame
  1344. * that TXPCU pre-announced it was waiting for and in
  1345. * RXPCU_SETUP TLV, TLV generated before the
  1346. * RECEIVED_RESPONSE_INFO TLV.
  1347. *
  1348. * received info user fields are there which is not needed
  1349. * for TX monitor
  1350. */
  1351. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_36_32_E);
  1352. break;
  1353. }
  1354. case WIFITXPCU_BUFFER_STATUS_E:
  1355. {
  1356. SHOW_DEFINED(WIFITXPCU_BUFFER_STATUS_E);
  1357. break;
  1358. }
  1359. case WIFITXPCU_USER_BUFFER_STATUS_E:
  1360. {
  1361. /*
  1362. * WIFITXPCU_USER_BUFFER_STATUS_E - user tlv
  1363. * for TX monitor we aren't interested in this tlv
  1364. */
  1365. SHOW_DEFINED(WIFITXPCU_USER_BUFFER_STATUS_E);
  1366. break;
  1367. }
  1368. case WIFITXDMA_STOP_REQUEST_E:
  1369. {
  1370. /*
  1371. * no tlv content
  1372. *
  1373. * TLV is destined to TXDMA and informs TXDMA to stop
  1374. * pushing data into the transmit path.
  1375. */
  1376. SHOW_DEFINED(WIFITXDMA_STOP_REQUEST_E);
  1377. break;
  1378. }
  1379. case WIFITX_CBF_INFO_E:
  1380. {
  1381. /*
  1382. * After NDPA + NDP is received, RXPCU sends the TX_CBF_INFO to
  1383. * TXPCU to respond the CBF frame
  1384. *
  1385. * compressed beamforming pkt doesn't has mac header
  1386. * Tx monitor not interested in this pkt.
  1387. */
  1388. SHOW_DEFINED(WIFITX_CBF_INFO_E);
  1389. break;
  1390. }
  1391. case WIFITX_MPDU_COUNT_TRANSFER_END_E:
  1392. {
  1393. /*
  1394. * no tlv content
  1395. *
  1396. * TLV indicates that TXPCU has finished generating the
  1397. * TQM_UPDATE_TX_MPDU_COUNT TLV for all users
  1398. */
  1399. SHOW_DEFINED(WIFITX_MPDU_COUNT_TRANSFER_END_E);
  1400. break;
  1401. }
  1402. case WIFIPDG_RESPONSE_E:
  1403. {
  1404. /*
  1405. * most of the feilds are already covered in
  1406. * other TLV
  1407. * This is generated by TX_PCU to PDG to calculate
  1408. * all the PHY header info.
  1409. *
  1410. * some useful fields like min transmit power,
  1411. * rate used for transmitting packet is present.
  1412. */
  1413. SHOW_DEFINED(WIFIPDG_RESPONSE_E);
  1414. break;
  1415. }
  1416. case WIFIPDG_TRIG_RESPONSE_E:
  1417. {
  1418. /* no tlv content */
  1419. SHOW_DEFINED(WIFIPDG_TRIG_RESPONSE_E);
  1420. break;
  1421. }
  1422. case WIFIRECEIVED_TRIGGER_INFO_E:
  1423. {
  1424. /*
  1425. * TLV generated by RXPCU to inform the scheduler that
  1426. * a trigger frame has been received
  1427. */
  1428. SHOW_DEFINED(WIFIRECEIVED_TRIGGER_INFO_E);
  1429. break;
  1430. }
  1431. case WIFIOFDMA_TRIGGER_DETAILS_E:
  1432. {
  1433. SHOW_DEFINED(WIFIOFDMA_TRIGGER_DETAILS_E);
  1434. break;
  1435. }
  1436. case WIFIRX_FRAME_BITMAP_ACK_E:
  1437. {
  1438. /* user tlv */
  1439. status = HAL_MON_RX_FRAME_BITMAP_ACK;
  1440. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_ACK_E);
  1441. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1442. TXMON_STATUS_INFO(tx_status_info, no_bitmap_avail) =
  1443. HAL_TX_DESC_GET_64(tx_tlv,
  1444. RX_FRAME_BITMAP_ACK,
  1445. NO_BITMAP_AVAILABLE);
  1446. TXMON_STATUS_INFO(tx_status_info, explicit_ack) =
  1447. HAL_TX_DESC_GET_64(tx_tlv,
  1448. RX_FRAME_BITMAP_ACK,
  1449. EXPLICIT_ACK);
  1450. /*
  1451. * get mac address, since address is received frame
  1452. * change the order and store it
  1453. */
  1454. *(uint32_t *)&tx_status_info->addr2[0] =
  1455. HAL_TX_DESC_GET_64(tx_tlv,
  1456. RX_FRAME_BITMAP_ACK,
  1457. ADDR1_31_0);
  1458. *(uint32_t *)&tx_status_info->addr2[4] =
  1459. HAL_TX_DESC_GET_64(tx_tlv,
  1460. RX_FRAME_BITMAP_ACK,
  1461. ADDR1_47_32);
  1462. *(uint32_t *)&tx_status_info->addr1[0] =
  1463. HAL_TX_DESC_GET_64(tx_tlv,
  1464. RX_FRAME_BITMAP_ACK,
  1465. ADDR2_15_0);
  1466. *(uint32_t *)&tx_status_info->addr1[2] =
  1467. HAL_TX_DESC_GET_64(tx_tlv,
  1468. RX_FRAME_BITMAP_ACK,
  1469. ADDR2_47_16);
  1470. TXMON_STATUS_INFO(tx_status_info, explicit_ack_type) =
  1471. HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_BITMAP_ACK,
  1472. EXPLICT_ACK_TYPE);
  1473. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  1474. HAL_TX_DESC_GET_64(tx_tlv,
  1475. RX_FRAME_BITMAP_ACK,
  1476. BA_TID);
  1477. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  1478. HAL_TX_DESC_GET_64(tx_tlv,
  1479. RX_FRAME_BITMAP_ACK,
  1480. STA_FULL_AID);
  1481. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  1482. HAL_TX_DESC_GET_64(tx_tlv,
  1483. RX_FRAME_BITMAP_ACK,
  1484. BA_TS_SEQ);
  1485. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  1486. HAL_TX_DESC_GET_64(tx_tlv,
  1487. RX_FRAME_BITMAP_ACK,
  1488. BA_TS_CTRL);
  1489. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  1490. HAL_TX_DESC_GET_64(tx_tlv,
  1491. RX_FRAME_BITMAP_ACK,
  1492. BA_BITMAP_SIZE);
  1493. /* ba bitmap */
  1494. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  1495. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  1496. RX_FRAME_BITMAP_ACK,
  1497. BA_TS_BITMAP_31_0, 0), 32);
  1498. break;
  1499. }
  1500. case WIFIRX_FRAME_1K_BITMAP_ACK_E:
  1501. {
  1502. /* user tlv */
  1503. status = HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K;
  1504. SHOW_DEFINED(WIFIRX_FRAME_1K_BITMAP_ACK_E);
  1505. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1506. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  1507. (4 + HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_1K_BITMAP_ACK,
  1508. BA_BITMAP_SIZE));
  1509. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  1510. HAL_TX_DESC_GET_64(tx_tlv,
  1511. RX_FRAME_1K_BITMAP_ACK,
  1512. BA_TID);
  1513. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  1514. HAL_TX_DESC_GET_64(tx_tlv,
  1515. RX_FRAME_1K_BITMAP_ACK,
  1516. STA_FULL_AID);
  1517. /* get mac address */
  1518. *(uint32_t *)&tx_status_info->addr1[0] =
  1519. HAL_TX_DESC_GET_64(tx_tlv,
  1520. RX_FRAME_1K_BITMAP_ACK,
  1521. ADDR1_31_0);
  1522. *(uint32_t *)&tx_status_info->addr1[4] =
  1523. HAL_TX_DESC_GET_64(tx_tlv,
  1524. RX_FRAME_1K_BITMAP_ACK,
  1525. ADDR1_47_32);
  1526. *(uint32_t *)&tx_status_info->addr2[0] =
  1527. HAL_TX_DESC_GET_64(tx_tlv,
  1528. RX_FRAME_1K_BITMAP_ACK,
  1529. ADDR2_15_0);
  1530. *(uint32_t *)&tx_status_info->addr2[2] =
  1531. HAL_TX_DESC_GET_64(tx_tlv,
  1532. RX_FRAME_1K_BITMAP_ACK,
  1533. ADDR2_47_16);
  1534. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  1535. HAL_TX_DESC_GET_64(tx_tlv,
  1536. RX_FRAME_1K_BITMAP_ACK,
  1537. BA_TS_SEQ);
  1538. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  1539. HAL_TX_DESC_GET_64(tx_tlv,
  1540. RX_FRAME_1K_BITMAP_ACK,
  1541. BA_TS_CTRL);
  1542. /* memcpy ba bitmap */
  1543. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  1544. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  1545. RX_FRAME_1K_BITMAP_ACK,
  1546. BA_TS_BITMAP_31_0, 0),
  1547. 4 << TXMON_HAL_USER(ppdu_info,
  1548. user_id, ba_bitmap_sz));
  1549. break;
  1550. }
  1551. case WIFIRESPONSE_START_STATUS_E:
  1552. {
  1553. /*
  1554. * TLV indicates which HW response the TXPCU
  1555. * started generating
  1556. *
  1557. * HW generated frames like
  1558. * ACK frame - handled
  1559. * CTS frame - handled
  1560. * BA frame - handled
  1561. * MBA frame - handled
  1562. * CBF frame - no frame header
  1563. * Trigger response - TODO
  1564. * NDP LMR - no frame header
  1565. */
  1566. SHOW_DEFINED(WIFIRESPONSE_START_STATUS_E);
  1567. break;
  1568. }
  1569. case WIFIRX_START_PARAM_E:
  1570. {
  1571. /*
  1572. * RXPCU send this TLV after PHY RX detected a frame
  1573. * in the medium
  1574. *
  1575. * TX monitor not interested in this TLV
  1576. */
  1577. SHOW_DEFINED(WIFIRX_START_PARAM_E);
  1578. break;
  1579. }
  1580. case WIFIRXPCU_EARLY_RX_INDICATION_E:
  1581. {
  1582. /*
  1583. * early indication of pkt type and mcs rate
  1584. * already captured in other tlv
  1585. */
  1586. SHOW_DEFINED(WIFIRXPCU_EARLY_RX_INDICATION_E);
  1587. break;
  1588. }
  1589. case WIFIRX_PM_INFO_E:
  1590. {
  1591. SHOW_DEFINED(WIFIRX_PM_INFO_E);
  1592. break;
  1593. }
  1594. /* Active window */
  1595. case WIFITX_FLUSH_REQ_E:
  1596. {
  1597. SHOW_DEFINED(WIFITX_FLUSH_REQ_E);
  1598. break;
  1599. }
  1600. case WIFICOEX_TX_STATUS_E:
  1601. {
  1602. /* duration are retrieved from coex tx status */
  1603. uint16_t duration;
  1604. uint8_t status_reason;
  1605. status = HAL_MON_COEX_TX_STATUS;
  1606. duration = HAL_TX_DESC_GET_64(tx_tlv,
  1607. COEX_TX_STATUS,
  1608. CURRENT_TX_DURATION);
  1609. status_reason = HAL_TX_DESC_GET_64(tx_tlv,
  1610. COEX_TX_STATUS,
  1611. TX_STATUS_REASON);
  1612. /* update duration */
  1613. if (status_reason == COEX_FES_TX_START ||
  1614. status_reason == COEX_RESPONSE_TX_START)
  1615. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  1616. SHOW_DEFINED(WIFICOEX_TX_STATUS_E);
  1617. break;
  1618. }
  1619. case WIFIR2R_STATUS_END_E:
  1620. {
  1621. SHOW_DEFINED(WIFIR2R_STATUS_END_E);
  1622. break;
  1623. }
  1624. case WIFIRX_PREAMBLE_E:
  1625. {
  1626. SHOW_DEFINED(WIFIRX_PREAMBLE_E);
  1627. break;
  1628. }
  1629. case WIFIMACTX_SERVICE_E:
  1630. {
  1631. SHOW_DEFINED(WIFIMACTX_SERVICE_E);
  1632. break;
  1633. }
  1634. case WIFIMACTX_U_SIG_EHT_SU_MU_E:
  1635. {
  1636. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_SU_MU_E);
  1637. break;
  1638. }
  1639. case WIFIMACTX_U_SIG_EHT_TB_E:
  1640. {
  1641. /* TODO: no radiotap info available */
  1642. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_TB_E);
  1643. break;
  1644. }
  1645. case WIFIMACTX_EHT_SIG_USR_OFDMA_E:
  1646. {
  1647. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_OFDMA_E);
  1648. break;
  1649. }
  1650. case WIFIMACTX_EHT_SIG_USR_MU_MIMO_E:
  1651. {
  1652. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_MU_MIMO_E);
  1653. break;
  1654. }
  1655. case WIFIMACTX_EHT_SIG_USR_SU_E:
  1656. {
  1657. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_SU_E);
  1658. /* TODO: no radiotap info available */
  1659. break;
  1660. }
  1661. case WIFIMACTX_HE_SIG_A_SU_E:
  1662. {
  1663. uint16_t he_mu_flag_1 = 0;
  1664. uint16_t he_mu_flag_2 = 0;
  1665. uint16_t num_users = 0;
  1666. uint8_t mcs_of_sig_b = 0;
  1667. uint8_t dcm_of_sig_b = 0;
  1668. uint8_t sig_a_bw = 0;
  1669. uint8_t i = 0;
  1670. uint8_t bss_color_id;
  1671. uint8_t coding;
  1672. uint8_t stbc;
  1673. uint8_t a_factor;
  1674. uint8_t pe_disambiguity;
  1675. uint8_t txbf;
  1676. uint8_t txbw;
  1677. uint8_t txop;
  1678. status = HAL_MON_MACTX_HE_SIG_A_SU;
  1679. num_users = TXMON_HAL(ppdu_info, num_users);
  1680. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  1681. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1682. TRANSMIT_MCS);
  1683. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  1684. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1685. DCM);
  1686. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  1687. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1688. TRANSMIT_BW);
  1689. bss_color_id = HAL_TX_DESC_GET_64(tx_tlv,
  1690. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1691. BSS_COLOR_ID);
  1692. coding = HAL_TX_DESC_GET_64(tx_tlv,
  1693. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1694. CODING);
  1695. stbc = HAL_TX_DESC_GET_64(tx_tlv,
  1696. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1697. STBC);
  1698. a_factor = HAL_TX_DESC_GET_64(tx_tlv,
  1699. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1700. PACKET_EXTENSION_A_FACTOR);
  1701. pe_disambiguity = HAL_TX_DESC_GET_64(tx_tlv,
  1702. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1703. PACKET_EXTENSION_PE_DISAMBIGUITY);
  1704. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  1705. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1706. TXBF);
  1707. txbw = HAL_TX_DESC_GET_64(tx_tlv,
  1708. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1709. TRANSMIT_BW);
  1710. txop = HAL_TX_DESC_GET_64(tx_tlv,
  1711. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1712. TXOP_DURATION);
  1713. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1714. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1715. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  1716. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  1717. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  1718. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN;
  1719. /* MCS */
  1720. he_mu_flag_1 |= mcs_of_sig_b <<
  1721. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  1722. /* DCM */
  1723. he_mu_flag_1 |= dcm_of_sig_b <<
  1724. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  1725. /* bandwidth */
  1726. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  1727. he_mu_flag_2 |= sig_a_bw <<
  1728. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  1729. TXMON_HAL_STATUS(ppdu_info,
  1730. he_mu_flags) = IS_MULTI_USERS(num_users);
  1731. for (i = 0; i < num_users; i++) {
  1732. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  1733. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  1734. }
  1735. /* HE data 1 */
  1736. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  1737. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  1738. QDF_MON_STATUS_HE_CODING_KNOWN;
  1739. /* HE data 2 */
  1740. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  1741. QDF_MON_STATUS_TXBF_KNOWN |
  1742. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  1743. QDF_MON_STATUS_TXOP_KNOWN |
  1744. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  1745. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  1746. /* HE data 3 */
  1747. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1748. bss_color_id |
  1749. (!!txbf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT) |
  1750. (coding << QDF_MON_STATUS_CODING_SHIFT) |
  1751. (stbc << QDF_MON_STATUS_STBC_SHIFT);
  1752. /* HE data 6 */
  1753. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  1754. (txop << QDF_MON_STATUS_TXOP_SHIFT);
  1755. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_SU_E);
  1756. break;
  1757. }
  1758. case WIFIMACTX_HE_SIG_A_MU_DL_E:
  1759. {
  1760. uint16_t he_mu_flag_1 = 0;
  1761. uint16_t he_mu_flag_2 = 0;
  1762. uint16_t num_users = 0;
  1763. uint8_t bss_color_id;
  1764. uint8_t txop;
  1765. uint8_t mcs_of_sig_b = 0;
  1766. uint8_t dcm_of_sig_b = 0;
  1767. uint8_t sig_a_bw = 0;
  1768. uint8_t num_sig_b_symb = 0;
  1769. uint8_t comp_mode_sig_b = 0;
  1770. uint8_t punc_bw = 0;
  1771. uint8_t i = 0;
  1772. status = HAL_MON_MACTX_HE_SIG_A_MU_DL;
  1773. num_users = TXMON_HAL(ppdu_info, num_users);
  1774. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  1775. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1776. MCS_OF_SIG_B);
  1777. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  1778. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1779. DCM_OF_SIG_B);
  1780. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  1781. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1782. TRANSMIT_BW);
  1783. num_sig_b_symb = HAL_TX_DESC_GET_64(tx_tlv,
  1784. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1785. NUM_SIG_B_SYMBOLS);
  1786. comp_mode_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  1787. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1788. COMP_MODE_SIG_B);
  1789. bss_color_id = HAL_TX_DESC_GET_64(tx_tlv,
  1790. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1791. BSS_COLOR_ID);
  1792. txop = HAL_TX_DESC_GET_64(tx_tlv,
  1793. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1794. TXOP_DURATION);
  1795. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1796. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1797. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  1798. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  1799. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  1800. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  1801. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  1802. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  1803. QDF_MON_STATUS_SIG_B_SYMBOL_USER_KNOWN;
  1804. /* MCS */
  1805. he_mu_flag_1 |= mcs_of_sig_b <<
  1806. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  1807. /* DCM */
  1808. he_mu_flag_1 |= dcm_of_sig_b <<
  1809. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  1810. /* Compression */
  1811. he_mu_flag_2 |= comp_mode_sig_b <<
  1812. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1813. /* bandwidth */
  1814. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  1815. he_mu_flag_2 |= sig_a_bw <<
  1816. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  1817. he_mu_flag_2 |= comp_mode_sig_b <<
  1818. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1819. /* number of symbol */
  1820. he_mu_flag_2 |= num_sig_b_symb <<
  1821. QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  1822. /* puncture bw */
  1823. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_KNOWN;
  1824. punc_bw = sig_a_bw;
  1825. he_mu_flag_2 |=
  1826. punc_bw << QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_SHIFT;
  1827. /* copy per user info to all user */
  1828. TXMON_HAL_STATUS(ppdu_info,
  1829. he_mu_flags) = IS_MULTI_USERS(num_users);
  1830. for (i = 0; i < num_users; i++) {
  1831. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  1832. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  1833. }
  1834. /* HE data 1 */
  1835. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  1836. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN;
  1837. /* HE data 2 */
  1838. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  1839. QDF_MON_STATUS_TXOP_KNOWN;
  1840. /* HE data 3 */
  1841. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= bss_color_id;
  1842. /* HE data 6 */
  1843. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  1844. (txop << QDF_MON_STATUS_TXOP_SHIFT);
  1845. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_DL_E);
  1846. break;
  1847. }
  1848. case WIFIMACTX_HE_SIG_A_MU_UL_E:
  1849. {
  1850. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_UL_E);
  1851. break;
  1852. }
  1853. case WIFIMACTX_HE_SIG_B1_MU_E:
  1854. {
  1855. status = HAL_MON_MACTX_HE_SIG_B1_MU;
  1856. SHOW_DEFINED(WIFIMACTX_HE_SIG_B1_MU_E);
  1857. break;
  1858. }
  1859. case WIFIMACTX_HE_SIG_B2_MU_E:
  1860. {
  1861. /* user tlv */
  1862. uint16_t sta_id = 0;
  1863. uint16_t sta_spatial_config = 0;
  1864. uint8_t sta_mcs = 0;
  1865. uint8_t coding = 0;
  1866. uint8_t nss = 0;
  1867. uint8_t user_order = 0;
  1868. status = HAL_MON_MACTX_HE_SIG_B2_MU;
  1869. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1870. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  1871. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1872. STA_ID);
  1873. sta_spatial_config = HAL_TX_DESC_GET_64(tx_tlv,
  1874. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1875. STA_SPATIAL_CONFIG);
  1876. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  1877. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1878. STA_MCS);
  1879. coding = HAL_TX_DESC_GET_64(tx_tlv,
  1880. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1881. STA_CODING);
  1882. nss = HAL_TX_DESC_GET_64(tx_tlv,
  1883. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1884. NSTS) + 1;
  1885. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  1886. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1887. USER_ORDER);
  1888. /* HE data 1 */
  1889. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  1890. QDF_MON_STATUS_HE_MCS_KNOWN |
  1891. QDF_MON_STATUS_HE_CODING_KNOWN;
  1892. /* HE data 2 */
  1893. /* HE data 3 */
  1894. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  1895. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1896. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1897. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1898. coding << QDF_MON_STATUS_CODING_SHIFT;
  1899. /* HE data 4 */
  1900. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  1901. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  1902. /* HE data 5 */
  1903. /* HE data 6 */
  1904. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  1905. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  1906. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_MU_E);
  1907. break;
  1908. }
  1909. case WIFIMACTX_HE_SIG_B2_OFDMA_E:
  1910. {
  1911. /* user tlv */
  1912. uint8_t *he_sig_b2_ofdma_info = NULL;
  1913. uint16_t sta_id = 0;
  1914. uint8_t nss = 0;
  1915. uint8_t txbf = 0;
  1916. uint8_t sta_mcs = 0;
  1917. uint8_t sta_dcm = 0;
  1918. uint8_t coding = 0;
  1919. uint8_t user_order = 0;
  1920. status = HAL_MON_MACTX_HE_SIG_B2_OFDMA;
  1921. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1922. he_sig_b2_ofdma_info = (uint8_t *)tx_tlv +
  1923. HAL_OFFSET(MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1924. STA_ID);
  1925. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  1926. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1927. STA_ID);
  1928. nss = HAL_TX_DESC_GET_64(tx_tlv,
  1929. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1930. NSTS);
  1931. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  1932. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1933. TXBF);
  1934. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  1935. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1936. STA_MCS);
  1937. sta_dcm = HAL_TX_DESC_GET_64(tx_tlv,
  1938. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1939. STA_DCM);
  1940. coding = HAL_TX_DESC_GET_64(tx_tlv,
  1941. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1942. STA_CODING);
  1943. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  1944. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1945. USER_ORDER);
  1946. /* HE data 1 */
  1947. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  1948. QDF_MON_STATUS_HE_MCS_KNOWN |
  1949. QDF_MON_STATUS_HE_CODING_KNOWN |
  1950. QDF_MON_STATUS_HE_DCM_KNOWN;
  1951. /* HE data 2 */
  1952. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  1953. QDF_MON_STATUS_TXBF_KNOWN;
  1954. /* HE data 3 */
  1955. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  1956. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1957. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1958. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1959. sta_dcm << QDF_MON_STATUS_DCM_SHIFT;
  1960. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1961. coding << QDF_MON_STATUS_CODING_SHIFT;
  1962. /* HE data 4 */
  1963. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  1964. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  1965. /* HE data 5 */
  1966. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  1967. txbf << QDF_MON_STATUS_TXBF_SHIFT;
  1968. /* HE data 6 */
  1969. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  1970. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  1971. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_OFDMA_E);
  1972. break;
  1973. }
  1974. case WIFIMACTX_L_SIG_A_E:
  1975. {
  1976. uint8_t *l_sig_a_info = NULL;
  1977. uint8_t rate = 0;
  1978. status = HAL_MON_MACTX_L_SIG_A;
  1979. l_sig_a_info = (uint8_t *)tx_tlv +
  1980. HAL_OFFSET(MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  1981. RATE);
  1982. rate = HAL_TX_DESC_GET_64(tx_tlv,
  1983. MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  1984. RATE);
  1985. switch (rate) {
  1986. case 8:
  1987. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_0MCS;
  1988. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  1989. break;
  1990. case 9:
  1991. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_1MCS;
  1992. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  1993. break;
  1994. case 10:
  1995. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_2MCS;
  1996. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  1997. break;
  1998. case 11:
  1999. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_3MCS;
  2000. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  2001. break;
  2002. case 12:
  2003. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_4MCS;
  2004. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  2005. break;
  2006. case 13:
  2007. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_5MCS;
  2008. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  2009. break;
  2010. case 14:
  2011. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_6MCS;
  2012. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  2013. break;
  2014. case 15:
  2015. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_7MCS;
  2016. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS7;
  2017. break;
  2018. default:
  2019. break;
  2020. }
  2021. TXMON_HAL_STATUS(ppdu_info, ofdm_flag) = 1;
  2022. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2023. TXMON_HAL_STATUS(ppdu_info, l_sig_a_info) = *l_sig_a_info;
  2024. SHOW_DEFINED(WIFIMACTX_L_SIG_A_E);
  2025. break;
  2026. }
  2027. case WIFIMACTX_L_SIG_B_E:
  2028. {
  2029. uint8_t *l_sig_b_info = NULL;
  2030. uint8_t rate = 0;
  2031. status = HAL_MON_MACTX_L_SIG_B;
  2032. l_sig_b_info = (uint8_t *)tx_tlv +
  2033. HAL_OFFSET(MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  2034. RATE);
  2035. rate = HAL_TX_DESC_GET_64(tx_tlv,
  2036. MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  2037. RATE);
  2038. switch (rate) {
  2039. case 1:
  2040. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_3MCS;
  2041. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  2042. break;
  2043. case 2:
  2044. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_2MCS;
  2045. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  2046. break;
  2047. case 3:
  2048. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_1MCS;
  2049. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  2050. break;
  2051. case 4:
  2052. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_0MCS;
  2053. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  2054. break;
  2055. case 5:
  2056. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_6MCS;
  2057. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  2058. break;
  2059. case 6:
  2060. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_5MCS;
  2061. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  2062. break;
  2063. case 7:
  2064. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_4MCS;
  2065. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  2066. break;
  2067. default:
  2068. break;
  2069. }
  2070. TXMON_HAL_STATUS(ppdu_info, cck_flag) = 1;
  2071. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2072. TXMON_HAL_STATUS(ppdu_info, l_sig_b_info) = *l_sig_b_info;
  2073. SHOW_DEFINED(WIFIMACTX_L_SIG_B_E);
  2074. break;
  2075. }
  2076. case WIFIMACTX_HT_SIG_E:
  2077. {
  2078. uint8_t mcs = 0;
  2079. uint8_t bw = 0;
  2080. uint8_t is_stbc = 0;
  2081. uint8_t coding = 0;
  2082. uint8_t gi = 0;
  2083. status = HAL_MON_MACTX_HT_SIG;
  2084. mcs = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, MCS);
  2085. bw = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, CBW);
  2086. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, STBC);
  2087. coding = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, FEC_CODING);
  2088. gi = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, SHORT_GI);
  2089. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  2090. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  2091. TXMON_HAL_STATUS(ppdu_info, ht_mcs) = mcs;
  2092. TXMON_HAL_STATUS(ppdu_info, bw) = bw;
  2093. TXMON_HAL_STATUS(ppdu_info, sgi) = gi;
  2094. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2095. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2096. SHOW_DEFINED(WIFIMACTX_HT_SIG_E);
  2097. break;
  2098. }
  2099. case WIFIMACTX_VHT_SIG_A_E:
  2100. {
  2101. uint8_t bandwidth = 0;
  2102. uint8_t is_stbc = 0;
  2103. uint8_t group_id = 0;
  2104. uint32_t nss_comb = 0;
  2105. uint8_t nss_su = 0;
  2106. uint8_t nss_mu[4] = {0};
  2107. uint8_t sgi = 0;
  2108. uint8_t coding = 0;
  2109. uint8_t mcs = 0;
  2110. uint8_t beamformed = 0;
  2111. uint8_t partial_aid = 0;
  2112. status = HAL_MON_MACTX_VHT_SIG_A;
  2113. bandwidth = HAL_TX_DESC_GET_64(tx_tlv,
  2114. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2115. BANDWIDTH);
  2116. is_stbc = HAL_TX_DESC_GET_64(tx_tlv,
  2117. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2118. STBC);
  2119. group_id = HAL_TX_DESC_GET_64(tx_tlv,
  2120. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2121. GROUP_ID);
  2122. /* nss_comb is su nss, MU nss and partial AID */
  2123. nss_comb = HAL_TX_DESC_GET_64(tx_tlv,
  2124. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2125. N_STS);
  2126. /* if it is SU */
  2127. nss_su = (nss_comb & 0x7) + 1;
  2128. /* partial aid - applicable only for SU */
  2129. partial_aid = (nss_comb >> 3) & 0x1F;
  2130. /* if it is MU */
  2131. nss_mu[0] = (nss_comb & 0x7) + 1;
  2132. nss_mu[1] = ((nss_comb >> 3) & 0x7) + 1;
  2133. nss_mu[2] = ((nss_comb >> 6) & 0x7) + 1;
  2134. nss_mu[3] = ((nss_comb >> 9) & 0x7) + 1;
  2135. sgi = HAL_TX_DESC_GET_64(tx_tlv,
  2136. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2137. GI_SETTING);
  2138. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2139. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2140. SU_MU_CODING);
  2141. mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2142. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2143. MCS);
  2144. beamformed = HAL_TX_DESC_GET_64(tx_tlv,
  2145. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2146. BEAMFORMED);
  2147. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  2148. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  2149. TXMON_STATUS_INFO(tx_status_info, sw_frame_group_id) = group_id;
  2150. TXMON_HAL_STATUS(ppdu_info, sgi) = sgi;
  2151. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2152. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2153. TXMON_HAL_STATUS(ppdu_info, beamformed) = beamformed;
  2154. if (group_id == 0 || group_id == 63) {
  2155. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  2156. HAL_RX_TYPE_SU;
  2157. TXMON_HAL_STATUS(ppdu_info, mcs) = mcs;
  2158. TXMON_HAL_STATUS(ppdu_info, nss) =
  2159. nss_su & VHT_SIG_SU_NSS_MASK;
  2160. TXMON_HAL_USER(ppdu_info, user_id,
  2161. vht_flag_values3[0]) = ((mcs << 4) |
  2162. nss_su);
  2163. } else {
  2164. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  2165. HAL_RX_TYPE_MU_MIMO;
  2166. TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs;
  2167. TXMON_HAL_USER(ppdu_info, user_id, nss) =
  2168. nss_su & VHT_SIG_SU_NSS_MASK;
  2169. TXMON_HAL_USER(ppdu_info, user_id,
  2170. vht_flag_values3[0]) = ((mcs << 4) |
  2171. nss_su);
  2172. TXMON_HAL_USER(ppdu_info, user_id,
  2173. vht_flag_values3[1]) = ((mcs << 4) |
  2174. nss_mu[1]);
  2175. TXMON_HAL_USER(ppdu_info, user_id,
  2176. vht_flag_values3[2]) = ((mcs << 4) |
  2177. nss_mu[2]);
  2178. TXMON_HAL_USER(ppdu_info, user_id,
  2179. vht_flag_values3[3]) = ((mcs << 4) |
  2180. nss_mu[3]);
  2181. }
  2182. /* TODO: loop over multiple user */
  2183. TXMON_HAL_USER(ppdu_info, user_id,
  2184. vht_flag_values2) = bandwidth;
  2185. TXMON_HAL_USER(ppdu_info, user_id,
  2186. vht_flag_values4) = coding;
  2187. TXMON_HAL_USER(ppdu_info, user_id,
  2188. vht_flag_values5) = group_id;
  2189. TXMON_HAL_USER(ppdu_info, user_id,
  2190. vht_flag_values6) = partial_aid;
  2191. SHOW_DEFINED(WIFIMACTX_VHT_SIG_A_E);
  2192. break;
  2193. }
  2194. case WIFIMACTX_VHT_SIG_B_MU160_E:
  2195. {
  2196. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU160_E);
  2197. break;
  2198. }
  2199. case WIFIMACTX_VHT_SIG_B_MU80_E:
  2200. {
  2201. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU80_E);
  2202. break;
  2203. }
  2204. case WIFIMACTX_VHT_SIG_B_MU40_E:
  2205. {
  2206. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU40_E);
  2207. break;
  2208. }
  2209. case WIFIMACTX_VHT_SIG_B_MU20_E:
  2210. {
  2211. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU20_E);
  2212. break;
  2213. }
  2214. case WIFIMACTX_VHT_SIG_B_SU160_E:
  2215. {
  2216. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU160_E);
  2217. break;
  2218. }
  2219. case WIFIMACTX_VHT_SIG_B_SU80_E:
  2220. {
  2221. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU80_E);
  2222. break;
  2223. }
  2224. case WIFIMACTX_VHT_SIG_B_SU40_E:
  2225. {
  2226. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU40_E);
  2227. break;
  2228. }
  2229. case WIFIMACTX_VHT_SIG_B_SU20_E:
  2230. {
  2231. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU20_E);
  2232. break;
  2233. }
  2234. case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E:
  2235. {
  2236. SHOW_DEFINED(WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E);
  2237. break;
  2238. }
  2239. case WIFIMACTX_USER_DESC_PER_USER_E:
  2240. {
  2241. /* user tlv */
  2242. uint32_t bf = 0;
  2243. uint32_t psdu_length = 0;
  2244. uint8_t ru_start_index = 0;
  2245. uint8_t ru_size = 0;
  2246. uint8_t nss = 0;
  2247. uint8_t mcs = 0;
  2248. uint8_t dcm = 0;
  2249. uint8_t fec_type = 0;
  2250. uint8_t is_ldpc_extra_symb = 0;
  2251. uint32_t he_data1 = TXMON_HAL_USER(ppdu_info, user_id,
  2252. he_data1);
  2253. uint32_t he_data2 = TXMON_HAL_USER(ppdu_info, user_id,
  2254. he_data2);
  2255. uint32_t he_data3 = TXMON_HAL_USER(ppdu_info, user_id,
  2256. he_data3);
  2257. uint32_t he_data5 = TXMON_HAL_USER(ppdu_info, user_id,
  2258. he_data5);
  2259. uint32_t he_data6 = TXMON_HAL_USER(ppdu_info, user_id,
  2260. he_data6);
  2261. status = HAL_MON_MACTX_USER_DESC_PER_USER;
  2262. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2263. psdu_length = HAL_TX_DESC_GET_64(tx_tlv,
  2264. MACTX_USER_DESC_PER_USER,
  2265. PSDU_LENGTH);
  2266. ru_start_index = HAL_TX_DESC_GET_64(tx_tlv,
  2267. MACTX_USER_DESC_PER_USER,
  2268. RU_START_INDEX);
  2269. ru_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  2270. RU_SIZE);
  2271. bf = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  2272. USER_BF_TYPE);
  2273. nss = HAL_TX_DESC_GET_64(tx_tlv,
  2274. MACTX_USER_DESC_PER_USER, NSS) + 1;
  2275. mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, MCS);
  2276. dcm = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, DCM);
  2277. fec_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  2278. FEC_TYPE);
  2279. is_ldpc_extra_symb =
  2280. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  2281. LDPC_EXTRA_SYMBOL);
  2282. if (!TXMON_HAL_STATUS(ppdu_info, he_flags))
  2283. break;
  2284. /* update */
  2285. /* BEAM CHANGE */
  2286. he_data1 |= QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN;
  2287. he_data1 |= QDF_MON_STATUS_TXBF_KNOWN;
  2288. he_data5 |= (!!bf << QDF_MON_STATUS_TXBF_SHIFT);
  2289. he_data3 |= (!!bf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT);
  2290. /* UL/DL known */
  2291. he_data1 |= QDF_MON_STATUS_HE_DL_UL_KNOWN;
  2292. he_data3 |= (1 << QDF_MON_STATUS_DL_UL_SHIFT);
  2293. /* MCS */
  2294. he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN;
  2295. he_data3 |= (mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT);
  2296. /* DCM */
  2297. he_data1 |= QDF_MON_STATUS_HE_DCM_KNOWN;
  2298. he_data3 |= (dcm << QDF_MON_STATUS_DCM_SHIFT);
  2299. /* LDPC EXTRA SYMB */
  2300. he_data1 |= QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN;
  2301. he_data3 |= (is_ldpc_extra_symb <<
  2302. QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT);
  2303. /* RU offset and RU */
  2304. he_data2 |= QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN;
  2305. he_data2 |= (get_ru_offset_from_start_index(ru_size,
  2306. ru_start_index) <<
  2307. QDF_MON_STATUS_RU_ALLOCATION_SHIFT);
  2308. /* Data BW and RU allocation */
  2309. if (ru_size < HAL_MAX_RU_INDEX) {
  2310. /* update bandwidth if it is full bandwidth */
  2311. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  2312. he_data5 = (he_data5 & 0xFFF0) | (4 + ru_size);
  2313. }
  2314. he_data6 |= (nss & 0xF);
  2315. TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs;
  2316. /* update stack variable to ppdu_info */
  2317. TXMON_HAL_USER(ppdu_info, user_id, he_data1) = he_data1;
  2318. TXMON_HAL_USER(ppdu_info, user_id, he_data2) = he_data2;
  2319. TXMON_HAL_USER(ppdu_info, user_id, he_data3) = he_data3;
  2320. TXMON_HAL_USER(ppdu_info, user_id, he_data5) = he_data5;
  2321. TXMON_HAL_USER(ppdu_info, user_id, he_data6) = he_data6;
  2322. SHOW_DEFINED(WIFIMACTX_USER_DESC_PER_USER_E);
  2323. break;
  2324. }
  2325. case WIFIMACTX_USER_DESC_COMMON_E:
  2326. {
  2327. uint16_t he_mu_flag_1 = 0;
  2328. uint16_t he_mu_flag_2 = 0;
  2329. uint16_t ru_channel_1[4] = {0};
  2330. uint16_t ru_channel_2[4] = {0};
  2331. uint16_t num_users = 0;
  2332. uint8_t doppler;
  2333. uint8_t ltf_size;
  2334. uint8_t num_ltf_symbols;
  2335. uint8_t pkt_extn_pe;
  2336. uint8_t a_factor;
  2337. uint8_t center_ru_0;
  2338. uint8_t center_ru_1;
  2339. uint8_t i = 0;
  2340. num_users = TXMON_HAL(ppdu_info, num_users);
  2341. doppler = HAL_TX_DESC_GET_64(tx_tlv,
  2342. MACTX_USER_DESC_COMMON,
  2343. DOPPLER_INDICATION);
  2344. ltf_size = HAL_TX_DESC_GET_64(tx_tlv,
  2345. MACTX_USER_DESC_COMMON,
  2346. LTF_SIZE);
  2347. num_ltf_symbols = HAL_TX_DESC_GET_64(tx_tlv,
  2348. MACTX_USER_DESC_COMMON,
  2349. NUM_DATA_SYMBOLS);
  2350. pkt_extn_pe = HAL_TX_DESC_GET_64(tx_tlv,
  2351. MACTX_USER_DESC_COMMON,
  2352. PACKET_EXTENSION_PE_DISAMBIGUITY);
  2353. a_factor = HAL_TX_DESC_GET_64(tx_tlv,
  2354. MACTX_USER_DESC_COMMON,
  2355. PACKET_EXTENSION_A_FACTOR);
  2356. center_ru_0 = HAL_TX_DESC_GET_64(tx_tlv,
  2357. MACTX_USER_DESC_COMMON,
  2358. CENTER_RU_0);
  2359. center_ru_1 = HAL_TX_DESC_GET_64(tx_tlv,
  2360. MACTX_USER_DESC_COMMON,
  2361. CENTER_RU_1);
  2362. ru_channel_1[0] = HAL_TX_DESC_GET_64(tx_tlv,
  2363. MACTX_USER_DESC_COMMON,
  2364. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0);
  2365. ru_channel_1[1] = HAL_TX_DESC_GET_64(tx_tlv,
  2366. MACTX_USER_DESC_COMMON,
  2367. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1);
  2368. ru_channel_1[2] = HAL_TX_DESC_GET_64(tx_tlv,
  2369. MACTX_USER_DESC_COMMON,
  2370. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2);
  2371. ru_channel_1[3] = HAL_TX_DESC_GET_64(tx_tlv,
  2372. MACTX_USER_DESC_COMMON,
  2373. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3);
  2374. ru_channel_2[0] = HAL_TX_DESC_GET_64(tx_tlv,
  2375. MACTX_USER_DESC_COMMON,
  2376. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0);
  2377. ru_channel_2[1] = HAL_TX_DESC_GET_64(tx_tlv,
  2378. MACTX_USER_DESC_COMMON,
  2379. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1);
  2380. ru_channel_2[2] = HAL_TX_DESC_GET_64(tx_tlv,
  2381. MACTX_USER_DESC_COMMON,
  2382. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2);
  2383. ru_channel_2[3] = HAL_TX_DESC_GET_64(tx_tlv,
  2384. MACTX_USER_DESC_COMMON,
  2385. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3);
  2386. /* HE data 1 */
  2387. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2388. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  2389. /* HE data 2 */
  2390. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2391. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  2392. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN;
  2393. /* HE data 5 */
  2394. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  2395. (pkt_extn_pe <<
  2396. QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT) |
  2397. (a_factor << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT) |
  2398. ((1 + ltf_size) <<
  2399. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT) |
  2400. (num_ltf_symbols <<
  2401. QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  2402. /* HE data 6 */
  2403. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  2404. (doppler << QDF_MON_STATUS_DOPPLER_SHIFT);
  2405. /* number of symbol */
  2406. he_mu_flag_1 |=
  2407. (QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  2408. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  2409. ((center_ru_0 <<
  2410. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_SHIFT) &
  2411. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_VALUE));
  2412. he_mu_flag_2 |= ((center_ru_1 <<
  2413. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_SHIFT) &
  2414. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_VALUE);
  2415. TXMON_HAL_STATUS(ppdu_info,
  2416. he_mu_flags) = IS_MULTI_USERS(num_users);
  2417. for (i = 0; i < num_users; i++) {
  2418. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2419. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2420. /* channel 1 */
  2421. TXMON_HAL_USER(ppdu_info, i,
  2422. he_RU[0]) = ru_channel_1[0];
  2423. TXMON_HAL_USER(ppdu_info, i,
  2424. he_RU[1]) = ru_channel_1[1];
  2425. TXMON_HAL_USER(ppdu_info, i,
  2426. he_RU[2]) = ru_channel_1[2];
  2427. TXMON_HAL_USER(ppdu_info, i,
  2428. he_RU[3]) = ru_channel_1[3];
  2429. /* channel 2 */
  2430. TXMON_HAL_USER(ppdu_info, i,
  2431. he_RU[4]) = ru_channel_2[0];
  2432. TXMON_HAL_USER(ppdu_info, i,
  2433. he_RU[5]) = ru_channel_2[1];
  2434. TXMON_HAL_USER(ppdu_info, i,
  2435. he_RU[6]) = ru_channel_2[2];
  2436. TXMON_HAL_USER(ppdu_info, i,
  2437. he_RU[7]) = ru_channel_2[3];
  2438. }
  2439. /* channel 1 */
  2440. TXMON_HAL_STATUS(ppdu_info, he_RU[0]) = ru_channel_1[0];
  2441. TXMON_HAL_STATUS(ppdu_info, he_RU[1]) = ru_channel_1[1];
  2442. TXMON_HAL_STATUS(ppdu_info, he_RU[2]) = ru_channel_1[2];
  2443. TXMON_HAL_STATUS(ppdu_info, he_RU[3]) = ru_channel_1[3];
  2444. /* channel 2 */
  2445. TXMON_HAL_STATUS(ppdu_info, he_RU[4]) = ru_channel_2[0];
  2446. TXMON_HAL_STATUS(ppdu_info, he_RU[5]) = ru_channel_2[1];
  2447. TXMON_HAL_STATUS(ppdu_info, he_RU[6]) = ru_channel_2[2];
  2448. TXMON_HAL_STATUS(ppdu_info, he_RU[7]) = ru_channel_2[3];
  2449. /* copy per user info to all user */
  2450. SHOW_DEFINED(WIFIMACTX_USER_DESC_COMMON_E);
  2451. break;
  2452. }
  2453. case WIFIMACTX_PHY_DESC_E:
  2454. {
  2455. /* pkt_type - preamble type */
  2456. uint32_t pkt_type = 0;
  2457. uint8_t bandwidth = 0;
  2458. uint8_t is_stbc = 0;
  2459. uint8_t is_triggered = 0;
  2460. uint8_t gi = 0;
  2461. uint8_t he_ppdu_subtype = 0;
  2462. uint32_t ltf_size = 0;
  2463. uint32_t he_data1 = 0;
  2464. uint32_t he_data2 = 0;
  2465. uint32_t he_data3 = 0;
  2466. uint32_t he_data5 = 0;
  2467. uint16_t he_mu_flag_1 = 0;
  2468. uint16_t he_mu_flag_2 = 0;
  2469. uint16_t num_users = 0;
  2470. uint8_t i = 0;
  2471. status = HAL_MON_MACTX_PHY_DESC;
  2472. num_users = TXMON_HAL(ppdu_info, num_users);
  2473. pkt_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, PKT_TYPE);
  2474. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, STBC);
  2475. is_triggered = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2476. TRIGGERED);
  2477. if (!is_triggered) {
  2478. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2479. BANDWIDTH);
  2480. } else {
  2481. /*
  2482. * is_triggered, bw is minimum of AP pkt bw
  2483. * or STA bw
  2484. */
  2485. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2486. AP_PKT_BW);
  2487. }
  2488. gi = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2489. CP_SETTING);
  2490. ltf_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, LTF_SIZE);
  2491. he_ppdu_subtype = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2492. HE_PPDU_SUBTYPE);
  2493. TXMON_HAL_STATUS(ppdu_info, preamble_type) = pkt_type;
  2494. TXMON_HAL_STATUS(ppdu_info, ltf_size) = ltf_size;
  2495. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2496. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2497. switch (ppdu_info->rx_status.preamble_type) {
  2498. case TXMON_PKT_TYPE_11N_MM:
  2499. TXMON_HAL_STATUS(ppdu_info, ht_flags) = 1;
  2500. TXMON_HAL_STATUS(ppdu_info,
  2501. rtap_flags) |= HT_SGI_PRESENT;
  2502. break;
  2503. case TXMON_PKT_TYPE_11AC:
  2504. TXMON_HAL_STATUS(ppdu_info, vht_flags) = 1;
  2505. break;
  2506. case TXMON_PKT_TYPE_11AX:
  2507. TXMON_HAL_STATUS(ppdu_info, he_flags) = 1;
  2508. break;
  2509. default:
  2510. break;
  2511. }
  2512. if (!TXMON_HAL_STATUS(ppdu_info, he_flags))
  2513. break;
  2514. /* update he flags */
  2515. /* PPDU FORMAT */
  2516. switch (he_ppdu_subtype) {
  2517. case TXMON_HE_SUBTYPE_SU:
  2518. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2519. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  2520. break;
  2521. case TXMON_HE_SUBTYPE_TRIG:
  2522. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2523. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  2524. break;
  2525. case TXMON_HE_SUBTYPE_MU:
  2526. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2527. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  2528. break;
  2529. case TXMON_HE_SUBTYPE_EXT_SU:
  2530. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2531. QDF_MON_STATUS_HE_EXT_SU_FORMAT_TYPE;
  2532. break;
  2533. };
  2534. /* STBC */
  2535. he_data1 |= QDF_MON_STATUS_HE_STBC_KNOWN;
  2536. he_data3 |= (is_stbc << QDF_MON_STATUS_STBC_SHIFT);
  2537. /* GI */
  2538. he_data2 |= QDF_MON_STATUS_HE_GI_KNOWN;
  2539. he_data5 |= (gi << QDF_MON_STATUS_GI_SHIFT);
  2540. /* Data BW and RU allocation */
  2541. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  2542. he_data5 = (he_data5 & 0xFFF0) | bandwidth;
  2543. he_data2 |= QDF_MON_STATUS_LTF_SYMBOLS_KNOWN;
  2544. he_data5 |= ((1 + ltf_size) <<
  2545. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT);
  2546. TXMON_HAL_STATUS(ppdu_info,
  2547. he_mu_flags) = IS_MULTI_USERS(num_users);
  2548. /* MAC TX PHY DESC is not a user tlv */
  2549. for (i = 0; i < num_users; i++) {
  2550. TXMON_HAL_USER(ppdu_info, i, he_data1) = he_data1;
  2551. TXMON_HAL_USER(ppdu_info, i, he_data2) = he_data2;
  2552. TXMON_HAL_USER(ppdu_info, i, he_data3) = he_data3;
  2553. TXMON_HAL_USER(ppdu_info, i, he_data5) = he_data5;
  2554. /* HE MU flags */
  2555. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2556. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2557. }
  2558. SHOW_DEFINED(WIFIMACTX_PHY_DESC_E);
  2559. break;
  2560. }
  2561. case WIFICOEX_RX_STATUS_E:
  2562. {
  2563. SHOW_DEFINED(WIFICOEX_RX_STATUS_E);
  2564. break;
  2565. }
  2566. case WIFIRX_PPDU_ACK_REPORT_E:
  2567. {
  2568. SHOW_DEFINED(WIFIRX_PPDU_ACK_REPORT_E);
  2569. break;
  2570. }
  2571. case WIFIRX_PPDU_NO_ACK_REPORT_E:
  2572. {
  2573. SHOW_DEFINED(WIFIRX_PPDU_NO_ACK_REPORT_E);
  2574. break;
  2575. }
  2576. case WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E:
  2577. {
  2578. SHOW_DEFINED(WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E);
  2579. break;
  2580. }
  2581. case WIFITXPCU_PHYTX_DEBUG32_E:
  2582. {
  2583. SHOW_DEFINED(WIFITXPCU_PHYTX_DEBUG32_E);
  2584. break;
  2585. }
  2586. case WIFITXPCU_PREAMBLE_DONE_E:
  2587. {
  2588. SHOW_DEFINED(WIFITXPCU_PREAMBLE_DONE_E);
  2589. break;
  2590. }
  2591. case WIFIRX_PHY_SLEEP_E:
  2592. {
  2593. SHOW_DEFINED(WIFIRX_PHY_SLEEP_E);
  2594. break;
  2595. }
  2596. case WIFIRX_FRAME_BITMAP_REQ_E:
  2597. {
  2598. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_REQ_E);
  2599. break;
  2600. }
  2601. case WIFIRXPCU_TX_SETUP_CLEAR_E:
  2602. {
  2603. SHOW_DEFINED(WIFIRXPCU_TX_SETUP_CLEAR_E);
  2604. break;
  2605. }
  2606. case WIFIRX_TRIG_INFO_E:
  2607. {
  2608. SHOW_DEFINED(WIFIRX_TRIG_INFO_E);
  2609. break;
  2610. }
  2611. case WIFIEXPECTED_RESPONSE_E:
  2612. {
  2613. SHOW_DEFINED(WIFIEXPECTED_RESPONSE_E);
  2614. break;
  2615. }
  2616. case WIFITRIGGER_RESPONSE_TX_DONE_E:
  2617. {
  2618. SHOW_DEFINED(WIFITRIGGER_RESPONSE_TX_DONE_E);
  2619. break;
  2620. }
  2621. case WIFIFW2SW_MON_E:
  2622. {
  2623. /* parse fw2sw tlv */
  2624. hal_txmon_parse_fw2sw(tx_tlv, tlv_user_id, data_status_info);
  2625. status = HAL_MON_TX_FW2SW;
  2626. SHOW_DEFINED(WIFIFW2SW_MON_E);
  2627. break;
  2628. }
  2629. }
  2630. return status;
  2631. }
  2632. #endif /* QCA_MONITOR_2_0_SUPPORT */
  2633. #ifdef REO_SHARED_QREF_TABLE_EN
  2634. static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl)
  2635. {
  2636. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2637. uint32_t reg_val = 0;
  2638. /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers
  2639. * of 37 peer/tids
  2640. */
  2641. reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE));
  2642. reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1);
  2643. HAL_REG_WRITE(hal,
  2644. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  2645. reg_val);
  2646. /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers
  2647. * of 37 peer/tids
  2648. */
  2649. reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1));
  2650. HAL_REG_WRITE(hal,
  2651. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  2652. reg_val);
  2653. hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of"
  2654. "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back"
  2655. "to erase stale entries in reo storage: regval:%x", hal, reg_val);
  2656. }
  2657. /* hal_reo_shared_qaddr_write(): Write REO tid queue addr
  2658. * LUT shared by SW and HW at the index given by peer id
  2659. * and tid.
  2660. *
  2661. * @hal_soc: hal soc pointer
  2662. * @reo_qref_addr: pointer to index pointed to be peer_id
  2663. * and tid
  2664. * @tid: tid queue number
  2665. * @hw_qdesc_paddr: reo queue addr
  2666. */
  2667. static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl,
  2668. uint16_t peer_id,
  2669. int tid,
  2670. qdf_dma_addr_t hw_qdesc_paddr)
  2671. {
  2672. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2673. struct rx_reo_queue_reference *reo_qref;
  2674. uint32_t peer_tid_idx;
  2675. /* Plug hw_desc_addr in Host reo queue reference table */
  2676. if (HAL_PEER_ID_IS_MLO(peer_id)) {
  2677. peer_tid_idx = ((peer_id - HAL_ML_PEER_ID_START) *
  2678. DP_MAX_TIDS) + tid;
  2679. reo_qref = (struct rx_reo_queue_reference *)
  2680. &hal->reo_qref.mlo_reo_qref_table_vaddr[peer_tid_idx];
  2681. } else {
  2682. peer_tid_idx = (peer_id * DP_MAX_TIDS) + tid;
  2683. reo_qref = (struct rx_reo_queue_reference *)
  2684. &hal->reo_qref.non_mlo_reo_qref_table_vaddr[peer_tid_idx];
  2685. }
  2686. reo_qref->rx_reo_queue_desc_addr_31_0 =
  2687. hw_qdesc_paddr & 0xffffffff;
  2688. reo_qref->rx_reo_queue_desc_addr_39_32 =
  2689. (hw_qdesc_paddr & 0xff00000000) >> 32;
  2690. if (hw_qdesc_paddr != 0)
  2691. reo_qref->receive_queue_number = tid;
  2692. else
  2693. reo_qref->receive_queue_number = 0;
  2694. hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl);
  2695. hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK,"
  2696. "rx_reo_queue_desc_addr_31_0: %x,"
  2697. "rx_reo_queue_desc_addr_39_32: %x",
  2698. (void *)hw_qdesc_paddr, tid, reo_qref,
  2699. reo_qref->rx_reo_queue_desc_addr_31_0,
  2700. reo_qref->rx_reo_queue_desc_addr_39_32);
  2701. }
  2702. /**
  2703. * hal_reo_shared_qaddr_setup() - Allocate MLO and Non MLO reo queue
  2704. * reference table shared between SW and HW and initialize in Qdesc Base0
  2705. * base1 registers provided by HW.
  2706. *
  2707. * @hal_soc: HAL Soc handle
  2708. *
  2709. * Return: None
  2710. */
  2711. static void hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl)
  2712. {
  2713. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2714. hal->reo_qref.reo_qref_table_en = 1;
  2715. hal->reo_qref.mlo_reo_qref_table_vaddr =
  2716. (uint64_t *)qdf_mem_alloc_consistent(
  2717. hal->qdf_dev, hal->qdf_dev->dev,
  2718. REO_QUEUE_REF_ML_TABLE_SIZE,
  2719. &hal->reo_qref.mlo_reo_qref_table_paddr);
  2720. hal->reo_qref.non_mlo_reo_qref_table_vaddr =
  2721. (uint64_t *)qdf_mem_alloc_consistent(
  2722. hal->qdf_dev, hal->qdf_dev->dev,
  2723. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  2724. &hal->reo_qref.non_mlo_reo_qref_table_paddr);
  2725. hal_verbose_debug("MLO table start paddr:%pK,"
  2726. "Non-MLO table start paddr:%pK,"
  2727. "MLO table start vaddr: %pK,"
  2728. "Non MLO table start vaddr: %pK",
  2729. (void *)hal->reo_qref.mlo_reo_qref_table_paddr,
  2730. (void *)hal->reo_qref.non_mlo_reo_qref_table_paddr,
  2731. hal->reo_qref.mlo_reo_qref_table_vaddr,
  2732. hal->reo_qref.non_mlo_reo_qref_table_vaddr);
  2733. }
  2734. /**
  2735. * hal_reo_shared_qaddr_init() - Zero out REO qref LUT and
  2736. * write start addr of MLO and Non MLO table in HW
  2737. *
  2738. * @hal_soc: HAL Soc handle
  2739. * @qref_reset: reset qref LUT
  2740. *
  2741. * Return: None
  2742. */
  2743. static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl,
  2744. int qref_reset)
  2745. {
  2746. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2747. if (qref_reset) {
  2748. qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr,
  2749. REO_QUEUE_REF_ML_TABLE_SIZE);
  2750. qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr,
  2751. REO_QUEUE_REF_NON_ML_TABLE_SIZE);
  2752. }
  2753. /* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address
  2754. * and lower 8 bits to be 0. Shift the physical address by 8 to plug
  2755. * upper 32bits only
  2756. */
  2757. HAL_REG_WRITE(hal,
  2758. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  2759. hal->reo_qref.non_mlo_reo_qref_table_paddr >> 8);
  2760. HAL_REG_WRITE(hal,
  2761. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  2762. hal->reo_qref.mlo_reo_qref_table_paddr >> 8);
  2763. HAL_REG_WRITE(hal,
  2764. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  2765. HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE,
  2766. 1));
  2767. HAL_REG_WRITE(hal,
  2768. HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE),
  2769. HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED,
  2770. 0x1fff));
  2771. }
  2772. /**
  2773. * hal_reo_shared_qaddr_detach() - Free MLO and Non MLO reo queue
  2774. * reference table shared between SW and HW
  2775. *
  2776. * @hal_soc: HAL Soc handle
  2777. *
  2778. * Return: None
  2779. */
  2780. static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl)
  2781. {
  2782. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2783. HAL_REG_WRITE(hal,
  2784. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  2785. 0);
  2786. HAL_REG_WRITE(hal,
  2787. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  2788. 0);
  2789. qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
  2790. REO_QUEUE_REF_ML_TABLE_SIZE,
  2791. hal->reo_qref.mlo_reo_qref_table_vaddr,
  2792. hal->reo_qref.mlo_reo_qref_table_paddr, 0);
  2793. qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
  2794. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  2795. hal->reo_qref.non_mlo_reo_qref_table_vaddr,
  2796. hal->reo_qref.non_mlo_reo_qref_table_paddr, 0);
  2797. }
  2798. #endif
  2799. /**
  2800. * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing
  2801. * @hal_soc: HAL SoC context
  2802. * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM
  2803. * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW
  2804. *
  2805. * Return: void
  2806. */
  2807. #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK
  2808. static inline void
  2809. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  2810. enum hal_tx_vdev_mismatch_notify
  2811. config)
  2812. {
  2813. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2814. uint32_t reg_addr, reg_val = 0;
  2815. uint32_t val = 0;
  2816. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  2817. val = HAL_REG_READ(hal_soc, reg_addr);
  2818. /* reset the corresponding bits in register */
  2819. val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK));
  2820. /* set config value */
  2821. reg_val = val | (config <<
  2822. HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT);
  2823. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  2824. }
  2825. #else
  2826. static inline void
  2827. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  2828. enum hal_tx_vdev_mismatch_notify
  2829. config)
  2830. {
  2831. }
  2832. #endif
  2833. /**
  2834. * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing
  2835. * @hal_soc: HAL SoC context
  2836. * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW
  2837. * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM
  2838. *
  2839. * Return: void
  2840. */
  2841. #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \
  2842. defined(WLAN_MCAST_MLO)
  2843. static inline void
  2844. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  2845. hal_soc_handle_t hal_soc_hdl,
  2846. enum hal_tx_mcast_mlo_reinject_notify config)
  2847. {
  2848. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2849. uint32_t reg_addr, reg_val = 0;
  2850. uint32_t val = 0;
  2851. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  2852. val = HAL_REG_READ(hal_soc, reg_addr);
  2853. /* reset the corresponding bits in register */
  2854. val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK));
  2855. /* set config value */
  2856. reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT);
  2857. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  2858. }
  2859. #else
  2860. static inline void
  2861. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  2862. hal_soc_handle_t hal_soc_hdl,
  2863. enum hal_tx_mcast_mlo_reinject_notify config)
  2864. {
  2865. }
  2866. #endif
  2867. /**
  2868. * hal_get_ba_aging_timeout_be - Get BA Aging timeout
  2869. *
  2870. * @hal_soc: Opaque HAL SOC handle
  2871. * @ac: Access category
  2872. * @value: window size to get
  2873. */
  2874. static inline
  2875. void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  2876. uint8_t ac, uint32_t *value)
  2877. {
  2878. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  2879. switch (ac) {
  2880. case WME_AC_BE:
  2881. *value = HAL_REG_READ(soc,
  2882. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  2883. REO_REG_REG_BASE)) / 1000;
  2884. break;
  2885. case WME_AC_BK:
  2886. *value = HAL_REG_READ(soc,
  2887. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  2888. REO_REG_REG_BASE)) / 1000;
  2889. break;
  2890. case WME_AC_VI:
  2891. *value = HAL_REG_READ(soc,
  2892. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  2893. REO_REG_REG_BASE)) / 1000;
  2894. break;
  2895. case WME_AC_VO:
  2896. *value = HAL_REG_READ(soc,
  2897. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  2898. REO_REG_REG_BASE)) / 1000;
  2899. break;
  2900. default:
  2901. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2902. "Invalid AC: %d\n", ac);
  2903. }
  2904. }
  2905. /**
  2906. * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the
  2907. * buffer list provided
  2908. *
  2909. * @hal_soc: Opaque HAL SOC handle
  2910. * @scatter_bufs_base_paddr: Array of physical base addresses
  2911. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  2912. * @num_scatter_bufs: Number of scatter buffers in the above lists
  2913. * @scatter_buf_size: Size of each scatter buffer
  2914. * @last_buf_end_offset: Offset to the last entry
  2915. * @num_entries: Total entries of all scatter bufs
  2916. *
  2917. * Return: None
  2918. */
  2919. static inline void
  2920. hal_setup_link_idle_list_generic_be(struct hal_soc *soc,
  2921. qdf_dma_addr_t scatter_bufs_base_paddr[],
  2922. void *scatter_bufs_base_vaddr[],
  2923. uint32_t num_scatter_bufs,
  2924. uint32_t scatter_buf_size,
  2925. uint32_t last_buf_end_offset,
  2926. uint32_t num_entries)
  2927. {
  2928. int i;
  2929. uint32_t *prev_buf_link_ptr = NULL;
  2930. uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
  2931. uint32_t val;
  2932. /* Link the scatter buffers */
  2933. for (i = 0; i < num_scatter_bufs; i++) {
  2934. if (i > 0) {
  2935. prev_buf_link_ptr[0] =
  2936. scatter_bufs_base_paddr[i] & 0xffffffff;
  2937. prev_buf_link_ptr[1] = HAL_SM(
  2938. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2939. BASE_ADDRESS_39_32,
  2940. ((uint64_t)(scatter_bufs_base_paddr[i])
  2941. >> 32)) | HAL_SM(
  2942. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2943. ADDRESS_MATCH_TAG,
  2944. ADDRESS_MATCH_TAG_VAL);
  2945. }
  2946. prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
  2947. scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
  2948. }
  2949. /* TBD: Register programming partly based on MLD & the rest based on
  2950. * inputs from HW team. Not complete yet.
  2951. */
  2952. reg_scatter_buf_size = (scatter_buf_size -
  2953. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
  2954. reg_tot_scatter_buf_size = ((scatter_buf_size -
  2955. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
  2956. HAL_REG_WRITE(soc,
  2957. HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(
  2958. WBM_REG_REG_BASE),
  2959. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE,
  2960. reg_scatter_buf_size) |
  2961. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE,
  2962. 0x1));
  2963. HAL_REG_WRITE(soc,
  2964. HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(
  2965. WBM_REG_REG_BASE),
  2966. HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
  2967. SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
  2968. reg_tot_scatter_buf_size));
  2969. HAL_REG_WRITE(soc,
  2970. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(
  2971. WBM_REG_REG_BASE),
  2972. scatter_bufs_base_paddr[0] & 0xffffffff);
  2973. HAL_REG_WRITE(soc,
  2974. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  2975. WBM_REG_REG_BASE),
  2976. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
  2977. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
  2978. HAL_REG_WRITE(soc,
  2979. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  2980. WBM_REG_REG_BASE),
  2981. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2982. BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0])
  2983. >> 32)) |
  2984. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2985. ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
  2986. /* ADDRESS_MATCH_TAG field in the above register is expected to match
  2987. * with the upper bits of link pointer. The above write sets this field
  2988. * to zero and we are also setting the upper bits of link pointers to
  2989. * zero while setting up the link list of scatter buffers above
  2990. */
  2991. /* Setup head and tail pointers for the idle list */
  2992. HAL_REG_WRITE(soc,
  2993. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  2994. WBM_REG_REG_BASE),
  2995. scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff);
  2996. HAL_REG_WRITE(soc,
  2997. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(
  2998. WBM_REG_REG_BASE),
  2999. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  3000. BUFFER_ADDRESS_39_32,
  3001. ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1])
  3002. >> 32)) |
  3003. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  3004. HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
  3005. HAL_REG_WRITE(soc,
  3006. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  3007. WBM_REG_REG_BASE),
  3008. scatter_bufs_base_paddr[0] & 0xffffffff);
  3009. HAL_REG_WRITE(soc,
  3010. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(
  3011. WBM_REG_REG_BASE),
  3012. scatter_bufs_base_paddr[0] & 0xffffffff);
  3013. HAL_REG_WRITE(soc,
  3014. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(
  3015. WBM_REG_REG_BASE),
  3016. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  3017. BUFFER_ADDRESS_39_32,
  3018. ((uint64_t)(scatter_bufs_base_paddr[0]) >>
  3019. 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  3020. TAIL_POINTER_OFFSET, 0));
  3021. HAL_REG_WRITE(soc,
  3022. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(
  3023. WBM_REG_REG_BASE),
  3024. 2 * num_entries);
  3025. /* Set RING_ID_DISABLE */
  3026. val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
  3027. /*
  3028. * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
  3029. * check the presence of the bit before toggling it.
  3030. */
  3031. #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
  3032. val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
  3033. #endif
  3034. HAL_REG_WRITE(soc,
  3035. HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE),
  3036. val);
  3037. }
  3038. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  3039. #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000
  3040. #endif
  3041. /**
  3042. * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register
  3043. * for REO/WBM
  3044. * @soc: HAL soc handle
  3045. * @cc_cfg: structure pointer for HW cookie conversion configuration
  3046. *
  3047. * Return: None
  3048. */
  3049. static inline
  3050. void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl,
  3051. struct hal_hw_cc_config *cc_cfg)
  3052. {
  3053. uint32_t reg_addr, reg_val = 0;
  3054. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3055. /* REO CFG */
  3056. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE);
  3057. reg_val = cc_cfg->lut_base_addr_31_0;
  3058. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3059. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE);
  3060. reg_val = 0;
  3061. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3062. SW_COOKIE_CONVERT_GLOBAL_ENABLE,
  3063. cc_cfg->cc_global_en);
  3064. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3065. SW_COOKIE_CONVERT_ENABLE,
  3066. cc_cfg->cc_global_en);
  3067. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3068. PAGE_ALIGNMENT,
  3069. cc_cfg->page_4k_align);
  3070. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3071. COOKIE_OFFSET_MSB,
  3072. cc_cfg->cookie_offset_msb);
  3073. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3074. COOKIE_PAGE_MSB,
  3075. cc_cfg->cookie_page_msb);
  3076. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3077. CMEM_LUT_BASE_ADDR_39_32,
  3078. cc_cfg->lut_base_addr_39_32);
  3079. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3080. /* WBM CFG */
  3081. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE);
  3082. reg_val = cc_cfg->lut_base_addr_31_0;
  3083. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3084. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE);
  3085. reg_val = 0;
  3086. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3087. PAGE_ALIGNMENT,
  3088. cc_cfg->page_4k_align);
  3089. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3090. COOKIE_OFFSET_MSB,
  3091. cc_cfg->cookie_offset_msb);
  3092. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3093. COOKIE_PAGE_MSB,
  3094. cc_cfg->cookie_page_msb);
  3095. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3096. CMEM_LUT_BASE_ADDR_39_32,
  3097. cc_cfg->lut_base_addr_39_32);
  3098. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3099. /*
  3100. * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE,
  3101. */
  3102. reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE);
  3103. reg_val = 0;
  3104. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3105. WBM_COOKIE_CONV_GLOBAL_ENABLE,
  3106. cc_cfg->cc_global_en);
  3107. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3108. WBM2SW6_COOKIE_CONVERSION_EN,
  3109. cc_cfg->wbm2sw6_cc_en);
  3110. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3111. WBM2SW5_COOKIE_CONVERSION_EN,
  3112. cc_cfg->wbm2sw5_cc_en);
  3113. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3114. WBM2SW4_COOKIE_CONVERSION_EN,
  3115. cc_cfg->wbm2sw4_cc_en);
  3116. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3117. WBM2SW3_COOKIE_CONVERSION_EN,
  3118. cc_cfg->wbm2sw3_cc_en);
  3119. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3120. WBM2SW2_COOKIE_CONVERSION_EN,
  3121. cc_cfg->wbm2sw2_cc_en);
  3122. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3123. WBM2SW1_COOKIE_CONVERSION_EN,
  3124. cc_cfg->wbm2sw1_cc_en);
  3125. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3126. WBM2SW0_COOKIE_CONVERSION_EN,
  3127. cc_cfg->wbm2sw0_cc_en);
  3128. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3129. WBM2FW_COOKIE_CONVERSION_EN,
  3130. cc_cfg->wbm2fw_cc_en);
  3131. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3132. #ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK
  3133. reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE);
  3134. reg_val = 0;
  3135. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3136. COOKIE_DEBUG_SEL,
  3137. cc_cfg->cc_global_en);
  3138. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3139. COOKIE_CONV_INDICATION_EN,
  3140. cc_cfg->cc_global_en);
  3141. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3142. ERROR_PATH_COOKIE_CONV_EN,
  3143. cc_cfg->error_path_cookie_conv_en);
  3144. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3145. RELEASE_PATH_COOKIE_CONV_EN,
  3146. cc_cfg->release_path_cookie_conv_en);
  3147. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3148. #endif
  3149. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  3150. /*
  3151. * To enable indication for HW cookie conversion done or not for
  3152. * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th
  3153. * bit spare_control[15] should be set.
  3154. */
  3155. reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE);
  3156. reg_val = HAL_REG_READ(soc, reg_addr);
  3157. reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL,
  3158. SPARE_CONTROL,
  3159. HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15);
  3160. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3161. #endif
  3162. }
  3163. /**
  3164. * hal_set_ba_aging_timeout_be - Set BA Aging timeout
  3165. *
  3166. * @hal_soc: Opaque HAL SOC handle
  3167. * @ac: Access category
  3168. * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice
  3169. * @value: Input value to set
  3170. */
  3171. static inline
  3172. void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  3173. uint8_t ac, uint32_t value)
  3174. {
  3175. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3176. switch (ac) {
  3177. case WME_AC_BE:
  3178. HAL_REG_WRITE(soc,
  3179. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  3180. REO_REG_REG_BASE),
  3181. value * 1000);
  3182. break;
  3183. case WME_AC_BK:
  3184. HAL_REG_WRITE(soc,
  3185. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  3186. REO_REG_REG_BASE),
  3187. value * 1000);
  3188. break;
  3189. case WME_AC_VI:
  3190. HAL_REG_WRITE(soc,
  3191. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  3192. REO_REG_REG_BASE),
  3193. value * 1000);
  3194. break;
  3195. case WME_AC_VO:
  3196. HAL_REG_WRITE(soc,
  3197. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  3198. REO_REG_REG_BASE),
  3199. value * 1000);
  3200. break;
  3201. default:
  3202. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3203. "Invalid AC: %d\n", ac);
  3204. }
  3205. }
  3206. /**
  3207. * hal_tx_populate_bank_register() - populate the bank register with
  3208. * the software configs.
  3209. * @soc: HAL soc handle
  3210. * @config: bank config
  3211. * @bank_id: bank id to be configured
  3212. *
  3213. * Returns: None
  3214. */
  3215. #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT
  3216. static inline void
  3217. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  3218. union hal_tx_bank_config *config,
  3219. uint8_t bank_id)
  3220. {
  3221. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3222. uint32_t reg_addr, reg_val = 0;
  3223. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  3224. bank_id);
  3225. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  3226. reg_val |= (config->encap_type <<
  3227. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  3228. reg_val |= (config->encrypt_type <<
  3229. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  3230. reg_val |= (config->src_buffer_swap <<
  3231. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  3232. reg_val |= (config->link_meta_swap <<
  3233. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  3234. reg_val |= (config->index_lookup_enable <<
  3235. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  3236. reg_val |= (config->addrx_en <<
  3237. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  3238. reg_val |= (config->addry_en <<
  3239. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  3240. reg_val |= (config->mesh_enable <<
  3241. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  3242. reg_val |= (config->vdev_id_check_en <<
  3243. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  3244. reg_val |= (config->pmac_id <<
  3245. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  3246. reg_val |= (config->mcast_pkt_ctrl <<
  3247. HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
  3248. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3249. }
  3250. #else
  3251. static inline void
  3252. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  3253. union hal_tx_bank_config *config,
  3254. uint8_t bank_id)
  3255. {
  3256. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3257. uint32_t reg_addr, reg_val = 0;
  3258. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  3259. bank_id);
  3260. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  3261. reg_val |= (config->encap_type <<
  3262. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  3263. reg_val |= (config->encrypt_type <<
  3264. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  3265. reg_val |= (config->src_buffer_swap <<
  3266. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  3267. reg_val |= (config->link_meta_swap <<
  3268. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  3269. reg_val |= (config->index_lookup_enable <<
  3270. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  3271. reg_val |= (config->addrx_en <<
  3272. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  3273. reg_val |= (config->addry_en <<
  3274. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  3275. reg_val |= (config->mesh_enable <<
  3276. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  3277. reg_val |= (config->vdev_id_check_en <<
  3278. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  3279. reg_val |= (config->pmac_id <<
  3280. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  3281. reg_val |= (config->dscp_tid_map_id <<
  3282. HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT);
  3283. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3284. }
  3285. #endif
  3286. #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
  3287. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4)
  3288. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF)
  3289. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3
  3290. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2
  3291. /**
  3292. * hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value
  3293. * @hal_soc: HAL SoC context
  3294. * @mcast_ctrl_val: mcast ctrl value for this VAP
  3295. *
  3296. * Return: void
  3297. */
  3298. static inline void
  3299. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  3300. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  3301. {
  3302. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3303. uint32_t reg_addr, reg_val = 0;
  3304. uint32_t val;
  3305. uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id);
  3306. uint8_t index_in_reg =
  3307. HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id);
  3308. reg_addr =
  3309. HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE,
  3310. reg_idx);
  3311. val = HAL_REG_READ(hal_soc, reg_addr);
  3312. /* mask out other stored value */
  3313. val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK <<
  3314. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)));
  3315. reg_val = val |
  3316. ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) <<
  3317. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg));
  3318. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3319. }
  3320. #else
  3321. static inline void
  3322. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  3323. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  3324. {
  3325. }
  3326. #endif
  3327. #endif /* _HAL_BE_GENERIC_API_H_ */