dp_tx.c 108 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "enet.h"
  33. #include "dp_internal.h"
  34. #ifdef FEATURE_WDS
  35. #include "dp_txrx_wds.h"
  36. #endif
  37. #ifdef ATH_SUPPORT_IQUE
  38. #include "dp_txrx_me.h"
  39. #endif
  40. /* TODO Add support in TSO */
  41. #define DP_DESC_NUM_FRAG(x) 0
  42. /* disable TQM_BYPASS */
  43. #define TQM_BYPASS_WAR 0
  44. /* invalid peer id for reinject*/
  45. #define DP_INVALID_PEER 0XFFFE
  46. /*mapping between hal encrypt type and cdp_sec_type*/
  47. #define MAX_CDP_SEC_TYPE 12
  48. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  49. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  50. HAL_TX_ENCRYPT_TYPE_WEP_128,
  51. HAL_TX_ENCRYPT_TYPE_WEP_104,
  52. HAL_TX_ENCRYPT_TYPE_WEP_40,
  53. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  55. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  56. HAL_TX_ENCRYPT_TYPE_WAPI,
  57. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  58. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  60. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  61. #if defined(FEATURE_TSO)
  62. /**
  63. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  64. *
  65. * @soc - core txrx main context
  66. * @seg_desc - tso segment descriptor
  67. * @num_seg_desc - tso number segment descriptor
  68. */
  69. static void dp_tx_tso_unmap_segment(
  70. struct dp_soc *soc,
  71. struct qdf_tso_seg_elem_t *seg_desc,
  72. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  73. {
  74. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  75. if (qdf_unlikely(!seg_desc)) {
  76. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  77. __func__, __LINE__);
  78. qdf_assert(0);
  79. } else if (qdf_unlikely(!num_seg_desc)) {
  80. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  81. __func__, __LINE__);
  82. qdf_assert(0);
  83. } else {
  84. bool is_last_seg;
  85. /* no tso segment left to do dma unmap */
  86. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  87. return;
  88. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  89. true : false;
  90. qdf_nbuf_unmap_tso_segment(soc->osdev,
  91. seg_desc, is_last_seg);
  92. num_seg_desc->num_seg.tso_cmn_num_seg--;
  93. }
  94. }
  95. /**
  96. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  97. * back to the freelist
  98. *
  99. * @soc - soc device handle
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  106. if (qdf_unlikely(!tx_desc->tso_desc)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO num desc is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  119. /* Add the tso num segment into the free list */
  120. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  121. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  122. tx_desc->tso_num_desc);
  123. tx_desc->tso_num_desc = NULL;
  124. }
  125. /* Add the tso segment into the free list*/
  126. dp_tx_tso_desc_free(soc,
  127. tx_desc->pool_id, tx_desc->tso_desc);
  128. tx_desc->tso_desc = NULL;
  129. }
  130. }
  131. #else
  132. static void dp_tx_tso_unmap_segment(
  133. struct dp_soc *soc,
  134. struct qdf_tso_seg_elem_t *seg_desc,
  135. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  136. {
  137. }
  138. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  139. struct dp_tx_desc_s *tx_desc)
  140. {
  141. }
  142. #endif
  143. /**
  144. * dp_tx_desc_release() - Release Tx Descriptor
  145. * @tx_desc : Tx Descriptor
  146. * @desc_pool_id: Descriptor Pool ID
  147. *
  148. * Deallocate all resources attached to Tx descriptor and free the Tx
  149. * descriptor.
  150. *
  151. * Return:
  152. */
  153. static void
  154. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  155. {
  156. struct dp_pdev *pdev = tx_desc->pdev;
  157. struct dp_soc *soc;
  158. uint8_t comp_status = 0;
  159. qdf_assert(pdev);
  160. soc = pdev->soc;
  161. if (tx_desc->frm_type == dp_tx_frm_tso)
  162. dp_tx_tso_desc_release(soc, tx_desc);
  163. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  164. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  165. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  166. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  167. qdf_atomic_dec(&pdev->num_tx_outstanding);
  168. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  169. qdf_atomic_dec(&pdev->num_tx_exception);
  170. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  171. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  172. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  173. soc->hal_soc);
  174. else
  175. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  176. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  177. "Tx Completion Release desc %d status %d outstanding %d",
  178. tx_desc->id, comp_status,
  179. qdf_atomic_read(&pdev->num_tx_outstanding));
  180. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  181. return;
  182. }
  183. /**
  184. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  185. * @vdev: DP vdev Handle
  186. * @nbuf: skb
  187. * @msdu_info: msdu_info required to create HTT metadata
  188. *
  189. * Prepares and fills HTT metadata in the frame pre-header for special frames
  190. * that should be transmitted using varying transmit parameters.
  191. * There are 2 VDEV modes that currently needs this special metadata -
  192. * 1) Mesh Mode
  193. * 2) DSRC Mode
  194. *
  195. * Return: HTT metadata size
  196. *
  197. */
  198. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  199. struct dp_tx_msdu_info_s *msdu_info)
  200. {
  201. uint32_t *meta_data = msdu_info->meta_data;
  202. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  203. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  204. uint8_t htt_desc_size;
  205. /* Size rounded of multiple of 8 bytes */
  206. uint8_t htt_desc_size_aligned;
  207. uint8_t *hdr = NULL;
  208. /*
  209. * Metadata - HTT MSDU Extension header
  210. */
  211. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  212. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  213. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer) {
  214. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  215. htt_desc_size_aligned)) {
  216. DP_STATS_INC(vdev,
  217. tx_i.dropped.headroom_insufficient, 1);
  218. return 0;
  219. }
  220. /* Fill and add HTT metaheader */
  221. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  222. if (!hdr) {
  223. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  224. "Error in filling HTT metadata");
  225. return 0;
  226. }
  227. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  228. } else if (vdev->opmode == wlan_op_mode_ocb) {
  229. /* Todo - Add support for DSRC */
  230. }
  231. return htt_desc_size_aligned;
  232. }
  233. /**
  234. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  235. * @tso_seg: TSO segment to process
  236. * @ext_desc: Pointer to MSDU extension descriptor
  237. *
  238. * Return: void
  239. */
  240. #if defined(FEATURE_TSO)
  241. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  242. void *ext_desc)
  243. {
  244. uint8_t num_frag;
  245. uint32_t tso_flags;
  246. /*
  247. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  248. * tcp_flag_mask
  249. *
  250. * Checksum enable flags are set in TCL descriptor and not in Extension
  251. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  252. */
  253. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  254. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  255. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  256. tso_seg->tso_flags.ip_len);
  257. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  258. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  259. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  260. uint32_t lo = 0;
  261. uint32_t hi = 0;
  262. qdf_dmaaddr_to_32s(
  263. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  264. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  265. tso_seg->tso_frags[num_frag].length);
  266. }
  267. return;
  268. }
  269. #else
  270. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  271. void *ext_desc)
  272. {
  273. return;
  274. }
  275. #endif
  276. #if defined(FEATURE_TSO)
  277. /**
  278. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  279. * allocated and free them
  280. *
  281. * @soc: soc handle
  282. * @free_seg: list of tso segments
  283. * @msdu_info: msdu descriptor
  284. *
  285. * Return - void
  286. */
  287. static void dp_tx_free_tso_seg_list(
  288. struct dp_soc *soc,
  289. struct qdf_tso_seg_elem_t *free_seg,
  290. struct dp_tx_msdu_info_s *msdu_info)
  291. {
  292. struct qdf_tso_seg_elem_t *next_seg;
  293. while (free_seg) {
  294. next_seg = free_seg->next;
  295. dp_tx_tso_desc_free(soc,
  296. msdu_info->tx_queue.desc_pool_id,
  297. free_seg);
  298. free_seg = next_seg;
  299. }
  300. }
  301. /**
  302. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  303. * allocated and free them
  304. *
  305. * @soc: soc handle
  306. * @free_num_seg: list of tso number segments
  307. * @msdu_info: msdu descriptor
  308. * Return - void
  309. */
  310. static void dp_tx_free_tso_num_seg_list(
  311. struct dp_soc *soc,
  312. struct qdf_tso_num_seg_elem_t *free_num_seg,
  313. struct dp_tx_msdu_info_s *msdu_info)
  314. {
  315. struct qdf_tso_num_seg_elem_t *next_num_seg;
  316. while (free_num_seg) {
  317. next_num_seg = free_num_seg->next;
  318. dp_tso_num_seg_free(soc,
  319. msdu_info->tx_queue.desc_pool_id,
  320. free_num_seg);
  321. free_num_seg = next_num_seg;
  322. }
  323. }
  324. /**
  325. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  326. * do dma unmap for each segment
  327. *
  328. * @soc: soc handle
  329. * @free_seg: list of tso segments
  330. * @num_seg_desc: tso number segment descriptor
  331. *
  332. * Return - void
  333. */
  334. static void dp_tx_unmap_tso_seg_list(
  335. struct dp_soc *soc,
  336. struct qdf_tso_seg_elem_t *free_seg,
  337. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  338. {
  339. struct qdf_tso_seg_elem_t *next_seg;
  340. if (qdf_unlikely(!num_seg_desc)) {
  341. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  342. return;
  343. }
  344. while (free_seg) {
  345. next_seg = free_seg->next;
  346. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  347. free_seg = next_seg;
  348. }
  349. }
  350. /**
  351. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  352. * free the tso segments descriptor and
  353. * tso num segments descriptor
  354. *
  355. * @soc: soc handle
  356. * @msdu_info: msdu descriptor
  357. * @tso_seg_unmap: flag to show if dma unmap is necessary
  358. *
  359. * Return - void
  360. */
  361. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  362. struct dp_tx_msdu_info_s *msdu_info,
  363. bool tso_seg_unmap)
  364. {
  365. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  366. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  367. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  368. tso_info->tso_num_seg_list;
  369. /* do dma unmap for each segment */
  370. if (tso_seg_unmap)
  371. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  372. /* free all tso number segment descriptor though looks only have 1 */
  373. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  374. /* free all tso segment descriptor */
  375. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  376. }
  377. /**
  378. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  379. * @vdev: virtual device handle
  380. * @msdu: network buffer
  381. * @msdu_info: meta data associated with the msdu
  382. *
  383. * Return: QDF_STATUS_SUCCESS success
  384. */
  385. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  386. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  387. {
  388. struct qdf_tso_seg_elem_t *tso_seg;
  389. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  390. struct dp_soc *soc = vdev->pdev->soc;
  391. struct qdf_tso_info_t *tso_info;
  392. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  393. tso_info = &msdu_info->u.tso_info;
  394. tso_info->curr_seg = NULL;
  395. tso_info->tso_seg_list = NULL;
  396. tso_info->num_segs = num_seg;
  397. msdu_info->frm_type = dp_tx_frm_tso;
  398. tso_info->tso_num_seg_list = NULL;
  399. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  400. while (num_seg) {
  401. tso_seg = dp_tx_tso_desc_alloc(
  402. soc, msdu_info->tx_queue.desc_pool_id);
  403. if (tso_seg) {
  404. tso_seg->next = tso_info->tso_seg_list;
  405. tso_info->tso_seg_list = tso_seg;
  406. num_seg--;
  407. } else {
  408. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  409. __func__);
  410. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  411. return QDF_STATUS_E_NOMEM;
  412. }
  413. }
  414. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  415. tso_num_seg = dp_tso_num_seg_alloc(soc,
  416. msdu_info->tx_queue.desc_pool_id);
  417. if (tso_num_seg) {
  418. tso_num_seg->next = tso_info->tso_num_seg_list;
  419. tso_info->tso_num_seg_list = tso_num_seg;
  420. } else {
  421. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  422. __func__);
  423. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  424. return QDF_STATUS_E_NOMEM;
  425. }
  426. msdu_info->num_seg =
  427. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  428. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  429. msdu_info->num_seg);
  430. if (!(msdu_info->num_seg)) {
  431. /*
  432. * Free allocated TSO seg desc and number seg desc,
  433. * do unmap for segments if dma map has done.
  434. */
  435. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  436. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  437. return QDF_STATUS_E_INVAL;
  438. }
  439. tso_info->curr_seg = tso_info->tso_seg_list;
  440. return QDF_STATUS_SUCCESS;
  441. }
  442. #else
  443. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  444. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  445. {
  446. return QDF_STATUS_E_NOMEM;
  447. }
  448. #endif
  449. /**
  450. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  451. * @vdev: DP Vdev handle
  452. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  453. * @desc_pool_id: Descriptor Pool ID
  454. *
  455. * Return:
  456. */
  457. static
  458. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  459. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  460. {
  461. uint8_t i;
  462. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  463. struct dp_tx_seg_info_s *seg_info;
  464. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  465. struct dp_soc *soc = vdev->pdev->soc;
  466. /* Allocate an extension descriptor */
  467. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  468. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  469. if (!msdu_ext_desc) {
  470. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  471. return NULL;
  472. }
  473. if (msdu_info->exception_fw &&
  474. qdf_unlikely(vdev->mesh_vdev)) {
  475. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  476. &msdu_info->meta_data[0],
  477. sizeof(struct htt_tx_msdu_desc_ext2_t));
  478. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  479. }
  480. switch (msdu_info->frm_type) {
  481. case dp_tx_frm_sg:
  482. case dp_tx_frm_me:
  483. case dp_tx_frm_raw:
  484. seg_info = msdu_info->u.sg_info.curr_seg;
  485. /* Update the buffer pointers in MSDU Extension Descriptor */
  486. for (i = 0; i < seg_info->frag_cnt; i++) {
  487. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  488. seg_info->frags[i].paddr_lo,
  489. seg_info->frags[i].paddr_hi,
  490. seg_info->frags[i].len);
  491. }
  492. break;
  493. case dp_tx_frm_tso:
  494. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  495. &cached_ext_desc[0]);
  496. break;
  497. default:
  498. break;
  499. }
  500. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  501. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  502. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  503. msdu_ext_desc->vaddr);
  504. return msdu_ext_desc;
  505. }
  506. /**
  507. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  508. *
  509. * @skb: skb to be traced
  510. * @msdu_id: msdu_id of the packet
  511. * @vdev_id: vdev_id of the packet
  512. *
  513. * Return: None
  514. */
  515. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  516. uint8_t vdev_id)
  517. {
  518. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  519. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  520. DPTRACE(qdf_dp_trace_ptr(skb,
  521. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  522. QDF_TRACE_DEFAULT_PDEV_ID,
  523. qdf_nbuf_data_addr(skb),
  524. sizeof(qdf_nbuf_data(skb)),
  525. msdu_id, vdev_id));
  526. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  527. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  528. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  529. msdu_id, QDF_TX));
  530. }
  531. #ifdef QCA_512M_CONFIG
  532. /**
  533. * dp_tx_pdev_pflow_control - Check if allocated tx descriptors reached max
  534. * tx descriptor configured value
  535. * @vdev: DP vdev handle
  536. *
  537. * Return: true if allocated tx descriptors reached max configured value, else
  538. * false.
  539. */
  540. static inline bool
  541. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  542. {
  543. struct dp_pdev *pdev = vdev->pdev;
  544. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  545. pdev->num_tx_allowed) {
  546. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  547. "%s: queued packets are more than max tx, drop the frame",
  548. __func__);
  549. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  550. return true;
  551. }
  552. return false;
  553. }
  554. #else
  555. static inline bool
  556. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  557. {
  558. return false;
  559. }
  560. #endif
  561. /**
  562. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  563. * @vdev: DP vdev handle
  564. * @nbuf: skb
  565. * @desc_pool_id: Descriptor pool ID
  566. * @meta_data: Metadata to the fw
  567. * @tx_exc_metadata: Handle that holds exception path metadata
  568. * Allocate and prepare Tx descriptor with msdu information.
  569. *
  570. * Return: Pointer to Tx Descriptor on success,
  571. * NULL on failure
  572. */
  573. static
  574. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  575. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  576. struct dp_tx_msdu_info_s *msdu_info,
  577. struct cdp_tx_exception_metadata *tx_exc_metadata)
  578. {
  579. uint8_t align_pad;
  580. uint8_t is_exception = 0;
  581. uint8_t htt_hdr_size;
  582. qdf_ether_header_t *eh;
  583. struct dp_tx_desc_s *tx_desc;
  584. struct dp_pdev *pdev = vdev->pdev;
  585. struct dp_soc *soc = pdev->soc;
  586. if (dp_tx_pdev_pflow_control(vdev))
  587. return NULL;
  588. /* Allocate software Tx descriptor */
  589. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  590. if (qdf_unlikely(!tx_desc)) {
  591. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  592. return NULL;
  593. }
  594. /* Flow control/Congestion Control counters */
  595. qdf_atomic_inc(&pdev->num_tx_outstanding);
  596. /* Initialize the SW tx descriptor */
  597. tx_desc->nbuf = nbuf;
  598. tx_desc->frm_type = dp_tx_frm_std;
  599. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  600. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  601. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  602. tx_desc->vdev = vdev;
  603. tx_desc->pdev = pdev;
  604. tx_desc->msdu_ext_desc = NULL;
  605. tx_desc->pkt_offset = 0;
  606. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  607. /*
  608. * For special modes (vdev_type == ocb or mesh), data frames should be
  609. * transmitted using varying transmit parameters (tx spec) which include
  610. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  611. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  612. * These frames are sent as exception packets to firmware.
  613. *
  614. * HW requirement is that metadata should always point to a
  615. * 8-byte aligned address. So we add alignment pad to start of buffer.
  616. * HTT Metadata should be ensured to be multiple of 8-bytes,
  617. * to get 8-byte aligned start address along with align_pad added
  618. *
  619. * |-----------------------------|
  620. * | |
  621. * |-----------------------------| <-----Buffer Pointer Address given
  622. * | | ^ in HW descriptor (aligned)
  623. * | HTT Metadata | |
  624. * | | |
  625. * | | | Packet Offset given in descriptor
  626. * | | |
  627. * |-----------------------------| |
  628. * | Alignment Pad | v
  629. * |-----------------------------| <----- Actual buffer start address
  630. * | SKB Data | (Unaligned)
  631. * | |
  632. * | |
  633. * | |
  634. * | |
  635. * | |
  636. * |-----------------------------|
  637. */
  638. if (qdf_unlikely((msdu_info->exception_fw)) ||
  639. (vdev->opmode == wlan_op_mode_ocb) ||
  640. (tx_exc_metadata &&
  641. tx_exc_metadata->is_tx_sniffer)) {
  642. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  643. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  644. DP_STATS_INC(vdev,
  645. tx_i.dropped.headroom_insufficient, 1);
  646. goto failure;
  647. }
  648. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  649. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  650. "qdf_nbuf_push_head failed");
  651. goto failure;
  652. }
  653. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  654. msdu_info);
  655. if (htt_hdr_size == 0)
  656. goto failure;
  657. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  658. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  659. is_exception = 1;
  660. }
  661. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  662. qdf_nbuf_map(soc->osdev, nbuf,
  663. QDF_DMA_TO_DEVICE))) {
  664. /* Handle failure */
  665. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  666. "qdf_nbuf_map failed");
  667. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  668. goto failure;
  669. }
  670. if (qdf_unlikely(vdev->nawds_enabled)) {
  671. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  672. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  673. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  674. is_exception = 1;
  675. }
  676. }
  677. #if !TQM_BYPASS_WAR
  678. if (is_exception || tx_exc_metadata)
  679. #endif
  680. {
  681. /* Temporary WAR due to TQM VP issues */
  682. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  683. qdf_atomic_inc(&pdev->num_tx_exception);
  684. }
  685. return tx_desc;
  686. failure:
  687. dp_tx_desc_release(tx_desc, desc_pool_id);
  688. return NULL;
  689. }
  690. /**
  691. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  692. * @vdev: DP vdev handle
  693. * @nbuf: skb
  694. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  695. * @desc_pool_id : Descriptor Pool ID
  696. *
  697. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  698. * information. For frames wth fragments, allocate and prepare
  699. * an MSDU extension descriptor
  700. *
  701. * Return: Pointer to Tx Descriptor on success,
  702. * NULL on failure
  703. */
  704. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  705. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  706. uint8_t desc_pool_id)
  707. {
  708. struct dp_tx_desc_s *tx_desc;
  709. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  710. struct dp_pdev *pdev = vdev->pdev;
  711. struct dp_soc *soc = pdev->soc;
  712. if (dp_tx_pdev_pflow_control(vdev))
  713. return NULL;
  714. /* Allocate software Tx descriptor */
  715. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  716. if (!tx_desc) {
  717. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  718. return NULL;
  719. }
  720. /* Flow control/Congestion Control counters */
  721. qdf_atomic_inc(&pdev->num_tx_outstanding);
  722. /* Initialize the SW tx descriptor */
  723. tx_desc->nbuf = nbuf;
  724. tx_desc->frm_type = msdu_info->frm_type;
  725. tx_desc->tx_encap_type = vdev->tx_encap_type;
  726. tx_desc->vdev = vdev;
  727. tx_desc->pdev = pdev;
  728. tx_desc->pkt_offset = 0;
  729. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  730. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  731. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  732. /* Handle scattered frames - TSO/SG/ME */
  733. /* Allocate and prepare an extension descriptor for scattered frames */
  734. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  735. if (!msdu_ext_desc) {
  736. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  737. "%s Tx Extension Descriptor Alloc Fail",
  738. __func__);
  739. goto failure;
  740. }
  741. #if TQM_BYPASS_WAR
  742. /* Temporary WAR due to TQM VP issues */
  743. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  744. qdf_atomic_inc(&pdev->num_tx_exception);
  745. #endif
  746. if (qdf_unlikely(msdu_info->exception_fw))
  747. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  748. tx_desc->msdu_ext_desc = msdu_ext_desc;
  749. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  750. return tx_desc;
  751. failure:
  752. dp_tx_desc_release(tx_desc, desc_pool_id);
  753. return NULL;
  754. }
  755. /**
  756. * dp_tx_prepare_raw() - Prepare RAW packet TX
  757. * @vdev: DP vdev handle
  758. * @nbuf: buffer pointer
  759. * @seg_info: Pointer to Segment info Descriptor to be prepared
  760. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  761. * descriptor
  762. *
  763. * Return:
  764. */
  765. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  766. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  767. {
  768. qdf_nbuf_t curr_nbuf = NULL;
  769. uint16_t total_len = 0;
  770. qdf_dma_addr_t paddr;
  771. int32_t i;
  772. int32_t mapped_buf_num = 0;
  773. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  774. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  775. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  776. /* Continue only if frames are of DATA type */
  777. if (!DP_FRAME_IS_DATA(qos_wh)) {
  778. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  780. "Pkt. recd is of not data type");
  781. goto error;
  782. }
  783. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  784. if (vdev->raw_mode_war &&
  785. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  786. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  787. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  788. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  789. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  790. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  791. QDF_DMA_TO_DEVICE)) {
  792. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  793. "%s dma map error ", __func__);
  794. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  795. mapped_buf_num = i;
  796. goto error;
  797. }
  798. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  799. seg_info->frags[i].paddr_lo = paddr;
  800. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  801. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  802. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  803. total_len += qdf_nbuf_len(curr_nbuf);
  804. }
  805. seg_info->frag_cnt = i;
  806. seg_info->total_len = total_len;
  807. seg_info->next = NULL;
  808. sg_info->curr_seg = seg_info;
  809. msdu_info->frm_type = dp_tx_frm_raw;
  810. msdu_info->num_seg = 1;
  811. return nbuf;
  812. error:
  813. i = 0;
  814. while (nbuf) {
  815. curr_nbuf = nbuf;
  816. if (i < mapped_buf_num) {
  817. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  818. i++;
  819. }
  820. nbuf = qdf_nbuf_next(nbuf);
  821. qdf_nbuf_free(curr_nbuf);
  822. }
  823. return NULL;
  824. }
  825. /**
  826. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  827. * @soc: DP soc handle
  828. * @nbuf: Buffer pointer
  829. *
  830. * unmap the chain of nbufs that belong to this RAW frame.
  831. *
  832. * Return: None
  833. */
  834. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  835. qdf_nbuf_t nbuf)
  836. {
  837. qdf_nbuf_t cur_nbuf = nbuf;
  838. do {
  839. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  840. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  841. } while (cur_nbuf);
  842. }
  843. /**
  844. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  845. * @soc: DP Soc Handle
  846. * @vdev: DP vdev handle
  847. * @tx_desc: Tx Descriptor Handle
  848. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  849. * @fw_metadata: Metadata to send to Target Firmware along with frame
  850. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  851. * @tx_exc_metadata: Handle that holds exception path meta data
  852. *
  853. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  854. * from software Tx descriptor
  855. *
  856. * Return:
  857. */
  858. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  859. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  860. uint16_t fw_metadata, uint8_t ring_id,
  861. struct cdp_tx_exception_metadata
  862. *tx_exc_metadata)
  863. {
  864. uint8_t type;
  865. uint16_t length;
  866. void *hal_tx_desc, *hal_tx_desc_cached;
  867. qdf_dma_addr_t dma_addr;
  868. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  869. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  870. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  871. tx_exc_metadata->sec_type : vdev->sec_type);
  872. /* Return Buffer Manager ID */
  873. uint8_t bm_id = ring_id;
  874. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  875. hal_tx_desc_cached = (void *) cached_desc;
  876. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  877. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  878. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  879. type = HAL_TX_BUF_TYPE_EXT_DESC;
  880. dma_addr = tx_desc->msdu_ext_desc->paddr;
  881. } else {
  882. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  883. type = HAL_TX_BUF_TYPE_BUFFER;
  884. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  885. }
  886. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  887. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  888. dma_addr, bm_id, tx_desc->id,
  889. type, soc->hal_soc);
  890. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  891. return QDF_STATUS_E_RESOURCES;
  892. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  893. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  894. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  895. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  896. vdev->pdev->lmac_id);
  897. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  898. vdev->search_type);
  899. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  900. vdev->bss_ast_hash);
  901. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  902. vdev->dscp_tid_map_id);
  903. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  904. sec_type_map[sec_type]);
  905. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  906. length, type, (uint64_t)dma_addr,
  907. tx_desc->pkt_offset, tx_desc->id);
  908. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  909. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  910. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  911. vdev->hal_desc_addr_search_flags);
  912. /* verify checksum offload configuration*/
  913. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  914. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  915. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  916. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  917. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  918. }
  919. if (tid != HTT_TX_EXT_TID_INVALID)
  920. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  921. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  922. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  923. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  924. /* Sync cached descriptor with HW */
  925. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  926. if (!hal_tx_desc) {
  927. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  928. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  929. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  930. return QDF_STATUS_E_RESOURCES;
  931. }
  932. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  933. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  934. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  935. return QDF_STATUS_SUCCESS;
  936. }
  937. /**
  938. * dp_cce_classify() - Classify the frame based on CCE rules
  939. * @vdev: DP vdev handle
  940. * @nbuf: skb
  941. *
  942. * Classify frames based on CCE rules
  943. * Return: bool( true if classified,
  944. * else false)
  945. */
  946. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  947. {
  948. qdf_ether_header_t *eh = NULL;
  949. uint16_t ether_type;
  950. qdf_llc_t *llcHdr;
  951. qdf_nbuf_t nbuf_clone = NULL;
  952. qdf_dot3_qosframe_t *qos_wh = NULL;
  953. /* for mesh packets don't do any classification */
  954. if (qdf_unlikely(vdev->mesh_vdev))
  955. return false;
  956. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  957. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  958. ether_type = eh->ether_type;
  959. llcHdr = (qdf_llc_t *)(nbuf->data +
  960. sizeof(qdf_ether_header_t));
  961. } else {
  962. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  963. /* For encrypted packets don't do any classification */
  964. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  965. return false;
  966. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  967. if (qdf_unlikely(
  968. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  969. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  970. ether_type = *(uint16_t *)(nbuf->data
  971. + QDF_IEEE80211_4ADDR_HDR_LEN
  972. + sizeof(qdf_llc_t)
  973. - sizeof(ether_type));
  974. llcHdr = (qdf_llc_t *)(nbuf->data +
  975. QDF_IEEE80211_4ADDR_HDR_LEN);
  976. } else {
  977. ether_type = *(uint16_t *)(nbuf->data
  978. + QDF_IEEE80211_3ADDR_HDR_LEN
  979. + sizeof(qdf_llc_t)
  980. - sizeof(ether_type));
  981. llcHdr = (qdf_llc_t *)(nbuf->data +
  982. QDF_IEEE80211_3ADDR_HDR_LEN);
  983. }
  984. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  985. && (ether_type ==
  986. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  987. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  988. return true;
  989. }
  990. }
  991. return false;
  992. }
  993. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  994. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  995. sizeof(*llcHdr));
  996. nbuf_clone = qdf_nbuf_clone(nbuf);
  997. if (qdf_unlikely(nbuf_clone)) {
  998. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  999. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1000. qdf_nbuf_pull_head(nbuf_clone,
  1001. sizeof(qdf_net_vlanhdr_t));
  1002. }
  1003. }
  1004. } else {
  1005. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1006. nbuf_clone = qdf_nbuf_clone(nbuf);
  1007. if (qdf_unlikely(nbuf_clone)) {
  1008. qdf_nbuf_pull_head(nbuf_clone,
  1009. sizeof(qdf_net_vlanhdr_t));
  1010. }
  1011. }
  1012. }
  1013. if (qdf_unlikely(nbuf_clone))
  1014. nbuf = nbuf_clone;
  1015. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1016. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1017. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1018. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1019. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1020. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1021. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1022. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1023. if (qdf_unlikely(nbuf_clone))
  1024. qdf_nbuf_free(nbuf_clone);
  1025. return true;
  1026. }
  1027. if (qdf_unlikely(nbuf_clone))
  1028. qdf_nbuf_free(nbuf_clone);
  1029. return false;
  1030. }
  1031. /**
  1032. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1033. * @vdev: DP vdev handle
  1034. * @nbuf: skb
  1035. *
  1036. * Extract the DSCP or PCP information from frame and map into TID value.
  1037. *
  1038. * Return: void
  1039. */
  1040. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1041. struct dp_tx_msdu_info_s *msdu_info)
  1042. {
  1043. uint8_t tos = 0, dscp_tid_override = 0;
  1044. uint8_t *hdr_ptr, *L3datap;
  1045. uint8_t is_mcast = 0;
  1046. qdf_ether_header_t *eh = NULL;
  1047. qdf_ethervlan_header_t *evh = NULL;
  1048. uint16_t ether_type;
  1049. qdf_llc_t *llcHdr;
  1050. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1051. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1052. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1053. eh = (qdf_ether_header_t *)nbuf->data;
  1054. hdr_ptr = eh->ether_dhost;
  1055. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1056. } else {
  1057. qdf_dot3_qosframe_t *qos_wh =
  1058. (qdf_dot3_qosframe_t *) nbuf->data;
  1059. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1060. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1061. return;
  1062. }
  1063. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1064. ether_type = eh->ether_type;
  1065. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1066. /*
  1067. * Check if packet is dot3 or eth2 type.
  1068. */
  1069. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1070. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1071. sizeof(*llcHdr));
  1072. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1073. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1074. sizeof(*llcHdr);
  1075. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1076. + sizeof(*llcHdr) +
  1077. sizeof(qdf_net_vlanhdr_t));
  1078. } else {
  1079. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1080. sizeof(*llcHdr);
  1081. }
  1082. } else {
  1083. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1084. evh = (qdf_ethervlan_header_t *) eh;
  1085. ether_type = evh->ether_type;
  1086. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1087. }
  1088. }
  1089. /*
  1090. * Find priority from IP TOS DSCP field
  1091. */
  1092. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1093. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1094. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1095. /* Only for unicast frames */
  1096. if (!is_mcast) {
  1097. /* send it on VO queue */
  1098. msdu_info->tid = DP_VO_TID;
  1099. }
  1100. } else {
  1101. /*
  1102. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1103. * from TOS byte.
  1104. */
  1105. tos = ip->ip_tos;
  1106. dscp_tid_override = 1;
  1107. }
  1108. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1109. /* TODO
  1110. * use flowlabel
  1111. *igmpmld cases to be handled in phase 2
  1112. */
  1113. unsigned long ver_pri_flowlabel;
  1114. unsigned long pri;
  1115. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1116. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1117. DP_IPV6_PRIORITY_SHIFT;
  1118. tos = pri;
  1119. dscp_tid_override = 1;
  1120. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1121. msdu_info->tid = DP_VO_TID;
  1122. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1123. /* Only for unicast frames */
  1124. if (!is_mcast) {
  1125. /* send ucast arp on VO queue */
  1126. msdu_info->tid = DP_VO_TID;
  1127. }
  1128. }
  1129. /*
  1130. * Assign all MCAST packets to BE
  1131. */
  1132. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1133. if (is_mcast) {
  1134. tos = 0;
  1135. dscp_tid_override = 1;
  1136. }
  1137. }
  1138. if (dscp_tid_override == 1) {
  1139. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1140. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1141. }
  1142. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1143. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1144. return;
  1145. }
  1146. /**
  1147. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1148. * @vdev: DP vdev handle
  1149. * @nbuf: skb
  1150. *
  1151. * Software based TID classification is required when more than 2 DSCP-TID
  1152. * mapping tables are needed.
  1153. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1154. *
  1155. * Return: void
  1156. */
  1157. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1158. struct dp_tx_msdu_info_s *msdu_info)
  1159. {
  1160. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1161. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1162. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1163. return;
  1164. /* for mesh packets don't do any classification */
  1165. if (qdf_unlikely(vdev->mesh_vdev))
  1166. return;
  1167. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1168. }
  1169. #ifdef FEATURE_WLAN_TDLS
  1170. /**
  1171. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1172. * @tx_desc: TX descriptor
  1173. *
  1174. * Return: None
  1175. */
  1176. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1177. {
  1178. if (tx_desc->vdev) {
  1179. if (tx_desc->vdev->is_tdls_frame) {
  1180. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1181. tx_desc->vdev->is_tdls_frame = false;
  1182. }
  1183. }
  1184. }
  1185. /**
  1186. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1187. * @tx_desc: TX descriptor
  1188. * @vdev: datapath vdev handle
  1189. *
  1190. * Return: None
  1191. */
  1192. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1193. struct dp_vdev *vdev)
  1194. {
  1195. struct hal_tx_completion_status ts = {0};
  1196. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1197. if (qdf_unlikely(!vdev)) {
  1198. dp_err("vdev is null!");
  1199. return;
  1200. }
  1201. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1202. if (vdev->tx_non_std_data_callback.func) {
  1203. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1204. vdev->tx_non_std_data_callback.func(
  1205. vdev->tx_non_std_data_callback.ctxt,
  1206. nbuf, ts.status);
  1207. return;
  1208. }
  1209. }
  1210. #else
  1211. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1212. {
  1213. }
  1214. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1215. struct dp_vdev *vdev)
  1216. {
  1217. }
  1218. #endif
  1219. /**
  1220. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1221. * @vdev: DP vdev handle
  1222. * @nbuf: skb
  1223. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1224. * @meta_data: Metadata to the fw
  1225. * @tx_q: Tx queue to be used for this Tx frame
  1226. * @peer_id: peer_id of the peer in case of NAWDS frames
  1227. * @tx_exc_metadata: Handle that holds exception path metadata
  1228. *
  1229. * Return: NULL on success,
  1230. * nbuf when it fails to send
  1231. */
  1232. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1233. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1234. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1235. {
  1236. struct dp_pdev *pdev = vdev->pdev;
  1237. struct dp_soc *soc = pdev->soc;
  1238. struct dp_tx_desc_s *tx_desc;
  1239. QDF_STATUS status;
  1240. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1241. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1242. uint16_t htt_tcl_metadata = 0;
  1243. uint8_t tid = msdu_info->tid;
  1244. struct cdp_tid_tx_stats *tid_stats = NULL;
  1245. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1246. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1247. msdu_info, tx_exc_metadata);
  1248. if (!tx_desc) {
  1249. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1250. vdev, tx_q->desc_pool_id);
  1251. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1252. tid_stats = &pdev->stats.tid_stats.
  1253. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1254. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1255. return nbuf;
  1256. }
  1257. if (qdf_unlikely(soc->cce_disable)) {
  1258. if (dp_cce_classify(vdev, nbuf) == true) {
  1259. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1260. tid = DP_VO_TID;
  1261. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1262. }
  1263. }
  1264. dp_tx_update_tdls_flags(tx_desc);
  1265. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1266. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1267. "%s %d : HAL RING Access Failed -- %pK",
  1268. __func__, __LINE__, hal_srng);
  1269. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1270. tid_stats = &pdev->stats.tid_stats.
  1271. tid_tx_stats[tx_q->ring_id][tid];
  1272. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1273. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1274. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1275. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1276. goto fail_return;
  1277. }
  1278. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1279. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1280. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1281. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1282. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1283. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1284. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1285. peer_id);
  1286. } else
  1287. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1288. if (msdu_info->exception_fw) {
  1289. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1290. }
  1291. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1292. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1293. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1294. if (status != QDF_STATUS_SUCCESS) {
  1295. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1296. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1297. __func__, tx_desc, tx_q->ring_id);
  1298. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1299. tid_stats = &pdev->stats.tid_stats.
  1300. tid_tx_stats[tx_q->ring_id][tid];
  1301. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1302. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1303. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1304. goto fail_return;
  1305. }
  1306. nbuf = NULL;
  1307. fail_return:
  1308. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1309. hal_srng_access_end(soc->hal_soc, hal_srng);
  1310. hif_pm_runtime_put(soc->hif_handle);
  1311. } else {
  1312. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1313. }
  1314. return nbuf;
  1315. }
  1316. /**
  1317. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1318. * @vdev: DP vdev handle
  1319. * @nbuf: skb
  1320. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1321. *
  1322. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1323. *
  1324. * Return: NULL on success,
  1325. * nbuf when it fails to send
  1326. */
  1327. #if QDF_LOCK_STATS
  1328. noinline
  1329. #else
  1330. #endif
  1331. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1332. struct dp_tx_msdu_info_s *msdu_info)
  1333. {
  1334. uint8_t i;
  1335. struct dp_pdev *pdev = vdev->pdev;
  1336. struct dp_soc *soc = pdev->soc;
  1337. struct dp_tx_desc_s *tx_desc;
  1338. bool is_cce_classified = false;
  1339. QDF_STATUS status;
  1340. uint16_t htt_tcl_metadata = 0;
  1341. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1342. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1343. struct cdp_tid_tx_stats *tid_stats = NULL;
  1344. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1345. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1346. "%s %d : HAL RING Access Failed -- %pK",
  1347. __func__, __LINE__, hal_srng);
  1348. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1349. tid_stats = &pdev->stats.tid_stats.
  1350. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1351. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1352. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1353. return nbuf;
  1354. }
  1355. if (qdf_unlikely(soc->cce_disable)) {
  1356. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1357. if (is_cce_classified) {
  1358. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1359. msdu_info->tid = DP_VO_TID;
  1360. }
  1361. }
  1362. if (msdu_info->frm_type == dp_tx_frm_me)
  1363. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1364. i = 0;
  1365. /* Print statement to track i and num_seg */
  1366. /*
  1367. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1368. * descriptors using information in msdu_info
  1369. */
  1370. while (i < msdu_info->num_seg) {
  1371. /*
  1372. * Setup Tx descriptor for an MSDU, and MSDU extension
  1373. * descriptor
  1374. */
  1375. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1376. tx_q->desc_pool_id);
  1377. if (!tx_desc) {
  1378. if (msdu_info->frm_type == dp_tx_frm_me) {
  1379. dp_tx_me_free_buf(pdev,
  1380. (void *)(msdu_info->u.sg_info
  1381. .curr_seg->frags[0].vaddr));
  1382. }
  1383. goto done;
  1384. }
  1385. if (msdu_info->frm_type == dp_tx_frm_me) {
  1386. tx_desc->me_buffer =
  1387. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1388. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1389. }
  1390. if (is_cce_classified)
  1391. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1392. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1393. if (msdu_info->exception_fw) {
  1394. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1395. }
  1396. /*
  1397. * Enqueue the Tx MSDU descriptor to HW for transmit
  1398. */
  1399. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1400. htt_tcl_metadata, tx_q->ring_id, NULL);
  1401. if (status != QDF_STATUS_SUCCESS) {
  1402. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1403. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1404. __func__, tx_desc, tx_q->ring_id);
  1405. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1406. tid_stats = &pdev->stats.tid_stats.
  1407. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1408. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1409. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1410. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1411. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1412. goto done;
  1413. }
  1414. /*
  1415. * TODO
  1416. * if tso_info structure can be modified to have curr_seg
  1417. * as first element, following 2 blocks of code (for TSO and SG)
  1418. * can be combined into 1
  1419. */
  1420. /*
  1421. * For frames with multiple segments (TSO, ME), jump to next
  1422. * segment.
  1423. */
  1424. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1425. if (msdu_info->u.tso_info.curr_seg->next) {
  1426. msdu_info->u.tso_info.curr_seg =
  1427. msdu_info->u.tso_info.curr_seg->next;
  1428. /*
  1429. * If this is a jumbo nbuf, then increment the number of
  1430. * nbuf users for each additional segment of the msdu.
  1431. * This will ensure that the skb is freed only after
  1432. * receiving tx completion for all segments of an nbuf
  1433. */
  1434. qdf_nbuf_inc_users(nbuf);
  1435. /* Check with MCL if this is needed */
  1436. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1437. }
  1438. }
  1439. /*
  1440. * For Multicast-Unicast converted packets,
  1441. * each converted frame (for a client) is represented as
  1442. * 1 segment
  1443. */
  1444. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1445. (msdu_info->frm_type == dp_tx_frm_me)) {
  1446. if (msdu_info->u.sg_info.curr_seg->next) {
  1447. msdu_info->u.sg_info.curr_seg =
  1448. msdu_info->u.sg_info.curr_seg->next;
  1449. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1450. }
  1451. }
  1452. i++;
  1453. }
  1454. nbuf = NULL;
  1455. done:
  1456. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1457. hal_srng_access_end(soc->hal_soc, hal_srng);
  1458. hif_pm_runtime_put(soc->hif_handle);
  1459. } else {
  1460. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1461. }
  1462. return nbuf;
  1463. }
  1464. /**
  1465. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1466. * for SG frames
  1467. * @vdev: DP vdev handle
  1468. * @nbuf: skb
  1469. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1470. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1471. *
  1472. * Return: NULL on success,
  1473. * nbuf when it fails to send
  1474. */
  1475. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1476. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1477. {
  1478. uint32_t cur_frag, nr_frags;
  1479. qdf_dma_addr_t paddr;
  1480. struct dp_tx_sg_info_s *sg_info;
  1481. sg_info = &msdu_info->u.sg_info;
  1482. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1483. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1484. QDF_DMA_TO_DEVICE)) {
  1485. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1486. "dma map error");
  1487. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1488. qdf_nbuf_free(nbuf);
  1489. return NULL;
  1490. }
  1491. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1492. seg_info->frags[0].paddr_lo = paddr;
  1493. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1494. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1495. seg_info->frags[0].vaddr = (void *) nbuf;
  1496. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1497. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1498. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1499. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1500. "frag dma map error");
  1501. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1502. qdf_nbuf_free(nbuf);
  1503. return NULL;
  1504. }
  1505. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1506. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1507. seg_info->frags[cur_frag + 1].paddr_hi =
  1508. ((uint64_t) paddr) >> 32;
  1509. seg_info->frags[cur_frag + 1].len =
  1510. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1511. }
  1512. seg_info->frag_cnt = (cur_frag + 1);
  1513. seg_info->total_len = qdf_nbuf_len(nbuf);
  1514. seg_info->next = NULL;
  1515. sg_info->curr_seg = seg_info;
  1516. msdu_info->frm_type = dp_tx_frm_sg;
  1517. msdu_info->num_seg = 1;
  1518. return nbuf;
  1519. }
  1520. /**
  1521. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1522. * @vdev: DP vdev handle
  1523. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1524. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1525. *
  1526. * Return: NULL on failure,
  1527. * nbuf when extracted successfully
  1528. */
  1529. static
  1530. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1531. struct dp_tx_msdu_info_s *msdu_info,
  1532. uint16_t ppdu_cookie)
  1533. {
  1534. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1535. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1536. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1537. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1538. (msdu_info->meta_data[5], 1);
  1539. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1540. (msdu_info->meta_data[5], 1);
  1541. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1542. (msdu_info->meta_data[6], ppdu_cookie);
  1543. msdu_info->exception_fw = 1;
  1544. msdu_info->is_tx_sniffer = 1;
  1545. }
  1546. #ifdef MESH_MODE_SUPPORT
  1547. /**
  1548. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1549. and prepare msdu_info for mesh frames.
  1550. * @vdev: DP vdev handle
  1551. * @nbuf: skb
  1552. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1553. *
  1554. * Return: NULL on failure,
  1555. * nbuf when extracted successfully
  1556. */
  1557. static
  1558. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1559. struct dp_tx_msdu_info_s *msdu_info)
  1560. {
  1561. struct meta_hdr_s *mhdr;
  1562. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1563. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1564. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1565. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1566. msdu_info->exception_fw = 0;
  1567. goto remove_meta_hdr;
  1568. }
  1569. msdu_info->exception_fw = 1;
  1570. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1571. meta_data->host_tx_desc_pool = 1;
  1572. meta_data->update_peer_cache = 1;
  1573. meta_data->learning_frame = 1;
  1574. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1575. meta_data->power = mhdr->power;
  1576. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1577. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1578. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1579. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1580. meta_data->dyn_bw = 1;
  1581. meta_data->valid_pwr = 1;
  1582. meta_data->valid_mcs_mask = 1;
  1583. meta_data->valid_nss_mask = 1;
  1584. meta_data->valid_preamble_type = 1;
  1585. meta_data->valid_retries = 1;
  1586. meta_data->valid_bw_info = 1;
  1587. }
  1588. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1589. meta_data->encrypt_type = 0;
  1590. meta_data->valid_encrypt_type = 1;
  1591. meta_data->learning_frame = 0;
  1592. }
  1593. meta_data->valid_key_flags = 1;
  1594. meta_data->key_flags = (mhdr->keyix & 0x3);
  1595. remove_meta_hdr:
  1596. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1597. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1598. "qdf_nbuf_pull_head failed");
  1599. qdf_nbuf_free(nbuf);
  1600. return NULL;
  1601. }
  1602. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1603. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1604. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1605. " tid %d to_fw %d",
  1606. __func__, msdu_info->meta_data[0],
  1607. msdu_info->meta_data[1],
  1608. msdu_info->meta_data[2],
  1609. msdu_info->meta_data[3],
  1610. msdu_info->meta_data[4],
  1611. msdu_info->meta_data[5],
  1612. msdu_info->tid, msdu_info->exception_fw);
  1613. return nbuf;
  1614. }
  1615. #else
  1616. static
  1617. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1618. struct dp_tx_msdu_info_s *msdu_info)
  1619. {
  1620. return nbuf;
  1621. }
  1622. #endif
  1623. /**
  1624. * dp_check_exc_metadata() - Checks if parameters are valid
  1625. * @tx_exc - holds all exception path parameters
  1626. *
  1627. * Returns true when all the parameters are valid else false
  1628. *
  1629. */
  1630. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1631. {
  1632. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1633. HTT_INVALID_TID);
  1634. bool invalid_encap_type = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1635. HTT_INVALID_TID);
  1636. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1637. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1638. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1639. tx_exc->ppdu_cookie == 0);
  1640. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1641. invalid_cookie) {
  1642. return false;
  1643. }
  1644. return true;
  1645. }
  1646. /**
  1647. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1648. * @vap_dev: DP vdev handle
  1649. * @nbuf: skb
  1650. * @tx_exc_metadata: Handle that holds exception path meta data
  1651. *
  1652. * Entry point for Core Tx layer (DP_TX) invoked from
  1653. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1654. *
  1655. * Return: NULL on success,
  1656. * nbuf when it fails to send
  1657. */
  1658. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1659. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1660. {
  1661. qdf_ether_header_t *eh = NULL;
  1662. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1663. struct dp_tx_msdu_info_s msdu_info;
  1664. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1665. if (!tx_exc_metadata)
  1666. goto fail;
  1667. msdu_info.tid = tx_exc_metadata->tid;
  1668. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1669. dp_verbose_debug("skb %pM", nbuf->data);
  1670. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1671. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1672. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1673. "Invalid parameters in exception path");
  1674. goto fail;
  1675. }
  1676. /* Basic sanity checks for unsupported packets */
  1677. /* MESH mode */
  1678. if (qdf_unlikely(vdev->mesh_vdev)) {
  1679. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1680. "Mesh mode is not supported in exception path");
  1681. goto fail;
  1682. }
  1683. /* TSO or SG */
  1684. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1685. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1686. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1687. "TSO and SG are not supported in exception path");
  1688. goto fail;
  1689. }
  1690. /* RAW */
  1691. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1692. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1693. "Raw frame is not supported in exception path");
  1694. goto fail;
  1695. }
  1696. /* Mcast enhancement*/
  1697. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1698. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1699. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1700. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1701. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1702. }
  1703. }
  1704. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1705. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1706. qdf_nbuf_len(nbuf));
  1707. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1708. tx_exc_metadata->ppdu_cookie);
  1709. }
  1710. /*
  1711. * Get HW Queue to use for this frame.
  1712. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1713. * dedicated for data and 1 for command.
  1714. * "queue_id" maps to one hardware ring.
  1715. * With each ring, we also associate a unique Tx descriptor pool
  1716. * to minimize lock contention for these resources.
  1717. */
  1718. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1719. /* Single linear frame */
  1720. /*
  1721. * If nbuf is a simple linear frame, use send_single function to
  1722. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1723. * SRNG. There is no need to setup a MSDU extension descriptor.
  1724. */
  1725. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1726. tx_exc_metadata->peer_id, tx_exc_metadata);
  1727. return nbuf;
  1728. fail:
  1729. dp_verbose_debug("pkt send failed");
  1730. return nbuf;
  1731. }
  1732. /**
  1733. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1734. * @vap_dev: DP vdev handle
  1735. * @nbuf: skb
  1736. *
  1737. * Entry point for Core Tx layer (DP_TX) invoked from
  1738. * hard_start_xmit in OSIF/HDD
  1739. *
  1740. * Return: NULL on success,
  1741. * nbuf when it fails to send
  1742. */
  1743. #ifdef MESH_MODE_SUPPORT
  1744. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1745. {
  1746. struct meta_hdr_s *mhdr;
  1747. qdf_nbuf_t nbuf_mesh = NULL;
  1748. qdf_nbuf_t nbuf_clone = NULL;
  1749. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1750. uint8_t no_enc_frame = 0;
  1751. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1752. if (!nbuf_mesh) {
  1753. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1754. "qdf_nbuf_unshare failed");
  1755. return nbuf;
  1756. }
  1757. nbuf = nbuf_mesh;
  1758. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1759. if ((vdev->sec_type != cdp_sec_type_none) &&
  1760. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1761. no_enc_frame = 1;
  1762. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1763. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1764. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1765. !no_enc_frame) {
  1766. nbuf_clone = qdf_nbuf_clone(nbuf);
  1767. if (!nbuf_clone) {
  1768. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1769. "qdf_nbuf_clone failed");
  1770. return nbuf;
  1771. }
  1772. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1773. }
  1774. if (nbuf_clone) {
  1775. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1776. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1777. } else {
  1778. qdf_nbuf_free(nbuf_clone);
  1779. }
  1780. }
  1781. if (no_enc_frame)
  1782. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1783. else
  1784. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1785. nbuf = dp_tx_send(vap_dev, nbuf);
  1786. if ((!nbuf) && no_enc_frame) {
  1787. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1788. }
  1789. return nbuf;
  1790. }
  1791. #else
  1792. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1793. {
  1794. return dp_tx_send(vap_dev, nbuf);
  1795. }
  1796. #endif
  1797. /**
  1798. * dp_tx_send() - Transmit a frame on a given VAP
  1799. * @vap_dev: DP vdev handle
  1800. * @nbuf: skb
  1801. *
  1802. * Entry point for Core Tx layer (DP_TX) invoked from
  1803. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1804. * cases
  1805. *
  1806. * Return: NULL on success,
  1807. * nbuf when it fails to send
  1808. */
  1809. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1810. {
  1811. qdf_ether_header_t *eh = NULL;
  1812. struct dp_tx_msdu_info_s msdu_info;
  1813. struct dp_tx_seg_info_s seg_info;
  1814. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1815. uint16_t peer_id = HTT_INVALID_PEER;
  1816. qdf_nbuf_t nbuf_mesh = NULL;
  1817. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1818. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1819. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1820. dp_verbose_debug("skb %pM", nbuf->data);
  1821. /*
  1822. * Set Default Host TID value to invalid TID
  1823. * (TID override disabled)
  1824. */
  1825. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1826. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1827. if (qdf_unlikely(vdev->mesh_vdev)) {
  1828. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1829. &msdu_info);
  1830. if (!nbuf_mesh) {
  1831. dp_verbose_debug("Extracting mesh metadata failed");
  1832. return nbuf;
  1833. }
  1834. nbuf = nbuf_mesh;
  1835. }
  1836. /*
  1837. * Get HW Queue to use for this frame.
  1838. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1839. * dedicated for data and 1 for command.
  1840. * "queue_id" maps to one hardware ring.
  1841. * With each ring, we also associate a unique Tx descriptor pool
  1842. * to minimize lock contention for these resources.
  1843. */
  1844. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1845. /*
  1846. * TCL H/W supports 2 DSCP-TID mapping tables.
  1847. * Table 1 - Default DSCP-TID mapping table
  1848. * Table 2 - 1 DSCP-TID override table
  1849. *
  1850. * If we need a different DSCP-TID mapping for this vap,
  1851. * call tid_classify to extract DSCP/ToS from frame and
  1852. * map to a TID and store in msdu_info. This is later used
  1853. * to fill in TCL Input descriptor (per-packet TID override).
  1854. */
  1855. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1856. /*
  1857. * Classify the frame and call corresponding
  1858. * "prepare" function which extracts the segment (TSO)
  1859. * and fragmentation information (for TSO , SG, ME, or Raw)
  1860. * into MSDU_INFO structure which is later used to fill
  1861. * SW and HW descriptors.
  1862. */
  1863. if (qdf_nbuf_is_tso(nbuf)) {
  1864. dp_verbose_debug("TSO frame %pK", vdev);
  1865. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1866. qdf_nbuf_len(nbuf));
  1867. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1868. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1869. qdf_nbuf_len(nbuf));
  1870. return nbuf;
  1871. }
  1872. goto send_multiple;
  1873. }
  1874. /* SG */
  1875. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1876. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1877. if (!nbuf)
  1878. return NULL;
  1879. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1880. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1881. qdf_nbuf_len(nbuf));
  1882. goto send_multiple;
  1883. }
  1884. #ifdef ATH_SUPPORT_IQUE
  1885. /* Mcast to Ucast Conversion*/
  1886. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1887. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1888. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1889. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1890. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1891. DP_STATS_INC_PKT(vdev,
  1892. tx_i.mcast_en.mcast_pkt, 1,
  1893. qdf_nbuf_len(nbuf));
  1894. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1895. QDF_STATUS_SUCCESS) {
  1896. return NULL;
  1897. }
  1898. }
  1899. }
  1900. #endif
  1901. /* RAW */
  1902. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1903. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1904. if (!nbuf)
  1905. return NULL;
  1906. dp_verbose_debug("Raw frame %pK", vdev);
  1907. goto send_multiple;
  1908. }
  1909. /* Single linear frame */
  1910. /*
  1911. * If nbuf is a simple linear frame, use send_single function to
  1912. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1913. * SRNG. There is no need to setup a MSDU extension descriptor.
  1914. */
  1915. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1916. return nbuf;
  1917. send_multiple:
  1918. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1919. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  1920. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  1921. return nbuf;
  1922. }
  1923. /**
  1924. * dp_tx_reinject_handler() - Tx Reinject Handler
  1925. * @tx_desc: software descriptor head pointer
  1926. * @status : Tx completion status from HTT descriptor
  1927. *
  1928. * This function reinjects frames back to Target.
  1929. * Todo - Host queue needs to be added
  1930. *
  1931. * Return: none
  1932. */
  1933. static
  1934. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1935. {
  1936. struct dp_vdev *vdev;
  1937. struct dp_peer *peer = NULL;
  1938. uint32_t peer_id = HTT_INVALID_PEER;
  1939. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1940. qdf_nbuf_t nbuf_copy = NULL;
  1941. struct dp_tx_msdu_info_s msdu_info;
  1942. struct dp_peer *sa_peer = NULL;
  1943. struct dp_ast_entry *ast_entry = NULL;
  1944. struct dp_soc *soc = NULL;
  1945. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1946. #ifdef WDS_VENDOR_EXTENSION
  1947. int is_mcast = 0, is_ucast = 0;
  1948. int num_peers_3addr = 0;
  1949. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1950. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1951. #endif
  1952. vdev = tx_desc->vdev;
  1953. soc = vdev->pdev->soc;
  1954. qdf_assert(vdev);
  1955. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1956. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1957. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1958. "%s Tx reinject path", __func__);
  1959. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1960. qdf_nbuf_len(tx_desc->nbuf));
  1961. qdf_spin_lock_bh(&(soc->ast_lock));
  1962. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1963. (soc,
  1964. (uint8_t *)(eh->ether_shost),
  1965. vdev->pdev->pdev_id);
  1966. if (ast_entry)
  1967. sa_peer = ast_entry->peer;
  1968. qdf_spin_unlock_bh(&(soc->ast_lock));
  1969. #ifdef WDS_VENDOR_EXTENSION
  1970. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1971. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1972. } else {
  1973. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1974. }
  1975. is_ucast = !is_mcast;
  1976. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1977. if (peer->bss_peer)
  1978. continue;
  1979. /* Detect wds peers that use 3-addr framing for mcast.
  1980. * if there are any, the bss_peer is used to send the
  1981. * the mcast frame using 3-addr format. all wds enabled
  1982. * peers that use 4-addr framing for mcast frames will
  1983. * be duplicated and sent as 4-addr frames below.
  1984. */
  1985. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1986. num_peers_3addr = 1;
  1987. break;
  1988. }
  1989. }
  1990. #endif
  1991. if (qdf_unlikely(vdev->mesh_vdev)) {
  1992. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1993. } else {
  1994. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1995. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1996. #ifdef WDS_VENDOR_EXTENSION
  1997. /*
  1998. * . if 3-addr STA, then send on BSS Peer
  1999. * . if Peer WDS enabled and accept 4-addr mcast,
  2000. * send mcast on that peer only
  2001. * . if Peer WDS enabled and accept 4-addr ucast,
  2002. * send ucast on that peer only
  2003. */
  2004. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2005. (peer->wds_enabled &&
  2006. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2007. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2008. #else
  2009. ((peer->bss_peer &&
  2010. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2011. peer->nawds_enabled)) {
  2012. #endif
  2013. peer_id = DP_INVALID_PEER;
  2014. if (peer->nawds_enabled) {
  2015. peer_id = peer->peer_ids[0];
  2016. if (sa_peer == peer) {
  2017. QDF_TRACE(
  2018. QDF_MODULE_ID_DP,
  2019. QDF_TRACE_LEVEL_DEBUG,
  2020. " %s: multicast packet",
  2021. __func__);
  2022. DP_STATS_INC(peer,
  2023. tx.nawds_mcast_drop, 1);
  2024. continue;
  2025. }
  2026. }
  2027. nbuf_copy = qdf_nbuf_copy(nbuf);
  2028. if (!nbuf_copy) {
  2029. QDF_TRACE(QDF_MODULE_ID_DP,
  2030. QDF_TRACE_LEVEL_DEBUG,
  2031. FL("nbuf copy failed"));
  2032. break;
  2033. }
  2034. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2035. nbuf_copy,
  2036. &msdu_info,
  2037. peer_id,
  2038. NULL);
  2039. if (nbuf_copy) {
  2040. QDF_TRACE(QDF_MODULE_ID_DP,
  2041. QDF_TRACE_LEVEL_DEBUG,
  2042. FL("pkt send failed"));
  2043. qdf_nbuf_free(nbuf_copy);
  2044. } else {
  2045. if (peer_id != DP_INVALID_PEER)
  2046. DP_STATS_INC_PKT(peer,
  2047. tx.nawds_mcast,
  2048. 1, qdf_nbuf_len(nbuf));
  2049. }
  2050. }
  2051. }
  2052. }
  2053. if (vdev->nawds_enabled) {
  2054. peer_id = DP_INVALID_PEER;
  2055. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2056. 1, qdf_nbuf_len(nbuf));
  2057. nbuf = dp_tx_send_msdu_single(vdev,
  2058. nbuf,
  2059. &msdu_info,
  2060. peer_id, NULL);
  2061. if (nbuf) {
  2062. QDF_TRACE(QDF_MODULE_ID_DP,
  2063. QDF_TRACE_LEVEL_DEBUG,
  2064. FL("pkt send failed"));
  2065. qdf_nbuf_free(nbuf);
  2066. }
  2067. } else
  2068. qdf_nbuf_free(nbuf);
  2069. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2070. }
  2071. /**
  2072. * dp_tx_inspect_handler() - Tx Inspect Handler
  2073. * @tx_desc: software descriptor head pointer
  2074. * @status : Tx completion status from HTT descriptor
  2075. *
  2076. * Handles Tx frames sent back to Host for inspection
  2077. * (ProxyARP)
  2078. *
  2079. * Return: none
  2080. */
  2081. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2082. {
  2083. struct dp_soc *soc;
  2084. struct dp_pdev *pdev = tx_desc->pdev;
  2085. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2086. "%s Tx inspect path",
  2087. __func__);
  2088. qdf_assert(pdev);
  2089. soc = pdev->soc;
  2090. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2091. qdf_nbuf_len(tx_desc->nbuf));
  2092. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2093. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2094. }
  2095. #ifdef FEATURE_PERPKT_INFO
  2096. /**
  2097. * dp_get_completion_indication_for_stack() - send completion to stack
  2098. * @soc : dp_soc handle
  2099. * @pdev: dp_pdev handle
  2100. * @peer: dp peer handle
  2101. * @ts: transmit completion status structure
  2102. * @netbuf: Buffer pointer for free
  2103. *
  2104. * This function is used for indication whether buffer needs to be
  2105. * sent to stack for freeing or not
  2106. */
  2107. QDF_STATUS
  2108. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2109. struct dp_pdev *pdev,
  2110. struct dp_peer *peer,
  2111. struct hal_tx_completion_status *ts,
  2112. qdf_nbuf_t netbuf,
  2113. uint64_t time_latency)
  2114. {
  2115. struct tx_capture_hdr *ppdu_hdr;
  2116. uint16_t peer_id = ts->peer_id;
  2117. uint32_t ppdu_id = ts->ppdu_id;
  2118. uint8_t first_msdu = ts->first_msdu;
  2119. uint8_t last_msdu = ts->last_msdu;
  2120. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2121. !pdev->latency_capture_enable))
  2122. return QDF_STATUS_E_NOSUPPORT;
  2123. if (!peer) {
  2124. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2125. FL("Peer Invalid"));
  2126. return QDF_STATUS_E_INVAL;
  2127. }
  2128. if (pdev->mcopy_mode) {
  2129. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2130. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2131. return QDF_STATUS_E_INVAL;
  2132. }
  2133. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2134. pdev->m_copy_id.tx_peer_id = peer_id;
  2135. }
  2136. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2137. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2138. FL("No headroom"));
  2139. return QDF_STATUS_E_NOMEM;
  2140. }
  2141. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2142. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2143. QDF_MAC_ADDR_SIZE);
  2144. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2145. QDF_MAC_ADDR_SIZE);
  2146. ppdu_hdr->ppdu_id = ppdu_id;
  2147. ppdu_hdr->peer_id = peer_id;
  2148. ppdu_hdr->first_msdu = first_msdu;
  2149. ppdu_hdr->last_msdu = last_msdu;
  2150. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2151. ppdu_hdr->tsf = ts->tsf;
  2152. ppdu_hdr->time_latency = time_latency;
  2153. }
  2154. return QDF_STATUS_SUCCESS;
  2155. }
  2156. /**
  2157. * dp_send_completion_to_stack() - send completion to stack
  2158. * @soc : dp_soc handle
  2159. * @pdev: dp_pdev handle
  2160. * @peer_id: peer_id of the peer for which completion came
  2161. * @ppdu_id: ppdu_id
  2162. * @netbuf: Buffer pointer for free
  2163. *
  2164. * This function is used to send completion to stack
  2165. * to free buffer
  2166. */
  2167. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2168. uint16_t peer_id, uint32_t ppdu_id,
  2169. qdf_nbuf_t netbuf)
  2170. {
  2171. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2172. netbuf, peer_id,
  2173. WDI_NO_VAL, pdev->pdev_id);
  2174. }
  2175. #else
  2176. static QDF_STATUS
  2177. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2178. struct dp_pdev *pdev,
  2179. struct dp_peer *peer,
  2180. struct hal_tx_completion_status *ts,
  2181. qdf_nbuf_t netbuf,
  2182. uint64_t time_latency)
  2183. {
  2184. return QDF_STATUS_E_NOSUPPORT;
  2185. }
  2186. static void
  2187. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2188. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2189. {
  2190. }
  2191. #endif
  2192. /**
  2193. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2194. * @soc: Soc handle
  2195. * @desc: software Tx descriptor to be processed
  2196. *
  2197. * Return: none
  2198. */
  2199. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2200. struct dp_tx_desc_s *desc)
  2201. {
  2202. struct dp_vdev *vdev = desc->vdev;
  2203. qdf_nbuf_t nbuf = desc->nbuf;
  2204. /* nbuf already freed in vdev detach path */
  2205. if (!nbuf)
  2206. return;
  2207. /* If it is TDLS mgmt, don't unmap or free the frame */
  2208. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2209. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2210. /* 0 : MSDU buffer, 1 : MLE */
  2211. if (desc->msdu_ext_desc) {
  2212. /* TSO free */
  2213. if (hal_tx_ext_desc_get_tso_enable(
  2214. desc->msdu_ext_desc->vaddr)) {
  2215. /* unmap eash TSO seg before free the nbuf */
  2216. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2217. desc->tso_num_desc);
  2218. qdf_nbuf_free(nbuf);
  2219. return;
  2220. }
  2221. }
  2222. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2223. if (qdf_unlikely(!vdev)) {
  2224. qdf_nbuf_free(nbuf);
  2225. return;
  2226. }
  2227. if (qdf_likely(!vdev->mesh_vdev))
  2228. qdf_nbuf_free(nbuf);
  2229. else {
  2230. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2231. qdf_nbuf_free(nbuf);
  2232. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2233. } else
  2234. vdev->osif_tx_free_ext((nbuf));
  2235. }
  2236. }
  2237. #ifdef MESH_MODE_SUPPORT
  2238. /**
  2239. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2240. * in mesh meta header
  2241. * @tx_desc: software descriptor head pointer
  2242. * @ts: pointer to tx completion stats
  2243. * Return: none
  2244. */
  2245. static
  2246. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2247. struct hal_tx_completion_status *ts)
  2248. {
  2249. struct meta_hdr_s *mhdr;
  2250. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2251. if (!tx_desc->msdu_ext_desc) {
  2252. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2253. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2254. "netbuf %pK offset %d",
  2255. netbuf, tx_desc->pkt_offset);
  2256. return;
  2257. }
  2258. }
  2259. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2260. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2261. "netbuf %pK offset %lu", netbuf,
  2262. sizeof(struct meta_hdr_s));
  2263. return;
  2264. }
  2265. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2266. mhdr->rssi = ts->ack_frame_rssi;
  2267. mhdr->channel = tx_desc->pdev->operating_channel;
  2268. }
  2269. #else
  2270. static
  2271. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2272. struct hal_tx_completion_status *ts)
  2273. {
  2274. }
  2275. #endif
  2276. /**
  2277. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2278. * to pass in correct fields
  2279. *
  2280. * @vdev: pdev handle
  2281. * @tx_desc: tx descriptor
  2282. * @tid: tid value
  2283. * @ring_id: TCL or WBM ring number for transmit path
  2284. * Return: none
  2285. */
  2286. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2287. struct dp_tx_desc_s *tx_desc,
  2288. uint8_t tid, uint8_t ring_id)
  2289. {
  2290. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2291. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2292. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2293. return;
  2294. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2295. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2296. timestamp_hw_enqueue = tx_desc->timestamp;
  2297. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2298. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2299. timestamp_hw_enqueue);
  2300. interframe_delay = (uint32_t)(timestamp_ingress -
  2301. vdev->prev_tx_enq_tstamp);
  2302. /*
  2303. * Delay in software enqueue
  2304. */
  2305. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2306. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2307. /*
  2308. * Delay between packet enqueued to HW and Tx completion
  2309. */
  2310. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2311. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2312. /*
  2313. * Update interframe delay stats calculated at hardstart receive point.
  2314. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2315. * interframe delay will not be calculate correctly for 1st frame.
  2316. * On the other side, this will help in avoiding extra per packet check
  2317. * of !vdev->prev_tx_enq_tstamp.
  2318. */
  2319. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2320. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2321. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2322. }
  2323. /**
  2324. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2325. * per wbm ring
  2326. *
  2327. * @tx_desc: software descriptor head pointer
  2328. * @ts: Tx completion status
  2329. * @peer: peer handle
  2330. * @ring_id: ring number
  2331. *
  2332. * Return: None
  2333. */
  2334. static inline void
  2335. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2336. struct hal_tx_completion_status *ts,
  2337. struct dp_peer *peer, uint8_t ring_id)
  2338. {
  2339. struct dp_pdev *pdev = peer->vdev->pdev;
  2340. struct dp_soc *soc = NULL;
  2341. uint8_t mcs, pkt_type;
  2342. uint8_t tid = ts->tid;
  2343. uint32_t length;
  2344. struct cdp_tid_tx_stats *tid_stats;
  2345. if (!pdev)
  2346. return;
  2347. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2348. tid = CDP_MAX_DATA_TIDS - 1;
  2349. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2350. soc = pdev->soc;
  2351. mcs = ts->mcs;
  2352. pkt_type = ts->pkt_type;
  2353. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2354. dp_err("Release source is not from TQM");
  2355. return;
  2356. }
  2357. length = qdf_nbuf_len(tx_desc->nbuf);
  2358. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2359. if (qdf_unlikely(pdev->delay_stats_flag))
  2360. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2361. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2362. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2363. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2364. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2365. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2366. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2367. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2368. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2369. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2370. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2371. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2372. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2373. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2374. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2375. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2376. tid_stats->comp_fail_cnt++;
  2377. return;
  2378. }
  2379. tid_stats->success_cnt++;
  2380. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2381. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2382. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2383. /*
  2384. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2385. * Return from here if HTT PPDU events are enabled.
  2386. */
  2387. if (!(soc->process_tx_status))
  2388. return;
  2389. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2390. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2391. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2392. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2393. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2394. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2395. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2396. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2397. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2398. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2399. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2400. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2401. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2402. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2403. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2404. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2405. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2406. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2407. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2408. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2409. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2410. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2411. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2412. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2413. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2414. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2415. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2416. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2417. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2418. &peer->stats, ts->peer_id,
  2419. UPDATE_PEER_STATS, pdev->pdev_id);
  2420. #endif
  2421. }
  2422. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2423. /**
  2424. * dp_tx_flow_pool_lock() - take flow pool lock
  2425. * @soc: core txrx main context
  2426. * @tx_desc: tx desc
  2427. *
  2428. * Return: None
  2429. */
  2430. static inline
  2431. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2432. struct dp_tx_desc_s *tx_desc)
  2433. {
  2434. struct dp_tx_desc_pool_s *pool;
  2435. uint8_t desc_pool_id;
  2436. desc_pool_id = tx_desc->pool_id;
  2437. pool = &soc->tx_desc[desc_pool_id];
  2438. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2439. }
  2440. /**
  2441. * dp_tx_flow_pool_unlock() - release flow pool lock
  2442. * @soc: core txrx main context
  2443. * @tx_desc: tx desc
  2444. *
  2445. * Return: None
  2446. */
  2447. static inline
  2448. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2449. struct dp_tx_desc_s *tx_desc)
  2450. {
  2451. struct dp_tx_desc_pool_s *pool;
  2452. uint8_t desc_pool_id;
  2453. desc_pool_id = tx_desc->pool_id;
  2454. pool = &soc->tx_desc[desc_pool_id];
  2455. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2456. }
  2457. #else
  2458. static inline
  2459. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2460. {
  2461. }
  2462. static inline
  2463. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2464. {
  2465. }
  2466. #endif
  2467. /**
  2468. * dp_tx_notify_completion() - Notify tx completion for this desc
  2469. * @soc: core txrx main context
  2470. * @tx_desc: tx desc
  2471. * @netbuf: buffer
  2472. *
  2473. * Return: none
  2474. */
  2475. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2476. struct dp_tx_desc_s *tx_desc,
  2477. qdf_nbuf_t netbuf)
  2478. {
  2479. void *osif_dev;
  2480. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2481. qdf_assert(tx_desc);
  2482. dp_tx_flow_pool_lock(soc, tx_desc);
  2483. if (!tx_desc->vdev ||
  2484. !tx_desc->vdev->osif_vdev) {
  2485. dp_tx_flow_pool_unlock(soc, tx_desc);
  2486. return;
  2487. }
  2488. osif_dev = tx_desc->vdev->osif_vdev;
  2489. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2490. dp_tx_flow_pool_unlock(soc, tx_desc);
  2491. if (tx_compl_cbk)
  2492. tx_compl_cbk(netbuf, osif_dev);
  2493. }
  2494. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2495. * @pdev: pdev handle
  2496. * @tid: tid value
  2497. * @txdesc_ts: timestamp from txdesc
  2498. * @ppdu_id: ppdu id
  2499. *
  2500. * Return: none
  2501. */
  2502. #ifdef FEATURE_PERPKT_INFO
  2503. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2504. struct dp_peer *peer,
  2505. uint8_t tid,
  2506. uint64_t txdesc_ts,
  2507. uint32_t ppdu_id)
  2508. {
  2509. uint64_t delta_ms;
  2510. struct cdp_tx_sojourn_stats *sojourn_stats;
  2511. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2512. return;
  2513. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2514. tid >= CDP_DATA_TID_MAX))
  2515. return;
  2516. if (qdf_unlikely(!pdev->sojourn_buf))
  2517. return;
  2518. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2519. qdf_nbuf_data(pdev->sojourn_buf);
  2520. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2521. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2522. txdesc_ts;
  2523. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2524. delta_ms);
  2525. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2526. sojourn_stats->num_msdus[tid] = 1;
  2527. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2528. peer->avg_sojourn_msdu[tid].internal;
  2529. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2530. pdev->sojourn_buf, HTT_INVALID_PEER,
  2531. WDI_NO_VAL, pdev->pdev_id);
  2532. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2533. sojourn_stats->num_msdus[tid] = 0;
  2534. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2535. }
  2536. #else
  2537. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2538. uint8_t tid,
  2539. uint64_t txdesc_ts,
  2540. uint32_t ppdu_id)
  2541. {
  2542. }
  2543. #endif
  2544. /**
  2545. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2546. * @soc: DP Soc handle
  2547. * @tx_desc: software Tx descriptor
  2548. * @ts : Tx completion status from HAL/HTT descriptor
  2549. *
  2550. * Return: none
  2551. */
  2552. static inline void
  2553. dp_tx_comp_process_desc(struct dp_soc *soc,
  2554. struct dp_tx_desc_s *desc,
  2555. struct hal_tx_completion_status *ts,
  2556. struct dp_peer *peer)
  2557. {
  2558. uint64_t time_latency = 0;
  2559. /*
  2560. * m_copy/tx_capture modes are not supported for
  2561. * scatter gather packets
  2562. */
  2563. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2564. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2565. desc->timestamp);
  2566. }
  2567. if (!(desc->msdu_ext_desc)) {
  2568. if (QDF_STATUS_SUCCESS ==
  2569. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2570. return;
  2571. }
  2572. if (QDF_STATUS_SUCCESS ==
  2573. dp_get_completion_indication_for_stack(soc,
  2574. desc->pdev,
  2575. peer, ts,
  2576. desc->nbuf,
  2577. time_latency)) {
  2578. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2579. QDF_DMA_TO_DEVICE);
  2580. dp_send_completion_to_stack(soc,
  2581. desc->pdev,
  2582. ts->peer_id,
  2583. ts->ppdu_id,
  2584. desc->nbuf);
  2585. return;
  2586. }
  2587. }
  2588. dp_tx_comp_free_buf(soc, desc);
  2589. }
  2590. /**
  2591. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2592. * @tx_desc: software descriptor head pointer
  2593. * @ts: Tx completion status
  2594. * @peer: peer handle
  2595. * @ring_id: ring number
  2596. *
  2597. * Return: none
  2598. */
  2599. static inline
  2600. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2601. struct hal_tx_completion_status *ts,
  2602. struct dp_peer *peer, uint8_t ring_id)
  2603. {
  2604. uint32_t length;
  2605. qdf_ether_header_t *eh;
  2606. struct dp_soc *soc = NULL;
  2607. struct dp_vdev *vdev = tx_desc->vdev;
  2608. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2609. if (!vdev || !nbuf) {
  2610. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2611. "invalid tx descriptor. vdev or nbuf NULL");
  2612. goto out;
  2613. }
  2614. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2615. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2616. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2617. QDF_TRACE_DEFAULT_PDEV_ID,
  2618. qdf_nbuf_data_addr(nbuf),
  2619. sizeof(qdf_nbuf_data(nbuf)),
  2620. tx_desc->id,
  2621. ts->status));
  2622. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2623. "-------------------- \n"
  2624. "Tx Completion Stats: \n"
  2625. "-------------------- \n"
  2626. "ack_frame_rssi = %d \n"
  2627. "first_msdu = %d \n"
  2628. "last_msdu = %d \n"
  2629. "msdu_part_of_amsdu = %d \n"
  2630. "rate_stats valid = %d \n"
  2631. "bw = %d \n"
  2632. "pkt_type = %d \n"
  2633. "stbc = %d \n"
  2634. "ldpc = %d \n"
  2635. "sgi = %d \n"
  2636. "mcs = %d \n"
  2637. "ofdma = %d \n"
  2638. "tones_in_ru = %d \n"
  2639. "tsf = %d \n"
  2640. "ppdu_id = %d \n"
  2641. "transmit_cnt = %d \n"
  2642. "tid = %d \n"
  2643. "peer_id = %d\n",
  2644. ts->ack_frame_rssi, ts->first_msdu,
  2645. ts->last_msdu, ts->msdu_part_of_amsdu,
  2646. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2647. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2648. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2649. ts->transmit_cnt, ts->tid, ts->peer_id);
  2650. soc = vdev->pdev->soc;
  2651. /* Update SoC level stats */
  2652. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2653. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2654. /* Update per-packet stats for mesh mode */
  2655. if (qdf_unlikely(vdev->mesh_vdev) &&
  2656. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2657. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2658. length = qdf_nbuf_len(nbuf);
  2659. /* Update peer level stats */
  2660. if (!peer) {
  2661. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2662. "peer is null or deletion in progress");
  2663. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2664. goto out;
  2665. }
  2666. if (qdf_likely(!peer->bss_peer)) {
  2667. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2668. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2669. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2670. } else {
  2671. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2672. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2673. if ((peer->vdev->tx_encap_type ==
  2674. htt_cmn_pkt_type_ethernet) &&
  2675. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2676. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2677. }
  2678. }
  2679. }
  2680. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2681. #ifdef QCA_SUPPORT_RDK_STATS
  2682. if (soc->wlanstats_enabled)
  2683. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2684. tx_desc->timestamp,
  2685. ts->ppdu_id);
  2686. #endif
  2687. out:
  2688. return;
  2689. }
  2690. /**
  2691. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2692. * @soc: core txrx main context
  2693. * @comp_head: software descriptor head pointer
  2694. * @ring_id: ring number
  2695. *
  2696. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2697. * and release the software descriptors after processing is complete
  2698. *
  2699. * Return: none
  2700. */
  2701. static void
  2702. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2703. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2704. {
  2705. struct dp_tx_desc_s *desc;
  2706. struct dp_tx_desc_s *next;
  2707. struct hal_tx_completion_status ts = {0};
  2708. struct dp_peer *peer;
  2709. qdf_nbuf_t netbuf;
  2710. desc = comp_head;
  2711. while (desc) {
  2712. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2713. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2714. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2715. netbuf = desc->nbuf;
  2716. /* check tx complete notification */
  2717. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2718. dp_tx_notify_completion(soc, desc, netbuf);
  2719. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2720. if (peer)
  2721. dp_peer_unref_del_find_by_id(peer);
  2722. next = desc->next;
  2723. dp_tx_desc_release(desc, desc->pool_id);
  2724. desc = next;
  2725. }
  2726. }
  2727. /**
  2728. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2729. * @tx_desc: software descriptor head pointer
  2730. * @status : Tx completion status from HTT descriptor
  2731. * @ring_id: ring number
  2732. *
  2733. * This function will process HTT Tx indication messages from Target
  2734. *
  2735. * Return: none
  2736. */
  2737. static
  2738. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2739. uint8_t ring_id)
  2740. {
  2741. uint8_t tx_status;
  2742. struct dp_pdev *pdev;
  2743. struct dp_vdev *vdev;
  2744. struct dp_soc *soc;
  2745. struct hal_tx_completion_status ts = {0};
  2746. uint32_t *htt_desc = (uint32_t *)status;
  2747. struct dp_peer *peer;
  2748. struct cdp_tid_tx_stats *tid_stats = NULL;
  2749. qdf_assert(tx_desc->pdev);
  2750. pdev = tx_desc->pdev;
  2751. vdev = tx_desc->vdev;
  2752. soc = pdev->soc;
  2753. if (!vdev)
  2754. return;
  2755. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2756. switch (tx_status) {
  2757. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2758. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2759. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2760. {
  2761. uint8_t tid;
  2762. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2763. ts.peer_id =
  2764. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2765. htt_desc[2]);
  2766. ts.tid =
  2767. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2768. htt_desc[2]);
  2769. } else {
  2770. ts.peer_id = HTT_INVALID_PEER;
  2771. ts.tid = HTT_INVALID_TID;
  2772. }
  2773. ts.ppdu_id =
  2774. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2775. htt_desc[1]);
  2776. ts.ack_frame_rssi =
  2777. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2778. htt_desc[1]);
  2779. ts.first_msdu = 1;
  2780. ts.last_msdu = 1;
  2781. tid = ts.tid;
  2782. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2783. tid = CDP_MAX_DATA_TIDS - 1;
  2784. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2785. if (qdf_unlikely(pdev->delay_stats_flag))
  2786. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2787. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2788. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2789. tid_stats->comp_fail_cnt++;
  2790. } else {
  2791. tid_stats->success_cnt++;
  2792. }
  2793. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2794. if (qdf_likely(peer))
  2795. dp_peer_unref_del_find_by_id(peer);
  2796. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2797. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2798. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2799. break;
  2800. }
  2801. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2802. {
  2803. dp_tx_reinject_handler(tx_desc, status);
  2804. break;
  2805. }
  2806. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2807. {
  2808. dp_tx_inspect_handler(tx_desc, status);
  2809. break;
  2810. }
  2811. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2812. {
  2813. dp_tx_mec_handler(vdev, status);
  2814. break;
  2815. }
  2816. default:
  2817. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2818. "%s Invalid HTT tx_status %d\n",
  2819. __func__, tx_status);
  2820. break;
  2821. }
  2822. }
  2823. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2824. static inline
  2825. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2826. {
  2827. bool limit_hit = false;
  2828. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2829. limit_hit =
  2830. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2831. if (limit_hit)
  2832. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2833. return limit_hit;
  2834. }
  2835. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2836. {
  2837. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2838. }
  2839. #else
  2840. static inline
  2841. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2842. {
  2843. return false;
  2844. }
  2845. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2846. {
  2847. return false;
  2848. }
  2849. #endif
  2850. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2851. void *hal_srng, uint8_t ring_id, uint32_t quota)
  2852. {
  2853. void *tx_comp_hal_desc;
  2854. uint8_t buffer_src;
  2855. uint8_t pool_id;
  2856. uint32_t tx_desc_id;
  2857. struct dp_tx_desc_s *tx_desc = NULL;
  2858. struct dp_tx_desc_s *head_desc = NULL;
  2859. struct dp_tx_desc_s *tail_desc = NULL;
  2860. uint32_t num_processed = 0;
  2861. uint32_t count = 0;
  2862. bool force_break = false;
  2863. DP_HIST_INIT();
  2864. more_data:
  2865. /* Re-initialize local variables to be re-used */
  2866. head_desc = NULL;
  2867. tail_desc = NULL;
  2868. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_srng))) {
  2869. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2870. "%s %d : HAL RING Access Failed -- %pK",
  2871. __func__, __LINE__, hal_srng);
  2872. return 0;
  2873. }
  2874. /* Find head descriptor from completion ring */
  2875. while (qdf_likely(tx_comp_hal_desc =
  2876. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2877. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2878. /* If this buffer was not released by TQM or FW, then it is not
  2879. * Tx completion indication, assert */
  2880. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2881. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2882. QDF_TRACE(QDF_MODULE_ID_DP,
  2883. QDF_TRACE_LEVEL_FATAL,
  2884. "Tx comp release_src != TQM | FW but from %d",
  2885. buffer_src);
  2886. hal_dump_comp_desc(tx_comp_hal_desc);
  2887. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2888. qdf_assert_always(0);
  2889. }
  2890. /* Get descriptor id */
  2891. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2892. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2893. DP_TX_DESC_ID_POOL_OS;
  2894. /* Find Tx descriptor */
  2895. tx_desc = dp_tx_desc_find(soc, pool_id,
  2896. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2897. DP_TX_DESC_ID_PAGE_OS,
  2898. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2899. DP_TX_DESC_ID_OFFSET_OS);
  2900. /*
  2901. * If the descriptor is already freed in vdev_detach,
  2902. * continue to next descriptor
  2903. */
  2904. if (!tx_desc->vdev && !tx_desc->flags) {
  2905. QDF_TRACE(QDF_MODULE_ID_DP,
  2906. QDF_TRACE_LEVEL_INFO,
  2907. "Descriptor freed in vdev_detach %d",
  2908. tx_desc_id);
  2909. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2910. count++;
  2911. continue;
  2912. }
  2913. /*
  2914. * If the release source is FW, process the HTT status
  2915. */
  2916. if (qdf_unlikely(buffer_src ==
  2917. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2918. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2919. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2920. htt_tx_status);
  2921. dp_tx_process_htt_completion(tx_desc,
  2922. htt_tx_status, ring_id);
  2923. } else {
  2924. /* Pool id is not matching. Error */
  2925. if (tx_desc->pool_id != pool_id) {
  2926. QDF_TRACE(QDF_MODULE_ID_DP,
  2927. QDF_TRACE_LEVEL_FATAL,
  2928. "Tx Comp pool id %d not matched %d",
  2929. pool_id, tx_desc->pool_id);
  2930. qdf_assert_always(0);
  2931. }
  2932. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2933. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2934. QDF_TRACE(QDF_MODULE_ID_DP,
  2935. QDF_TRACE_LEVEL_FATAL,
  2936. "Txdesc invalid, flgs = %x,id = %d",
  2937. tx_desc->flags, tx_desc_id);
  2938. qdf_assert_always(0);
  2939. }
  2940. /* First ring descriptor on the cycle */
  2941. if (!head_desc) {
  2942. head_desc = tx_desc;
  2943. tail_desc = tx_desc;
  2944. }
  2945. tail_desc->next = tx_desc;
  2946. tx_desc->next = NULL;
  2947. tail_desc = tx_desc;
  2948. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  2949. /* Collect hw completion contents */
  2950. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2951. &tx_desc->comp, 1);
  2952. }
  2953. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2954. /*
  2955. * Processed packet count is more than given quota
  2956. * stop to processing
  2957. */
  2958. if (num_processed >= quota) {
  2959. force_break = true;
  2960. break;
  2961. }
  2962. count++;
  2963. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  2964. break;
  2965. }
  2966. dp_srng_access_end(int_ctx, soc, hal_srng);
  2967. /* Process the reaped descriptors */
  2968. if (head_desc)
  2969. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  2970. if (dp_tx_comp_enable_eol_data_check(soc)) {
  2971. if (!force_break &&
  2972. hal_srng_dst_peek_sync_locked(soc, hal_srng)) {
  2973. DP_STATS_INC(soc, tx.hp_oos2, 1);
  2974. if (!hif_exec_should_yield(soc->hif_handle,
  2975. int_ctx->dp_intr_id))
  2976. goto more_data;
  2977. }
  2978. }
  2979. DP_TX_HIST_STATS_PER_PDEV();
  2980. return num_processed;
  2981. }
  2982. #ifdef FEATURE_WLAN_TDLS
  2983. /**
  2984. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2985. *
  2986. * @data_vdev - which vdev should transmit the tx data frames
  2987. * @tx_spec - what non-standard handling to apply to the tx data frames
  2988. * @msdu_list - NULL-terminated list of tx MSDUs
  2989. *
  2990. * Return: NULL on success,
  2991. * nbuf when it fails to send
  2992. */
  2993. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2994. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2995. {
  2996. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2997. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2998. vdev->is_tdls_frame = true;
  2999. return dp_tx_send(vdev_handle, msdu_list);
  3000. }
  3001. #endif
  3002. /**
  3003. * dp_tx_vdev_attach() - attach vdev to dp tx
  3004. * @vdev: virtual device instance
  3005. *
  3006. * Return: QDF_STATUS_SUCCESS: success
  3007. * QDF_STATUS_E_RESOURCES: Error return
  3008. */
  3009. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3010. {
  3011. /*
  3012. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3013. */
  3014. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3015. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3016. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3017. vdev->vdev_id);
  3018. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3019. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3020. /*
  3021. * Set HTT Extension Valid bit to 0 by default
  3022. */
  3023. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3024. dp_tx_vdev_update_search_flags(vdev);
  3025. return QDF_STATUS_SUCCESS;
  3026. }
  3027. #ifndef FEATURE_WDS
  3028. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3029. {
  3030. return false;
  3031. }
  3032. #endif
  3033. /**
  3034. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3035. * @vdev: virtual device instance
  3036. *
  3037. * Return: void
  3038. *
  3039. */
  3040. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3041. {
  3042. struct dp_soc *soc = vdev->pdev->soc;
  3043. /*
  3044. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3045. * for TDLS link
  3046. *
  3047. * Enable AddrY (SA based search) only for non-WDS STA and
  3048. * ProxySTA VAP (in HKv1) modes.
  3049. *
  3050. * In all other VAP modes, only DA based search should be
  3051. * enabled
  3052. */
  3053. if (vdev->opmode == wlan_op_mode_sta &&
  3054. vdev->tdls_link_connected)
  3055. vdev->hal_desc_addr_search_flags =
  3056. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3057. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3058. !dp_tx_da_search_override(vdev))
  3059. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3060. else
  3061. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3062. /* Set search type only when peer map v2 messaging is enabled
  3063. * as we will have the search index (AST hash) only when v2 is
  3064. * enabled
  3065. */
  3066. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3067. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3068. else
  3069. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3070. }
  3071. static inline bool
  3072. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3073. struct dp_vdev *vdev,
  3074. struct dp_tx_desc_s *tx_desc)
  3075. {
  3076. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3077. return false;
  3078. /*
  3079. * if vdev is given, then only check whether desc
  3080. * vdev match. if vdev is NULL, then check whether
  3081. * desc pdev match.
  3082. */
  3083. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3084. }
  3085. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3086. /**
  3087. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3088. *
  3089. * @soc: Handle to DP SoC structure
  3090. * @tx_desc: pointer of one TX desc
  3091. * @desc_pool_id: TX Desc pool id
  3092. */
  3093. static inline void
  3094. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3095. uint8_t desc_pool_id)
  3096. {
  3097. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3098. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3099. tx_desc->vdev = NULL;
  3100. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3101. }
  3102. /**
  3103. * dp_tx_desc_flush() - release resources associated
  3104. * to TX Desc
  3105. *
  3106. * @dp_pdev: Handle to DP pdev structure
  3107. * @vdev: virtual device instance
  3108. * NULL: no specific Vdev is required and check all allcated TX desc
  3109. * on this pdev.
  3110. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3111. *
  3112. * @force_free:
  3113. * true: flush the TX desc.
  3114. * false: only reset the Vdev in each allocated TX desc
  3115. * that associated to current Vdev.
  3116. *
  3117. * This function will go through the TX desc pool to flush
  3118. * the outstanding TX data or reset Vdev to NULL in associated TX
  3119. * Desc.
  3120. */
  3121. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3122. struct dp_vdev *vdev,
  3123. bool force_free)
  3124. {
  3125. uint8_t i;
  3126. uint32_t j;
  3127. uint32_t num_desc, page_id, offset;
  3128. uint16_t num_desc_per_page;
  3129. struct dp_soc *soc = pdev->soc;
  3130. struct dp_tx_desc_s *tx_desc = NULL;
  3131. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3132. if (!vdev && !force_free) {
  3133. dp_err("Reset TX desc vdev, Vdev param is required!");
  3134. return;
  3135. }
  3136. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3137. tx_desc_pool = &soc->tx_desc[i];
  3138. if (!(tx_desc_pool->pool_size) ||
  3139. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3140. !(tx_desc_pool->desc_pages.cacheable_pages))
  3141. continue;
  3142. num_desc = tx_desc_pool->pool_size;
  3143. num_desc_per_page =
  3144. tx_desc_pool->desc_pages.num_element_per_page;
  3145. for (j = 0; j < num_desc; j++) {
  3146. page_id = j / num_desc_per_page;
  3147. offset = j % num_desc_per_page;
  3148. if (qdf_unlikely(!(tx_desc_pool->
  3149. desc_pages.cacheable_pages)))
  3150. break;
  3151. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3152. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3153. /*
  3154. * Free TX desc if force free is
  3155. * required, otherwise only reset vdev
  3156. * in this TX desc.
  3157. */
  3158. if (force_free) {
  3159. dp_tx_comp_free_buf(soc, tx_desc);
  3160. dp_tx_desc_release(tx_desc, i);
  3161. } else {
  3162. dp_tx_desc_reset_vdev(soc, tx_desc,
  3163. i);
  3164. }
  3165. }
  3166. }
  3167. }
  3168. }
  3169. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3170. static inline void
  3171. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3172. uint8_t desc_pool_id)
  3173. {
  3174. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3175. tx_desc->vdev = NULL;
  3176. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3177. }
  3178. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3179. struct dp_vdev *vdev,
  3180. bool force_free)
  3181. {
  3182. uint8_t i, num_pool;
  3183. uint32_t j;
  3184. uint32_t num_desc, page_id, offset;
  3185. uint16_t num_desc_per_page;
  3186. struct dp_soc *soc = pdev->soc;
  3187. struct dp_tx_desc_s *tx_desc = NULL;
  3188. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3189. if (!vdev && !force_free) {
  3190. dp_err("Reset TX desc vdev, Vdev param is required!");
  3191. return;
  3192. }
  3193. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3194. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3195. for (i = 0; i < num_pool; i++) {
  3196. tx_desc_pool = &soc->tx_desc[i];
  3197. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3198. continue;
  3199. num_desc_per_page =
  3200. tx_desc_pool->desc_pages.num_element_per_page;
  3201. for (j = 0; j < num_desc; j++) {
  3202. page_id = j / num_desc_per_page;
  3203. offset = j % num_desc_per_page;
  3204. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3205. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3206. if (force_free) {
  3207. dp_tx_comp_free_buf(soc, tx_desc);
  3208. dp_tx_desc_release(tx_desc, i);
  3209. } else {
  3210. dp_tx_desc_reset_vdev(soc, tx_desc,
  3211. i);
  3212. }
  3213. }
  3214. }
  3215. }
  3216. }
  3217. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3218. /**
  3219. * dp_tx_vdev_detach() - detach vdev from dp tx
  3220. * @vdev: virtual device instance
  3221. *
  3222. * Return: QDF_STATUS_SUCCESS: success
  3223. * QDF_STATUS_E_RESOURCES: Error return
  3224. */
  3225. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3226. {
  3227. struct dp_pdev *pdev = vdev->pdev;
  3228. /* Reset TX desc associated to this Vdev as NULL */
  3229. dp_tx_desc_flush(pdev, vdev, false);
  3230. return QDF_STATUS_SUCCESS;
  3231. }
  3232. /**
  3233. * dp_tx_pdev_attach() - attach pdev to dp tx
  3234. * @pdev: physical device instance
  3235. *
  3236. * Return: QDF_STATUS_SUCCESS: success
  3237. * QDF_STATUS_E_RESOURCES: Error return
  3238. */
  3239. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3240. {
  3241. struct dp_soc *soc = pdev->soc;
  3242. /* Initialize Flow control counters */
  3243. qdf_atomic_init(&pdev->num_tx_exception);
  3244. qdf_atomic_init(&pdev->num_tx_outstanding);
  3245. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3246. /* Initialize descriptors in TCL Ring */
  3247. hal_tx_init_data_ring(soc->hal_soc,
  3248. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3249. }
  3250. return QDF_STATUS_SUCCESS;
  3251. }
  3252. /**
  3253. * dp_tx_pdev_detach() - detach pdev from dp tx
  3254. * @pdev: physical device instance
  3255. *
  3256. * Return: QDF_STATUS_SUCCESS: success
  3257. * QDF_STATUS_E_RESOURCES: Error return
  3258. */
  3259. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3260. {
  3261. /* flush TX outstanding data per pdev */
  3262. dp_tx_desc_flush(pdev, NULL, true);
  3263. dp_tx_me_exit(pdev);
  3264. return QDF_STATUS_SUCCESS;
  3265. }
  3266. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3267. /* Pools will be allocated dynamically */
  3268. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3269. int num_desc)
  3270. {
  3271. uint8_t i;
  3272. for (i = 0; i < num_pool; i++) {
  3273. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3274. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3275. }
  3276. return 0;
  3277. }
  3278. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3279. {
  3280. uint8_t i;
  3281. for (i = 0; i < num_pool; i++)
  3282. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3283. }
  3284. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3285. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3286. int num_desc)
  3287. {
  3288. uint8_t i;
  3289. /* Allocate software Tx descriptor pools */
  3290. for (i = 0; i < num_pool; i++) {
  3291. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3292. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3293. "%s Tx Desc Pool alloc %d failed %pK",
  3294. __func__, i, soc);
  3295. return ENOMEM;
  3296. }
  3297. }
  3298. return 0;
  3299. }
  3300. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3301. {
  3302. uint8_t i;
  3303. for (i = 0; i < num_pool; i++) {
  3304. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3305. if (dp_tx_desc_pool_free(soc, i)) {
  3306. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3307. "%s Tx Desc Pool Free failed", __func__);
  3308. }
  3309. }
  3310. }
  3311. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3312. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3313. /**
  3314. * dp_tso_attach_wifi3() - TSO attach handler
  3315. * @txrx_soc: Opaque Dp handle
  3316. *
  3317. * Reserve TSO descriptor buffers
  3318. *
  3319. * Return: QDF_STATUS_E_FAILURE on failure or
  3320. * QDF_STATUS_SUCCESS on success
  3321. */
  3322. static
  3323. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3324. {
  3325. return dp_tso_soc_attach(txrx_soc);
  3326. }
  3327. /**
  3328. * dp_tso_detach_wifi3() - TSO Detach handler
  3329. * @txrx_soc: Opaque Dp handle
  3330. *
  3331. * Deallocate TSO descriptor buffers
  3332. *
  3333. * Return: QDF_STATUS_E_FAILURE on failure or
  3334. * QDF_STATUS_SUCCESS on success
  3335. */
  3336. static
  3337. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3338. {
  3339. return dp_tso_soc_detach(txrx_soc);
  3340. }
  3341. #else
  3342. static
  3343. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3344. {
  3345. return QDF_STATUS_SUCCESS;
  3346. }
  3347. static
  3348. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3349. {
  3350. return QDF_STATUS_SUCCESS;
  3351. }
  3352. #endif
  3353. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3354. {
  3355. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3356. uint8_t i;
  3357. uint8_t num_pool;
  3358. uint32_t num_desc;
  3359. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3360. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3361. for (i = 0; i < num_pool; i++)
  3362. dp_tx_tso_desc_pool_free(soc, i);
  3363. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3364. __func__, num_pool, num_desc);
  3365. for (i = 0; i < num_pool; i++)
  3366. dp_tx_tso_num_seg_pool_free(soc, i);
  3367. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3368. __func__, num_pool, num_desc);
  3369. return QDF_STATUS_SUCCESS;
  3370. }
  3371. /**
  3372. * dp_tso_attach() - TSO attach handler
  3373. * @txrx_soc: Opaque Dp handle
  3374. *
  3375. * Reserve TSO descriptor buffers
  3376. *
  3377. * Return: QDF_STATUS_E_FAILURE on failure or
  3378. * QDF_STATUS_SUCCESS on success
  3379. */
  3380. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3381. {
  3382. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3383. uint8_t i;
  3384. uint8_t num_pool;
  3385. uint32_t num_desc;
  3386. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3387. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3388. for (i = 0; i < num_pool; i++) {
  3389. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3390. dp_err("TSO Desc Pool alloc %d failed %pK",
  3391. i, soc);
  3392. return QDF_STATUS_E_FAILURE;
  3393. }
  3394. }
  3395. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3396. __func__, num_pool, num_desc);
  3397. for (i = 0; i < num_pool; i++) {
  3398. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3399. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3400. i, soc);
  3401. return QDF_STATUS_E_FAILURE;
  3402. }
  3403. }
  3404. return QDF_STATUS_SUCCESS;
  3405. }
  3406. /**
  3407. * dp_tx_soc_detach() - detach soc from dp tx
  3408. * @soc: core txrx main context
  3409. *
  3410. * This function will detach dp tx into main device context
  3411. * will free dp tx resource and initialize resources
  3412. *
  3413. * Return: QDF_STATUS_SUCCESS: success
  3414. * QDF_STATUS_E_RESOURCES: Error return
  3415. */
  3416. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3417. {
  3418. uint8_t num_pool;
  3419. uint16_t num_desc;
  3420. uint16_t num_ext_desc;
  3421. uint8_t i;
  3422. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3423. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3424. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3425. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3426. dp_tx_flow_control_deinit(soc);
  3427. dp_tx_delete_static_pools(soc, num_pool);
  3428. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3429. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3430. __func__, num_pool, num_desc);
  3431. for (i = 0; i < num_pool; i++) {
  3432. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3433. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3434. "%s Tx Ext Desc Pool Free failed",
  3435. __func__);
  3436. return QDF_STATUS_E_RESOURCES;
  3437. }
  3438. }
  3439. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3440. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3441. __func__, num_pool, num_ext_desc);
  3442. status = dp_tso_detach_wifi3(soc);
  3443. if (status != QDF_STATUS_SUCCESS)
  3444. return status;
  3445. return QDF_STATUS_SUCCESS;
  3446. }
  3447. /**
  3448. * dp_tx_soc_attach() - attach soc to dp tx
  3449. * @soc: core txrx main context
  3450. *
  3451. * This function will attach dp tx into main device context
  3452. * will allocate dp tx resource and initialize resources
  3453. *
  3454. * Return: QDF_STATUS_SUCCESS: success
  3455. * QDF_STATUS_E_RESOURCES: Error return
  3456. */
  3457. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3458. {
  3459. uint8_t i;
  3460. uint8_t num_pool;
  3461. uint32_t num_desc;
  3462. uint32_t num_ext_desc;
  3463. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3464. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3465. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3466. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3467. if (num_pool > MAX_TXDESC_POOLS)
  3468. goto fail;
  3469. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3470. goto fail;
  3471. dp_tx_flow_control_init(soc);
  3472. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3473. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3474. __func__, num_pool, num_desc);
  3475. /* Allocate extension tx descriptor pools */
  3476. for (i = 0; i < num_pool; i++) {
  3477. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3478. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3479. "MSDU Ext Desc Pool alloc %d failed %pK",
  3480. i, soc);
  3481. goto fail;
  3482. }
  3483. }
  3484. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3485. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3486. __func__, num_pool, num_ext_desc);
  3487. status = dp_tso_attach_wifi3((void *)soc);
  3488. if (status != QDF_STATUS_SUCCESS)
  3489. goto fail;
  3490. /* Initialize descriptors in TCL Rings */
  3491. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3492. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3493. hal_tx_init_data_ring(soc->hal_soc,
  3494. soc->tcl_data_ring[i].hal_srng);
  3495. }
  3496. }
  3497. /*
  3498. * todo - Add a runtime config option to enable this.
  3499. */
  3500. /*
  3501. * Due to multiple issues on NPR EMU, enable it selectively
  3502. * only for NPR EMU, should be removed, once NPR platforms
  3503. * are stable.
  3504. */
  3505. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3506. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3507. "%s HAL Tx init Success", __func__);
  3508. return QDF_STATUS_SUCCESS;
  3509. fail:
  3510. /* Detach will take care of freeing only allocated resources */
  3511. dp_tx_soc_detach(soc);
  3512. return QDF_STATUS_E_RESOURCES;
  3513. }