dp_be_rx.c 41 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_types.h"
  22. #include "dp_rx.h"
  23. #include "dp_tx.h"
  24. #include "dp_be_rx.h"
  25. #include "dp_peer.h"
  26. #include "hal_rx.h"
  27. #include "hal_be_rx.h"
  28. #include "hal_api.h"
  29. #include "hal_be_api.h"
  30. #include "qdf_nbuf.h"
  31. #include "hal_be_rx_tlv.h"
  32. #ifdef MESH_MODE_SUPPORT
  33. #include "if_meta_hdr.h"
  34. #endif
  35. #include "dp_internal.h"
  36. #include "dp_ipa.h"
  37. #ifdef FEATURE_WDS
  38. #include "dp_txrx_wds.h"
  39. #endif
  40. #include "dp_hist.h"
  41. #include "dp_rx_buffer_pool.h"
  42. #ifndef AST_OFFLOAD_ENABLE
  43. static void
  44. dp_rx_wds_learn(struct dp_soc *soc,
  45. struct dp_vdev *vdev,
  46. uint8_t *rx_tlv_hdr,
  47. struct dp_txrx_peer *txrx_peer,
  48. qdf_nbuf_t nbuf,
  49. struct hal_rx_msdu_metadata msdu_metadata)
  50. {
  51. /* WDS Source Port Learning */
  52. if (qdf_likely(vdev->wds_enabled))
  53. dp_rx_wds_srcport_learn(soc,
  54. rx_tlv_hdr,
  55. txrx_peer,
  56. nbuf,
  57. msdu_metadata);
  58. }
  59. #else
  60. #ifdef QCA_SUPPORT_WDS_EXTENDED
  61. /**
  62. * dp_wds_ext_peer_learn_be() - function to send event to control
  63. * path on receiving 1st 4-address frame from backhaul.
  64. * @soc: DP soc
  65. * @ta_txrx_peer: WDS repeater txrx peer
  66. * @rx_tlv_hdr : start address of rx tlvs
  67. *
  68. * Return: void
  69. */
  70. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  71. struct dp_txrx_peer *ta_txrx_peer,
  72. uint8_t *rx_tlv_hdr)
  73. {
  74. uint8_t wds_ext_src_mac[QDF_MAC_ADDR_SIZE];
  75. struct dp_peer *ta_base_peer;
  76. /* instead of checking addr4 is valid or not in per packet path
  77. * check for init bit, which will be set on reception of
  78. * first addr4 valid packet.
  79. */
  80. if (!ta_txrx_peer->vdev->wds_ext_enabled ||
  81. qdf_atomic_test_bit(WDS_EXT_PEER_INIT_BIT,
  82. &ta_txrx_peer->wds_ext.init))
  83. return;
  84. if (hal_rx_get_mpdu_mac_ad4_valid_be(rx_tlv_hdr)) {
  85. qdf_atomic_test_and_set_bit(WDS_EXT_PEER_INIT_BIT,
  86. &ta_txrx_peer->wds_ext.init);
  87. ta_base_peer = dp_peer_get_ref_by_id(soc, ta_txrx_peer->peer_id,
  88. DP_MOD_ID_RX);
  89. if (!ta_base_peer)
  90. return;
  91. qdf_mem_copy(wds_ext_src_mac, &ta_base_peer->mac_addr.raw[0],
  92. QDF_MAC_ADDR_SIZE);
  93. dp_peer_unref_delete(ta_base_peer, DP_MOD_ID_RX);
  94. soc->cdp_soc.ol_ops->rx_wds_ext_peer_learn(
  95. soc->ctrl_psoc,
  96. ta_txrx_peer->peer_id,
  97. ta_txrx_peer->vdev->vdev_id,
  98. wds_ext_src_mac);
  99. }
  100. }
  101. #else
  102. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  103. struct dp_txrx_peer *ta_txrx_peer,
  104. uint8_t *rx_tlv_hdr)
  105. {
  106. }
  107. #endif
  108. static void
  109. dp_rx_wds_learn(struct dp_soc *soc,
  110. struct dp_vdev *vdev,
  111. uint8_t *rx_tlv_hdr,
  112. struct dp_txrx_peer *ta_txrx_peer,
  113. qdf_nbuf_t nbuf,
  114. struct hal_rx_msdu_metadata msdu_metadata)
  115. {
  116. dp_wds_ext_peer_learn_be(soc, ta_txrx_peer, rx_tlv_hdr);
  117. }
  118. #endif
  119. /**
  120. * dp_rx_process_be() - Brain of the Rx processing functionality
  121. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  122. * @int_ctx: per interrupt context
  123. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  124. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  125. * @quota: No. of units (packets) that can be serviced in one shot.
  126. *
  127. * This function implements the core of Rx functionality. This is
  128. * expected to handle only non-error frames.
  129. *
  130. * Return: uint32_t: No. of elements processed
  131. */
  132. uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
  133. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  134. uint32_t quota)
  135. {
  136. hal_ring_desc_t ring_desc;
  137. hal_soc_handle_t hal_soc;
  138. struct dp_rx_desc *rx_desc = NULL;
  139. qdf_nbuf_t nbuf, next;
  140. bool near_full;
  141. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  142. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  143. uint32_t num_pending;
  144. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  145. uint16_t msdu_len = 0;
  146. uint16_t peer_id;
  147. uint8_t vdev_id;
  148. struct dp_txrx_peer *txrx_peer;
  149. dp_txrx_ref_handle txrx_ref_handle = NULL;
  150. struct dp_vdev *vdev;
  151. uint32_t pkt_len = 0;
  152. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  153. struct hal_rx_msdu_desc_info msdu_desc_info;
  154. enum hal_reo_error_status error;
  155. uint32_t peer_mdata;
  156. uint8_t *rx_tlv_hdr;
  157. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  158. uint8_t mac_id = 0;
  159. struct dp_pdev *rx_pdev;
  160. bool enh_flag;
  161. struct dp_srng *dp_rxdma_srng;
  162. struct rx_desc_pool *rx_desc_pool;
  163. struct dp_soc *soc = int_ctx->soc;
  164. uint8_t core_id = 0;
  165. struct cdp_tid_rx_stats *tid_stats;
  166. qdf_nbuf_t nbuf_head;
  167. qdf_nbuf_t nbuf_tail;
  168. qdf_nbuf_t deliver_list_head;
  169. qdf_nbuf_t deliver_list_tail;
  170. uint32_t num_rx_bufs_reaped = 0;
  171. uint32_t intr_id;
  172. struct hif_opaque_softc *scn;
  173. int32_t tid = 0;
  174. bool is_prev_msdu_last = true;
  175. uint32_t num_entries_avail = 0;
  176. uint32_t rx_ol_pkt_cnt = 0;
  177. uint32_t num_entries = 0;
  178. struct hal_rx_msdu_metadata msdu_metadata;
  179. QDF_STATUS status;
  180. qdf_nbuf_t ebuf_head;
  181. qdf_nbuf_t ebuf_tail;
  182. uint8_t pkt_capture_offload = 0;
  183. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  184. int max_reap_limit, ring_near_full;
  185. struct dp_soc *replenish_soc;
  186. DP_HIST_INIT();
  187. qdf_assert_always(soc && hal_ring_hdl);
  188. hal_soc = soc->hal_soc;
  189. qdf_assert_always(hal_soc);
  190. scn = soc->hif_handle;
  191. hif_pm_runtime_mark_dp_rx_busy(scn);
  192. intr_id = int_ctx->dp_intr_id;
  193. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  194. more_data:
  195. /* reset local variables here to be re-used in the function */
  196. nbuf_head = NULL;
  197. nbuf_tail = NULL;
  198. deliver_list_head = NULL;
  199. deliver_list_tail = NULL;
  200. txrx_peer = NULL;
  201. vdev = NULL;
  202. num_rx_bufs_reaped = 0;
  203. ebuf_head = NULL;
  204. ebuf_tail = NULL;
  205. ring_near_full = 0;
  206. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  207. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  208. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  209. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  210. qdf_mem_zero(head, sizeof(head));
  211. qdf_mem_zero(tail, sizeof(tail));
  212. ring_near_full = _dp_srng_test_and_update_nf_params(soc, rx_ring,
  213. &max_reap_limit);
  214. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  215. /*
  216. * Need API to convert from hal_ring pointer to
  217. * Ring Type / Ring Id combo
  218. */
  219. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  220. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  221. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  222. goto done;
  223. }
  224. /*
  225. * start reaping the buffers from reo ring and queue
  226. * them in per vdev queue.
  227. * Process the received pkts in a different per vdev loop.
  228. */
  229. while (qdf_likely(quota &&
  230. (ring_desc = hal_srng_dst_peek(hal_soc,
  231. hal_ring_hdl)))) {
  232. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  233. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  234. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  235. soc, hal_ring_hdl, error);
  236. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  237. 1);
  238. /* Don't know how to deal with this -- assert */
  239. qdf_assert(0);
  240. }
  241. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  242. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  243. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  244. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  245. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  246. break;
  247. }
  248. rx_desc = (struct dp_rx_desc *)
  249. hal_rx_get_reo_desc_va(ring_desc);
  250. dp_rx_desc_sw_cc_check(soc, rx_buf_cookie, &rx_desc);
  251. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  252. ring_desc, rx_desc);
  253. if (QDF_IS_STATUS_ERROR(status)) {
  254. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  255. qdf_assert_always(!rx_desc->unmapped);
  256. dp_rx_nbuf_unmap(soc, rx_desc, reo_ring_num);
  257. rx_desc->unmapped = 1;
  258. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  259. rx_desc->pool_id);
  260. dp_rx_add_to_free_desc_list(
  261. &head[rx_desc->pool_id],
  262. &tail[rx_desc->pool_id],
  263. rx_desc);
  264. }
  265. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  266. continue;
  267. }
  268. /*
  269. * this is a unlikely scenario where the host is reaping
  270. * a descriptor which it already reaped just a while ago
  271. * but is yet to replenish it back to HW.
  272. * In this case host will dump the last 128 descriptors
  273. * including the software descriptor rx_desc and assert.
  274. */
  275. if (qdf_unlikely(!rx_desc->in_use)) {
  276. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  277. dp_info_rl("Reaping rx_desc not in use!");
  278. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  279. ring_desc, rx_desc);
  280. /* ignore duplicate RX desc and continue to process */
  281. /* Pop out the descriptor */
  282. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  283. continue;
  284. }
  285. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  286. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  287. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  288. dp_info_rl("Nbuf sanity check failure!");
  289. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  290. ring_desc, rx_desc);
  291. rx_desc->in_err_state = 1;
  292. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  293. continue;
  294. }
  295. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  296. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  297. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  298. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  299. ring_desc, rx_desc);
  300. }
  301. /* Get MPDU DESC info */
  302. hal_rx_mpdu_desc_info_get_be(ring_desc, &mpdu_desc_info);
  303. /* Get MSDU DESC info */
  304. hal_rx_msdu_desc_info_get_be(ring_desc, &msdu_desc_info);
  305. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  306. HAL_MSDU_F_MSDU_CONTINUATION)) {
  307. /* previous msdu has end bit set, so current one is
  308. * the new MPDU
  309. */
  310. if (is_prev_msdu_last) {
  311. /* Get number of entries available in HW ring */
  312. num_entries_avail =
  313. hal_srng_dst_num_valid(hal_soc,
  314. hal_ring_hdl, 1);
  315. /* For new MPDU check if we can read complete
  316. * MPDU by comparing the number of buffers
  317. * available and number of buffers needed to
  318. * reap this MPDU
  319. */
  320. if ((msdu_desc_info.msdu_len /
  321. (RX_DATA_BUFFER_SIZE -
  322. soc->rx_pkt_tlv_size) + 1) >
  323. num_entries_avail) {
  324. DP_STATS_INC(soc,
  325. rx.msdu_scatter_wait_break,
  326. 1);
  327. dp_rx_cookie_reset_invalid_bit(
  328. ring_desc);
  329. break;
  330. }
  331. is_prev_msdu_last = false;
  332. }
  333. }
  334. core_id = smp_processor_id();
  335. DP_STATS_INC(soc, rx.ring_packets[core_id][reo_ring_num], 1);
  336. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  337. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  338. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  339. HAL_MPDU_F_RAW_AMPDU))
  340. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  341. if (!is_prev_msdu_last &&
  342. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  343. is_prev_msdu_last = true;
  344. /* Pop out the descriptor*/
  345. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  346. rx_bufs_reaped[rx_desc->pool_id]++;
  347. peer_mdata = mpdu_desc_info.peer_meta_data;
  348. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  349. dp_rx_peer_metadata_peer_id_get_be(soc, peer_mdata);
  350. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  351. dp_rx_peer_metadata_vdev_id_get_be(soc, peer_mdata);
  352. /* to indicate whether this msdu is rx offload */
  353. pkt_capture_offload =
  354. DP_PEER_METADATA_OFFLOAD_GET_BE(peer_mdata);
  355. /*
  356. * save msdu flags first, last and continuation msdu in
  357. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  358. * length to nbuf->cb. This ensures the info required for
  359. * per pkt processing is always in the same cache line.
  360. * This helps in improving throughput for smaller pkt
  361. * sizes.
  362. */
  363. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  364. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  365. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  366. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  367. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  368. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  369. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  370. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  371. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  372. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  373. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  374. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  375. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_INTRA_BSS)
  376. qdf_nbuf_set_intra_bss(rx_desc->nbuf, 1);
  377. if (qdf_likely(mpdu_desc_info.mpdu_flags &
  378. HAL_MPDU_F_QOS_CONTROL_VALID))
  379. qdf_nbuf_set_tid_val(rx_desc->nbuf, mpdu_desc_info.tid);
  380. /* set sw exception */
  381. qdf_nbuf_set_rx_reo_dest_ind_or_sw_excpt(
  382. rx_desc->nbuf,
  383. hal_rx_sw_exception_get_be(ring_desc));
  384. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  385. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  386. /*
  387. * move unmap after scattered msdu waiting break logic
  388. * in case double skb unmap happened.
  389. */
  390. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  391. dp_rx_nbuf_unmap(soc, rx_desc, reo_ring_num);
  392. rx_desc->unmapped = 1;
  393. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  394. ebuf_tail, rx_desc);
  395. /*
  396. * if continuation bit is set then we have MSDU spread
  397. * across multiple buffers, let us not decrement quota
  398. * till we reap all buffers of that MSDU.
  399. */
  400. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf)))
  401. quota -= 1;
  402. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  403. &tail[rx_desc->pool_id], rx_desc);
  404. num_rx_bufs_reaped++;
  405. /*
  406. * only if complete msdu is received for scatter case,
  407. * then allow break.
  408. */
  409. if (is_prev_msdu_last &&
  410. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  411. max_reap_limit))
  412. break;
  413. }
  414. done:
  415. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  416. replenish_soc = dp_rx_replensih_soc_get(soc, reo_ring_num);
  417. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  418. /*
  419. * continue with next mac_id if no pkts were reaped
  420. * from that pool
  421. */
  422. if (!rx_bufs_reaped[mac_id])
  423. continue;
  424. dp_rxdma_srng = &replenish_soc->rx_refill_buf_ring[mac_id];
  425. rx_desc_pool = &replenish_soc->rx_desc_buf[mac_id];
  426. dp_rx_buffers_replenish(replenish_soc, mac_id, dp_rxdma_srng,
  427. rx_desc_pool, rx_bufs_reaped[mac_id],
  428. &head[mac_id], &tail[mac_id]);
  429. }
  430. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  431. /* Peer can be NULL is case of LFR */
  432. if (qdf_likely(txrx_peer))
  433. vdev = NULL;
  434. /*
  435. * BIG loop where each nbuf is dequeued from global queue,
  436. * processed and queued back on a per vdev basis. These nbufs
  437. * are sent to stack as and when we run out of nbufs
  438. * or a new nbuf dequeued from global queue has a different
  439. * vdev when compared to previous nbuf.
  440. */
  441. nbuf = nbuf_head;
  442. while (nbuf) {
  443. next = nbuf->next;
  444. dp_rx_prefetch_nbuf_data_be(nbuf, next);
  445. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  446. nbuf = next;
  447. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  448. continue;
  449. }
  450. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  451. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  452. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  453. if (dp_rx_is_list_ready(deliver_list_head, vdev, txrx_peer,
  454. peer_id, vdev_id)) {
  455. dp_rx_deliver_to_stack(soc, vdev, txrx_peer,
  456. deliver_list_head,
  457. deliver_list_tail);
  458. deliver_list_head = NULL;
  459. deliver_list_tail = NULL;
  460. }
  461. /* Get TID from struct cb->tid_val, save to tid */
  462. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  463. tid = qdf_nbuf_get_tid_val(nbuf);
  464. if (qdf_unlikely(!txrx_peer)) {
  465. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  466. &txrx_ref_handle,
  467. DP_MOD_ID_RX);
  468. } else if (txrx_peer && txrx_peer->peer_id != peer_id) {
  469. dp_txrx_peer_unref_delete(txrx_ref_handle,
  470. DP_MOD_ID_RX);
  471. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  472. &txrx_ref_handle,
  473. DP_MOD_ID_RX);
  474. }
  475. if (txrx_peer) {
  476. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  477. qdf_dp_trace_set_track(nbuf, QDF_RX);
  478. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  479. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  480. QDF_NBUF_RX_PKT_DATA_TRACK;
  481. }
  482. rx_bufs_used++;
  483. if (qdf_likely(txrx_peer)) {
  484. vdev = txrx_peer->vdev;
  485. } else {
  486. nbuf->next = NULL;
  487. dp_rx_deliver_to_pkt_capture_no_peer(
  488. soc, nbuf, pkt_capture_offload);
  489. if (!pkt_capture_offload)
  490. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  491. nbuf = next;
  492. continue;
  493. }
  494. if (qdf_unlikely(!vdev)) {
  495. dp_rx_nbuf_free(nbuf);
  496. nbuf = next;
  497. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  498. continue;
  499. }
  500. /* when hlos tid override is enabled, save tid in
  501. * skb->priority
  502. */
  503. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  504. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  505. qdf_nbuf_set_priority(nbuf, tid);
  506. rx_pdev = vdev->pdev;
  507. DP_RX_TID_SAVE(nbuf, tid);
  508. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  509. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  510. soc->wlan_cfg_ctx)) ||
  511. dp_rx_pkt_tracepoints_enabled())
  512. qdf_nbuf_set_timestamp(nbuf);
  513. enh_flag = rx_pdev->enhanced_stats_en;
  514. tid_stats =
  515. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  516. /*
  517. * Check if DMA completed -- msdu_done is the last bit
  518. * to be written
  519. */
  520. if (qdf_unlikely(!qdf_nbuf_is_rx_chfrag_cont(nbuf) &&
  521. !hal_rx_tlv_msdu_done_get_be(rx_tlv_hdr))) {
  522. dp_err("MSDU DONE failure");
  523. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  524. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  525. QDF_TRACE_LEVEL_INFO);
  526. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  527. dp_rx_nbuf_free(nbuf);
  528. qdf_assert(0);
  529. nbuf = next;
  530. continue;
  531. }
  532. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  533. /*
  534. * First IF condition:
  535. * 802.11 Fragmented pkts are reinjected to REO
  536. * HW block as SG pkts and for these pkts we only
  537. * need to pull the RX TLVS header length.
  538. * Second IF condition:
  539. * The below condition happens when an MSDU is spread
  540. * across multiple buffers. This can happen in two cases
  541. * 1. The nbuf size is smaller then the received msdu.
  542. * ex: we have set the nbuf size to 2048 during
  543. * nbuf_alloc. but we received an msdu which is
  544. * 2304 bytes in size then this msdu is spread
  545. * across 2 nbufs.
  546. *
  547. * 2. AMSDUs when RAW mode is enabled.
  548. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  549. * across 1st nbuf and 2nd nbuf and last MSDU is
  550. * spread across 2nd nbuf and 3rd nbuf.
  551. *
  552. * for these scenarios let us create a skb frag_list and
  553. * append these buffers till the last MSDU of the AMSDU
  554. * Third condition:
  555. * This is the most likely case, we receive 802.3 pkts
  556. * decapsulated by HW, here we need to set the pkt length.
  557. */
  558. hal_rx_msdu_packet_metadata_get_generic_be(rx_tlv_hdr,
  559. &msdu_metadata);
  560. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  561. bool is_mcbc, is_sa_vld, is_da_vld;
  562. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  563. rx_tlv_hdr);
  564. is_sa_vld =
  565. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  566. rx_tlv_hdr);
  567. is_da_vld =
  568. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  569. rx_tlv_hdr);
  570. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  571. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  572. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  573. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  574. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  575. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  576. nbuf = dp_rx_sg_create(soc, nbuf);
  577. next = nbuf->next;
  578. if (qdf_nbuf_is_raw_frame(nbuf)) {
  579. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  580. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  581. rx.raw, 1,
  582. msdu_len);
  583. } else {
  584. dp_rx_nbuf_free(nbuf);
  585. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  586. dp_info_rl("scatter msdu len %d, dropped",
  587. msdu_len);
  588. nbuf = next;
  589. continue;
  590. }
  591. } else {
  592. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  593. pkt_len = msdu_len +
  594. msdu_metadata.l3_hdr_pad +
  595. soc->rx_pkt_tlv_size;
  596. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  597. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  598. }
  599. /*
  600. * process frame for mulitpass phrase processing
  601. */
  602. if (qdf_unlikely(vdev->multipass_en)) {
  603. if (dp_rx_multipass_process(txrx_peer, nbuf,
  604. tid) == false) {
  605. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  606. rx.multipass_rx_pkt_drop,
  607. 1);
  608. dp_rx_nbuf_free(nbuf);
  609. nbuf = next;
  610. continue;
  611. }
  612. }
  613. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, txrx_peer)) {
  614. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  615. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  616. rx.policy_check_drop, 1);
  617. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  618. /* Drop & free packet */
  619. dp_rx_nbuf_free(nbuf);
  620. /* Statistics */
  621. nbuf = next;
  622. continue;
  623. }
  624. if (qdf_unlikely(txrx_peer && (txrx_peer->nawds_enabled) &&
  625. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  626. (hal_rx_get_mpdu_mac_ad4_valid_be(rx_tlv_hdr)
  627. == false))) {
  628. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  629. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  630. rx.nawds_mcast_drop, 1);
  631. dp_rx_nbuf_free(nbuf);
  632. nbuf = next;
  633. continue;
  634. }
  635. /*
  636. * Drop non-EAPOL frames from unauthorized peer.
  637. */
  638. if (qdf_likely(txrx_peer) &&
  639. qdf_unlikely(!txrx_peer->authorize) &&
  640. !qdf_nbuf_is_raw_frame(nbuf)) {
  641. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  642. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  643. if (!is_eapol) {
  644. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  645. rx.peer_unauth_rx_pkt_drop,
  646. 1);
  647. dp_rx_nbuf_free(nbuf);
  648. nbuf = next;
  649. continue;
  650. }
  651. }
  652. if (soc->process_rx_status)
  653. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  654. /* Update the protocol tag in SKB based on CCE metadata */
  655. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  656. reo_ring_num, false, true);
  657. /* Update the flow tag in SKB based on FSE metadata */
  658. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  659. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, txrx_peer,
  660. reo_ring_num, tid_stats);
  661. if (qdf_unlikely(vdev->mesh_vdev)) {
  662. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  663. == QDF_STATUS_SUCCESS) {
  664. dp_rx_info("%pK: mesh pkt filtered", soc);
  665. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  666. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  667. 1);
  668. dp_rx_nbuf_free(nbuf);
  669. nbuf = next;
  670. continue;
  671. }
  672. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr,
  673. txrx_peer);
  674. }
  675. if (qdf_likely(vdev->rx_decap_type ==
  676. htt_cmn_pkt_type_ethernet) &&
  677. qdf_likely(!vdev->mesh_vdev)) {
  678. dp_rx_wds_learn(soc, vdev,
  679. rx_tlv_hdr,
  680. txrx_peer,
  681. nbuf,
  682. msdu_metadata);
  683. /* Intrabss-fwd */
  684. if (dp_rx_check_ap_bridge(vdev))
  685. if (dp_rx_intrabss_fwd_be(soc, txrx_peer,
  686. rx_tlv_hdr,
  687. nbuf,
  688. msdu_metadata)) {
  689. nbuf = next;
  690. tid_stats->intrabss_cnt++;
  691. continue; /* Get next desc */
  692. }
  693. }
  694. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  695. dp_rx_mark_first_packet_after_wow_wakeup(vdev->pdev, rx_tlv_hdr,
  696. nbuf);
  697. dp_rx_update_stats(soc, nbuf);
  698. DP_RX_LIST_APPEND(deliver_list_head,
  699. deliver_list_tail,
  700. nbuf);
  701. DP_PEER_TO_STACK_INCC_PKT(txrx_peer, 1,
  702. QDF_NBUF_CB_RX_PKT_LEN(nbuf),
  703. enh_flag);
  704. if (qdf_unlikely(txrx_peer->in_twt))
  705. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  706. rx.to_stack_twt, 1,
  707. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  708. tid_stats->delivered_to_stack++;
  709. nbuf = next;
  710. }
  711. if (qdf_likely(deliver_list_head)) {
  712. if (qdf_likely(txrx_peer)) {
  713. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  714. pkt_capture_offload,
  715. deliver_list_head);
  716. if (!pkt_capture_offload)
  717. dp_rx_deliver_to_stack(soc, vdev, txrx_peer,
  718. deliver_list_head,
  719. deliver_list_tail);
  720. } else {
  721. nbuf = deliver_list_head;
  722. while (nbuf) {
  723. next = nbuf->next;
  724. nbuf->next = NULL;
  725. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  726. nbuf = next;
  727. }
  728. }
  729. }
  730. if (qdf_likely(txrx_peer))
  731. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  732. /*
  733. * If we are processing in near-full condition, there are 3 scenario
  734. * 1) Ring entries has reached critical state
  735. * 2) Ring entries are still near high threshold
  736. * 3) Ring entries are below the safe level
  737. *
  738. * One more loop will move the state to normal processing and yield
  739. */
  740. if (ring_near_full && quota)
  741. goto more_data;
  742. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  743. if (quota) {
  744. num_pending =
  745. dp_rx_srng_get_num_pending(hal_soc,
  746. hal_ring_hdl,
  747. num_entries,
  748. &near_full);
  749. if (num_pending) {
  750. DP_STATS_INC(soc, rx.hp_oos2, 1);
  751. if (!hif_exec_should_yield(scn, intr_id))
  752. goto more_data;
  753. if (qdf_unlikely(near_full)) {
  754. DP_STATS_INC(soc, rx.near_full, 1);
  755. goto more_data;
  756. }
  757. }
  758. }
  759. if (vdev && vdev->osif_fisa_flush)
  760. vdev->osif_fisa_flush(soc, reo_ring_num);
  761. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  762. vdev->osif_gro_flush(vdev->osif_vdev,
  763. reo_ring_num);
  764. }
  765. }
  766. /* Update histogram statistics by looping through pdev's */
  767. DP_RX_HIST_STATS_PER_PDEV();
  768. return rx_bufs_used; /* Assume no scale factor for now */
  769. }
  770. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  771. /**
  772. * dp_rx_desc_pool_init_be_cc() - initial RX desc pool for cookie conversion
  773. * @soc: Handle to DP Soc structure
  774. * @rx_desc_pool: Rx descriptor pool handler
  775. * @pool_id: Rx descriptor pool ID
  776. *
  777. * Return: QDF_STATUS_SUCCESS - succeeded, others - failed
  778. */
  779. static QDF_STATUS
  780. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  781. struct rx_desc_pool *rx_desc_pool,
  782. uint32_t pool_id)
  783. {
  784. struct dp_hw_cookie_conversion_t *cc_ctx;
  785. struct dp_soc_be *be_soc;
  786. union dp_rx_desc_list_elem_t *rx_desc_elem;
  787. struct dp_spt_page_desc *page_desc;
  788. uint32_t ppt_idx = 0;
  789. uint32_t avail_entry_index = 0;
  790. if (!rx_desc_pool->pool_size) {
  791. dp_err("desc_num 0 !!");
  792. return QDF_STATUS_E_FAILURE;
  793. }
  794. be_soc = dp_get_be_soc_from_dp_soc(soc);
  795. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  796. page_desc = &cc_ctx->page_desc_base[0];
  797. rx_desc_elem = rx_desc_pool->freelist;
  798. while (rx_desc_elem) {
  799. if (avail_entry_index == 0) {
  800. if (ppt_idx >= cc_ctx->total_page_num) {
  801. dp_alert("insufficient secondary page tables");
  802. qdf_assert_always(0);
  803. }
  804. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  805. }
  806. /* put each RX Desc VA to SPT pages and
  807. * get corresponding ID
  808. */
  809. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  810. avail_entry_index,
  811. &rx_desc_elem->rx_desc);
  812. rx_desc_elem->rx_desc.cookie =
  813. dp_cc_desc_id_generate(page_desc->ppt_index,
  814. avail_entry_index);
  815. rx_desc_elem->rx_desc.pool_id = pool_id;
  816. rx_desc_elem->rx_desc.in_use = 0;
  817. rx_desc_elem = rx_desc_elem->next;
  818. avail_entry_index = (avail_entry_index + 1) &
  819. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  820. }
  821. return QDF_STATUS_SUCCESS;
  822. }
  823. #else
  824. static QDF_STATUS
  825. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  826. struct rx_desc_pool *rx_desc_pool,
  827. uint32_t pool_id)
  828. {
  829. struct dp_hw_cookie_conversion_t *cc_ctx;
  830. struct dp_soc_be *be_soc;
  831. struct dp_spt_page_desc *page_desc;
  832. uint32_t ppt_idx = 0;
  833. uint32_t avail_entry_index = 0;
  834. int i = 0;
  835. if (!rx_desc_pool->pool_size) {
  836. dp_err("desc_num 0 !!");
  837. return QDF_STATUS_E_FAILURE;
  838. }
  839. be_soc = dp_get_be_soc_from_dp_soc(soc);
  840. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  841. page_desc = &cc_ctx->page_desc_base[0];
  842. for (i = 0; i <= rx_desc_pool->pool_size - 1; i++) {
  843. if (i == rx_desc_pool->pool_size - 1)
  844. rx_desc_pool->array[i].next = NULL;
  845. else
  846. rx_desc_pool->array[i].next =
  847. &rx_desc_pool->array[i + 1];
  848. if (avail_entry_index == 0) {
  849. if (ppt_idx >= cc_ctx->total_page_num) {
  850. dp_alert("insufficient secondary page tables");
  851. qdf_assert_always(0);
  852. }
  853. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  854. }
  855. /* put each RX Desc VA to SPT pages and
  856. * get corresponding ID
  857. */
  858. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  859. avail_entry_index,
  860. &rx_desc_pool->array[i].rx_desc);
  861. rx_desc_pool->array[i].rx_desc.cookie =
  862. dp_cc_desc_id_generate(page_desc->ppt_index,
  863. avail_entry_index);
  864. rx_desc_pool->array[i].rx_desc.pool_id = pool_id;
  865. rx_desc_pool->array[i].rx_desc.in_use = 0;
  866. avail_entry_index = (avail_entry_index + 1) &
  867. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  868. }
  869. return QDF_STATUS_SUCCESS;
  870. }
  871. #endif
  872. static void
  873. dp_rx_desc_pool_deinit_be_cc(struct dp_soc *soc,
  874. struct rx_desc_pool *rx_desc_pool,
  875. uint32_t pool_id)
  876. {
  877. struct dp_spt_page_desc *page_desc;
  878. struct dp_soc_be *be_soc;
  879. int i = 0;
  880. struct dp_hw_cookie_conversion_t *cc_ctx;
  881. be_soc = dp_get_be_soc_from_dp_soc(soc);
  882. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  883. for (i = 0; i < cc_ctx->total_page_num; i++) {
  884. page_desc = &cc_ctx->page_desc_base[i];
  885. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  886. }
  887. }
  888. QDF_STATUS dp_rx_desc_pool_init_be(struct dp_soc *soc,
  889. struct rx_desc_pool *rx_desc_pool,
  890. uint32_t pool_id)
  891. {
  892. QDF_STATUS status = QDF_STATUS_SUCCESS;
  893. /* Only regular RX buffer desc pool use HW cookie conversion */
  894. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE) {
  895. dp_info("rx_desc_buf pool init");
  896. status = dp_rx_desc_pool_init_be_cc(soc,
  897. rx_desc_pool,
  898. pool_id);
  899. } else {
  900. dp_info("non_rx_desc_buf_pool init");
  901. status = dp_rx_desc_pool_init_generic(soc, rx_desc_pool,
  902. pool_id);
  903. }
  904. return status;
  905. }
  906. void dp_rx_desc_pool_deinit_be(struct dp_soc *soc,
  907. struct rx_desc_pool *rx_desc_pool,
  908. uint32_t pool_id)
  909. {
  910. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE)
  911. dp_rx_desc_pool_deinit_be_cc(soc, rx_desc_pool, pool_id);
  912. }
  913. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  914. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  915. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  916. void *ring_desc,
  917. struct dp_rx_desc **r_rx_desc)
  918. {
  919. if (hal_rx_wbm_get_cookie_convert_done(ring_desc)) {
  920. /* HW cookie conversion done */
  921. *r_rx_desc = (struct dp_rx_desc *)
  922. hal_rx_wbm_get_desc_va(ring_desc);
  923. } else {
  924. /* SW do cookie conversion */
  925. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  926. *r_rx_desc = (struct dp_rx_desc *)
  927. dp_cc_desc_find(soc, cookie);
  928. }
  929. return QDF_STATUS_SUCCESS;
  930. }
  931. #else
  932. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  933. void *ring_desc,
  934. struct dp_rx_desc **r_rx_desc)
  935. {
  936. *r_rx_desc = (struct dp_rx_desc *)
  937. hal_rx_wbm_get_desc_va(ring_desc);
  938. return QDF_STATUS_SUCCESS;
  939. }
  940. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  941. #else
  942. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  943. void *ring_desc,
  944. struct dp_rx_desc **r_rx_desc)
  945. {
  946. /* SW do cookie conversion */
  947. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  948. *r_rx_desc = (struct dp_rx_desc *)
  949. dp_cc_desc_find(soc, cookie);
  950. return QDF_STATUS_SUCCESS;
  951. }
  952. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  953. struct dp_rx_desc *dp_rx_desc_cookie_2_va_be(struct dp_soc *soc,
  954. uint32_t cookie)
  955. {
  956. return (struct dp_rx_desc *)dp_cc_desc_find(soc, cookie);
  957. }
  958. #if defined(WLAN_FEATURE_11BE_MLO)
  959. #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO)
  960. static inline void dp_rx_dummy_src_mac(qdf_nbuf_t nbuf)
  961. {
  962. qdf_ether_header_t *eh =
  963. (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  964. eh->ether_shost[0] = 0x4d; /* M */
  965. eh->ether_shost[1] = 0x4c; /* L */
  966. eh->ether_shost[2] = 0x4d; /* M */
  967. eh->ether_shost[3] = 0x43; /* C */
  968. eh->ether_shost[4] = 0x41; /* A */
  969. eh->ether_shost[5] = 0x53; /* S */
  970. }
  971. bool dp_rx_mlo_igmp_handler(struct dp_soc *soc,
  972. struct dp_vdev *vdev,
  973. struct dp_txrx_peer *peer,
  974. qdf_nbuf_t nbuf)
  975. {
  976. struct dp_vdev *mcast_primary_vdev = NULL;
  977. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  978. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  979. if (!(qdf_nbuf_is_ipv4_igmp_pkt(buf) ||
  980. qdf_nbuf_is_ipv6_igmp_pkt(buf)))
  981. return false;
  982. if (vdev->mcast_enhancement_en || be_vdev->mcast_primary)
  983. goto send_pkt;
  984. mcast_primary_vdev = dp_mlo_get_mcast_primary_vdev(be_soc, be_vdev,
  985. DP_MOD_ID_RX);
  986. if (!mcast_primary_vdev) {
  987. dp_rx_debug("Non mlo vdev");
  988. goto send_pkt;
  989. }
  990. dp_rx_dummy_src_mac(nbuf);
  991. dp_rx_deliver_to_stack(mcast_primary_vdev->pdev->soc,
  992. mcast_primary_vdev,
  993. peer,
  994. nbuf,
  995. NULL);
  996. dp_vdev_unref_delete(mcast_primary_vdev->pdev->soc,
  997. mcast_primary_vdev,
  998. DP_MOD_ID_RX);
  999. return true;
  1000. send_pkt:
  1001. dp_rx_deliver_to_stack(be_vdev->vdev.pdev->soc,
  1002. &be_vdev->vdev,
  1003. peer,
  1004. nbuf,
  1005. NULL);
  1006. return true;
  1007. }
  1008. #else
  1009. bool dp_rx_mlo_igmp_handler(struct dp_soc *soc,
  1010. struct dp_vdev *vdev,
  1011. struct dp_peer *peer,
  1012. qdf_nbuf_t nbuf)
  1013. {
  1014. return false;
  1015. }
  1016. #endif
  1017. #endif
  1018. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1019. uint32_t dp_rx_nf_process(struct dp_intr *int_ctx,
  1020. hal_ring_handle_t hal_ring_hdl,
  1021. uint8_t reo_ring_num,
  1022. uint32_t quota)
  1023. {
  1024. struct dp_soc *soc = int_ctx->soc;
  1025. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  1026. uint32_t work_done = 0;
  1027. if (dp_srng_get_near_full_level(soc, rx_ring) <
  1028. DP_SRNG_THRESH_NEAR_FULL)
  1029. return 0;
  1030. qdf_atomic_set(&rx_ring->near_full, 1);
  1031. work_done++;
  1032. return work_done;
  1033. }
  1034. #endif
  1035. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1036. #ifdef WLAN_FEATURE_11BE_MLO
  1037. /**
  1038. * dp_rx_intrabss_fwd_mlo_allow() - check if MLO forwarding is allowed
  1039. * @ta_peer: transmitter peer handle
  1040. * @da_peer: destination peer handle
  1041. *
  1042. * Return: true - MLO forwarding case, false: not
  1043. */
  1044. static inline bool
  1045. dp_rx_intrabss_fwd_mlo_allow(struct dp_txrx_peer *ta_peer,
  1046. struct dp_txrx_peer *da_peer)
  1047. {
  1048. /* one of TA/DA peer should belong to MLO connection peer,
  1049. * only MLD peer type is as expected
  1050. */
  1051. if (!IS_MLO_DP_MLD_TXRX_PEER(ta_peer) &&
  1052. !IS_MLO_DP_MLD_TXRX_PEER(da_peer))
  1053. return false;
  1054. /* TA peer and DA peer's vdev should be partner MLO vdevs */
  1055. if (dp_peer_find_mac_addr_cmp(&ta_peer->vdev->mld_mac_addr,
  1056. &da_peer->vdev->mld_mac_addr))
  1057. return false;
  1058. return true;
  1059. }
  1060. #else
  1061. static inline bool
  1062. dp_rx_intrabss_fwd_mlo_allow(struct dp_txrx_peer *ta_peer,
  1063. struct dp_txrx_peer *da_peer)
  1064. {
  1065. return false;
  1066. }
  1067. #endif
  1068. #ifdef INTRA_BSS_FWD_OFFLOAD
  1069. /**
  1070. * dp_rx_intrabss_ucast_check_be() - Check if intrabss is allowed
  1071. for unicast frame
  1072. * @soc: SOC hanlde
  1073. * @nbuf: RX packet buffer
  1074. * @ta_peer: transmitter DP peer handle
  1075. * @msdu_metadata: MSDU meta data info
  1076. * @p_tx_vdev_id: get vdev id for Intra-BSS TX
  1077. *
  1078. * Return: true - intrabss allowed
  1079. false - not allow
  1080. */
  1081. static bool
  1082. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1083. struct dp_txrx_peer *ta_peer,
  1084. struct hal_rx_msdu_metadata *msdu_metadata,
  1085. struct dp_be_intrabss_params *params)
  1086. {
  1087. uint16_t da_peer_id;
  1088. struct dp_txrx_peer *da_peer;
  1089. dp_txrx_ref_handle txrx_ref_handle = NULL;
  1090. if (!qdf_nbuf_is_intra_bss(nbuf))
  1091. return false;
  1092. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1093. params->dest_soc,
  1094. msdu_metadata->da_idx);
  1095. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1096. &txrx_ref_handle, DP_MOD_ID_RX);
  1097. if (!da_peer)
  1098. return false;
  1099. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1100. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1101. return true;
  1102. }
  1103. #else
  1104. #ifdef WLAN_MLO_MULTI_CHIP
  1105. static bool
  1106. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1107. struct dp_txrx_peer *ta_peer,
  1108. struct hal_rx_msdu_metadata *msdu_metadata,
  1109. struct dp_be_intrabss_params *params)
  1110. {
  1111. uint16_t da_peer_id;
  1112. struct dp_txrx_peer *da_peer;
  1113. bool ret = false;
  1114. uint8_t dest_chip_id;
  1115. uint8_t soc_idx;
  1116. dp_txrx_ref_handle txrx_ref_handle = NULL;
  1117. struct dp_vdev_be *be_vdev =
  1118. dp_get_be_vdev_from_dp_vdev(ta_peer->vdev);
  1119. struct dp_soc_be *be_soc =
  1120. dp_get_be_soc_from_dp_soc(params->dest_soc);
  1121. if (!(qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf)))
  1122. return false;
  1123. dest_chip_id = HAL_RX_DEST_CHIP_ID_GET(msdu_metadata);
  1124. qdf_assert_always(dest_chip_id <= (DP_MLO_MAX_DEST_CHIP_ID - 1));
  1125. if (be_soc->mlo_enabled) {
  1126. /* validate chip_id, get a ref, and re-assign soc */
  1127. params->dest_soc =
  1128. dp_mlo_get_soc_ref_by_chip_id(be_soc->ml_ctxt,
  1129. dest_chip_id);
  1130. if (!params->dest_soc)
  1131. return false;
  1132. }
  1133. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(params->dest_soc,
  1134. msdu_metadata->da_idx);
  1135. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1136. &txrx_ref_handle, DP_MOD_ID_RX);
  1137. if (!da_peer)
  1138. return false;
  1139. /* soc unref if needed */
  1140. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1141. /* If the source or destination peer in the isolation
  1142. * list then dont forward instead push to bridge stack.
  1143. */
  1144. if (dp_get_peer_isolation(ta_peer) ||
  1145. dp_get_peer_isolation(da_peer))
  1146. goto rel_da_peer;
  1147. if (da_peer->bss_peer || da_peer == ta_peer)
  1148. goto rel_da_peer;
  1149. /* Same vdev, support Inra-BSS */
  1150. if (da_peer->vdev == ta_peer->vdev) {
  1151. ret = true;
  1152. goto rel_da_peer;
  1153. }
  1154. /* MLO specific Intra-BSS check */
  1155. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1156. /* index of soc in the array */
  1157. soc_idx = dest_chip_id << DP_MLO_DEST_CHIP_ID_SHIFT;
  1158. if (!(be_vdev->partner_vdev_list[soc_idx][0] ==
  1159. params->tx_vdev_id) &&
  1160. !(be_vdev->partner_vdev_list[soc_idx][1] ==
  1161. params->tx_vdev_id)) {
  1162. /*dp_soc_unref_delete(soc);*/
  1163. goto rel_da_peer;
  1164. }
  1165. ret = true;
  1166. }
  1167. rel_da_peer:
  1168. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1169. return ret;
  1170. }
  1171. #else
  1172. static bool
  1173. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1174. struct dp_txrx_peer *ta_peer,
  1175. struct hal_rx_msdu_metadata *msdu_metadata,
  1176. struct dp_be_intrabss_params *params)
  1177. {
  1178. uint16_t da_peer_id;
  1179. struct dp_txrx_peer *da_peer;
  1180. bool ret = false;
  1181. dp_txrx_ref_handle txrx_ref_handle = NULL;
  1182. if (!qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf))
  1183. return false;
  1184. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1185. params->dest_soc,
  1186. msdu_metadata->da_idx);
  1187. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1188. &txrx_ref_handle, DP_MOD_ID_RX);
  1189. if (!da_peer)
  1190. return false;
  1191. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1192. /* If the source or destination peer in the isolation
  1193. * list then dont forward instead push to bridge stack.
  1194. */
  1195. if (dp_get_peer_isolation(ta_peer) ||
  1196. dp_get_peer_isolation(da_peer))
  1197. goto rel_da_peer;
  1198. if (da_peer->bss_peer || da_peer == ta_peer)
  1199. goto rel_da_peer;
  1200. /* Same vdev, support Inra-BSS */
  1201. if (da_peer->vdev == ta_peer->vdev) {
  1202. ret = true;
  1203. goto rel_da_peer;
  1204. }
  1205. /* MLO specific Intra-BSS check */
  1206. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1207. ret = true;
  1208. goto rel_da_peer;
  1209. }
  1210. rel_da_peer:
  1211. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1212. return ret;
  1213. }
  1214. #endif /* WLAN_MLO_MULTI_CHIP */
  1215. #endif /* INTRA_BSS_FWD_OFFLOAD */
  1216. /*
  1217. * dp_rx_intrabss_handle_nawds_be() - Forward mcbc intrabss pkts in nawds case
  1218. * @soc: core txrx main context
  1219. * @ta_txrx_peer: source txrx_peer entry
  1220. * @nbuf_copy: nbuf that has to be intrabss forwarded
  1221. * @tid_stats: tid_stats structure
  1222. *
  1223. * Return: true if it is forwarded else false
  1224. */
  1225. bool
  1226. dp_rx_intrabss_handle_nawds_be(struct dp_soc *soc,
  1227. struct dp_txrx_peer *ta_txrx_peer,
  1228. qdf_nbuf_t nbuf_copy,
  1229. struct cdp_tid_rx_stats *tid_stats)
  1230. {
  1231. if (qdf_unlikely(ta_txrx_peer->vdev->nawds_enabled)) {
  1232. struct cdp_tx_exception_metadata tx_exc_metadata = {0};
  1233. uint16_t len = QDF_NBUF_CB_RX_PKT_LEN(nbuf_copy);
  1234. tx_exc_metadata.peer_id = ta_txrx_peer->peer_id;
  1235. tx_exc_metadata.is_intrabss_fwd = 1;
  1236. tx_exc_metadata.tid = HTT_TX_EXT_TID_INVALID;
  1237. if (dp_tx_send_exception((struct cdp_soc_t *)soc,
  1238. ta_txrx_peer->vdev->vdev_id,
  1239. nbuf_copy,
  1240. &tx_exc_metadata)) {
  1241. DP_PEER_PER_PKT_STATS_INC_PKT(ta_txrx_peer,
  1242. rx.intra_bss.fail, 1,
  1243. len);
  1244. tid_stats->fail_cnt[INTRABSS_DROP]++;
  1245. qdf_nbuf_free(nbuf_copy);
  1246. } else {
  1247. DP_PEER_PER_PKT_STATS_INC_PKT(ta_txrx_peer,
  1248. rx.intra_bss.pkts, 1,
  1249. len);
  1250. tid_stats->intrabss_cnt++;
  1251. }
  1252. return true;
  1253. }
  1254. return false;
  1255. }
  1256. /*
  1257. * dp_rx_intrabss_fwd_be() - API for intrabss fwd. For EAPOL
  1258. * pkt with DA not equal to vdev mac addr, fwd is not allowed.
  1259. * @soc: core txrx main context
  1260. * @ta_peer: source peer entry
  1261. * @rx_tlv_hdr: start address of rx tlvs
  1262. * @nbuf: nbuf that has to be intrabss forwarded
  1263. * @msdu_metadata: msdu metadata
  1264. *
  1265. * Return: true if it is forwarded else false
  1266. */
  1267. bool dp_rx_intrabss_fwd_be(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
  1268. uint8_t *rx_tlv_hdr, qdf_nbuf_t nbuf,
  1269. struct hal_rx_msdu_metadata msdu_metadata)
  1270. {
  1271. uint8_t tid = qdf_nbuf_get_tid_val(nbuf);
  1272. uint8_t ring_id = QDF_NBUF_CB_RX_CTX_ID(nbuf);
  1273. struct cdp_tid_rx_stats *tid_stats = &ta_peer->vdev->pdev->stats.
  1274. tid_stats.tid_rx_stats[ring_id][tid];
  1275. bool ret = false;
  1276. struct dp_be_intrabss_params params;
  1277. /* if it is a broadcast pkt (eg: ARP) and it is not its own
  1278. * source, then clone the pkt and send the cloned pkt for
  1279. * intra BSS forwarding and original pkt up the network stack
  1280. * Note: how do we handle multicast pkts. do we forward
  1281. * all multicast pkts as is or let a higher layer module
  1282. * like igmpsnoop decide whether to forward or not with
  1283. * Mcast enhancement.
  1284. */
  1285. if (qdf_nbuf_is_da_mcbc(nbuf) && !ta_peer->bss_peer) {
  1286. return dp_rx_intrabss_mcbc_fwd(soc, ta_peer, rx_tlv_hdr,
  1287. nbuf, tid_stats);
  1288. }
  1289. if (dp_rx_intrabss_eapol_drop_check(soc, ta_peer, rx_tlv_hdr,
  1290. nbuf))
  1291. return true;
  1292. params.dest_soc = soc;
  1293. if (dp_rx_intrabss_ucast_check_be(nbuf, ta_peer,
  1294. &msdu_metadata, &params)) {
  1295. ret = dp_rx_intrabss_ucast_fwd(params.dest_soc, ta_peer,
  1296. params.tx_vdev_id,
  1297. rx_tlv_hdr, nbuf, tid_stats);
  1298. }
  1299. return ret;
  1300. }
  1301. #endif