sde_hw_top.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include "sde_hwio.h"
  6. #include "sde_hw_catalog.h"
  7. #include "sde_hw_top.h"
  8. #include "sde_dbg.h"
  9. #include "sde_kms.h"
  10. #define SSPP_SPARE 0x28
  11. #define UBWC_DEC_HW_VERSION 0x058
  12. #define UBWC_STATIC 0x144
  13. #define UBWC_CTRL_2 0x150
  14. #define UBWC_PREDICTION_MODE 0x154
  15. #define FLD_SPLIT_DISPLAY_CMD BIT(1)
  16. #define FLD_SMART_PANEL_FREE_RUN BIT(2)
  17. #define FLD_INTF_1_SW_TRG_MUX BIT(4)
  18. #define FLD_INTF_2_SW_TRG_MUX BIT(8)
  19. #define FLD_TE_LINE_INTER_WATERLEVEL_MASK 0xFFFF
  20. #define DANGER_STATUS 0x360
  21. #define SAFE_STATUS 0x364
  22. #define TE_LINE_INTERVAL 0x3F4
  23. #define TRAFFIC_SHAPER_EN BIT(31)
  24. #define TRAFFIC_SHAPER_RD_CLIENT(num) (0x030 + (num * 4))
  25. #define TRAFFIC_SHAPER_WR_CLIENT(num) (0x060 + (num * 4))
  26. #define TRAFFIC_SHAPER_FIXPOINT_FACTOR 4
  27. #define MDP_WD_TIMER_0_CTL 0x380
  28. #define MDP_WD_TIMER_0_CTL2 0x384
  29. #define MDP_WD_TIMER_0_LOAD_VALUE 0x388
  30. #define MDP_WD_TIMER_1_CTL 0x390
  31. #define MDP_WD_TIMER_1_CTL2 0x394
  32. #define MDP_WD_TIMER_1_LOAD_VALUE 0x398
  33. #define MDP_WD_TIMER_2_CTL 0x420
  34. #define MDP_WD_TIMER_2_CTL2 0x424
  35. #define MDP_WD_TIMER_2_LOAD_VALUE 0x428
  36. #define MDP_WD_TIMER_3_CTL 0x430
  37. #define MDP_WD_TIMER_3_CTL2 0x434
  38. #define MDP_WD_TIMER_3_LOAD_VALUE 0x438
  39. #define MDP_WD_TIMER_4_CTL 0x440
  40. #define MDP_WD_TIMER_4_CTL2 0x444
  41. #define MDP_WD_TIMER_4_LOAD_VALUE 0x448
  42. #define MDP_TICK_COUNT 16
  43. #define XO_CLK_RATE 19200
  44. #define MS_TICKS_IN_SEC 1000
  45. #define CALCULATE_WD_LOAD_VALUE(fps) \
  46. ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))
  47. #define DCE_SEL 0x450
  48. #define ROT_SID_RD 0x20
  49. #define ROT_SID_WR 0x24
  50. #define ROT_SID_ID_VAL 0x1c
  51. static void sde_hw_setup_split_pipe(struct sde_hw_mdp *mdp,
  52. struct split_pipe_cfg *cfg)
  53. {
  54. struct sde_hw_blk_reg_map *c;
  55. u32 upper_pipe = 0;
  56. u32 lower_pipe = 0;
  57. if (!mdp || !cfg)
  58. return;
  59. c = &mdp->hw;
  60. if (cfg->en) {
  61. if (cfg->mode == INTF_MODE_CMD) {
  62. lower_pipe = FLD_SPLIT_DISPLAY_CMD;
  63. /* interface controlling sw trigger */
  64. if (cfg->intf == INTF_2)
  65. lower_pipe |= FLD_INTF_1_SW_TRG_MUX;
  66. else
  67. lower_pipe |= FLD_INTF_2_SW_TRG_MUX;
  68. /* free run */
  69. if (cfg->pp_split_slave != INTF_MAX)
  70. lower_pipe = FLD_SMART_PANEL_FREE_RUN;
  71. upper_pipe = lower_pipe;
  72. /* smart panel align mode */
  73. lower_pipe |= BIT(mdp->caps->smart_panel_align_mode);
  74. } else {
  75. if (cfg->intf == INTF_2) {
  76. lower_pipe = FLD_INTF_1_SW_TRG_MUX;
  77. upper_pipe = FLD_INTF_2_SW_TRG_MUX;
  78. } else {
  79. lower_pipe = FLD_INTF_2_SW_TRG_MUX;
  80. upper_pipe = FLD_INTF_1_SW_TRG_MUX;
  81. }
  82. }
  83. }
  84. SDE_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0);
  85. SDE_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe);
  86. SDE_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe);
  87. SDE_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
  88. }
  89. static u32 sde_hw_get_split_flush(struct sde_hw_mdp *mdp)
  90. {
  91. struct sde_hw_blk_reg_map *c;
  92. if (!mdp)
  93. return 0;
  94. c = &mdp->hw;
  95. return (SDE_REG_READ(c, SSPP_SPARE) & 0x1);
  96. }
  97. static void sde_hw_setup_pp_split(struct sde_hw_mdp *mdp,
  98. struct split_pipe_cfg *cfg)
  99. {
  100. u32 ppb_config = 0x0;
  101. u32 ppb_control = 0x0;
  102. if (!mdp || !cfg)
  103. return;
  104. if (cfg->en && cfg->pp_split_slave != INTF_MAX) {
  105. ppb_config |= (cfg->pp_split_slave - INTF_0 + 1) << 20;
  106. ppb_config |= BIT(16); /* split enable */
  107. ppb_control = BIT(5); /* horz split*/
  108. }
  109. if (cfg->pp_split_index) {
  110. SDE_REG_WRITE(&mdp->hw, PPB0_CONFIG, 0x0);
  111. SDE_REG_WRITE(&mdp->hw, PPB0_CNTL, 0x0);
  112. SDE_REG_WRITE(&mdp->hw, PPB1_CONFIG, ppb_config);
  113. SDE_REG_WRITE(&mdp->hw, PPB1_CNTL, ppb_control);
  114. } else {
  115. SDE_REG_WRITE(&mdp->hw, PPB0_CONFIG, ppb_config);
  116. SDE_REG_WRITE(&mdp->hw, PPB0_CNTL, ppb_control);
  117. SDE_REG_WRITE(&mdp->hw, PPB1_CONFIG, 0x0);
  118. SDE_REG_WRITE(&mdp->hw, PPB1_CNTL, 0x0);
  119. }
  120. }
  121. static void sde_hw_setup_cdm_output(struct sde_hw_mdp *mdp,
  122. struct cdm_output_cfg *cfg)
  123. {
  124. struct sde_hw_blk_reg_map *c;
  125. u32 out_ctl = 0;
  126. if (!mdp || !cfg)
  127. return;
  128. c = &mdp->hw;
  129. if (cfg->wb_en)
  130. out_ctl |= BIT(24);
  131. else if (cfg->intf_en)
  132. out_ctl |= BIT(19);
  133. SDE_REG_WRITE(c, MDP_OUT_CTL_0, out_ctl);
  134. }
  135. static bool sde_hw_setup_clk_force_ctrl(struct sde_hw_mdp *mdp,
  136. enum sde_clk_ctrl_type clk_ctrl, bool enable)
  137. {
  138. struct sde_hw_blk_reg_map *c;
  139. u32 reg_off, bit_off;
  140. u32 reg_val, new_val;
  141. bool clk_forced_on;
  142. if (!mdp)
  143. return false;
  144. c = &mdp->hw;
  145. if (clk_ctrl <= SDE_CLK_CTRL_NONE || clk_ctrl >= SDE_CLK_CTRL_MAX)
  146. return false;
  147. reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off;
  148. bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off;
  149. reg_val = SDE_REG_READ(c, reg_off);
  150. if (enable)
  151. new_val = reg_val | BIT(bit_off);
  152. else
  153. new_val = reg_val & ~BIT(bit_off);
  154. SDE_REG_WRITE(c, reg_off, new_val);
  155. wmb(); /* ensure write finished before progressing */
  156. clk_forced_on = !(reg_val & BIT(bit_off));
  157. return clk_forced_on;
  158. }
  159. static void sde_hw_get_danger_status(struct sde_hw_mdp *mdp,
  160. struct sde_danger_safe_status *status)
  161. {
  162. struct sde_hw_blk_reg_map *c;
  163. u32 value;
  164. if (!mdp || !status)
  165. return;
  166. c = &mdp->hw;
  167. value = SDE_REG_READ(c, DANGER_STATUS);
  168. status->mdp = (value >> 0) & 0x3;
  169. status->sspp[SSPP_VIG0] = (value >> 4) & 0x3;
  170. status->sspp[SSPP_VIG1] = (value >> 6) & 0x3;
  171. status->sspp[SSPP_VIG2] = (value >> 8) & 0x3;
  172. status->sspp[SSPP_VIG3] = (value >> 10) & 0x3;
  173. status->sspp[SSPP_RGB0] = (value >> 12) & 0x3;
  174. status->sspp[SSPP_RGB1] = (value >> 14) & 0x3;
  175. status->sspp[SSPP_RGB2] = (value >> 16) & 0x3;
  176. status->sspp[SSPP_RGB3] = (value >> 18) & 0x3;
  177. status->sspp[SSPP_DMA0] = (value >> 20) & 0x3;
  178. status->sspp[SSPP_DMA1] = (value >> 22) & 0x3;
  179. status->sspp[SSPP_DMA2] = (value >> 28) & 0x3;
  180. status->sspp[SSPP_DMA3] = (value >> 30) & 0x3;
  181. status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x3;
  182. status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3;
  183. status->wb[WB_0] = 0;
  184. status->wb[WB_1] = 0;
  185. status->wb[WB_2] = (value >> 2) & 0x3;
  186. status->wb[WB_3] = 0;
  187. }
  188. static void _update_vsync_source(struct sde_hw_mdp *mdp,
  189. struct sde_vsync_source_cfg *cfg)
  190. {
  191. struct sde_hw_blk_reg_map *c;
  192. u32 reg, wd_load_value, wd_ctl, wd_ctl2;
  193. if (!mdp || !cfg)
  194. return;
  195. c = &mdp->hw;
  196. if (cfg->vsync_source >= SDE_VSYNC_SOURCE_WD_TIMER_4 &&
  197. cfg->vsync_source <= SDE_VSYNC_SOURCE_WD_TIMER_0) {
  198. switch (cfg->vsync_source) {
  199. case SDE_VSYNC_SOURCE_WD_TIMER_4:
  200. wd_load_value = MDP_WD_TIMER_4_LOAD_VALUE;
  201. wd_ctl = MDP_WD_TIMER_4_CTL;
  202. wd_ctl2 = MDP_WD_TIMER_4_CTL2;
  203. break;
  204. case SDE_VSYNC_SOURCE_WD_TIMER_3:
  205. wd_load_value = MDP_WD_TIMER_3_LOAD_VALUE;
  206. wd_ctl = MDP_WD_TIMER_3_CTL;
  207. wd_ctl2 = MDP_WD_TIMER_3_CTL2;
  208. break;
  209. case SDE_VSYNC_SOURCE_WD_TIMER_2:
  210. wd_load_value = MDP_WD_TIMER_2_LOAD_VALUE;
  211. wd_ctl = MDP_WD_TIMER_2_CTL;
  212. wd_ctl2 = MDP_WD_TIMER_2_CTL2;
  213. break;
  214. case SDE_VSYNC_SOURCE_WD_TIMER_1:
  215. wd_load_value = MDP_WD_TIMER_1_LOAD_VALUE;
  216. wd_ctl = MDP_WD_TIMER_1_CTL;
  217. wd_ctl2 = MDP_WD_TIMER_1_CTL2;
  218. break;
  219. case SDE_VSYNC_SOURCE_WD_TIMER_0:
  220. default:
  221. wd_load_value = MDP_WD_TIMER_0_LOAD_VALUE;
  222. wd_ctl = MDP_WD_TIMER_0_CTL;
  223. wd_ctl2 = MDP_WD_TIMER_0_CTL2;
  224. break;
  225. }
  226. if (cfg->is_dummy) {
  227. SDE_REG_WRITE(c, wd_ctl2, 0x0);
  228. } else {
  229. SDE_REG_WRITE(c, wd_load_value,
  230. CALCULATE_WD_LOAD_VALUE(cfg->frame_rate));
  231. SDE_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */
  232. reg = SDE_REG_READ(c, wd_ctl2);
  233. reg |= BIT(8); /* enable heartbeat timer */
  234. reg |= BIT(0); /* enable WD timer */
  235. SDE_REG_WRITE(c, wd_ctl2, reg);
  236. }
  237. /* make sure that timers are enabled/disabled for vsync state */
  238. wmb();
  239. }
  240. }
  241. static void sde_hw_setup_vsync_source(struct sde_hw_mdp *mdp,
  242. struct sde_vsync_source_cfg *cfg)
  243. {
  244. struct sde_hw_blk_reg_map *c;
  245. u32 reg, i;
  246. static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18};
  247. if (!mdp || !cfg || (cfg->pp_count > ARRAY_SIZE(cfg->ppnumber)))
  248. return;
  249. c = &mdp->hw;
  250. reg = SDE_REG_READ(c, MDP_VSYNC_SEL);
  251. for (i = 0; i < cfg->pp_count; i++) {
  252. int pp_idx = cfg->ppnumber[i] - PINGPONG_0;
  253. if (pp_idx >= ARRAY_SIZE(pp_offset))
  254. continue;
  255. reg &= ~(0xf << pp_offset[pp_idx]);
  256. reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx];
  257. }
  258. SDE_REG_WRITE(c, MDP_VSYNC_SEL, reg);
  259. _update_vsync_source(mdp, cfg);
  260. }
  261. static void sde_hw_setup_vsync_source_v1(struct sde_hw_mdp *mdp,
  262. struct sde_vsync_source_cfg *cfg)
  263. {
  264. _update_vsync_source(mdp, cfg);
  265. }
  266. static void sde_hw_get_safe_status(struct sde_hw_mdp *mdp,
  267. struct sde_danger_safe_status *status)
  268. {
  269. struct sde_hw_blk_reg_map *c;
  270. u32 value;
  271. if (!mdp || !status)
  272. return;
  273. c = &mdp->hw;
  274. value = SDE_REG_READ(c, SAFE_STATUS);
  275. status->mdp = (value >> 0) & 0x1;
  276. status->sspp[SSPP_VIG0] = (value >> 4) & 0x1;
  277. status->sspp[SSPP_VIG1] = (value >> 6) & 0x1;
  278. status->sspp[SSPP_VIG2] = (value >> 8) & 0x1;
  279. status->sspp[SSPP_VIG3] = (value >> 10) & 0x1;
  280. status->sspp[SSPP_RGB0] = (value >> 12) & 0x1;
  281. status->sspp[SSPP_RGB1] = (value >> 14) & 0x1;
  282. status->sspp[SSPP_RGB2] = (value >> 16) & 0x1;
  283. status->sspp[SSPP_RGB3] = (value >> 18) & 0x1;
  284. status->sspp[SSPP_DMA0] = (value >> 20) & 0x1;
  285. status->sspp[SSPP_DMA1] = (value >> 22) & 0x1;
  286. status->sspp[SSPP_DMA2] = (value >> 28) & 0x1;
  287. status->sspp[SSPP_DMA3] = (value >> 30) & 0x1;
  288. status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x1;
  289. status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
  290. status->wb[WB_0] = 0;
  291. status->wb[WB_1] = 0;
  292. status->wb[WB_2] = (value >> 2) & 0x1;
  293. status->wb[WB_3] = 0;
  294. }
  295. static void sde_hw_setup_dce(struct sde_hw_mdp *mdp, u32 dce_sel)
  296. {
  297. struct sde_hw_blk_reg_map *c;
  298. if (!mdp)
  299. return;
  300. c = &mdp->hw;
  301. SDE_REG_WRITE(c, DCE_SEL, dce_sel);
  302. }
  303. void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m)
  304. {
  305. struct sde_hw_blk_reg_map c;
  306. u32 ubwc_version;
  307. if (!mdp || !m)
  308. return;
  309. /* force blk offset to zero to access beginning of register region */
  310. c = mdp->hw;
  311. c.blk_off = 0x0;
  312. ubwc_version = SDE_REG_READ(&c, UBWC_DEC_HW_VERSION);
  313. if (IS_UBWC_40_SUPPORTED(ubwc_version)) {
  314. u32 ver = 2;
  315. u32 mode = 1;
  316. u32 reg = (m->mdp[0].ubwc_swizzle & 0x7) |
  317. ((m->mdp[0].ubwc_static & 0x1) << 3) |
  318. ((m->mdp[0].highest_bank_bit & 0x7) << 4) |
  319. ((m->macrotile_mode & 0x1) << 12);
  320. if (IS_UBWC_30_SUPPORTED(m->ubwc_version)) {
  321. ver = 1;
  322. mode = 0;
  323. }
  324. SDE_REG_WRITE(&c, UBWC_STATIC, reg);
  325. SDE_REG_WRITE(&c, UBWC_CTRL_2, ver);
  326. SDE_REG_WRITE(&c, UBWC_PREDICTION_MODE, mode);
  327. } else if (IS_UBWC_20_SUPPORTED(ubwc_version)) {
  328. SDE_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);
  329. } else if (IS_UBWC_30_SUPPORTED(ubwc_version)) {
  330. u32 reg = m->mdp[0].ubwc_static |
  331. (m->mdp[0].ubwc_swizzle & 0x1) |
  332. ((m->mdp[0].highest_bank_bit & 0x3) << 4) |
  333. ((m->macrotile_mode & 0x1) << 12);
  334. if (IS_UBWC_30_SUPPORTED(m->ubwc_version))
  335. reg |= BIT(10);
  336. SDE_REG_WRITE(&c, UBWC_STATIC, reg);
  337. } else {
  338. SDE_ERROR("Unsupported UBWC version 0x%08x\n", ubwc_version);
  339. }
  340. }
  341. static void sde_hw_intf_audio_select(struct sde_hw_mdp *mdp)
  342. {
  343. struct sde_hw_blk_reg_map *c;
  344. if (!mdp)
  345. return;
  346. c = &mdp->hw;
  347. SDE_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1);
  348. }
  349. struct sde_hw_sid *sde_hw_sid_init(void __iomem *addr,
  350. u32 sid_len, const struct sde_mdss_cfg *m)
  351. {
  352. struct sde_hw_sid *c;
  353. c = kzalloc(sizeof(*c), GFP_KERNEL);
  354. if (!c)
  355. return ERR_PTR(-ENOMEM);
  356. c->hw.base_off = addr;
  357. c->hw.blk_off = 0;
  358. c->hw.length = sid_len;
  359. c->hw.hwversion = m->hwversion;
  360. c->hw.log_mask = SDE_DBG_MASK_SID;
  361. return c;
  362. }
  363. void sde_hw_sid_rotator_set(struct sde_hw_sid *sid)
  364. {
  365. SDE_REG_WRITE(&sid->hw, ROT_SID_RD, ROT_SID_ID_VAL);
  366. SDE_REG_WRITE(&sid->hw, ROT_SID_WR, ROT_SID_ID_VAL);
  367. }
  368. static void sde_hw_program_cwb_ppb_ctrl(struct sde_hw_mdp *mdp,
  369. bool dual, bool dspp_out)
  370. {
  371. u32 value = dspp_out ? 0x4 : 0x0;
  372. SDE_REG_WRITE(&mdp->hw, PPB2_CNTL, value);
  373. if (dual) {
  374. value |= 0x1;
  375. SDE_REG_WRITE(&mdp->hw, PPB3_CNTL, value);
  376. }
  377. }
  378. static void sde_hw_set_hdr_plus_metadata(struct sde_hw_mdp *mdp,
  379. u8 *payload, u32 len, u32 stream_id)
  380. {
  381. u32 i;
  382. size_t length = len - 1;
  383. u32 offset = 0, data = 0, byte_idx = 0;
  384. const u32 dword_size = sizeof(u32);
  385. if (!payload || !len) {
  386. SDE_ERROR("invalid payload with length: %d\n", len);
  387. return;
  388. }
  389. if (stream_id)
  390. offset = DP_DHDR_MEM_POOL_1_DATA - DP_DHDR_MEM_POOL_0_DATA;
  391. /* payload[0] is set in VSCEXT header byte 1, skip programming here */
  392. SDE_REG_WRITE(&mdp->hw, DP_DHDR_MEM_POOL_0_NUM_BYTES + offset, length);
  393. for (i = 1; i < len; i++) {
  394. if (byte_idx && !(byte_idx % dword_size)) {
  395. SDE_REG_WRITE(&mdp->hw, DP_DHDR_MEM_POOL_0_DATA +
  396. offset, data);
  397. data = 0;
  398. }
  399. data |= payload[i] << (8 * (byte_idx++ % dword_size));
  400. }
  401. SDE_REG_WRITE(&mdp->hw, DP_DHDR_MEM_POOL_0_DATA + offset, data);
  402. }
  403. static void _setup_mdp_ops(struct sde_hw_mdp_ops *ops,
  404. unsigned long cap)
  405. {
  406. ops->setup_split_pipe = sde_hw_setup_split_pipe;
  407. ops->setup_pp_split = sde_hw_setup_pp_split;
  408. ops->setup_cdm_output = sde_hw_setup_cdm_output;
  409. ops->setup_clk_force_ctrl = sde_hw_setup_clk_force_ctrl;
  410. ops->get_danger_status = sde_hw_get_danger_status;
  411. ops->setup_vsync_source = sde_hw_setup_vsync_source;
  412. ops->set_cwb_ppb_cntl = sde_hw_program_cwb_ppb_ctrl;
  413. ops->get_safe_status = sde_hw_get_safe_status;
  414. ops->get_split_flush_status = sde_hw_get_split_flush;
  415. ops->setup_dce = sde_hw_setup_dce;
  416. ops->reset_ubwc = sde_hw_reset_ubwc;
  417. ops->intf_audio_select = sde_hw_intf_audio_select;
  418. if (cap & BIT(SDE_MDP_VSYNC_SEL))
  419. ops->setup_vsync_source = sde_hw_setup_vsync_source;
  420. else
  421. ops->setup_vsync_source = sde_hw_setup_vsync_source_v1;
  422. if (cap & BIT(SDE_MDP_DHDR_MEMPOOL))
  423. ops->set_hdr_plus_metadata = sde_hw_set_hdr_plus_metadata;
  424. }
  425. static const struct sde_mdp_cfg *_top_offset(enum sde_mdp mdp,
  426. const struct sde_mdss_cfg *m,
  427. void __iomem *addr,
  428. struct sde_hw_blk_reg_map *b)
  429. {
  430. int i;
  431. if (!m || !addr || !b)
  432. return ERR_PTR(-EINVAL);
  433. for (i = 0; i < m->mdp_count; i++) {
  434. if (mdp == m->mdp[i].id) {
  435. b->base_off = addr;
  436. b->blk_off = m->mdp[i].base;
  437. b->length = m->mdp[i].len;
  438. b->hwversion = m->hwversion;
  439. b->log_mask = SDE_DBG_MASK_TOP;
  440. return &m->mdp[i];
  441. }
  442. }
  443. return ERR_PTR(-EINVAL);
  444. }
  445. static struct sde_hw_blk_ops sde_hw_ops = {
  446. .start = NULL,
  447. .stop = NULL,
  448. };
  449. struct sde_hw_mdp *sde_hw_mdptop_init(enum sde_mdp idx,
  450. void __iomem *addr,
  451. const struct sde_mdss_cfg *m)
  452. {
  453. struct sde_hw_mdp *mdp;
  454. const struct sde_mdp_cfg *cfg;
  455. int rc;
  456. if (!addr || !m)
  457. return ERR_PTR(-EINVAL);
  458. mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
  459. if (!mdp)
  460. return ERR_PTR(-ENOMEM);
  461. cfg = _top_offset(idx, m, addr, &mdp->hw);
  462. if (IS_ERR_OR_NULL(cfg)) {
  463. kfree(mdp);
  464. return ERR_PTR(-EINVAL);
  465. }
  466. /*
  467. * Assign ops
  468. */
  469. mdp->idx = idx;
  470. mdp->caps = cfg;
  471. _setup_mdp_ops(&mdp->ops, mdp->caps->features);
  472. rc = sde_hw_blk_init(&mdp->base, SDE_HW_BLK_TOP, idx, &sde_hw_ops);
  473. if (rc) {
  474. SDE_ERROR("failed to init hw blk %d\n", rc);
  475. goto blk_init_error;
  476. }
  477. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
  478. mdp->hw.blk_off, mdp->hw.blk_off + mdp->hw.length,
  479. mdp->hw.xin_id);
  480. sde_dbg_set_sde_top_offset(mdp->hw.blk_off);
  481. return mdp;
  482. blk_init_error:
  483. kzfree(mdp);
  484. return ERR_PTR(rc);
  485. }
  486. void sde_hw_mdp_destroy(struct sde_hw_mdp *mdp)
  487. {
  488. if (mdp)
  489. sde_hw_blk_destroy(&mdp->base);
  490. kfree(mdp);
  491. }