dp_tx.c 177 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef WLAN_PEER_JITTER
  66. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  67. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  68. #endif
  69. #ifdef QCA_DP_TX_FW_METADATA_V2
  70. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  71. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  80. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  81. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  82. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  84. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  85. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  86. #else
  87. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  88. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  97. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  98. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  99. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  100. HTT_TCL_METADATA_TYPE_PEER_BASED
  101. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  102. HTT_TCL_METADATA_TYPE_VDEV_BASED
  103. #endif
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  232. /**
  233. * dp_is_tput_high() - Check if throughput is high
  234. *
  235. * @soc - core txrx main context
  236. *
  237. * The current function is based of the RTPM tput policy variable where RTPM is
  238. * avoided based on throughput.
  239. */
  240. static inline int dp_is_tput_high(struct dp_soc *soc)
  241. {
  242. return dp_get_rtpm_tput_policy_requirement(soc);
  243. }
  244. #if defined(FEATURE_TSO)
  245. /**
  246. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  247. *
  248. * @soc - core txrx main context
  249. * @seg_desc - tso segment descriptor
  250. * @num_seg_desc - tso number segment descriptor
  251. */
  252. static void dp_tx_tso_unmap_segment(
  253. struct dp_soc *soc,
  254. struct qdf_tso_seg_elem_t *seg_desc,
  255. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  256. {
  257. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  258. if (qdf_unlikely(!seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else if (qdf_unlikely(!num_seg_desc)) {
  263. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  264. __func__, __LINE__);
  265. qdf_assert(0);
  266. } else {
  267. bool is_last_seg;
  268. /* no tso segment left to do dma unmap */
  269. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  270. return;
  271. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  272. true : false;
  273. qdf_nbuf_unmap_tso_segment(soc->osdev,
  274. seg_desc, is_last_seg);
  275. num_seg_desc->num_seg.tso_cmn_num_seg--;
  276. }
  277. }
  278. /**
  279. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  280. * back to the freelist
  281. *
  282. * @soc - soc device handle
  283. * @tx_desc - Tx software descriptor
  284. */
  285. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  286. struct dp_tx_desc_s *tx_desc)
  287. {
  288. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  289. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  290. dp_tx_err("SO desc is NULL!");
  291. qdf_assert(0);
  292. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  293. dp_tx_err("TSO num desc is NULL!");
  294. qdf_assert(0);
  295. } else {
  296. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  297. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  298. msdu_ext_desc->tso_num_desc;
  299. /* Add the tso num segment into the free list */
  300. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  301. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  302. tx_desc->msdu_ext_desc->
  303. tso_num_desc);
  304. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  305. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  306. }
  307. /* Add the tso segment into the free list*/
  308. dp_tx_tso_desc_free(soc,
  309. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  310. tso_desc);
  311. tx_desc->msdu_ext_desc->tso_desc = NULL;
  312. }
  313. }
  314. #else
  315. static void dp_tx_tso_unmap_segment(
  316. struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *seg_desc,
  318. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  319. {
  320. }
  321. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  322. struct dp_tx_desc_s *tx_desc)
  323. {
  324. }
  325. #endif
  326. /**
  327. * dp_tx_desc_release() - Release Tx Descriptor
  328. * @tx_desc : Tx Descriptor
  329. * @desc_pool_id: Descriptor Pool ID
  330. *
  331. * Deallocate all resources attached to Tx descriptor and free the Tx
  332. * descriptor.
  333. *
  334. * Return:
  335. */
  336. void
  337. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  338. {
  339. struct dp_pdev *pdev = tx_desc->pdev;
  340. struct dp_soc *soc;
  341. uint8_t comp_status = 0;
  342. qdf_assert(pdev);
  343. soc = pdev->soc;
  344. dp_tx_outstanding_dec(pdev);
  345. if (tx_desc->msdu_ext_desc) {
  346. if (tx_desc->frm_type == dp_tx_frm_tso)
  347. dp_tx_tso_desc_release(soc, tx_desc);
  348. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  349. dp_tx_me_free_buf(tx_desc->pdev,
  350. tx_desc->msdu_ext_desc->me_buffer);
  351. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  352. }
  353. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  354. qdf_atomic_dec(&soc->num_tx_exception);
  355. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  356. tx_desc->buffer_src)
  357. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  358. soc->hal_soc);
  359. else
  360. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  361. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  362. tx_desc->id, comp_status,
  363. qdf_atomic_read(&pdev->num_tx_outstanding));
  364. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  365. return;
  366. }
  367. /**
  368. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  369. * @vdev: DP vdev Handle
  370. * @nbuf: skb
  371. * @msdu_info: msdu_info required to create HTT metadata
  372. *
  373. * Prepares and fills HTT metadata in the frame pre-header for special frames
  374. * that should be transmitted using varying transmit parameters.
  375. * There are 2 VDEV modes that currently needs this special metadata -
  376. * 1) Mesh Mode
  377. * 2) DSRC Mode
  378. *
  379. * Return: HTT metadata size
  380. *
  381. */
  382. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  383. struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. uint32_t *meta_data = msdu_info->meta_data;
  386. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  387. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  388. uint8_t htt_desc_size;
  389. /* Size rounded of multiple of 8 bytes */
  390. uint8_t htt_desc_size_aligned;
  391. uint8_t *hdr = NULL;
  392. /*
  393. * Metadata - HTT MSDU Extension header
  394. */
  395. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  396. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  397. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  398. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  399. meta_data[0]) ||
  400. msdu_info->exception_fw) {
  401. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  402. htt_desc_size_aligned)) {
  403. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  404. htt_desc_size_aligned);
  405. if (!nbuf) {
  406. /*
  407. * qdf_nbuf_realloc_headroom won't do skb_clone
  408. * as skb_realloc_headroom does. so, no free is
  409. * needed here.
  410. */
  411. DP_STATS_INC(vdev,
  412. tx_i.dropped.headroom_insufficient,
  413. 1);
  414. qdf_print(" %s[%d] skb_realloc_headroom failed",
  415. __func__, __LINE__);
  416. return 0;
  417. }
  418. }
  419. /* Fill and add HTT metaheader */
  420. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  421. if (!hdr) {
  422. dp_tx_err("Error in filling HTT metadata");
  423. return 0;
  424. }
  425. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  426. } else if (vdev->opmode == wlan_op_mode_ocb) {
  427. /* Todo - Add support for DSRC */
  428. }
  429. return htt_desc_size_aligned;
  430. }
  431. /**
  432. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  433. * @tso_seg: TSO segment to process
  434. * @ext_desc: Pointer to MSDU extension descriptor
  435. *
  436. * Return: void
  437. */
  438. #if defined(FEATURE_TSO)
  439. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  440. void *ext_desc)
  441. {
  442. uint8_t num_frag;
  443. uint32_t tso_flags;
  444. /*
  445. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  446. * tcp_flag_mask
  447. *
  448. * Checksum enable flags are set in TCL descriptor and not in Extension
  449. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  450. */
  451. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  452. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  453. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  454. tso_seg->tso_flags.ip_len);
  455. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  456. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  457. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  458. uint32_t lo = 0;
  459. uint32_t hi = 0;
  460. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  461. (tso_seg->tso_frags[num_frag].length));
  462. qdf_dmaaddr_to_32s(
  463. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  464. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  465. tso_seg->tso_frags[num_frag].length);
  466. }
  467. return;
  468. }
  469. #else
  470. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  471. void *ext_desc)
  472. {
  473. return;
  474. }
  475. #endif
  476. #if defined(FEATURE_TSO)
  477. /**
  478. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  479. * allocated and free them
  480. *
  481. * @soc: soc handle
  482. * @free_seg: list of tso segments
  483. * @msdu_info: msdu descriptor
  484. *
  485. * Return - void
  486. */
  487. static void dp_tx_free_tso_seg_list(
  488. struct dp_soc *soc,
  489. struct qdf_tso_seg_elem_t *free_seg,
  490. struct dp_tx_msdu_info_s *msdu_info)
  491. {
  492. struct qdf_tso_seg_elem_t *next_seg;
  493. while (free_seg) {
  494. next_seg = free_seg->next;
  495. dp_tx_tso_desc_free(soc,
  496. msdu_info->tx_queue.desc_pool_id,
  497. free_seg);
  498. free_seg = next_seg;
  499. }
  500. }
  501. /**
  502. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  503. * allocated and free them
  504. *
  505. * @soc: soc handle
  506. * @free_num_seg: list of tso number segments
  507. * @msdu_info: msdu descriptor
  508. * Return - void
  509. */
  510. static void dp_tx_free_tso_num_seg_list(
  511. struct dp_soc *soc,
  512. struct qdf_tso_num_seg_elem_t *free_num_seg,
  513. struct dp_tx_msdu_info_s *msdu_info)
  514. {
  515. struct qdf_tso_num_seg_elem_t *next_num_seg;
  516. while (free_num_seg) {
  517. next_num_seg = free_num_seg->next;
  518. dp_tso_num_seg_free(soc,
  519. msdu_info->tx_queue.desc_pool_id,
  520. free_num_seg);
  521. free_num_seg = next_num_seg;
  522. }
  523. }
  524. /**
  525. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  526. * do dma unmap for each segment
  527. *
  528. * @soc: soc handle
  529. * @free_seg: list of tso segments
  530. * @num_seg_desc: tso number segment descriptor
  531. *
  532. * Return - void
  533. */
  534. static void dp_tx_unmap_tso_seg_list(
  535. struct dp_soc *soc,
  536. struct qdf_tso_seg_elem_t *free_seg,
  537. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  538. {
  539. struct qdf_tso_seg_elem_t *next_seg;
  540. if (qdf_unlikely(!num_seg_desc)) {
  541. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  542. return;
  543. }
  544. while (free_seg) {
  545. next_seg = free_seg->next;
  546. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  547. free_seg = next_seg;
  548. }
  549. }
  550. #ifdef FEATURE_TSO_STATS
  551. /**
  552. * dp_tso_get_stats_idx: Retrieve the tso packet id
  553. * @pdev - pdev handle
  554. *
  555. * Return: id
  556. */
  557. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  558. {
  559. uint32_t stats_idx;
  560. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  561. % CDP_MAX_TSO_PACKETS);
  562. return stats_idx;
  563. }
  564. #else
  565. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  566. {
  567. return 0;
  568. }
  569. #endif /* FEATURE_TSO_STATS */
  570. /**
  571. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  572. * free the tso segments descriptor and
  573. * tso num segments descriptor
  574. *
  575. * @soc: soc handle
  576. * @msdu_info: msdu descriptor
  577. * @tso_seg_unmap: flag to show if dma unmap is necessary
  578. *
  579. * Return - void
  580. */
  581. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  582. struct dp_tx_msdu_info_s *msdu_info,
  583. bool tso_seg_unmap)
  584. {
  585. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  586. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  587. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  588. tso_info->tso_num_seg_list;
  589. /* do dma unmap for each segment */
  590. if (tso_seg_unmap)
  591. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  592. /* free all tso number segment descriptor though looks only have 1 */
  593. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  594. /* free all tso segment descriptor */
  595. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  596. }
  597. /**
  598. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  599. * @vdev: virtual device handle
  600. * @msdu: network buffer
  601. * @msdu_info: meta data associated with the msdu
  602. *
  603. * Return: QDF_STATUS_SUCCESS success
  604. */
  605. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  606. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  607. {
  608. struct qdf_tso_seg_elem_t *tso_seg;
  609. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  610. struct dp_soc *soc = vdev->pdev->soc;
  611. struct dp_pdev *pdev = vdev->pdev;
  612. struct qdf_tso_info_t *tso_info;
  613. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  614. tso_info = &msdu_info->u.tso_info;
  615. tso_info->curr_seg = NULL;
  616. tso_info->tso_seg_list = NULL;
  617. tso_info->num_segs = num_seg;
  618. msdu_info->frm_type = dp_tx_frm_tso;
  619. tso_info->tso_num_seg_list = NULL;
  620. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  621. while (num_seg) {
  622. tso_seg = dp_tx_tso_desc_alloc(
  623. soc, msdu_info->tx_queue.desc_pool_id);
  624. if (tso_seg) {
  625. tso_seg->next = tso_info->tso_seg_list;
  626. tso_info->tso_seg_list = tso_seg;
  627. num_seg--;
  628. } else {
  629. dp_err_rl("Failed to alloc tso seg desc");
  630. DP_STATS_INC_PKT(vdev->pdev,
  631. tso_stats.tso_no_mem_dropped, 1,
  632. qdf_nbuf_len(msdu));
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  634. return QDF_STATUS_E_NOMEM;
  635. }
  636. }
  637. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  638. tso_num_seg = dp_tso_num_seg_alloc(soc,
  639. msdu_info->tx_queue.desc_pool_id);
  640. if (tso_num_seg) {
  641. tso_num_seg->next = tso_info->tso_num_seg_list;
  642. tso_info->tso_num_seg_list = tso_num_seg;
  643. } else {
  644. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  645. __func__);
  646. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  647. return QDF_STATUS_E_NOMEM;
  648. }
  649. msdu_info->num_seg =
  650. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  651. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  652. msdu_info->num_seg);
  653. if (!(msdu_info->num_seg)) {
  654. /*
  655. * Free allocated TSO seg desc and number seg desc,
  656. * do unmap for segments if dma map has done.
  657. */
  658. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  659. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  660. return QDF_STATUS_E_INVAL;
  661. }
  662. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  663. msdu, 0, DP_TX_DESC_MAP);
  664. tso_info->curr_seg = tso_info->tso_seg_list;
  665. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  666. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  667. msdu, msdu_info->num_seg);
  668. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  669. tso_info->msdu_stats_idx);
  670. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  671. return QDF_STATUS_SUCCESS;
  672. }
  673. #else
  674. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  675. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  676. {
  677. return QDF_STATUS_E_NOMEM;
  678. }
  679. #endif
  680. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  681. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  682. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  683. /**
  684. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  685. * @vdev: DP Vdev handle
  686. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  687. * @desc_pool_id: Descriptor Pool ID
  688. *
  689. * Return:
  690. */
  691. static
  692. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  693. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  694. {
  695. uint8_t i;
  696. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  697. struct dp_tx_seg_info_s *seg_info;
  698. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  699. struct dp_soc *soc = vdev->pdev->soc;
  700. /* Allocate an extension descriptor */
  701. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  702. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  703. if (!msdu_ext_desc) {
  704. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  705. return NULL;
  706. }
  707. if (msdu_info->exception_fw &&
  708. qdf_unlikely(vdev->mesh_vdev)) {
  709. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  710. &msdu_info->meta_data[0],
  711. sizeof(struct htt_tx_msdu_desc_ext2_t));
  712. qdf_atomic_inc(&soc->num_tx_exception);
  713. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  714. }
  715. switch (msdu_info->frm_type) {
  716. case dp_tx_frm_sg:
  717. case dp_tx_frm_me:
  718. case dp_tx_frm_raw:
  719. seg_info = msdu_info->u.sg_info.curr_seg;
  720. /* Update the buffer pointers in MSDU Extension Descriptor */
  721. for (i = 0; i < seg_info->frag_cnt; i++) {
  722. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  723. seg_info->frags[i].paddr_lo,
  724. seg_info->frags[i].paddr_hi,
  725. seg_info->frags[i].len);
  726. }
  727. break;
  728. case dp_tx_frm_tso:
  729. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  730. &cached_ext_desc[0]);
  731. break;
  732. default:
  733. break;
  734. }
  735. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  736. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  737. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  738. msdu_ext_desc->vaddr);
  739. return msdu_ext_desc;
  740. }
  741. /**
  742. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  743. *
  744. * @skb: skb to be traced
  745. * @msdu_id: msdu_id of the packet
  746. * @vdev_id: vdev_id of the packet
  747. *
  748. * Return: None
  749. */
  750. #ifdef DP_DISABLE_TX_PKT_TRACE
  751. static void dp_tx_trace_pkt(struct dp_soc *soc,
  752. qdf_nbuf_t skb, uint16_t msdu_id,
  753. uint8_t vdev_id)
  754. {
  755. }
  756. #else
  757. static void dp_tx_trace_pkt(struct dp_soc *soc,
  758. qdf_nbuf_t skb, uint16_t msdu_id,
  759. uint8_t vdev_id)
  760. {
  761. if (dp_is_tput_high(soc))
  762. return;
  763. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  764. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  765. DPTRACE(qdf_dp_trace_ptr(skb,
  766. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  767. QDF_TRACE_DEFAULT_PDEV_ID,
  768. qdf_nbuf_data_addr(skb),
  769. sizeof(qdf_nbuf_data(skb)),
  770. msdu_id, vdev_id, 0));
  771. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  772. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  773. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  774. msdu_id, QDF_TX));
  775. }
  776. #endif
  777. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  778. /**
  779. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  780. * exception by the upper layer (OS_IF)
  781. * @soc: DP soc handle
  782. * @nbuf: packet to be transmitted
  783. *
  784. * Returns: 1 if the packet is marked as exception,
  785. * 0, if the packet is not marked as exception.
  786. */
  787. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  788. qdf_nbuf_t nbuf)
  789. {
  790. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  791. }
  792. #else
  793. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  794. qdf_nbuf_t nbuf)
  795. {
  796. return 0;
  797. }
  798. #endif
  799. #ifdef DP_TRAFFIC_END_INDICATION
  800. /**
  801. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  802. * as indication to fw to inform that
  803. * data stream has ended
  804. * @vdev: DP vdev handle
  805. * @nbuf: original buffer from network stack
  806. *
  807. * Return: NULL on failure,
  808. * nbuf on success
  809. */
  810. static inline qdf_nbuf_t
  811. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  812. qdf_nbuf_t nbuf)
  813. {
  814. /* Packet length should be enough to copy upto L3 header */
  815. uint8_t end_nbuf_len = 64;
  816. uint8_t htt_desc_size_aligned;
  817. uint8_t htt_desc_size;
  818. qdf_nbuf_t end_nbuf;
  819. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  820. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  821. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  822. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  823. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  824. if (!end_nbuf) {
  825. end_nbuf = qdf_nbuf_alloc(NULL,
  826. (htt_desc_size_aligned +
  827. end_nbuf_len),
  828. htt_desc_size_aligned,
  829. 8, false);
  830. if (!end_nbuf) {
  831. dp_err("Packet allocation failed");
  832. goto out;
  833. }
  834. } else {
  835. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  836. }
  837. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  838. end_nbuf_len);
  839. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  840. return end_nbuf;
  841. }
  842. out:
  843. return NULL;
  844. }
  845. /**
  846. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  847. * via exception path.
  848. * @vdev: DP vdev handle
  849. * @end_nbuf: skb to send as indication
  850. * @msdu_info: msdu_info of original nbuf
  851. * @peer_id: peer id
  852. *
  853. * Return: None
  854. */
  855. static inline void
  856. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  857. qdf_nbuf_t end_nbuf,
  858. struct dp_tx_msdu_info_s *msdu_info,
  859. uint16_t peer_id)
  860. {
  861. struct dp_tx_msdu_info_s e_msdu_info = {0};
  862. qdf_nbuf_t nbuf;
  863. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  864. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  865. e_msdu_info.tx_queue = msdu_info->tx_queue;
  866. e_msdu_info.tid = msdu_info->tid;
  867. e_msdu_info.exception_fw = 1;
  868. desc_ext->host_tx_desc_pool = 1;
  869. desc_ext->traffic_end_indication = 1;
  870. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  871. peer_id, NULL);
  872. if (nbuf) {
  873. dp_err("Traffic end indication packet tx failed");
  874. qdf_nbuf_free(nbuf);
  875. }
  876. }
  877. /**
  878. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  879. * mark it traffic end indication
  880. * packet.
  881. * @tx_desc: Tx descriptor pointer
  882. * @msdu_info: msdu_info structure pointer
  883. *
  884. * Return: None
  885. */
  886. static inline void
  887. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  888. struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  891. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  892. if (qdf_unlikely(desc_ext->traffic_end_indication))
  893. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  894. }
  895. /**
  896. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  897. * freeing which are associated
  898. * with traffic end indication
  899. * flagged descriptor.
  900. * @soc: dp soc handle
  901. * @desc: Tx descriptor pointer
  902. * @nbuf: buffer pointer
  903. *
  904. * Return: True if packet gets enqueued else false
  905. */
  906. static bool
  907. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  908. struct dp_tx_desc_s *desc,
  909. qdf_nbuf_t nbuf)
  910. {
  911. struct dp_vdev *vdev = NULL;
  912. if (qdf_unlikely((desc->flags &
  913. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  914. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  915. DP_MOD_ID_TX_COMP);
  916. if (vdev) {
  917. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  918. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  919. return true;
  920. }
  921. }
  922. return false;
  923. }
  924. /**
  925. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  926. * enable/disable status
  927. * @vdev: dp vdev handle
  928. *
  929. * Return: True if feature is enable else false
  930. */
  931. static inline bool
  932. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  933. {
  934. return qdf_unlikely(vdev->traffic_end_ind_en);
  935. }
  936. static inline qdf_nbuf_t
  937. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  938. struct dp_tx_msdu_info_s *msdu_info,
  939. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  940. {
  941. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  942. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  943. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  944. if (qdf_unlikely(end_nbuf))
  945. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  946. msdu_info, peer_id);
  947. return nbuf;
  948. }
  949. #else
  950. static inline qdf_nbuf_t
  951. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  952. qdf_nbuf_t nbuf)
  953. {
  954. return NULL;
  955. }
  956. static inline void
  957. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  958. qdf_nbuf_t end_nbuf,
  959. struct dp_tx_msdu_info_s *msdu_info,
  960. uint16_t peer_id)
  961. {}
  962. static inline void
  963. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  964. struct dp_tx_msdu_info_s *msdu_info)
  965. {}
  966. static inline bool
  967. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  968. struct dp_tx_desc_s *desc,
  969. qdf_nbuf_t nbuf)
  970. {
  971. return false;
  972. }
  973. static inline bool
  974. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  975. {
  976. return false;
  977. }
  978. static inline qdf_nbuf_t
  979. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  980. struct dp_tx_msdu_info_s *msdu_info,
  981. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  982. {
  983. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  984. }
  985. #endif
  986. /**
  987. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  988. * @vdev: DP vdev handle
  989. * @nbuf: skb
  990. * @desc_pool_id: Descriptor pool ID
  991. * @meta_data: Metadata to the fw
  992. * @tx_exc_metadata: Handle that holds exception path metadata
  993. * Allocate and prepare Tx descriptor with msdu information.
  994. *
  995. * Return: Pointer to Tx Descriptor on success,
  996. * NULL on failure
  997. */
  998. static
  999. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1000. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1001. struct dp_tx_msdu_info_s *msdu_info,
  1002. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1003. {
  1004. uint8_t align_pad;
  1005. uint8_t is_exception = 0;
  1006. uint8_t htt_hdr_size;
  1007. struct dp_tx_desc_s *tx_desc;
  1008. struct dp_pdev *pdev = vdev->pdev;
  1009. struct dp_soc *soc = pdev->soc;
  1010. if (dp_tx_limit_check(vdev))
  1011. return NULL;
  1012. /* Allocate software Tx descriptor */
  1013. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1014. if (qdf_unlikely(!tx_desc)) {
  1015. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1016. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1017. return NULL;
  1018. }
  1019. dp_tx_outstanding_inc(pdev);
  1020. /* Initialize the SW tx descriptor */
  1021. tx_desc->nbuf = nbuf;
  1022. tx_desc->frm_type = dp_tx_frm_std;
  1023. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1024. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1025. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1026. tx_desc->vdev_id = vdev->vdev_id;
  1027. tx_desc->pdev = pdev;
  1028. tx_desc->msdu_ext_desc = NULL;
  1029. tx_desc->pkt_offset = 0;
  1030. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1031. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1032. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1033. if (qdf_unlikely(vdev->multipass_en)) {
  1034. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1035. goto failure;
  1036. }
  1037. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1038. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1039. is_exception = 1;
  1040. /*
  1041. * For special modes (vdev_type == ocb or mesh), data frames should be
  1042. * transmitted using varying transmit parameters (tx spec) which include
  1043. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1044. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1045. * These frames are sent as exception packets to firmware.
  1046. *
  1047. * HW requirement is that metadata should always point to a
  1048. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1049. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1050. * to get 8-byte aligned start address along with align_pad added
  1051. *
  1052. * |-----------------------------|
  1053. * | |
  1054. * |-----------------------------| <-----Buffer Pointer Address given
  1055. * | | ^ in HW descriptor (aligned)
  1056. * | HTT Metadata | |
  1057. * | | |
  1058. * | | | Packet Offset given in descriptor
  1059. * | | |
  1060. * |-----------------------------| |
  1061. * | Alignment Pad | v
  1062. * |-----------------------------| <----- Actual buffer start address
  1063. * | SKB Data | (Unaligned)
  1064. * | |
  1065. * | |
  1066. * | |
  1067. * | |
  1068. * | |
  1069. * |-----------------------------|
  1070. */
  1071. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1072. (vdev->opmode == wlan_op_mode_ocb) ||
  1073. (tx_exc_metadata &&
  1074. tx_exc_metadata->is_tx_sniffer)) {
  1075. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1076. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1077. DP_STATS_INC(vdev,
  1078. tx_i.dropped.headroom_insufficient, 1);
  1079. goto failure;
  1080. }
  1081. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1082. dp_tx_err("qdf_nbuf_push_head failed");
  1083. goto failure;
  1084. }
  1085. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1086. msdu_info);
  1087. if (htt_hdr_size == 0)
  1088. goto failure;
  1089. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1090. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1091. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1092. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1093. msdu_info);
  1094. is_exception = 1;
  1095. tx_desc->length -= tx_desc->pkt_offset;
  1096. }
  1097. #if !TQM_BYPASS_WAR
  1098. if (is_exception || tx_exc_metadata)
  1099. #endif
  1100. {
  1101. /* Temporary WAR due to TQM VP issues */
  1102. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1103. qdf_atomic_inc(&soc->num_tx_exception);
  1104. }
  1105. return tx_desc;
  1106. failure:
  1107. dp_tx_desc_release(tx_desc, desc_pool_id);
  1108. return NULL;
  1109. }
  1110. /**
  1111. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1112. * @vdev: DP vdev handle
  1113. * @nbuf: skb
  1114. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1115. * @desc_pool_id : Descriptor Pool ID
  1116. *
  1117. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1118. * information. For frames with fragments, allocate and prepare
  1119. * an MSDU extension descriptor
  1120. *
  1121. * Return: Pointer to Tx Descriptor on success,
  1122. * NULL on failure
  1123. */
  1124. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1125. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1126. uint8_t desc_pool_id)
  1127. {
  1128. struct dp_tx_desc_s *tx_desc;
  1129. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1130. struct dp_pdev *pdev = vdev->pdev;
  1131. struct dp_soc *soc = pdev->soc;
  1132. if (dp_tx_limit_check(vdev))
  1133. return NULL;
  1134. /* Allocate software Tx descriptor */
  1135. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1136. if (!tx_desc) {
  1137. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1138. return NULL;
  1139. }
  1140. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1141. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1142. dp_tx_outstanding_inc(pdev);
  1143. /* Initialize the SW tx descriptor */
  1144. tx_desc->nbuf = nbuf;
  1145. tx_desc->frm_type = msdu_info->frm_type;
  1146. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1147. tx_desc->vdev_id = vdev->vdev_id;
  1148. tx_desc->pdev = pdev;
  1149. tx_desc->pkt_offset = 0;
  1150. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1151. /* Handle scattered frames - TSO/SG/ME */
  1152. /* Allocate and prepare an extension descriptor for scattered frames */
  1153. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1154. if (!msdu_ext_desc) {
  1155. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1156. goto failure;
  1157. }
  1158. #if TQM_BYPASS_WAR
  1159. /* Temporary WAR due to TQM VP issues */
  1160. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1161. qdf_atomic_inc(&soc->num_tx_exception);
  1162. #endif
  1163. if (qdf_unlikely(msdu_info->exception_fw))
  1164. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1165. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1166. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1167. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1168. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1169. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1170. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1171. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1172. else
  1173. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1174. return tx_desc;
  1175. failure:
  1176. dp_tx_desc_release(tx_desc, desc_pool_id);
  1177. return NULL;
  1178. }
  1179. /**
  1180. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1181. * @vdev: DP vdev handle
  1182. * @nbuf: buffer pointer
  1183. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1184. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1185. * descriptor
  1186. *
  1187. * Return:
  1188. */
  1189. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1190. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1191. {
  1192. qdf_nbuf_t curr_nbuf = NULL;
  1193. uint16_t total_len = 0;
  1194. qdf_dma_addr_t paddr;
  1195. int32_t i;
  1196. int32_t mapped_buf_num = 0;
  1197. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1198. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1199. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1200. /* Continue only if frames are of DATA type */
  1201. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1202. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1203. dp_tx_debug("Pkt. recd is of not data type");
  1204. goto error;
  1205. }
  1206. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1207. if (vdev->raw_mode_war &&
  1208. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1209. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1210. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1211. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1212. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1213. /*
  1214. * Number of nbuf's must not exceed the size of the frags
  1215. * array in seg_info.
  1216. */
  1217. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1218. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1219. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1220. goto error;
  1221. }
  1222. if (QDF_STATUS_SUCCESS !=
  1223. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1224. curr_nbuf,
  1225. QDF_DMA_TO_DEVICE,
  1226. curr_nbuf->len)) {
  1227. dp_tx_err("%s dma map error ", __func__);
  1228. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1229. goto error;
  1230. }
  1231. /* Update the count of mapped nbuf's */
  1232. mapped_buf_num++;
  1233. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1234. seg_info->frags[i].paddr_lo = paddr;
  1235. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1236. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1237. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1238. total_len += qdf_nbuf_len(curr_nbuf);
  1239. }
  1240. seg_info->frag_cnt = i;
  1241. seg_info->total_len = total_len;
  1242. seg_info->next = NULL;
  1243. sg_info->curr_seg = seg_info;
  1244. msdu_info->frm_type = dp_tx_frm_raw;
  1245. msdu_info->num_seg = 1;
  1246. return nbuf;
  1247. error:
  1248. i = 0;
  1249. while (nbuf) {
  1250. curr_nbuf = nbuf;
  1251. if (i < mapped_buf_num) {
  1252. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1253. QDF_DMA_TO_DEVICE,
  1254. curr_nbuf->len);
  1255. i++;
  1256. }
  1257. nbuf = qdf_nbuf_next(nbuf);
  1258. qdf_nbuf_free(curr_nbuf);
  1259. }
  1260. return NULL;
  1261. }
  1262. /**
  1263. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1264. * @soc: DP soc handle
  1265. * @nbuf: Buffer pointer
  1266. *
  1267. * unmap the chain of nbufs that belong to this RAW frame.
  1268. *
  1269. * Return: None
  1270. */
  1271. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1272. qdf_nbuf_t nbuf)
  1273. {
  1274. qdf_nbuf_t cur_nbuf = nbuf;
  1275. do {
  1276. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1277. QDF_DMA_TO_DEVICE,
  1278. cur_nbuf->len);
  1279. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1280. } while (cur_nbuf);
  1281. }
  1282. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1283. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1284. qdf_nbuf_t nbuf)
  1285. {
  1286. qdf_nbuf_t nbuf_local;
  1287. struct dp_vdev *vdev_local = vdev_hdl;
  1288. do {
  1289. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1290. break;
  1291. nbuf_local = nbuf;
  1292. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1293. htt_cmn_pkt_type_raw))
  1294. break;
  1295. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1296. break;
  1297. else if (qdf_nbuf_is_tso((nbuf_local)))
  1298. break;
  1299. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1300. (nbuf_local),
  1301. NULL, 1, 0);
  1302. } while (0);
  1303. }
  1304. #endif
  1305. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1306. /**
  1307. * dp_tx_update_stats() - Update soc level tx stats
  1308. * @soc: DP soc handle
  1309. * @tx_desc: TX descriptor reference
  1310. * @ring_id: TCL ring id
  1311. *
  1312. * Returns: none
  1313. */
  1314. void dp_tx_update_stats(struct dp_soc *soc,
  1315. struct dp_tx_desc_s *tx_desc,
  1316. uint8_t ring_id)
  1317. {
  1318. uint32_t stats_len = 0;
  1319. if (tx_desc->frm_type == dp_tx_frm_tso)
  1320. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1321. else
  1322. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1323. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1324. }
  1325. int
  1326. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1327. struct dp_tx_desc_s *tx_desc,
  1328. uint8_t tid,
  1329. struct dp_tx_msdu_info_s *msdu_info,
  1330. uint8_t ring_id)
  1331. {
  1332. struct dp_swlm *swlm = &soc->swlm;
  1333. union swlm_data swlm_query_data;
  1334. struct dp_swlm_tcl_data tcl_data;
  1335. QDF_STATUS status;
  1336. int ret;
  1337. if (!swlm->is_enabled)
  1338. return msdu_info->skip_hp_update;
  1339. tcl_data.nbuf = tx_desc->nbuf;
  1340. tcl_data.tid = tid;
  1341. tcl_data.ring_id = ring_id;
  1342. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1343. tcl_data.pkt_len =
  1344. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1345. } else {
  1346. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1347. }
  1348. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1349. swlm_query_data.tcl_data = &tcl_data;
  1350. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1351. if (QDF_IS_STATUS_ERROR(status)) {
  1352. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1353. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1354. return 0;
  1355. }
  1356. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1357. if (ret) {
  1358. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1359. } else {
  1360. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1361. }
  1362. return ret;
  1363. }
  1364. void
  1365. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1366. int coalesce)
  1367. {
  1368. if (coalesce)
  1369. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1370. else
  1371. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1372. }
  1373. static inline void
  1374. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1375. {
  1376. if (((i + 1) < msdu_info->num_seg))
  1377. msdu_info->skip_hp_update = 1;
  1378. else
  1379. msdu_info->skip_hp_update = 0;
  1380. }
  1381. static inline void
  1382. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1383. {
  1384. hal_ring_handle_t hal_ring_hdl =
  1385. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1386. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1387. dp_err("Fillmore: SRNG access start failed");
  1388. return;
  1389. }
  1390. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1391. }
  1392. static inline void
  1393. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1394. QDF_STATUS status,
  1395. struct dp_tx_msdu_info_s *msdu_info)
  1396. {
  1397. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1398. dp_flush_tcp_hp(soc,
  1399. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1400. }
  1401. }
  1402. #else
  1403. static inline void
  1404. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1405. {
  1406. }
  1407. static inline void
  1408. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1409. QDF_STATUS status,
  1410. struct dp_tx_msdu_info_s *msdu_info)
  1411. {
  1412. }
  1413. #endif
  1414. #ifdef FEATURE_RUNTIME_PM
  1415. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1416. {
  1417. int ret;
  1418. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1419. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1420. return ret;
  1421. }
  1422. /**
  1423. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1424. * @soc: Datapath soc handle
  1425. * @hal_ring_hdl: HAL ring handle
  1426. * @coalesce: Coalesce the current write or not
  1427. *
  1428. * Wrapper for HAL ring access end for data transmission for
  1429. * FEATURE_RUNTIME_PM
  1430. *
  1431. * Returns: none
  1432. */
  1433. void
  1434. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1435. hal_ring_handle_t hal_ring_hdl,
  1436. int coalesce)
  1437. {
  1438. int ret;
  1439. /*
  1440. * Avoid runtime get and put APIs under high throughput scenarios.
  1441. */
  1442. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1443. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1444. return;
  1445. }
  1446. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1447. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1448. if (hif_system_pm_state_check(soc->hif_handle)) {
  1449. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1450. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1451. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1452. } else {
  1453. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1454. }
  1455. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1456. } else {
  1457. dp_runtime_get(soc);
  1458. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1459. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1460. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1461. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1462. dp_runtime_put(soc);
  1463. }
  1464. }
  1465. #else
  1466. #ifdef DP_POWER_SAVE
  1467. void
  1468. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1469. hal_ring_handle_t hal_ring_hdl,
  1470. int coalesce)
  1471. {
  1472. if (hif_system_pm_state_check(soc->hif_handle)) {
  1473. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1474. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1475. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1476. } else {
  1477. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1478. }
  1479. }
  1480. #endif
  1481. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1482. {
  1483. return 0;
  1484. }
  1485. #endif
  1486. /**
  1487. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1488. * @vdev: DP vdev handle
  1489. * @nbuf: skb
  1490. *
  1491. * Extract the DSCP or PCP information from frame and map into TID value.
  1492. *
  1493. * Return: void
  1494. */
  1495. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1496. struct dp_tx_msdu_info_s *msdu_info)
  1497. {
  1498. uint8_t tos = 0, dscp_tid_override = 0;
  1499. uint8_t *hdr_ptr, *L3datap;
  1500. uint8_t is_mcast = 0;
  1501. qdf_ether_header_t *eh = NULL;
  1502. qdf_ethervlan_header_t *evh = NULL;
  1503. uint16_t ether_type;
  1504. qdf_llc_t *llcHdr;
  1505. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1506. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1507. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1508. eh = (qdf_ether_header_t *)nbuf->data;
  1509. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1510. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1511. } else {
  1512. qdf_dot3_qosframe_t *qos_wh =
  1513. (qdf_dot3_qosframe_t *) nbuf->data;
  1514. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1515. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1516. return;
  1517. }
  1518. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1519. ether_type = eh->ether_type;
  1520. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1521. /*
  1522. * Check if packet is dot3 or eth2 type.
  1523. */
  1524. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1525. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1526. sizeof(*llcHdr));
  1527. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1528. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1529. sizeof(*llcHdr);
  1530. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1531. + sizeof(*llcHdr) +
  1532. sizeof(qdf_net_vlanhdr_t));
  1533. } else {
  1534. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1535. sizeof(*llcHdr);
  1536. }
  1537. } else {
  1538. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1539. evh = (qdf_ethervlan_header_t *) eh;
  1540. ether_type = evh->ether_type;
  1541. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1542. }
  1543. }
  1544. /*
  1545. * Find priority from IP TOS DSCP field
  1546. */
  1547. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1548. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1549. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1550. /* Only for unicast frames */
  1551. if (!is_mcast) {
  1552. /* send it on VO queue */
  1553. msdu_info->tid = DP_VO_TID;
  1554. }
  1555. } else {
  1556. /*
  1557. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1558. * from TOS byte.
  1559. */
  1560. tos = ip->ip_tos;
  1561. dscp_tid_override = 1;
  1562. }
  1563. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1564. /* TODO
  1565. * use flowlabel
  1566. *igmpmld cases to be handled in phase 2
  1567. */
  1568. unsigned long ver_pri_flowlabel;
  1569. unsigned long pri;
  1570. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1571. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1572. DP_IPV6_PRIORITY_SHIFT;
  1573. tos = pri;
  1574. dscp_tid_override = 1;
  1575. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1576. msdu_info->tid = DP_VO_TID;
  1577. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1578. /* Only for unicast frames */
  1579. if (!is_mcast) {
  1580. /* send ucast arp on VO queue */
  1581. msdu_info->tid = DP_VO_TID;
  1582. }
  1583. }
  1584. /*
  1585. * Assign all MCAST packets to BE
  1586. */
  1587. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1588. if (is_mcast) {
  1589. tos = 0;
  1590. dscp_tid_override = 1;
  1591. }
  1592. }
  1593. if (dscp_tid_override == 1) {
  1594. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1595. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1596. }
  1597. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1598. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1599. return;
  1600. }
  1601. /**
  1602. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1603. * @vdev: DP vdev handle
  1604. * @nbuf: skb
  1605. *
  1606. * Software based TID classification is required when more than 2 DSCP-TID
  1607. * mapping tables are needed.
  1608. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1609. *
  1610. * Return: void
  1611. */
  1612. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1613. struct dp_tx_msdu_info_s *msdu_info)
  1614. {
  1615. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1616. /*
  1617. * skip_sw_tid_classification flag will set in below cases-
  1618. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1619. * 2. hlos_tid_override enabled for vdev
  1620. * 3. mesh mode enabled for vdev
  1621. */
  1622. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1623. /* Update tid in msdu_info from skb priority */
  1624. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1625. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1626. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1627. if (tid == DP_TX_INVALID_QOS_TAG)
  1628. return;
  1629. msdu_info->tid = tid;
  1630. return;
  1631. }
  1632. return;
  1633. }
  1634. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1635. }
  1636. #ifdef FEATURE_WLAN_TDLS
  1637. /**
  1638. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1639. * @soc: datapath SOC
  1640. * @vdev: datapath vdev
  1641. * @tx_desc: TX descriptor
  1642. *
  1643. * Return: None
  1644. */
  1645. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1646. struct dp_vdev *vdev,
  1647. struct dp_tx_desc_s *tx_desc)
  1648. {
  1649. if (vdev) {
  1650. if (vdev->is_tdls_frame) {
  1651. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1652. vdev->is_tdls_frame = false;
  1653. }
  1654. }
  1655. }
  1656. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1657. {
  1658. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1659. switch (soc->arch_id) {
  1660. case CDP_ARCH_TYPE_LI:
  1661. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1662. break;
  1663. case CDP_ARCH_TYPE_BE:
  1664. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1665. break;
  1666. default:
  1667. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1668. QDF_BUG(0);
  1669. }
  1670. return tx_status;
  1671. }
  1672. /**
  1673. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1674. * @soc: dp_soc handle
  1675. * @tx_desc: TX descriptor
  1676. * @vdev: datapath vdev handle
  1677. *
  1678. * Return: None
  1679. */
  1680. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1681. struct dp_tx_desc_s *tx_desc)
  1682. {
  1683. uint8_t tx_status = 0;
  1684. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1685. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1686. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1687. DP_MOD_ID_TDLS);
  1688. if (qdf_unlikely(!vdev)) {
  1689. dp_err_rl("vdev is null!");
  1690. goto error;
  1691. }
  1692. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1693. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1694. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1695. if (vdev->tx_non_std_data_callback.func) {
  1696. qdf_nbuf_set_next(nbuf, NULL);
  1697. vdev->tx_non_std_data_callback.func(
  1698. vdev->tx_non_std_data_callback.ctxt,
  1699. nbuf, tx_status);
  1700. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1701. return;
  1702. } else {
  1703. dp_err_rl("callback func is null");
  1704. }
  1705. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1706. error:
  1707. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1708. qdf_nbuf_free(nbuf);
  1709. }
  1710. /**
  1711. * dp_tx_msdu_single_map() - do nbuf map
  1712. * @vdev: DP vdev handle
  1713. * @tx_desc: DP TX descriptor pointer
  1714. * @nbuf: skb pointer
  1715. *
  1716. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1717. * operation done in other component.
  1718. *
  1719. * Return: QDF_STATUS
  1720. */
  1721. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1722. struct dp_tx_desc_s *tx_desc,
  1723. qdf_nbuf_t nbuf)
  1724. {
  1725. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1726. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1727. nbuf,
  1728. QDF_DMA_TO_DEVICE,
  1729. nbuf->len);
  1730. else
  1731. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1732. QDF_DMA_TO_DEVICE);
  1733. }
  1734. #else
  1735. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1736. struct dp_vdev *vdev,
  1737. struct dp_tx_desc_s *tx_desc)
  1738. {
  1739. }
  1740. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1741. struct dp_tx_desc_s *tx_desc)
  1742. {
  1743. }
  1744. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1745. struct dp_tx_desc_s *tx_desc,
  1746. qdf_nbuf_t nbuf)
  1747. {
  1748. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1749. nbuf,
  1750. QDF_DMA_TO_DEVICE,
  1751. nbuf->len);
  1752. }
  1753. #endif
  1754. static inline
  1755. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1756. struct dp_tx_desc_s *tx_desc,
  1757. qdf_nbuf_t nbuf)
  1758. {
  1759. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1760. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1761. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1762. return 0;
  1763. return qdf_nbuf_mapped_paddr_get(nbuf);
  1764. }
  1765. static inline
  1766. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1767. {
  1768. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1769. desc->nbuf,
  1770. desc->dma_addr,
  1771. QDF_DMA_TO_DEVICE,
  1772. desc->length);
  1773. }
  1774. #ifdef QCA_DP_TX_RMNET_OPTIMIZATION
  1775. static inline bool
  1776. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1777. {
  1778. struct net_device *ingress_dev;
  1779. skb_frag_t *frag;
  1780. uint16_t buf_len = 0;
  1781. uint16_t linear_data_len = 0;
  1782. uint8_t *payload_addr = NULL;
  1783. ingress_dev = dev_get_by_index(dev_net(nbuf->dev), nbuf->skb_iif);
  1784. if ((ingress_dev->priv_flags & IFF_PHONY_HEADROOM)) {
  1785. dev_put(ingress_dev);
  1786. frag = &(skb_shinfo(nbuf)->frags[0]);
  1787. buf_len = skb_frag_size(frag);
  1788. payload_addr = (uint8_t *)skb_frag_address(frag);
  1789. linear_data_len = skb_headlen(nbuf);
  1790. buf_len += linear_data_len;
  1791. payload_addr = payload_addr - linear_data_len;
  1792. memcpy(payload_addr, nbuf->data, linear_data_len);
  1793. msdu_info->frm_type = dp_tx_frm_rmnet;
  1794. msdu_info->buf_len = buf_len;
  1795. msdu_info->payload_addr = payload_addr;
  1796. return true;
  1797. }
  1798. dev_put(ingress_dev);
  1799. return false;
  1800. }
  1801. static inline
  1802. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1803. struct dp_tx_desc_s *tx_desc)
  1804. {
  1805. qdf_dma_addr_t paddr;
  1806. paddr = (qdf_dma_addr_t)qdf_mem_virt_to_phys(msdu_info->payload_addr);
  1807. tx_desc->length = msdu_info->buf_len;
  1808. qdf_nbuf_dma_clean_range((void *)msdu_info->payload_addr,
  1809. (void *)(msdu_info->payload_addr +
  1810. msdu_info->buf_len));
  1811. tx_desc->flags |= DP_TX_DESC_FLAG_RMNET;
  1812. return paddr;
  1813. }
  1814. #else
  1815. static inline bool
  1816. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1817. {
  1818. return false;
  1819. }
  1820. static inline
  1821. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1822. struct dp_tx_desc_s *tx_desc)
  1823. {
  1824. return 0;
  1825. }
  1826. #endif
  1827. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1828. static inline
  1829. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1830. struct dp_tx_desc_s *tx_desc,
  1831. qdf_nbuf_t nbuf)
  1832. {
  1833. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1834. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1835. (void *)(nbuf->data + nbuf->len));
  1836. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1837. } else {
  1838. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1839. }
  1840. }
  1841. static inline
  1842. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1843. struct dp_tx_desc_s *desc)
  1844. {
  1845. if (qdf_unlikely(!(desc->flags &
  1846. (DP_TX_DESC_FLAG_SIMPLE | DP_TX_DESC_FLAG_RMNET))))
  1847. return dp_tx_nbuf_unmap_regular(soc, desc);
  1848. }
  1849. #else
  1850. static inline
  1851. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1852. struct dp_tx_desc_s *tx_desc,
  1853. qdf_nbuf_t nbuf)
  1854. {
  1855. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1856. }
  1857. static inline
  1858. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1859. struct dp_tx_desc_s *desc)
  1860. {
  1861. return dp_tx_nbuf_unmap_regular(soc, desc);
  1862. }
  1863. #endif
  1864. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1865. static inline
  1866. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1867. {
  1868. dp_tx_nbuf_unmap(soc, desc);
  1869. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1870. }
  1871. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1872. {
  1873. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1874. dp_tx_nbuf_unmap(soc, desc);
  1875. }
  1876. #else
  1877. static inline
  1878. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1879. {
  1880. }
  1881. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1882. {
  1883. dp_tx_nbuf_unmap(soc, desc);
  1884. }
  1885. #endif
  1886. #ifdef MESH_MODE_SUPPORT
  1887. /**
  1888. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1889. * @soc: datapath SOC
  1890. * @vdev: datapath vdev
  1891. * @tx_desc: TX descriptor
  1892. *
  1893. * Return: None
  1894. */
  1895. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1896. struct dp_vdev *vdev,
  1897. struct dp_tx_desc_s *tx_desc)
  1898. {
  1899. if (qdf_unlikely(vdev->mesh_vdev))
  1900. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1901. }
  1902. /**
  1903. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1904. * @soc: dp_soc handle
  1905. * @tx_desc: TX descriptor
  1906. * @delayed_free: delay the nbuf free
  1907. *
  1908. * Return: nbuf to be freed late
  1909. */
  1910. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1911. struct dp_tx_desc_s *tx_desc,
  1912. bool delayed_free)
  1913. {
  1914. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1915. struct dp_vdev *vdev = NULL;
  1916. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1917. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1918. if (vdev)
  1919. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1920. if (delayed_free)
  1921. return nbuf;
  1922. qdf_nbuf_free(nbuf);
  1923. } else {
  1924. if (vdev && vdev->osif_tx_free_ext) {
  1925. vdev->osif_tx_free_ext((nbuf));
  1926. } else {
  1927. if (delayed_free)
  1928. return nbuf;
  1929. qdf_nbuf_free(nbuf);
  1930. }
  1931. }
  1932. if (vdev)
  1933. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1934. return NULL;
  1935. }
  1936. #else
  1937. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1938. struct dp_vdev *vdev,
  1939. struct dp_tx_desc_s *tx_desc)
  1940. {
  1941. }
  1942. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1943. struct dp_tx_desc_s *tx_desc,
  1944. bool delayed_free)
  1945. {
  1946. return NULL;
  1947. }
  1948. #endif
  1949. /**
  1950. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1951. * @vdev: DP vdev handle
  1952. * @nbuf: skb
  1953. *
  1954. * Return: 1 if frame needs to be dropped else 0
  1955. */
  1956. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1957. {
  1958. struct dp_pdev *pdev = NULL;
  1959. struct dp_ast_entry *src_ast_entry = NULL;
  1960. struct dp_ast_entry *dst_ast_entry = NULL;
  1961. struct dp_soc *soc = NULL;
  1962. qdf_assert(vdev);
  1963. pdev = vdev->pdev;
  1964. qdf_assert(pdev);
  1965. soc = pdev->soc;
  1966. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1967. (soc, dstmac, vdev->pdev->pdev_id);
  1968. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1969. (soc, srcmac, vdev->pdev->pdev_id);
  1970. if (dst_ast_entry && src_ast_entry) {
  1971. if (dst_ast_entry->peer_id ==
  1972. src_ast_entry->peer_id)
  1973. return 1;
  1974. }
  1975. return 0;
  1976. }
  1977. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1978. defined(WLAN_MCAST_MLO)
  1979. /* MLO peer id for reinject*/
  1980. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1981. /* MLO vdev id inc offset */
  1982. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1983. static inline void
  1984. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1985. {
  1986. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1987. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1988. qdf_atomic_inc(&soc->num_tx_exception);
  1989. }
  1990. }
  1991. static inline void
  1992. dp_tx_update_mcast_param(uint16_t peer_id,
  1993. uint16_t *htt_tcl_metadata,
  1994. struct dp_vdev *vdev,
  1995. struct dp_tx_msdu_info_s *msdu_info)
  1996. {
  1997. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1998. *htt_tcl_metadata = 0;
  1999. DP_TX_TCL_METADATA_TYPE_SET(
  2000. *htt_tcl_metadata,
  2001. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  2002. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  2003. msdu_info->gsn);
  2004. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  2005. if (qdf_unlikely(vdev->nawds_enabled))
  2006. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2007. *htt_tcl_metadata, 1);
  2008. } else {
  2009. msdu_info->vdev_id = vdev->vdev_id;
  2010. }
  2011. }
  2012. #else
  2013. static inline void
  2014. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2015. {
  2016. }
  2017. static inline void
  2018. dp_tx_update_mcast_param(uint16_t peer_id,
  2019. uint16_t *htt_tcl_metadata,
  2020. struct dp_vdev *vdev,
  2021. struct dp_tx_msdu_info_s *msdu_info)
  2022. {
  2023. }
  2024. #endif
  2025. #ifdef DP_TX_SW_DROP_STATS_INC
  2026. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2027. qdf_nbuf_t nbuf,
  2028. enum cdp_tx_sw_drop drop_code)
  2029. {
  2030. /* EAPOL Drop stats */
  2031. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  2032. switch (drop_code) {
  2033. case TX_DESC_ERR:
  2034. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  2035. break;
  2036. case TX_HAL_RING_ACCESS_ERR:
  2037. DP_STATS_INC(pdev,
  2038. eap_drop_stats.tx_hal_ring_access_err, 1);
  2039. break;
  2040. case TX_DMA_MAP_ERR:
  2041. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  2042. break;
  2043. case TX_HW_ENQUEUE:
  2044. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  2045. break;
  2046. case TX_SW_ENQUEUE:
  2047. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  2048. break;
  2049. default:
  2050. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  2051. break;
  2052. }
  2053. }
  2054. }
  2055. #else
  2056. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2057. qdf_nbuf_t nbuf,
  2058. enum cdp_tx_sw_drop drop_code)
  2059. {
  2060. }
  2061. #endif
  2062. /**
  2063. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  2064. * @vdev: DP vdev handle
  2065. * @nbuf: skb
  2066. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  2067. * @meta_data: Metadata to the fw
  2068. * @tx_q: Tx queue to be used for this Tx frame
  2069. * @peer_id: peer_id of the peer in case of NAWDS frames
  2070. * @tx_exc_metadata: Handle that holds exception path metadata
  2071. *
  2072. * Return: NULL on success,
  2073. * nbuf when it fails to send
  2074. */
  2075. qdf_nbuf_t
  2076. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2077. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2078. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2079. {
  2080. struct dp_pdev *pdev = vdev->pdev;
  2081. struct dp_soc *soc = pdev->soc;
  2082. struct dp_tx_desc_s *tx_desc;
  2083. QDF_STATUS status;
  2084. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2085. uint16_t htt_tcl_metadata = 0;
  2086. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2087. uint8_t tid = msdu_info->tid;
  2088. struct cdp_tid_tx_stats *tid_stats = NULL;
  2089. qdf_dma_addr_t paddr;
  2090. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2091. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2092. msdu_info, tx_exc_metadata);
  2093. if (!tx_desc) {
  2094. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2095. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2096. drop_code = TX_DESC_ERR;
  2097. goto fail_return;
  2098. }
  2099. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2100. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2101. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2102. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2103. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2104. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2105. DP_TCL_METADATA_TYPE_PEER_BASED);
  2106. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2107. peer_id);
  2108. dp_tx_bypass_reinjection(soc, tx_desc);
  2109. } else
  2110. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2111. if (msdu_info->exception_fw)
  2112. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2113. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2114. !pdev->enhanced_stats_en);
  2115. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2116. if (qdf_unlikely(msdu_info->frm_type == dp_tx_frm_rmnet))
  2117. paddr = dp_tx_rmnet_nbuf_map(msdu_info, tx_desc);
  2118. else
  2119. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2120. if (!paddr) {
  2121. /* Handle failure */
  2122. dp_err("qdf_nbuf_map failed");
  2123. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2124. drop_code = TX_DMA_MAP_ERR;
  2125. goto release_desc;
  2126. }
  2127. tx_desc->dma_addr = paddr;
  2128. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2129. tx_desc->id, DP_TX_DESC_MAP);
  2130. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2131. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2132. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2133. htt_tcl_metadata,
  2134. tx_exc_metadata, msdu_info);
  2135. if (status != QDF_STATUS_SUCCESS) {
  2136. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2137. tx_desc, tx_q->ring_id);
  2138. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2139. tx_desc->id, DP_TX_DESC_UNMAP);
  2140. dp_tx_nbuf_unmap(soc, tx_desc);
  2141. drop_code = TX_HW_ENQUEUE;
  2142. goto release_desc;
  2143. }
  2144. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2145. return NULL;
  2146. release_desc:
  2147. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2148. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2149. fail_return:
  2150. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2151. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2152. tid_stats = &pdev->stats.tid_stats.
  2153. tid_tx_stats[tx_q->ring_id][tid];
  2154. tid_stats->swdrop_cnt[drop_code]++;
  2155. return nbuf;
  2156. }
  2157. /**
  2158. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2159. * @soc: Soc handle
  2160. * @desc: software Tx descriptor to be processed
  2161. * @delayed_free: defer freeing of nbuf
  2162. *
  2163. * Return: nbuf to be freed later
  2164. */
  2165. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2166. bool delayed_free)
  2167. {
  2168. qdf_nbuf_t nbuf = desc->nbuf;
  2169. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2170. /* nbuf already freed in vdev detach path */
  2171. if (!nbuf)
  2172. return NULL;
  2173. /* If it is TDLS mgmt, don't unmap or free the frame */
  2174. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2175. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2176. return NULL;
  2177. }
  2178. /* 0 : MSDU buffer, 1 : MLE */
  2179. if (desc->msdu_ext_desc) {
  2180. /* TSO free */
  2181. if (hal_tx_ext_desc_get_tso_enable(
  2182. desc->msdu_ext_desc->vaddr)) {
  2183. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2184. desc->id, DP_TX_COMP_MSDU_EXT);
  2185. dp_tx_tso_seg_history_add(soc,
  2186. desc->msdu_ext_desc->tso_desc,
  2187. desc->nbuf, desc->id, type);
  2188. /* unmap eash TSO seg before free the nbuf */
  2189. dp_tx_tso_unmap_segment(soc,
  2190. desc->msdu_ext_desc->tso_desc,
  2191. desc->msdu_ext_desc->
  2192. tso_num_desc);
  2193. goto nbuf_free;
  2194. }
  2195. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2196. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2197. qdf_dma_addr_t iova;
  2198. uint32_t frag_len;
  2199. uint32_t i;
  2200. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2201. QDF_DMA_TO_DEVICE,
  2202. qdf_nbuf_headlen(nbuf));
  2203. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2204. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2205. &iova,
  2206. &frag_len);
  2207. if (!iova || !frag_len)
  2208. break;
  2209. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2210. QDF_DMA_TO_DEVICE);
  2211. }
  2212. goto nbuf_free;
  2213. }
  2214. }
  2215. /* If it's ME frame, dont unmap the cloned nbuf's */
  2216. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2217. goto nbuf_free;
  2218. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2219. dp_tx_unmap(soc, desc);
  2220. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2221. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2222. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2223. return NULL;
  2224. nbuf_free:
  2225. if (delayed_free)
  2226. return nbuf;
  2227. qdf_nbuf_free(nbuf);
  2228. return NULL;
  2229. }
  2230. /**
  2231. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2232. * @soc: DP soc handle
  2233. * @nbuf: skb
  2234. * @msdu_info: MSDU info
  2235. *
  2236. * Return: None
  2237. */
  2238. static inline void
  2239. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2240. struct dp_tx_msdu_info_s *msdu_info)
  2241. {
  2242. uint32_t cur_idx;
  2243. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2244. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2245. qdf_nbuf_headlen(nbuf));
  2246. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2247. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2248. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2249. seg->frags[cur_idx].paddr_hi) << 32),
  2250. seg->frags[cur_idx].len,
  2251. QDF_DMA_TO_DEVICE);
  2252. }
  2253. /**
  2254. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2255. * @vdev: DP vdev handle
  2256. * @nbuf: skb
  2257. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2258. *
  2259. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2260. *
  2261. * Return: NULL on success,
  2262. * nbuf when it fails to send
  2263. */
  2264. #if QDF_LOCK_STATS
  2265. noinline
  2266. #else
  2267. #endif
  2268. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2269. struct dp_tx_msdu_info_s *msdu_info)
  2270. {
  2271. uint32_t i;
  2272. struct dp_pdev *pdev = vdev->pdev;
  2273. struct dp_soc *soc = pdev->soc;
  2274. struct dp_tx_desc_s *tx_desc;
  2275. bool is_cce_classified = false;
  2276. QDF_STATUS status;
  2277. uint16_t htt_tcl_metadata = 0;
  2278. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2279. struct cdp_tid_tx_stats *tid_stats = NULL;
  2280. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2281. if (msdu_info->frm_type == dp_tx_frm_me)
  2282. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2283. i = 0;
  2284. /* Print statement to track i and num_seg */
  2285. /*
  2286. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2287. * descriptors using information in msdu_info
  2288. */
  2289. while (i < msdu_info->num_seg) {
  2290. /*
  2291. * Setup Tx descriptor for an MSDU, and MSDU extension
  2292. * descriptor
  2293. */
  2294. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2295. tx_q->desc_pool_id);
  2296. if (!tx_desc) {
  2297. if (msdu_info->frm_type == dp_tx_frm_me) {
  2298. prep_desc_fail++;
  2299. dp_tx_me_free_buf(pdev,
  2300. (void *)(msdu_info->u.sg_info
  2301. .curr_seg->frags[0].vaddr));
  2302. if (prep_desc_fail == msdu_info->num_seg) {
  2303. /*
  2304. * Unmap is needed only if descriptor
  2305. * preparation failed for all segments.
  2306. */
  2307. qdf_nbuf_unmap(soc->osdev,
  2308. msdu_info->u.sg_info.
  2309. curr_seg->nbuf,
  2310. QDF_DMA_TO_DEVICE);
  2311. }
  2312. /*
  2313. * Free the nbuf for the current segment
  2314. * and make it point to the next in the list.
  2315. * For me, there are as many segments as there
  2316. * are no of clients.
  2317. */
  2318. qdf_nbuf_free(msdu_info->u.sg_info
  2319. .curr_seg->nbuf);
  2320. if (msdu_info->u.sg_info.curr_seg->next) {
  2321. msdu_info->u.sg_info.curr_seg =
  2322. msdu_info->u.sg_info
  2323. .curr_seg->next;
  2324. nbuf = msdu_info->u.sg_info
  2325. .curr_seg->nbuf;
  2326. }
  2327. i++;
  2328. continue;
  2329. }
  2330. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2331. dp_tx_tso_seg_history_add(
  2332. soc,
  2333. msdu_info->u.tso_info.curr_seg,
  2334. nbuf, 0, DP_TX_DESC_UNMAP);
  2335. dp_tx_tso_unmap_segment(soc,
  2336. msdu_info->u.tso_info.
  2337. curr_seg,
  2338. msdu_info->u.tso_info.
  2339. tso_num_seg_list);
  2340. if (msdu_info->u.tso_info.curr_seg->next) {
  2341. msdu_info->u.tso_info.curr_seg =
  2342. msdu_info->u.tso_info.curr_seg->next;
  2343. i++;
  2344. continue;
  2345. }
  2346. }
  2347. if (msdu_info->frm_type == dp_tx_frm_sg)
  2348. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2349. goto done;
  2350. }
  2351. if (msdu_info->frm_type == dp_tx_frm_me) {
  2352. tx_desc->msdu_ext_desc->me_buffer =
  2353. (struct dp_tx_me_buf_t *)msdu_info->
  2354. u.sg_info.curr_seg->frags[0].vaddr;
  2355. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2356. }
  2357. if (is_cce_classified)
  2358. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2359. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2360. if (msdu_info->exception_fw) {
  2361. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2362. }
  2363. dp_tx_is_hp_update_required(i, msdu_info);
  2364. /*
  2365. * For frames with multiple segments (TSO, ME), jump to next
  2366. * segment.
  2367. */
  2368. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2369. if (msdu_info->u.tso_info.curr_seg->next) {
  2370. msdu_info->u.tso_info.curr_seg =
  2371. msdu_info->u.tso_info.curr_seg->next;
  2372. /*
  2373. * If this is a jumbo nbuf, then increment the
  2374. * number of nbuf users for each additional
  2375. * segment of the msdu. This will ensure that
  2376. * the skb is freed only after receiving tx
  2377. * completion for all segments of an nbuf
  2378. */
  2379. qdf_nbuf_inc_users(nbuf);
  2380. /* Check with MCL if this is needed */
  2381. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2382. */
  2383. }
  2384. }
  2385. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2386. &htt_tcl_metadata,
  2387. vdev,
  2388. msdu_info);
  2389. /*
  2390. * Enqueue the Tx MSDU descriptor to HW for transmit
  2391. */
  2392. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2393. htt_tcl_metadata,
  2394. NULL, msdu_info);
  2395. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2396. if (status != QDF_STATUS_SUCCESS) {
  2397. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2398. tx_desc, tx_q->ring_id);
  2399. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2400. tid_stats = &pdev->stats.tid_stats.
  2401. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2402. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2403. if (msdu_info->frm_type == dp_tx_frm_me) {
  2404. hw_enq_fail++;
  2405. if (hw_enq_fail == msdu_info->num_seg) {
  2406. /*
  2407. * Unmap is needed only if enqueue
  2408. * failed for all segments.
  2409. */
  2410. qdf_nbuf_unmap(soc->osdev,
  2411. msdu_info->u.sg_info.
  2412. curr_seg->nbuf,
  2413. QDF_DMA_TO_DEVICE);
  2414. }
  2415. /*
  2416. * Free the nbuf for the current segment
  2417. * and make it point to the next in the list.
  2418. * For me, there are as many segments as there
  2419. * are no of clients.
  2420. */
  2421. qdf_nbuf_free(msdu_info->u.sg_info
  2422. .curr_seg->nbuf);
  2423. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2424. if (msdu_info->u.sg_info.curr_seg->next) {
  2425. msdu_info->u.sg_info.curr_seg =
  2426. msdu_info->u.sg_info
  2427. .curr_seg->next;
  2428. nbuf = msdu_info->u.sg_info
  2429. .curr_seg->nbuf;
  2430. } else
  2431. break;
  2432. i++;
  2433. continue;
  2434. }
  2435. /*
  2436. * For TSO frames, the nbuf users increment done for
  2437. * the current segment has to be reverted, since the
  2438. * hw enqueue for this segment failed
  2439. */
  2440. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2441. msdu_info->u.tso_info.curr_seg) {
  2442. /*
  2443. * unmap and free current,
  2444. * retransmit remaining segments
  2445. */
  2446. dp_tx_comp_free_buf(soc, tx_desc, false);
  2447. i++;
  2448. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2449. continue;
  2450. }
  2451. if (msdu_info->frm_type == dp_tx_frm_sg)
  2452. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2453. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2454. goto done;
  2455. }
  2456. /*
  2457. * TODO
  2458. * if tso_info structure can be modified to have curr_seg
  2459. * as first element, following 2 blocks of code (for TSO and SG)
  2460. * can be combined into 1
  2461. */
  2462. /*
  2463. * For Multicast-Unicast converted packets,
  2464. * each converted frame (for a client) is represented as
  2465. * 1 segment
  2466. */
  2467. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2468. (msdu_info->frm_type == dp_tx_frm_me)) {
  2469. if (msdu_info->u.sg_info.curr_seg->next) {
  2470. msdu_info->u.sg_info.curr_seg =
  2471. msdu_info->u.sg_info.curr_seg->next;
  2472. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2473. } else
  2474. break;
  2475. }
  2476. i++;
  2477. }
  2478. nbuf = NULL;
  2479. done:
  2480. return nbuf;
  2481. }
  2482. /**
  2483. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2484. * for SG frames
  2485. * @vdev: DP vdev handle
  2486. * @nbuf: skb
  2487. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2488. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2489. *
  2490. * Return: NULL on success,
  2491. * nbuf when it fails to send
  2492. */
  2493. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2494. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2495. {
  2496. uint32_t cur_frag, nr_frags, i;
  2497. qdf_dma_addr_t paddr;
  2498. struct dp_tx_sg_info_s *sg_info;
  2499. sg_info = &msdu_info->u.sg_info;
  2500. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2501. if (QDF_STATUS_SUCCESS !=
  2502. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2503. QDF_DMA_TO_DEVICE,
  2504. qdf_nbuf_headlen(nbuf))) {
  2505. dp_tx_err("dma map error");
  2506. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2507. qdf_nbuf_free(nbuf);
  2508. return NULL;
  2509. }
  2510. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2511. seg_info->frags[0].paddr_lo = paddr;
  2512. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2513. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2514. seg_info->frags[0].vaddr = (void *) nbuf;
  2515. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2516. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2517. nbuf, 0,
  2518. QDF_DMA_TO_DEVICE,
  2519. cur_frag)) {
  2520. dp_tx_err("frag dma map error");
  2521. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2522. goto map_err;
  2523. }
  2524. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2525. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2526. seg_info->frags[cur_frag + 1].paddr_hi =
  2527. ((uint64_t) paddr) >> 32;
  2528. seg_info->frags[cur_frag + 1].len =
  2529. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2530. }
  2531. seg_info->frag_cnt = (cur_frag + 1);
  2532. seg_info->total_len = qdf_nbuf_len(nbuf);
  2533. seg_info->next = NULL;
  2534. sg_info->curr_seg = seg_info;
  2535. msdu_info->frm_type = dp_tx_frm_sg;
  2536. msdu_info->num_seg = 1;
  2537. return nbuf;
  2538. map_err:
  2539. /* restore paddr into nbuf before calling unmap */
  2540. qdf_nbuf_mapped_paddr_set(nbuf,
  2541. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2542. ((uint64_t)
  2543. seg_info->frags[0].paddr_hi) << 32));
  2544. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2545. QDF_DMA_TO_DEVICE,
  2546. seg_info->frags[0].len);
  2547. for (i = 1; i <= cur_frag; i++) {
  2548. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2549. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2550. seg_info->frags[i].paddr_hi) << 32),
  2551. seg_info->frags[i].len,
  2552. QDF_DMA_TO_DEVICE);
  2553. }
  2554. qdf_nbuf_free(nbuf);
  2555. return NULL;
  2556. }
  2557. /**
  2558. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2559. * @vdev: DP vdev handle
  2560. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2561. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2562. *
  2563. * Return: NULL on failure,
  2564. * nbuf when extracted successfully
  2565. */
  2566. static
  2567. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2568. struct dp_tx_msdu_info_s *msdu_info,
  2569. uint16_t ppdu_cookie)
  2570. {
  2571. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2572. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2573. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2574. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2575. (msdu_info->meta_data[5], 1);
  2576. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2577. (msdu_info->meta_data[5], 1);
  2578. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2579. (msdu_info->meta_data[6], ppdu_cookie);
  2580. msdu_info->exception_fw = 1;
  2581. msdu_info->is_tx_sniffer = 1;
  2582. }
  2583. #ifdef MESH_MODE_SUPPORT
  2584. /**
  2585. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2586. and prepare msdu_info for mesh frames.
  2587. * @vdev: DP vdev handle
  2588. * @nbuf: skb
  2589. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2590. *
  2591. * Return: NULL on failure,
  2592. * nbuf when extracted successfully
  2593. */
  2594. static
  2595. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2596. struct dp_tx_msdu_info_s *msdu_info)
  2597. {
  2598. struct meta_hdr_s *mhdr;
  2599. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2600. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2601. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2602. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2603. msdu_info->exception_fw = 0;
  2604. goto remove_meta_hdr;
  2605. }
  2606. msdu_info->exception_fw = 1;
  2607. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2608. meta_data->host_tx_desc_pool = 1;
  2609. meta_data->update_peer_cache = 1;
  2610. meta_data->learning_frame = 1;
  2611. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2612. meta_data->power = mhdr->power;
  2613. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2614. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2615. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2616. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2617. meta_data->dyn_bw = 1;
  2618. meta_data->valid_pwr = 1;
  2619. meta_data->valid_mcs_mask = 1;
  2620. meta_data->valid_nss_mask = 1;
  2621. meta_data->valid_preamble_type = 1;
  2622. meta_data->valid_retries = 1;
  2623. meta_data->valid_bw_info = 1;
  2624. }
  2625. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2626. meta_data->encrypt_type = 0;
  2627. meta_data->valid_encrypt_type = 1;
  2628. meta_data->learning_frame = 0;
  2629. }
  2630. meta_data->valid_key_flags = 1;
  2631. meta_data->key_flags = (mhdr->keyix & 0x3);
  2632. remove_meta_hdr:
  2633. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2634. dp_tx_err("qdf_nbuf_pull_head failed");
  2635. qdf_nbuf_free(nbuf);
  2636. return NULL;
  2637. }
  2638. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2639. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2640. " tid %d to_fw %d",
  2641. msdu_info->meta_data[0],
  2642. msdu_info->meta_data[1],
  2643. msdu_info->meta_data[2],
  2644. msdu_info->meta_data[3],
  2645. msdu_info->meta_data[4],
  2646. msdu_info->meta_data[5],
  2647. msdu_info->tid, msdu_info->exception_fw);
  2648. return nbuf;
  2649. }
  2650. #else
  2651. static
  2652. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2653. struct dp_tx_msdu_info_s *msdu_info)
  2654. {
  2655. return nbuf;
  2656. }
  2657. #endif
  2658. /**
  2659. * dp_check_exc_metadata() - Checks if parameters are valid
  2660. * @tx_exc - holds all exception path parameters
  2661. *
  2662. * Returns true when all the parameters are valid else false
  2663. *
  2664. */
  2665. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2666. {
  2667. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2668. HTT_INVALID_TID);
  2669. bool invalid_encap_type =
  2670. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2671. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2672. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2673. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2674. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2675. tx_exc->ppdu_cookie == 0);
  2676. if (tx_exc->is_intrabss_fwd)
  2677. return true;
  2678. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2679. invalid_cookie) {
  2680. return false;
  2681. }
  2682. return true;
  2683. }
  2684. #ifdef ATH_SUPPORT_IQUE
  2685. /**
  2686. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2687. * @vdev: vdev handle
  2688. * @nbuf: skb
  2689. *
  2690. * Return: true on success,
  2691. * false on failure
  2692. */
  2693. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2694. {
  2695. qdf_ether_header_t *eh;
  2696. /* Mcast to Ucast Conversion*/
  2697. if (qdf_likely(!vdev->mcast_enhancement_en))
  2698. return true;
  2699. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2700. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2701. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2702. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2703. qdf_nbuf_set_next(nbuf, NULL);
  2704. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2705. qdf_nbuf_len(nbuf));
  2706. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2707. QDF_STATUS_SUCCESS) {
  2708. return false;
  2709. }
  2710. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2711. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2712. QDF_STATUS_SUCCESS) {
  2713. return false;
  2714. }
  2715. }
  2716. }
  2717. return true;
  2718. }
  2719. #else
  2720. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2721. {
  2722. return true;
  2723. }
  2724. #endif
  2725. #ifdef QCA_SUPPORT_WDS_EXTENDED
  2726. /**
  2727. * dp_tx_mcast_drop() - Drop mcast frame if drop_tx_mcast is set in WDS_EXT
  2728. * @vdev: vdev handle
  2729. * @nbuf: skb
  2730. *
  2731. * Return: true if frame is dropped, false otherwise
  2732. */
  2733. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2734. {
  2735. /* Drop tx mcast and WDS Extended feature check */
  2736. if (qdf_unlikely((vdev->drop_tx_mcast) && (vdev->wds_ext_enabled))) {
  2737. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2738. qdf_nbuf_data(nbuf);
  2739. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  2740. DP_STATS_INC(vdev, tx_i.dropped.tx_mcast_drop, 1);
  2741. return true;
  2742. }
  2743. }
  2744. return false;
  2745. }
  2746. #else
  2747. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2748. {
  2749. return false;
  2750. }
  2751. #endif
  2752. /**
  2753. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2754. * @nbuf: qdf_nbuf_t
  2755. * @vdev: struct dp_vdev *
  2756. *
  2757. * Allow packet for processing only if it is for peer client which is
  2758. * connected with same vap. Drop packet if client is connected to
  2759. * different vap.
  2760. *
  2761. * Return: QDF_STATUS
  2762. */
  2763. static inline QDF_STATUS
  2764. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2765. {
  2766. struct dp_ast_entry *dst_ast_entry = NULL;
  2767. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2768. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2769. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2770. return QDF_STATUS_SUCCESS;
  2771. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2772. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2773. eh->ether_dhost,
  2774. vdev->vdev_id);
  2775. /* If there is no ast entry, return failure */
  2776. if (qdf_unlikely(!dst_ast_entry)) {
  2777. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2778. return QDF_STATUS_E_FAILURE;
  2779. }
  2780. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2781. return QDF_STATUS_SUCCESS;
  2782. }
  2783. /**
  2784. * dp_tx_nawds_handler() - NAWDS handler
  2785. *
  2786. * @soc: DP soc handle
  2787. * @vdev_id: id of DP vdev handle
  2788. * @msdu_info: msdu_info required to create HTT metadata
  2789. * @nbuf: skb
  2790. *
  2791. * This API transfers the multicast frames with the peer id
  2792. * on NAWDS enabled peer.
  2793. * Return: none
  2794. */
  2795. static inline
  2796. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2797. struct dp_tx_msdu_info_s *msdu_info,
  2798. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2799. {
  2800. struct dp_peer *peer = NULL;
  2801. qdf_nbuf_t nbuf_clone = NULL;
  2802. uint16_t peer_id = DP_INVALID_PEER;
  2803. struct dp_txrx_peer *txrx_peer;
  2804. /* This check avoids pkt forwarding which is entered
  2805. * in the ast table but still doesn't have valid peerid.
  2806. */
  2807. if (sa_peer_id == HTT_INVALID_PEER)
  2808. return;
  2809. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2810. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2811. txrx_peer = dp_get_txrx_peer(peer);
  2812. if (!txrx_peer)
  2813. continue;
  2814. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2815. peer_id = peer->peer_id;
  2816. if (!dp_peer_is_primary_link_peer(peer))
  2817. continue;
  2818. /* Multicast packets needs to be
  2819. * dropped in case of intra bss forwarding
  2820. */
  2821. if (sa_peer_id == txrx_peer->peer_id) {
  2822. dp_tx_debug("multicast packet");
  2823. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2824. tx.nawds_mcast_drop,
  2825. 1);
  2826. continue;
  2827. }
  2828. nbuf_clone = qdf_nbuf_clone(nbuf);
  2829. if (!nbuf_clone) {
  2830. QDF_TRACE(QDF_MODULE_ID_DP,
  2831. QDF_TRACE_LEVEL_ERROR,
  2832. FL("nbuf clone failed"));
  2833. break;
  2834. }
  2835. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2836. msdu_info, peer_id,
  2837. NULL);
  2838. if (nbuf_clone) {
  2839. dp_tx_debug("pkt send failed");
  2840. qdf_nbuf_free(nbuf_clone);
  2841. } else {
  2842. if (peer_id != DP_INVALID_PEER)
  2843. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2844. tx.nawds_mcast,
  2845. 1, qdf_nbuf_len(nbuf));
  2846. }
  2847. }
  2848. }
  2849. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2850. }
  2851. /**
  2852. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2853. * @soc: DP soc handle
  2854. * @vdev_id: id of DP vdev handle
  2855. * @nbuf: skb
  2856. * @tx_exc_metadata: Handle that holds exception path meta data
  2857. *
  2858. * Entry point for Core Tx layer (DP_TX) invoked from
  2859. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2860. *
  2861. * Return: NULL on success,
  2862. * nbuf when it fails to send
  2863. */
  2864. qdf_nbuf_t
  2865. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2866. qdf_nbuf_t nbuf,
  2867. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2868. {
  2869. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2870. qdf_ether_header_t *eh = NULL;
  2871. struct dp_tx_msdu_info_s msdu_info;
  2872. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2873. DP_MOD_ID_TX_EXCEPTION);
  2874. if (qdf_unlikely(!vdev))
  2875. goto fail;
  2876. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2877. if (!tx_exc_metadata)
  2878. goto fail;
  2879. msdu_info.tid = tx_exc_metadata->tid;
  2880. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2881. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2882. QDF_MAC_ADDR_REF(nbuf->data));
  2883. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2884. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2885. dp_tx_err("Invalid parameters in exception path");
  2886. goto fail;
  2887. }
  2888. /* for peer based metadata check if peer is valid */
  2889. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2890. struct dp_peer *peer = NULL;
  2891. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2892. tx_exc_metadata->peer_id,
  2893. DP_MOD_ID_TX_EXCEPTION);
  2894. if (qdf_unlikely(!peer)) {
  2895. DP_STATS_INC(vdev,
  2896. tx_i.dropped.invalid_peer_id_in_exc_path,
  2897. 1);
  2898. goto fail;
  2899. }
  2900. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2901. }
  2902. /* Basic sanity checks for unsupported packets */
  2903. /* MESH mode */
  2904. if (qdf_unlikely(vdev->mesh_vdev)) {
  2905. dp_tx_err("Mesh mode is not supported in exception path");
  2906. goto fail;
  2907. }
  2908. /*
  2909. * Classify the frame and call corresponding
  2910. * "prepare" function which extracts the segment (TSO)
  2911. * and fragmentation information (for TSO , SG, ME, or Raw)
  2912. * into MSDU_INFO structure which is later used to fill
  2913. * SW and HW descriptors.
  2914. */
  2915. if (qdf_nbuf_is_tso(nbuf)) {
  2916. dp_verbose_debug("TSO frame %pK", vdev);
  2917. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2918. qdf_nbuf_len(nbuf));
  2919. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2920. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2921. qdf_nbuf_len(nbuf));
  2922. goto fail;
  2923. }
  2924. goto send_multiple;
  2925. }
  2926. /* SG */
  2927. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2928. struct dp_tx_seg_info_s seg_info = {0};
  2929. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2930. if (!nbuf)
  2931. goto fail;
  2932. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2933. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2934. qdf_nbuf_len(nbuf));
  2935. goto send_multiple;
  2936. }
  2937. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2938. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2939. qdf_nbuf_len(nbuf));
  2940. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2941. tx_exc_metadata->ppdu_cookie);
  2942. }
  2943. /*
  2944. * Get HW Queue to use for this frame.
  2945. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2946. * dedicated for data and 1 for command.
  2947. * "queue_id" maps to one hardware ring.
  2948. * With each ring, we also associate a unique Tx descriptor pool
  2949. * to minimize lock contention for these resources.
  2950. */
  2951. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2952. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2953. if (qdf_unlikely(vdev->nawds_enabled)) {
  2954. /*
  2955. * This is a multicast packet
  2956. */
  2957. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2958. tx_exc_metadata->peer_id);
  2959. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2960. 1, qdf_nbuf_len(nbuf));
  2961. }
  2962. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2963. DP_INVALID_PEER, NULL);
  2964. } else {
  2965. /*
  2966. * Check exception descriptors
  2967. */
  2968. if (dp_tx_exception_limit_check(vdev))
  2969. goto fail;
  2970. /* Single linear frame */
  2971. /*
  2972. * If nbuf is a simple linear frame, use send_single function to
  2973. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2974. * SRNG. There is no need to setup a MSDU extension descriptor.
  2975. */
  2976. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2977. tx_exc_metadata->peer_id,
  2978. tx_exc_metadata);
  2979. }
  2980. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2981. return nbuf;
  2982. send_multiple:
  2983. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2984. fail:
  2985. if (vdev)
  2986. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2987. dp_verbose_debug("pkt send failed");
  2988. return nbuf;
  2989. }
  2990. /**
  2991. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2992. * in exception path in special case to avoid regular exception path chk.
  2993. * @soc: DP soc handle
  2994. * @vdev_id: id of DP vdev handle
  2995. * @nbuf: skb
  2996. * @tx_exc_metadata: Handle that holds exception path meta data
  2997. *
  2998. * Entry point for Core Tx layer (DP_TX) invoked from
  2999. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  3000. *
  3001. * Return: NULL on success,
  3002. * nbuf when it fails to send
  3003. */
  3004. qdf_nbuf_t
  3005. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3006. uint8_t vdev_id, qdf_nbuf_t nbuf,
  3007. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3008. {
  3009. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3010. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3011. DP_MOD_ID_TX_EXCEPTION);
  3012. if (qdf_unlikely(!vdev))
  3013. goto fail;
  3014. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3015. == QDF_STATUS_E_FAILURE)) {
  3016. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3017. goto fail;
  3018. }
  3019. /* Unref count as it will again be taken inside dp_tx_exception */
  3020. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3021. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  3022. fail:
  3023. if (vdev)
  3024. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3025. dp_verbose_debug("pkt send failed");
  3026. return nbuf;
  3027. }
  3028. /**
  3029. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  3030. * @soc: DP soc handle
  3031. * @vdev_id: DP vdev handle
  3032. * @nbuf: skb
  3033. *
  3034. * Entry point for Core Tx layer (DP_TX) invoked from
  3035. * hard_start_xmit in OSIF/HDD
  3036. *
  3037. * Return: NULL on success,
  3038. * nbuf when it fails to send
  3039. */
  3040. #ifdef MESH_MODE_SUPPORT
  3041. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3042. qdf_nbuf_t nbuf)
  3043. {
  3044. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3045. struct meta_hdr_s *mhdr;
  3046. qdf_nbuf_t nbuf_mesh = NULL;
  3047. qdf_nbuf_t nbuf_clone = NULL;
  3048. struct dp_vdev *vdev;
  3049. uint8_t no_enc_frame = 0;
  3050. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3051. if (!nbuf_mesh) {
  3052. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3053. "qdf_nbuf_unshare failed");
  3054. return nbuf;
  3055. }
  3056. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3057. if (!vdev) {
  3058. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3059. "vdev is NULL for vdev_id %d", vdev_id);
  3060. return nbuf;
  3061. }
  3062. nbuf = nbuf_mesh;
  3063. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3064. if ((vdev->sec_type != cdp_sec_type_none) &&
  3065. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3066. no_enc_frame = 1;
  3067. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3068. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3069. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3070. !no_enc_frame) {
  3071. nbuf_clone = qdf_nbuf_clone(nbuf);
  3072. if (!nbuf_clone) {
  3073. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3074. "qdf_nbuf_clone failed");
  3075. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3076. return nbuf;
  3077. }
  3078. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3079. }
  3080. if (nbuf_clone) {
  3081. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3082. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3083. } else {
  3084. qdf_nbuf_free(nbuf_clone);
  3085. }
  3086. }
  3087. if (no_enc_frame)
  3088. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3089. else
  3090. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3091. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3092. if ((!nbuf) && no_enc_frame) {
  3093. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3094. }
  3095. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3096. return nbuf;
  3097. }
  3098. #else
  3099. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  3100. qdf_nbuf_t nbuf)
  3101. {
  3102. return dp_tx_send(soc, vdev_id, nbuf);
  3103. }
  3104. #endif
  3105. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3106. static inline
  3107. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3108. {
  3109. if (nbuf) {
  3110. qdf_prefetch(&nbuf->len);
  3111. qdf_prefetch(&nbuf->data);
  3112. }
  3113. }
  3114. #else
  3115. static inline
  3116. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3117. {
  3118. }
  3119. #endif
  3120. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3121. /*
  3122. * dp_tx_drop() - Drop the frame on a given VAP
  3123. * @soc: DP soc handle
  3124. * @vdev_id: id of DP vdev handle
  3125. * @nbuf: skb
  3126. *
  3127. * Drop all the incoming packets
  3128. *
  3129. * Return: nbuf
  3130. *
  3131. */
  3132. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3133. qdf_nbuf_t nbuf)
  3134. {
  3135. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3136. struct dp_vdev *vdev = NULL;
  3137. vdev = soc->vdev_id_map[vdev_id];
  3138. if (qdf_unlikely(!vdev))
  3139. return nbuf;
  3140. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3141. return nbuf;
  3142. }
  3143. /*
  3144. * dp_tx_exc_drop() - Drop the frame on a given VAP
  3145. * @soc: DP soc handle
  3146. * @vdev_id: id of DP vdev handle
  3147. * @nbuf: skb
  3148. * @tx_exc_metadata: Handle that holds exception path meta data
  3149. *
  3150. * Drop all the incoming packets
  3151. *
  3152. * Return: nbuf
  3153. *
  3154. */
  3155. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3156. qdf_nbuf_t nbuf,
  3157. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3158. {
  3159. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3160. }
  3161. #endif
  3162. /*
  3163. * dp_tx_send() - Transmit a frame on a given VAP
  3164. * @soc: DP soc handle
  3165. * @vdev_id: id of DP vdev handle
  3166. * @nbuf: skb
  3167. *
  3168. * Entry point for Core Tx layer (DP_TX) invoked from
  3169. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3170. * cases
  3171. *
  3172. * Return: NULL on success,
  3173. * nbuf when it fails to send
  3174. */
  3175. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3176. qdf_nbuf_t nbuf)
  3177. {
  3178. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3179. uint16_t peer_id = HTT_INVALID_PEER;
  3180. /*
  3181. * doing a memzero is causing additional function call overhead
  3182. * so doing static stack clearing
  3183. */
  3184. struct dp_tx_msdu_info_s msdu_info = {0};
  3185. struct dp_vdev *vdev = NULL;
  3186. qdf_nbuf_t end_nbuf = NULL;
  3187. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3188. return nbuf;
  3189. /*
  3190. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3191. * this in per packet path.
  3192. *
  3193. * As in this path vdev memory is already protected with netdev
  3194. * tx lock
  3195. */
  3196. vdev = soc->vdev_id_map[vdev_id];
  3197. if (qdf_unlikely(!vdev))
  3198. return nbuf;
  3199. /*
  3200. * Set Default Host TID value to invalid TID
  3201. * (TID override disabled)
  3202. */
  3203. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3204. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_headlen(nbuf));
  3205. if (qdf_unlikely(vdev->mesh_vdev)) {
  3206. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3207. &msdu_info);
  3208. if (!nbuf_mesh) {
  3209. dp_verbose_debug("Extracting mesh metadata failed");
  3210. return nbuf;
  3211. }
  3212. nbuf = nbuf_mesh;
  3213. }
  3214. /*
  3215. * Get HW Queue to use for this frame.
  3216. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3217. * dedicated for data and 1 for command.
  3218. * "queue_id" maps to one hardware ring.
  3219. * With each ring, we also associate a unique Tx descriptor pool
  3220. * to minimize lock contention for these resources.
  3221. */
  3222. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3223. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3224. 1);
  3225. /*
  3226. * TCL H/W supports 2 DSCP-TID mapping tables.
  3227. * Table 1 - Default DSCP-TID mapping table
  3228. * Table 2 - 1 DSCP-TID override table
  3229. *
  3230. * If we need a different DSCP-TID mapping for this vap,
  3231. * call tid_classify to extract DSCP/ToS from frame and
  3232. * map to a TID and store in msdu_info. This is later used
  3233. * to fill in TCL Input descriptor (per-packet TID override).
  3234. */
  3235. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3236. /*
  3237. * Classify the frame and call corresponding
  3238. * "prepare" function which extracts the segment (TSO)
  3239. * and fragmentation information (for TSO , SG, ME, or Raw)
  3240. * into MSDU_INFO structure which is later used to fill
  3241. * SW and HW descriptors.
  3242. */
  3243. if (qdf_nbuf_is_tso(nbuf)) {
  3244. dp_verbose_debug("TSO frame %pK", vdev);
  3245. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3246. qdf_nbuf_len(nbuf));
  3247. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3248. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3249. qdf_nbuf_len(nbuf));
  3250. return nbuf;
  3251. }
  3252. goto send_multiple;
  3253. }
  3254. /* SG */
  3255. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3256. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3257. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3258. return nbuf;
  3259. } else {
  3260. struct dp_tx_seg_info_s seg_info = {0};
  3261. if (qdf_unlikely(is_nbuf_frm_rmnet(nbuf, &msdu_info)))
  3262. goto send_single;
  3263. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3264. &msdu_info);
  3265. if (!nbuf)
  3266. return NULL;
  3267. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3268. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3269. qdf_nbuf_len(nbuf));
  3270. goto send_multiple;
  3271. }
  3272. }
  3273. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3274. return NULL;
  3275. if (qdf_unlikely(dp_tx_mcast_drop(vdev, nbuf)))
  3276. return nbuf;
  3277. /* RAW */
  3278. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3279. struct dp_tx_seg_info_s seg_info = {0};
  3280. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3281. if (!nbuf)
  3282. return NULL;
  3283. dp_verbose_debug("Raw frame %pK", vdev);
  3284. goto send_multiple;
  3285. }
  3286. if (qdf_unlikely(vdev->nawds_enabled)) {
  3287. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3288. qdf_nbuf_data(nbuf);
  3289. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3290. uint16_t sa_peer_id = DP_INVALID_PEER;
  3291. if (!soc->ast_offload_support) {
  3292. struct dp_ast_entry *ast_entry = NULL;
  3293. qdf_spin_lock_bh(&soc->ast_lock);
  3294. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3295. (soc,
  3296. (uint8_t *)(eh->ether_shost),
  3297. vdev->pdev->pdev_id);
  3298. if (ast_entry)
  3299. sa_peer_id = ast_entry->peer_id;
  3300. qdf_spin_unlock_bh(&soc->ast_lock);
  3301. }
  3302. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3303. sa_peer_id);
  3304. }
  3305. peer_id = DP_INVALID_PEER;
  3306. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3307. 1, qdf_nbuf_len(nbuf));
  3308. }
  3309. send_single:
  3310. /* Single linear frame */
  3311. /*
  3312. * If nbuf is a simple linear frame, use send_single function to
  3313. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3314. * SRNG. There is no need to setup a MSDU extension descriptor.
  3315. */
  3316. dp_tx_prefetch_nbuf_data(nbuf);
  3317. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3318. peer_id, end_nbuf);
  3319. return nbuf;
  3320. send_multiple:
  3321. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3322. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3323. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3324. return nbuf;
  3325. }
  3326. /**
  3327. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3328. * case to vaoid check in perpkt path.
  3329. * @soc: DP soc handle
  3330. * @vdev_id: id of DP vdev handle
  3331. * @nbuf: skb
  3332. *
  3333. * Entry point for Core Tx layer (DP_TX) invoked from
  3334. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3335. * with special condition to avoid per pkt check in dp_tx_send
  3336. *
  3337. * Return: NULL on success,
  3338. * nbuf when it fails to send
  3339. */
  3340. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3341. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3342. {
  3343. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3344. struct dp_vdev *vdev = NULL;
  3345. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3346. return nbuf;
  3347. /*
  3348. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3349. * this in per packet path.
  3350. *
  3351. * As in this path vdev memory is already protected with netdev
  3352. * tx lock
  3353. */
  3354. vdev = soc->vdev_id_map[vdev_id];
  3355. if (qdf_unlikely(!vdev))
  3356. return nbuf;
  3357. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3358. == QDF_STATUS_E_FAILURE)) {
  3359. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3360. return nbuf;
  3361. }
  3362. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3363. }
  3364. #ifdef UMAC_SUPPORT_PROXY_ARP
  3365. /**
  3366. * dp_tx_proxy_arp() - Tx proxy arp handler
  3367. * @vdev: datapath vdev handle
  3368. * @buf: sk buffer
  3369. *
  3370. * Return: status
  3371. */
  3372. static inline
  3373. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3374. {
  3375. if (vdev->osif_proxy_arp)
  3376. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3377. /*
  3378. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3379. * osif_proxy_arp has a valid function pointer assigned
  3380. * to it
  3381. */
  3382. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3383. return QDF_STATUS_NOT_INITIALIZED;
  3384. }
  3385. #else
  3386. /**
  3387. * dp_tx_proxy_arp() - Tx proxy arp handler
  3388. * @vdev: datapath vdev handle
  3389. * @buf: sk buffer
  3390. *
  3391. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3392. * is not defined.
  3393. *
  3394. * Return: status
  3395. */
  3396. static inline
  3397. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3398. {
  3399. return QDF_STATUS_SUCCESS;
  3400. }
  3401. #endif
  3402. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3403. #ifdef WLAN_MCAST_MLO
  3404. static bool
  3405. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3406. struct dp_tx_desc_s *tx_desc,
  3407. qdf_nbuf_t nbuf,
  3408. uint8_t reinject_reason)
  3409. {
  3410. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3411. if (soc->arch_ops.dp_tx_mcast_handler)
  3412. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3413. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3414. return true;
  3415. }
  3416. return false;
  3417. }
  3418. #else /* WLAN_MCAST_MLO */
  3419. static inline bool
  3420. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3421. struct dp_tx_desc_s *tx_desc,
  3422. qdf_nbuf_t nbuf,
  3423. uint8_t reinject_reason)
  3424. {
  3425. return false;
  3426. }
  3427. #endif /* WLAN_MCAST_MLO */
  3428. #else
  3429. static inline bool
  3430. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3431. struct dp_tx_desc_s *tx_desc,
  3432. qdf_nbuf_t nbuf,
  3433. uint8_t reinject_reason)
  3434. {
  3435. return false;
  3436. }
  3437. #endif
  3438. /**
  3439. * dp_tx_reinject_handler() - Tx Reinject Handler
  3440. * @soc: datapath soc handle
  3441. * @vdev: datapath vdev handle
  3442. * @tx_desc: software descriptor head pointer
  3443. * @status : Tx completion status from HTT descriptor
  3444. * @reinject_reason : reinject reason from HTT descriptor
  3445. *
  3446. * This function reinjects frames back to Target.
  3447. * Todo - Host queue needs to be added
  3448. *
  3449. * Return: none
  3450. */
  3451. void dp_tx_reinject_handler(struct dp_soc *soc,
  3452. struct dp_vdev *vdev,
  3453. struct dp_tx_desc_s *tx_desc,
  3454. uint8_t *status,
  3455. uint8_t reinject_reason)
  3456. {
  3457. struct dp_peer *peer = NULL;
  3458. uint32_t peer_id = HTT_INVALID_PEER;
  3459. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3460. qdf_nbuf_t nbuf_copy = NULL;
  3461. struct dp_tx_msdu_info_s msdu_info;
  3462. #ifdef WDS_VENDOR_EXTENSION
  3463. int is_mcast = 0, is_ucast = 0;
  3464. int num_peers_3addr = 0;
  3465. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3466. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3467. #endif
  3468. struct dp_txrx_peer *txrx_peer;
  3469. qdf_assert(vdev);
  3470. dp_tx_debug("Tx reinject path");
  3471. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3472. qdf_nbuf_len(tx_desc->nbuf));
  3473. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3474. return;
  3475. #ifdef WDS_VENDOR_EXTENSION
  3476. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3477. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3478. } else {
  3479. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3480. }
  3481. is_ucast = !is_mcast;
  3482. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3483. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3484. txrx_peer = dp_get_txrx_peer(peer);
  3485. if (!txrx_peer || txrx_peer->bss_peer)
  3486. continue;
  3487. /* Detect wds peers that use 3-addr framing for mcast.
  3488. * if there are any, the bss_peer is used to send the
  3489. * the mcast frame using 3-addr format. all wds enabled
  3490. * peers that use 4-addr framing for mcast frames will
  3491. * be duplicated and sent as 4-addr frames below.
  3492. */
  3493. if (!txrx_peer->wds_enabled ||
  3494. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3495. num_peers_3addr = 1;
  3496. break;
  3497. }
  3498. }
  3499. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3500. #endif
  3501. if (qdf_unlikely(vdev->mesh_vdev)) {
  3502. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3503. } else {
  3504. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3505. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3506. txrx_peer = dp_get_txrx_peer(peer);
  3507. if (!txrx_peer)
  3508. continue;
  3509. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3510. #ifdef WDS_VENDOR_EXTENSION
  3511. /*
  3512. * . if 3-addr STA, then send on BSS Peer
  3513. * . if Peer WDS enabled and accept 4-addr mcast,
  3514. * send mcast on that peer only
  3515. * . if Peer WDS enabled and accept 4-addr ucast,
  3516. * send ucast on that peer only
  3517. */
  3518. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3519. (txrx_peer->wds_enabled &&
  3520. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3521. (is_ucast &&
  3522. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3523. #else
  3524. (txrx_peer->bss_peer &&
  3525. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3526. #endif
  3527. peer_id = DP_INVALID_PEER;
  3528. nbuf_copy = qdf_nbuf_copy(nbuf);
  3529. if (!nbuf_copy) {
  3530. dp_tx_debug("nbuf copy failed");
  3531. break;
  3532. }
  3533. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3534. dp_tx_get_queue(vdev, nbuf,
  3535. &msdu_info.tx_queue);
  3536. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3537. nbuf_copy,
  3538. &msdu_info,
  3539. peer_id,
  3540. NULL);
  3541. if (nbuf_copy) {
  3542. dp_tx_debug("pkt send failed");
  3543. qdf_nbuf_free(nbuf_copy);
  3544. }
  3545. }
  3546. }
  3547. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3548. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3549. QDF_DMA_TO_DEVICE, nbuf->len);
  3550. qdf_nbuf_free(nbuf);
  3551. }
  3552. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3553. }
  3554. /**
  3555. * dp_tx_inspect_handler() - Tx Inspect Handler
  3556. * @soc: datapath soc handle
  3557. * @vdev: datapath vdev handle
  3558. * @tx_desc: software descriptor head pointer
  3559. * @status : Tx completion status from HTT descriptor
  3560. *
  3561. * Handles Tx frames sent back to Host for inspection
  3562. * (ProxyARP)
  3563. *
  3564. * Return: none
  3565. */
  3566. void dp_tx_inspect_handler(struct dp_soc *soc,
  3567. struct dp_vdev *vdev,
  3568. struct dp_tx_desc_s *tx_desc,
  3569. uint8_t *status)
  3570. {
  3571. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3572. "%s Tx inspect path",
  3573. __func__);
  3574. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3575. qdf_nbuf_len(tx_desc->nbuf));
  3576. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3577. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3578. }
  3579. #ifdef MESH_MODE_SUPPORT
  3580. /**
  3581. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3582. * in mesh meta header
  3583. * @tx_desc: software descriptor head pointer
  3584. * @ts: pointer to tx completion stats
  3585. * Return: none
  3586. */
  3587. static
  3588. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3589. struct hal_tx_completion_status *ts)
  3590. {
  3591. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3592. if (!tx_desc->msdu_ext_desc) {
  3593. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3594. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3595. "netbuf %pK offset %d",
  3596. netbuf, tx_desc->pkt_offset);
  3597. return;
  3598. }
  3599. }
  3600. }
  3601. #else
  3602. static
  3603. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3604. struct hal_tx_completion_status *ts)
  3605. {
  3606. }
  3607. #endif
  3608. #ifdef CONFIG_SAWF
  3609. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3610. struct dp_vdev *vdev,
  3611. struct dp_txrx_peer *txrx_peer,
  3612. struct dp_tx_desc_s *tx_desc,
  3613. struct hal_tx_completion_status *ts,
  3614. uint8_t tid)
  3615. {
  3616. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3617. ts, tid);
  3618. }
  3619. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3620. uint32_t nw_delay,
  3621. uint32_t sw_delay,
  3622. uint32_t hw_delay)
  3623. {
  3624. dp_peer_tid_delay_avg(tx_delay,
  3625. nw_delay,
  3626. sw_delay,
  3627. hw_delay);
  3628. }
  3629. #else
  3630. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3631. struct dp_vdev *vdev,
  3632. struct dp_txrx_peer *txrx_peer,
  3633. struct dp_tx_desc_s *tx_desc,
  3634. struct hal_tx_completion_status *ts,
  3635. uint8_t tid)
  3636. {
  3637. }
  3638. static inline void
  3639. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3640. uint32_t nw_delay, uint32_t sw_delay,
  3641. uint32_t hw_delay)
  3642. {
  3643. }
  3644. #endif
  3645. #ifdef QCA_PEER_EXT_STATS
  3646. #ifdef WLAN_CONFIG_TX_DELAY
  3647. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3648. struct dp_tx_desc_s *tx_desc,
  3649. struct hal_tx_completion_status *ts,
  3650. struct dp_vdev *vdev)
  3651. {
  3652. struct dp_soc *soc = vdev->pdev->soc;
  3653. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3654. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3655. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3656. if (!ts->valid)
  3657. return;
  3658. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3659. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3660. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3661. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3662. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3663. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3664. &fwhw_transmit_delay))
  3665. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3666. fwhw_transmit_delay);
  3667. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3668. fwhw_transmit_delay);
  3669. }
  3670. #else
  3671. /*
  3672. * dp_tx_compute_tid_delay() - Compute per TID delay
  3673. * @stats: Per TID delay stats
  3674. * @tx_desc: Software Tx descriptor
  3675. * @ts: Tx completion status
  3676. * @vdev: vdev
  3677. *
  3678. * Compute the software enqueue and hw enqueue delays and
  3679. * update the respective histograms
  3680. *
  3681. * Return: void
  3682. */
  3683. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3684. struct dp_tx_desc_s *tx_desc,
  3685. struct hal_tx_completion_status *ts,
  3686. struct dp_vdev *vdev)
  3687. {
  3688. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3689. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3690. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3691. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3692. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3693. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3694. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3695. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3696. timestamp_hw_enqueue);
  3697. /*
  3698. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3699. */
  3700. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3701. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3702. }
  3703. #endif
  3704. /*
  3705. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3706. * @txrx_peer: DP peer context
  3707. * @tx_desc: Tx software descriptor
  3708. * @tid: Transmission ID
  3709. * @ring_id: Rx CPU context ID/CPU_ID
  3710. *
  3711. * Update the peer extended stats. These are enhanced other
  3712. * delay stats per msdu level.
  3713. *
  3714. * Return: void
  3715. */
  3716. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3717. struct dp_tx_desc_s *tx_desc,
  3718. struct hal_tx_completion_status *ts,
  3719. uint8_t ring_id)
  3720. {
  3721. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3722. struct dp_soc *soc = NULL;
  3723. struct dp_peer_delay_stats *delay_stats = NULL;
  3724. uint8_t tid;
  3725. soc = pdev->soc;
  3726. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3727. return;
  3728. tid = ts->tid;
  3729. delay_stats = txrx_peer->delay_stats;
  3730. qdf_assert(delay_stats);
  3731. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3732. /*
  3733. * For non-TID packets use the TID 9
  3734. */
  3735. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3736. tid = CDP_MAX_DATA_TIDS - 1;
  3737. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3738. tx_desc, ts, txrx_peer->vdev);
  3739. }
  3740. #else
  3741. static inline
  3742. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3743. struct dp_tx_desc_s *tx_desc,
  3744. struct hal_tx_completion_status *ts,
  3745. uint8_t ring_id)
  3746. {
  3747. }
  3748. #endif
  3749. #ifdef WLAN_PEER_JITTER
  3750. /*
  3751. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3752. * @curr_delay: Current delay
  3753. * @prev_Delay: Previous delay
  3754. * @avg_jitter: Average Jitter
  3755. * Return: Newly Computed Average Jitter
  3756. */
  3757. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3758. uint32_t prev_delay,
  3759. uint32_t avg_jitter)
  3760. {
  3761. uint32_t curr_jitter;
  3762. int32_t jitter_diff;
  3763. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3764. if (!avg_jitter)
  3765. return curr_jitter;
  3766. jitter_diff = curr_jitter - avg_jitter;
  3767. if (jitter_diff < 0)
  3768. avg_jitter = avg_jitter -
  3769. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3770. else
  3771. avg_jitter = avg_jitter +
  3772. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3773. return avg_jitter;
  3774. }
  3775. /*
  3776. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3777. * @curr_delay: Current delay
  3778. * @avg_Delay: Average delay
  3779. * Return: Newly Computed Average Delay
  3780. */
  3781. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3782. uint32_t avg_delay)
  3783. {
  3784. int32_t delay_diff;
  3785. if (!avg_delay)
  3786. return curr_delay;
  3787. delay_diff = curr_delay - avg_delay;
  3788. if (delay_diff < 0)
  3789. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3790. DP_AVG_DELAY_WEIGHT_DENOM);
  3791. else
  3792. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3793. DP_AVG_DELAY_WEIGHT_DENOM);
  3794. return avg_delay;
  3795. }
  3796. #ifdef WLAN_CONFIG_TX_DELAY
  3797. /*
  3798. * dp_tx_compute_cur_delay() - get the current delay
  3799. * @soc: soc handle
  3800. * @vdev: vdev structure for data path state
  3801. * @ts: Tx completion status
  3802. * @curr_delay: current delay
  3803. * @tx_desc: tx descriptor
  3804. * Return: void
  3805. */
  3806. static
  3807. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3808. struct dp_vdev *vdev,
  3809. struct hal_tx_completion_status *ts,
  3810. uint32_t *curr_delay,
  3811. struct dp_tx_desc_s *tx_desc)
  3812. {
  3813. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3814. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3815. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3816. curr_delay);
  3817. return status;
  3818. }
  3819. #else
  3820. static
  3821. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3822. struct dp_vdev *vdev,
  3823. struct hal_tx_completion_status *ts,
  3824. uint32_t *curr_delay,
  3825. struct dp_tx_desc_s *tx_desc)
  3826. {
  3827. int64_t current_timestamp, timestamp_hw_enqueue;
  3828. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3829. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3830. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3831. return QDF_STATUS_SUCCESS;
  3832. }
  3833. #endif
  3834. /* dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3835. * @jiiter - per tid per ring jitter stats
  3836. * @ts: Tx completion status
  3837. * @vdev - vdev structure for data path state
  3838. * @tx_desc - tx descriptor
  3839. * Return: void
  3840. */
  3841. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3842. struct hal_tx_completion_status *ts,
  3843. struct dp_vdev *vdev,
  3844. struct dp_tx_desc_s *tx_desc)
  3845. {
  3846. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3847. struct dp_soc *soc = vdev->pdev->soc;
  3848. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3849. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3850. jitter->tx_drop += 1;
  3851. return;
  3852. }
  3853. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3854. tx_desc);
  3855. if (QDF_IS_STATUS_SUCCESS(status)) {
  3856. avg_delay = jitter->tx_avg_delay;
  3857. avg_jitter = jitter->tx_avg_jitter;
  3858. prev_delay = jitter->tx_prev_delay;
  3859. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3860. prev_delay,
  3861. avg_jitter);
  3862. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3863. jitter->tx_avg_delay = avg_delay;
  3864. jitter->tx_avg_jitter = avg_jitter;
  3865. jitter->tx_prev_delay = curr_delay;
  3866. jitter->tx_total_success += 1;
  3867. } else if (status == QDF_STATUS_E_FAILURE) {
  3868. jitter->tx_avg_err += 1;
  3869. }
  3870. }
  3871. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3872. * @txrx_peer: DP peer context
  3873. * @tx_desc: Tx software descriptor
  3874. * @ts: Tx completion status
  3875. * @ring_id: Rx CPU context ID/CPU_ID
  3876. * Return: void
  3877. */
  3878. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3879. struct dp_tx_desc_s *tx_desc,
  3880. struct hal_tx_completion_status *ts,
  3881. uint8_t ring_id)
  3882. {
  3883. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3884. struct dp_soc *soc = pdev->soc;
  3885. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3886. uint8_t tid;
  3887. struct cdp_peer_tid_stats *rx_tid = NULL;
  3888. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3889. return;
  3890. tid = ts->tid;
  3891. jitter_stats = txrx_peer->jitter_stats;
  3892. qdf_assert_always(jitter_stats);
  3893. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3894. /*
  3895. * For non-TID packets use the TID 9
  3896. */
  3897. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3898. tid = CDP_MAX_DATA_TIDS - 1;
  3899. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3900. dp_tx_compute_tid_jitter(rx_tid,
  3901. ts, txrx_peer->vdev, tx_desc);
  3902. }
  3903. #else
  3904. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3905. struct dp_tx_desc_s *tx_desc,
  3906. struct hal_tx_completion_status *ts,
  3907. uint8_t ring_id)
  3908. {
  3909. }
  3910. #endif
  3911. #ifdef HW_TX_DELAY_STATS_ENABLE
  3912. /**
  3913. * dp_update_tx_delay_stats() - update the delay stats
  3914. * @vdev: vdev handle
  3915. * @delay: delay in ms or us based on the flag delay_in_us
  3916. * @tid: tid value
  3917. * @mode: type of tx delay mode
  3918. * @ring id: ring number
  3919. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3920. *
  3921. * Return: none
  3922. */
  3923. static inline
  3924. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3925. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3926. {
  3927. struct cdp_tid_tx_stats *tstats =
  3928. &vdev->stats.tid_tx_stats[ring_id][tid];
  3929. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3930. delay_in_us);
  3931. }
  3932. #else
  3933. static inline
  3934. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3935. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3936. {
  3937. struct cdp_tid_tx_stats *tstats =
  3938. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3939. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3940. delay_in_us);
  3941. }
  3942. #endif
  3943. /**
  3944. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3945. * to pass in correct fields
  3946. *
  3947. * @vdev: pdev handle
  3948. * @tx_desc: tx descriptor
  3949. * @tid: tid value
  3950. * @ring_id: TCL or WBM ring number for transmit path
  3951. * Return: none
  3952. */
  3953. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3954. uint8_t tid, uint8_t ring_id)
  3955. {
  3956. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3957. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3958. uint32_t fwhw_transmit_delay_us;
  3959. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3960. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3961. return;
  3962. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3963. fwhw_transmit_delay_us =
  3964. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3965. qdf_ktime_to_us(tx_desc->timestamp);
  3966. /*
  3967. * Delay between packet enqueued to HW and Tx completion in us
  3968. */
  3969. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3970. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3971. ring_id, true);
  3972. /*
  3973. * For MCL, only enqueue to completion delay is required
  3974. * so return if the vdev flag is enabled.
  3975. */
  3976. return;
  3977. }
  3978. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3979. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3980. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3981. timestamp_hw_enqueue);
  3982. /*
  3983. * Delay between packet enqueued to HW and Tx completion in ms
  3984. */
  3985. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3986. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3987. false);
  3988. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3989. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3990. interframe_delay = (uint32_t)(timestamp_ingress -
  3991. vdev->prev_tx_enq_tstamp);
  3992. /*
  3993. * Delay in software enqueue
  3994. */
  3995. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3996. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3997. false);
  3998. /*
  3999. * Update interframe delay stats calculated at hardstart receive point.
  4000. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  4001. * interframe delay will not be calculate correctly for 1st frame.
  4002. * On the other side, this will help in avoiding extra per packet check
  4003. * of !vdev->prev_tx_enq_tstamp.
  4004. */
  4005. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  4006. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  4007. false);
  4008. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  4009. }
  4010. #ifdef DISABLE_DP_STATS
  4011. static
  4012. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  4013. struct dp_txrx_peer *txrx_peer)
  4014. {
  4015. }
  4016. #else
  4017. static inline void
  4018. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  4019. {
  4020. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  4021. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  4022. if (subtype != QDF_PROTO_INVALID)
  4023. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  4024. 1);
  4025. }
  4026. #endif
  4027. #ifndef QCA_ENHANCED_STATS_SUPPORT
  4028. #ifdef DP_PEER_EXTENDED_API
  4029. static inline uint8_t
  4030. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4031. {
  4032. return txrx_peer->mpdu_retry_threshold;
  4033. }
  4034. #else
  4035. static inline uint8_t
  4036. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4037. {
  4038. return 0;
  4039. }
  4040. #endif
  4041. /**
  4042. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  4043. *
  4044. * @ts: Tx compltion status
  4045. * @txrx_peer: datapath txrx_peer handle
  4046. *
  4047. * Return: void
  4048. */
  4049. static inline void
  4050. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4051. struct dp_txrx_peer *txrx_peer)
  4052. {
  4053. uint8_t mcs, pkt_type, dst_mcs_idx;
  4054. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  4055. mcs = ts->mcs;
  4056. pkt_type = ts->pkt_type;
  4057. /* do HW to SW pkt type conversion */
  4058. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  4059. hal_2_dp_pkt_type_map[pkt_type]);
  4060. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  4061. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  4062. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4063. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  4064. 1);
  4065. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  4066. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  4067. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  4068. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4069. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  4070. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  4071. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  4072. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  4073. if (ts->first_msdu) {
  4074. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  4075. ts->transmit_cnt > 1);
  4076. if (!retry_threshold)
  4077. return;
  4078. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  4079. qdf_do_div(ts->transmit_cnt,
  4080. retry_threshold),
  4081. ts->transmit_cnt > retry_threshold);
  4082. }
  4083. }
  4084. #else
  4085. static inline void
  4086. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4087. struct dp_txrx_peer *txrx_peer)
  4088. {
  4089. }
  4090. #endif
  4091. /**
  4092. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  4093. * per wbm ring
  4094. *
  4095. * @tx_desc: software descriptor head pointer
  4096. * @ts: Tx completion status
  4097. * @peer: peer handle
  4098. * @ring_id: ring number
  4099. *
  4100. * Return: None
  4101. */
  4102. static inline void
  4103. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  4104. struct hal_tx_completion_status *ts,
  4105. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  4106. {
  4107. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  4108. uint8_t tid = ts->tid;
  4109. uint32_t length;
  4110. struct cdp_tid_tx_stats *tid_stats;
  4111. if (!pdev)
  4112. return;
  4113. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  4114. tid = CDP_MAX_DATA_TIDS - 1;
  4115. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4116. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4117. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4118. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  4119. return;
  4120. }
  4121. length = qdf_nbuf_len(tx_desc->nbuf);
  4122. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4123. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4124. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4125. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4126. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4127. tid_stats->tqm_status_cnt[ts->status]++;
  4128. }
  4129. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4130. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4131. ts->transmit_cnt > 1);
  4132. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4133. 1, ts->transmit_cnt > 2);
  4134. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  4135. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4136. ts->msdu_part_of_amsdu);
  4137. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4138. !ts->msdu_part_of_amsdu);
  4139. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  4140. qdf_system_ticks();
  4141. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  4142. return;
  4143. }
  4144. /*
  4145. * tx_failed is ideally supposed to be updated from HTT ppdu
  4146. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4147. * hw limitation there are no completions for failed cases.
  4148. * Hence updating tx_failed from data path. Please note that
  4149. * if tx_failed is fixed to be from ppdu, then this has to be
  4150. * removed
  4151. */
  4152. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4153. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4154. ts->transmit_cnt > DP_RETRY_COUNT);
  4155. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  4156. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4157. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  4158. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4159. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4160. length);
  4161. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4162. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  4163. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4164. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  4165. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4166. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  4167. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4168. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  4169. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4170. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  4171. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4172. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4173. tx.dropped.fw_rem_queue_disable, 1);
  4174. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4175. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4176. tx.dropped.fw_rem_no_match, 1);
  4177. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4178. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4179. tx.dropped.drop_threshold, 1);
  4180. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4181. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4182. tx.dropped.drop_link_desc_na, 1);
  4183. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4184. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4185. tx.dropped.invalid_drop, 1);
  4186. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4187. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4188. tx.dropped.mcast_vdev_drop, 1);
  4189. } else {
  4190. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  4191. }
  4192. }
  4193. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4194. /**
  4195. * dp_tx_flow_pool_lock() - take flow pool lock
  4196. * @soc: core txrx main context
  4197. * @tx_desc: tx desc
  4198. *
  4199. * Return: None
  4200. */
  4201. static inline
  4202. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4203. struct dp_tx_desc_s *tx_desc)
  4204. {
  4205. struct dp_tx_desc_pool_s *pool;
  4206. uint8_t desc_pool_id;
  4207. desc_pool_id = tx_desc->pool_id;
  4208. pool = &soc->tx_desc[desc_pool_id];
  4209. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4210. }
  4211. /**
  4212. * dp_tx_flow_pool_unlock() - release flow pool lock
  4213. * @soc: core txrx main context
  4214. * @tx_desc: tx desc
  4215. *
  4216. * Return: None
  4217. */
  4218. static inline
  4219. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4220. struct dp_tx_desc_s *tx_desc)
  4221. {
  4222. struct dp_tx_desc_pool_s *pool;
  4223. uint8_t desc_pool_id;
  4224. desc_pool_id = tx_desc->pool_id;
  4225. pool = &soc->tx_desc[desc_pool_id];
  4226. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4227. }
  4228. #else
  4229. static inline
  4230. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4231. {
  4232. }
  4233. static inline
  4234. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4235. {
  4236. }
  4237. #endif
  4238. /**
  4239. * dp_tx_notify_completion() - Notify tx completion for this desc
  4240. * @soc: core txrx main context
  4241. * @vdev: datapath vdev handle
  4242. * @tx_desc: tx desc
  4243. * @netbuf: buffer
  4244. * @status: tx status
  4245. *
  4246. * Return: none
  4247. */
  4248. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4249. struct dp_vdev *vdev,
  4250. struct dp_tx_desc_s *tx_desc,
  4251. qdf_nbuf_t netbuf,
  4252. uint8_t status)
  4253. {
  4254. void *osif_dev;
  4255. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4256. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4257. qdf_assert(tx_desc);
  4258. if (!vdev ||
  4259. !vdev->osif_vdev) {
  4260. return;
  4261. }
  4262. osif_dev = vdev->osif_vdev;
  4263. tx_compl_cbk = vdev->tx_comp;
  4264. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4265. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4266. if (tx_compl_cbk)
  4267. tx_compl_cbk(netbuf, osif_dev, flag);
  4268. }
  4269. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  4270. * @pdev: pdev handle
  4271. * @tid: tid value
  4272. * @txdesc_ts: timestamp from txdesc
  4273. * @ppdu_id: ppdu id
  4274. *
  4275. * Return: none
  4276. */
  4277. #ifdef FEATURE_PERPKT_INFO
  4278. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4279. struct dp_txrx_peer *txrx_peer,
  4280. uint8_t tid,
  4281. uint64_t txdesc_ts,
  4282. uint32_t ppdu_id)
  4283. {
  4284. uint64_t delta_ms;
  4285. struct cdp_tx_sojourn_stats *sojourn_stats;
  4286. struct dp_peer *primary_link_peer = NULL;
  4287. struct dp_soc *link_peer_soc = NULL;
  4288. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4289. return;
  4290. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4291. tid >= CDP_DATA_TID_MAX))
  4292. return;
  4293. if (qdf_unlikely(!pdev->sojourn_buf))
  4294. return;
  4295. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4296. txrx_peer->peer_id,
  4297. DP_MOD_ID_TX_COMP);
  4298. if (qdf_unlikely(!primary_link_peer))
  4299. return;
  4300. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4301. qdf_nbuf_data(pdev->sojourn_buf);
  4302. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4303. sojourn_stats->cookie = (void *)
  4304. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4305. primary_link_peer);
  4306. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4307. txdesc_ts;
  4308. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4309. delta_ms);
  4310. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4311. sojourn_stats->num_msdus[tid] = 1;
  4312. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4313. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4314. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4315. pdev->sojourn_buf, HTT_INVALID_PEER,
  4316. WDI_NO_VAL, pdev->pdev_id);
  4317. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4318. sojourn_stats->num_msdus[tid] = 0;
  4319. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4320. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4321. }
  4322. #else
  4323. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4324. struct dp_txrx_peer *txrx_peer,
  4325. uint8_t tid,
  4326. uint64_t txdesc_ts,
  4327. uint32_t ppdu_id)
  4328. {
  4329. }
  4330. #endif
  4331. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4332. /**
  4333. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  4334. * @soc: dp_soc handle
  4335. * @desc: Tx Descriptor
  4336. * @ts: HAL Tx completion descriptor contents
  4337. *
  4338. * This function is used to send tx completion to packet capture
  4339. */
  4340. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4341. struct dp_tx_desc_s *desc,
  4342. struct hal_tx_completion_status *ts)
  4343. {
  4344. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4345. desc, ts->peer_id,
  4346. WDI_NO_VAL, desc->pdev->pdev_id);
  4347. }
  4348. #endif
  4349. /**
  4350. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  4351. * @soc: DP Soc handle
  4352. * @tx_desc: software Tx descriptor
  4353. * @ts : Tx completion status from HAL/HTT descriptor
  4354. *
  4355. * Return: none
  4356. */
  4357. void
  4358. dp_tx_comp_process_desc(struct dp_soc *soc,
  4359. struct dp_tx_desc_s *desc,
  4360. struct hal_tx_completion_status *ts,
  4361. struct dp_txrx_peer *txrx_peer)
  4362. {
  4363. uint64_t time_latency = 0;
  4364. uint16_t peer_id = DP_INVALID_PEER_ID;
  4365. /*
  4366. * m_copy/tx_capture modes are not supported for
  4367. * scatter gather packets
  4368. */
  4369. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4370. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4371. qdf_ktime_to_ms(desc->timestamp));
  4372. }
  4373. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4374. if (dp_tx_pkt_tracepoints_enabled())
  4375. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4376. desc->msdu_ext_desc ?
  4377. desc->msdu_ext_desc->tso_desc : NULL,
  4378. qdf_ktime_to_ms(desc->timestamp));
  4379. if (!(desc->msdu_ext_desc)) {
  4380. dp_tx_enh_unmap(soc, desc);
  4381. if (txrx_peer)
  4382. peer_id = txrx_peer->peer_id;
  4383. if (QDF_STATUS_SUCCESS ==
  4384. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4385. return;
  4386. }
  4387. if (QDF_STATUS_SUCCESS ==
  4388. dp_get_completion_indication_for_stack(soc,
  4389. desc->pdev,
  4390. txrx_peer, ts,
  4391. desc->nbuf,
  4392. time_latency)) {
  4393. dp_send_completion_to_stack(soc,
  4394. desc->pdev,
  4395. ts->peer_id,
  4396. ts->ppdu_id,
  4397. desc->nbuf);
  4398. return;
  4399. }
  4400. }
  4401. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4402. dp_tx_comp_free_buf(soc, desc, false);
  4403. }
  4404. #ifdef DISABLE_DP_STATS
  4405. /**
  4406. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4407. * @soc: core txrx main context
  4408. * @tx_desc: tx desc
  4409. * @status: tx status
  4410. *
  4411. * Return: none
  4412. */
  4413. static inline
  4414. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4415. struct dp_vdev *vdev,
  4416. struct dp_tx_desc_s *tx_desc,
  4417. uint8_t status)
  4418. {
  4419. }
  4420. #else
  4421. static inline
  4422. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4423. struct dp_vdev *vdev,
  4424. struct dp_tx_desc_s *tx_desc,
  4425. uint8_t status)
  4426. {
  4427. void *osif_dev;
  4428. ol_txrx_stats_rx_fp stats_cbk;
  4429. uint8_t pkt_type;
  4430. qdf_assert(tx_desc);
  4431. if (!vdev ||
  4432. !vdev->osif_vdev ||
  4433. !vdev->stats_cb)
  4434. return;
  4435. osif_dev = vdev->osif_vdev;
  4436. stats_cbk = vdev->stats_cb;
  4437. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4438. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4439. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4440. &pkt_type);
  4441. }
  4442. #endif
  4443. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4444. /* Mask for bit29 ~ bit31 */
  4445. #define DP_TX_TS_BIT29_31_MASK 0xE0000000
  4446. /* Timestamp value (unit us) if bit29 is set */
  4447. #define DP_TX_TS_BIT29_SET_VALUE BIT(29)
  4448. /**
  4449. * dp_tx_adjust_enqueue_buffer_ts() - adjust the enqueue buffer_timestamp
  4450. * @ack_ts: OTA ack timestamp, unit us.
  4451. * @enqueue_ts: TCL enqueue TX data to TQM timestamp, unit us.
  4452. * @base_delta_ts: base timestamp delta for ack_ts and enqueue_ts
  4453. *
  4454. * this function will restore the bit29 ~ bit31 3 bits value for
  4455. * buffer_timestamp in wbm2sw ring entry, currently buffer_timestamp only
  4456. * can support 0x7FFF * 1024 us (29 bits), but if the timestamp is >
  4457. * 0x7FFF * 1024 us, bit29~ bit31 will be lost.
  4458. *
  4459. * Return: the adjusted buffer_timestamp value
  4460. */
  4461. static inline
  4462. uint32_t dp_tx_adjust_enqueue_buffer_ts(uint32_t ack_ts,
  4463. uint32_t enqueue_ts,
  4464. uint32_t base_delta_ts)
  4465. {
  4466. uint32_t ack_buffer_ts;
  4467. uint32_t ack_buffer_ts_bit29_31;
  4468. uint32_t adjusted_enqueue_ts;
  4469. /* corresponding buffer_timestamp value when receive OTA Ack */
  4470. ack_buffer_ts = ack_ts - base_delta_ts;
  4471. ack_buffer_ts_bit29_31 = ack_buffer_ts & DP_TX_TS_BIT29_31_MASK;
  4472. /* restore the bit29 ~ bit31 value */
  4473. adjusted_enqueue_ts = ack_buffer_ts_bit29_31 | enqueue_ts;
  4474. /*
  4475. * if actual enqueue_ts value occupied 29 bits only, this enqueue_ts
  4476. * value + real UL delay overflow 29 bits, then 30th bit (bit-29)
  4477. * should not be marked, otherwise extra 0x20000000 us is added to
  4478. * enqueue_ts.
  4479. */
  4480. if (qdf_unlikely(adjusted_enqueue_ts > ack_buffer_ts))
  4481. adjusted_enqueue_ts -= DP_TX_TS_BIT29_SET_VALUE;
  4482. return adjusted_enqueue_ts;
  4483. }
  4484. QDF_STATUS
  4485. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4486. uint32_t delta_tsf,
  4487. uint32_t *delay_us)
  4488. {
  4489. uint32_t buffer_ts;
  4490. uint32_t delay;
  4491. if (!delay_us)
  4492. return QDF_STATUS_E_INVAL;
  4493. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4494. if (!ts->valid)
  4495. return QDF_STATUS_E_INVAL;
  4496. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4497. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4498. * valid up to 29 bits.
  4499. */
  4500. buffer_ts = ts->buffer_timestamp << 10;
  4501. buffer_ts = dp_tx_adjust_enqueue_buffer_ts(ts->tsf,
  4502. buffer_ts, delta_tsf);
  4503. delay = ts->tsf - buffer_ts - delta_tsf;
  4504. if (qdf_unlikely(delay & 0x80000000)) {
  4505. dp_err_rl("delay = 0x%x (-ve)\n"
  4506. "release_src = %d\n"
  4507. "ppdu_id = 0x%x\n"
  4508. "peer_id = 0x%x\n"
  4509. "tid = 0x%x\n"
  4510. "release_reason = %d\n"
  4511. "tsf = %u (0x%x)\n"
  4512. "buffer_timestamp = %u (0x%x)\n"
  4513. "delta_tsf = %u (0x%x)\n",
  4514. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4515. ts->tid, ts->status, ts->tsf, ts->tsf,
  4516. ts->buffer_timestamp, ts->buffer_timestamp,
  4517. delta_tsf, delta_tsf);
  4518. delay = 0;
  4519. goto end;
  4520. }
  4521. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4522. if (delay > 0x1000000) {
  4523. dp_info_rl("----------------------\n"
  4524. "Tx completion status:\n"
  4525. "----------------------\n"
  4526. "release_src = %d\n"
  4527. "ppdu_id = 0x%x\n"
  4528. "release_reason = %d\n"
  4529. "tsf = %u (0x%x)\n"
  4530. "buffer_timestamp = %u (0x%x)\n"
  4531. "delta_tsf = %u (0x%x)\n",
  4532. ts->release_src, ts->ppdu_id, ts->status,
  4533. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4534. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4535. return QDF_STATUS_E_FAILURE;
  4536. }
  4537. end:
  4538. *delay_us = delay;
  4539. return QDF_STATUS_SUCCESS;
  4540. }
  4541. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4542. uint32_t delta_tsf)
  4543. {
  4544. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4545. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4546. DP_MOD_ID_CDP);
  4547. if (!vdev) {
  4548. dp_err_rl("vdev %d does not exist", vdev_id);
  4549. return;
  4550. }
  4551. vdev->delta_tsf = delta_tsf;
  4552. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4553. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4554. }
  4555. #endif
  4556. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4557. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4558. uint8_t vdev_id, bool enable)
  4559. {
  4560. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4561. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4562. DP_MOD_ID_CDP);
  4563. if (!vdev) {
  4564. dp_err_rl("vdev %d does not exist", vdev_id);
  4565. return QDF_STATUS_E_FAILURE;
  4566. }
  4567. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4568. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4569. return QDF_STATUS_SUCCESS;
  4570. }
  4571. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4572. uint32_t *val)
  4573. {
  4574. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4575. struct dp_vdev *vdev;
  4576. uint32_t delay_accum;
  4577. uint32_t pkts_accum;
  4578. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4579. if (!vdev) {
  4580. dp_err_rl("vdev %d does not exist", vdev_id);
  4581. return QDF_STATUS_E_FAILURE;
  4582. }
  4583. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4584. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4585. return QDF_STATUS_E_FAILURE;
  4586. }
  4587. /* Average uplink delay based on current accumulated values */
  4588. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4589. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4590. *val = delay_accum / pkts_accum;
  4591. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4592. delay_accum, pkts_accum);
  4593. /* Reset accumulated values to 0 */
  4594. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4595. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4596. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4597. return QDF_STATUS_SUCCESS;
  4598. }
  4599. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4600. struct hal_tx_completion_status *ts)
  4601. {
  4602. uint32_t ul_delay;
  4603. if (qdf_unlikely(!vdev)) {
  4604. dp_info_rl("vdev is null or delete in progress");
  4605. return;
  4606. }
  4607. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4608. return;
  4609. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4610. vdev->delta_tsf,
  4611. &ul_delay)))
  4612. return;
  4613. ul_delay /= 1000; /* in unit of ms */
  4614. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4615. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4616. }
  4617. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4618. static inline
  4619. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4620. struct hal_tx_completion_status *ts)
  4621. {
  4622. }
  4623. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4624. /**
  4625. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4626. * @soc: DP soc handle
  4627. * @tx_desc: software descriptor head pointer
  4628. * @ts: Tx completion status
  4629. * @txrx_peer: txrx peer handle
  4630. * @ring_id: ring number
  4631. *
  4632. * Return: none
  4633. */
  4634. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4635. struct dp_tx_desc_s *tx_desc,
  4636. struct hal_tx_completion_status *ts,
  4637. struct dp_txrx_peer *txrx_peer,
  4638. uint8_t ring_id)
  4639. {
  4640. uint32_t length;
  4641. qdf_ether_header_t *eh;
  4642. struct dp_vdev *vdev = NULL;
  4643. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4644. enum qdf_dp_tx_rx_status dp_status;
  4645. if (!nbuf) {
  4646. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4647. goto out;
  4648. }
  4649. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4650. length = qdf_nbuf_len(nbuf);
  4651. dp_status = dp_tx_hw_to_qdf(ts->status);
  4652. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4653. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4654. QDF_TRACE_DEFAULT_PDEV_ID,
  4655. qdf_nbuf_data_addr(nbuf),
  4656. sizeof(qdf_nbuf_data(nbuf)),
  4657. tx_desc->id, ts->status, dp_status));
  4658. dp_tx_comp_debug("-------------------- \n"
  4659. "Tx Completion Stats: \n"
  4660. "-------------------- \n"
  4661. "ack_frame_rssi = %d \n"
  4662. "first_msdu = %d \n"
  4663. "last_msdu = %d \n"
  4664. "msdu_part_of_amsdu = %d \n"
  4665. "rate_stats valid = %d \n"
  4666. "bw = %d \n"
  4667. "pkt_type = %d \n"
  4668. "stbc = %d \n"
  4669. "ldpc = %d \n"
  4670. "sgi = %d \n"
  4671. "mcs = %d \n"
  4672. "ofdma = %d \n"
  4673. "tones_in_ru = %d \n"
  4674. "tsf = %d \n"
  4675. "ppdu_id = %d \n"
  4676. "transmit_cnt = %d \n"
  4677. "tid = %d \n"
  4678. "peer_id = %d\n"
  4679. "tx_status = %d\n",
  4680. ts->ack_frame_rssi, ts->first_msdu,
  4681. ts->last_msdu, ts->msdu_part_of_amsdu,
  4682. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4683. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4684. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4685. ts->transmit_cnt, ts->tid, ts->peer_id,
  4686. ts->status);
  4687. /* Update SoC level stats */
  4688. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4689. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4690. if (!txrx_peer) {
  4691. dp_info_rl("peer is null or deletion in progress");
  4692. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4693. goto out;
  4694. }
  4695. vdev = txrx_peer->vdev;
  4696. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4697. dp_tx_update_uplink_delay(soc, vdev, ts);
  4698. /* check tx complete notification */
  4699. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4700. dp_tx_notify_completion(soc, vdev, tx_desc,
  4701. nbuf, ts->status);
  4702. /* Update per-packet stats for mesh mode */
  4703. if (qdf_unlikely(vdev->mesh_vdev) &&
  4704. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4705. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4706. /* Update peer level stats */
  4707. if (qdf_unlikely(txrx_peer->bss_peer &&
  4708. vdev->opmode == wlan_op_mode_ap)) {
  4709. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4710. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4711. length);
  4712. if (txrx_peer->vdev->tx_encap_type ==
  4713. htt_cmn_pkt_type_ethernet &&
  4714. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4715. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4716. tx.bcast, 1,
  4717. length);
  4718. }
  4719. }
  4720. } else {
  4721. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4722. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4723. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4724. 1, length);
  4725. if (qdf_unlikely(txrx_peer->in_twt)) {
  4726. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4727. tx.tx_success_twt,
  4728. 1, length);
  4729. }
  4730. }
  4731. }
  4732. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4733. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4734. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4735. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4736. ts, ts->tid);
  4737. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4738. #ifdef QCA_SUPPORT_RDK_STATS
  4739. if (soc->peerstats_enabled)
  4740. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4741. qdf_ktime_to_ms(tx_desc->timestamp),
  4742. ts->ppdu_id);
  4743. #endif
  4744. out:
  4745. return;
  4746. }
  4747. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4748. defined(QCA_ENHANCED_STATS_SUPPORT)
  4749. /*
  4750. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4751. * @txrx_peer: Datapath txrx_peer handle
  4752. * @length: Length of the packet
  4753. * @tx_status: Tx status from TQM/FW
  4754. * @update: enhanced flag value present in dp_pdev
  4755. *
  4756. * Return: none
  4757. */
  4758. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4759. uint32_t length, uint8_t tx_status,
  4760. bool update)
  4761. {
  4762. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4763. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4764. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4765. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4766. }
  4767. }
  4768. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4769. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4770. uint32_t length, uint8_t tx_status,
  4771. bool update)
  4772. {
  4773. if (!txrx_peer->hw_txrx_stats_en) {
  4774. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4775. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4776. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4777. }
  4778. }
  4779. #else
  4780. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4781. uint32_t length, uint8_t tx_status,
  4782. bool update)
  4783. {
  4784. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4785. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4786. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4787. }
  4788. #endif
  4789. /*
  4790. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4791. * @nbuf: skb buffer
  4792. *
  4793. * Return: none
  4794. */
  4795. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4796. static inline
  4797. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4798. {
  4799. qdf_nbuf_t nbuf = NULL;
  4800. if (next)
  4801. nbuf = next->nbuf;
  4802. if (nbuf)
  4803. qdf_prefetch(nbuf);
  4804. }
  4805. #else
  4806. static inline
  4807. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4808. {
  4809. }
  4810. #endif
  4811. /**
  4812. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4813. * @soc: core txrx main context
  4814. * @desc: software descriptor
  4815. *
  4816. * Return: true when packet is reinjected
  4817. */
  4818. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4819. defined(WLAN_MCAST_MLO)
  4820. static inline bool
  4821. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4822. {
  4823. struct dp_vdev *vdev = NULL;
  4824. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4825. if (!soc->arch_ops.dp_tx_mcast_handler ||
  4826. !soc->arch_ops.dp_tx_is_mcast_primary)
  4827. return false;
  4828. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4829. DP_MOD_ID_REINJECT);
  4830. if (qdf_unlikely(!vdev)) {
  4831. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4832. desc->id);
  4833. return false;
  4834. }
  4835. if (!(soc->arch_ops.dp_tx_is_mcast_primary(soc, vdev))) {
  4836. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4837. return false;
  4838. }
  4839. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4840. qdf_nbuf_len(desc->nbuf));
  4841. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4842. dp_tx_desc_release(desc, desc->pool_id);
  4843. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4844. return true;
  4845. }
  4846. return false;
  4847. }
  4848. #else
  4849. static inline bool
  4850. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4851. {
  4852. return false;
  4853. }
  4854. #endif
  4855. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  4856. static inline void
  4857. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4858. {
  4859. qdf_nbuf_queue_head_init(nbuf_queue_head);
  4860. }
  4861. static inline void
  4862. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4863. struct dp_tx_desc_s *desc)
  4864. {
  4865. qdf_nbuf_t nbuf = NULL;
  4866. nbuf = desc->nbuf;
  4867. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_FAST))
  4868. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4869. else
  4870. qdf_nbuf_free(nbuf);
  4871. }
  4872. static inline void
  4873. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4874. {
  4875. qdf_nbuf_dev_kfree_list(nbuf_queue_head);
  4876. }
  4877. #else
  4878. static inline void
  4879. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4880. {
  4881. }
  4882. static inline void
  4883. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4884. struct dp_tx_desc_s *desc)
  4885. {
  4886. qdf_nbuf_free(desc->nbuf);
  4887. }
  4888. static inline void
  4889. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4890. {
  4891. }
  4892. #endif
  4893. /**
  4894. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4895. * @soc: core txrx main context
  4896. * @comp_head: software descriptor head pointer
  4897. * @ring_id: ring number
  4898. *
  4899. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4900. * and release the software descriptors after processing is complete
  4901. *
  4902. * Return: none
  4903. */
  4904. void
  4905. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4906. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4907. {
  4908. struct dp_tx_desc_s *desc;
  4909. struct dp_tx_desc_s *next;
  4910. struct hal_tx_completion_status ts;
  4911. struct dp_txrx_peer *txrx_peer = NULL;
  4912. uint16_t peer_id = DP_INVALID_PEER;
  4913. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4914. qdf_nbuf_queue_head_t h;
  4915. desc = comp_head;
  4916. dp_tx_nbuf_queue_head_init(&h);
  4917. while (desc) {
  4918. next = desc->next;
  4919. dp_tx_prefetch_next_nbuf_data(next);
  4920. if (peer_id != desc->peer_id) {
  4921. if (txrx_peer)
  4922. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4923. DP_MOD_ID_TX_COMP);
  4924. peer_id = desc->peer_id;
  4925. txrx_peer =
  4926. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4927. &txrx_ref_handle,
  4928. DP_MOD_ID_TX_COMP);
  4929. }
  4930. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4931. desc = next;
  4932. continue;
  4933. }
  4934. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4935. if (qdf_likely(txrx_peer))
  4936. dp_tx_update_peer_basic_stats(txrx_peer,
  4937. desc->length,
  4938. desc->tx_status,
  4939. false);
  4940. dp_tx_nbuf_dev_queue_free(&h, desc);
  4941. dp_ppeds_tx_desc_free(soc, desc);
  4942. desc = next;
  4943. continue;
  4944. }
  4945. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4946. struct dp_pdev *pdev = desc->pdev;
  4947. if (qdf_likely(txrx_peer))
  4948. dp_tx_update_peer_basic_stats(txrx_peer,
  4949. desc->length,
  4950. desc->tx_status,
  4951. false);
  4952. qdf_assert(pdev);
  4953. dp_tx_outstanding_dec(pdev);
  4954. /*
  4955. * Calling a QDF WRAPPER here is creating significant
  4956. * performance impact so avoided the wrapper call here
  4957. */
  4958. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4959. desc->id, DP_TX_COMP_UNMAP);
  4960. dp_tx_nbuf_unmap(soc, desc);
  4961. dp_tx_nbuf_dev_queue_free(&h, desc);
  4962. dp_tx_desc_free(soc, desc, desc->pool_id);
  4963. desc = next;
  4964. continue;
  4965. }
  4966. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4967. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4968. ring_id);
  4969. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4970. dp_tx_desc_release(desc, desc->pool_id);
  4971. desc = next;
  4972. }
  4973. dp_tx_nbuf_dev_kfree_list(&h);
  4974. if (txrx_peer)
  4975. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4976. }
  4977. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4978. static inline
  4979. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4980. int max_reap_limit)
  4981. {
  4982. bool limit_hit = false;
  4983. limit_hit =
  4984. (num_reaped >= max_reap_limit) ? true : false;
  4985. if (limit_hit)
  4986. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4987. return limit_hit;
  4988. }
  4989. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4990. {
  4991. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4992. }
  4993. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4994. {
  4995. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4996. return cfg->tx_comp_loop_pkt_limit;
  4997. }
  4998. #else
  4999. static inline
  5000. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  5001. int max_reap_limit)
  5002. {
  5003. return false;
  5004. }
  5005. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  5006. {
  5007. return false;
  5008. }
  5009. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5010. {
  5011. return 0;
  5012. }
  5013. #endif
  5014. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  5015. static inline int
  5016. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5017. int *max_reap_limit)
  5018. {
  5019. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  5020. max_reap_limit);
  5021. }
  5022. #else
  5023. static inline int
  5024. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5025. int *max_reap_limit)
  5026. {
  5027. return 0;
  5028. }
  5029. #endif
  5030. #ifdef DP_TX_TRACKING
  5031. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  5032. {
  5033. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  5034. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  5035. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  5036. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  5037. }
  5038. }
  5039. #endif
  5040. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  5041. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  5042. uint32_t quota)
  5043. {
  5044. void *tx_comp_hal_desc;
  5045. void *last_prefetched_hw_desc = NULL;
  5046. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  5047. hal_soc_handle_t hal_soc;
  5048. uint8_t buffer_src;
  5049. struct dp_tx_desc_s *tx_desc = NULL;
  5050. struct dp_tx_desc_s *head_desc = NULL;
  5051. struct dp_tx_desc_s *tail_desc = NULL;
  5052. uint32_t num_processed = 0;
  5053. uint32_t count;
  5054. uint32_t num_avail_for_reap = 0;
  5055. bool force_break = false;
  5056. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  5057. int max_reap_limit, ring_near_full;
  5058. uint32_t num_entries;
  5059. DP_HIST_INIT();
  5060. num_entries = hal_srng_get_num_entries(soc->hal_soc, hal_ring_hdl);
  5061. more_data:
  5062. hal_soc = soc->hal_soc;
  5063. /* Re-initialize local variables to be re-used */
  5064. head_desc = NULL;
  5065. tail_desc = NULL;
  5066. count = 0;
  5067. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  5068. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  5069. &max_reap_limit);
  5070. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  5071. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  5072. return 0;
  5073. }
  5074. if (!num_avail_for_reap)
  5075. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
  5076. hal_ring_hdl, 0);
  5077. if (num_avail_for_reap >= quota)
  5078. num_avail_for_reap = quota;
  5079. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  5080. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  5081. hal_ring_hdl,
  5082. num_avail_for_reap);
  5083. /* Find head descriptor from completion ring */
  5084. while (qdf_likely(num_avail_for_reap--)) {
  5085. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  5086. if (qdf_unlikely(!tx_comp_hal_desc))
  5087. break;
  5088. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  5089. tx_comp_hal_desc);
  5090. /* If this buffer was not released by TQM or FW, then it is not
  5091. * Tx completion indication, assert */
  5092. if (qdf_unlikely(buffer_src !=
  5093. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  5094. (qdf_unlikely(buffer_src !=
  5095. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  5096. uint8_t wbm_internal_error;
  5097. dp_err_rl(
  5098. "Tx comp release_src != TQM | FW but from %d",
  5099. buffer_src);
  5100. hal_dump_comp_desc(tx_comp_hal_desc);
  5101. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  5102. /* When WBM sees NULL buffer_addr_info in any of
  5103. * ingress rings it sends an error indication,
  5104. * with wbm_internal_error=1, to a specific ring.
  5105. * The WBM2SW ring used to indicate these errors is
  5106. * fixed in HW, and that ring is being used as Tx
  5107. * completion ring. These errors are not related to
  5108. * Tx completions, and should just be ignored
  5109. */
  5110. wbm_internal_error = hal_get_wbm_internal_error(
  5111. hal_soc,
  5112. tx_comp_hal_desc);
  5113. if (wbm_internal_error) {
  5114. dp_err_rl("Tx comp wbm_internal_error!!");
  5115. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  5116. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  5117. buffer_src)
  5118. dp_handle_wbm_internal_error(
  5119. soc,
  5120. tx_comp_hal_desc,
  5121. hal_tx_comp_get_buffer_type(
  5122. tx_comp_hal_desc));
  5123. } else {
  5124. dp_err_rl("Tx comp wbm_internal_error false");
  5125. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  5126. }
  5127. continue;
  5128. }
  5129. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  5130. tx_comp_hal_desc,
  5131. &tx_desc);
  5132. if (qdf_unlikely(!tx_desc)) {
  5133. dp_err("unable to retrieve tx_desc!");
  5134. hal_dump_comp_desc(tx_comp_hal_desc);
  5135. DP_STATS_INC(soc, tx.invalid_tx_comp_desc, 1);
  5136. QDF_BUG(0);
  5137. continue;
  5138. }
  5139. tx_desc->buffer_src = buffer_src;
  5140. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  5141. goto add_to_pool2;
  5142. /*
  5143. * If the release source is FW, process the HTT status
  5144. */
  5145. if (qdf_unlikely(buffer_src ==
  5146. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  5147. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  5148. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  5149. htt_tx_status);
  5150. /* Collect hw completion contents */
  5151. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5152. &tx_desc->comp, 1);
  5153. soc->arch_ops.dp_tx_process_htt_completion(
  5154. soc,
  5155. tx_desc,
  5156. htt_tx_status,
  5157. ring_id);
  5158. } else {
  5159. tx_desc->tx_status =
  5160. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  5161. tx_desc->buffer_src = buffer_src;
  5162. /*
  5163. * If the fast completion mode is enabled extended
  5164. * metadata from descriptor is not copied
  5165. */
  5166. if (qdf_likely(tx_desc->flags &
  5167. DP_TX_DESC_FLAG_SIMPLE))
  5168. goto add_to_pool;
  5169. /*
  5170. * If the descriptor is already freed in vdev_detach,
  5171. * continue to next descriptor
  5172. */
  5173. if (qdf_unlikely
  5174. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5175. !tx_desc->flags)) {
  5176. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5177. tx_desc->id);
  5178. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5179. dp_tx_desc_check_corruption(tx_desc);
  5180. continue;
  5181. }
  5182. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5183. dp_tx_comp_info_rl("pdev in down state %d",
  5184. tx_desc->id);
  5185. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5186. dp_tx_comp_free_buf(soc, tx_desc, false);
  5187. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5188. goto next_desc;
  5189. }
  5190. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5191. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5192. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5193. tx_desc->flags, tx_desc->id);
  5194. qdf_assert_always(0);
  5195. }
  5196. /* Collect hw completion contents */
  5197. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5198. &tx_desc->comp, 1);
  5199. add_to_pool:
  5200. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5201. add_to_pool2:
  5202. /* First ring descriptor on the cycle */
  5203. if (!head_desc) {
  5204. head_desc = tx_desc;
  5205. tail_desc = tx_desc;
  5206. }
  5207. tail_desc->next = tx_desc;
  5208. tx_desc->next = NULL;
  5209. tail_desc = tx_desc;
  5210. }
  5211. next_desc:
  5212. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5213. /*
  5214. * Processed packet count is more than given quota
  5215. * stop to processing
  5216. */
  5217. count++;
  5218. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5219. num_avail_for_reap,
  5220. hal_ring_hdl,
  5221. &last_prefetched_hw_desc,
  5222. &last_prefetched_sw_desc);
  5223. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5224. break;
  5225. }
  5226. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5227. /* Process the reaped descriptors */
  5228. if (head_desc)
  5229. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5230. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5231. /*
  5232. * If we are processing in near-full condition, there are 3 scenario
  5233. * 1) Ring entries has reached critical state
  5234. * 2) Ring entries are still near high threshold
  5235. * 3) Ring entries are below the safe level
  5236. *
  5237. * One more loop will move the state to normal processing and yield
  5238. */
  5239. if (ring_near_full)
  5240. goto more_data;
  5241. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5242. if (num_processed >= quota)
  5243. force_break = true;
  5244. if (!force_break &&
  5245. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5246. hal_ring_hdl)) {
  5247. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5248. if (!hif_exec_should_yield(soc->hif_handle,
  5249. int_ctx->dp_intr_id))
  5250. goto more_data;
  5251. num_avail_for_reap =
  5252. hal_srng_dst_num_valid_locked(soc->hal_soc,
  5253. hal_ring_hdl,
  5254. true);
  5255. if (qdf_unlikely(num_entries &&
  5256. (num_avail_for_reap >=
  5257. num_entries >> 1))) {
  5258. DP_STATS_INC(soc, tx.near_full, 1);
  5259. goto more_data;
  5260. }
  5261. }
  5262. }
  5263. DP_TX_HIST_STATS_PER_PDEV();
  5264. return num_processed;
  5265. }
  5266. #ifdef FEATURE_WLAN_TDLS
  5267. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5268. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5269. {
  5270. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5271. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5272. DP_MOD_ID_TDLS);
  5273. if (!vdev) {
  5274. dp_err("vdev handle for id %d is NULL", vdev_id);
  5275. return NULL;
  5276. }
  5277. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5278. vdev->is_tdls_frame = true;
  5279. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5280. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5281. }
  5282. #endif
  5283. /**
  5284. * dp_tx_vdev_attach() - attach vdev to dp tx
  5285. * @vdev: virtual device instance
  5286. *
  5287. * Return: QDF_STATUS_SUCCESS: success
  5288. * QDF_STATUS_E_RESOURCES: Error return
  5289. */
  5290. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5291. {
  5292. int pdev_id;
  5293. /*
  5294. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5295. */
  5296. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5297. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5298. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5299. vdev->vdev_id);
  5300. pdev_id =
  5301. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5302. vdev->pdev->pdev_id);
  5303. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5304. /*
  5305. * Set HTT Extension Valid bit to 0 by default
  5306. */
  5307. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5308. dp_tx_vdev_update_search_flags(vdev);
  5309. return QDF_STATUS_SUCCESS;
  5310. }
  5311. #ifndef FEATURE_WDS
  5312. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5313. {
  5314. return false;
  5315. }
  5316. #endif
  5317. /**
  5318. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  5319. * @vdev: virtual device instance
  5320. *
  5321. * Return: void
  5322. *
  5323. */
  5324. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5325. {
  5326. struct dp_soc *soc = vdev->pdev->soc;
  5327. /*
  5328. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5329. * for TDLS link
  5330. *
  5331. * Enable AddrY (SA based search) only for non-WDS STA and
  5332. * ProxySTA VAP (in HKv1) modes.
  5333. *
  5334. * In all other VAP modes, only DA based search should be
  5335. * enabled
  5336. */
  5337. if (vdev->opmode == wlan_op_mode_sta &&
  5338. vdev->tdls_link_connected)
  5339. vdev->hal_desc_addr_search_flags =
  5340. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5341. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5342. !dp_tx_da_search_override(vdev))
  5343. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5344. else
  5345. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5346. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5347. vdev->search_type = soc->sta_mode_search_policy;
  5348. else
  5349. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5350. }
  5351. static inline bool
  5352. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5353. struct dp_vdev *vdev,
  5354. struct dp_tx_desc_s *tx_desc)
  5355. {
  5356. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5357. return false;
  5358. /*
  5359. * if vdev is given, then only check whether desc
  5360. * vdev match. if vdev is NULL, then check whether
  5361. * desc pdev match.
  5362. */
  5363. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5364. (tx_desc->pdev == pdev);
  5365. }
  5366. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5367. /**
  5368. * dp_tx_desc_flush() - release resources associated
  5369. * to TX Desc
  5370. *
  5371. * @dp_pdev: Handle to DP pdev structure
  5372. * @vdev: virtual device instance
  5373. * NULL: no specific Vdev is required and check all allcated TX desc
  5374. * on this pdev.
  5375. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  5376. *
  5377. * @force_free:
  5378. * true: flush the TX desc.
  5379. * false: only reset the Vdev in each allocated TX desc
  5380. * that associated to current Vdev.
  5381. *
  5382. * This function will go through the TX desc pool to flush
  5383. * the outstanding TX data or reset Vdev to NULL in associated TX
  5384. * Desc.
  5385. */
  5386. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5387. bool force_free)
  5388. {
  5389. uint8_t i;
  5390. uint32_t j;
  5391. uint32_t num_desc, page_id, offset;
  5392. uint16_t num_desc_per_page;
  5393. struct dp_soc *soc = pdev->soc;
  5394. struct dp_tx_desc_s *tx_desc = NULL;
  5395. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5396. if (!vdev && !force_free) {
  5397. dp_err("Reset TX desc vdev, Vdev param is required!");
  5398. return;
  5399. }
  5400. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5401. tx_desc_pool = &soc->tx_desc[i];
  5402. if (!(tx_desc_pool->pool_size) ||
  5403. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5404. !(tx_desc_pool->desc_pages.cacheable_pages))
  5405. continue;
  5406. /*
  5407. * Add flow pool lock protection in case pool is freed
  5408. * due to all tx_desc is recycled when handle TX completion.
  5409. * this is not necessary when do force flush as:
  5410. * a. double lock will happen if dp_tx_desc_release is
  5411. * also trying to acquire it.
  5412. * b. dp interrupt has been disabled before do force TX desc
  5413. * flush in dp_pdev_deinit().
  5414. */
  5415. if (!force_free)
  5416. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5417. num_desc = tx_desc_pool->pool_size;
  5418. num_desc_per_page =
  5419. tx_desc_pool->desc_pages.num_element_per_page;
  5420. for (j = 0; j < num_desc; j++) {
  5421. page_id = j / num_desc_per_page;
  5422. offset = j % num_desc_per_page;
  5423. if (qdf_unlikely(!(tx_desc_pool->
  5424. desc_pages.cacheable_pages)))
  5425. break;
  5426. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5427. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5428. /*
  5429. * Free TX desc if force free is
  5430. * required, otherwise only reset vdev
  5431. * in this TX desc.
  5432. */
  5433. if (force_free) {
  5434. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5435. dp_tx_comp_free_buf(soc, tx_desc,
  5436. false);
  5437. dp_tx_desc_release(tx_desc, i);
  5438. } else {
  5439. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5440. }
  5441. }
  5442. }
  5443. if (!force_free)
  5444. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5445. }
  5446. }
  5447. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5448. /**
  5449. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5450. *
  5451. * @soc: Handle to DP soc structure
  5452. * @tx_desc: pointer of one TX desc
  5453. * @desc_pool_id: TX Desc pool id
  5454. */
  5455. static inline void
  5456. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5457. uint8_t desc_pool_id)
  5458. {
  5459. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5460. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5461. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5462. }
  5463. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5464. bool force_free)
  5465. {
  5466. uint8_t i, num_pool;
  5467. uint32_t j;
  5468. uint32_t num_desc, page_id, offset;
  5469. uint16_t num_desc_per_page;
  5470. struct dp_soc *soc = pdev->soc;
  5471. struct dp_tx_desc_s *tx_desc = NULL;
  5472. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5473. if (!vdev && !force_free) {
  5474. dp_err("Reset TX desc vdev, Vdev param is required!");
  5475. return;
  5476. }
  5477. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5478. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5479. for (i = 0; i < num_pool; i++) {
  5480. tx_desc_pool = &soc->tx_desc[i];
  5481. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5482. continue;
  5483. num_desc_per_page =
  5484. tx_desc_pool->desc_pages.num_element_per_page;
  5485. for (j = 0; j < num_desc; j++) {
  5486. page_id = j / num_desc_per_page;
  5487. offset = j % num_desc_per_page;
  5488. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5489. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5490. if (force_free) {
  5491. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5492. dp_tx_comp_free_buf(soc, tx_desc,
  5493. false);
  5494. dp_tx_desc_release(tx_desc, i);
  5495. } else {
  5496. dp_tx_desc_reset_vdev(soc, tx_desc,
  5497. i);
  5498. }
  5499. }
  5500. }
  5501. }
  5502. }
  5503. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5504. /**
  5505. * dp_tx_vdev_detach() - detach vdev from dp tx
  5506. * @vdev: virtual device instance
  5507. *
  5508. * Return: QDF_STATUS_SUCCESS: success
  5509. * QDF_STATUS_E_RESOURCES: Error return
  5510. */
  5511. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5512. {
  5513. struct dp_pdev *pdev = vdev->pdev;
  5514. /* Reset TX desc associated to this Vdev as NULL */
  5515. dp_tx_desc_flush(pdev, vdev, false);
  5516. return QDF_STATUS_SUCCESS;
  5517. }
  5518. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5519. /* Pools will be allocated dynamically */
  5520. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5521. int num_desc)
  5522. {
  5523. uint8_t i;
  5524. for (i = 0; i < num_pool; i++) {
  5525. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5526. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5527. }
  5528. return QDF_STATUS_SUCCESS;
  5529. }
  5530. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5531. uint32_t num_desc)
  5532. {
  5533. return QDF_STATUS_SUCCESS;
  5534. }
  5535. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5536. {
  5537. }
  5538. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5539. {
  5540. uint8_t i;
  5541. for (i = 0; i < num_pool; i++)
  5542. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5543. }
  5544. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5545. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5546. uint32_t num_desc)
  5547. {
  5548. uint8_t i, count;
  5549. /* Allocate software Tx descriptor pools */
  5550. for (i = 0; i < num_pool; i++) {
  5551. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5552. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5553. FL("Tx Desc Pool alloc %d failed %pK"),
  5554. i, soc);
  5555. goto fail;
  5556. }
  5557. }
  5558. return QDF_STATUS_SUCCESS;
  5559. fail:
  5560. for (count = 0; count < i; count++)
  5561. dp_tx_desc_pool_free(soc, count);
  5562. return QDF_STATUS_E_NOMEM;
  5563. }
  5564. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5565. uint32_t num_desc)
  5566. {
  5567. uint8_t i;
  5568. for (i = 0; i < num_pool; i++) {
  5569. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5570. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5571. FL("Tx Desc Pool init %d failed %pK"),
  5572. i, soc);
  5573. return QDF_STATUS_E_NOMEM;
  5574. }
  5575. }
  5576. return QDF_STATUS_SUCCESS;
  5577. }
  5578. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5579. {
  5580. uint8_t i;
  5581. for (i = 0; i < num_pool; i++)
  5582. dp_tx_desc_pool_deinit(soc, i);
  5583. }
  5584. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5585. {
  5586. uint8_t i;
  5587. for (i = 0; i < num_pool; i++)
  5588. dp_tx_desc_pool_free(soc, i);
  5589. }
  5590. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5591. /**
  5592. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5593. * @soc: core txrx main context
  5594. * @num_pool: number of pools
  5595. *
  5596. */
  5597. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5598. {
  5599. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5600. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5601. }
  5602. /**
  5603. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5604. * @soc: core txrx main context
  5605. * @num_pool: number of pools
  5606. *
  5607. */
  5608. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5609. {
  5610. dp_tx_tso_desc_pool_free(soc, num_pool);
  5611. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5612. }
  5613. /**
  5614. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5615. * @soc: core txrx main context
  5616. *
  5617. * This function frees all tx related descriptors as below
  5618. * 1. Regular TX descriptors (static pools)
  5619. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5620. * 3. TSO descriptors
  5621. *
  5622. */
  5623. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5624. {
  5625. uint8_t num_pool;
  5626. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5627. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5628. dp_tx_ext_desc_pool_free(soc, num_pool);
  5629. dp_tx_delete_static_pools(soc, num_pool);
  5630. }
  5631. /**
  5632. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5633. * @soc: core txrx main context
  5634. *
  5635. * This function de-initializes all tx related descriptors as below
  5636. * 1. Regular TX descriptors (static pools)
  5637. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5638. * 3. TSO descriptors
  5639. *
  5640. */
  5641. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5642. {
  5643. uint8_t num_pool;
  5644. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5645. dp_tx_flow_control_deinit(soc);
  5646. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5647. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5648. dp_tx_deinit_static_pools(soc, num_pool);
  5649. }
  5650. /**
  5651. * dp_tso_attach() - TSO attach handler
  5652. * @txrx_soc: Opaque Dp handle
  5653. *
  5654. * Reserve TSO descriptor buffers
  5655. *
  5656. * Return: QDF_STATUS_E_FAILURE on failure or
  5657. * QDF_STATUS_SUCCESS on success
  5658. */
  5659. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5660. uint8_t num_pool,
  5661. uint32_t num_desc)
  5662. {
  5663. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5664. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5665. return QDF_STATUS_E_FAILURE;
  5666. }
  5667. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5668. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5669. num_pool, soc);
  5670. return QDF_STATUS_E_FAILURE;
  5671. }
  5672. return QDF_STATUS_SUCCESS;
  5673. }
  5674. /**
  5675. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5676. * @soc: DP soc handle
  5677. * @num_pool: Number of pools
  5678. * @num_desc: Number of descriptors
  5679. *
  5680. * Initialize TSO descriptor pools
  5681. *
  5682. * Return: QDF_STATUS_E_FAILURE on failure or
  5683. * QDF_STATUS_SUCCESS on success
  5684. */
  5685. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5686. uint8_t num_pool,
  5687. uint32_t num_desc)
  5688. {
  5689. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5690. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5691. return QDF_STATUS_E_FAILURE;
  5692. }
  5693. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5694. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5695. num_pool, soc);
  5696. return QDF_STATUS_E_FAILURE;
  5697. }
  5698. return QDF_STATUS_SUCCESS;
  5699. }
  5700. /**
  5701. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5702. * @soc: core txrx main context
  5703. *
  5704. * This function allocates memory for following descriptor pools
  5705. * 1. regular sw tx descriptor pools (static pools)
  5706. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5707. * 3. TSO descriptor pools
  5708. *
  5709. * Return: QDF_STATUS_SUCCESS: success
  5710. * QDF_STATUS_E_RESOURCES: Error return
  5711. */
  5712. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5713. {
  5714. uint8_t num_pool;
  5715. uint32_t num_desc;
  5716. uint32_t num_ext_desc;
  5717. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5718. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5719. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5720. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5721. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5722. __func__, num_pool, num_desc);
  5723. if ((num_pool > MAX_TXDESC_POOLS) ||
  5724. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5725. goto fail1;
  5726. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5727. goto fail1;
  5728. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5729. goto fail2;
  5730. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5731. return QDF_STATUS_SUCCESS;
  5732. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5733. goto fail3;
  5734. return QDF_STATUS_SUCCESS;
  5735. fail3:
  5736. dp_tx_ext_desc_pool_free(soc, num_pool);
  5737. fail2:
  5738. dp_tx_delete_static_pools(soc, num_pool);
  5739. fail1:
  5740. return QDF_STATUS_E_RESOURCES;
  5741. }
  5742. /**
  5743. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5744. * @soc: core txrx main context
  5745. *
  5746. * This function initializes the following TX descriptor pools
  5747. * 1. regular sw tx descriptor pools (static pools)
  5748. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5749. * 3. TSO descriptor pools
  5750. *
  5751. * Return: QDF_STATUS_SUCCESS: success
  5752. * QDF_STATUS_E_RESOURCES: Error return
  5753. */
  5754. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5755. {
  5756. uint8_t num_pool;
  5757. uint32_t num_desc;
  5758. uint32_t num_ext_desc;
  5759. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5760. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5761. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5762. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5763. goto fail1;
  5764. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5765. goto fail2;
  5766. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5767. return QDF_STATUS_SUCCESS;
  5768. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5769. goto fail3;
  5770. dp_tx_flow_control_init(soc);
  5771. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5772. return QDF_STATUS_SUCCESS;
  5773. fail3:
  5774. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5775. fail2:
  5776. dp_tx_deinit_static_pools(soc, num_pool);
  5777. fail1:
  5778. return QDF_STATUS_E_RESOURCES;
  5779. }
  5780. /**
  5781. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5782. * @txrx_soc: dp soc handle
  5783. *
  5784. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5785. * QDF_STATUS_E_FAILURE
  5786. */
  5787. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5788. {
  5789. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5790. uint8_t num_pool;
  5791. uint32_t num_desc;
  5792. uint32_t num_ext_desc;
  5793. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5794. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5795. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5796. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5797. return QDF_STATUS_E_FAILURE;
  5798. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5799. return QDF_STATUS_E_FAILURE;
  5800. return QDF_STATUS_SUCCESS;
  5801. }
  5802. /**
  5803. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5804. * @txrx_soc: dp soc handle
  5805. *
  5806. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5807. */
  5808. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5809. {
  5810. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5811. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5812. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5813. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5814. return QDF_STATUS_SUCCESS;
  5815. }
  5816. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5817. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5818. enum qdf_pkt_timestamp_index index, uint64_t time,
  5819. qdf_nbuf_t nbuf)
  5820. {
  5821. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5822. uint64_t tsf_time;
  5823. if (vdev->get_tsf_time) {
  5824. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5825. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5826. }
  5827. }
  5828. }
  5829. void dp_pkt_get_timestamp(uint64_t *time)
  5830. {
  5831. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5832. *time = qdf_get_log_timestamp();
  5833. }
  5834. #endif