dp_be.h 24 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef __DP_BE_H
  20. #define __DP_BE_H
  21. #include <dp_types.h>
  22. #include <hal_be_tx.h>
  23. #ifdef WLAN_MLO_MULTI_CHIP
  24. #include "mlo/dp_mlo.h"
  25. #else
  26. #include <dp_peer.h>
  27. #endif
  28. #ifdef WIFI_MONITOR_SUPPORT
  29. #include <dp_mon.h>
  30. #endif
  31. enum CMEM_MEM_CLIENTS {
  32. COOKIE_CONVERSION,
  33. FISA_FST,
  34. };
  35. /* maximum number of entries in one page of secondary page table */
  36. #define DP_CC_SPT_PAGE_MAX_ENTRIES 512
  37. /* maximum number of entries in one page of secondary page table */
  38. #define DP_CC_SPT_PAGE_MAX_ENTRIES_MASK (DP_CC_SPT_PAGE_MAX_ENTRIES - 1)
  39. /* maximum number of entries in primary page table */
  40. #define DP_CC_PPT_MAX_ENTRIES 1024
  41. /* cookie conversion required CMEM offset from CMEM pool */
  42. #define DP_CC_MEM_OFFSET_IN_CMEM 0
  43. /* cookie conversion primary page table size 4K */
  44. #define DP_CC_PPT_MEM_SIZE 4096
  45. /* FST required CMEM offset from CMEM pool */
  46. #define DP_FST_MEM_OFFSET_IN_CMEM \
  47. (DP_CC_MEM_OFFSET_IN_CMEM + DP_CC_PPT_MEM_SIZE)
  48. /* CMEM size for FISA FST 16K */
  49. #define DP_CMEM_FST_SIZE 16384
  50. /* lower 9 bits in Desc ID for offset in page of SPT */
  51. #define DP_CC_DESC_ID_SPT_VA_OS_SHIFT 0
  52. #define DP_CC_DESC_ID_SPT_VA_OS_MASK 0x1FF
  53. #define DP_CC_DESC_ID_SPT_VA_OS_LSB 0
  54. #define DP_CC_DESC_ID_SPT_VA_OS_MSB 8
  55. /* higher 11 bits in Desc ID for offset in CMEM of PPT */
  56. #define DP_CC_DESC_ID_PPT_PAGE_OS_LSB 9
  57. #define DP_CC_DESC_ID_PPT_PAGE_OS_MSB 19
  58. #define DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT 9
  59. #define DP_CC_DESC_ID_PPT_PAGE_OS_MASK 0xFFE00
  60. /*
  61. * page 4K unaligned case, single SPT page physical address
  62. * need 8 bytes in PPT
  63. */
  64. #define DP_CC_PPT_ENTRY_SIZE_4K_UNALIGNED 8
  65. /*
  66. * page 4K aligned case, single SPT page physical address
  67. * need 4 bytes in PPT
  68. */
  69. #define DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED 4
  70. /* 4K aligned case, number of bits HW append for one PPT entry value */
  71. #define DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED 12
  72. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  73. /* WBM2SW ring id for rx release */
  74. #define WBM2SW_REL_ERR_RING_NUM 3
  75. #else
  76. /* WBM2SW ring id for rx release */
  77. #define WBM2SW_REL_ERR_RING_NUM 5
  78. #endif
  79. #ifdef WLAN_SUPPORT_PPEDS
  80. /* The MAX PPE PRI2TID */
  81. #define DP_TX_INT_PRI2TID_MAX 15
  82. #define DP_TX_PPEDS_POOL_ID 0
  83. /* size of CMEM needed for a ppeds tx desc pool */
  84. #define DP_TX_PPEDS_DESC_POOL_CMEM_SIZE \
  85. ((WLAN_CFG_NUM_PPEDS_TX_DESC_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \
  86. DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
  87. /* Offset of ppeds tx descripotor pool */
  88. #define DP_TX_PPEDS_DESC_CMEM_OFFSET 0
  89. #define PEER_ROUTING_USE_PPE 1
  90. #define PEER_ROUTING_ENABLED 1
  91. #define DP_PPE_INTR_STRNG_LEN 32
  92. #define DP_PPE_INTR_MAX 3
  93. #else
  94. #define DP_TX_PPEDS_DESC_CMEM_OFFSET 0
  95. #define DP_TX_PPEDS_DESC_POOL_CMEM_SIZE 0
  96. #define DP_PPE_INTR_STRNG_LEN 0
  97. #define DP_PPE_INTR_MAX 0
  98. #endif
  99. /* tx descriptor are programmed at start of CMEM region*/
  100. #define DP_TX_DESC_CMEM_OFFSET \
  101. (DP_TX_PPEDS_DESC_CMEM_OFFSET + DP_TX_PPEDS_DESC_POOL_CMEM_SIZE)
  102. /* size of CMEM needed for a tx desc pool*/
  103. #define DP_TX_DESC_POOL_CMEM_SIZE \
  104. ((WLAN_CFG_NUM_TX_DESC_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \
  105. DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
  106. /* Offset of rx descripotor pool */
  107. #define DP_RX_DESC_CMEM_OFFSET \
  108. DP_TX_DESC_CMEM_OFFSET + (MAX_TXDESC_POOLS * DP_TX_DESC_POOL_CMEM_SIZE)
  109. /* size of CMEM needed for a rx desc pool */
  110. #define DP_RX_DESC_POOL_CMEM_SIZE \
  111. ((WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \
  112. DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
  113. /* get ppt_id from CMEM_OFFSET */
  114. #define DP_CMEM_OFFSET_TO_PPT_ID(offset) \
  115. ((offset) / DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
  116. /**
  117. * struct dp_spt_page_desc - secondary page table page descriptors
  118. * @next: pointer to next linked SPT page Desc
  119. * @page_v_addr: page virtual address
  120. * @page_p_addr: page physical address
  121. * @ppt_index: entry index in primary page table where this page physical
  122. address stored
  123. * @avail_entry_index: index for available entry that store TX/RX Desc VA
  124. */
  125. struct dp_spt_page_desc {
  126. uint8_t *page_v_addr;
  127. qdf_dma_addr_t page_p_addr;
  128. uint32_t ppt_index;
  129. };
  130. /**
  131. * struct dp_hw_cookie_conversion_t - main context for HW cookie conversion
  132. * @cmem_offset: CMEM offset from base address for primary page table setup
  133. * @total_page_num: total DDR page allocated
  134. * @page_desc_freelist: available page Desc list
  135. * @page_desc_base: page Desc buffer base address.
  136. * @page_pool: DDR pages pool
  137. * @cc_lock: locks for page acquiring/free
  138. */
  139. struct dp_hw_cookie_conversion_t {
  140. uint32_t cmem_offset;
  141. uint32_t total_page_num;
  142. struct dp_spt_page_desc *page_desc_base;
  143. struct qdf_mem_multi_page_t page_pool;
  144. qdf_spinlock_t cc_lock;
  145. };
  146. /**
  147. * struct dp_spt_page_desc_list - containor of SPT page desc list info
  148. * @spt_page_list_head: head of SPT page descriptor list
  149. * @spt_page_list_tail: tail of SPT page descriptor list
  150. * @num_spt_pages: number of SPT page descriptor allocated
  151. */
  152. struct dp_spt_page_desc_list {
  153. struct dp_spt_page_desc *spt_page_list_head;
  154. struct dp_spt_page_desc *spt_page_list_tail;
  155. uint16_t num_spt_pages;
  156. };
  157. /* HW reading 8 bytes for VA */
  158. #define DP_CC_HW_READ_BYTES 8
  159. #define DP_CC_SPT_PAGE_UPDATE_VA(_page_base_va, _index, _desc_va) \
  160. { *((uintptr_t *)((_page_base_va) + (_index) * DP_CC_HW_READ_BYTES)) \
  161. = (uintptr_t)(_desc_va); }
  162. /**
  163. * struct dp_tx_bank_profile - DP wrapper for TCL banks
  164. * @is_configured: flag indicating if this bank is configured
  165. * @ref_count: ref count indicating number of users of the bank
  166. * @bank_config: HAL TX bank configuration
  167. */
  168. struct dp_tx_bank_profile {
  169. uint8_t is_configured;
  170. qdf_atomic_t ref_count;
  171. union hal_tx_bank_config bank_config;
  172. };
  173. #ifdef WLAN_SUPPORT_PPEDS
  174. /**
  175. * struct dp_ppe_vp_tbl_entry - PPE Virtual table entry
  176. * @is_configured: Boolean that the entry is configured.
  177. */
  178. struct dp_ppe_vp_tbl_entry {
  179. bool is_configured;
  180. };
  181. /**
  182. * struct dp_ppe_vp_profile - PPE direct switch profiler per vdev
  183. * @vp_num: Virtual port number
  184. * @ppe_vp_num_idx: Index to the PPE VP table entry
  185. * @search_idx_reg_num: Address search Index register number
  186. * @drop_prec_enable: Drop precedance enable
  187. * @to_fw: To FW exception enable/disable.
  188. * @use_ppe_int_pri: Use PPE INT_PRI to TID mapping table
  189. */
  190. struct dp_ppe_vp_profile {
  191. uint8_t vp_num;
  192. uint8_t ppe_vp_num_idx;
  193. uint8_t search_idx_reg_num;
  194. uint8_t drop_prec_enable;
  195. uint8_t to_fw;
  196. uint8_t use_ppe_int_pri;
  197. };
  198. /**
  199. * struct dp_ppeds_tx_desc_pool_s - PPEDS Tx Descriptor Pool
  200. * @elem_size: Size of each descriptor
  201. * @num_allocated: Number of used descriptors
  202. * @freelist: Chain of free descriptors
  203. * @desc_pages: multiple page allocation information for actual descriptors
  204. * @elem_count: Number of descriptors in the pool
  205. * @num_free: Number of free descriptors
  206. * @lock- Lock for descriptor allocation/free from/to the pool
  207. */
  208. struct dp_ppeds_tx_desc_pool_s {
  209. uint16_t elem_size;
  210. uint32_t num_allocated;
  211. struct dp_tx_desc_s *freelist;
  212. struct qdf_mem_multi_page_t desc_pages;
  213. uint16_t elem_count;
  214. uint32_t num_free;
  215. qdf_spinlock_t lock;
  216. };
  217. #endif
  218. /**
  219. * struct dp_ppeds_napi - napi parameters for ppe ds
  220. * @napi: napi structure to register with napi infra
  221. * @ndev: net_dev structure
  222. */
  223. struct dp_ppeds_napi {
  224. struct napi_struct napi;
  225. struct net_device ndev;
  226. };
  227. /**
  228. * struct dp_soc_be - Extended DP soc for BE targets
  229. * @soc: dp soc structure
  230. * @num_bank_profiles: num TX bank profiles
  231. * @bank_profiles: bank profiles for various TX banks
  232. * @cc_cmem_base: cmem offset reserved for CC
  233. * @tx_cc_ctx: Cookie conversion context for tx desc pools
  234. * @rx_cc_ctx: Cookie conversion context for rx desc pools
  235. * @monitor_soc_be: BE specific monitor object
  236. * @mlo_enabled: Flag to indicate MLO is enabled or not
  237. * @mlo_chip_id: MLO chip_id
  238. * @ml_ctxt: pointer to global ml_context
  239. * @delta_tqm: delta_tqm
  240. * @mlo_tstamp_offset: mlo timestamp offset
  241. * @mld_peer_hash: peer hash table for ML peers
  242. * Associated peer with this MAC address)
  243. * @mld_peer_hash_lock: lock to protect mld_peer_hash
  244. * @ppe_ds_int_mode_enabled: PPE DS interrupt mode enabled
  245. * @reo2ppe_ring: REO2PPE ring
  246. * @ppe2tcl_ring: PPE2TCL ring
  247. * @ppe_vp_tbl: PPE VP table
  248. * @ppe_vp_tbl_lock: PPE VP table lock
  249. * @num_ppe_vp_entries : Number of PPE VP entries
  250. * @ipa_bank_id: TCL bank id used by IPA
  251. * @ppeds_tx_cc_ctx: Cookie conversion context for ppeds tx desc pool
  252. * @ppeds_tx_desc: PPEDS tx desc pool
  253. * @ppeds_handle: PPEDS soc instance handle
  254. */
  255. struct dp_soc_be {
  256. struct dp_soc soc;
  257. uint8_t num_bank_profiles;
  258. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  259. qdf_mutex_t tx_bank_lock;
  260. #else
  261. qdf_spinlock_t tx_bank_lock;
  262. #endif
  263. struct dp_tx_bank_profile *bank_profiles;
  264. struct dp_spt_page_desc *page_desc_base;
  265. uint32_t cc_cmem_base;
  266. struct dp_hw_cookie_conversion_t tx_cc_ctx[MAX_TXDESC_POOLS];
  267. struct dp_hw_cookie_conversion_t rx_cc_ctx[MAX_RXDESC_POOLS];
  268. #ifdef WLAN_SUPPORT_PPEDS
  269. uint8_t ppeds_int_mode_enabled:1,
  270. ppeds_stopped:1;
  271. struct dp_srng reo2ppe_ring;
  272. struct dp_srng ppe2tcl_ring;
  273. struct dp_srng ppeds_wbm_release_ring;
  274. struct dp_ppe_vp_tbl_entry *ppe_vp_tbl;
  275. struct dp_hw_cookie_conversion_t ppeds_tx_cc_ctx;
  276. struct dp_ppeds_tx_desc_pool_s ppeds_tx_desc;
  277. struct dp_ppeds_napi ppeds_napi_ctxt;
  278. void *ppeds_handle;
  279. qdf_mutex_t ppe_vp_tbl_lock;
  280. uint8_t num_ppe_vp_entries;
  281. char irq_name[DP_PPE_INTR_MAX][DP_PPE_INTR_STRNG_LEN];
  282. #endif
  283. #ifdef WLAN_FEATURE_11BE_MLO
  284. #ifdef WLAN_MLO_MULTI_CHIP
  285. uint8_t mlo_enabled;
  286. uint8_t mlo_chip_id;
  287. struct dp_mlo_ctxt *ml_ctxt;
  288. uint64_t delta_tqm;
  289. uint64_t mlo_tstamp_offset;
  290. #else
  291. /* Protect mld peer hash table */
  292. DP_MUTEX_TYPE mld_peer_hash_lock;
  293. struct {
  294. uint32_t mask;
  295. uint32_t idx_bits;
  296. TAILQ_HEAD(, dp_peer) * bins;
  297. } mld_peer_hash;
  298. #endif
  299. #endif
  300. #ifdef IPA_OFFLOAD
  301. int8_t ipa_bank_id;
  302. #endif
  303. };
  304. /* convert struct dp_soc_be pointer to struct dp_soc pointer */
  305. #define DP_SOC_BE_GET_SOC(be_soc) ((struct dp_soc *)be_soc)
  306. /**
  307. * struct dp_pdev_be - Extended DP pdev for BE targets
  308. * @pdev: dp pdev structure
  309. * @monitor_pdev_be: BE specific monitor object
  310. * @mlo_link_id: MLO link id for PDEV
  311. * @delta_tsf2: delta_tsf2
  312. */
  313. struct dp_pdev_be {
  314. struct dp_pdev pdev;
  315. #ifdef WLAN_MLO_MULTI_CHIP
  316. uint8_t mlo_link_id;
  317. uint64_t delta_tsf2;
  318. #endif
  319. };
  320. /**
  321. * struct dp_vdev_be - Extended DP vdev for BE targets
  322. * @vdev: dp vdev structure
  323. * @bank_id: bank_id to be used for TX
  324. * @vdev_id_check_en: flag if HW vdev_id check is enabled for vdev
  325. * @ppe_vp_enabled: flag to check if PPE VP is enabled for vdev
  326. * @ppe_vp_profile: PPE VP profile
  327. */
  328. struct dp_vdev_be {
  329. struct dp_vdev vdev;
  330. int8_t bank_id;
  331. uint8_t vdev_id_check_en;
  332. #ifdef WLAN_MLO_MULTI_CHIP
  333. /* partner list used for Intra-BSS */
  334. uint8_t partner_vdev_list[WLAN_MAX_MLO_CHIPS][WLAN_MAX_MLO_LINKS_PER_SOC];
  335. #ifdef WLAN_FEATURE_11BE_MLO
  336. #ifdef WLAN_MCAST_MLO
  337. /* DP MLO seq number */
  338. uint16_t seq_num;
  339. /* MLO Mcast primary vdev */
  340. bool mcast_primary;
  341. #endif
  342. #endif
  343. #endif
  344. unsigned long ppe_vp_enabled;
  345. #ifdef WLAN_SUPPORT_PPEDS
  346. struct dp_ppe_vp_profile ppe_vp_profile;
  347. #endif
  348. };
  349. /**
  350. * struct dp_peer_be - Extended DP peer for BE targets
  351. * @dp_peer: dp peer structure
  352. */
  353. struct dp_peer_be {
  354. struct dp_peer peer;
  355. #ifdef WLAN_SUPPORT_PPEDS
  356. uint8_t priority_valid;
  357. #endif
  358. };
  359. /**
  360. * dp_get_soc_context_size_be() - get context size for target specific DP soc
  361. *
  362. * Return: value in bytes for BE specific soc structure
  363. */
  364. qdf_size_t dp_get_soc_context_size_be(void);
  365. /**
  366. * dp_initialize_arch_ops_be() - initialize BE specific arch ops
  367. * @arch_ops: arch ops pointer
  368. *
  369. * Return: none
  370. */
  371. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops);
  372. /**
  373. * dp_get_context_size_be() - get BE specific size for peer/vdev/pdev/soc
  374. * @arch_ops: arch ops pointer
  375. *
  376. * Return: size in bytes for the context_type
  377. */
  378. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type);
  379. /**
  380. * dp_get_be_soc_from_dp_soc() - get dp_soc_be from dp_soc
  381. * @soc: dp_soc pointer
  382. *
  383. * Return: dp_soc_be pointer
  384. */
  385. static inline struct dp_soc_be *dp_get_be_soc_from_dp_soc(struct dp_soc *soc)
  386. {
  387. return (struct dp_soc_be *)soc;
  388. }
  389. #ifdef WLAN_MLO_MULTI_CHIP
  390. typedef struct dp_mlo_ctxt *dp_mld_peer_hash_obj_t;
  391. /*
  392. * dp_mlo_get_peer_hash_obj() - return the container struct of MLO hash table
  393. *
  394. * @soc: soc handle
  395. *
  396. * return: MLD peer hash object
  397. */
  398. static inline dp_mld_peer_hash_obj_t
  399. dp_mlo_get_peer_hash_obj(struct dp_soc *soc)
  400. {
  401. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  402. return be_soc->ml_ctxt;
  403. }
  404. void dp_clr_mlo_ptnr_list(struct dp_soc *soc, struct dp_vdev *vdev);
  405. #if defined(WLAN_FEATURE_11BE_MLO)
  406. /**
  407. * dp_mlo_partner_chips_map() - Map MLO peers to partner SOCs
  408. * @soc: Soc handle
  409. * @peer: DP peer handle for ML peer
  410. * @peer_id: peer_id
  411. * Return: None
  412. */
  413. void dp_mlo_partner_chips_map(struct dp_soc *soc,
  414. struct dp_peer *peer,
  415. uint16_t peer_id);
  416. /**
  417. * dp_mlo_partner_chips_unmap() - Unmap MLO peers to partner SOCs
  418. * @soc: Soc handle
  419. * @peer_id: peer_id
  420. * Return: None
  421. */
  422. void dp_mlo_partner_chips_unmap(struct dp_soc *soc,
  423. uint16_t peer_id);
  424. #ifdef WLAN_MCAST_MLO
  425. typedef void dp_ptnr_vdev_iter_func(struct dp_vdev_be *be_vdev,
  426. struct dp_vdev *ptnr_vdev,
  427. void *arg);
  428. typedef void dp_ptnr_soc_iter_func(struct dp_soc *ptnr_soc,
  429. void *arg);
  430. /*
  431. * dp_mcast_mlo_iter_ptnr_vdev - API to iterate through ptnr vdev list
  432. * @be_soc: dp_soc_be pointer
  433. * @be_vdev: dp_vdev_be pointer
  434. * @func : function to be called for each peer
  435. * @arg : argument need to be passed to func
  436. * @mod_id: module id
  437. *
  438. * Return: None
  439. */
  440. void dp_mcast_mlo_iter_ptnr_vdev(struct dp_soc_be *be_soc,
  441. struct dp_vdev_be *be_vdev,
  442. dp_ptnr_vdev_iter_func func,
  443. void *arg,
  444. enum dp_mod_id mod_id);
  445. /*
  446. * dp_mcast_mlo_iter_ptnr_soc - API to iterate through ptnr soc list
  447. * @be_soc: dp_soc_be pointer
  448. * @func : function to be called for each peer
  449. * @arg : argument need to be passed to func
  450. *
  451. * Return: None
  452. */
  453. void dp_mcast_mlo_iter_ptnr_soc(struct dp_soc_be *be_soc,
  454. dp_ptnr_soc_iter_func func,
  455. void *arg);
  456. /*
  457. * dp_mlo_get_mcast_primary_vdev- get ref to mcast primary vdev
  458. * @be_soc: dp_soc_be pointer
  459. * @be_vdev: dp_vdev_be pointer
  460. * @mod_id: module id
  461. *
  462. * Return: mcast primary DP VDEV handle on success, NULL on failure
  463. */
  464. struct dp_vdev *dp_mlo_get_mcast_primary_vdev(struct dp_soc_be *be_soc,
  465. struct dp_vdev_be *be_vdev,
  466. enum dp_mod_id mod_id);
  467. #endif
  468. #endif
  469. #else
  470. typedef struct dp_soc_be *dp_mld_peer_hash_obj_t;
  471. static inline dp_mld_peer_hash_obj_t
  472. dp_mlo_get_peer_hash_obj(struct dp_soc *soc)
  473. {
  474. return dp_get_be_soc_from_dp_soc(soc);
  475. }
  476. static inline void dp_clr_mlo_ptnr_list(struct dp_soc *soc,
  477. struct dp_vdev *vdev)
  478. {
  479. }
  480. #endif
  481. /*
  482. * dp_mlo_peer_find_hash_attach_be() - API to initialize ML peer hash table
  483. *
  484. * @mld_hash_obj: Peer has object
  485. * @hash_elems: number of entries in hash table
  486. *
  487. * return: QDF_STATUS_SUCCESS when attach is success else QDF_STATUS_FAILURE
  488. */
  489. QDF_STATUS
  490. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  491. int hash_elems);
  492. /*
  493. * dp_mlo_peer_find_hash_detach_be() - API to de-initialize ML peer hash table
  494. *
  495. * @mld_hash_obj: Peer has object
  496. *
  497. * return: void
  498. */
  499. void dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj);
  500. /**
  501. * dp_get_be_pdev_from_dp_pdev() - get dp_pdev_be from dp_pdev
  502. * @pdev: dp_pdev pointer
  503. *
  504. * Return: dp_pdev_be pointer
  505. */
  506. static inline
  507. struct dp_pdev_be *dp_get_be_pdev_from_dp_pdev(struct dp_pdev *pdev)
  508. {
  509. return (struct dp_pdev_be *)pdev;
  510. }
  511. /**
  512. * dp_get_be_vdev_from_dp_vdev() - get dp_vdev_be from dp_vdev
  513. * @vdev: dp_vdev pointer
  514. *
  515. * Return: dp_vdev_be pointer
  516. */
  517. static inline
  518. struct dp_vdev_be *dp_get_be_vdev_from_dp_vdev(struct dp_vdev *vdev)
  519. {
  520. return (struct dp_vdev_be *)vdev;
  521. }
  522. /**
  523. * dp_get_be_peer_from_dp_peer() - get dp_peer_be from dp_peer
  524. * @peer: dp_peer pointer
  525. *
  526. * Return: dp_peer_be pointer
  527. */
  528. static inline
  529. struct dp_peer_be *dp_get_be_peer_from_dp_peer(struct dp_peer *peer)
  530. {
  531. return (struct dp_peer_be *)peer;
  532. }
  533. void dp_ppeds_disable_irq(struct dp_soc *soc, struct dp_srng *srng);
  534. void dp_ppeds_enable_irq(struct dp_soc *soc, struct dp_srng *srng);
  535. QDF_STATUS
  536. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  537. struct dp_hw_cookie_conversion_t *cc_ctx,
  538. uint32_t num_descs,
  539. enum dp_desc_type desc_type,
  540. uint8_t desc_pool_id);
  541. QDF_STATUS
  542. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  543. struct dp_hw_cookie_conversion_t *cc_ctx);
  544. QDF_STATUS
  545. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  546. struct dp_hw_cookie_conversion_t *cc_ctx);
  547. QDF_STATUS
  548. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  549. struct dp_hw_cookie_conversion_t *cc_ctx);
  550. /**
  551. * dp_cc_spt_page_desc_alloc() - allocate SPT DDR page descriptor from pool
  552. * @be_soc: beryllium soc handler
  553. * @list_head: pointer to page desc head
  554. * @list_tail: pointer to page desc tail
  555. * @num_desc: number of TX/RX Descs required for SPT pages
  556. *
  557. * Return: number of SPT page Desc allocated
  558. */
  559. uint16_t dp_cc_spt_page_desc_alloc(struct dp_soc_be *be_soc,
  560. struct dp_spt_page_desc **list_head,
  561. struct dp_spt_page_desc **list_tail,
  562. uint16_t num_desc);
  563. /**
  564. * dp_cc_spt_page_desc_free() - free SPT DDR page descriptor to pool
  565. * @be_soc: beryllium soc handler
  566. * @list_head: pointer to page desc head
  567. * @list_tail: pointer to page desc tail
  568. * @page_nums: number of page desc freed back to pool
  569. */
  570. void dp_cc_spt_page_desc_free(struct dp_soc_be *be_soc,
  571. struct dp_spt_page_desc **list_head,
  572. struct dp_spt_page_desc **list_tail,
  573. uint16_t page_nums);
  574. /**
  575. * dp_cc_desc_id_generate() - generate SW cookie ID according to
  576. DDR page 4K aligned or not
  577. * @ppt_index: offset index in primary page table
  578. * @spt_index: offset index in sceondary DDR page
  579. *
  580. * Generate SW cookie ID to match as HW expected
  581. *
  582. * Return: cookie ID
  583. */
  584. static inline uint32_t dp_cc_desc_id_generate(uint32_t ppt_index,
  585. uint16_t spt_index)
  586. {
  587. /*
  588. * for 4k aligned case, cmem entry size is 4 bytes,
  589. * HW index from bit19~bit10 value = ppt_index / 2, high 32bits flag
  590. * from bit9 value = ppt_index % 2, then bit 19 ~ bit9 value is
  591. * exactly same with original ppt_index value.
  592. * for 4k un-aligned case, cmem entry size is 8 bytes.
  593. * bit19 ~ bit9 will be HW index value, same as ppt_index value.
  594. */
  595. return ((((uint32_t)ppt_index) << DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT) |
  596. spt_index);
  597. }
  598. /**
  599. * dp_cc_desc_va_find() - find TX/RX Descs virtual address by ID
  600. * @be_soc: be soc handle
  601. * @desc_id: TX/RX Dess ID
  602. *
  603. * Return: TX/RX Desc virtual address
  604. */
  605. static inline uintptr_t dp_cc_desc_find(struct dp_soc *soc,
  606. uint32_t desc_id)
  607. {
  608. struct dp_soc_be *be_soc;
  609. uint16_t ppt_page_id, spt_va_id;
  610. uint8_t *spt_page_va;
  611. be_soc = dp_get_be_soc_from_dp_soc(soc);
  612. ppt_page_id = (desc_id & DP_CC_DESC_ID_PPT_PAGE_OS_MASK) >>
  613. DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT;
  614. spt_va_id = (desc_id & DP_CC_DESC_ID_SPT_VA_OS_MASK) >>
  615. DP_CC_DESC_ID_SPT_VA_OS_SHIFT;
  616. /*
  617. * ppt index in cmem is same order where the page in the
  618. * page desc array during initialization.
  619. * entry size in DDR page is 64 bits, for 32 bits system,
  620. * only lower 32 bits VA value is needed.
  621. */
  622. spt_page_va = be_soc->page_desc_base[ppt_page_id].page_v_addr;
  623. return (*((uintptr_t *)(spt_page_va +
  624. spt_va_id * DP_CC_HW_READ_BYTES)));
  625. }
  626. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  627. /**
  628. * enum dp_srng_near_full_levels - SRNG Near FULL levels
  629. * @DP_SRNG_THRESH_SAFE: SRNG level safe for yielding the near full mode
  630. * of processing the entries in SRNG
  631. * @DP_SRNG_THRESH_NEAR_FULL: SRNG level enters the near full mode
  632. * of processing the entries in SRNG
  633. * @DP_SRNG_THRESH_CRITICAL: SRNG level enters the critical level of full
  634. * condition and drastic steps need to be taken for processing
  635. * the entries in SRNG
  636. */
  637. enum dp_srng_near_full_levels {
  638. DP_SRNG_THRESH_SAFE,
  639. DP_SRNG_THRESH_NEAR_FULL,
  640. DP_SRNG_THRESH_CRITICAL,
  641. };
  642. /**
  643. * dp_srng_check_ring_near_full() - Check if SRNG is marked as near-full from
  644. * its corresponding near-full irq handler
  645. * @soc: Datapath SoC handle
  646. * @dp_srng: datapath handle for this SRNG
  647. *
  648. * Return: 1, if the srng was marked as near-full
  649. * 0, if the srng was not marked as near-full
  650. */
  651. static inline int dp_srng_check_ring_near_full(struct dp_soc *soc,
  652. struct dp_srng *dp_srng)
  653. {
  654. return qdf_atomic_read(&dp_srng->near_full);
  655. }
  656. /**
  657. * dp_srng_get_near_full_level() - Check the num available entries in the
  658. * consumer srng and return the level of the srng
  659. * near full state.
  660. * @soc: Datapath SoC Handle [To be validated by the caller]
  661. * @hal_ring_hdl: SRNG handle
  662. *
  663. * Return: near-full level
  664. */
  665. static inline int
  666. dp_srng_get_near_full_level(struct dp_soc *soc, struct dp_srng *dp_srng)
  667. {
  668. uint32_t num_valid;
  669. num_valid = hal_srng_dst_num_valid_nolock(soc->hal_soc,
  670. dp_srng->hal_srng,
  671. true);
  672. if (num_valid > dp_srng->crit_thresh)
  673. return DP_SRNG_THRESH_CRITICAL;
  674. else if (num_valid < dp_srng->safe_thresh)
  675. return DP_SRNG_THRESH_SAFE;
  676. else
  677. return DP_SRNG_THRESH_NEAR_FULL;
  678. }
  679. #define DP_SRNG_PER_LOOP_NF_REAP_MULTIPLIER 2
  680. /**
  681. * dp_srng_test_and_update_nf_params() - Test the near full level and update
  682. * the reap_limit and flags to reflect the state.
  683. * @soc: Datapath soc handle
  684. * @srng: Datapath handle for the srng
  685. * @max_reap_limit: [Output Param] Buffer to set the map_reap_limit as
  686. * per the near-full state
  687. *
  688. * Return: 1, if the srng is near full
  689. * 0, if the srng is not near full
  690. */
  691. static inline int
  692. _dp_srng_test_and_update_nf_params(struct dp_soc *soc,
  693. struct dp_srng *srng,
  694. int *max_reap_limit)
  695. {
  696. int ring_near_full = 0, near_full_level;
  697. if (dp_srng_check_ring_near_full(soc, srng)) {
  698. near_full_level = dp_srng_get_near_full_level(soc, srng);
  699. switch (near_full_level) {
  700. case DP_SRNG_THRESH_CRITICAL:
  701. /* Currently not doing anything special here */
  702. fallthrough;
  703. case DP_SRNG_THRESH_NEAR_FULL:
  704. ring_near_full = 1;
  705. *max_reap_limit *= DP_SRNG_PER_LOOP_NF_REAP_MULTIPLIER;
  706. break;
  707. case DP_SRNG_THRESH_SAFE:
  708. qdf_atomic_set(&srng->near_full, 0);
  709. ring_near_full = 0;
  710. break;
  711. default:
  712. qdf_assert(0);
  713. break;
  714. }
  715. }
  716. return ring_near_full;
  717. }
  718. #else
  719. static inline int
  720. _dp_srng_test_and_update_nf_params(struct dp_soc *soc,
  721. struct dp_srng *srng,
  722. int *max_reap_limit)
  723. {
  724. return 0;
  725. }
  726. #endif
  727. static inline
  728. uint32_t dp_desc_pool_get_cmem_base(uint8_t chip_id, uint8_t desc_pool_id,
  729. enum dp_desc_type desc_type)
  730. {
  731. switch (desc_type) {
  732. case DP_TX_DESC_TYPE:
  733. return (DP_TX_DESC_CMEM_OFFSET +
  734. (desc_pool_id * DP_TX_DESC_POOL_CMEM_SIZE));
  735. case DP_RX_DESC_BUF_TYPE:
  736. return (DP_RX_DESC_CMEM_OFFSET +
  737. ((chip_id * MAX_RXDESC_POOLS) + desc_pool_id) *
  738. DP_RX_DESC_POOL_CMEM_SIZE);
  739. case DP_TX_PPEDS_DESC_TYPE:
  740. return DP_TX_PPEDS_DESC_CMEM_OFFSET;
  741. default:
  742. QDF_BUG(0);
  743. }
  744. return 0;
  745. }
  746. #ifndef WLAN_MLO_MULTI_CHIP
  747. static inline
  748. void dp_soc_mlo_fill_params(struct dp_soc *soc,
  749. struct cdp_soc_attach_params *params)
  750. {
  751. }
  752. static inline
  753. void dp_pdev_mlo_fill_params(struct dp_pdev *pdev,
  754. struct cdp_pdev_attach_params *params)
  755. {
  756. }
  757. static inline
  758. void dp_mlo_update_link_to_pdev_map(struct dp_soc *soc, struct dp_pdev *pdev)
  759. {
  760. }
  761. static inline
  762. void dp_mlo_update_link_to_pdev_unmap(struct dp_soc *soc, struct dp_pdev *pdev)
  763. {
  764. }
  765. #endif
  766. #endif