dp_be.c 67 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #ifdef WIFI_MONITOR_SUPPORT
  26. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  27. #include "dp_mon_2.0.h"
  28. #endif
  29. #include "dp_mon.h"
  30. #endif
  31. #include <hal_be_api.h>
  32. #ifdef WLAN_SUPPORT_PPEDS
  33. #include "be/dp_ppeds.h"
  34. #include <ppe_vp_public.h>
  35. #include <ppe_drv_sc.h>
  36. #endif
  37. /* Generic AST entry aging timer value */
  38. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  39. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  40. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  41. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  42. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  43. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  44. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  45. #ifdef QCA_WIFI_KIWI_V2
  46. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  47. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  48. #else
  49. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  50. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  51. #endif
  52. };
  53. #else
  54. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  55. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  56. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  57. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  58. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  59. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  60. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  61. };
  62. #endif
  63. #ifdef WLAN_SUPPORT_PPEDS
  64. static struct cdp_ppeds_txrx_ops dp_ops_ppeds_be = {
  65. .ppeds_entry_attach = dp_ppeds_attach_vdev_be,
  66. .ppeds_entry_detach = dp_ppeds_detach_vdev_be,
  67. .ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be,
  68. .ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be,
  69. .ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be,
  70. .ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be,
  71. };
  72. static void dp_ppeds_rings_status(struct dp_soc *soc)
  73. {
  74. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  75. dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
  76. dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
  77. dp_print_ring_stat_from_hal(soc, &be_soc->ppeds_wbm_release_ring,
  78. WBM2SW_RELEASE);
  79. }
  80. static void dp_ppeds_inuse_desc(struct dp_soc *soc)
  81. {
  82. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  83. DP_PRINT_STATS("PPE-DS Tx Descriptors in Use = %u num_free %u",
  84. be_soc->ppeds_tx_desc.num_allocated,
  85. be_soc->ppeds_tx_desc.num_free);
  86. }
  87. #endif
  88. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  89. {
  90. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  91. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  92. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  93. /* this is used only when dmac mode is enabled */
  94. soc->num_rx_refill_buf_rings = 1;
  95. soc->wlan_cfg_ctx->notify_frame_support =
  96. DP_MARK_NOTIFY_FRAME_SUPPORT;
  97. }
  98. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  99. {
  100. switch (context_type) {
  101. case DP_CONTEXT_TYPE_SOC:
  102. return sizeof(struct dp_soc_be);
  103. case DP_CONTEXT_TYPE_PDEV:
  104. return sizeof(struct dp_pdev_be);
  105. case DP_CONTEXT_TYPE_VDEV:
  106. return sizeof(struct dp_vdev_be);
  107. case DP_CONTEXT_TYPE_PEER:
  108. return sizeof(struct dp_peer_be);
  109. default:
  110. return 0;
  111. }
  112. }
  113. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  114. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  115. /**
  116. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  117. * per wbm2sw ring
  118. *
  119. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  120. *
  121. * Return: None
  122. */
  123. static inline
  124. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  125. {
  126. cc_cfg->wbm2sw6_cc_en = 1;
  127. cc_cfg->wbm2sw5_cc_en = 1;
  128. cc_cfg->wbm2sw4_cc_en = 1;
  129. cc_cfg->wbm2sw3_cc_en = 1;
  130. cc_cfg->wbm2sw2_cc_en = 1;
  131. /* disable wbm2sw1 hw cc as it's for FW */
  132. cc_cfg->wbm2sw1_cc_en = 0;
  133. cc_cfg->wbm2sw0_cc_en = 1;
  134. cc_cfg->wbm2fw_cc_en = 0;
  135. }
  136. #else
  137. static inline
  138. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  139. {
  140. cc_cfg->wbm2sw6_cc_en = 1;
  141. cc_cfg->wbm2sw5_cc_en = 1;
  142. cc_cfg->wbm2sw4_cc_en = 1;
  143. cc_cfg->wbm2sw3_cc_en = 1;
  144. cc_cfg->wbm2sw2_cc_en = 1;
  145. cc_cfg->wbm2sw1_cc_en = 1;
  146. cc_cfg->wbm2sw0_cc_en = 1;
  147. cc_cfg->wbm2fw_cc_en = 0;
  148. }
  149. #endif
  150. #if defined(WLAN_SUPPORT_RX_FISA)
  151. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  152. {
  153. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  154. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  155. /* get CMEM for cookie conversion */
  156. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  157. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  158. return QDF_STATUS_E_NOMEM;
  159. }
  160. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  161. soc->fst_cmem_base = soc->cmem_base +
  162. (soc->cmem_total_size - soc->cmem_avail_size);
  163. soc->cmem_avail_size -= soc->fst_cmem_size;
  164. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  165. soc->fst_cmem_base, soc->fst_cmem_size);
  166. return QDF_STATUS_SUCCESS;
  167. }
  168. #else /* !WLAN_SUPPORT_RX_FISA */
  169. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  170. {
  171. return QDF_STATUS_SUCCESS;
  172. }
  173. #endif
  174. /**
  175. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  176. * conversion register
  177. *
  178. * @soc: SOC handle
  179. * @is_4k_align: page address 4k aligned
  180. *
  181. * Return: None
  182. */
  183. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  184. bool is_4k_align)
  185. {
  186. struct hal_hw_cc_config cc_cfg = { 0 };
  187. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  188. if (soc->cdp_soc.ol_ops->get_con_mode &&
  189. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  190. return;
  191. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  192. dp_info("INI skip HW CC register setting");
  193. return;
  194. }
  195. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  196. cc_cfg.cc_global_en = true;
  197. cc_cfg.page_4k_align = is_4k_align;
  198. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  199. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  200. /* 36th bit should be 1 then HW know this is CMEM address */
  201. cc_cfg.lut_base_addr_39_32 = 0x10;
  202. cc_cfg.error_path_cookie_conv_en = true;
  203. cc_cfg.release_path_cookie_conv_en = true;
  204. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  205. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  206. }
  207. /**
  208. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  209. * @hal_soc_hdl: HAL SOC handle
  210. * @offset: CMEM address
  211. * @value: value to write
  212. *
  213. * Return: None.
  214. */
  215. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  216. uint32_t offset,
  217. uint32_t value)
  218. {
  219. hal_cmem_write(hal_soc_hdl, offset, value);
  220. }
  221. /**
  222. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  223. * HW cookie conversion
  224. *
  225. * @soc: SOC handle
  226. *
  227. * Return: 0 in case of success, else error value
  228. */
  229. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  230. {
  231. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  232. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  233. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  234. /* get CMEM for cookie conversion */
  235. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  236. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  237. return QDF_STATUS_E_RESOURCES;
  238. }
  239. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  240. DP_CC_MEM_OFFSET_IN_CMEM);
  241. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  242. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  243. be_soc->cc_cmem_base, soc->cmem_avail_size);
  244. return QDF_STATUS_SUCCESS;
  245. }
  246. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  247. uint8_t for_feature)
  248. {
  249. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  250. switch (for_feature) {
  251. case COOKIE_CONVERSION:
  252. status = dp_hw_cc_cmem_addr_init(soc);
  253. break;
  254. case FISA_FST:
  255. status = dp_fisa_fst_cmem_addr_init(soc);
  256. break;
  257. default:
  258. dp_err("Invalid CMEM request");
  259. }
  260. return status;
  261. }
  262. #else
  263. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  264. bool is_4k_align) {}
  265. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  266. uint32_t offset,
  267. uint32_t value)
  268. { }
  269. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  270. {
  271. return QDF_STATUS_SUCCESS;
  272. }
  273. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  274. uint8_t for_feature)
  275. {
  276. return QDF_STATUS_SUCCESS;
  277. }
  278. #endif
  279. QDF_STATUS
  280. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  281. struct dp_hw_cookie_conversion_t *cc_ctx,
  282. uint32_t num_descs,
  283. enum dp_desc_type desc_type,
  284. uint8_t desc_pool_id)
  285. {
  286. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  287. uint32_t num_spt_pages, i = 0;
  288. struct dp_spt_page_desc *spt_desc;
  289. struct qdf_mem_dma_page_t *dma_page;
  290. uint8_t chip_id;
  291. /* estimate how many SPT DDR pages needed */
  292. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  293. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  294. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  295. dp_info("num_spt_pages needed %d", num_spt_pages);
  296. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  297. &cc_ctx->page_pool, qdf_page_size,
  298. num_spt_pages, 0, false);
  299. if (!cc_ctx->page_pool.dma_pages) {
  300. dp_err("spt ddr pages allocation failed");
  301. return QDF_STATUS_E_RESOURCES;
  302. }
  303. cc_ctx->page_desc_base = qdf_mem_malloc(
  304. num_spt_pages * sizeof(struct dp_spt_page_desc));
  305. if (!cc_ctx->page_desc_base) {
  306. dp_err("spt page descs allocation failed");
  307. goto fail_0;
  308. }
  309. chip_id = dp_mlo_get_chip_id(soc);
  310. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  311. desc_type);
  312. /* initial page desc */
  313. spt_desc = cc_ctx->page_desc_base;
  314. dma_page = cc_ctx->page_pool.dma_pages;
  315. while (i < num_spt_pages) {
  316. /* check if page address 4K aligned */
  317. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  318. dp_err("non-4k aligned pages addr %pK",
  319. (void *)dma_page[i].page_p_addr);
  320. goto fail_1;
  321. }
  322. spt_desc[i].page_v_addr =
  323. dma_page[i].page_v_addr_start;
  324. spt_desc[i].page_p_addr =
  325. dma_page[i].page_p_addr;
  326. i++;
  327. }
  328. cc_ctx->total_page_num = num_spt_pages;
  329. qdf_spinlock_create(&cc_ctx->cc_lock);
  330. return QDF_STATUS_SUCCESS;
  331. fail_1:
  332. qdf_mem_free(cc_ctx->page_desc_base);
  333. fail_0:
  334. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  335. &cc_ctx->page_pool, 0, false);
  336. return QDF_STATUS_E_FAILURE;
  337. }
  338. QDF_STATUS
  339. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  340. struct dp_hw_cookie_conversion_t *cc_ctx)
  341. {
  342. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  343. qdf_mem_free(cc_ctx->page_desc_base);
  344. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  345. &cc_ctx->page_pool, 0, false);
  346. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  347. return QDF_STATUS_SUCCESS;
  348. }
  349. QDF_STATUS
  350. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  351. struct dp_hw_cookie_conversion_t *cc_ctx)
  352. {
  353. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  354. uint32_t i = 0;
  355. struct dp_spt_page_desc *spt_desc;
  356. uint32_t ppt_index;
  357. uint32_t ppt_id_start;
  358. if (!cc_ctx->total_page_num) {
  359. dp_err("total page num is 0");
  360. return QDF_STATUS_E_INVAL;
  361. }
  362. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  363. spt_desc = cc_ctx->page_desc_base;
  364. while (i < cc_ctx->total_page_num) {
  365. /* write page PA to CMEM */
  366. dp_hw_cc_cmem_write(soc->hal_soc,
  367. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  368. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  369. (spt_desc[i].page_p_addr >>
  370. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  371. ppt_index = ppt_id_start + i;
  372. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  373. qdf_assert_always(0);
  374. spt_desc[i].ppt_index = ppt_index;
  375. be_soc->page_desc_base[ppt_index].page_v_addr =
  376. spt_desc[i].page_v_addr;
  377. i++;
  378. }
  379. return QDF_STATUS_SUCCESS;
  380. }
  381. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  382. QDF_STATUS
  383. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  384. struct dp_hw_cookie_conversion_t *cc_ctx)
  385. {
  386. uint32_t ppt_index;
  387. struct dp_spt_page_desc *spt_desc;
  388. int i = 0;
  389. spt_desc = cc_ctx->page_desc_base;
  390. while (i < cc_ctx->total_page_num) {
  391. ppt_index = spt_desc[i].ppt_index;
  392. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  393. i++;
  394. }
  395. return QDF_STATUS_SUCCESS;
  396. }
  397. #else
  398. QDF_STATUS
  399. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  400. struct dp_hw_cookie_conversion_t *cc_ctx)
  401. {
  402. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  403. uint32_t ppt_index;
  404. struct dp_spt_page_desc *spt_desc;
  405. int i = 0;
  406. spt_desc = cc_ctx->page_desc_base;
  407. while (i < cc_ctx->total_page_num) {
  408. /* reset PA in CMEM to NULL */
  409. dp_hw_cc_cmem_write(soc->hal_soc,
  410. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  411. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  412. 0);
  413. ppt_index = spt_desc[i].ppt_index;
  414. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  415. i++;
  416. }
  417. return QDF_STATUS_SUCCESS;
  418. }
  419. #endif
  420. #ifdef WLAN_SUPPORT_PPEDS
  421. static QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  422. {
  423. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  424. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  425. /*
  426. * Check if PPE DS is enabled.
  427. */
  428. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx))
  429. return QDF_STATUS_SUCCESS;
  430. if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS)
  431. return QDF_STATUS_SUCCESS;
  432. cdp_ops->ppeds_ops = &dp_ops_ppeds_be;
  433. return QDF_STATUS_SUCCESS;
  434. }
  435. static QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  436. {
  437. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  438. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  439. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx))
  440. return QDF_STATUS_E_FAILURE;
  441. dp_ppeds_detach_soc_be(be_soc);
  442. cdp_ops->ppeds_ops = NULL;
  443. return QDF_STATUS_SUCCESS;
  444. }
  445. static QDF_STATUS dp_peer_ppeds_default_route_be(struct dp_soc *soc,
  446. struct dp_peer_be *be_peer,
  447. uint8_t vdev_id,
  448. uint16_t src_info)
  449. {
  450. uint16_t service_code;
  451. uint8_t priority_valid;
  452. uint8_t use_ppe_ds = PEER_ROUTING_USE_PPE;
  453. uint8_t peer_routing_enabled = PEER_ROUTING_ENABLED;
  454. QDF_STATUS status = QDF_STATUS_SUCCESS;
  455. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  456. struct dp_vdev_be *be_vdev;
  457. be_vdev = dp_get_be_vdev_from_dp_vdev(be_peer->peer.vdev);
  458. /*
  459. * Program service code bypass to avoid L2 new mac address
  460. * learning exception when fdb learning is disabled.
  461. */
  462. service_code = PPE_DRV_SC_SPF_BYPASS;
  463. priority_valid = be_peer->priority_valid;
  464. /*
  465. * if FST is enabled and MLO is disabled then
  466. * let flow rule take the decision of routing
  467. * the pkt to DS or host
  468. */
  469. if (wlan_cfg_is_rx_flow_tag_enabled(cfg) &&
  470. qdf_is_macaddr_zero((struct qdf_mac_addr *)
  471. be_vdev->vdev.mld_mac_addr.raw))
  472. use_ppe_ds = 0;
  473. if (soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing) {
  474. status =
  475. soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing
  476. (soc->ctrl_psoc,
  477. be_peer->peer.mac_addr.raw,
  478. service_code, priority_valid,
  479. src_info, vdev_id, use_ppe_ds,
  480. peer_routing_enabled);
  481. if (status != QDF_STATUS_SUCCESS) {
  482. qdf_err("vdev_id: %d, PPE peer routing mac:"
  483. QDF_MAC_ADDR_FMT, vdev_id,
  484. QDF_MAC_ADDR_REF(be_peer->peer.mac_addr.raw));
  485. return QDF_STATUS_E_FAILURE;
  486. }
  487. }
  488. return QDF_STATUS_SUCCESS;
  489. }
  490. static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  491. struct dp_peer *peer,
  492. struct dp_vdev_be *be_vdev)
  493. {
  494. struct dp_ppe_vp_profile *ppe_vp_profile = &be_vdev->ppe_vp_profile;
  495. uint16_t src_info = ppe_vp_profile->vp_num;
  496. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  497. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  498. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  499. if (!be_peer) {
  500. qdf_err("BE peer is null");
  501. return QDF_STATUS_E_NULL_VALUE;
  502. }
  503. if (IS_DP_LEGACY_PEER(peer)) {
  504. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  505. vdev_id, src_info);
  506. } else if (IS_MLO_DP_MLD_PEER(peer)) {
  507. int i;
  508. struct dp_peer *link_peer = NULL;
  509. struct dp_mld_link_peers link_peers_info;
  510. /* get link peers with reference */
  511. dp_get_link_peers_ref_from_mld_peer(soc, peer, &link_peers_info,
  512. DP_MOD_ID_DS);
  513. for (i = 0; i < link_peers_info.num_links; i++) {
  514. link_peer = link_peers_info.link_peers[i];
  515. be_peer = dp_get_be_peer_from_dp_peer(link_peer);
  516. if (!be_peer) {
  517. qdf_err("BE peer is null for peer id %d ",
  518. link_peer->peer_id);
  519. continue;
  520. }
  521. be_vdev = dp_get_be_vdev_from_dp_vdev(link_peer->vdev);
  522. if (!be_vdev) {
  523. qdf_err("BE vap is null for peer id %d ",
  524. link_peer->peer_id);
  525. continue;
  526. }
  527. vdev_id = be_vdev->vdev.vdev_id;
  528. qdf_status = dp_peer_ppeds_default_route_be(soc,
  529. be_peer,
  530. vdev_id,
  531. src_info);
  532. }
  533. dp_release_link_peers_ref(&link_peers_info, DP_MOD_ID_DS);
  534. } else {
  535. struct dp_peer *mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  536. if (!mld_peer)
  537. return qdf_status;
  538. be_vdev = dp_get_be_vdev_from_dp_vdev(mld_peer->vdev);
  539. if (!be_vdev) {
  540. qdf_err("BE vap is null");
  541. return QDF_STATUS_E_NULL_VALUE;
  542. }
  543. ppe_vp_profile = &be_vdev->ppe_vp_profile;
  544. src_info = ppe_vp_profile->vp_num;
  545. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  546. vdev_id, src_info);
  547. }
  548. return qdf_status;
  549. }
  550. #else
  551. static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
  552. {
  553. return QDF_STATUS_SUCCESS;
  554. }
  555. static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
  556. {
  557. return QDF_STATUS_SUCCESS;
  558. }
  559. static inline QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  560. {
  561. return QDF_STATUS_SUCCESS;
  562. }
  563. static inline QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  564. {
  565. return QDF_STATUS_SUCCESS;
  566. }
  567. static inline
  568. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, struct dp_peer *peer,
  569. struct dp_vdev_be *be_vdev)
  570. {
  571. return QDF_STATUS_SUCCESS;
  572. }
  573. #endif /* WLAN_SUPPORT_PPEDS */
  574. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  575. {
  576. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  577. int i = 0;
  578. dp_soc_ppeds_detach_be(soc);
  579. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  580. dp_hw_cookie_conversion_detach(be_soc,
  581. &be_soc->tx_cc_ctx[i]);
  582. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  583. dp_hw_cookie_conversion_detach(be_soc,
  584. &be_soc->rx_cc_ctx[i]);
  585. qdf_mem_free(be_soc->page_desc_base);
  586. be_soc->page_desc_base = NULL;
  587. return QDF_STATUS_SUCCESS;
  588. }
  589. #ifdef WLAN_MLO_MULTI_CHIP
  590. #ifdef WLAN_MCAST_MLO
  591. static inline void
  592. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  593. {
  594. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  595. be_vdev->mcast_primary = false;
  596. be_vdev->seq_num = 0;
  597. hal_tx_mcast_mlo_reinject_routing_set(
  598. soc->hal_soc,
  599. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  600. if (vdev->opmode == wlan_op_mode_ap) {
  601. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  602. vdev->vdev_id,
  603. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  604. }
  605. }
  606. static inline void
  607. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  608. {
  609. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  610. be_vdev->seq_num = 0;
  611. be_vdev->mcast_primary = false;
  612. vdev->mlo_vdev = false;
  613. }
  614. #else
  615. static inline void
  616. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  617. {
  618. }
  619. static inline void
  620. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  621. {
  622. }
  623. #endif
  624. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  625. {
  626. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  627. qdf_mem_set(be_vdev->partner_vdev_list,
  628. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  629. CDP_INVALID_VDEV_ID);
  630. }
  631. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  632. struct cdp_lro_hash_config *lro_hash)
  633. {
  634. dp_mlo_get_rx_hash_key(soc, lro_hash);
  635. }
  636. #else
  637. static inline void
  638. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  639. {
  640. }
  641. static inline void
  642. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  643. {
  644. }
  645. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  646. {
  647. }
  648. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  649. struct cdp_lro_hash_config *lro_hash)
  650. {
  651. dp_get_rx_hash_key_bytes(lro_hash);
  652. }
  653. #endif
  654. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  655. struct cdp_soc_attach_params *params)
  656. {
  657. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  658. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  659. uint32_t max_tx_rx_desc_num, num_spt_pages;
  660. uint32_t num_entries;
  661. int i = 0;
  662. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  663. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
  664. WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
  665. /* estimate how many SPT DDR pages needed */
  666. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  667. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  668. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  669. be_soc->page_desc_base = qdf_mem_malloc(
  670. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  671. if (!be_soc->page_desc_base) {
  672. dp_err("spt page descs allocation failed");
  673. return QDF_STATUS_E_NOMEM;
  674. }
  675. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  676. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  677. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  678. goto fail;
  679. dp_soc_mlo_fill_params(soc, params);
  680. qdf_status = dp_soc_ppeds_attach_be(soc);
  681. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  682. goto fail;
  683. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  684. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  685. qdf_status =
  686. dp_hw_cookie_conversion_attach(be_soc,
  687. &be_soc->tx_cc_ctx[i],
  688. num_entries,
  689. DP_TX_DESC_TYPE, i);
  690. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  691. goto fail;
  692. }
  693. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  694. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  695. goto fail;
  696. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  697. num_entries =
  698. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  699. qdf_status =
  700. dp_hw_cookie_conversion_attach(be_soc,
  701. &be_soc->rx_cc_ctx[i],
  702. num_entries,
  703. DP_RX_DESC_BUF_TYPE, i);
  704. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  705. goto fail;
  706. }
  707. return qdf_status;
  708. fail:
  709. dp_soc_detach_be(soc);
  710. return qdf_status;
  711. }
  712. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  713. {
  714. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  715. int i = 0;
  716. dp_tx_deinit_bank_profiles(be_soc);
  717. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  718. dp_hw_cookie_conversion_deinit(be_soc,
  719. &be_soc->tx_cc_ctx[i]);
  720. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  721. dp_hw_cookie_conversion_deinit(be_soc,
  722. &be_soc->rx_cc_ctx[i]);
  723. dp_ppeds_deinit_soc_be(soc);
  724. return QDF_STATUS_SUCCESS;
  725. }
  726. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  727. {
  728. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  729. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  730. int i = 0;
  731. dp_ppeds_init_soc_be(soc);
  732. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  733. qdf_status =
  734. dp_hw_cookie_conversion_init(be_soc,
  735. &be_soc->tx_cc_ctx[i]);
  736. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  737. goto fail;
  738. }
  739. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  740. qdf_status =
  741. dp_hw_cookie_conversion_init(be_soc,
  742. &be_soc->rx_cc_ctx[i]);
  743. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  744. goto fail;
  745. }
  746. /* route vdev_id mismatch notification via FW completion */
  747. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  748. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  749. qdf_status = dp_tx_init_bank_profiles(be_soc);
  750. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  751. goto fail;
  752. /* write WBM/REO cookie conversion CFG register */
  753. dp_cc_reg_cfg_init(soc, true);
  754. return qdf_status;
  755. fail:
  756. dp_soc_deinit_be(soc);
  757. return qdf_status;
  758. }
  759. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  760. struct cdp_pdev_attach_params *params)
  761. {
  762. dp_pdev_mlo_fill_params(pdev, params);
  763. return QDF_STATUS_SUCCESS;
  764. }
  765. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  766. {
  767. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  768. return QDF_STATUS_SUCCESS;
  769. }
  770. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  771. {
  772. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  773. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  774. struct dp_pdev *pdev = vdev->pdev;
  775. if (vdev->opmode == wlan_op_mode_monitor)
  776. return QDF_STATUS_SUCCESS;
  777. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  778. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  779. vdev->bank_id = be_vdev->bank_id;
  780. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  781. QDF_BUG(0);
  782. return QDF_STATUS_E_FAULT;
  783. }
  784. if (vdev->opmode == wlan_op_mode_sta) {
  785. if (soc->cdp_soc.ol_ops->set_mec_timer)
  786. soc->cdp_soc.ol_ops->set_mec_timer(
  787. soc->ctrl_psoc,
  788. vdev->vdev_id,
  789. DP_AST_AGING_TIMER_DEFAULT_MS);
  790. if (pdev->isolation)
  791. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  792. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  793. else
  794. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  795. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  796. }
  797. dp_mlo_mcast_init(soc, vdev);
  798. dp_mlo_init_ptnr_list(vdev);
  799. return QDF_STATUS_SUCCESS;
  800. }
  801. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  802. {
  803. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  804. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  805. if (vdev->opmode == wlan_op_mode_monitor)
  806. return QDF_STATUS_SUCCESS;
  807. if (vdev->opmode == wlan_op_mode_ap)
  808. dp_mlo_mcast_deinit(soc, vdev);
  809. dp_tx_put_bank_profile(be_soc, be_vdev);
  810. dp_clr_mlo_ptnr_list(soc, vdev);
  811. return QDF_STATUS_SUCCESS;
  812. }
  813. #ifdef WLAN_SUPPORT_PPEDS
  814. static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
  815. {
  816. struct dp_vdev_be *be_vdev;
  817. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  818. be_vdev = dp_get_be_vdev_from_dp_vdev(peer->vdev);
  819. if (!be_vdev) {
  820. qdf_err("BE vap is null");
  821. return QDF_STATUS_E_NULL_VALUE;
  822. }
  823. /*
  824. * Check if PPE DS routing is enabled on the associated vap.
  825. */
  826. if (be_vdev->ppe_vp_enabled == PPE_VP_USER_TYPE_DS)
  827. qdf_status = dp_peer_setup_ppeds_be(soc, peer, be_vdev);
  828. return qdf_status;
  829. }
  830. #else
  831. static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
  832. {
  833. return QDF_STATUS_SUCCESS;
  834. }
  835. #endif
  836. qdf_size_t dp_get_soc_context_size_be(void)
  837. {
  838. return sizeof(struct dp_soc_be);
  839. }
  840. #ifdef CONFIG_WORD_BASED_TLV
  841. /**
  842. * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
  843. * @soc: Common DP soc handle
  844. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  845. *
  846. * Return: none
  847. */
  848. static inline void
  849. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  850. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  851. {
  852. htt_tlv_filter->rx_msdu_end_wmask =
  853. hal_rx_msdu_end_wmask_get(soc->hal_soc);
  854. htt_tlv_filter->rx_mpdu_start_wmask =
  855. hal_rx_mpdu_start_wmask_get(soc->hal_soc);
  856. }
  857. #else
  858. static inline void
  859. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  860. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  861. {
  862. }
  863. #endif
  864. #ifdef WLAN_SUPPORT_PPEDS
  865. static
  866. void dp_free_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  867. int ring_type, int ring_num)
  868. {
  869. if (srng->irq >= 0) {
  870. if (ring_type == WBM2SW_RELEASE &&
  871. ring_num == WBM2_SW_PPE_REL_RING_ID)
  872. pld_pfrm_free_irq(soc->osdev->dev, srng->irq, soc);
  873. else if (ring_type == REO2PPE || ring_type == PPE2TCL)
  874. pld_pfrm_free_irq(soc->osdev->dev, srng->irq,
  875. dp_get_ppe_ds_ctxt(soc));
  876. }
  877. }
  878. static
  879. int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  880. int vector, int ring_type, int ring_num)
  881. {
  882. int irq = -1, ret = 0;
  883. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  884. int pci_slot = pld_get_pci_slot(soc->osdev->dev);
  885. srng->irq = -1;
  886. irq = pld_get_msi_irq(soc->osdev->dev, vector);
  887. if (ring_type == WBM2SW_RELEASE &&
  888. ring_num == WBM2_SW_PPE_REL_RING_ID) {
  889. snprintf(be_soc->irq_name[2], DP_PPE_INTR_STRNG_LEN,
  890. "pci%d_ppe_wbm_rel", pci_slot);
  891. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  892. dp_ppeds_handle_tx_comp,
  893. IRQF_SHARED | IRQF_NO_SUSPEND,
  894. be_soc->irq_name[2], (void *)soc);
  895. if (ret)
  896. goto fail;
  897. } else if (ring_type == REO2PPE && be_soc->ppeds_int_mode_enabled) {
  898. snprintf(be_soc->irq_name[0], DP_PPE_INTR_STRNG_LEN,
  899. "pci%d_reo2ppe", pci_slot);
  900. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  901. dp_ppe_ds_reo2ppe_irq_handler,
  902. IRQF_SHARED | IRQF_NO_SUSPEND,
  903. be_soc->irq_name[0],
  904. dp_get_ppe_ds_ctxt(soc));
  905. if (ret)
  906. goto fail;
  907. } else if (ring_type == PPE2TCL && be_soc->ppeds_int_mode_enabled) {
  908. snprintf(be_soc->irq_name[1], DP_PPE_INTR_STRNG_LEN,
  909. "pci%d_ppe2tcl", pci_slot);
  910. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  911. dp_ppe_ds_ppe2tcl_irq_handler,
  912. IRQF_SHARED | IRQF_NO_SUSPEND,
  913. be_soc->irq_name[1],
  914. dp_get_ppe_ds_ctxt(soc));
  915. if (ret)
  916. goto fail;
  917. pld_pfrm_disable_irq_nosync(soc->osdev->dev, irq);
  918. } else {
  919. return 0;
  920. }
  921. srng->irq = irq;
  922. dp_info("Registered irq %d for soc %pK ring type %d",
  923. irq, soc, ring_type);
  924. return 0;
  925. fail:
  926. dp_err("Unable to config irq : ring type %d irq %d vector %d",
  927. ring_type, irq, vector);
  928. return ret;
  929. }
  930. void dp_ppeds_disable_irq(struct dp_soc *soc, struct dp_srng *srng)
  931. {
  932. if (srng->irq >= 0)
  933. pld_pfrm_disable_irq_nosync(soc->osdev->dev, srng->irq);
  934. }
  935. void dp_ppeds_enable_irq(struct dp_soc *soc, struct dp_srng *srng)
  936. {
  937. if (srng->irq >= 0)
  938. pld_pfrm_enable_irq(soc->osdev->dev, srng->irq);
  939. }
  940. #endif
  941. #ifdef NO_RX_PKT_HDR_TLV
  942. /**
  943. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  944. * @soc: Common DP soc handle
  945. *
  946. * Return: QDF_STATUS
  947. */
  948. static QDF_STATUS
  949. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  950. {
  951. int i;
  952. int mac_id;
  953. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  954. struct dp_srng *rx_mac_srng;
  955. QDF_STATUS status = QDF_STATUS_SUCCESS;
  956. /*
  957. * In Beryllium chipset msdu_start, mpdu_end
  958. * and rx_attn are part of msdu_end/mpdu_start
  959. */
  960. htt_tlv_filter.msdu_start = 0;
  961. htt_tlv_filter.mpdu_end = 0;
  962. htt_tlv_filter.attention = 0;
  963. htt_tlv_filter.mpdu_start = 1;
  964. htt_tlv_filter.msdu_end = 1;
  965. htt_tlv_filter.packet = 1;
  966. htt_tlv_filter.packet_header = 0;
  967. htt_tlv_filter.ppdu_start = 0;
  968. htt_tlv_filter.ppdu_end = 0;
  969. htt_tlv_filter.ppdu_end_user_stats = 0;
  970. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  971. htt_tlv_filter.ppdu_end_status_done = 0;
  972. htt_tlv_filter.enable_fp = 1;
  973. htt_tlv_filter.enable_md = 0;
  974. htt_tlv_filter.enable_md = 0;
  975. htt_tlv_filter.enable_mo = 0;
  976. htt_tlv_filter.fp_mgmt_filter = 0;
  977. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  978. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  979. FILTER_DATA_MCAST |
  980. FILTER_DATA_DATA);
  981. htt_tlv_filter.mo_mgmt_filter = 0;
  982. htt_tlv_filter.mo_ctrl_filter = 0;
  983. htt_tlv_filter.mo_data_filter = 0;
  984. htt_tlv_filter.md_data_filter = 0;
  985. htt_tlv_filter.offset_valid = true;
  986. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  987. htt_tlv_filter.rx_mpdu_end_offset = 0;
  988. htt_tlv_filter.rx_msdu_start_offset = 0;
  989. htt_tlv_filter.rx_attn_offset = 0;
  990. /*
  991. * For monitor mode, the packet hdr tlv is enabled later during
  992. * filter update
  993. */
  994. if (soc->cdp_soc.ol_ops->get_con_mode &&
  995. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  996. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  997. else
  998. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  999. /*Not subscribing rx_pkt_header*/
  1000. htt_tlv_filter.rx_header_offset = 0;
  1001. htt_tlv_filter.rx_mpdu_start_offset =
  1002. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1003. htt_tlv_filter.rx_msdu_end_offset =
  1004. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1005. dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
  1006. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1007. struct dp_pdev *pdev = soc->pdev_list[i];
  1008. if (!pdev)
  1009. continue;
  1010. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1011. int mac_for_pdev =
  1012. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1013. /*
  1014. * Obtain lmac id from pdev to access the LMAC ring
  1015. * in soc context
  1016. */
  1017. int lmac_id =
  1018. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1019. pdev->pdev_id);
  1020. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1021. if (!rx_mac_srng->hal_srng)
  1022. continue;
  1023. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1024. rx_mac_srng->hal_srng,
  1025. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1026. &htt_tlv_filter);
  1027. }
  1028. }
  1029. return status;
  1030. }
  1031. #else
  1032. /**
  1033. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1034. * @soc: Common DP soc handle
  1035. *
  1036. * Return: QDF_STATUS
  1037. */
  1038. static QDF_STATUS
  1039. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1040. {
  1041. int i;
  1042. int mac_id;
  1043. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1044. struct dp_srng *rx_mac_srng;
  1045. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1046. /*
  1047. * In Beryllium chipset msdu_start, mpdu_end
  1048. * and rx_attn are part of msdu_end/mpdu_start
  1049. */
  1050. htt_tlv_filter.msdu_start = 0;
  1051. htt_tlv_filter.mpdu_end = 0;
  1052. htt_tlv_filter.attention = 0;
  1053. htt_tlv_filter.mpdu_start = 1;
  1054. htt_tlv_filter.msdu_end = 1;
  1055. htt_tlv_filter.packet = 1;
  1056. htt_tlv_filter.packet_header = 1;
  1057. htt_tlv_filter.ppdu_start = 0;
  1058. htt_tlv_filter.ppdu_end = 0;
  1059. htt_tlv_filter.ppdu_end_user_stats = 0;
  1060. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1061. htt_tlv_filter.ppdu_end_status_done = 0;
  1062. htt_tlv_filter.enable_fp = 1;
  1063. htt_tlv_filter.enable_md = 0;
  1064. htt_tlv_filter.enable_md = 0;
  1065. htt_tlv_filter.enable_mo = 0;
  1066. htt_tlv_filter.fp_mgmt_filter = 0;
  1067. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1068. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1069. FILTER_DATA_MCAST |
  1070. FILTER_DATA_DATA);
  1071. htt_tlv_filter.mo_mgmt_filter = 0;
  1072. htt_tlv_filter.mo_ctrl_filter = 0;
  1073. htt_tlv_filter.mo_data_filter = 0;
  1074. htt_tlv_filter.md_data_filter = 0;
  1075. htt_tlv_filter.offset_valid = true;
  1076. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1077. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1078. htt_tlv_filter.rx_msdu_start_offset = 0;
  1079. htt_tlv_filter.rx_attn_offset = 0;
  1080. /*
  1081. * For monitor mode, the packet hdr tlv is enabled later during
  1082. * filter update
  1083. */
  1084. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1085. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1086. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1087. else
  1088. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1089. htt_tlv_filter.rx_header_offset =
  1090. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  1091. htt_tlv_filter.rx_mpdu_start_offset =
  1092. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1093. htt_tlv_filter.rx_msdu_end_offset =
  1094. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1095. dp_info("TLV subscription\n"
  1096. "msdu_start %d, mpdu_end %d, attention %d"
  1097. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  1098. "TLV offsets\n"
  1099. "msdu_start %d, mpdu_end %d, attention %d"
  1100. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  1101. htt_tlv_filter.msdu_start,
  1102. htt_tlv_filter.mpdu_end,
  1103. htt_tlv_filter.attention,
  1104. htt_tlv_filter.mpdu_start,
  1105. htt_tlv_filter.msdu_end,
  1106. htt_tlv_filter.packet_header,
  1107. htt_tlv_filter.packet,
  1108. htt_tlv_filter.rx_msdu_start_offset,
  1109. htt_tlv_filter.rx_mpdu_end_offset,
  1110. htt_tlv_filter.rx_attn_offset,
  1111. htt_tlv_filter.rx_mpdu_start_offset,
  1112. htt_tlv_filter.rx_msdu_end_offset,
  1113. htt_tlv_filter.rx_header_offset,
  1114. htt_tlv_filter.rx_packet_offset);
  1115. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1116. struct dp_pdev *pdev = soc->pdev_list[i];
  1117. if (!pdev)
  1118. continue;
  1119. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1120. int mac_for_pdev =
  1121. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1122. /*
  1123. * Obtain lmac id from pdev to access the LMAC ring
  1124. * in soc context
  1125. */
  1126. int lmac_id =
  1127. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1128. pdev->pdev_id);
  1129. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1130. if (!rx_mac_srng->hal_srng)
  1131. continue;
  1132. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1133. rx_mac_srng->hal_srng,
  1134. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1135. &htt_tlv_filter);
  1136. }
  1137. }
  1138. return status;
  1139. }
  1140. #endif
  1141. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1142. /**
  1143. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  1144. * near-full IRQs.
  1145. * @soc: Datapath SoC handle
  1146. * @int_ctx: Interrupt context
  1147. * @dp_budget: Budget of the work that can be done in the bottom half
  1148. *
  1149. * Return: work done in the handler
  1150. */
  1151. static uint32_t
  1152. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  1153. uint32_t dp_budget)
  1154. {
  1155. int ring = 0;
  1156. int budget = dp_budget;
  1157. uint32_t work_done = 0;
  1158. uint32_t remaining_quota = dp_budget;
  1159. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1160. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  1161. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  1162. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  1163. int rx_near_full_mask = rx_near_full_grp_1_mask |
  1164. rx_near_full_grp_2_mask;
  1165. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  1166. rx_near_full_mask,
  1167. tx_ring_near_full_mask);
  1168. if (rx_near_full_mask) {
  1169. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1170. if (!(rx_near_full_mask & (1 << ring)))
  1171. continue;
  1172. work_done = dp_rx_nf_process(int_ctx,
  1173. soc->reo_dest_ring[ring].hal_srng,
  1174. ring, remaining_quota);
  1175. if (work_done) {
  1176. intr_stats->num_rx_ring_near_full_masks[ring]++;
  1177. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  1178. rx_near_full_mask, ring,
  1179. work_done,
  1180. budget);
  1181. budget -= work_done;
  1182. if (budget <= 0)
  1183. goto budget_done;
  1184. remaining_quota = budget;
  1185. }
  1186. }
  1187. }
  1188. if (tx_ring_near_full_mask) {
  1189. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  1190. if (!(tx_ring_near_full_mask & (1 << ring)))
  1191. continue;
  1192. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  1193. soc->tx_comp_ring[ring].hal_srng,
  1194. ring, remaining_quota);
  1195. if (work_done) {
  1196. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  1197. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  1198. tx_ring_near_full_mask, ring,
  1199. work_done, budget);
  1200. budget -= work_done;
  1201. if (budget <= 0)
  1202. break;
  1203. remaining_quota = budget;
  1204. }
  1205. }
  1206. }
  1207. intr_stats->num_near_full_masks++;
  1208. budget_done:
  1209. return dp_budget - budget;
  1210. }
  1211. /**
  1212. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  1213. * state and set the reap_limit appropriately
  1214. * as per the near full state
  1215. * @soc: Datapath soc handle
  1216. * @dp_srng: Datapath handle for SRNG
  1217. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  1218. * the srng near-full state
  1219. *
  1220. * Return: 1, if the srng is in near-full state
  1221. * 0, if the srng is not in near-full state
  1222. */
  1223. static int
  1224. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  1225. struct dp_srng *dp_srng,
  1226. int *max_reap_limit)
  1227. {
  1228. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  1229. }
  1230. /**
  1231. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  1232. * near full IRQ handling operations.
  1233. * @arch_ops: arch ops handle
  1234. *
  1235. * Return: none
  1236. */
  1237. static inline void
  1238. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1239. {
  1240. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  1241. arch_ops->dp_srng_test_and_update_nf_params =
  1242. dp_srng_test_and_update_nf_params_be;
  1243. }
  1244. #else
  1245. static inline void
  1246. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1247. {
  1248. }
  1249. #endif
  1250. #ifdef WLAN_SUPPORT_PPEDS
  1251. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1252. {
  1253. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1254. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1255. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1256. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1257. return;
  1258. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  1259. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1260. be_soc->ppe2tcl_ring.alloc_size,
  1261. soc->ctrl_psoc,
  1262. WLAN_MD_DP_SRNG_PPE2TCL,
  1263. "ppe2tcl_ring");
  1264. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  1265. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1266. be_soc->reo2ppe_ring.alloc_size,
  1267. soc->ctrl_psoc,
  1268. WLAN_MD_DP_SRNG_REO2PPE,
  1269. "reo2ppe_ring");
  1270. dp_srng_deinit(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1271. WBM2_SW_PPE_REL_RING_ID);
  1272. wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1273. be_soc->ppeds_wbm_release_ring.alloc_size,
  1274. soc->ctrl_psoc,
  1275. WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1276. "ppeds_wbm_release_ring");
  1277. }
  1278. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1279. {
  1280. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1281. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1282. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1283. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1284. return;
  1285. dp_srng_free(soc, &be_soc->ppeds_wbm_release_ring);
  1286. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  1287. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  1288. }
  1289. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1290. {
  1291. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1292. uint32_t entries;
  1293. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1294. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1295. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1296. return QDF_STATUS_SUCCESS;
  1297. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  1298. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  1299. entries, 0)) {
  1300. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  1301. goto fail;
  1302. }
  1303. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  1304. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  1305. entries, 0)) {
  1306. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  1307. goto fail;
  1308. }
  1309. entries = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  1310. if (dp_srng_alloc(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1311. entries, 1)) {
  1312. dp_err("%pK: dp_srng_alloc failed for ppeds_wbm_release_ring",
  1313. soc);
  1314. goto fail;
  1315. }
  1316. return QDF_STATUS_SUCCESS;
  1317. fail:
  1318. dp_soc_ppeds_srng_free(soc);
  1319. return QDF_STATUS_E_NOMEM;
  1320. }
  1321. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1322. {
  1323. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1324. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1325. hal_soc_handle_t hal_soc = soc->hal_soc;
  1326. struct dp_ppe_ds_idxs idx = {0};
  1327. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1328. if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
  1329. return QDF_STATUS_SUCCESS;
  1330. if (dp_ppeds_register_soc_be(be_soc, &idx)) {
  1331. dp_err("%pK: ppeds registration failed", soc);
  1332. goto fail;
  1333. }
  1334. if (dp_srng_init_idx(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0,
  1335. idx.reo2ppe_start_idx)) {
  1336. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1337. goto fail;
  1338. }
  1339. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1340. be_soc->reo2ppe_ring.alloc_size,
  1341. soc->ctrl_psoc,
  1342. WLAN_MD_DP_SRNG_REO2PPE,
  1343. "reo2ppe_ring");
  1344. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1345. if (dp_srng_init_idx(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0,
  1346. idx.ppe2tcl_start_idx)) {
  1347. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1348. goto fail;
  1349. }
  1350. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1351. be_soc->ppe2tcl_ring.alloc_size,
  1352. soc->ctrl_psoc,
  1353. WLAN_MD_DP_SRNG_PPE2TCL,
  1354. "ppe2tcl_ring");
  1355. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1356. be_soc->ppe2tcl_ring.hal_srng,
  1357. WBM2_SW_PPE_REL_MAP_ID);
  1358. if (dp_srng_init(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1359. WBM2_SW_PPE_REL_RING_ID, 0)) {
  1360. dp_err("%pK: dp_srng_init failed for ppeds_wbm_release_ring",
  1361. soc);
  1362. goto fail;
  1363. }
  1364. wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1365. be_soc->ppeds_wbm_release_ring.alloc_size,
  1366. soc->ctrl_psoc,
  1367. WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1368. "ppeds_wbm_release_ring");
  1369. return QDF_STATUS_SUCCESS;
  1370. fail:
  1371. dp_soc_ppeds_srng_deinit(soc);
  1372. return QDF_STATUS_E_NOMEM;
  1373. }
  1374. #else
  1375. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1376. {
  1377. }
  1378. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1379. {
  1380. }
  1381. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1382. {
  1383. return QDF_STATUS_SUCCESS;
  1384. }
  1385. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1386. {
  1387. return QDF_STATUS_SUCCESS;
  1388. }
  1389. #endif
  1390. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1391. {
  1392. uint32_t i;
  1393. dp_soc_ppeds_srng_deinit(soc);
  1394. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1395. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1396. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1397. RXDMA_BUF, 0);
  1398. }
  1399. }
  1400. }
  1401. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1402. {
  1403. uint32_t i;
  1404. dp_soc_ppeds_srng_free(soc);
  1405. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1406. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1407. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1408. }
  1409. }
  1410. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1411. {
  1412. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1413. uint32_t ring_size;
  1414. uint32_t i;
  1415. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1416. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1417. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1418. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1419. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1420. RXDMA_BUF, ring_size, 0)) {
  1421. dp_err("%pK: dp_srng_alloc failed refill ring",
  1422. soc);
  1423. goto fail;
  1424. }
  1425. }
  1426. }
  1427. if (dp_soc_ppeds_srng_alloc(soc)) {
  1428. dp_err("%pK: ppe rings alloc failed",
  1429. soc);
  1430. goto fail;
  1431. }
  1432. return QDF_STATUS_SUCCESS;
  1433. fail:
  1434. dp_soc_srng_free_be(soc);
  1435. return QDF_STATUS_E_NOMEM;
  1436. }
  1437. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1438. {
  1439. int i = 0;
  1440. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1441. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1442. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1443. RXDMA_BUF, 0, 0)) {
  1444. dp_err("%pK: dp_srng_init failed refill ring",
  1445. soc);
  1446. goto fail;
  1447. }
  1448. }
  1449. }
  1450. if (dp_soc_ppeds_srng_init(soc)) {
  1451. dp_err("%pK: ppe ds rings init failed",
  1452. soc);
  1453. goto fail;
  1454. }
  1455. return QDF_STATUS_SUCCESS;
  1456. fail:
  1457. dp_soc_srng_deinit_be(soc);
  1458. return QDF_STATUS_E_NOMEM;
  1459. }
  1460. #ifdef WLAN_FEATURE_11BE_MLO
  1461. static inline unsigned
  1462. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1463. union dp_align_mac_addr *mac_addr)
  1464. {
  1465. uint32_t index;
  1466. index =
  1467. mac_addr->align2.bytes_ab ^
  1468. mac_addr->align2.bytes_cd ^
  1469. mac_addr->align2.bytes_ef;
  1470. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1471. index &= mld_hash_obj->mld_peer_hash.mask;
  1472. return index;
  1473. }
  1474. QDF_STATUS
  1475. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1476. int hash_elems)
  1477. {
  1478. int i, log2;
  1479. if (!mld_hash_obj)
  1480. return QDF_STATUS_E_FAILURE;
  1481. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1482. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1483. log2 = dp_log2_ceil(hash_elems);
  1484. hash_elems = 1 << log2;
  1485. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1486. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1487. /* allocate an array of TAILQ peer object lists */
  1488. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1489. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1490. if (!mld_hash_obj->mld_peer_hash.bins)
  1491. return QDF_STATUS_E_NOMEM;
  1492. for (i = 0; i < hash_elems; i++)
  1493. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1494. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1495. return QDF_STATUS_SUCCESS;
  1496. }
  1497. void
  1498. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1499. {
  1500. if (!mld_hash_obj)
  1501. return;
  1502. if (mld_hash_obj->mld_peer_hash.bins) {
  1503. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1504. mld_hash_obj->mld_peer_hash.bins = NULL;
  1505. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1506. }
  1507. }
  1508. #ifdef WLAN_MLO_MULTI_CHIP
  1509. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1510. {
  1511. /* In case of MULTI chip MLO peer hash table when MLO global object
  1512. * is created, avoid from SOC attach path
  1513. */
  1514. return QDF_STATUS_SUCCESS;
  1515. }
  1516. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1517. {
  1518. }
  1519. #else
  1520. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1521. {
  1522. dp_mld_peer_hash_obj_t mld_hash_obj;
  1523. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1524. if (!mld_hash_obj)
  1525. return QDF_STATUS_E_FAILURE;
  1526. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1527. }
  1528. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1529. {
  1530. dp_mld_peer_hash_obj_t mld_hash_obj;
  1531. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1532. if (!mld_hash_obj)
  1533. return;
  1534. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1535. }
  1536. #endif
  1537. static struct dp_peer *
  1538. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1539. uint8_t *peer_mac_addr,
  1540. int mac_addr_is_aligned,
  1541. enum dp_mod_id mod_id,
  1542. uint8_t vdev_id)
  1543. {
  1544. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1545. uint32_t index;
  1546. struct dp_peer *peer;
  1547. struct dp_vdev *vdev;
  1548. dp_mld_peer_hash_obj_t mld_hash_obj;
  1549. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1550. if (!mld_hash_obj)
  1551. return NULL;
  1552. if (!mld_hash_obj->mld_peer_hash.bins)
  1553. return NULL;
  1554. if (mac_addr_is_aligned) {
  1555. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1556. } else {
  1557. qdf_mem_copy(
  1558. &local_mac_addr_aligned.raw[0],
  1559. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1560. mac_addr = &local_mac_addr_aligned;
  1561. }
  1562. if (vdev_id != DP_VDEV_ALL) {
  1563. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1564. if (!vdev) {
  1565. dp_err("vdev is null\n");
  1566. return NULL;
  1567. }
  1568. } else {
  1569. vdev = NULL;
  1570. }
  1571. /* search mld peer table if no link peer for given mac address */
  1572. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1573. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1574. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1575. hash_list_elem) {
  1576. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1577. if ((vdev_id == DP_VDEV_ALL) || (
  1578. dp_peer_find_mac_addr_cmp(
  1579. &peer->vdev->mld_mac_addr,
  1580. &vdev->mld_mac_addr) == 0)) {
  1581. /* take peer reference before returning */
  1582. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1583. QDF_STATUS_SUCCESS)
  1584. peer = NULL;
  1585. if (vdev)
  1586. dp_vdev_unref_delete(soc, vdev, mod_id);
  1587. qdf_spin_unlock_bh(
  1588. &mld_hash_obj->mld_peer_hash_lock);
  1589. return peer;
  1590. }
  1591. }
  1592. }
  1593. if (vdev)
  1594. dp_vdev_unref_delete(soc, vdev, mod_id);
  1595. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1596. return NULL; /* failure */
  1597. }
  1598. static void
  1599. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1600. {
  1601. uint32_t index;
  1602. struct dp_peer *tmppeer = NULL;
  1603. int found = 0;
  1604. dp_mld_peer_hash_obj_t mld_hash_obj;
  1605. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1606. if (!mld_hash_obj)
  1607. return;
  1608. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1609. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1610. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1611. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1612. hash_list_elem) {
  1613. if (tmppeer == peer) {
  1614. found = 1;
  1615. break;
  1616. }
  1617. }
  1618. QDF_ASSERT(found);
  1619. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1620. hash_list_elem);
  1621. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1622. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1623. }
  1624. static void
  1625. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1626. {
  1627. uint32_t index;
  1628. dp_mld_peer_hash_obj_t mld_hash_obj;
  1629. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1630. if (!mld_hash_obj)
  1631. return;
  1632. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1633. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1634. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1635. DP_MOD_ID_CONFIG))) {
  1636. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1637. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1638. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1639. return;
  1640. }
  1641. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1642. hash_list_elem);
  1643. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1644. }
  1645. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1646. {
  1647. uint32_t index;
  1648. struct dp_peer *peer;
  1649. dp_mld_peer_hash_obj_t mld_hash_obj;
  1650. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1651. if (!mld_hash_obj)
  1652. return;
  1653. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1654. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1655. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1656. hash_list_elem) {
  1657. dp_print_peer_ast_entries(soc, peer, NULL);
  1658. }
  1659. }
  1660. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1661. }
  1662. #endif
  1663. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1664. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1665. struct dp_vdev *vdev)
  1666. {
  1667. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1668. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1669. hal_soc_handle_t hal_soc = soc->hal_soc;
  1670. uint8_t vdev_id = vdev->vdev_id;
  1671. if (vdev->opmode == wlan_op_mode_sta) {
  1672. if (vdev->pdev->isolation)
  1673. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1674. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1675. else
  1676. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1677. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1678. } else if (vdev->opmode == wlan_op_mode_ap) {
  1679. hal_tx_mcast_mlo_reinject_routing_set(
  1680. hal_soc,
  1681. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  1682. if (vdev->mlo_vdev) {
  1683. hal_tx_vdev_mcast_ctrl_set(
  1684. hal_soc,
  1685. vdev_id,
  1686. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1687. } else {
  1688. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1689. vdev_id,
  1690. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1691. }
  1692. }
  1693. }
  1694. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1695. {
  1696. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1697. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1698. union hal_tx_bank_config *bank_config;
  1699. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  1700. return;
  1701. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  1702. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  1703. be_vdev->bank_id);
  1704. }
  1705. #endif
  1706. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1707. defined(WLAN_MCAST_MLO)
  1708. static void dp_mlo_mcast_reset_pri_mcast(struct dp_vdev_be *be_vdev,
  1709. struct dp_vdev *ptnr_vdev,
  1710. void *arg)
  1711. {
  1712. struct dp_vdev_be *be_ptnr_vdev =
  1713. dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  1714. be_ptnr_vdev->mcast_primary = false;
  1715. }
  1716. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1717. struct dp_vdev *vdev,
  1718. cdp_config_param_type val)
  1719. {
  1720. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1721. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1722. be_vdev->vdev.pdev->soc);
  1723. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1724. vdev->mlo_vdev = true;
  1725. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1726. vdev->vdev_id,
  1727. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1728. if (be_vdev->mcast_primary) {
  1729. dp_mcast_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  1730. dp_mlo_mcast_reset_pri_mcast,
  1731. (void *)&be_vdev->mcast_primary,
  1732. DP_MOD_ID_TX_MCAST);
  1733. }
  1734. }
  1735. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  1736. struct dp_vdev *vdev,
  1737. cdp_config_param_type val)
  1738. {
  1739. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1740. be_vdev->mcast_primary = false;
  1741. vdev->mlo_vdev = false;
  1742. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1743. vdev->vdev_id,
  1744. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1745. }
  1746. /**
  1747. * dp_txrx_get_vdev_mcast_param_be() - Target specific ops for getting vdev
  1748. * params related to multicast
  1749. * @soc: DP soc handle
  1750. * @vdev: pointer to vdev structure
  1751. * @val: buffer address
  1752. *
  1753. * Return: QDF_STATUS
  1754. */
  1755. static
  1756. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  1757. struct dp_vdev *vdev,
  1758. cdp_config_param_type *val)
  1759. {
  1760. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1761. if (be_vdev->mcast_primary)
  1762. val->cdp_vdev_param_mcast_vdev = true;
  1763. else
  1764. val->cdp_vdev_param_mcast_vdev = false;
  1765. return QDF_STATUS_SUCCESS;
  1766. }
  1767. #else
  1768. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1769. struct dp_vdev *vdev,
  1770. cdp_config_param_type val)
  1771. {
  1772. }
  1773. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  1774. struct dp_vdev *vdev,
  1775. cdp_config_param_type val)
  1776. {
  1777. }
  1778. static
  1779. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  1780. struct dp_vdev *vdev,
  1781. cdp_config_param_type *val)
  1782. {
  1783. return QDF_STATUS_SUCCESS;
  1784. }
  1785. #endif
  1786. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1787. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1788. uint8_t tx_ring_id,
  1789. uint8_t bm_id)
  1790. {
  1791. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1792. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1793. bm_id);
  1794. }
  1795. #else
  1796. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1797. uint8_t tx_ring_id,
  1798. uint8_t bm_id)
  1799. {
  1800. }
  1801. #endif
  1802. /**
  1803. * dp_txrx_set_vdev_param_be() - Target specific ops while setting vdev params
  1804. * @soc: DP soc handle
  1805. * @vdev: pointer to vdev structure
  1806. * @param: parameter type to get value
  1807. * @val: value
  1808. *
  1809. * Return: QDF_STATUS
  1810. */
  1811. static
  1812. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1813. struct dp_vdev *vdev,
  1814. enum cdp_vdev_param_type param,
  1815. cdp_config_param_type val)
  1816. {
  1817. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1818. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1819. switch (param) {
  1820. case CDP_TX_ENCAP_TYPE:
  1821. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1822. case CDP_UPDATE_TDLS_FLAGS:
  1823. dp_tx_update_bank_profile(be_soc, be_vdev);
  1824. break;
  1825. case CDP_ENABLE_CIPHER:
  1826. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1827. dp_tx_update_bank_profile(be_soc, be_vdev);
  1828. break;
  1829. case CDP_SET_MCAST_VDEV:
  1830. dp_txrx_set_mlo_mcast_primary_vdev_param_be(vdev, val);
  1831. break;
  1832. case CDP_RESET_MLO_MCAST_VDEV:
  1833. dp_txrx_reset_mlo_mcast_primary_vdev_param_be(vdev, val);
  1834. break;
  1835. default:
  1836. dp_warn("invalid param %d", param);
  1837. break;
  1838. }
  1839. return QDF_STATUS_SUCCESS;
  1840. }
  1841. #ifdef WLAN_FEATURE_11BE_MLO
  1842. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1843. static inline void
  1844. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1845. {
  1846. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1847. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1848. /*
  1849. * Double the peers since we use ML indication bit
  1850. * alongwith peer_id to find peers.
  1851. */
  1852. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1853. }
  1854. #else
  1855. static inline void
  1856. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1857. {
  1858. soc->max_peer_id =
  1859. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1860. }
  1861. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1862. #else
  1863. static inline void
  1864. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1865. {
  1866. soc->max_peer_id = soc->max_peers;
  1867. }
  1868. #endif /* WLAN_FEATURE_11BE_MLO */
  1869. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1870. {
  1871. if (soc->host_ast_db_enable)
  1872. dp_peer_ast_hash_detach(soc);
  1873. }
  1874. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1875. {
  1876. QDF_STATUS status;
  1877. if (soc->host_ast_db_enable) {
  1878. status = dp_peer_ast_hash_attach(soc);
  1879. if (QDF_IS_STATUS_ERROR(status))
  1880. return status;
  1881. }
  1882. dp_soc_max_peer_id_set(soc);
  1883. return QDF_STATUS_SUCCESS;
  1884. }
  1885. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  1886. uint8_t *dest_mac,
  1887. uint8_t vdev_id)
  1888. {
  1889. struct dp_peer *peer = NULL;
  1890. struct dp_peer *tgt_peer = NULL;
  1891. struct dp_ast_entry *ast_entry = NULL;
  1892. uint16_t peer_id;
  1893. qdf_spin_lock_bh(&soc->ast_lock);
  1894. ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
  1895. if (!ast_entry) {
  1896. qdf_spin_unlock_bh(&soc->ast_lock);
  1897. dp_err("NULL ast entry");
  1898. return NULL;
  1899. }
  1900. peer_id = ast_entry->peer_id;
  1901. qdf_spin_unlock_bh(&soc->ast_lock);
  1902. if (peer_id == HTT_INVALID_PEER)
  1903. return NULL;
  1904. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
  1905. if (!peer) {
  1906. dp_err("NULL peer for peer_id:%d", peer_id);
  1907. return NULL;
  1908. }
  1909. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  1910. /*
  1911. * Once tgt_peer is obtained,
  1912. * release the ref taken for original peer.
  1913. */
  1914. dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
  1915. dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
  1916. return tgt_peer;
  1917. }
  1918. #ifdef WLAN_FEATURE_11BE_MLO
  1919. #ifdef WLAN_MCAST_MLO
  1920. static inline void
  1921. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1922. {
  1923. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1924. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1925. arch_ops->dp_tx_is_mcast_primary = dp_tx_mlo_is_mcast_primary_be;
  1926. }
  1927. #else /* WLAN_MCAST_MLO */
  1928. static inline void
  1929. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1930. {
  1931. }
  1932. #endif /* WLAN_MCAST_MLO */
  1933. #ifdef WLAN_MLO_MULTI_CHIP
  1934. static inline void
  1935. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  1936. {
  1937. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  1938. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  1939. arch_ops->dp_soc_get_by_idle_bm_id = dp_soc_get_by_idle_bm_id;
  1940. }
  1941. #else
  1942. static inline void
  1943. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  1944. {
  1945. }
  1946. #endif
  1947. static inline void
  1948. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1949. {
  1950. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  1951. dp_initialize_arch_ops_be_mlo_multi_chip(arch_ops);
  1952. arch_ops->mlo_peer_find_hash_detach =
  1953. dp_mlo_peer_find_hash_detach_wrapper;
  1954. arch_ops->mlo_peer_find_hash_attach =
  1955. dp_mlo_peer_find_hash_attach_wrapper;
  1956. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1957. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1958. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1959. }
  1960. #else /* WLAN_FEATURE_11BE_MLO */
  1961. static inline void
  1962. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1963. {
  1964. }
  1965. #endif /* WLAN_FEATURE_11BE_MLO */
  1966. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  1967. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  1968. #define DP_LMAC_PEER_ID_MSB_MLO 3
  1969. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1970. struct cdp_peer_setup_info *setup_info,
  1971. enum cdp_host_reo_dest_ring *reo_dest,
  1972. bool *hash_based,
  1973. uint8_t *lmac_peer_id_msb)
  1974. {
  1975. struct dp_soc *soc = vdev->pdev->soc;
  1976. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1977. if (!be_soc->mlo_enabled)
  1978. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  1979. hash_based);
  1980. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1981. *reo_dest = vdev->pdev->reo_dest;
  1982. /* Not a ML link peer use non-mlo */
  1983. if (!setup_info) {
  1984. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1985. return;
  1986. }
  1987. /* For STA ML VAP we do not have num links info at this point
  1988. * use MLO case always
  1989. */
  1990. if (vdev->opmode == wlan_op_mode_sta) {
  1991. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  1992. return;
  1993. }
  1994. /* For AP ML VAP consider the peer as ML only it associates with
  1995. * multiple links
  1996. */
  1997. if (setup_info->num_links == 1) {
  1998. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1999. return;
  2000. }
  2001. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2002. }
  2003. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2004. uint32_t *remap0,
  2005. uint32_t *remap1,
  2006. uint32_t *remap2)
  2007. {
  2008. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2009. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2010. uint32_t reo_mlo_config =
  2011. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  2012. if (!be_soc->mlo_enabled)
  2013. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2014. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2015. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  2016. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2017. return true;
  2018. }
  2019. #else
  2020. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2021. struct cdp_peer_setup_info *setup_info,
  2022. enum cdp_host_reo_dest_ring *reo_dest,
  2023. bool *hash_based,
  2024. uint8_t *lmac_peer_id_msb)
  2025. {
  2026. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  2027. }
  2028. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2029. uint32_t *remap0,
  2030. uint32_t *remap1,
  2031. uint32_t *remap2)
  2032. {
  2033. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2034. }
  2035. #endif
  2036. #ifdef IPA_OFFLOAD
  2037. static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
  2038. {
  2039. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2040. return be_soc->ipa_bank_id;
  2041. }
  2042. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2043. {
  2044. arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
  2045. }
  2046. #else /* !IPA_OFFLOAD */
  2047. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2048. {
  2049. }
  2050. #endif /* IPA_OFFLOAD */
  2051. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  2052. {
  2053. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  2054. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  2055. arch_ops->dp_rx_process = dp_rx_process_be;
  2056. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  2057. arch_ops->tx_comp_get_params_from_hal_desc =
  2058. dp_tx_comp_get_params_from_hal_desc_be;
  2059. arch_ops->dp_tx_process_htt_completion =
  2060. dp_tx_process_htt_completion_be;
  2061. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  2062. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  2063. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  2064. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  2065. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  2066. dp_wbm_get_rx_desc_from_hal_desc_be;
  2067. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  2068. arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be;
  2069. #endif
  2070. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  2071. #ifdef WIFI_MONITOR_SUPPORT
  2072. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  2073. #endif
  2074. arch_ops->dp_rx_desc_cookie_2_va =
  2075. dp_rx_desc_cookie_2_va_be;
  2076. arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
  2077. arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
  2078. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  2079. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  2080. arch_ops->txrx_soc_init = dp_soc_init_be;
  2081. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  2082. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  2083. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  2084. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  2085. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  2086. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  2087. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  2088. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  2089. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  2090. arch_ops->txrx_peer_setup = dp_peer_setup_be;
  2091. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  2092. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  2093. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  2094. arch_ops->dp_rx_peer_metadata_peer_id_get =
  2095. dp_rx_peer_metadata_peer_id_get_be;
  2096. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  2097. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  2098. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  2099. dp_initialize_arch_ops_be_mlo(arch_ops);
  2100. arch_ops->dp_rx_replenish_soc_get = dp_rx_replensih_soc_get;
  2101. arch_ops->dp_peer_rx_reorder_queue_setup =
  2102. dp_peer_rx_reorder_queue_setup_be;
  2103. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  2104. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  2105. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  2106. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  2107. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  2108. dp_reconfig_tx_vdev_mcast_ctrl_be;
  2109. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  2110. #endif
  2111. #ifdef WLAN_SUPPORT_PPEDS
  2112. arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
  2113. arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be;
  2114. arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be;
  2115. arch_ops->dp_register_ppeds_interrupts = dp_register_ppeds_interrupts;
  2116. arch_ops->dp_free_ppeds_interrupts = dp_free_ppeds_interrupts;
  2117. arch_ops->dp_tx_ppeds_inuse_desc = dp_ppeds_inuse_desc;
  2118. #endif
  2119. dp_init_near_full_arch_ops_be(arch_ops);
  2120. arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be;
  2121. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  2122. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  2123. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  2124. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  2125. arch_ops->txrx_get_vdev_mcast_param = dp_txrx_get_vdev_mcast_param_be;
  2126. dp_initialize_arch_ops_be_ipa(arch_ops);
  2127. }