sde_plane.c 142 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010
  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/debugfs.h>
  21. #include <linux/dma-buf.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/msm_drm_pp.h>
  24. #include <linux/version.h>
  25. #include "msm_prop.h"
  26. #include "msm_drv.h"
  27. #include "sde_kms.h"
  28. #include "sde_fence.h"
  29. #include "sde_formats.h"
  30. #include "sde_hw_sspp.h"
  31. #include "sde_hw_catalog_format.h"
  32. #include "sde_trace.h"
  33. #include "sde_crtc.h"
  34. #include "sde_vbif.h"
  35. #include "sde_plane.h"
  36. #include "sde_color_processing.h"
  37. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  40. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  41. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  42. #define PHASE_STEP_SHIFT 21
  43. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  44. #define PHASE_RESIDUAL 15
  45. #define SHARP_STRENGTH_DEFAULT 32
  46. #define SHARP_EDGE_THR_DEFAULT 112
  47. #define SHARP_SMOOTH_THR_DEFAULT 8
  48. #define SHARP_NOISE_THR_DEFAULT 2
  49. #define SDE_NAME_SIZE 12
  50. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  51. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  52. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  53. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  54. /**
  55. * enum sde_plane_qos - Different qos configurations for each pipe
  56. *
  57. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  58. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  59. * this configuration is mutually exclusive from VBLANK_CTRL.
  60. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  61. */
  62. enum sde_plane_qos {
  63. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  64. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  65. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  66. };
  67. struct sde_plane {
  68. struct drm_plane base;
  69. struct mutex lock;
  70. enum sde_sspp pipe;
  71. uint64_t features; /* capabilities from catalog */
  72. uint32_t perf_features; /* perf capabilities from catalog */
  73. uint32_t nformats;
  74. uint32_t formats[64];
  75. struct sde_hw_pipe *pipe_hw;
  76. struct sde_hw_pipe_cfg pipe_cfg;
  77. struct sde_hw_sharp_cfg sharp_cfg;
  78. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  79. uint32_t color_fill;
  80. bool is_error;
  81. bool is_rt_pipe;
  82. enum sde_wb_usage_type wb_usage_type;
  83. bool is_virtual;
  84. struct list_head mplane_list;
  85. struct sde_mdss_cfg *catalog;
  86. bool revalidate;
  87. bool xin_halt_forced_clk;
  88. struct sde_csc_cfg csc_cfg;
  89. struct sde_csc_cfg *csc_usr_ptr;
  90. struct sde_csc_cfg *csc_ptr;
  91. uint32_t cached_lut_flag;
  92. struct sde_hw_scaler3_cfg scaler3_cfg;
  93. struct sde_hw_pixel_ext pixel_ext;
  94. const struct sde_sspp_sub_blks *pipe_sblk;
  95. char pipe_name[SDE_NAME_SIZE];
  96. struct msm_property_info property_info;
  97. struct msm_property_data property_data[PLANE_PROP_COUNT];
  98. struct drm_property_blob *blob_info;
  99. struct drm_property_blob *blob_rot_caps;
  100. /* debugfs related stuff */
  101. struct dentry *debugfs_root;
  102. bool debugfs_default_scale;
  103. };
  104. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  105. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  106. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  107. {
  108. struct msm_drm_private *priv;
  109. if (!plane || !plane->dev)
  110. return NULL;
  111. priv = plane->dev->dev_private;
  112. if (!priv)
  113. return NULL;
  114. return to_sde_kms(priv->kms);
  115. }
  116. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  117. {
  118. struct drm_plane_state *pstate = NULL;
  119. struct drm_crtc *drm_crtc = NULL;
  120. struct sde_crtc *sde_crtc = NULL;
  121. struct sde_crtc_mixer *mixer = NULL;
  122. struct sde_hw_ctl *ctl = NULL;
  123. if (!plane) {
  124. DRM_ERROR("Invalid plane %pK\n", plane);
  125. return NULL;
  126. }
  127. pstate = plane->state;
  128. if (!pstate) {
  129. DRM_ERROR("Invalid plane state %pK\n", pstate);
  130. return NULL;
  131. }
  132. drm_crtc = pstate->crtc;
  133. if (!drm_crtc) {
  134. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  135. return NULL;
  136. }
  137. sde_crtc = to_sde_crtc(drm_crtc);
  138. if (!sde_crtc) {
  139. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  140. return NULL;
  141. }
  142. /* it will always return the first mixer and single CTL */
  143. mixer = sde_crtc->mixers;
  144. if (!mixer) {
  145. DRM_ERROR("invalid mixer %pK\n", mixer);
  146. return NULL;
  147. }
  148. ctl = mixer->hw_ctl;
  149. if (!mixer) {
  150. DRM_ERROR("invalid ctl %pK\n", ctl);
  151. return NULL;
  152. }
  153. return ctl;
  154. }
  155. static void _sde_plane_setup_panel_stacking(struct sde_plane *psde,
  156. struct sde_plane_state *pstate)
  157. {
  158. struct sde_hw_pipe_line_insertion_cfg *cfg;
  159. struct sde_crtc_state *cstate;
  160. u32 h_start = 0, h_total = 0, y_start = 0;
  161. struct drm_plane_state *dpstate = NULL;
  162. struct drm_crtc *drm_crtc = NULL;
  163. if (!psde || !psde->base.state || !psde->base.state->crtc) {
  164. SDE_ERROR("Invalid plane psde %p or drm plane state or drm crtc\n", psde);
  165. return;
  166. }
  167. dpstate = psde->base.state;
  168. drm_crtc = dpstate->crtc;
  169. cstate = to_sde_crtc_state(drm_crtc->state);
  170. pstate->lineinsertion_feature = cstate->line_insertion.panel_line_insertion_enable;
  171. if ((!test_bit(SDE_SSPP_LINE_INSERTION, (unsigned long *)&psde->features)) ||
  172. !cstate->line_insertion.panel_line_insertion_enable)
  173. return;
  174. cfg = &pstate->line_insertion_cfg;
  175. memset(cfg, 0, sizeof(*cfg));
  176. if (!cstate->line_insertion.padding_height)
  177. return;
  178. sde_crtc_calc_vpadding_param(psde->base.state->crtc->state,
  179. pstate->base.crtc_y, pstate->base.crtc_h,
  180. &y_start, &h_start, &h_total);
  181. cfg->enable = true;
  182. cfg->dummy_lines = cstate->line_insertion.padding_dummy;
  183. cfg->active_lines = cstate->line_insertion.padding_active;
  184. cfg->first_active_lines = h_start;
  185. cfg->dst_h = h_total;
  186. psde->pipe_cfg.dst_rect.y += y_start - pstate->base.crtc_y;
  187. }
  188. static bool sde_plane_enabled(const struct drm_plane_state *state)
  189. {
  190. return state && state->fb && state->crtc;
  191. }
  192. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  193. {
  194. struct sde_plane *psde;
  195. if (!plane)
  196. return false;
  197. psde = to_sde_plane(plane);
  198. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  199. }
  200. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  201. enum sde_sspp_multirect_index rect_mode, bool enable)
  202. {
  203. struct sde_plane *psde;
  204. if (!plane)
  205. return;
  206. psde = to_sde_plane(plane);
  207. if (psde->pipe_hw->ops.set_src_split_order)
  208. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  209. rect_mode, enable);
  210. }
  211. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  212. {
  213. struct sde_plane *psde;
  214. struct sde_kms *sde_kms;
  215. struct msm_drm_private *priv;
  216. if (!plane || !plane->dev) {
  217. SDE_ERROR("invalid plane\n");
  218. return;
  219. }
  220. priv = plane->dev->dev_private;
  221. if (!priv || !priv->kms) {
  222. SDE_ERROR("invalid KMS reference\n");
  223. return;
  224. }
  225. sde_kms = to_sde_kms(priv->kms);
  226. psde = to_sde_plane(plane);
  227. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm, sde_kms->catalog);
  228. }
  229. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  230. struct drm_crtc *crtc,
  231. struct drm_framebuffer *fb)
  232. {
  233. struct sde_plane *psde;
  234. const struct sde_format *fmt = NULL;
  235. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, ds_lut_index;
  236. struct sde_perf_cfg *perf;
  237. struct sde_plane_state *pstate;
  238. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  239. bool inline_rot = false, landscape = false;
  240. struct drm_display_mode *mode;
  241. u32 fl_require0 = 0;
  242. if (!plane || !fb) {
  243. SDE_ERROR("invalid arguments\n");
  244. return;
  245. }
  246. psde = to_sde_plane(plane);
  247. pstate = to_sde_plane_state(plane->state);
  248. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  249. SDE_ERROR("invalid arguments\n");
  250. return;
  251. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  252. return;
  253. }
  254. mode = &crtc->state->adjusted_mode;
  255. landscape = mode->hdisplay > mode->vdisplay ? true : false;
  256. frame_rate = drm_mode_vrefresh(&crtc->mode);
  257. perf = &psde->catalog->perf;
  258. qos_count = perf->qos_refresh_count;
  259. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  260. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  261. (fps_index == qos_count - 1))
  262. break;
  263. fps_index++;
  264. }
  265. if (psde->is_rt_pipe) {
  266. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  267. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  268. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  269. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  270. else if (inline_rot)
  271. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  272. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  273. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  274. else
  275. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  276. } else {
  277. lut_index = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  278. SDE_QOS_LUT_USAGE_OFFLINE_WB : SDE_QOS_LUT_USAGE_NRT;
  279. }
  280. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  281. if (psde->scaler3_cfg.enable)
  282. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  283. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_CREQ_LUT_TYPE_MAX);
  284. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  285. ds_lut_index = lut_index * SDE_DANGER_SAFE_LUT_TYPE_MAX;
  286. if (landscape) {
  287. if (psde->catalog->qos_target_time_ns && sde_crtc->line_time_in_ns)
  288. fl_require0 = psde->catalog->qos_target_time_ns /
  289. (sde_crtc->line_time_in_ns * 2);
  290. if (!fl_require0 || fl_require0 < 4.5)
  291. ds_lut_index += SDE_DANGER_SAFE_LUT_TYPE_LANDSCAPE;
  292. }
  293. ds_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_DANGER_SAFE_LUT_TYPE_MAX);
  294. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[ds_lut_index];
  295. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[ds_lut_index];
  296. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0,
  297. (fmt) ? fmt->fetch_mode : 0, psde->pipe_qos_cfg.danger_lut,
  298. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut);
  299. SDE_DEBUG("plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d lut[0x%x,0x%x 0x%llx] rt:%d type:%d\n",
  300. plane->base.id, psde->pipe - SSPP_VIG0,
  301. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  302. fmt ? fmt->fetch_mode : -1, psde->pipe_qos_cfg.danger_lut,
  303. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut,
  304. psde->is_rt_pipe, psde->wb_usage_type);
  305. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  306. }
  307. /**
  308. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  309. * @plane: Pointer to drm plane
  310. * @enable: true to enable QoS control
  311. * @flags: QoS control mode (enum sde_plane_qos)
  312. */
  313. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  314. bool enable, u32 flags)
  315. {
  316. struct sde_plane *psde;
  317. if (!plane) {
  318. SDE_ERROR("invalid arguments\n");
  319. return;
  320. }
  321. psde = to_sde_plane(plane);
  322. if (!psde->pipe_hw || !psde->pipe_sblk) {
  323. SDE_ERROR("invalid arguments\n");
  324. return;
  325. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  326. return;
  327. }
  328. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  329. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  330. psde->pipe_qos_cfg.danger_vblank =
  331. psde->pipe_sblk->danger_vblank;
  332. psde->pipe_qos_cfg.vblank_en = enable;
  333. }
  334. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  335. /* this feature overrules previous VBLANK_CTRL */
  336. psde->pipe_qos_cfg.vblank_en = false;
  337. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  338. psde->pipe_qos_cfg.danger_vblank = 0;
  339. }
  340. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  341. psde->pipe_qos_cfg.danger_safe_en = enable;
  342. if (!psde->is_rt_pipe) {
  343. psde->pipe_qos_cfg.vblank_en = false;
  344. psde->pipe_qos_cfg.danger_safe_en = false;
  345. }
  346. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  347. plane->base.id,
  348. psde->pipe - SSPP_VIG0,
  349. psde->pipe_qos_cfg.danger_safe_en,
  350. psde->pipe_qos_cfg.vblank_en,
  351. psde->pipe_qos_cfg.creq_vblank,
  352. psde->pipe_qos_cfg.danger_vblank,
  353. psde->is_rt_pipe);
  354. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  355. &psde->pipe_qos_cfg);
  356. }
  357. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  358. {
  359. struct sde_plane *psde;
  360. if (!plane)
  361. return;
  362. psde = to_sde_plane(plane);
  363. psde->revalidate = enable;
  364. }
  365. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  366. {
  367. struct sde_plane *psde;
  368. int rc;
  369. if (!plane) {
  370. SDE_ERROR("invalid arguments\n");
  371. return -EINVAL;
  372. }
  373. psde = to_sde_plane(plane);
  374. if (!psde->is_rt_pipe)
  375. goto end;
  376. rc = pm_runtime_resume_and_get(plane->dev->dev);
  377. if (rc < 0) {
  378. SDE_ERROR("failed to enable power resource %d\n", rc);
  379. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  380. return rc;
  381. }
  382. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  383. pm_runtime_put_sync(plane->dev->dev);
  384. end:
  385. return 0;
  386. }
  387. /**
  388. * _sde_plane_set_ot_limit - set OT limit for the given plane
  389. * @plane: Pointer to drm plane
  390. * @crtc: Pointer to drm crtc
  391. */
  392. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  393. struct drm_crtc *crtc)
  394. {
  395. struct sde_plane *psde;
  396. struct sde_vbif_set_ot_params ot_params;
  397. struct msm_drm_private *priv;
  398. struct sde_kms *sde_kms;
  399. if (!plane || !plane->dev || !crtc) {
  400. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  401. !plane, !crtc);
  402. return;
  403. }
  404. priv = plane->dev->dev_private;
  405. if (!priv || !priv->kms) {
  406. SDE_ERROR("invalid KMS reference\n");
  407. return;
  408. }
  409. sde_kms = to_sde_kms(priv->kms);
  410. psde = to_sde_plane(plane);
  411. if (!psde->pipe_hw) {
  412. SDE_ERROR("invalid pipe reference\n");
  413. return;
  414. }
  415. memset(&ot_params, 0, sizeof(ot_params));
  416. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  417. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  418. ot_params.width = psde->pipe_cfg.src_rect.w;
  419. ot_params.height = psde->pipe_cfg.src_rect.h;
  420. ot_params.is_wfd = ((psde->is_rt_pipe)
  421. || (psde->wb_usage_type == WB_USAGE_OFFLINE_WB)) ? false : true;
  422. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  423. ot_params.vbif_idx = VBIF_RT;
  424. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  425. ot_params.rd = true;
  426. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  427. }
  428. /**
  429. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  430. * @plane: Pointer to drm plane
  431. */
  432. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  433. {
  434. struct sde_plane *psde;
  435. struct sde_vbif_set_qos_params qos_params;
  436. struct msm_drm_private *priv;
  437. struct sde_kms *sde_kms;
  438. if (!plane || !plane->dev) {
  439. SDE_ERROR("invalid arguments\n");
  440. return;
  441. }
  442. priv = plane->dev->dev_private;
  443. if (!priv || !priv->kms) {
  444. SDE_ERROR("invalid KMS reference\n");
  445. return;
  446. }
  447. sde_kms = to_sde_kms(priv->kms);
  448. psde = to_sde_plane(plane);
  449. if (!psde->pipe_hw) {
  450. SDE_ERROR("invalid pipe reference\n");
  451. return;
  452. }
  453. memset(&qos_params, 0, sizeof(qos_params));
  454. qos_params.vbif_idx = VBIF_RT;
  455. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  456. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  457. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  458. if (psde->is_rt_pipe)
  459. qos_params.client_type = VBIF_RT_CLIENT;
  460. else
  461. qos_params.client_type = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  462. VBIF_OFFLINE_WB_CLIENT : VBIF_NRT_CLIENT;
  463. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  464. plane->base.id, qos_params.num,
  465. qos_params.vbif_idx,
  466. qos_params.xin_id, qos_params.client_type,
  467. qos_params.clk_ctrl);
  468. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  469. }
  470. /**
  471. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  472. * @plane: Pointer to drm plane
  473. * @pstate: Pointer to sde plane state
  474. */
  475. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  476. struct sde_plane_state *pstate)
  477. {
  478. struct sde_plane *psde;
  479. struct sde_hw_pipe_ts_cfg cfg;
  480. struct msm_drm_private *priv;
  481. struct sde_kms *sde_kms;
  482. if (!plane || !plane->dev) {
  483. SDE_ERROR("invalid arguments");
  484. return;
  485. }
  486. priv = plane->dev->dev_private;
  487. if (!priv || !priv->kms) {
  488. SDE_ERROR("invalid KMS reference\n");
  489. return;
  490. }
  491. sde_kms = to_sde_kms(priv->kms);
  492. psde = to_sde_plane(plane);
  493. if (!psde->pipe_hw) {
  494. SDE_ERROR("invalid pipe reference\n");
  495. return;
  496. }
  497. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  498. return;
  499. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  500. memset(&cfg, 0, sizeof(cfg));
  501. cfg.size = sde_plane_get_property(pstate,
  502. PLANE_PROP_PREFILL_SIZE);
  503. cfg.time = sde_plane_get_property(pstate,
  504. PLANE_PROP_PREFILL_TIME);
  505. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  506. plane->base.id, cfg.size, cfg.time);
  507. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  508. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  509. pstate->multirect_index);
  510. }
  511. /* helper to update a state's input fence pointer from the property */
  512. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  513. struct sde_plane_state *pstate, uint64_t fd)
  514. {
  515. if (!psde || !pstate) {
  516. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  517. !psde, !pstate);
  518. return;
  519. }
  520. /* clear previous reference */
  521. if (pstate->input_fence)
  522. sde_sync_put(pstate->input_fence);
  523. /* get fence pointer for later */
  524. if (fd == 0)
  525. pstate->input_fence = NULL;
  526. else
  527. pstate->input_fence = sde_sync_get(fd);
  528. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  529. }
  530. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  531. {
  532. struct sde_plane *psde;
  533. struct sde_plane_state *pstate;
  534. uint32_t prefix;
  535. void *input_fence;
  536. int ret = -EINVAL;
  537. signed long rc;
  538. if (!plane) {
  539. SDE_ERROR("invalid plane\n");
  540. } else if (!plane->state) {
  541. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  542. } else {
  543. psde = to_sde_plane(plane);
  544. pstate = to_sde_plane_state(plane->state);
  545. input_fence = pstate->input_fence;
  546. if (input_fence) {
  547. prefix = sde_sync_get_name_prefix(input_fence);
  548. rc = sde_sync_wait(input_fence, wait_ms);
  549. switch (rc) {
  550. case 0:
  551. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  552. wait_ms, prefix, sde_plane_get_property(pstate,
  553. PLANE_PROP_INPUT_FENCE));
  554. psde->is_error = true;
  555. sde_kms_timeline_status(plane->dev);
  556. ret = -ETIMEDOUT;
  557. break;
  558. case -ERESTARTSYS:
  559. SDE_ERROR_PLANE(psde,
  560. "%ums wait interrupted on %08X\n",
  561. wait_ms, prefix);
  562. psde->is_error = true;
  563. ret = -ERESTARTSYS;
  564. break;
  565. case -EINVAL:
  566. SDE_ERROR_PLANE(psde,
  567. "invalid fence param for %08X\n",
  568. prefix);
  569. psde->is_error = true;
  570. ret = -EINVAL;
  571. break;
  572. case -EBADF:
  573. SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
  574. plane->base.id,
  575. sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
  576. psde->is_error = true;
  577. ret = 0;
  578. break;
  579. default:
  580. SDE_DEBUG_PLANE(psde, "signaled\n");
  581. ret = 0;
  582. break;
  583. }
  584. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  585. } else {
  586. ret = 0;
  587. }
  588. }
  589. return ret;
  590. }
  591. /**
  592. * _sde_plane_get_aspace: gets the address space based on the
  593. * fb_translation mode property
  594. */
  595. static int _sde_plane_get_aspace(
  596. struct sde_plane *psde,
  597. struct sde_plane_state *pstate,
  598. struct msm_gem_address_space **aspace)
  599. {
  600. struct sde_kms *kms;
  601. int mode;
  602. if (!psde || !pstate || !aspace) {
  603. SDE_ERROR("invalid parameters\n");
  604. return -EINVAL;
  605. }
  606. kms = _sde_plane_get_kms(&psde->base);
  607. if (!kms) {
  608. SDE_ERROR("invalid kms\n");
  609. return -EINVAL;
  610. }
  611. mode = sde_plane_get_property(pstate,
  612. PLANE_PROP_FB_TRANSLATION_MODE);
  613. switch (mode) {
  614. case SDE_DRM_FB_NON_SEC:
  615. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  616. if (!aspace)
  617. return -EINVAL;
  618. break;
  619. case SDE_DRM_FB_SEC:
  620. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  621. if (!aspace)
  622. return -EINVAL;
  623. break;
  624. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  625. case SDE_DRM_FB_SEC_DIR_TRANS:
  626. *aspace = NULL;
  627. break;
  628. default:
  629. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  630. return -EFAULT;
  631. }
  632. return 0;
  633. }
  634. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  635. struct sde_plane_state *pstate,
  636. struct sde_hw_pipe_cfg *pipe_cfg,
  637. struct drm_framebuffer *fb)
  638. {
  639. struct sde_plane *psde;
  640. struct msm_gem_address_space *aspace = NULL;
  641. int ret, mode;
  642. bool secure = false;
  643. if (!plane || !pstate || !pipe_cfg || !fb) {
  644. SDE_ERROR(
  645. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  646. !plane, !pstate, !pipe_cfg, !fb);
  647. return;
  648. }
  649. psde = to_sde_plane(plane);
  650. if (!psde->pipe_hw) {
  651. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  652. return;
  653. }
  654. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  655. if (ret) {
  656. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  657. return;
  658. }
  659. /*
  660. * framebuffer prepare is deferred for prepare_fb calls that
  661. * happen during the transition from secure to non-secure.
  662. * Handle the prepare at this point for such cases. This can be
  663. * expected for one or two frames during the transition.
  664. */
  665. if (aspace && pstate->defer_prepare_fb) {
  666. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  667. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  668. if (ret) {
  669. SDE_ERROR_PLANE(psde,
  670. "failed to prepare framebuffer %d\n", ret);
  671. return;
  672. }
  673. pstate->defer_prepare_fb = false;
  674. }
  675. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  676. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  677. secure = true;
  678. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  679. if (ret == -EAGAIN)
  680. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  681. else if (ret) {
  682. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  683. /*
  684. * Force solid fill color on error. This is to prevent
  685. * smmu faults during secure session transition.
  686. */
  687. psde->is_error = true;
  688. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  689. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  690. pipe_cfg->layout.width,
  691. pipe_cfg->layout.height,
  692. pipe_cfg->layout.plane_addr[0],
  693. pipe_cfg->layout.plane_size[0],
  694. pipe_cfg->layout.plane_addr[1],
  695. pipe_cfg->layout.plane_size[1],
  696. pipe_cfg->layout.plane_addr[2],
  697. pipe_cfg->layout.plane_size[2],
  698. pipe_cfg->layout.plane_addr[3],
  699. pipe_cfg->layout.plane_size[3],
  700. pstate->multirect_index,
  701. secure);
  702. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  703. pstate->multirect_index);
  704. }
  705. }
  706. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  707. struct sde_plane_state *pstate)
  708. {
  709. struct sde_hw_scaler3_cfg *cfg;
  710. int ret = 0;
  711. if (!psde || !pstate) {
  712. SDE_ERROR("invalid args\n");
  713. return -EINVAL;
  714. }
  715. cfg = &psde->scaler3_cfg;
  716. cfg->dir_lut = msm_property_get_blob(
  717. &psde->property_info,
  718. &pstate->property_state, &cfg->dir_len,
  719. PLANE_PROP_SCALER_LUT_ED);
  720. cfg->cir_lut = msm_property_get_blob(
  721. &psde->property_info,
  722. &pstate->property_state, &cfg->cir_len,
  723. PLANE_PROP_SCALER_LUT_CIR);
  724. cfg->sep_lut = msm_property_get_blob(
  725. &psde->property_info,
  726. &pstate->property_state, &cfg->sep_len,
  727. PLANE_PROP_SCALER_LUT_SEP);
  728. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  729. ret = -ENODATA;
  730. return ret;
  731. }
  732. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  733. struct sde_plane_state *pstate)
  734. {
  735. struct sde_hw_scaler3_cfg *cfg;
  736. cfg = &psde->scaler3_cfg;
  737. cfg->sep_lut = msm_property_get_blob(
  738. &psde->property_info,
  739. &pstate->property_state, &cfg->sep_len,
  740. PLANE_PROP_SCALER_LUT_SEP);
  741. return cfg->sep_lut ? 0 : -ENODATA;
  742. }
  743. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  744. struct sde_plane_state *pstate, const struct sde_format *fmt,
  745. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  746. {
  747. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  748. struct sde_hw_scaler3_cfg *scale_cfg;
  749. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  750. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  751. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  752. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  753. chroma_subsmpl_h, chroma_subsmpl_v);
  754. return;
  755. }
  756. scale_cfg = &psde->scaler3_cfg;
  757. src_w = psde->pipe_cfg.src_rect.w;
  758. src_h = psde->pipe_cfg.src_rect.h;
  759. dst_w = psde->pipe_cfg.dst_rect.w;
  760. dst_h = psde->pipe_cfg.dst_rect.h;
  761. memset(scale_cfg, 0, sizeof(*scale_cfg));
  762. memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  763. /*
  764. * For inline rotation cases, scaler config is post-rotation,
  765. * so swap the dimensions here. However, pixel extension will
  766. * need pre-rotation settings, this will be corrected below
  767. * when calculating pixel extension settings.
  768. */
  769. if (inline_rotation)
  770. swap(src_w, src_h);
  771. decimated = DECIMATED_DIMENSION(src_w,
  772. psde->pipe_cfg.horz_decimation);
  773. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  774. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  775. decimated = DECIMATED_DIMENSION(src_h,
  776. psde->pipe_cfg.vert_decimation);
  777. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  778. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  779. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  780. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  781. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  782. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  783. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  784. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  785. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  786. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  787. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  788. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  789. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  790. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  791. for (i = 0; i < SDE_MAX_PLANES; i++) {
  792. /*
  793. * For inline rotation cases with pre-downscaling enabled
  794. * set x pre-downscale value if required. Only x direction
  795. * is currently supported. Use src_h as values have been swapped
  796. * and x direction corresponds to height value.
  797. */
  798. src_h_pre_down = src_h;
  799. if (pre_down_supported && inline_rotation) {
  800. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  801. src_h_pre_down = src_h / 2;
  802. }
  803. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  804. psde->pipe_cfg.horz_decimation);
  805. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  806. psde->pipe_cfg.vert_decimation);
  807. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  808. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  809. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  810. }
  811. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  812. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  813. /* For pixel extension we need the pre-rotated orientation */
  814. if (inline_rotation) {
  815. psde->pixel_ext.num_ext_pxls_top[i] =
  816. scale_cfg->src_width[i];
  817. psde->pixel_ext.num_ext_pxls_left[i] =
  818. scale_cfg->src_height[i];
  819. } else {
  820. psde->pixel_ext.num_ext_pxls_top[i] =
  821. scale_cfg->src_height[i];
  822. psde->pixel_ext.num_ext_pxls_left[i] =
  823. scale_cfg->src_width[i];
  824. }
  825. }
  826. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  827. && (src_w == dst_w) && !inline_rotation) ||
  828. pstate->multirect_mode)
  829. return;
  830. SDE_DEBUG_PLANE(psde,
  831. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  832. src_w, src_h, dst_w, dst_h,
  833. chroma_subsmpl_v, chroma_subsmpl_h,
  834. fmt->base.pixel_format);
  835. scale_cfg->dst_width = dst_w;
  836. scale_cfg->dst_height = dst_h;
  837. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  838. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  839. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  840. scale_cfg->lut_flag = 0;
  841. scale_cfg->blend_cfg = 1;
  842. scale_cfg->enable = 1;
  843. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  844. }
  845. /**
  846. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  847. * @psde: Pointer to SDE plane object
  848. * @src: Source size
  849. * @dst: Destination size
  850. * @phase_steps: Pointer to output array for phase steps
  851. * @filter: Pointer to output array for filter type
  852. * @fmt: Pointer to format definition
  853. * @chroma_subsampling: Subsampling amount for chroma channel
  854. *
  855. * Returns: 0 on success
  856. */
  857. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  858. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  859. enum sde_hw_filter *filter, const struct sde_format *fmt,
  860. uint32_t chroma_subsampling)
  861. {
  862. if (!psde || !phase_steps || !filter || !fmt) {
  863. SDE_ERROR(
  864. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  865. !psde, !phase_steps, !filter, !fmt);
  866. return -EINVAL;
  867. }
  868. /* calculate phase steps, leave init phase as zero */
  869. phase_steps[SDE_SSPP_COMP_0] =
  870. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  871. phase_steps[SDE_SSPP_COMP_1_2] =
  872. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  873. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  874. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  875. /* calculate scaler config, if necessary */
  876. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  877. filter[SDE_SSPP_COMP_3] =
  878. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  879. SDE_SCALE_FILTER_PCMN;
  880. if (SDE_FORMAT_IS_YUV(fmt)) {
  881. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  882. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  883. } else {
  884. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  885. filter[SDE_SSPP_COMP_1_2] =
  886. SDE_SCALE_FILTER_NEAREST;
  887. }
  888. } else {
  889. /* disable scaler */
  890. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  891. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  892. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  893. }
  894. return 0;
  895. }
  896. /**
  897. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  898. * @psde: Pointer to SDE plane object
  899. * @src: Source size
  900. * @dst: Destination size
  901. * @decimated_src: Source size after decimation, if any
  902. * @phase_steps: Pointer to output array for phase steps
  903. * @out_src: Output array for pixel extension values
  904. * @out_edge1: Output array for pixel extension first edge
  905. * @out_edge2: Output array for pixel extension second edge
  906. * @filter: Pointer to array for filter type
  907. * @fmt: Pointer to format definition
  908. * @chroma_subsampling: Subsampling amount for chroma channel
  909. * @post_compare: Whether to chroma subsampled source size for comparisions
  910. */
  911. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  912. uint32_t src, uint32_t dst, uint32_t decimated_src,
  913. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  914. int *out_edge2, enum sde_hw_filter *filter,
  915. const struct sde_format *fmt, uint32_t chroma_subsampling,
  916. bool post_compare)
  917. {
  918. int64_t edge1, edge2, caf;
  919. uint32_t src_work;
  920. int i, tmp;
  921. if (psde && phase_steps && out_src && out_edge1 &&
  922. out_edge2 && filter && fmt) {
  923. /* handle CAF for YUV formats */
  924. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  925. caf = PHASE_STEP_UNIT_SCALE;
  926. else
  927. caf = 0;
  928. for (i = 0; i < SDE_MAX_PLANES; i++) {
  929. src_work = decimated_src;
  930. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  931. src_work /= chroma_subsampling;
  932. if (post_compare)
  933. src = src_work;
  934. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  935. /* unity */
  936. edge1 = 0;
  937. edge2 = 0;
  938. } else if (dst >= src) {
  939. /* upscale */
  940. edge1 = (1 << PHASE_RESIDUAL);
  941. edge1 -= caf;
  942. edge2 = (1 << PHASE_RESIDUAL);
  943. edge2 += (dst - 1) * *(phase_steps + i);
  944. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  945. edge2 += caf;
  946. edge2 = -(edge2);
  947. } else {
  948. /* downscale */
  949. edge1 = 0;
  950. edge2 = (dst - 1) * *(phase_steps + i);
  951. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  952. edge2 += *(phase_steps + i);
  953. edge2 = -(edge2);
  954. }
  955. /* only enable CAF for luma plane */
  956. caf = 0;
  957. /* populate output arrays */
  958. *(out_src + i) = src_work;
  959. /* edge updates taken from __pxl_extn_helper */
  960. if (edge1 >= 0) {
  961. tmp = (uint32_t)edge1;
  962. tmp >>= PHASE_STEP_SHIFT;
  963. *(out_edge1 + i) = -tmp;
  964. } else {
  965. tmp = (uint32_t)(-edge1);
  966. *(out_edge1 + i) =
  967. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  968. PHASE_STEP_SHIFT;
  969. }
  970. if (edge2 >= 0) {
  971. tmp = (uint32_t)edge2;
  972. tmp >>= PHASE_STEP_SHIFT;
  973. *(out_edge2 + i) = -tmp;
  974. } else {
  975. tmp = (uint32_t)(-edge2);
  976. *(out_edge2 + i) =
  977. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  978. PHASE_STEP_SHIFT;
  979. }
  980. }
  981. }
  982. }
  983. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  984. {
  985. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  986. {
  987. /* S15.16 format */
  988. 0x00012A00, 0x00000000, 0x00019880,
  989. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  990. 0x00012A00, 0x00020480, 0x00000000,
  991. },
  992. /* signed bias */
  993. { 0xfff0, 0xff80, 0xff80,},
  994. { 0x0, 0x0, 0x0,},
  995. /* unsigned clamp */
  996. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  997. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  998. };
  999. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  1000. {
  1001. /* S15.16 format */
  1002. 0x00012A00, 0x00000000, 0x00019880,
  1003. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  1004. 0x00012A00, 0x00020480, 0x00000000,
  1005. },
  1006. /* signed bias */
  1007. { 0xffc0, 0xfe00, 0xfe00,},
  1008. { 0x0, 0x0, 0x0,},
  1009. /* unsigned clamp */
  1010. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  1011. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  1012. };
  1013. if (!psde) {
  1014. SDE_ERROR("invalid plane\n");
  1015. return;
  1016. }
  1017. /* revert to kernel default if override not available */
  1018. if (psde->csc_usr_ptr)
  1019. psde->csc_ptr = psde->csc_usr_ptr;
  1020. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  1021. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  1022. else
  1023. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  1024. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  1025. psde->csc_ptr->csc_mv[0],
  1026. psde->csc_ptr->csc_mv[1],
  1027. psde->csc_ptr->csc_mv[2]);
  1028. }
  1029. static void sde_color_process_plane_setup(struct drm_plane *plane)
  1030. {
  1031. struct sde_plane *psde;
  1032. struct sde_plane_state *pstate;
  1033. uint32_t hue, saturation, value, contrast;
  1034. struct drm_msm_memcol *memcol = NULL;
  1035. struct drm_msm_3d_gamut *vig_gamut = NULL;
  1036. struct drm_msm_igc_lut *igc = NULL;
  1037. struct drm_msm_pgc_lut *gc = NULL;
  1038. size_t memcol_sz = 0, size = 0;
  1039. struct sde_hw_cp_cfg hw_cfg = {};
  1040. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1041. bool fp16_igc, fp16_unmult;
  1042. struct drm_msm_fp16_gc *fp16_gc = NULL;
  1043. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1044. psde = to_sde_plane(plane);
  1045. pstate = to_sde_plane_state(plane->state);
  1046. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1047. if (psde->pipe_hw->ops.setup_pa_hue)
  1048. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1049. saturation = (uint32_t) sde_plane_get_property(pstate,
  1050. PLANE_PROP_SATURATION_ADJUST);
  1051. if (psde->pipe_hw->ops.setup_pa_sat)
  1052. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1053. value = (uint32_t) sde_plane_get_property(pstate,
  1054. PLANE_PROP_VALUE_ADJUST);
  1055. if (psde->pipe_hw->ops.setup_pa_val)
  1056. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1057. contrast = (uint32_t) sde_plane_get_property(pstate,
  1058. PLANE_PROP_CONTRAST_ADJUST);
  1059. if (psde->pipe_hw->ops.setup_pa_cont)
  1060. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1061. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1062. /* Skin memory color setup */
  1063. memcol = msm_property_get_blob(&psde->property_info,
  1064. &pstate->property_state,
  1065. &memcol_sz,
  1066. PLANE_PROP_SKIN_COLOR);
  1067. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1068. MEMCOLOR_SKIN, memcol);
  1069. /* Sky memory color setup */
  1070. memcol = msm_property_get_blob(&psde->property_info,
  1071. &pstate->property_state,
  1072. &memcol_sz,
  1073. PLANE_PROP_SKY_COLOR);
  1074. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1075. MEMCOLOR_SKY, memcol);
  1076. /* Foliage memory color setup */
  1077. memcol = msm_property_get_blob(&psde->property_info,
  1078. &pstate->property_state,
  1079. &memcol_sz,
  1080. PLANE_PROP_FOLIAGE_COLOR);
  1081. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1082. MEMCOLOR_FOLIAGE, memcol);
  1083. }
  1084. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1085. psde->pipe_hw->ops.setup_vig_gamut) {
  1086. vig_gamut = msm_property_get_blob(&psde->property_info,
  1087. &pstate->property_state,
  1088. &size,
  1089. PLANE_PROP_VIG_GAMUT);
  1090. hw_cfg.last_feature = 0;
  1091. hw_cfg.ctl = ctl;
  1092. hw_cfg.len = size;
  1093. hw_cfg.payload = vig_gamut;
  1094. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1095. }
  1096. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1097. psde->pipe_hw->ops.setup_vig_igc) {
  1098. igc = msm_property_get_blob(&psde->property_info,
  1099. &pstate->property_state,
  1100. &size,
  1101. PLANE_PROP_VIG_IGC);
  1102. hw_cfg.last_feature = 0;
  1103. hw_cfg.ctl = ctl;
  1104. hw_cfg.len = size;
  1105. hw_cfg.payload = igc;
  1106. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1107. }
  1108. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1109. psde->pipe_hw->ops.setup_dma_igc) {
  1110. igc = msm_property_get_blob(&psde->property_info,
  1111. &pstate->property_state,
  1112. &size,
  1113. PLANE_PROP_DMA_IGC);
  1114. hw_cfg.last_feature = 0;
  1115. hw_cfg.ctl = ctl;
  1116. hw_cfg.len = size;
  1117. hw_cfg.payload = igc;
  1118. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1119. pstate->multirect_index);
  1120. }
  1121. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1122. psde->pipe_hw->ops.setup_dma_gc) {
  1123. gc = msm_property_get_blob(&psde->property_info,
  1124. &pstate->property_state,
  1125. &size,
  1126. PLANE_PROP_DMA_GC);
  1127. hw_cfg.last_feature = 0;
  1128. hw_cfg.ctl = ctl;
  1129. hw_cfg.len = size;
  1130. hw_cfg.payload = gc;
  1131. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1132. pstate->multirect_index);
  1133. }
  1134. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1135. psde->pipe_hw->ops.setup_fp16_igc) {
  1136. fp16_igc = !!sde_plane_get_property(pstate,
  1137. PLANE_PROP_FP16_IGC);
  1138. hw_cfg.last_feature = 0;
  1139. hw_cfg.ctl = ctl;
  1140. hw_cfg.len = sizeof(bool);
  1141. hw_cfg.payload = &fp16_igc;
  1142. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1143. pstate->multirect_index, &hw_cfg);
  1144. }
  1145. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1146. psde->pipe_hw->ops.setup_fp16_gc) {
  1147. fp16_gc = msm_property_get_blob(&psde->property_info,
  1148. &pstate->property_state,
  1149. &size,
  1150. PLANE_PROP_FP16_GC);
  1151. hw_cfg.last_feature = 0;
  1152. hw_cfg.ctl = ctl;
  1153. hw_cfg.len = size;
  1154. hw_cfg.payload = fp16_gc;
  1155. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1156. pstate->multirect_index, &hw_cfg);
  1157. }
  1158. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1159. psde->pipe_hw->ops.setup_fp16_csc) {
  1160. fp16_csc = msm_property_get_blob(&psde->property_info,
  1161. &pstate->property_state,
  1162. &size,
  1163. PLANE_PROP_FP16_CSC);
  1164. hw_cfg.last_feature = 0;
  1165. hw_cfg.ctl = ctl;
  1166. hw_cfg.len = size;
  1167. hw_cfg.payload = fp16_csc;
  1168. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1169. pstate->multirect_index, &hw_cfg);
  1170. }
  1171. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1172. psde->pipe_hw->ops.setup_fp16_unmult) {
  1173. fp16_unmult = !!sde_plane_get_property(pstate,
  1174. PLANE_PROP_FP16_UNMULT);
  1175. hw_cfg.last_feature = 0;
  1176. hw_cfg.ctl = ctl;
  1177. hw_cfg.len = sizeof(bool);
  1178. hw_cfg.payload = &fp16_unmult;
  1179. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1180. pstate->multirect_index, &hw_cfg);
  1181. }
  1182. }
  1183. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1184. struct sde_plane_state *pstate,
  1185. const struct sde_format *fmt, bool color_fill)
  1186. {
  1187. struct sde_hw_pixel_ext *pe;
  1188. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1189. const struct drm_format_info *info = NULL;
  1190. if (!psde || !fmt || !pstate) {
  1191. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1192. !psde, !fmt, !pstate);
  1193. return;
  1194. }
  1195. memcpy(&psde->scaler3_cfg, &pstate->scaler3_cfg,
  1196. sizeof(psde->scaler3_cfg));
  1197. memcpy(&psde->pixel_ext, &pstate->pixel_ext,
  1198. sizeof(psde->pixel_ext));
  1199. info = drm_format_info(fmt->base.pixel_format);
  1200. pe = &psde->pixel_ext;
  1201. psde->pipe_cfg.horz_decimation =
  1202. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1203. psde->pipe_cfg.vert_decimation =
  1204. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1205. /* don't chroma subsample if decimating */
  1206. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1207. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1208. /* update scaler */
  1209. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1210. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1211. int rc = -EINVAL;
  1212. if (!color_fill && !psde->debugfs_default_scale)
  1213. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1214. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1215. _sde_plane_setup_scaler3_lut(psde, pstate);
  1216. if (rc || pstate->scaler_check_state !=
  1217. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1218. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1219. pstate->scaler_check_state,
  1220. psde->debugfs_default_scale, rc,
  1221. psde->pipe_cfg.src_rect.w,
  1222. psde->pipe_cfg.src_rect.h,
  1223. psde->pipe_cfg.dst_rect.w,
  1224. psde->pipe_cfg.dst_rect.h,
  1225. pstate->multirect_mode);
  1226. /* calculate default config for QSEED3 */
  1227. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1228. chroma_subsmpl_h, chroma_subsmpl_v);
  1229. }
  1230. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1231. color_fill || psde->debugfs_default_scale) {
  1232. uint32_t deci_dim, i;
  1233. /* calculate default configuration for QSEED2 */
  1234. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1235. SDE_DEBUG_PLANE(psde, "default config\n");
  1236. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1237. psde->pipe_cfg.horz_decimation);
  1238. _sde_plane_setup_scaler2(psde,
  1239. deci_dim,
  1240. psde->pipe_cfg.dst_rect.w,
  1241. pe->phase_step_x,
  1242. pe->horz_filter, fmt, chroma_subsmpl_h);
  1243. if (SDE_FORMAT_IS_YUV(fmt))
  1244. deci_dim &= ~0x1;
  1245. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1246. psde->pipe_cfg.dst_rect.w, deci_dim,
  1247. pe->phase_step_x,
  1248. pe->roi_w,
  1249. pe->num_ext_pxls_left,
  1250. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1251. chroma_subsmpl_h, 0);
  1252. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1253. psde->pipe_cfg.vert_decimation);
  1254. _sde_plane_setup_scaler2(psde,
  1255. deci_dim,
  1256. psde->pipe_cfg.dst_rect.h,
  1257. pe->phase_step_y,
  1258. pe->vert_filter, fmt, chroma_subsmpl_v);
  1259. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1260. psde->pipe_cfg.dst_rect.h, deci_dim,
  1261. pe->phase_step_y,
  1262. pe->roi_h,
  1263. pe->num_ext_pxls_top,
  1264. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1265. chroma_subsmpl_v, 1);
  1266. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1267. if (pe->num_ext_pxls_left[i] >= 0)
  1268. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1269. else
  1270. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1271. if (pe->num_ext_pxls_right[i] >= 0)
  1272. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1273. else
  1274. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1275. if (pe->num_ext_pxls_top[i] >= 0)
  1276. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1277. else
  1278. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1279. if (pe->num_ext_pxls_btm[i] >= 0)
  1280. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1281. else
  1282. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1283. }
  1284. }
  1285. if (psde->pipe_hw->ops.setup_pre_downscale)
  1286. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1287. &pstate->pre_down);
  1288. }
  1289. /**
  1290. * _sde_plane_color_fill - enables color fill on plane
  1291. * @psde: Pointer to SDE plane object
  1292. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1293. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1294. * Returns: 0 on success
  1295. */
  1296. static int _sde_plane_color_fill(struct sde_plane *psde,
  1297. uint32_t color, uint32_t alpha)
  1298. {
  1299. const struct sde_format *fmt;
  1300. const struct drm_plane *plane;
  1301. struct sde_plane_state *pstate;
  1302. bool blend_enable = true;
  1303. if (!psde || !psde->base.state) {
  1304. SDE_ERROR("invalid plane\n");
  1305. return -EINVAL;
  1306. }
  1307. if (!psde->pipe_hw) {
  1308. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1309. return -EINVAL;
  1310. }
  1311. plane = &psde->base;
  1312. pstate = to_sde_plane_state(plane->state);
  1313. SDE_DEBUG_PLANE(psde, "\n");
  1314. /*
  1315. * select fill format to match user property expectation,
  1316. * h/w only supports RGB variants
  1317. */
  1318. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1319. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1320. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1321. /* update sspp */
  1322. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1323. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1324. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1325. pstate->multirect_index);
  1326. /* override scaler/decimation if solid fill */
  1327. psde->pipe_cfg.src_rect.x = 0;
  1328. psde->pipe_cfg.src_rect.y = 0;
  1329. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1330. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1331. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1332. if (psde->pipe_hw->ops.setup_format)
  1333. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1334. fmt, blend_enable,
  1335. SDE_SSPP_SOLID_FILL,
  1336. pstate->multirect_index);
  1337. if (psde->pipe_hw->ops.setup_rects)
  1338. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1339. &psde->pipe_cfg,
  1340. pstate->multirect_index);
  1341. if (psde->pipe_hw->ops.setup_pe)
  1342. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1343. &psde->pixel_ext);
  1344. if (psde->pipe_hw->ops.setup_scaler &&
  1345. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1346. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1347. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1348. &psde->pipe_cfg, &psde->pixel_ext,
  1349. &psde->scaler3_cfg);
  1350. }
  1351. }
  1352. return 0;
  1353. }
  1354. /**
  1355. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1356. * @plane: Pointer to drm plane
  1357. * @state: Pointer to drm plane state to be validated
  1358. * return: 0 if success; error code otherwise
  1359. */
  1360. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1361. struct drm_plane_state *state)
  1362. {
  1363. struct sde_plane *psde;
  1364. struct sde_plane_state *pstate, *old_pstate;
  1365. int ret = 0;
  1366. u32 rotation;
  1367. if (!plane || !state) {
  1368. SDE_ERROR("invalid plane/state\n");
  1369. return -EINVAL;
  1370. }
  1371. psde = to_sde_plane(plane);
  1372. pstate = to_sde_plane_state(state);
  1373. old_pstate = to_sde_plane_state(plane->state);
  1374. /* check inline rotation and simplify the transform */
  1375. rotation = drm_rotation_simplify(
  1376. state->rotation,
  1377. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1378. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1379. if ((rotation & DRM_MODE_ROTATE_180) ||
  1380. (rotation & DRM_MODE_ROTATE_270)) {
  1381. SDE_ERROR_PLANE(psde,
  1382. "invalid rotation transform must be simplified 0x%x\n",
  1383. rotation);
  1384. ret = -EINVAL;
  1385. goto exit;
  1386. }
  1387. if (rotation & DRM_MODE_ROTATE_90) {
  1388. struct msm_drm_private *priv = plane->dev->dev_private;
  1389. struct sde_kms *sde_kms;
  1390. const struct msm_format *msm_fmt;
  1391. const struct sde_format *fmt;
  1392. struct sde_rect src;
  1393. bool q16_data = true;
  1394. POPULATE_RECT(&src, state->src_x, state->src_y,
  1395. state->src_w, state->src_h, q16_data);
  1396. /*
  1397. * DRM framework expects rotation flag in counter-clockwise
  1398. * direction and the HW expects in clockwise direction.
  1399. * Flip the flags to match with HW.
  1400. */
  1401. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1402. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1403. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1404. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1405. !psde->pipe_sblk->in_rot_maxheight ||
  1406. !psde->pipe_sblk->in_rot_format_list ||
  1407. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1408. SDE_ERROR_PLANE(psde,
  1409. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1410. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1411. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1412. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1413. !psde->pipe_sblk->in_rot_format_list,
  1414. !psde->pipe_sblk->in_rot_maxheight,
  1415. psde->features);
  1416. ret = -EINVAL;
  1417. goto exit;
  1418. }
  1419. /* check for valid height */
  1420. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1421. SDE_ERROR_PLANE(psde,
  1422. "invalid height for inline rot:%d max:%d\n",
  1423. src.h, psde->pipe_sblk->in_rot_maxheight);
  1424. ret = -EINVAL;
  1425. goto exit;
  1426. }
  1427. if (!sde_plane_enabled(state))
  1428. goto exit;
  1429. /* check for valid formats supported by inline rot */
  1430. sde_kms = to_sde_kms(priv->kms);
  1431. msm_fmt = msm_framebuffer_format(state->fb);
  1432. fmt = to_sde_format(msm_fmt);
  1433. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1434. psde->pipe_sblk->in_rot_format_list);
  1435. }
  1436. exit:
  1437. pstate->rotation = rotation;
  1438. return ret;
  1439. }
  1440. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1441. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1442. {
  1443. struct sde_plane *psde;
  1444. struct msm_drm_private *priv;
  1445. struct sde_vbif_set_xin_halt_params halt_params;
  1446. if (!plane || !plane->dev) {
  1447. SDE_ERROR("invalid arguments\n");
  1448. return false;
  1449. }
  1450. psde = to_sde_plane(plane);
  1451. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1452. SDE_ERROR("invalid pipe reference\n");
  1453. return false;
  1454. }
  1455. priv = plane->dev->dev_private;
  1456. if (!priv || !priv->kms) {
  1457. SDE_ERROR("invalid KMS reference\n");
  1458. return false;
  1459. }
  1460. memset(&halt_params, 0, sizeof(halt_params));
  1461. halt_params.vbif_idx = VBIF_RT;
  1462. halt_params.xin_id = xin_id;
  1463. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1464. halt_params.forced_on = halt_forced_clk;
  1465. halt_params.enable = enable;
  1466. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1467. }
  1468. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1469. {
  1470. struct sde_plane *psde;
  1471. if (!plane) {
  1472. SDE_ERROR("invalid plane\n");
  1473. return;
  1474. }
  1475. psde = to_sde_plane(plane);
  1476. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1477. SDE_ERROR("invalid pipe reference\n");
  1478. return;
  1479. }
  1480. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1481. psde->xin_halt_forced_clk =
  1482. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1483. psde->xin_halt_forced_clk, enable);
  1484. }
  1485. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1486. struct drm_crtc *crtc)
  1487. {
  1488. struct sde_plane *psde;
  1489. if (!plane || !crtc) {
  1490. SDE_ERROR("invalid plane/crtc\n");
  1491. return;
  1492. }
  1493. psde = to_sde_plane(plane);
  1494. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1495. return;
  1496. /* do all VBIF programming for the sec-ui allowed SSPP */
  1497. _sde_plane_set_qos_remap(plane);
  1498. _sde_plane_set_ot_limit(plane, crtc);
  1499. }
  1500. /**
  1501. * sde_plane_rot_install_properties - install plane rotator properties
  1502. * @plane: Pointer to drm plane
  1503. * @catalog: Pointer to mdss configuration
  1504. * return: none
  1505. */
  1506. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1507. struct sde_mdss_cfg *catalog)
  1508. {
  1509. struct sde_plane *psde = to_sde_plane(plane);
  1510. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1511. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1512. int ret = 0;
  1513. if (!plane || !psde) {
  1514. SDE_ERROR("invalid plane\n");
  1515. return;
  1516. } else if (!catalog) {
  1517. SDE_ERROR("invalid catalog\n");
  1518. return;
  1519. }
  1520. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1521. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1522. ret = drm_plane_create_rotation_property(plane,
  1523. DRM_MODE_ROTATE_0, supported_rotations);
  1524. if (ret) {
  1525. DRM_ERROR("create rotation property failed: %d\n", ret);
  1526. return;
  1527. }
  1528. }
  1529. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1530. {
  1531. struct sde_plane_state *pstate;
  1532. if (!drm_state)
  1533. return;
  1534. pstate = to_sde_plane_state(drm_state);
  1535. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1536. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1537. }
  1538. /**
  1539. * multi_rect validate API allows to validate only R0 and R1 RECT
  1540. * passing for each plane. Client of this API must not pass multiple
  1541. * plane which are not sharing same XIN client. Such calls will fail
  1542. * even though kernel client is passing valid multirect configuration.
  1543. */
  1544. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1545. {
  1546. struct sde_plane_state *pstate[R_MAX];
  1547. const struct drm_plane_state *drm_state[R_MAX];
  1548. struct sde_rect src[R_MAX], dst[R_MAX];
  1549. struct sde_plane *sde_plane[R_MAX];
  1550. const struct sde_format *fmt[R_MAX];
  1551. int xin_id[R_MAX];
  1552. bool q16_data = true;
  1553. int i, j, buffer_lines, width_threshold[R_MAX];
  1554. unsigned int max_tile_height = 1;
  1555. bool parallel_fetch_qualified = true;
  1556. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1557. const struct msm_format *msm_fmt;
  1558. bool const_alpha_enable = true;
  1559. for (i = 0; i < R_MAX; i++) {
  1560. drm_state[i] = i ? plane->r1 : plane->r0;
  1561. if (!drm_state[i]) {
  1562. SDE_ERROR("drm plane state is NULL\n");
  1563. return -EINVAL;
  1564. }
  1565. pstate[i] = to_sde_plane_state(drm_state[i]);
  1566. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1567. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1568. for (j = 0; j < i; j++) {
  1569. if (xin_id[i] != xin_id[j]) {
  1570. SDE_ERROR_PLANE(sde_plane[i],
  1571. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1572. j, xin_id[j], i, xin_id[i]);
  1573. return -EINVAL;
  1574. }
  1575. }
  1576. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1577. if (!msm_fmt) {
  1578. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1579. return -EINVAL;
  1580. }
  1581. fmt[i] = to_sde_format(msm_fmt);
  1582. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1583. (fmt[i]->tile_height > max_tile_height))
  1584. max_tile_height = fmt[i]->tile_height;
  1585. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1586. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1587. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1588. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1589. drm_state[i]->crtc_h, !q16_data);
  1590. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1591. SDE_ERROR_PLANE(sde_plane[i],
  1592. "scaling is not supported in multirect mode\n");
  1593. return -EINVAL;
  1594. }
  1595. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1596. SDE_ERROR_PLANE(sde_plane[i],
  1597. "inline rotation is not supported in mulirect mode\n");
  1598. return -EINVAL;
  1599. }
  1600. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1601. SDE_ERROR_PLANE(sde_plane[i],
  1602. "Unsupported format for multirect mode\n");
  1603. return -EINVAL;
  1604. }
  1605. /**
  1606. * SSPP PD_MEM is split half - one for each RECT.
  1607. * Tiled formats need 5 lines of buffering while fetching
  1608. * whereas linear formats need only 2 lines.
  1609. * So we cannot support more than half of the supported SSPP
  1610. * width for tiled formats.
  1611. */
  1612. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1613. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1614. width_threshold[i] /= 2;
  1615. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1616. parallel_fetch_qualified = false;
  1617. if (sde_plane[i]->is_virtual)
  1618. mode = sde_plane_get_property(pstate[i],
  1619. PLANE_PROP_MULTIRECT_MODE);
  1620. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1621. const_alpha_enable = false;
  1622. }
  1623. buffer_lines = 2 * max_tile_height;
  1624. /**
  1625. * fallback to driver mode selection logic if client is using
  1626. * multirect plane without setting property.
  1627. *
  1628. * validate multirect mode configuration based on rectangle
  1629. */
  1630. switch (mode) {
  1631. case SDE_SSPP_MULTIRECT_NONE:
  1632. if (parallel_fetch_qualified)
  1633. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1634. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1635. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1636. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1637. else
  1638. SDE_ERROR(
  1639. "planes(%d - %d) multirect mode selection fail\n",
  1640. drm_state[R0]->plane->base.id,
  1641. drm_state[R1]->plane->base.id);
  1642. break;
  1643. case SDE_SSPP_MULTIRECT_PARALLEL:
  1644. if (!parallel_fetch_qualified) {
  1645. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1646. drm_state[R0]->plane->base.id,
  1647. width_threshold[R0], src[R0].w);
  1648. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1649. drm_state[R1]->plane->base.id,
  1650. width_threshold[R1], src[R1].w);
  1651. SDE_ERROR("parallel fetch not qualified\n");
  1652. mode = SDE_SSPP_MULTIRECT_NONE;
  1653. }
  1654. break;
  1655. case SDE_SSPP_MULTIRECT_TIME_MX:
  1656. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1657. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1658. SDE_ERROR(
  1659. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1660. buffer_lines, drm_state[R0]->plane->base.id,
  1661. dst[R0].y, dst[R0].h);
  1662. SDE_ERROR(
  1663. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1664. buffer_lines, drm_state[R1]->plane->base.id,
  1665. dst[R1].y, dst[R1].h);
  1666. SDE_ERROR("time multiplexed fetch not qualified\n");
  1667. mode = SDE_SSPP_MULTIRECT_NONE;
  1668. }
  1669. break;
  1670. default:
  1671. SDE_ERROR("bad mode:%d selection\n", mode);
  1672. mode = SDE_SSPP_MULTIRECT_NONE;
  1673. break;
  1674. }
  1675. for (i = 0; i < R_MAX; i++) {
  1676. pstate[i]->multirect_mode = mode;
  1677. pstate[i]->const_alpha_en = const_alpha_enable;
  1678. }
  1679. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1680. return -EINVAL;
  1681. if (sde_plane[R0]->is_virtual) {
  1682. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1683. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1684. } else {
  1685. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1686. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1687. }
  1688. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1689. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1690. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1691. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1692. return 0;
  1693. }
  1694. /**
  1695. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1696. * @plane: Pointer to drm plane structure
  1697. * @ctl: Pointer to hardware control driver
  1698. * @set: set if true else clear
  1699. */
  1700. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1701. bool set)
  1702. {
  1703. if (!plane || !ctl) {
  1704. SDE_ERROR("invalid parameters\n");
  1705. return;
  1706. }
  1707. if (!ctl->ops.update_bitmask_sspp) {
  1708. SDE_ERROR("invalid ops\n");
  1709. return;
  1710. }
  1711. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1712. }
  1713. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1714. struct drm_plane_state *new_state)
  1715. {
  1716. struct drm_framebuffer *fb = new_state->fb;
  1717. struct sde_plane *psde = to_sde_plane(plane);
  1718. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1719. struct sde_hw_fmt_layout layout;
  1720. struct msm_gem_address_space *aspace;
  1721. int ret;
  1722. if (!fb)
  1723. return 0;
  1724. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1725. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1726. if (ret) {
  1727. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1728. return ret;
  1729. }
  1730. /* cache aspace */
  1731. pstate->aspace = aspace;
  1732. /*
  1733. * when transitioning from secure to non-secure,
  1734. * plane->prepare_fb happens before the commit. In such case,
  1735. * defer the prepare_fb and handled it late, during the commit
  1736. * after attaching the domains as part of the transition
  1737. */
  1738. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1739. true : false;
  1740. if (pstate->defer_prepare_fb) {
  1741. SDE_EVT32(DRMID(plane), psde->pipe);
  1742. SDE_DEBUG_PLANE(psde,
  1743. "domain not attached, prepare_fb handled later\n");
  1744. return 0;
  1745. }
  1746. if (pstate->aspace && fb) {
  1747. ret = msm_framebuffer_prepare(fb,
  1748. pstate->aspace);
  1749. if (ret) {
  1750. SDE_ERROR("failed to prepare framebuffer fb:%d plane:%d pipe:%d ret:%d\n",
  1751. fb->base.id, plane->base.id, psde->pipe, ret);
  1752. SDE_EVT32(fb->base.id, plane->base.id, psde->pipe, ret, SDE_EVTLOG_ERROR);
  1753. return ret;
  1754. }
  1755. }
  1756. /* validate framebuffer layout before commit */
  1757. ret = sde_format_populate_layout(pstate->aspace,
  1758. fb, &layout);
  1759. if (ret) {
  1760. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1761. return ret;
  1762. }
  1763. return 0;
  1764. }
  1765. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1766. struct drm_plane_state *old_state)
  1767. {
  1768. struct sde_plane *psde = to_sde_plane(plane);
  1769. struct sde_plane_state *old_pstate;
  1770. if (!old_state || !old_state->fb || !plane)
  1771. return;
  1772. old_pstate = to_sde_plane_state(old_state);
  1773. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1774. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1775. }
  1776. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1777. struct drm_plane_state *state,
  1778. struct drm_plane_state *old_state)
  1779. {
  1780. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1781. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1782. struct drm_framebuffer *fb, *old_fb;
  1783. /* no need to check it again */
  1784. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1785. return;
  1786. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1787. || psde->is_error) {
  1788. SDE_DEBUG_PLANE(psde,
  1789. "enabling/disabling full modeset required\n");
  1790. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1791. } else if (to_sde_plane_state(old_state)->pending) {
  1792. SDE_DEBUG_PLANE(psde, "still pending\n");
  1793. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1794. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1795. pstate->multirect_mode != old_pstate->multirect_mode) {
  1796. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1797. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1798. } else if (state->src_w != old_state->src_w ||
  1799. state->src_h != old_state->src_h ||
  1800. state->src_x != old_state->src_x ||
  1801. state->src_y != old_state->src_y) {
  1802. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1803. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1804. } else if (state->crtc_w != old_state->crtc_w ||
  1805. state->crtc_h != old_state->crtc_h ||
  1806. state->crtc_x != old_state->crtc_x ||
  1807. state->crtc_y != old_state->crtc_y) {
  1808. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1809. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1810. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1811. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1812. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1813. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1814. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1815. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1816. } else if (pstate->rotation != old_pstate->rotation) {
  1817. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1818. pstate->rotation, old_pstate->rotation);
  1819. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1820. }
  1821. fb = state->fb;
  1822. old_fb = old_state->fb;
  1823. if (!fb || !old_fb) {
  1824. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1825. } else if ((fb->format->format != old_fb->format->format) ||
  1826. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1827. SDE_DEBUG_PLANE(psde, "format change\n");
  1828. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1829. } else {
  1830. uint64_t new_mod = fb->modifier;
  1831. uint64_t old_mod = old_fb->modifier;
  1832. uint32_t *new_pitches = fb->pitches;
  1833. uint32_t *old_pitches = old_fb->pitches;
  1834. uint32_t *new_offset = fb->offsets;
  1835. uint32_t *old_offset = old_fb->offsets;
  1836. int i;
  1837. if (new_mod != old_mod) {
  1838. SDE_DEBUG_PLANE(psde,
  1839. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1840. new_mod, old_mod);
  1841. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1842. SDE_PLANE_DIRTY_RECTS;
  1843. }
  1844. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1845. if (new_pitches[i] != old_pitches[i]) {
  1846. SDE_DEBUG_PLANE(psde,
  1847. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1848. i, old_pitches[i], new_pitches[i]);
  1849. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1850. break;
  1851. }
  1852. }
  1853. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1854. if (new_offset[i] != old_offset[i]) {
  1855. SDE_DEBUG_PLANE(psde,
  1856. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1857. i, old_offset[i], new_offset[i]);
  1858. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1859. SDE_PLANE_DIRTY_RECTS;
  1860. break;
  1861. }
  1862. }
  1863. }
  1864. }
  1865. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1866. unsigned long base_addr, u32 size)
  1867. {
  1868. int ret = -EINVAL;
  1869. u32 addr;
  1870. struct sde_plane *psde = to_sde_plane(plane);
  1871. if (!psde || !base_addr || !size) {
  1872. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1873. return ret;
  1874. }
  1875. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1876. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1877. is_sde_plane_virtual(plane));
  1878. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1879. ret = 0;
  1880. }
  1881. return ret;
  1882. }
  1883. static inline bool _sde_plane_is_pre_downscale_enabled(
  1884. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1885. {
  1886. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1887. }
  1888. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1889. struct sde_plane_state *pstate,
  1890. const struct sde_format *fmt,
  1891. uint32_t img_w, uint32_t img_h,
  1892. uint32_t src_w, uint32_t src_h,
  1893. uint32_t deci_w, uint32_t deci_h)
  1894. {
  1895. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1896. bool pre_down_en;
  1897. int i;
  1898. if (!psde || !pstate || !fmt) {
  1899. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1900. return -EINVAL;
  1901. }
  1902. if (psde->debugfs_default_scale ||
  1903. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1904. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1905. return 0;
  1906. pd_cfg = &pstate->pre_down;
  1907. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1908. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1909. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1910. uint32_t hor_req_pixels, hor_fetch_pixels;
  1911. uint32_t vert_req_pixels, vert_fetch_pixels;
  1912. uint32_t src_w_tmp, src_h_tmp;
  1913. uint32_t scaler_w, scaler_h;
  1914. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1915. bool rot;
  1916. /* re-use color plane 1's config for plane 2 */
  1917. if (i == 2)
  1918. continue;
  1919. if (pre_down_en) {
  1920. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1921. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1922. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1923. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1924. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1925. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1926. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1927. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1928. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1929. i, pre_down_ratio_x, pre_down_ratio_y);
  1930. }
  1931. src_w_tmp = src_w;
  1932. src_h_tmp = src_h;
  1933. /*
  1934. * For chroma plane, width is half for the following sub sampled
  1935. * formats. Except in case of decimation, where hardware avoids
  1936. * 1 line of decimation instead of downsampling.
  1937. */
  1938. if (i == 1) {
  1939. if (!deci_w &&
  1940. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1941. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1942. src_w_tmp >>= 1;
  1943. if (!deci_h &&
  1944. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1945. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1946. src_h_tmp >>= 1;
  1947. }
  1948. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1949. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1950. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1951. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1952. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1953. deci_w);
  1954. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1955. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1956. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1957. deci_h);
  1958. if ((hor_req_pixels != hor_fetch_pixels) ||
  1959. (hor_fetch_pixels > img_w) ||
  1960. (vert_req_pixels != vert_fetch_pixels) ||
  1961. (vert_fetch_pixels > img_h)) {
  1962. SDE_ERROR_PLANE(psde,
  1963. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1964. hor_req_pixels, vert_req_pixels,
  1965. hor_fetch_pixels, vert_fetch_pixels,
  1966. img_w, img_h);
  1967. return -EINVAL;
  1968. }
  1969. /*
  1970. * swap the scaler src width & height for inline-rotation 90
  1971. * comparison with Pixel-Extension, as PE is based on
  1972. * pre-rotation and QSEED is based on post-rotation
  1973. */
  1974. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1975. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1976. : pstate->scaler3_cfg.src_width[i];
  1977. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1978. : pstate->scaler3_cfg.src_height[i];
  1979. /*
  1980. * Alpha plane can only be scaled using bilinear or pixel
  1981. * repeat/drop, src_width and src_height are only specified
  1982. * for Y and UV plane
  1983. */
  1984. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1985. vert_req_pixels / pre_down_ratio_y !=
  1986. scaler_h)) {
  1987. SDE_ERROR_PLANE(psde,
  1988. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1989. i, pstate->pixel_ext.roi_w[i],
  1990. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1991. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1992. return -EINVAL;
  1993. }
  1994. /*
  1995. * SSPP fetch , unpack output and QSEED3 input lines need
  1996. * to match for Y plane
  1997. */
  1998. if (i == 0 &&
  1999. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2000. BIT(SDE_DRM_DEINTERLACE)) &&
  2001. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  2002. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  2003. SDE_ERROR_PLANE(psde,
  2004. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  2005. i, pstate->pixel_ext.roi_w[i],
  2006. pstate->pixel_ext.roi_h[i],
  2007. pstate->scaler3_cfg.src_width[i],
  2008. pstate->scaler3_cfg.src_height[i],
  2009. src_w, src_h);
  2010. return -EINVAL;
  2011. }
  2012. }
  2013. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  2014. return 0;
  2015. }
  2016. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  2017. {
  2018. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  2019. }
  2020. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  2021. struct sde_plane_state *pstate, struct sde_rect *dst,
  2022. u32 src_w, u32 src_h)
  2023. {
  2024. int ret = 0;
  2025. u32 min_ratio_numer, min_ratio_denom;
  2026. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  2027. bool pd_x;
  2028. bool pd_y;
  2029. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  2030. return ret;
  2031. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  2032. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  2033. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  2034. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2035. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  2036. SDE_ERROR_PLANE(psde,
  2037. "hw does not support pre-downscale X: 0x%x\n",
  2038. psde->features);
  2039. ret = -EINVAL;
  2040. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2041. SDE_ERROR_PLANE(psde,
  2042. "hw does not support pre-downscale Y: 0x%x\n",
  2043. psde->features);
  2044. ret = -EINVAL;
  2045. } else if (!min_ratio_numer || !min_ratio_denom) {
  2046. SDE_ERROR_PLANE(psde,
  2047. "min downscale ratio not set! %u / %u\n",
  2048. min_ratio_numer, min_ratio_denom);
  2049. ret = -EINVAL;
  2050. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2051. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2052. min_ratio_denom))) {
  2053. SDE_ERROR_PLANE(psde,
  2054. "failed min downscale-x check %u->%u, %u/%u\n",
  2055. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2056. ret = -EINVAL;
  2057. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2058. min_ratio_denom))) {
  2059. SDE_ERROR_PLANE(psde,
  2060. "failed min downscale-y check %u->%u, %u/%u\n",
  2061. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2062. ret = -EINVAL;
  2063. }
  2064. return ret;
  2065. }
  2066. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2067. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2068. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2069. u32 *max_numer_h, u32 *max_denom_h)
  2070. {
  2071. bool rotated, has_predown, default_scale;
  2072. const struct sde_sspp_sub_blks *sblk;
  2073. struct sde_hw_inline_pre_downscale_cfg *pd = NULL;
  2074. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2075. sblk = psde->pipe_sblk;
  2076. *max_numer_w = sblk->maxdwnscale;
  2077. *max_denom_w = 1;
  2078. *max_numer_h = sblk->maxdwnscale;
  2079. *max_denom_h = 1;
  2080. has_predown = _sde_plane_has_pre_downscale(psde);
  2081. if (has_predown)
  2082. pd = &pstate->pre_down;
  2083. default_scale = psde->debugfs_default_scale ||
  2084. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2085. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2086. /**
  2087. * Inline rotation has different max vertical downscaling limits since
  2088. * the source-width becomes the scaler's pre-downscaled source-height.
  2089. **/
  2090. if (rotated) {
  2091. if (pd != NULL && rt_client && has_predown) {
  2092. if (default_scale)
  2093. pd->pre_downscale_x_0 = (src_h >
  2094. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2095. *max_numer_h = pd->pre_downscale_x_0 ?
  2096. sblk->in_rot_maxdwnscale_rt_num :
  2097. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2098. *max_denom_h = pd->pre_downscale_x_0 ?
  2099. sblk->in_rot_maxdwnscale_rt_denom :
  2100. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2101. } else if (rt_client) {
  2102. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2103. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2104. } else {
  2105. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2106. }
  2107. }
  2108. }
  2109. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2110. struct sde_plane *psde, const struct sde_format *fmt,
  2111. struct sde_plane_state *pstate, struct sde_rect *src,
  2112. struct sde_rect *dst, u32 width, u32 height)
  2113. {
  2114. int ret = 0;
  2115. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2116. uint32_t scaler_src_w, scaler_src_h;
  2117. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2118. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2119. uint32_t max_upscale, max_linewidth;
  2120. bool inline_rotation, rt_client;
  2121. struct drm_crtc *crtc;
  2122. struct drm_crtc_state *new_cstate;
  2123. const struct sde_sspp_sub_blks *sblk;
  2124. if (!state || !state->state || !state->crtc) {
  2125. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2126. return -EINVAL;
  2127. }
  2128. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2129. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2130. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2131. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2132. /* with inline rotator, the source of the scaler is post-rotated */
  2133. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2134. if (inline_rotation) {
  2135. scaler_src_w = src_deci_h;
  2136. scaler_src_h = src_deci_w;
  2137. } else {
  2138. scaler_src_w = src_deci_w;
  2139. scaler_src_h = src_deci_h;
  2140. }
  2141. sblk = psde->pipe_sblk;
  2142. max_upscale = sblk->maxupscale;
  2143. if (inline_rotation)
  2144. max_linewidth = sblk->in_rot_maxheight;
  2145. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2146. max_linewidth = sblk->scaling_linewidth;
  2147. else
  2148. max_linewidth = sblk->maxlinewidth;
  2149. crtc = state->crtc;
  2150. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2151. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2152. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2153. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2154. &max_downscale_num_h, &max_downscale_denom_h);
  2155. /* decimation validation */
  2156. if ((deci_w || deci_h)
  2157. && ((deci_w > sblk->maxhdeciexp)
  2158. || (deci_h > sblk->maxvdeciexp))) {
  2159. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2160. ret = -EINVAL;
  2161. } else if ((deci_w || deci_h)
  2162. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2163. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2164. ret = -EINVAL;
  2165. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2166. ((src->w != dst->w) || (src->h != dst->h))) {
  2167. SDE_ERROR_PLANE(psde,
  2168. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2169. src->w, src->h, dst->w, dst->h);
  2170. ret = -EINVAL;
  2171. /* check scaler source width */
  2172. } else if (scaler_src_w > max_linewidth) {
  2173. SDE_ERROR_PLANE(psde,
  2174. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2175. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2176. ret = -E2BIG;
  2177. /* check max scaler capability */
  2178. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2179. ((scaler_src_h * max_upscale) < dst->h) ||
  2180. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2181. < scaler_src_w) ||
  2182. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2183. < scaler_src_h)) {
  2184. SDE_ERROR_PLANE(psde,
  2185. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2186. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2187. inline_rotation, max_downscale_num_w,
  2188. max_downscale_denom_w, max_downscale_num_h,
  2189. max_downscale_denom_h);
  2190. ret = -E2BIG;
  2191. /* check inline pre-downscale support */
  2192. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2193. pstate, dst, src_deci_w, src_deci_h)) {
  2194. ret = -EINVAL;
  2195. /* QSEED validation */
  2196. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2197. width, height, src->w, src->h,
  2198. deci_w, deci_h)) {
  2199. ret = -EINVAL;
  2200. }
  2201. return ret;
  2202. }
  2203. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2204. struct sde_plane_state *pstate, struct sde_rect *src,
  2205. const struct sde_format *fmt, int ret)
  2206. {
  2207. /* check excl rect configs */
  2208. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2209. struct sde_rect intersect;
  2210. /*
  2211. * Check exclusion rect against src rect.
  2212. * it must intersect with source rect.
  2213. */
  2214. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2215. if (intersect.w != pstate->excl_rect.w ||
  2216. intersect.h != pstate->excl_rect.h ||
  2217. SDE_FORMAT_IS_YUV(fmt)) {
  2218. SDE_ERROR_PLANE(psde,
  2219. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2220. pstate->excl_rect.x, pstate->excl_rect.y,
  2221. pstate->excl_rect.w, pstate->excl_rect.h,
  2222. src->x, src->y, src->w, src->h,
  2223. (char *)&fmt->base.pixel_format);
  2224. ret = -EINVAL;
  2225. }
  2226. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2227. pstate->excl_rect.x, pstate->excl_rect.y,
  2228. pstate->excl_rect.w, pstate->excl_rect.h);
  2229. }
  2230. return ret;
  2231. }
  2232. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2233. struct drm_plane_state *state)
  2234. {
  2235. struct sde_kms *sde_kms;
  2236. struct sde_splash_display *splash_display;
  2237. int i;
  2238. sde_kms = _sde_plane_get_kms(&psde->base);
  2239. if (!sde_kms || !state->crtc)
  2240. return 0;
  2241. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2242. splash_display = &sde_kms->splash_data.splash_display[i];
  2243. if (splash_display && splash_display->cont_splash_enabled &&
  2244. splash_display->encoder &&
  2245. state->crtc != splash_display->encoder->crtc) {
  2246. struct sde_sspp_index_info *pipe_info = &splash_display->pipe_info;
  2247. if (test_bit(psde->pipe, pipe_info->pipes) ||
  2248. test_bit(psde->pipe, pipe_info->virt_pipes)) {
  2249. SDE_ERROR_PLANE(psde, "pipe:%d used in cont-splash on crtc:%d\n",
  2250. psde->pipe,
  2251. splash_display->encoder->crtc->base.id);
  2252. return -EINVAL;
  2253. }
  2254. }
  2255. }
  2256. return 0;
  2257. }
  2258. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2259. const struct sde_format *fmt,
  2260. struct sde_rect src, struct sde_rect dst,
  2261. u32 width, u32 height)
  2262. {
  2263. int ret = 0;
  2264. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2265. if (SDE_FORMAT_IS_YUV(fmt) &&
  2266. (!(psde->features & SDE_SSPP_SCALER) ||
  2267. !(psde->features & (BIT(SDE_SSPP_CSC)
  2268. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2269. SDE_ERROR_PLANE(psde,
  2270. "plane doesn't have scaler/csc for yuv\n");
  2271. ret = -EINVAL;
  2272. /* check src bounds */
  2273. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2274. src.w < min_src_size || src.h < min_src_size ||
  2275. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2276. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2277. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2278. src.x, src.y, src.w, src.h);
  2279. ret = -E2BIG;
  2280. /* valid yuv image */
  2281. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2282. (src.w & 0x1) || (src.h & 0x1))) {
  2283. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2284. src.x, src.y, src.w, src.h);
  2285. ret = -EINVAL;
  2286. /* min dst support */
  2287. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2288. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2289. dst.x, dst.y, dst.w, dst.h);
  2290. ret = -EINVAL;
  2291. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2292. !psde->catalog->ubwc_rev) {
  2293. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2294. ret = -EINVAL;
  2295. }
  2296. return ret;
  2297. }
  2298. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2299. struct drm_plane_state *state)
  2300. {
  2301. int ret = 0;
  2302. struct sde_plane *psde;
  2303. struct sde_plane_state *pstate;
  2304. const struct msm_format *msm_fmt;
  2305. const struct sde_format *fmt;
  2306. struct sde_rect src, dst;
  2307. bool q16_data = true;
  2308. struct drm_framebuffer *fb;
  2309. u32 width;
  2310. u32 height;
  2311. psde = to_sde_plane(plane);
  2312. pstate = to_sde_plane_state(state);
  2313. if (!psde->pipe_sblk) {
  2314. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2315. return -EINVAL;
  2316. }
  2317. /* src values are in Q16 fixed point, convert to integer */
  2318. POPULATE_RECT(&src, state->src_x, state->src_y,
  2319. state->src_w, state->src_h, q16_data);
  2320. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2321. state->crtc_h, !q16_data);
  2322. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2323. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2324. if (!sde_plane_enabled(state))
  2325. goto modeset_update;
  2326. fb = state->fb;
  2327. width = fb ? state->fb->width : 0x0;
  2328. height = fb ? state->fb->height : 0x0;
  2329. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2330. plane->base.id,
  2331. pstate->rotation,
  2332. width, height,
  2333. fb ? (char *) &state->fb->format->format : 0x0,
  2334. fb ? state->fb->modifier : 0x0);
  2335. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2336. state->src_w >> 16, state->src_h >> 16,
  2337. state->src_x >> 16, state->src_y >> 16,
  2338. state->crtc_w, state->crtc_h,
  2339. state->crtc_x, state->crtc_y);
  2340. msm_fmt = msm_framebuffer_format(fb);
  2341. fmt = to_sde_format(msm_fmt);
  2342. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2343. height);
  2344. if (ret)
  2345. return ret;
  2346. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2347. &src, &dst, width, height);
  2348. if (ret)
  2349. return ret;
  2350. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2351. &src, fmt, ret);
  2352. if (ret)
  2353. return ret;
  2354. ret = _sde_plane_validate_shared_crtc(psde, state);
  2355. if (ret)
  2356. return ret;
  2357. pstate->const_alpha_en = fmt->alpha_enable &&
  2358. (SDE_DRM_BLEND_OP_OPAQUE !=
  2359. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2360. (pstate->stage != SDE_STAGE_0);
  2361. modeset_update:
  2362. if (!ret)
  2363. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2364. state, plane->state);
  2365. return ret;
  2366. }
  2367. static int _sde_plane_atomic_check(struct drm_plane *plane,
  2368. struct drm_plane_state *state)
  2369. {
  2370. int ret = 0;
  2371. struct sde_plane *psde;
  2372. struct sde_plane_state *pstate;
  2373. psde = to_sde_plane(plane);
  2374. pstate = to_sde_plane_state(state);
  2375. SDE_DEBUG_PLANE(psde, "\n");
  2376. ret = sde_plane_rot_atomic_check(plane, state);
  2377. if (ret)
  2378. goto exit;
  2379. ret = sde_plane_sspp_atomic_check(plane, state);
  2380. exit:
  2381. return ret;
  2382. }
  2383. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2384. static int sde_plane_atomic_check(struct drm_plane *plane,
  2385. struct drm_atomic_state *atomic_state)
  2386. {
  2387. struct drm_plane_state *state = NULL;
  2388. if (!plane || !atomic_state) {
  2389. SDE_ERROR("invalid arg(s), plane %d atomic_state %d\n",
  2390. !plane, !atomic_state);
  2391. return -EINVAL;
  2392. }
  2393. state = drm_atomic_get_new_plane_state(atomic_state, plane);
  2394. return _sde_plane_atomic_check(plane, state);
  2395. }
  2396. #else
  2397. static int sde_plane_atomic_check(struct drm_plane *plane,
  2398. struct drm_plane_state *state)
  2399. {
  2400. if (!plane || !state) {
  2401. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2402. !plane, !state);
  2403. return -EINVAL;
  2404. }
  2405. return _sde_plane_atomic_check(plane, state);
  2406. }
  2407. #endif
  2408. void sde_plane_flush(struct drm_plane *plane)
  2409. {
  2410. struct sde_plane *psde;
  2411. struct sde_plane_state *pstate;
  2412. if (!plane || !plane->state) {
  2413. SDE_ERROR("invalid plane\n");
  2414. return;
  2415. }
  2416. psde = to_sde_plane(plane);
  2417. pstate = to_sde_plane_state(plane->state);
  2418. /*
  2419. * These updates have to be done immediately before the plane flush
  2420. * timing, and may not be moved to the atomic_update/mode_set functions.
  2421. */
  2422. if (psde->is_error)
  2423. /* force white frame with 100% alpha pipe output on error */
  2424. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2425. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2426. /* force 100% alpha */
  2427. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2428. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2429. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2430. /* flag h/w flush complete */
  2431. if (plane->state)
  2432. pstate->pending = false;
  2433. }
  2434. /**
  2435. * sde_plane_set_error: enable/disable error condition
  2436. * @plane: pointer to drm_plane structure
  2437. */
  2438. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2439. {
  2440. struct sde_plane *psde;
  2441. if (!plane)
  2442. return;
  2443. psde = to_sde_plane(plane);
  2444. psde->is_error = error;
  2445. }
  2446. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2447. struct sde_plane_state *pstate)
  2448. {
  2449. struct drm_plane_state *state = psde->base.state;
  2450. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2451. struct sde_hw_pipe_sc_cfg *cfg = &pstate->sc_cfg;
  2452. bool prev_rd_en = cfg->rd_en;
  2453. u32 fb_cache_flag, fb_cache_type;
  2454. msm_framebuffer_get_cache_hint(state->fb, &fb_cache_flag, &fb_cache_type);
  2455. cfg->rd_en = false;
  2456. cfg->rd_scid = 0x0;
  2457. cfg->flags = SYS_CACHE_EN_FLAG | SYS_CACHE_SCID;
  2458. cfg->type = SDE_SYS_CACHE_NONE;
  2459. if ((sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
  2460. && ((pstate->static_cache_state == CACHE_STATE_FRAME_WRITE)
  2461. || (pstate->static_cache_state == CACHE_STATE_FRAME_READ))) {
  2462. cfg->rd_en = true;
  2463. cfg->rd_scid = sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2464. cfg->rd_noallocate = (pstate->static_cache_state == CACHE_STATE_FRAME_READ);
  2465. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2466. cfg->type = SDE_SYS_CACHE_DISP;
  2467. } else if ((sc_cfg[fb_cache_type].has_sys_cache) && fb_cache_flag) {
  2468. cfg->rd_en = true;
  2469. cfg->rd_scid = sc_cfg[fb_cache_type].llcc_scid;
  2470. cfg->rd_noallocate = true;
  2471. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2472. cfg->type = fb_cache_type;
  2473. msm_framebuffer_set_cache_hint(state->fb, MSM_FB_CACHE_READ_EN, fb_cache_type);
  2474. }
  2475. if (!cfg->rd_en && !prev_rd_en)
  2476. return;
  2477. SDE_EVT32(DRMID(&psde->base), cfg->rd_scid, cfg->rd_en, cfg->rd_noallocate, cfg->flags,
  2478. fb_cache_flag, fb_cache_type);
  2479. psde->pipe_hw->ops.setup_sys_cache(psde->pipe_hw, cfg);
  2480. }
  2481. void sde_plane_static_img_control(struct drm_plane *plane,
  2482. enum sde_sys_cache_state state)
  2483. {
  2484. struct sde_plane *psde;
  2485. struct sde_plane_state *pstate;
  2486. if (!plane || !plane->state) {
  2487. SDE_ERROR("invalid plane\n");
  2488. return;
  2489. }
  2490. psde = to_sde_plane(plane);
  2491. pstate = to_sde_plane_state(plane->state);
  2492. pstate->static_cache_state = state;
  2493. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2494. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2495. }
  2496. static void _sde_plane_map_prop_to_dirty_bits(void)
  2497. {
  2498. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2499. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2500. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2501. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2502. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2503. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2504. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2505. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2506. plane_prop_array[PLANE_PROP_ZPOS] =
  2507. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2508. plane_prop_array[PLANE_PROP_UBWC_STATS_ROI] =
  2509. SDE_PLANE_DIRTY_RECTS;
  2510. plane_prop_array[PLANE_PROP_CSC_V1] =
  2511. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2512. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2513. SDE_PLANE_DIRTY_FORMAT;
  2514. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2515. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2516. SDE_PLANE_DIRTY_ALL;
  2517. /* no special action required */
  2518. plane_prop_array[PLANE_PROP_INFO] =
  2519. plane_prop_array[PLANE_PROP_ALPHA] =
  2520. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2521. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2522. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2523. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2524. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2525. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2526. SDE_PLANE_DIRTY_PERF;
  2527. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2528. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2529. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2530. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2531. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2532. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2533. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2534. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2535. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2536. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2537. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2538. SDE_PLANE_DIRTY_ALL;
  2539. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2540. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2541. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2542. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2543. }
  2544. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2545. struct sde_rect *src, struct sde_rect *dst)
  2546. {
  2547. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2548. u32 downscale = (src->h * 1000)/dst->h;
  2549. return (downscale > max_downscale) ? false : true;
  2550. }
  2551. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2552. struct sde_plane *psde, struct sde_plane_state *pstate,
  2553. struct sde_rect *src, struct sde_rect *dst)
  2554. {
  2555. struct sde_hw_pipe_uidle_cfg cfg;
  2556. u32 line_time = sde_crtc_get_line_time(crtc);
  2557. u32 fal1_target_idle_time_ns =
  2558. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2559. u32 fal10_target_idle_time_ns =
  2560. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2561. u32 fal10_threshold =
  2562. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2563. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2564. fal1_target_idle_time_ns) {
  2565. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2566. cfg.fal10_threshold = fal10_threshold;
  2567. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2568. cfg.fal1_threshold = min(1 +
  2569. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2570. psde->catalog->uidle_cfg.fal1_max_threshold);
  2571. cfg.fal_allowed_threshold = fal10_threshold +
  2572. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2573. cfg.fill_level_scale = 0;
  2574. /*
  2575. * if uidle fill scale is supported, determing the scale value
  2576. * and adjust fal10 thresholds to their scaled values.
  2577. * fal1 thresholds and fal_allowed are not scaled.
  2578. */
  2579. if (psde->pipe_hw->ops.setup_uidle_fill_scale) {
  2580. u32 fl_require0 = psde->catalog->qos_target_time_ns / line_time * 2;
  2581. u32 fl_require = max(fal10_threshold * 1000, fl_require0);
  2582. u32 fl_scale = fl_require / fal10_threshold;
  2583. u32 fal10_threshold_noscale;
  2584. cfg.fill_level_scale = (fl_scale <= 1) ? 0 : (32 / fl_scale);
  2585. if (cfg.fill_level_scale) {
  2586. fal10_threshold_noscale = fal10_threshold *
  2587. 32/cfg.fill_level_scale;
  2588. cfg.fal_allowed_threshold = fal10_threshold_noscale +
  2589. (fal10_target_idle_time_ns * 1000 / line_time * 2) / 1000;
  2590. }
  2591. }
  2592. } else {
  2593. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2594. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2595. fal1_target_idle_time_ns);
  2596. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2597. }
  2598. SDE_DEBUG_PLANE(psde,
  2599. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d fill_scale=%d\n",
  2600. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2601. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2602. cfg.fill_level_scale);
  2603. SDE_DEBUG_PLANE(psde,
  2604. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2605. line_time, fal1_target_idle_time_ns,
  2606. fal10_target_idle_time_ns,
  2607. psde->catalog->uidle_cfg.max_dwnscale);
  2608. SDE_EVT32_VERBOSE(cfg.enable,
  2609. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2610. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2611. cfg.fill_level_scale, psde->catalog->uidle_cfg.max_dwnscale);
  2612. if (psde->pipe_hw->ops.setup_uidle_fill_scale)
  2613. psde->pipe_hw->ops.setup_uidle_fill_scale(psde->pipe_hw, &cfg);
  2614. psde->pipe_hw->ops.setup_uidle(
  2615. psde->pipe_hw, &cfg,
  2616. pstate->multirect_index);
  2617. }
  2618. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2619. struct sde_plane_state *pstate)
  2620. {
  2621. bool enable = false;
  2622. int mode = sde_plane_get_property(pstate,
  2623. PLANE_PROP_FB_TRANSLATION_MODE);
  2624. if ((mode == SDE_DRM_FB_SEC) ||
  2625. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2626. enable = true;
  2627. /* update secure session flag */
  2628. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2629. pstate->multirect_index,
  2630. enable);
  2631. }
  2632. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2633. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2634. {
  2635. const struct sde_format *fmt;
  2636. const struct msm_format *msm_fmt;
  2637. struct sde_plane *psde;
  2638. struct drm_plane_state *state;
  2639. struct sde_plane_state *pstate;
  2640. struct sde_rect src, dst;
  2641. const struct sde_rect *crtc_roi;
  2642. bool q16_data = true;
  2643. int idx;
  2644. psde = to_sde_plane(plane);
  2645. state = plane->state;
  2646. pstate = to_sde_plane_state(state);
  2647. msm_fmt = msm_framebuffer_format(fb);
  2648. if (!msm_fmt) {
  2649. SDE_ERROR("crtc%d plane%d: null format\n",
  2650. DRMID(crtc), DRMID(plane));
  2651. return;
  2652. }
  2653. fmt = to_sde_format(msm_fmt);
  2654. POPULATE_RECT(&src, state->src_x, state->src_y,
  2655. state->src_w, state->src_h, q16_data);
  2656. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2657. state->crtc_w, state->crtc_h, !q16_data);
  2658. SDE_DEBUG_PLANE(psde,
  2659. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2660. fb->base.id, src.x, src.y, src.w, src.h,
  2661. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2662. (char *)&fmt->base.pixel_format,
  2663. SDE_FORMAT_IS_UBWC(fmt));
  2664. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2665. BIT(SDE_DRM_DEINTERLACE)) {
  2666. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2667. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2668. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2669. src.h /= 2;
  2670. src.y = DIV_ROUND_UP(src.y, 2);
  2671. src.y &= ~0x1;
  2672. }
  2673. /*
  2674. * adjust layer mixer position of the sspp in the presence
  2675. * of a partial update to the active lm origin
  2676. */
  2677. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2678. dst.x -= crtc_roi->x;
  2679. dst.y -= crtc_roi->y;
  2680. /* check for UIDLE */
  2681. if (psde->pipe_hw->ops.setup_uidle)
  2682. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2683. psde->pipe_cfg.src_rect = src;
  2684. psde->pipe_cfg.dst_rect = dst;
  2685. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2686. _sde_plane_setup_panel_stacking(psde, pstate);
  2687. /* check for color fill */
  2688. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2689. PLANE_PROP_COLOR_FILL);
  2690. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2691. /* skip remaining processing on color fill */
  2692. pstate->dirty = 0x0;
  2693. } else if (psde->pipe_hw->ops.setup_rects) {
  2694. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2695. &psde->pipe_cfg,
  2696. pstate->multirect_index);
  2697. }
  2698. if (psde->pipe_hw->ops.setup_pe &&
  2699. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2700. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2701. &psde->pixel_ext);
  2702. /**
  2703. * when programmed in multirect mode, scalar block will be
  2704. * bypassed. Still we need to update alpha and bitwidth
  2705. * ONLY for RECT0
  2706. */
  2707. if (psde->pipe_hw->ops.setup_scaler &&
  2708. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2709. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2710. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2711. &psde->pipe_cfg, &psde->pixel_ext,
  2712. &psde->scaler3_cfg);
  2713. }
  2714. /* update excl rect */
  2715. if (psde->pipe_hw->ops.setup_excl_rect)
  2716. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2717. &pstate->excl_rect,
  2718. pstate->multirect_index);
  2719. /* enable multirect config of corresponding rect */
  2720. if (psde->pipe_hw->ops.update_multirect)
  2721. psde->pipe_hw->ops.update_multirect(
  2722. psde->pipe_hw,
  2723. true,
  2724. pstate->multirect_index,
  2725. pstate->multirect_mode);
  2726. /* update line insertion */
  2727. if (pstate->lineinsertion_feature && psde->pipe_hw->ops.setup_line_insertion)
  2728. psde->pipe_hw->ops.setup_line_insertion(psde->pipe_hw,
  2729. pstate->multirect_index,
  2730. &pstate->line_insertion_cfg);
  2731. }
  2732. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2733. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2734. {
  2735. uint32_t src_flags = 0;
  2736. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2737. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2738. src_flags |= SDE_SSPP_FLIP_LR;
  2739. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2740. src_flags |= SDE_SSPP_FLIP_UD;
  2741. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2742. src_flags |= SDE_SSPP_ROT_90;
  2743. /* update format */
  2744. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2745. pstate->const_alpha_en, src_flags,
  2746. pstate->multirect_index);
  2747. if (psde->pipe_hw->ops.setup_cdp) {
  2748. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2749. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2750. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2751. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2752. cdp_cfg->ubwc_meta_enable =
  2753. SDE_FORMAT_IS_UBWC(fmt);
  2754. cdp_cfg->tile_amortize_enable =
  2755. SDE_FORMAT_IS_UBWC(fmt) ||
  2756. SDE_FORMAT_IS_TILE(fmt);
  2757. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2758. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2759. pstate->multirect_index);
  2760. }
  2761. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2762. /* update csc */
  2763. if (SDE_FORMAT_IS_YUV(fmt))
  2764. _sde_plane_setup_csc(psde);
  2765. else
  2766. psde->csc_ptr = 0;
  2767. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2768. uint32_t pma_mode = 0;
  2769. if (fmt->alpha_enable)
  2770. pma_mode = (uint32_t) sde_plane_get_property(
  2771. pstate, PLANE_PROP_INVERSE_PMA);
  2772. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2773. pstate->multirect_index, pma_mode);
  2774. }
  2775. if (psde->pipe_hw->ops.setup_dgm_csc)
  2776. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2777. pstate->multirect_index, psde->csc_usr_ptr);
  2778. if (psde->pipe_hw->ops.set_ubwc_stats_roi) {
  2779. if (SDE_FORMAT_IS_UBWC(fmt) && !SDE_FORMAT_IS_YUV(fmt))
  2780. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2781. pstate->multirect_index, &pstate->ubwc_stats_roi);
  2782. else
  2783. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2784. pstate->multirect_index, NULL);
  2785. }
  2786. }
  2787. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2788. {
  2789. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2790. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2791. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2792. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2793. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2794. &psde->sharp_cfg);
  2795. }
  2796. static void _sde_plane_update_properties(struct drm_plane *plane,
  2797. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2798. {
  2799. uint32_t nplanes;
  2800. const struct msm_format *msm_fmt;
  2801. const struct sde_format *fmt;
  2802. struct sde_plane *psde;
  2803. struct drm_plane_state *state;
  2804. struct sde_plane_state *pstate;
  2805. psde = to_sde_plane(plane);
  2806. state = plane->state;
  2807. pstate = to_sde_plane_state(state);
  2808. if (!pstate) {
  2809. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2810. return;
  2811. }
  2812. msm_fmt = msm_framebuffer_format(fb);
  2813. if (!msm_fmt) {
  2814. SDE_ERROR("crtc%d plane%d: null format\n",
  2815. DRMID(crtc), DRMID(plane));
  2816. return;
  2817. }
  2818. fmt = to_sde_format(msm_fmt);
  2819. nplanes = fmt->num_planes;
  2820. /* update secure session flag */
  2821. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2822. _sde_plane_update_secure_session(psde, pstate);
  2823. /* update roi config */
  2824. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2825. _sde_plane_update_roi_config(plane, crtc, fb);
  2826. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2827. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2828. psde->pipe_hw->ops.setup_format)
  2829. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2830. sde_color_process_plane_setup(plane);
  2831. /* update sharpening */
  2832. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2833. psde->pipe_hw->ops.setup_sharpening)
  2834. _sde_plane_update_sharpening(psde);
  2835. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2836. SDE_PLANE_DIRTY_FORMAT))
  2837. _sde_plane_set_qos_lut(plane, crtc, fb);
  2838. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2839. _sde_plane_set_ot_limit(plane, crtc);
  2840. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2841. _sde_plane_set_ts_prefill(plane, pstate);
  2842. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2843. _sde_plane_set_qos_remap(plane);
  2844. /* clear dirty */
  2845. pstate->dirty = 0x0;
  2846. }
  2847. static void _sde_plane_check_lut_dirty(struct sde_plane *psde,
  2848. struct sde_plane_state *pstate)
  2849. {
  2850. /**
  2851. * Valid configuration if scaler is not enabled or
  2852. * lut flag is set
  2853. */
  2854. if (pstate->scaler3_cfg.lut_flag || !pstate->scaler3_cfg.enable)
  2855. return;
  2856. pstate->scaler3_cfg.lut_flag = psde->cached_lut_flag;
  2857. SDE_EVT32(DRMID(&psde->base), pstate->scaler3_cfg.lut_flag, SDE_EVTLOG_ERROR);
  2858. }
  2859. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2860. struct drm_plane_state *old_state)
  2861. {
  2862. struct sde_plane *psde;
  2863. struct drm_plane_state *state;
  2864. struct sde_plane_state *pstate;
  2865. struct sde_plane_state *old_pstate;
  2866. struct drm_crtc *crtc;
  2867. struct drm_framebuffer *fb;
  2868. int idx;
  2869. int dirty_prop_flag;
  2870. bool is_rt;
  2871. if (!plane) {
  2872. SDE_ERROR("invalid plane\n");
  2873. return -EINVAL;
  2874. } else if (!plane->state) {
  2875. SDE_ERROR("invalid plane state\n");
  2876. return -EINVAL;
  2877. } else if (!old_state) {
  2878. SDE_ERROR("invalid old state\n");
  2879. return -EINVAL;
  2880. }
  2881. psde = to_sde_plane(plane);
  2882. state = plane->state;
  2883. pstate = to_sde_plane_state(state);
  2884. old_pstate = to_sde_plane_state(old_state);
  2885. crtc = state->crtc;
  2886. fb = state->fb;
  2887. if (!crtc || !fb) {
  2888. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2889. !crtc, !fb);
  2890. return -EINVAL;
  2891. }
  2892. SDE_DEBUG(
  2893. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2894. plane->base.id,
  2895. state->fb->width, state->fb->height,
  2896. (char *) &state->fb->format->format,
  2897. state->fb->modifier,
  2898. state->src_w >> 16, state->src_h >> 16,
  2899. state->src_x >> 16, state->src_y >> 16,
  2900. pstate->rotation,
  2901. state->crtc_w, state->crtc_h,
  2902. state->crtc_x, state->crtc_y);
  2903. /* Caching the valid lut flag in sde plane */
  2904. if (pstate->scaler3_cfg.enable && pstate->scaler3_cfg.lut_flag)
  2905. psde->cached_lut_flag = pstate->scaler3_cfg.lut_flag;
  2906. /* force reprogramming of all the parameters, if the flag is set */
  2907. if (psde->revalidate) {
  2908. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2909. plane->base.id);
  2910. _sde_plane_check_lut_dirty(psde, pstate);
  2911. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2912. psde->revalidate = false;
  2913. }
  2914. /* determine what needs to be refreshed */
  2915. mutex_lock(&psde->property_info.property_lock);
  2916. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2917. &pstate->property_state)) >= 0) {
  2918. dirty_prop_flag = plane_prop_array[idx];
  2919. pstate->dirty |= dirty_prop_flag;
  2920. }
  2921. mutex_unlock(&psde->property_info.property_lock);
  2922. /**
  2923. * since plane_atomic_check is invoked before crtc_atomic_check
  2924. * in the commit sequence, all the parameters for updating the
  2925. * plane dirty flag will not be available during
  2926. * plane_atomic_check as some features params are updated
  2927. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2928. * before sspp update.
  2929. */
  2930. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2931. old_state);
  2932. /* re-program the output rects always if partial update roi changed */
  2933. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2934. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2935. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2936. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2937. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2938. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2939. if (is_rt != psde->is_rt_pipe || crtc->state->mode_changed) {
  2940. psde->is_rt_pipe = is_rt;
  2941. psde->wb_usage_type = psde->is_rt_pipe ? 0 : sde_crtc_get_wb_usage_type(crtc);
  2942. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2943. }
  2944. /* early out if nothing dirty */
  2945. if (!pstate->dirty)
  2946. return 0;
  2947. pstate->pending = true;
  2948. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2949. _sde_plane_update_properties(plane, crtc, fb);
  2950. return 0;
  2951. }
  2952. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2953. struct drm_plane_state *old_state)
  2954. {
  2955. struct sde_plane *psde;
  2956. struct drm_plane_state *state;
  2957. struct sde_plane_state *pstate;
  2958. u32 multirect_index = SDE_SSPP_RECT_0;
  2959. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  2960. u32 blend_type;
  2961. if (!plane) {
  2962. SDE_ERROR("invalid plane\n");
  2963. return;
  2964. } else if (!plane->state) {
  2965. SDE_ERROR("invalid plane state\n");
  2966. return;
  2967. } else if (!old_state) {
  2968. SDE_ERROR("invalid old state\n");
  2969. return;
  2970. }
  2971. psde = to_sde_plane(plane);
  2972. state = plane->state;
  2973. pstate = to_sde_plane_state(state);
  2974. blend_type = sde_plane_get_property(pstate,
  2975. PLANE_PROP_BLEND_OP);
  2976. /* some of the color features are dependent on plane with skip blend.
  2977. * if skip blend plane is being disabled, we need to disable color properties.
  2978. */
  2979. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  2980. skip_blend_plane.valid_plane = false;
  2981. skip_blend_plane.plane = SSPP_NONE;
  2982. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  2983. sde_crtc_disable_cp_features(old_state->crtc);
  2984. }
  2985. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2986. pstate->multirect_mode);
  2987. pstate->pending = true;
  2988. if (is_sde_plane_virtual(plane))
  2989. multirect_index = SDE_SSPP_RECT_1;
  2990. /* disable multirect config of corresponding rect */
  2991. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2992. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2993. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2994. }
  2995. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2996. static void _sde_plane_atomic_update(struct drm_plane *plane,
  2997. struct drm_plane_state *old_state)
  2998. #else
  2999. static void sde_plane_atomic_update(struct drm_plane *plane,
  3000. struct drm_plane_state *old_state)
  3001. #endif
  3002. {
  3003. struct sde_plane *psde;
  3004. struct drm_plane_state *state;
  3005. if (!plane) {
  3006. SDE_ERROR("invalid plane\n");
  3007. return;
  3008. } else if (!plane->state) {
  3009. SDE_ERROR("invalid plane state\n");
  3010. return;
  3011. }
  3012. psde = to_sde_plane(plane);
  3013. psde->is_error = false;
  3014. state = plane->state;
  3015. SDE_DEBUG_PLANE(psde, "\n");
  3016. if (!sde_plane_enabled(state)) {
  3017. _sde_plane_atomic_disable(plane, old_state);
  3018. } else {
  3019. int ret;
  3020. ret = sde_plane_sspp_atomic_update(plane, old_state);
  3021. /* atomic_check should have ensured that this doesn't fail */
  3022. WARN_ON(ret < 0);
  3023. }
  3024. }
  3025. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3026. static void sde_plane_atomic_update(struct drm_plane *plane,
  3027. struct drm_atomic_state *atomic_state)
  3028. {
  3029. struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(atomic_state, plane);
  3030. _sde_plane_atomic_update(plane, old_state);
  3031. }
  3032. #endif
  3033. void sde_plane_restore(struct drm_plane *plane)
  3034. {
  3035. struct sde_plane *psde;
  3036. if (!plane || !plane->state) {
  3037. SDE_ERROR("invalid plane\n");
  3038. return;
  3039. }
  3040. psde = to_sde_plane(plane);
  3041. /*
  3042. * Revalidate is only true here if idle PC occurred and
  3043. * there is no plane state update in current commit cycle.
  3044. */
  3045. if (!psde->revalidate)
  3046. return;
  3047. SDE_DEBUG_PLANE(psde, "\n");
  3048. /* last plane state is same as current state */
  3049. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3050. _sde_plane_atomic_update(plane, plane->state);
  3051. #else
  3052. sde_plane_atomic_update(plane, plane->state);
  3053. #endif
  3054. }
  3055. bool sde_plane_is_cache_required(struct drm_plane *plane,
  3056. enum sde_sys_cache_type type)
  3057. {
  3058. struct sde_plane_state *pstate;
  3059. if (!plane || !plane->state) {
  3060. SDE_ERROR("invalid plane\n");
  3061. return false;
  3062. }
  3063. pstate = to_sde_plane_state(plane->state);
  3064. /* check if llcc is required for the plane */
  3065. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  3066. return true;
  3067. else
  3068. return false;
  3069. }
  3070. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  3071. {
  3072. char feature_name[256];
  3073. if (psde->pipe_sblk->maxhdeciexp) {
  3074. msm_property_install_range(&psde->property_info,
  3075. "h_decimate", 0x0, 0,
  3076. psde->pipe_sblk->maxhdeciexp, 0,
  3077. PLANE_PROP_H_DECIMATE);
  3078. }
  3079. if (psde->pipe_sblk->maxvdeciexp) {
  3080. msm_property_install_range(&psde->property_info,
  3081. "v_decimate", 0x0, 0,
  3082. psde->pipe_sblk->maxvdeciexp, 0,
  3083. PLANE_PROP_V_DECIMATE);
  3084. }
  3085. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  3086. msm_property_install_range(
  3087. &psde->property_info, "scaler_v2",
  3088. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3089. msm_property_install_blob(&psde->property_info,
  3090. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  3091. msm_property_install_blob(&psde->property_info,
  3092. "lut_cir", 0,
  3093. PLANE_PROP_SCALER_LUT_CIR);
  3094. msm_property_install_blob(&psde->property_info,
  3095. "lut_sep", 0,
  3096. PLANE_PROP_SCALER_LUT_SEP);
  3097. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  3098. msm_property_install_range(
  3099. &psde->property_info, "scaler_v2",
  3100. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3101. msm_property_install_blob(&psde->property_info,
  3102. "lut_sep", 0,
  3103. PLANE_PROP_SCALER_LUT_SEP);
  3104. } else if (psde->features & SDE_SSPP_SCALER) {
  3105. msm_property_install_range(
  3106. &psde->property_info, "scaler_v1", 0x0,
  3107. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  3108. }
  3109. if (psde->features & BIT(SDE_SSPP_CSC) ||
  3110. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  3111. msm_property_install_volatile_range(
  3112. &psde->property_info, "csc_v1", 0x0,
  3113. 0, ~0, 0, PLANE_PROP_CSC_V1);
  3114. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  3115. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3116. "SDE_SSPP_HUE_V",
  3117. psde->pipe_sblk->hsic_blk.version >> 16);
  3118. msm_property_install_range(&psde->property_info,
  3119. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3120. PLANE_PROP_HUE_ADJUST);
  3121. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3122. "SDE_SSPP_SATURATION_V",
  3123. psde->pipe_sblk->hsic_blk.version >> 16);
  3124. msm_property_install_range(&psde->property_info,
  3125. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3126. PLANE_PROP_SATURATION_ADJUST);
  3127. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3128. "SDE_SSPP_VALUE_V",
  3129. psde->pipe_sblk->hsic_blk.version >> 16);
  3130. msm_property_install_range(&psde->property_info,
  3131. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3132. PLANE_PROP_VALUE_ADJUST);
  3133. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3134. "SDE_SSPP_CONTRAST_V",
  3135. psde->pipe_sblk->hsic_blk.version >> 16);
  3136. msm_property_install_range(&psde->property_info,
  3137. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3138. PLANE_PROP_CONTRAST_ADJUST);
  3139. }
  3140. }
  3141. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3142. struct sde_kms_info *info)
  3143. {
  3144. char feature_name[256];
  3145. bool is_master = !psde->is_virtual;
  3146. if ((is_master &&
  3147. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3148. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3149. msm_property_install_range(&psde->property_info,
  3150. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3151. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3152. }
  3153. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3154. msm_property_install_volatile_range(
  3155. &psde->property_info, "csc_dma_v1", 0x0,
  3156. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3157. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3158. }
  3159. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3160. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3161. "SDE_SSPP_SKIN_COLOR_V",
  3162. psde->pipe_sblk->memcolor_blk.version >> 16);
  3163. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3164. PLANE_PROP_SKIN_COLOR);
  3165. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3166. "SDE_SSPP_SKY_COLOR_V",
  3167. psde->pipe_sblk->memcolor_blk.version >> 16);
  3168. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3169. PLANE_PROP_SKY_COLOR);
  3170. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3171. "SDE_SSPP_FOLIAGE_COLOR_V",
  3172. psde->pipe_sblk->memcolor_blk.version >> 16);
  3173. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3174. PLANE_PROP_FOLIAGE_COLOR);
  3175. }
  3176. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3177. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3178. "SDE_VIG_3D_LUT_GAMUT_V",
  3179. psde->pipe_sblk->gamut_blk.version >> 16);
  3180. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3181. PLANE_PROP_VIG_GAMUT);
  3182. }
  3183. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3184. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3185. "SDE_VIG_1D_LUT_IGC_V",
  3186. psde->pipe_sblk->igc_blk[0].version >> 16);
  3187. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3188. PLANE_PROP_VIG_IGC);
  3189. }
  3190. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3191. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3192. "SDE_DGM_1D_LUT_IGC_V",
  3193. psde->pipe_sblk->igc_blk[0].version >> 16);
  3194. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3195. PLANE_PROP_DMA_IGC);
  3196. }
  3197. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3198. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3199. "SDE_DGM_1D_LUT_GC_V",
  3200. psde->pipe_sblk->gc_blk[0].version >> 16);
  3201. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3202. PLANE_PROP_DMA_GC);
  3203. }
  3204. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3205. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3206. "SDE_SSPP_FP16_IGC_V",
  3207. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3208. msm_property_install_range(&psde->property_info, feature_name,
  3209. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3210. }
  3211. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3212. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3213. "SDE_SSPP_FP16_GC_V",
  3214. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3215. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3216. PLANE_PROP_FP16_GC);
  3217. }
  3218. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3219. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3220. "SDE_SSPP_FP16_CSC_V",
  3221. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3222. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3223. PLANE_PROP_FP16_CSC);
  3224. }
  3225. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3226. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3227. "SDE_SSPP_FP16_UNMULT_V",
  3228. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3229. msm_property_install_range(&psde->property_info, feature_name,
  3230. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3231. }
  3232. }
  3233. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3234. u32 master_plane_id, struct sde_kms_info *info,
  3235. struct sde_mdss_cfg *catalog)
  3236. {
  3237. bool is_master = !psde->is_virtual;
  3238. const struct sde_format_extended *format_list;
  3239. u32 index;
  3240. int pipe_id;
  3241. if (is_master) {
  3242. format_list = psde->pipe_sblk->format_list;
  3243. } else {
  3244. format_list = psde->pipe_sblk->virt_format_list;
  3245. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3246. master_plane_id);
  3247. }
  3248. if (format_list) {
  3249. sde_kms_info_start(info, "pixel_formats");
  3250. while (format_list->fourcc_format) {
  3251. sde_kms_info_append_format(info,
  3252. format_list->fourcc_format,
  3253. format_list->modifier);
  3254. ++format_list;
  3255. }
  3256. sde_kms_info_stop(info);
  3257. }
  3258. if (psde->pipe_hw && catalog->qseed_hw_rev)
  3259. sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
  3260. sde_kms_info_add_keyint(info, "max_linewidth",
  3261. psde->pipe_sblk->maxlinewidth);
  3262. sde_kms_info_add_keyint(info, "max_upscale",
  3263. psde->pipe_sblk->maxupscale);
  3264. sde_kms_info_add_keyint(info, "max_downscale",
  3265. psde->pipe_sblk->maxdwnscale);
  3266. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3267. psde->pipe_sblk->maxhdeciexp);
  3268. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3269. psde->pipe_sblk->maxvdeciexp);
  3270. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3271. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3272. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3273. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3274. if (SDE_SSPP_VALID_VIG(psde->pipe))
  3275. pipe_id = psde->pipe - SSPP_VIG0;
  3276. else if (SDE_SSPP_VALID_DMA(psde->pipe))
  3277. pipe_id = psde->pipe - SSPP_DMA0;
  3278. else
  3279. pipe_id = -1;
  3280. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3281. index = (master_plane_id == 0) ? 0 : 1;
  3282. if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
  3283. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3284. sde_kms_info_add_keyint(info, "demura_block", index);
  3285. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3286. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3287. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3288. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3289. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3290. const struct sde_format_extended *inline_rot_fmt_list;
  3291. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3292. catalog->true_inline_rot_rev);
  3293. sde_kms_info_add_keyint(info,
  3294. "true_inline_dwnscale_rt",
  3295. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3296. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3297. sde_kms_info_add_keyint(info,
  3298. "true_inline_dwnscale_rt_numerator",
  3299. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3300. sde_kms_info_add_keyint(info,
  3301. "true_inline_dwnscale_rt_denominator",
  3302. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3303. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3304. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3305. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3306. psde->pipe_sblk->in_rot_maxheight);
  3307. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3308. if (inline_rot_fmt_list) {
  3309. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3310. while (inline_rot_fmt_list->fourcc_format) {
  3311. sde_kms_info_append_format(info,
  3312. inline_rot_fmt_list->fourcc_format,
  3313. inline_rot_fmt_list->modifier);
  3314. ++inline_rot_fmt_list;
  3315. }
  3316. sde_kms_info_stop(info);
  3317. }
  3318. }
  3319. }
  3320. /* helper to install properties which are common to planes and crtcs */
  3321. static void _sde_plane_install_properties(struct drm_plane *plane,
  3322. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3323. {
  3324. static const struct drm_prop_enum_list e_blend_op[] = {
  3325. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3326. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3327. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3328. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3329. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3330. };
  3331. static const struct drm_prop_enum_list e_src_config[] = {
  3332. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3333. };
  3334. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3335. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3336. {SDE_DRM_FB_SEC, "sec"},
  3337. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3338. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3339. };
  3340. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3341. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3342. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3343. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3344. };
  3345. struct sde_kms_info *info;
  3346. struct sde_plane *psde = to_sde_plane(plane);
  3347. bool is_master;
  3348. int zpos_max = 255;
  3349. int zpos_def = 0;
  3350. if (!plane || !psde) {
  3351. SDE_ERROR("invalid plane\n");
  3352. return;
  3353. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3354. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3355. !psde->pipe_hw, !psde->pipe_sblk);
  3356. return;
  3357. } else if (!catalog) {
  3358. SDE_ERROR("invalid catalog\n");
  3359. return;
  3360. }
  3361. psde->catalog = catalog;
  3362. is_master = !psde->is_virtual;
  3363. info = vzalloc(sizeof(struct sde_kms_info));
  3364. if (!info) {
  3365. SDE_ERROR("failed to allocate info memory\n");
  3366. return;
  3367. }
  3368. if (sde_is_custom_client()) {
  3369. if (catalog->mixer_count &&
  3370. catalog->mixer[0].sblk->maxblendstages) {
  3371. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3372. if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
  3373. (zpos_max > SDE_STAGE_MAX - 1))
  3374. zpos_max = SDE_STAGE_MAX - 1;
  3375. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3376. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3377. }
  3378. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3379. /* reserve zpos == 0 for primary planes */
  3380. zpos_def = drm_plane_index(plane) + 1;
  3381. }
  3382. msm_property_install_range(&psde->property_info, "zpos",
  3383. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3384. msm_property_install_range(&psde->property_info, "alpha",
  3385. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3386. /* linux default file descriptor range on each process */
  3387. msm_property_install_range(&psde->property_info, "input_fence",
  3388. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3389. if (is_master)
  3390. _sde_plane_install_master_only_properties(psde);
  3391. else
  3392. msm_property_install_enum(&psde->property_info,
  3393. "multirect_mode", 0x0, 0, e_multirect_mode,
  3394. ARRAY_SIZE(e_multirect_mode), 0,
  3395. PLANE_PROP_MULTIRECT_MODE);
  3396. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3397. msm_property_install_volatile_range(&psde->property_info,
  3398. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3399. sde_plane_rot_install_properties(plane, catalog);
  3400. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3401. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3402. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3403. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3404. PLANE_PROP_SRC_CONFIG);
  3405. if (psde->pipe_hw->ops.setup_solidfill)
  3406. msm_property_install_range(&psde->property_info, "color_fill",
  3407. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3408. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3409. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3410. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3411. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3412. msm_property_install_blob(&psde->property_info, "capabilities",
  3413. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3414. sde_kms_info_reset(info);
  3415. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3416. catalog);
  3417. _sde_plane_install_colorproc_properties(psde, info);
  3418. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3419. info->data, SDE_KMS_INFO_DATALEN(info),
  3420. PLANE_PROP_INFO);
  3421. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3422. 0x0, 0, e_fb_translation_mode,
  3423. ARRAY_SIZE(e_fb_translation_mode), 0,
  3424. PLANE_PROP_FB_TRANSLATION_MODE);
  3425. if (psde->pipe_hw->ops.set_ubwc_stats_roi)
  3426. msm_property_install_range(&psde->property_info, "ubwc_stats_roi",
  3427. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_UBWC_STATS_ROI);
  3428. vfree(info);
  3429. }
  3430. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3431. void __user *usr_ptr)
  3432. {
  3433. struct sde_drm_csc_v1 csc_v1;
  3434. int i;
  3435. if (!psde) {
  3436. SDE_ERROR("invalid plane\n");
  3437. return;
  3438. }
  3439. psde->csc_usr_ptr = NULL;
  3440. if (!usr_ptr) {
  3441. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3442. return;
  3443. }
  3444. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3445. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3446. return;
  3447. }
  3448. /* populate from user space */
  3449. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3450. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3451. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3452. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3453. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3454. }
  3455. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3456. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3457. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3458. }
  3459. psde->csc_usr_ptr = &psde->csc_cfg;
  3460. }
  3461. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3462. struct sde_plane_state *pstate, void __user *usr)
  3463. {
  3464. struct sde_drm_scaler_v1 scale_v1;
  3465. struct sde_hw_pixel_ext *pe;
  3466. int i;
  3467. if (!psde || !pstate) {
  3468. SDE_ERROR("invalid argument(s)\n");
  3469. return;
  3470. }
  3471. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3472. if (!usr) {
  3473. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3474. return;
  3475. }
  3476. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3477. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3478. return;
  3479. }
  3480. /* force property to be dirty, even if the pointer didn't change */
  3481. msm_property_set_dirty(&psde->property_info,
  3482. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3483. /* populate from user space */
  3484. pe = &pstate->pixel_ext;
  3485. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3486. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3487. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3488. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3489. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3490. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3491. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3492. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3493. }
  3494. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3495. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3496. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3497. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3498. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3499. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3500. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3501. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3502. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3503. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3504. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3505. }
  3506. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3507. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3508. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3509. }
  3510. static void _sde_plane_clear_predownscale_settings(
  3511. struct sde_plane_state *pstate)
  3512. {
  3513. pstate->pre_down.pre_downscale_x_0 = 0;
  3514. pstate->pre_down.pre_downscale_x_1 = 0;
  3515. pstate->pre_down.pre_downscale_y_0 = 0;
  3516. pstate->pre_down.pre_downscale_y_1 = 0;
  3517. }
  3518. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3519. struct sde_plane_state *pstate, void __user *usr)
  3520. {
  3521. struct sde_drm_scaler_v2 scale_v2;
  3522. struct sde_hw_pixel_ext *pe;
  3523. int i;
  3524. struct sde_hw_scaler3_cfg *cfg;
  3525. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3526. if (!psde || !pstate) {
  3527. SDE_ERROR("invalid argument(s)\n");
  3528. return;
  3529. }
  3530. cfg = &pstate->scaler3_cfg;
  3531. pd_cfg = &pstate->pre_down;
  3532. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3533. if (!usr) {
  3534. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3535. cfg->enable = 0;
  3536. _sde_plane_clear_predownscale_settings(pstate);
  3537. goto end;
  3538. }
  3539. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3540. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3541. return;
  3542. }
  3543. /* detach/ignore user data if 'disabled' */
  3544. if (!scale_v2.enable) {
  3545. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3546. cfg->enable = 0;
  3547. _sde_plane_clear_predownscale_settings(pstate);
  3548. goto end;
  3549. }
  3550. /* populate from user space */
  3551. sde_set_scaler_v2(cfg, &scale_v2);
  3552. if (_sde_plane_has_pre_downscale(psde)) {
  3553. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3554. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3555. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3556. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3557. }
  3558. pe = &pstate->pixel_ext;
  3559. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3560. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3561. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3562. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3563. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3564. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3565. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3566. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3567. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3568. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3569. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3570. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3571. }
  3572. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3573. end:
  3574. /* force property to be dirty, even if the pointer didn't change */
  3575. msm_property_set_dirty(&psde->property_info,
  3576. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3577. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3578. cfg->src_width[0], cfg->src_height[0],
  3579. cfg->dst_width, cfg->dst_height);
  3580. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3581. }
  3582. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3583. struct sde_plane_state *pstate, void __user *usr_ptr)
  3584. {
  3585. struct drm_clip_rect excl_rect_v1;
  3586. if (!psde || !pstate) {
  3587. SDE_ERROR("invalid argument(s)\n");
  3588. return;
  3589. }
  3590. if (!usr_ptr) {
  3591. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3592. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3593. return;
  3594. }
  3595. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3596. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3597. return;
  3598. }
  3599. /* populate from user space */
  3600. pstate->excl_rect.x = excl_rect_v1.x1;
  3601. pstate->excl_rect.y = excl_rect_v1.y1;
  3602. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3603. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3604. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3605. pstate->excl_rect.x, pstate->excl_rect.y,
  3606. pstate->excl_rect.w, pstate->excl_rect.h);
  3607. }
  3608. static void _sde_plane_set_ubwc_stats_roi(struct sde_plane *psde,
  3609. struct sde_plane_state *pstate, void __user *usr_ptr)
  3610. {
  3611. struct sde_drm_ubwc_stats_roi roi = {0};
  3612. if (!psde || !pstate) {
  3613. SDE_ERROR("invalid argument(s)\n");
  3614. return;
  3615. }
  3616. if (!usr_ptr) {
  3617. SDE_DEBUG_PLANE(psde, "ubwc roi disabled");
  3618. goto end;
  3619. }
  3620. if (copy_from_user(&roi, usr_ptr, sizeof(roi))) {
  3621. SDE_ERROR_PLANE(psde, "failed to copy ubwc stats roi");
  3622. return;
  3623. }
  3624. if (roi.y_coord0 > psde->pipe_cfg.src_rect.h || roi.y_coord1 > psde->pipe_cfg.src_rect.h) {
  3625. SDE_ERROR_PLANE(psde, "invalid ubwc roi y0 0x%x, y1 0x%x, src height 0x%x",
  3626. roi.y_coord0, roi.y_coord1, psde->pipe_cfg.src_rect.h);
  3627. memset(&roi, 0, sizeof(roi));
  3628. }
  3629. end:
  3630. SDE_EVT32(psde, roi.y_coord0, roi.y_coord1);
  3631. memcpy(&pstate->ubwc_stats_roi, &roi, sizeof(struct sde_drm_ubwc_stats_roi));
  3632. }
  3633. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3634. struct drm_plane_state *state, struct drm_property *property,
  3635. uint64_t val)
  3636. {
  3637. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3638. struct sde_plane_state *pstate;
  3639. int idx, ret = -EINVAL;
  3640. SDE_DEBUG_PLANE(psde, "\n");
  3641. if (!plane) {
  3642. SDE_ERROR("invalid plane\n");
  3643. } else if (!state) {
  3644. SDE_ERROR_PLANE(psde, "invalid state\n");
  3645. } else {
  3646. pstate = to_sde_plane_state(state);
  3647. ret = msm_property_atomic_set(&psde->property_info,
  3648. &pstate->property_state, property, val);
  3649. if (!ret) {
  3650. idx = msm_property_index(&psde->property_info,
  3651. property);
  3652. switch (idx) {
  3653. case PLANE_PROP_INPUT_FENCE:
  3654. _sde_plane_set_input_fence(psde, pstate, val);
  3655. break;
  3656. case PLANE_PROP_CSC_V1:
  3657. case PLANE_PROP_CSC_DMA_V1:
  3658. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3659. break;
  3660. case PLANE_PROP_SCALER_V1:
  3661. _sde_plane_set_scaler_v1(psde, pstate,
  3662. (void *)(uintptr_t)val);
  3663. break;
  3664. case PLANE_PROP_SCALER_V2:
  3665. _sde_plane_set_scaler_v2(psde, pstate,
  3666. (void *)(uintptr_t)val);
  3667. break;
  3668. case PLANE_PROP_EXCL_RECT_V1:
  3669. _sde_plane_set_excl_rect_v1(psde, pstate,
  3670. (void *)(uintptr_t)val);
  3671. break;
  3672. case PLANE_PROP_UBWC_STATS_ROI:
  3673. _sde_plane_set_ubwc_stats_roi(psde, pstate,
  3674. (void __user *)(uintptr_t)val);
  3675. break;
  3676. default:
  3677. /* nothing to do */
  3678. break;
  3679. }
  3680. }
  3681. }
  3682. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3683. property->name, property->base.id, val, ret);
  3684. return ret;
  3685. }
  3686. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3687. const struct drm_plane_state *state,
  3688. struct drm_property *property, uint64_t *val)
  3689. {
  3690. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3691. struct sde_plane_state *pstate;
  3692. int ret = -EINVAL;
  3693. if (!plane) {
  3694. SDE_ERROR("invalid plane\n");
  3695. } else if (!state) {
  3696. SDE_ERROR("invalid state\n");
  3697. } else {
  3698. SDE_DEBUG_PLANE(psde, "\n");
  3699. pstate = to_sde_plane_state(state);
  3700. ret = msm_property_atomic_get(&psde->property_info,
  3701. &pstate->property_state, property, val);
  3702. }
  3703. return ret;
  3704. }
  3705. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3706. struct drm_plane_state *plane_state)
  3707. {
  3708. struct sde_plane *psde;
  3709. struct sde_plane_state *pstate;
  3710. struct drm_property *drm_prop;
  3711. enum msm_mdp_plane_property prop_idx;
  3712. if (!plane || !plane_state) {
  3713. SDE_ERROR("invalid params\n");
  3714. return -EINVAL;
  3715. }
  3716. psde = to_sde_plane(plane);
  3717. pstate = to_sde_plane_state(plane_state);
  3718. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3719. uint64_t val = pstate->property_values[prop_idx].value;
  3720. uint64_t def;
  3721. int ret;
  3722. drm_prop = msm_property_index_to_drm_property(
  3723. &psde->property_info, prop_idx);
  3724. if (!drm_prop) {
  3725. /* not all props will be installed, based on caps */
  3726. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3727. prop_idx);
  3728. continue;
  3729. }
  3730. def = msm_property_get_default(&psde->property_info, prop_idx);
  3731. if (val == def)
  3732. continue;
  3733. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3734. drm_prop->name, prop_idx, val, def);
  3735. ret = sde_plane_atomic_set_property(plane, plane_state,
  3736. drm_prop, def);
  3737. if (ret) {
  3738. SDE_ERROR_PLANE(psde,
  3739. "set property failed, idx %d ret %d\n",
  3740. prop_idx, ret);
  3741. continue;
  3742. }
  3743. }
  3744. return 0;
  3745. }
  3746. static void sde_plane_destroy(struct drm_plane *plane)
  3747. {
  3748. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3749. SDE_DEBUG_PLANE(psde, "\n");
  3750. if (psde) {
  3751. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3752. if (psde->blob_info)
  3753. drm_property_blob_put(psde->blob_info);
  3754. msm_property_destroy(&psde->property_info);
  3755. mutex_destroy(&psde->lock);
  3756. /* this will destroy the states as well */
  3757. drm_plane_cleanup(plane);
  3758. if (psde->pipe_hw)
  3759. sde_hw_sspp_destroy(psde->pipe_hw);
  3760. kfree(psde);
  3761. }
  3762. }
  3763. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3764. {
  3765. struct sde_plane_state *pstate;
  3766. if (!state) {
  3767. SDE_ERROR("invalid arg state %d\n", !state);
  3768. return;
  3769. }
  3770. pstate = to_sde_plane_state(state);
  3771. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3772. SDE_DRM_FB_SEC) {
  3773. /* remove ref count for frame buffers */
  3774. if (state->fb) {
  3775. drm_framebuffer_put(state->fb);
  3776. state->fb = NULL;
  3777. }
  3778. }
  3779. }
  3780. static void sde_plane_destroy_state(struct drm_plane *plane,
  3781. struct drm_plane_state *state)
  3782. {
  3783. struct sde_plane *psde;
  3784. struct sde_plane_state *pstate;
  3785. if (!plane || !state) {
  3786. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3787. !plane, !state);
  3788. return;
  3789. }
  3790. psde = to_sde_plane(plane);
  3791. pstate = to_sde_plane_state(state);
  3792. SDE_DEBUG_PLANE(psde, "\n");
  3793. /* remove ref count for frame buffers */
  3794. if (state->fb)
  3795. drm_framebuffer_put(state->fb);
  3796. /* remove ref count for fence */
  3797. if (pstate->input_fence)
  3798. sde_sync_put(pstate->input_fence);
  3799. pstate->input_fence = 0;
  3800. /* destroy value helper */
  3801. msm_property_destroy_state(&psde->property_info, pstate,
  3802. &pstate->property_state);
  3803. }
  3804. static struct drm_plane_state *
  3805. sde_plane_duplicate_state(struct drm_plane *plane)
  3806. {
  3807. struct sde_plane *psde;
  3808. struct sde_plane_state *pstate;
  3809. struct sde_plane_state *old_state;
  3810. struct drm_property *drm_prop;
  3811. uint64_t input_fence_default;
  3812. if (!plane) {
  3813. SDE_ERROR("invalid plane\n");
  3814. return NULL;
  3815. } else if (!plane->state) {
  3816. SDE_ERROR("invalid plane state\n");
  3817. return NULL;
  3818. }
  3819. old_state = to_sde_plane_state(plane->state);
  3820. psde = to_sde_plane(plane);
  3821. if (old_state->cont_splash_populated) {
  3822. plane->state->crtc = NULL;
  3823. old_state->cont_splash_populated = false;
  3824. }
  3825. pstate = msm_property_alloc_state(&psde->property_info);
  3826. if (!pstate) {
  3827. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3828. return NULL;
  3829. }
  3830. SDE_DEBUG_PLANE(psde, "\n");
  3831. /* duplicate value helper */
  3832. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3833. &pstate->property_state, pstate->property_values);
  3834. /* clear out any input fence */
  3835. pstate->input_fence = 0;
  3836. input_fence_default = msm_property_get_default(
  3837. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3838. drm_prop = msm_property_index_to_drm_property(
  3839. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3840. if (msm_property_atomic_set(&psde->property_info,
  3841. &pstate->property_state, drm_prop,
  3842. input_fence_default))
  3843. SDE_DEBUG_PLANE(psde,
  3844. "error clearing duplicated input fence\n");
  3845. pstate->dirty = 0x0;
  3846. pstate->pending = false;
  3847. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3848. /* reset layout offset */
  3849. if (pstate->layout_offset) {
  3850. if (pstate->layout_offset > 0)
  3851. pstate->base.crtc_x += pstate->layout_offset;
  3852. pstate->layout = SDE_LAYOUT_NONE;
  3853. pstate->layout_offset = 0;
  3854. }
  3855. return &pstate->base;
  3856. }
  3857. static void sde_plane_reset(struct drm_plane *plane)
  3858. {
  3859. struct sde_plane *psde;
  3860. struct sde_plane_state *pstate;
  3861. if (!plane) {
  3862. SDE_ERROR("invalid plane\n");
  3863. return;
  3864. }
  3865. psde = to_sde_plane(plane);
  3866. SDE_DEBUG_PLANE(psde, "\n");
  3867. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3868. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3869. return;
  3870. }
  3871. /* remove previous state, if present */
  3872. if (plane->state) {
  3873. sde_plane_destroy_state(plane, plane->state);
  3874. plane->state = 0;
  3875. }
  3876. pstate = msm_property_alloc_state(&psde->property_info);
  3877. if (!pstate) {
  3878. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3879. return;
  3880. }
  3881. /* reset value helper */
  3882. msm_property_reset_state(&psde->property_info, pstate,
  3883. &pstate->property_state,
  3884. pstate->property_values);
  3885. pstate->base.plane = plane;
  3886. plane->state = &pstate->base;
  3887. }
  3888. void sde_plane_get_frame_data(struct drm_plane *plane,
  3889. struct sde_drm_plane_frame_data *data)
  3890. {
  3891. struct sde_plane *psde;
  3892. struct sde_plane_state *pstate;
  3893. struct sde_drm_ubwc_stats_data *ubwc_stats;
  3894. if (!plane) {
  3895. SDE_ERROR("invalid plane\n");
  3896. return;
  3897. }
  3898. psde = to_sde_plane(plane);
  3899. pstate = to_sde_plane_state(plane->state);
  3900. ubwc_stats = &data->ubwc_stats;
  3901. data->plane_id = DRMID(plane);
  3902. if (psde->pipe_hw->ops.get_ubwc_stats_data) {
  3903. memcpy(&ubwc_stats->roi, &pstate->ubwc_stats_roi,
  3904. sizeof(struct sde_drm_ubwc_stats_roi));
  3905. psde->pipe_hw->ops.get_ubwc_stats_data(psde->pipe_hw,
  3906. pstate->multirect_index, ubwc_stats);
  3907. }
  3908. if (psde->pipe_hw->ops.get_ubwc_error)
  3909. ubwc_stats->error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  3910. pstate->multirect_index);
  3911. if (psde->pipe_hw->ops.clear_ubwc_error && ubwc_stats->error)
  3912. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  3913. if (psde->pipe_hw->ops.get_meta_error)
  3914. ubwc_stats->meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  3915. pstate->multirect_index);
  3916. if (psde->pipe_hw->ops.clear_meta_error && ubwc_stats->meta_error)
  3917. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  3918. if (ubwc_stats->error || ubwc_stats->meta_error) {
  3919. SDE_EVT32(DRMID(plane), ubwc_stats->error, ubwc_stats->meta_error,
  3920. SDE_EVTLOG_ERROR);
  3921. SDE_DEBUG_PLANE(psde, "plane%d ubwc_error %d meta_error %d\n",
  3922. ubwc_stats->error, ubwc_stats->meta_error);
  3923. }
  3924. }
  3925. #if IS_ENABLED(CONFIG_DEBUG_FS)
  3926. static ssize_t _sde_plane_danger_read(struct file *file,
  3927. char __user *buff, size_t count, loff_t *ppos)
  3928. {
  3929. struct sde_kms *kms = file->private_data;
  3930. struct sde_mdss_cfg *cfg = kms->catalog;
  3931. int len = 0;
  3932. char buf[40] = {'\0'};
  3933. if (!cfg)
  3934. return -ENODEV;
  3935. if (*ppos)
  3936. return 0; /* the end */
  3937. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3938. if (len < 0 || len >= sizeof(buf))
  3939. return 0;
  3940. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3941. return -EFAULT;
  3942. *ppos += len; /* increase offset */
  3943. return len;
  3944. }
  3945. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3946. {
  3947. struct drm_plane *plane;
  3948. drm_for_each_plane(plane, kms->dev) {
  3949. if (plane->fb && plane->state) {
  3950. sde_plane_danger_signal_ctrl(plane, enable);
  3951. SDE_DEBUG("plane:%d img:%dx%d ",
  3952. plane->base.id, plane->fb->width,
  3953. plane->fb->height);
  3954. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3955. plane->state->src_x >> 16,
  3956. plane->state->src_y >> 16,
  3957. plane->state->src_w >> 16,
  3958. plane->state->src_h >> 16,
  3959. plane->state->crtc_x, plane->state->crtc_y,
  3960. plane->state->crtc_w, plane->state->crtc_h);
  3961. } else {
  3962. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3963. }
  3964. }
  3965. }
  3966. static ssize_t _sde_plane_danger_write(struct file *file,
  3967. const char __user *user_buf, size_t count, loff_t *ppos)
  3968. {
  3969. struct sde_kms *kms = file->private_data;
  3970. struct sde_mdss_cfg *cfg = kms->catalog;
  3971. int disable_panic;
  3972. char buf[10];
  3973. if (!cfg)
  3974. return -EFAULT;
  3975. if (count >= sizeof(buf))
  3976. return -EFAULT;
  3977. if (copy_from_user(buf, user_buf, count))
  3978. return -EFAULT;
  3979. buf[count] = 0; /* end of string */
  3980. if (kstrtoint(buf, 0, &disable_panic))
  3981. return -EFAULT;
  3982. if (disable_panic) {
  3983. /* Disable panic signal for all active pipes */
  3984. SDE_DEBUG("Disabling danger:\n");
  3985. _sde_plane_set_danger_state(kms, false);
  3986. kms->has_danger_ctrl = false;
  3987. } else {
  3988. /* Enable panic signal for all active pipes */
  3989. SDE_DEBUG("Enabling danger:\n");
  3990. kms->has_danger_ctrl = true;
  3991. _sde_plane_set_danger_state(kms, true);
  3992. }
  3993. return count;
  3994. }
  3995. static const struct file_operations sde_plane_danger_enable = {
  3996. .open = simple_open,
  3997. .read = _sde_plane_danger_read,
  3998. .write = _sde_plane_danger_write,
  3999. };
  4000. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4001. {
  4002. struct sde_plane *psde;
  4003. struct sde_kms *kms;
  4004. struct msm_drm_private *priv;
  4005. const struct sde_sspp_sub_blks *sblk = 0;
  4006. const struct sde_sspp_cfg *cfg = 0;
  4007. if (!plane || !plane->dev) {
  4008. SDE_ERROR("invalid arguments\n");
  4009. return -EINVAL;
  4010. }
  4011. priv = plane->dev->dev_private;
  4012. if (!priv || !priv->kms) {
  4013. SDE_ERROR("invalid KMS reference\n");
  4014. return -EINVAL;
  4015. }
  4016. kms = to_sde_kms(priv->kms);
  4017. psde = to_sde_plane(plane);
  4018. if (psde && psde->pipe_hw)
  4019. cfg = psde->pipe_hw->cap;
  4020. if (cfg)
  4021. sblk = cfg->sblk;
  4022. if (!sblk)
  4023. return 0;
  4024. /* create overall sub-directory for the pipe */
  4025. psde->debugfs_root =
  4026. debugfs_create_dir(psde->pipe_name,
  4027. plane->dev->primary->debugfs_root);
  4028. if (!psde->debugfs_root)
  4029. return -ENOMEM;
  4030. /* don't error check these */
  4031. debugfs_create_x64("features", 0400,
  4032. psde->debugfs_root, &psde->features);
  4033. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  4034. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  4035. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  4036. debugfs_create_bool("default_scaling",
  4037. 0600,
  4038. psde->debugfs_root,
  4039. &psde->debugfs_default_scale);
  4040. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  4041. debugfs_create_u32("in_rot_max_downscale_rt_num",
  4042. 0600,
  4043. psde->debugfs_root,
  4044. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  4045. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  4046. 0600,
  4047. psde->debugfs_root,
  4048. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  4049. debugfs_create_u32("in_rot_max_downscale_nrt",
  4050. 0600,
  4051. psde->debugfs_root,
  4052. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  4053. debugfs_create_u32("in_rot_max_height",
  4054. 0600,
  4055. psde->debugfs_root,
  4056. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  4057. }
  4058. debugfs_create_u32("xin_id",
  4059. 0400,
  4060. psde->debugfs_root,
  4061. (u32 *) &cfg->xin_id);
  4062. debugfs_create_x32("creq_vblank",
  4063. 0600,
  4064. psde->debugfs_root,
  4065. (u32 *) &sblk->creq_vblank);
  4066. debugfs_create_x32("danger_vblank",
  4067. 0600,
  4068. psde->debugfs_root,
  4069. (u32 *) &sblk->danger_vblank);
  4070. debugfs_create_file("disable_danger",
  4071. 0600,
  4072. psde->debugfs_root,
  4073. kms, &sde_plane_danger_enable);
  4074. return 0;
  4075. }
  4076. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4077. {
  4078. struct sde_plane *psde;
  4079. if (!plane)
  4080. return;
  4081. psde = to_sde_plane(plane);
  4082. debugfs_remove_recursive(psde->debugfs_root);
  4083. }
  4084. #else
  4085. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4086. {
  4087. return 0;
  4088. }
  4089. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4090. {
  4091. }
  4092. #endif /* CONFIG_DEBUG_FS */
  4093. static int sde_plane_late_register(struct drm_plane *plane)
  4094. {
  4095. return _sde_plane_init_debugfs(plane);
  4096. }
  4097. static void sde_plane_early_unregister(struct drm_plane *plane)
  4098. {
  4099. _sde_plane_destroy_debugfs(plane);
  4100. }
  4101. static const struct drm_plane_funcs sde_plane_funcs = {
  4102. .update_plane = drm_atomic_helper_update_plane,
  4103. .disable_plane = drm_atomic_helper_disable_plane,
  4104. .destroy = sde_plane_destroy,
  4105. .atomic_set_property = sde_plane_atomic_set_property,
  4106. .atomic_get_property = sde_plane_atomic_get_property,
  4107. .reset = sde_plane_reset,
  4108. .atomic_duplicate_state = sde_plane_duplicate_state,
  4109. .atomic_destroy_state = sde_plane_destroy_state,
  4110. .late_register = sde_plane_late_register,
  4111. .early_unregister = sde_plane_early_unregister,
  4112. };
  4113. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  4114. .prepare_fb = sde_plane_prepare_fb,
  4115. .cleanup_fb = sde_plane_cleanup_fb,
  4116. .atomic_check = sde_plane_atomic_check,
  4117. .atomic_update = sde_plane_atomic_update,
  4118. };
  4119. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  4120. {
  4121. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  4122. }
  4123. bool is_sde_plane_virtual(struct drm_plane *plane)
  4124. {
  4125. return plane ? to_sde_plane(plane)->is_virtual : false;
  4126. }
  4127. /* initialize plane */
  4128. struct drm_plane *sde_plane_init(struct drm_device *dev,
  4129. uint32_t pipe, bool primary_plane,
  4130. unsigned long possible_crtcs, u32 master_plane_id)
  4131. {
  4132. struct drm_plane *plane = NULL, *master_plane = NULL;
  4133. const struct sde_format_extended *format_list;
  4134. struct sde_plane *psde;
  4135. struct msm_drm_private *priv;
  4136. struct sde_kms *kms;
  4137. enum drm_plane_type type;
  4138. struct sde_vbif_clk_client clk_client;
  4139. int ret = -EINVAL;
  4140. if (!dev) {
  4141. SDE_ERROR("[%u]device is NULL\n", pipe);
  4142. goto exit;
  4143. }
  4144. priv = dev->dev_private;
  4145. if (!priv) {
  4146. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4147. goto exit;
  4148. }
  4149. if (!priv->kms) {
  4150. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4151. goto exit;
  4152. }
  4153. kms = to_sde_kms(priv->kms);
  4154. if (!kms->catalog) {
  4155. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4156. goto exit;
  4157. }
  4158. /* create and zero local structure */
  4159. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4160. if (!psde) {
  4161. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4162. ret = -ENOMEM;
  4163. goto exit;
  4164. }
  4165. /* cache local stuff for later */
  4166. plane = &psde->base;
  4167. psde->pipe = pipe;
  4168. psde->is_virtual = (master_plane_id != 0);
  4169. INIT_LIST_HEAD(&psde->mplane_list);
  4170. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4171. if (master_plane) {
  4172. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4173. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4174. }
  4175. /* initialize underlying h/w driver */
  4176. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog, psde->is_virtual,
  4177. &clk_client);
  4178. if (IS_ERR(psde->pipe_hw)) {
  4179. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4180. ret = PTR_ERR(psde->pipe_hw);
  4181. goto clean_plane;
  4182. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4183. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4184. goto clean_sspp;
  4185. }
  4186. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, kms->catalog->features)) {
  4187. ret = sde_vbif_clk_register(kms, &clk_client);
  4188. if (ret) {
  4189. SDE_ERROR("failed to register vbif client %d\n",
  4190. clk_client.clk_ctrl);
  4191. goto clean_sspp;
  4192. }
  4193. }
  4194. /* cache features mask for later */
  4195. psde->features = psde->pipe_hw->cap->features_ext;
  4196. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4197. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4198. if (!psde->pipe_sblk) {
  4199. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4200. goto clean_sspp;
  4201. }
  4202. if (psde->is_virtual)
  4203. format_list = psde->pipe_sblk->virt_format_list;
  4204. else
  4205. format_list = psde->pipe_sblk->format_list;
  4206. psde->nformats = sde_populate_formats(format_list,
  4207. psde->formats,
  4208. 0,
  4209. ARRAY_SIZE(psde->formats));
  4210. if (!psde->nformats) {
  4211. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4212. goto clean_sspp;
  4213. }
  4214. if (primary_plane)
  4215. type = DRM_PLANE_TYPE_PRIMARY;
  4216. else
  4217. type = DRM_PLANE_TYPE_OVERLAY;
  4218. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4219. psde->formats, psde->nformats,
  4220. NULL, type, NULL);
  4221. if (ret)
  4222. goto clean_sspp;
  4223. /* Populate static array of plane property flags */
  4224. _sde_plane_map_prop_to_dirty_bits();
  4225. /* success! finalize initialization */
  4226. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4227. msm_property_init(&psde->property_info, &plane->base, dev,
  4228. priv->plane_property, psde->property_data,
  4229. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4230. sizeof(struct sde_plane_state));
  4231. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4232. /* save user friendly pipe name for later */
  4233. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4234. mutex_init(&psde->lock);
  4235. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4236. pipe, plane->base.id, master_plane_id);
  4237. return plane;
  4238. clean_sspp:
  4239. if (psde && psde->pipe_hw)
  4240. sde_hw_sspp_destroy(psde->pipe_hw);
  4241. clean_plane:
  4242. kfree(psde);
  4243. exit:
  4244. return ERR_PTR(ret);
  4245. }
  4246. void sde_plane_add_data_to_minidump_va(struct drm_plane *plane)
  4247. {
  4248. struct sde_plane *sde_plane;
  4249. struct sde_plane_state *pstate;
  4250. sde_plane = to_sde_plane(plane);
  4251. pstate = to_sde_plane_state(plane->state);
  4252. sde_mini_dump_add_va_region("sde_plane", sizeof(*sde_plane), sde_plane);
  4253. sde_mini_dump_add_va_region("plane_state", sizeof(*pstate), pstate);
  4254. }