bus.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include "bus.h"
  7. #include "debug.h"
  8. #include "pci.h"
  9. enum cnss_dev_bus_type cnss_get_dev_bus_type(struct device *dev)
  10. {
  11. if (!dev)
  12. return CNSS_BUS_NONE;
  13. if (!dev->bus)
  14. return CNSS_BUS_NONE;
  15. if (memcmp(dev->bus->name, "pci", 3) == 0)
  16. return CNSS_BUS_PCI;
  17. else
  18. return CNSS_BUS_NONE;
  19. }
  20. enum cnss_dev_bus_type cnss_get_bus_type(struct cnss_plat_data *plat_priv)
  21. {
  22. int ret;
  23. struct device *dev;
  24. u32 bus_type_dt = CNSS_BUS_NONE;
  25. if (plat_priv->dt_type == CNSS_DTT_MULTIEXCHG) {
  26. dev = &plat_priv->plat_dev->dev;
  27. ret = of_property_read_u32(dev->of_node, "qcom,bus-type",
  28. &bus_type_dt);
  29. if (!ret)
  30. if (bus_type_dt < CNSS_BUS_MAX)
  31. cnss_pr_dbg("Got bus type[%u] from dt\n",
  32. bus_type_dt);
  33. else
  34. bus_type_dt = CNSS_BUS_NONE;
  35. else
  36. cnss_pr_err("No bus type for multi-exchg dt\n");
  37. return bus_type_dt;
  38. }
  39. switch (plat_priv->device_id) {
  40. case QCA6174_DEVICE_ID:
  41. case QCA6290_DEVICE_ID:
  42. case QCA6390_DEVICE_ID:
  43. case QCA6490_DEVICE_ID:
  44. case KIWI_DEVICE_ID:
  45. case MANGO_DEVICE_ID:
  46. return CNSS_BUS_PCI;
  47. default:
  48. cnss_pr_err("Unknown device_id: 0x%lx\n", plat_priv->device_id);
  49. return CNSS_BUS_NONE;
  50. }
  51. }
  52. void *cnss_bus_dev_to_bus_priv(struct device *dev)
  53. {
  54. if (!dev)
  55. return NULL;
  56. switch (cnss_get_dev_bus_type(dev)) {
  57. case CNSS_BUS_PCI:
  58. return cnss_get_pci_priv(to_pci_dev(dev));
  59. default:
  60. return NULL;
  61. }
  62. }
  63. struct cnss_plat_data *cnss_bus_dev_to_plat_priv(struct device *dev)
  64. {
  65. void *bus_priv;
  66. if (!dev)
  67. return cnss_get_plat_priv(NULL);
  68. bus_priv = cnss_bus_dev_to_bus_priv(dev);
  69. if (!bus_priv)
  70. return NULL;
  71. switch (cnss_get_dev_bus_type(dev)) {
  72. case CNSS_BUS_PCI:
  73. return cnss_pci_priv_to_plat_priv(bus_priv);
  74. default:
  75. return NULL;
  76. }
  77. }
  78. int cnss_bus_init(struct cnss_plat_data *plat_priv)
  79. {
  80. if (!plat_priv)
  81. return -ENODEV;
  82. switch (plat_priv->bus_type) {
  83. case CNSS_BUS_PCI:
  84. return cnss_pci_init(plat_priv);
  85. default:
  86. cnss_pr_err("Unsupported bus type: %d\n",
  87. plat_priv->bus_type);
  88. return -EINVAL;
  89. }
  90. }
  91. void cnss_bus_deinit(struct cnss_plat_data *plat_priv)
  92. {
  93. if (!plat_priv)
  94. return;
  95. switch (plat_priv->bus_type) {
  96. case CNSS_BUS_PCI:
  97. return cnss_pci_deinit(plat_priv);
  98. default:
  99. cnss_pr_err("Unsupported bus type: %d\n",
  100. plat_priv->bus_type);
  101. return;
  102. }
  103. }
  104. void cnss_bus_add_fw_prefix_name(struct cnss_plat_data *plat_priv,
  105. char *prefix_name, char *name)
  106. {
  107. if (!plat_priv)
  108. return;
  109. switch (plat_priv->bus_type) {
  110. case CNSS_BUS_PCI:
  111. return cnss_pci_add_fw_prefix_name(plat_priv->bus_priv,
  112. prefix_name, name);
  113. default:
  114. cnss_pr_err("Unsupported bus type: %d\n",
  115. plat_priv->bus_type);
  116. return;
  117. }
  118. }
  119. int cnss_bus_load_m3(struct cnss_plat_data *plat_priv)
  120. {
  121. if (!plat_priv)
  122. return -ENODEV;
  123. switch (plat_priv->bus_type) {
  124. case CNSS_BUS_PCI:
  125. return cnss_pci_load_m3(plat_priv->bus_priv);
  126. default:
  127. cnss_pr_err("Unsupported bus type: %d\n",
  128. plat_priv->bus_type);
  129. return -EINVAL;
  130. }
  131. }
  132. int cnss_bus_handle_dev_sol_irq(struct cnss_plat_data *plat_priv)
  133. {
  134. if (!plat_priv)
  135. return -ENODEV;
  136. switch (plat_priv->bus_type) {
  137. case CNSS_BUS_PCI:
  138. return cnss_pci_handle_dev_sol_irq(plat_priv->bus_priv);
  139. default:
  140. cnss_pr_err("Unsupported bus type: %d\n",
  141. plat_priv->bus_type);
  142. return -EINVAL;
  143. }
  144. }
  145. int cnss_bus_alloc_fw_mem(struct cnss_plat_data *plat_priv)
  146. {
  147. if (!plat_priv)
  148. return -ENODEV;
  149. switch (plat_priv->bus_type) {
  150. case CNSS_BUS_PCI:
  151. return cnss_pci_alloc_fw_mem(plat_priv->bus_priv);
  152. default:
  153. cnss_pr_err("Unsupported bus type: %d\n",
  154. plat_priv->bus_type);
  155. return -EINVAL;
  156. }
  157. }
  158. int cnss_bus_alloc_qdss_mem(struct cnss_plat_data *plat_priv)
  159. {
  160. if (!plat_priv)
  161. return -ENODEV;
  162. switch (plat_priv->bus_type) {
  163. case CNSS_BUS_PCI:
  164. return cnss_pci_alloc_qdss_mem(plat_priv->bus_priv);
  165. default:
  166. cnss_pr_err("Unsupported bus type: %d\n",
  167. plat_priv->bus_type);
  168. return -EINVAL;
  169. }
  170. }
  171. void cnss_bus_free_qdss_mem(struct cnss_plat_data *plat_priv)
  172. {
  173. if (!plat_priv)
  174. return;
  175. switch (plat_priv->bus_type) {
  176. case CNSS_BUS_PCI:
  177. cnss_pci_free_qdss_mem(plat_priv->bus_priv);
  178. return;
  179. default:
  180. cnss_pr_err("Unsupported bus type: %d\n",
  181. plat_priv->bus_type);
  182. return;
  183. }
  184. }
  185. u32 cnss_bus_get_wake_irq(struct cnss_plat_data *plat_priv)
  186. {
  187. if (!plat_priv)
  188. return -ENODEV;
  189. switch (plat_priv->bus_type) {
  190. case CNSS_BUS_PCI:
  191. return cnss_pci_get_wake_msi(plat_priv->bus_priv);
  192. default:
  193. cnss_pr_err("Unsupported bus type: %d\n",
  194. plat_priv->bus_type);
  195. return -EINVAL;
  196. }
  197. }
  198. int cnss_bus_force_fw_assert_hdlr(struct cnss_plat_data *plat_priv)
  199. {
  200. if (!plat_priv)
  201. return -ENODEV;
  202. switch (plat_priv->bus_type) {
  203. case CNSS_BUS_PCI:
  204. return cnss_pci_force_fw_assert_hdlr(plat_priv->bus_priv);
  205. default:
  206. cnss_pr_err("Unsupported bus type: %d\n",
  207. plat_priv->bus_type);
  208. return -EINVAL;
  209. }
  210. }
  211. int cnss_bus_qmi_send_get(struct cnss_plat_data *plat_priv)
  212. {
  213. if (!plat_priv)
  214. return -ENODEV;
  215. switch (plat_priv->bus_type) {
  216. case CNSS_BUS_PCI:
  217. return cnss_pci_qmi_send_get(plat_priv->bus_priv);
  218. default:
  219. cnss_pr_err("Unsupported bus type: %d\n",
  220. plat_priv->bus_type);
  221. return -EINVAL;
  222. }
  223. }
  224. int cnss_bus_qmi_send_put(struct cnss_plat_data *plat_priv)
  225. {
  226. if (!plat_priv)
  227. return -ENODEV;
  228. switch (plat_priv->bus_type) {
  229. case CNSS_BUS_PCI:
  230. return cnss_pci_qmi_send_put(plat_priv->bus_priv);
  231. default:
  232. cnss_pr_err("Unsupported bus type: %d\n",
  233. plat_priv->bus_type);
  234. return -EINVAL;
  235. }
  236. }
  237. void cnss_bus_fw_boot_timeout_hdlr(struct timer_list *t)
  238. {
  239. struct cnss_plat_data *plat_priv =
  240. from_timer(plat_priv, t, fw_boot_timer);
  241. if (!plat_priv)
  242. return;
  243. switch (plat_priv->bus_type) {
  244. case CNSS_BUS_PCI:
  245. return cnss_pci_fw_boot_timeout_hdlr(plat_priv->bus_priv);
  246. default:
  247. cnss_pr_err("Unsupported bus type: %d\n",
  248. plat_priv->bus_type);
  249. return;
  250. }
  251. }
  252. void cnss_bus_collect_dump_info(struct cnss_plat_data *plat_priv, bool in_panic)
  253. {
  254. if (!plat_priv)
  255. return;
  256. switch (plat_priv->bus_type) {
  257. case CNSS_BUS_PCI:
  258. return cnss_pci_collect_dump_info(plat_priv->bus_priv,
  259. in_panic);
  260. default:
  261. cnss_pr_err("Unsupported bus type: %d\n",
  262. plat_priv->bus_type);
  263. return;
  264. }
  265. }
  266. void cnss_bus_device_crashed(struct cnss_plat_data *plat_priv)
  267. {
  268. if (!plat_priv)
  269. return;
  270. switch (plat_priv->bus_type) {
  271. case CNSS_BUS_PCI:
  272. return cnss_pci_device_crashed(plat_priv->bus_priv);
  273. default:
  274. cnss_pr_err("Unsupported bus type: %d\n",
  275. plat_priv->bus_type);
  276. return;
  277. }
  278. }
  279. int cnss_bus_call_driver_probe(struct cnss_plat_data *plat_priv)
  280. {
  281. if (!plat_priv)
  282. return -ENODEV;
  283. switch (plat_priv->bus_type) {
  284. case CNSS_BUS_PCI:
  285. return cnss_pci_call_driver_probe(plat_priv->bus_priv);
  286. default:
  287. cnss_pr_err("Unsupported bus type: %d\n",
  288. plat_priv->bus_type);
  289. return -EINVAL;
  290. }
  291. }
  292. int cnss_bus_call_driver_remove(struct cnss_plat_data *plat_priv)
  293. {
  294. if (!plat_priv)
  295. return -ENODEV;
  296. switch (plat_priv->bus_type) {
  297. case CNSS_BUS_PCI:
  298. return cnss_pci_call_driver_remove(plat_priv->bus_priv);
  299. default:
  300. cnss_pr_err("Unsupported bus type: %d\n",
  301. plat_priv->bus_type);
  302. return -EINVAL;
  303. }
  304. }
  305. int cnss_bus_dev_powerup(struct cnss_plat_data *plat_priv)
  306. {
  307. if (!plat_priv)
  308. return -ENODEV;
  309. switch (plat_priv->bus_type) {
  310. case CNSS_BUS_PCI:
  311. return cnss_pci_dev_powerup(plat_priv->bus_priv);
  312. default:
  313. cnss_pr_err("Unsupported bus type: %d\n",
  314. plat_priv->bus_type);
  315. return -EINVAL;
  316. }
  317. }
  318. int cnss_bus_dev_shutdown(struct cnss_plat_data *plat_priv)
  319. {
  320. if (!plat_priv)
  321. return -ENODEV;
  322. switch (plat_priv->bus_type) {
  323. case CNSS_BUS_PCI:
  324. return cnss_pci_dev_shutdown(plat_priv->bus_priv);
  325. default:
  326. cnss_pr_err("Unsupported bus type: %d\n",
  327. plat_priv->bus_type);
  328. return -EINVAL;
  329. }
  330. }
  331. int cnss_bus_dev_crash_shutdown(struct cnss_plat_data *plat_priv)
  332. {
  333. if (!plat_priv)
  334. return -ENODEV;
  335. switch (plat_priv->bus_type) {
  336. case CNSS_BUS_PCI:
  337. return cnss_pci_dev_crash_shutdown(plat_priv->bus_priv);
  338. default:
  339. cnss_pr_err("Unsupported bus type: %d\n",
  340. plat_priv->bus_type);
  341. return -EINVAL;
  342. }
  343. }
  344. int cnss_bus_dev_ramdump(struct cnss_plat_data *plat_priv)
  345. {
  346. if (!plat_priv)
  347. return -ENODEV;
  348. switch (plat_priv->bus_type) {
  349. case CNSS_BUS_PCI:
  350. return cnss_pci_dev_ramdump(plat_priv->bus_priv);
  351. default:
  352. cnss_pr_err("Unsupported bus type: %d\n",
  353. plat_priv->bus_type);
  354. return -EINVAL;
  355. }
  356. }
  357. int cnss_bus_register_driver_hdlr(struct cnss_plat_data *plat_priv, void *data)
  358. {
  359. if (!plat_priv)
  360. return -ENODEV;
  361. switch (plat_priv->bus_type) {
  362. case CNSS_BUS_PCI:
  363. return cnss_pci_register_driver_hdlr(plat_priv->bus_priv, data);
  364. default:
  365. cnss_pr_err("Unsupported bus type: %d\n",
  366. plat_priv->bus_type);
  367. return -EINVAL;
  368. }
  369. }
  370. int cnss_bus_unregister_driver_hdlr(struct cnss_plat_data *plat_priv)
  371. {
  372. if (!plat_priv)
  373. return -ENODEV;
  374. switch (plat_priv->bus_type) {
  375. case CNSS_BUS_PCI:
  376. return cnss_pci_unregister_driver_hdlr(plat_priv->bus_priv);
  377. default:
  378. cnss_pr_err("Unsupported bus type: %d\n",
  379. plat_priv->bus_type);
  380. return -EINVAL;
  381. }
  382. }
  383. int cnss_bus_call_driver_modem_status(struct cnss_plat_data *plat_priv,
  384. int modem_current_status)
  385. {
  386. if (!plat_priv)
  387. return -ENODEV;
  388. switch (plat_priv->bus_type) {
  389. case CNSS_BUS_PCI:
  390. return cnss_pci_call_driver_modem_status(plat_priv->bus_priv,
  391. modem_current_status);
  392. default:
  393. cnss_pr_err("Unsupported bus type: %d\n",
  394. plat_priv->bus_type);
  395. return -EINVAL;
  396. }
  397. }
  398. int cnss_bus_update_status(struct cnss_plat_data *plat_priv,
  399. enum cnss_driver_status status)
  400. {
  401. if (!plat_priv)
  402. return -ENODEV;
  403. switch (plat_priv->bus_type) {
  404. case CNSS_BUS_PCI:
  405. return cnss_pci_update_status(plat_priv->bus_priv, status);
  406. default:
  407. cnss_pr_err("Unsupported bus type: %d\n",
  408. plat_priv->bus_type);
  409. return -EINVAL;
  410. }
  411. }
  412. int cnss_bus_update_uevent(struct cnss_plat_data *plat_priv,
  413. enum cnss_driver_status status, void *data)
  414. {
  415. if (!plat_priv)
  416. return -ENODEV;
  417. switch (plat_priv->bus_type) {
  418. case CNSS_BUS_PCI:
  419. return cnss_pci_call_driver_uevent(plat_priv->bus_priv,
  420. status, data);
  421. default:
  422. cnss_pr_err("Unsupported bus type: %d\n",
  423. plat_priv->bus_type);
  424. return -EINVAL;
  425. }
  426. }
  427. int cnss_bus_is_device_down(struct cnss_plat_data *plat_priv)
  428. {
  429. if (!plat_priv)
  430. return -ENODEV;
  431. switch (plat_priv->bus_type) {
  432. case CNSS_BUS_PCI:
  433. return cnss_pcie_is_device_down(plat_priv->bus_priv);
  434. default:
  435. cnss_pr_dbg("Unsupported bus type: %d\n",
  436. plat_priv->bus_type);
  437. return 0;
  438. }
  439. }
  440. int cnss_bus_check_link_status(struct cnss_plat_data *plat_priv)
  441. {
  442. if (!plat_priv)
  443. return -ENODEV;
  444. switch (plat_priv->bus_type) {
  445. case CNSS_BUS_PCI:
  446. return cnss_pci_check_link_status(plat_priv->bus_priv);
  447. default:
  448. cnss_pr_dbg("Unsupported bus type: %d\n",
  449. plat_priv->bus_type);
  450. return 0;
  451. }
  452. }
  453. int cnss_bus_recover_link_down(struct cnss_plat_data *plat_priv)
  454. {
  455. if (!plat_priv)
  456. return -ENODEV;
  457. switch (plat_priv->bus_type) {
  458. case CNSS_BUS_PCI:
  459. return cnss_pci_recover_link_down(plat_priv->bus_priv);
  460. default:
  461. cnss_pr_dbg("Unsupported bus type: %d\n",
  462. plat_priv->bus_type);
  463. return -EINVAL;
  464. }
  465. }
  466. int cnss_bus_debug_reg_read(struct cnss_plat_data *plat_priv, u32 offset,
  467. u32 *val, bool raw_access)
  468. {
  469. if (!plat_priv)
  470. return -ENODEV;
  471. switch (plat_priv->bus_type) {
  472. case CNSS_BUS_PCI:
  473. return cnss_pci_debug_reg_read(plat_priv->bus_priv, offset,
  474. val, raw_access);
  475. default:
  476. cnss_pr_dbg("Unsupported bus type: %d\n",
  477. plat_priv->bus_type);
  478. return 0;
  479. }
  480. }
  481. int cnss_bus_debug_reg_write(struct cnss_plat_data *plat_priv, u32 offset,
  482. u32 val, bool raw_access)
  483. {
  484. if (!plat_priv)
  485. return -ENODEV;
  486. switch (plat_priv->bus_type) {
  487. case CNSS_BUS_PCI:
  488. return cnss_pci_debug_reg_write(plat_priv->bus_priv, offset,
  489. val, raw_access);
  490. default:
  491. cnss_pr_dbg("Unsupported bus type: %d\n",
  492. plat_priv->bus_type);
  493. return 0;
  494. }
  495. }
  496. int cnss_bus_get_iova(struct cnss_plat_data *plat_priv, u64 *addr, u64 *size)
  497. {
  498. if (!plat_priv)
  499. return -ENODEV;
  500. switch (plat_priv->bus_type) {
  501. case CNSS_BUS_PCI:
  502. return cnss_pci_get_iova(plat_priv->bus_priv, addr, size);
  503. default:
  504. cnss_pr_err("Unsupported bus type: %d\n",
  505. plat_priv->bus_type);
  506. return -EINVAL;
  507. }
  508. }
  509. int cnss_bus_get_iova_ipa(struct cnss_plat_data *plat_priv, u64 *addr,
  510. u64 *size)
  511. {
  512. if (!plat_priv)
  513. return -ENODEV;
  514. switch (plat_priv->bus_type) {
  515. case CNSS_BUS_PCI:
  516. return cnss_pci_get_iova_ipa(plat_priv->bus_priv, addr, size);
  517. default:
  518. cnss_pr_err("Unsupported bus type: %d\n",
  519. plat_priv->bus_type);
  520. return -EINVAL;
  521. }
  522. }
  523. bool cnss_bus_is_smmu_s1_enabled(struct cnss_plat_data *plat_priv)
  524. {
  525. if (!plat_priv)
  526. return false;
  527. switch (plat_priv->bus_type) {
  528. case CNSS_BUS_PCI:
  529. return cnss_pci_is_smmu_s1_enabled(plat_priv->bus_priv);
  530. default:
  531. cnss_pr_err("Unsupported bus type: %d\n",
  532. plat_priv->bus_type);
  533. return false;
  534. }
  535. }
  536. int cnss_bus_update_time_sync_period(struct cnss_plat_data *plat_priv,
  537. unsigned int time_sync_period)
  538. {
  539. if (!plat_priv)
  540. return -ENODEV;
  541. switch (plat_priv->bus_type) {
  542. case CNSS_BUS_PCI:
  543. return cnss_pci_update_time_sync_period(plat_priv->bus_priv,
  544. time_sync_period);
  545. default:
  546. cnss_pr_err("Unsupported bus type: %d\n",
  547. plat_priv->bus_type);
  548. return -EINVAL;
  549. }
  550. }
  551. #if IS_ENABLED(CONFIG_MHI_BUS_MISC)
  552. void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *plat_priv)
  553. {
  554. struct cnss_pci_data *pci_priv;
  555. pci_priv = plat_priv->bus_priv;
  556. if (!pci_priv) {
  557. cnss_pr_err("mhi satellite could not be disabled since pci_priv is NULL\n");
  558. return;
  559. }
  560. switch (plat_priv->bus_type) {
  561. case CNSS_BUS_PCI:
  562. /* MHI satellite configuration is only for KIWI V2 and
  563. * that too only in DRV mode.
  564. */
  565. if (plat_priv->device_id == KIWI_DEVICE_ID &&
  566. plat_priv->device_version.major_version == FW_V2_NUMBER) {
  567. cnss_pr_dbg("Remove MHI satellite configuration\n");
  568. return cnss_mhi_controller_set_base(pci_priv, 0);
  569. }
  570. break;
  571. default:
  572. cnss_pr_dbg("Unsupported bus type: %d, ignore disable mhi satellite cfg\n",
  573. plat_priv->bus_type);
  574. return;
  575. }
  576. return;
  577. }
  578. #else
  579. void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *pci_priv)
  580. {
  581. }
  582. #endif