dp_tx.c 114 KB

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  1. /*
  2. * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "enet.h"
  33. #include "dp_internal.h"
  34. #define DP_TX_QUEUE_MASK 0x3
  35. /* TODO Add support in TSO */
  36. #define DP_DESC_NUM_FRAG(x) 0
  37. /* disable TQM_BYPASS */
  38. #define TQM_BYPASS_WAR 0
  39. /* invalid peer id for reinject*/
  40. #define DP_INVALID_PEER 0XFFFE
  41. /*mapping between hal encrypt type and cdp_sec_type*/
  42. #define MAX_CDP_SEC_TYPE 12
  43. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  44. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  45. HAL_TX_ENCRYPT_TYPE_WEP_128,
  46. HAL_TX_ENCRYPT_TYPE_WEP_104,
  47. HAL_TX_ENCRYPT_TYPE_WEP_40,
  48. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  49. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  50. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  51. HAL_TX_ENCRYPT_TYPE_WAPI,
  52. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  53. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  54. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  55. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  56. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  57. #include "dp_tx_capture.h"
  58. #endif
  59. /**
  60. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  61. * @vdev: DP Virtual device handle
  62. * @nbuf: Buffer pointer
  63. * @queue: queue ids container for nbuf
  64. *
  65. * TX packet queue has 2 instances, software descriptors id and dma ring id
  66. * Based on tx feature and hardware configuration queue id combination could be
  67. * different.
  68. * For example -
  69. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  70. * With no XPS,lock based resource protection, Descriptor pool ids are different
  71. * for each vdev, dma ring id will be same as single pdev id
  72. *
  73. * Return: None
  74. */
  75. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  76. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  77. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  78. {
  79. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  80. queue->desc_pool_id = queue_offset;
  81. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  82. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  83. "%s, pool_id:%d ring_id: %d",
  84. __func__, queue->desc_pool_id, queue->ring_id);
  85. return;
  86. }
  87. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  88. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  89. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  90. {
  91. /* get flow id */
  92. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  93. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  94. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  95. "%s, pool_id:%d ring_id: %d",
  96. __func__, queue->desc_pool_id, queue->ring_id);
  97. return;
  98. }
  99. #endif
  100. #if defined(FEATURE_TSO)
  101. /**
  102. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  103. *
  104. * @soc - core txrx main context
  105. * @seg_desc - tso segment descriptor
  106. * @num_seg_desc - tso number segment descriptor
  107. */
  108. static void dp_tx_tso_unmap_segment(
  109. struct dp_soc *soc,
  110. struct qdf_tso_seg_elem_t *seg_desc,
  111. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  112. {
  113. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  114. if (qdf_unlikely(!seg_desc)) {
  115. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  116. __func__, __LINE__);
  117. qdf_assert(0);
  118. } else if (qdf_unlikely(!num_seg_desc)) {
  119. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  120. __func__, __LINE__);
  121. qdf_assert(0);
  122. } else {
  123. bool is_last_seg;
  124. /* no tso segment left to do dma unmap */
  125. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  126. return;
  127. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  128. true : false;
  129. qdf_nbuf_unmap_tso_segment(soc->osdev,
  130. seg_desc, is_last_seg);
  131. num_seg_desc->num_seg.tso_cmn_num_seg--;
  132. }
  133. }
  134. /**
  135. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  136. * back to the freelist
  137. *
  138. * @soc - soc device handle
  139. * @tx_desc - Tx software descriptor
  140. */
  141. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  142. struct dp_tx_desc_s *tx_desc)
  143. {
  144. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  145. if (qdf_unlikely(!tx_desc->tso_desc)) {
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "%s %d TSO desc is NULL!",
  148. __func__, __LINE__);
  149. qdf_assert(0);
  150. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  151. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  152. "%s %d TSO num desc is NULL!",
  153. __func__, __LINE__);
  154. qdf_assert(0);
  155. } else {
  156. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  157. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  158. /* Add the tso num segment into the free list */
  159. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  160. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  161. tx_desc->tso_num_desc);
  162. tx_desc->tso_num_desc = NULL;
  163. }
  164. /* Add the tso segment into the free list*/
  165. dp_tx_tso_desc_free(soc,
  166. tx_desc->pool_id, tx_desc->tso_desc);
  167. tx_desc->tso_desc = NULL;
  168. }
  169. }
  170. #else
  171. static void dp_tx_tso_unmap_segment(
  172. struct dp_soc *soc,
  173. struct qdf_tso_seg_elem_t *seg_desc,
  174. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  175. {
  176. }
  177. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  178. struct dp_tx_desc_s *tx_desc)
  179. {
  180. }
  181. #endif
  182. /**
  183. * dp_tx_desc_release() - Release Tx Descriptor
  184. * @tx_desc : Tx Descriptor
  185. * @desc_pool_id: Descriptor Pool ID
  186. *
  187. * Deallocate all resources attached to Tx descriptor and free the Tx
  188. * descriptor.
  189. *
  190. * Return:
  191. */
  192. static void
  193. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  194. {
  195. struct dp_pdev *pdev = tx_desc->pdev;
  196. struct dp_soc *soc;
  197. uint8_t comp_status = 0;
  198. qdf_assert(pdev);
  199. soc = pdev->soc;
  200. if (tx_desc->frm_type == dp_tx_frm_tso)
  201. dp_tx_tso_desc_release(soc, tx_desc);
  202. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  203. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  204. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  205. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  206. qdf_atomic_dec(&pdev->num_tx_outstanding);
  207. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  208. qdf_atomic_dec(&pdev->num_tx_exception);
  209. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  210. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  211. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  212. soc->hal_soc);
  213. else
  214. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  215. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  216. "Tx Completion Release desc %d status %d outstanding %d",
  217. tx_desc->id, comp_status,
  218. qdf_atomic_read(&pdev->num_tx_outstanding));
  219. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  220. return;
  221. }
  222. /**
  223. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  224. * @vdev: DP vdev Handle
  225. * @nbuf: skb
  226. *
  227. * Prepares and fills HTT metadata in the frame pre-header for special frames
  228. * that should be transmitted using varying transmit parameters.
  229. * There are 2 VDEV modes that currently needs this special metadata -
  230. * 1) Mesh Mode
  231. * 2) DSRC Mode
  232. *
  233. * Return: HTT metadata size
  234. *
  235. */
  236. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  237. uint32_t *meta_data)
  238. {
  239. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  240. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  241. uint8_t htt_desc_size;
  242. /* Size rounded of multiple of 8 bytes */
  243. uint8_t htt_desc_size_aligned;
  244. uint8_t *hdr = NULL;
  245. /*
  246. * Metadata - HTT MSDU Extension header
  247. */
  248. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  249. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  250. if (vdev->mesh_vdev) {
  251. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  252. htt_desc_size_aligned)) {
  253. DP_STATS_INC(vdev,
  254. tx_i.dropped.headroom_insufficient, 1);
  255. return 0;
  256. }
  257. /* Fill and add HTT metaheader */
  258. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  259. if (!hdr) {
  260. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  261. "Error in filling HTT metadata");
  262. return 0;
  263. }
  264. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  265. } else if (vdev->opmode == wlan_op_mode_ocb) {
  266. /* Todo - Add support for DSRC */
  267. }
  268. return htt_desc_size_aligned;
  269. }
  270. /**
  271. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  272. * @tso_seg: TSO segment to process
  273. * @ext_desc: Pointer to MSDU extension descriptor
  274. *
  275. * Return: void
  276. */
  277. #if defined(FEATURE_TSO)
  278. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  279. void *ext_desc)
  280. {
  281. uint8_t num_frag;
  282. uint32_t tso_flags;
  283. /*
  284. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  285. * tcp_flag_mask
  286. *
  287. * Checksum enable flags are set in TCL descriptor and not in Extension
  288. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  289. */
  290. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  291. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  292. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  293. tso_seg->tso_flags.ip_len);
  294. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  295. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  296. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  297. uint32_t lo = 0;
  298. uint32_t hi = 0;
  299. qdf_dmaaddr_to_32s(
  300. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  301. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  302. tso_seg->tso_frags[num_frag].length);
  303. }
  304. return;
  305. }
  306. #else
  307. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  308. void *ext_desc)
  309. {
  310. return;
  311. }
  312. #endif
  313. #if defined(FEATURE_TSO)
  314. /**
  315. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  316. * allocated and free them
  317. *
  318. * @soc: soc handle
  319. * @free_seg: list of tso segments
  320. * @msdu_info: msdu descriptor
  321. *
  322. * Return - void
  323. */
  324. static void dp_tx_free_tso_seg_list(
  325. struct dp_soc *soc,
  326. struct qdf_tso_seg_elem_t *free_seg,
  327. struct dp_tx_msdu_info_s *msdu_info)
  328. {
  329. struct qdf_tso_seg_elem_t *next_seg;
  330. while (free_seg) {
  331. next_seg = free_seg->next;
  332. dp_tx_tso_desc_free(soc,
  333. msdu_info->tx_queue.desc_pool_id,
  334. free_seg);
  335. free_seg = next_seg;
  336. }
  337. }
  338. /**
  339. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  340. * allocated and free them
  341. *
  342. * @soc: soc handle
  343. * @free_num_seg: list of tso number segments
  344. * @msdu_info: msdu descriptor
  345. * Return - void
  346. */
  347. static void dp_tx_free_tso_num_seg_list(
  348. struct dp_soc *soc,
  349. struct qdf_tso_num_seg_elem_t *free_num_seg,
  350. struct dp_tx_msdu_info_s *msdu_info)
  351. {
  352. struct qdf_tso_num_seg_elem_t *next_num_seg;
  353. while (free_num_seg) {
  354. next_num_seg = free_num_seg->next;
  355. dp_tso_num_seg_free(soc,
  356. msdu_info->tx_queue.desc_pool_id,
  357. free_num_seg);
  358. free_num_seg = next_num_seg;
  359. }
  360. }
  361. /**
  362. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  363. * do dma unmap for each segment
  364. *
  365. * @soc: soc handle
  366. * @free_seg: list of tso segments
  367. * @num_seg_desc: tso number segment descriptor
  368. *
  369. * Return - void
  370. */
  371. static void dp_tx_unmap_tso_seg_list(
  372. struct dp_soc *soc,
  373. struct qdf_tso_seg_elem_t *free_seg,
  374. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  375. {
  376. struct qdf_tso_seg_elem_t *next_seg;
  377. if (qdf_unlikely(!num_seg_desc)) {
  378. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  379. return;
  380. }
  381. while (free_seg) {
  382. next_seg = free_seg->next;
  383. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  384. free_seg = next_seg;
  385. }
  386. }
  387. /**
  388. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  389. * free the tso segments descriptor and
  390. * tso num segments descriptor
  391. *
  392. * @soc: soc handle
  393. * @msdu_info: msdu descriptor
  394. * @tso_seg_unmap: flag to show if dma unmap is necessary
  395. *
  396. * Return - void
  397. */
  398. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  399. struct dp_tx_msdu_info_s *msdu_info,
  400. bool tso_seg_unmap)
  401. {
  402. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  403. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  404. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  405. tso_info->tso_num_seg_list;
  406. /* do dma unmap for each segment */
  407. if (tso_seg_unmap)
  408. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  409. /* free all tso number segment descriptor though looks only have 1 */
  410. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  411. /* free all tso segment descriptor */
  412. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  413. }
  414. /**
  415. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  416. * @vdev: virtual device handle
  417. * @msdu: network buffer
  418. * @msdu_info: meta data associated with the msdu
  419. *
  420. * Return: QDF_STATUS_SUCCESS success
  421. */
  422. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  423. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  424. {
  425. struct qdf_tso_seg_elem_t *tso_seg;
  426. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  427. struct dp_soc *soc = vdev->pdev->soc;
  428. struct qdf_tso_info_t *tso_info;
  429. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  430. tso_info = &msdu_info->u.tso_info;
  431. tso_info->curr_seg = NULL;
  432. tso_info->tso_seg_list = NULL;
  433. tso_info->num_segs = num_seg;
  434. msdu_info->frm_type = dp_tx_frm_tso;
  435. tso_info->tso_num_seg_list = NULL;
  436. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  437. while (num_seg) {
  438. tso_seg = dp_tx_tso_desc_alloc(
  439. soc, msdu_info->tx_queue.desc_pool_id);
  440. if (tso_seg) {
  441. tso_seg->next = tso_info->tso_seg_list;
  442. tso_info->tso_seg_list = tso_seg;
  443. num_seg--;
  444. } else {
  445. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  446. __func__);
  447. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  448. return QDF_STATUS_E_NOMEM;
  449. }
  450. }
  451. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  452. tso_num_seg = dp_tso_num_seg_alloc(soc,
  453. msdu_info->tx_queue.desc_pool_id);
  454. if (tso_num_seg) {
  455. tso_num_seg->next = tso_info->tso_num_seg_list;
  456. tso_info->tso_num_seg_list = tso_num_seg;
  457. } else {
  458. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  459. __func__);
  460. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  461. return QDF_STATUS_E_NOMEM;
  462. }
  463. msdu_info->num_seg =
  464. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  465. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  466. msdu_info->num_seg);
  467. if (!(msdu_info->num_seg)) {
  468. /*
  469. * Free allocated TSO seg desc and number seg desc,
  470. * do unmap for segments if dma map has done.
  471. */
  472. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  473. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  474. return QDF_STATUS_E_INVAL;
  475. }
  476. tso_info->curr_seg = tso_info->tso_seg_list;
  477. return QDF_STATUS_SUCCESS;
  478. }
  479. #else
  480. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  481. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  482. {
  483. return QDF_STATUS_E_NOMEM;
  484. }
  485. #endif
  486. /**
  487. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  488. * @vdev: DP Vdev handle
  489. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  490. * @desc_pool_id: Descriptor Pool ID
  491. *
  492. * Return:
  493. */
  494. static
  495. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  496. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  497. {
  498. uint8_t i;
  499. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  500. struct dp_tx_seg_info_s *seg_info;
  501. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  502. struct dp_soc *soc = vdev->pdev->soc;
  503. /* Allocate an extension descriptor */
  504. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  505. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  506. if (!msdu_ext_desc) {
  507. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  508. return NULL;
  509. }
  510. if (msdu_info->exception_fw &&
  511. qdf_unlikely(vdev->mesh_vdev)) {
  512. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  513. &msdu_info->meta_data[0],
  514. sizeof(struct htt_tx_msdu_desc_ext2_t));
  515. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  516. }
  517. switch (msdu_info->frm_type) {
  518. case dp_tx_frm_sg:
  519. case dp_tx_frm_me:
  520. case dp_tx_frm_raw:
  521. seg_info = msdu_info->u.sg_info.curr_seg;
  522. /* Update the buffer pointers in MSDU Extension Descriptor */
  523. for (i = 0; i < seg_info->frag_cnt; i++) {
  524. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  525. seg_info->frags[i].paddr_lo,
  526. seg_info->frags[i].paddr_hi,
  527. seg_info->frags[i].len);
  528. }
  529. break;
  530. case dp_tx_frm_tso:
  531. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  532. &cached_ext_desc[0]);
  533. break;
  534. default:
  535. break;
  536. }
  537. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  538. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  539. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  540. msdu_ext_desc->vaddr);
  541. return msdu_ext_desc;
  542. }
  543. /**
  544. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  545. *
  546. * @skb: skb to be traced
  547. * @msdu_id: msdu_id of the packet
  548. * @vdev_id: vdev_id of the packet
  549. *
  550. * Return: None
  551. */
  552. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  553. uint8_t vdev_id)
  554. {
  555. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  556. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  557. DPTRACE(qdf_dp_trace_ptr(skb,
  558. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  559. QDF_TRACE_DEFAULT_PDEV_ID,
  560. qdf_nbuf_data_addr(skb),
  561. sizeof(qdf_nbuf_data(skb)),
  562. msdu_id, vdev_id));
  563. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  564. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  565. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  566. msdu_id, QDF_TX));
  567. }
  568. #ifdef QCA_512M_CONFIG
  569. /**
  570. * dp_tx_pdev_pflow_control - Check if allocated tx descriptors reached max
  571. * tx descriptor configured value
  572. * @vdev: DP vdev handle
  573. *
  574. * Return: true if allocated tx descriptors reached max configured value, else
  575. * false.
  576. */
  577. static inline bool
  578. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  579. {
  580. struct dp_pdev *pdev = vdev->pdev;
  581. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  582. pdev->num_tx_allowed) {
  583. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  584. "%s: queued packets are more than max tx, drop the frame",
  585. __func__);
  586. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  587. return true;
  588. }
  589. return false;
  590. }
  591. #else
  592. static inline bool
  593. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  594. {
  595. return false;
  596. }
  597. #endif
  598. /**
  599. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  600. * @vdev: DP vdev handle
  601. * @nbuf: skb
  602. * @desc_pool_id: Descriptor pool ID
  603. * @meta_data: Metadata to the fw
  604. * @tx_exc_metadata: Handle that holds exception path metadata
  605. * Allocate and prepare Tx descriptor with msdu information.
  606. *
  607. * Return: Pointer to Tx Descriptor on success,
  608. * NULL on failure
  609. */
  610. static
  611. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  612. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  613. struct dp_tx_msdu_info_s *msdu_info,
  614. struct cdp_tx_exception_metadata *tx_exc_metadata)
  615. {
  616. uint8_t align_pad;
  617. uint8_t is_exception = 0;
  618. uint8_t htt_hdr_size;
  619. qdf_ether_header_t *eh;
  620. struct dp_tx_desc_s *tx_desc;
  621. struct dp_pdev *pdev = vdev->pdev;
  622. struct dp_soc *soc = pdev->soc;
  623. if (dp_tx_pdev_pflow_control(vdev))
  624. return NULL;
  625. /* Allocate software Tx descriptor */
  626. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  627. if (qdf_unlikely(!tx_desc)) {
  628. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  629. return NULL;
  630. }
  631. /* Flow control/Congestion Control counters */
  632. qdf_atomic_inc(&pdev->num_tx_outstanding);
  633. /* Initialize the SW tx descriptor */
  634. tx_desc->nbuf = nbuf;
  635. tx_desc->frm_type = dp_tx_frm_std;
  636. tx_desc->tx_encap_type = (tx_exc_metadata ?
  637. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  638. tx_desc->vdev = vdev;
  639. tx_desc->pdev = pdev;
  640. tx_desc->msdu_ext_desc = NULL;
  641. tx_desc->pkt_offset = 0;
  642. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  643. /*
  644. * For special modes (vdev_type == ocb or mesh), data frames should be
  645. * transmitted using varying transmit parameters (tx spec) which include
  646. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  647. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  648. * These frames are sent as exception packets to firmware.
  649. *
  650. * HW requirement is that metadata should always point to a
  651. * 8-byte aligned address. So we add alignment pad to start of buffer.
  652. * HTT Metadata should be ensured to be multiple of 8-bytes,
  653. * to get 8-byte aligned start address along with align_pad added
  654. *
  655. * |-----------------------------|
  656. * | |
  657. * |-----------------------------| <-----Buffer Pointer Address given
  658. * | | ^ in HW descriptor (aligned)
  659. * | HTT Metadata | |
  660. * | | |
  661. * | | | Packet Offset given in descriptor
  662. * | | |
  663. * |-----------------------------| |
  664. * | Alignment Pad | v
  665. * |-----------------------------| <----- Actual buffer start address
  666. * | SKB Data | (Unaligned)
  667. * | |
  668. * | |
  669. * | |
  670. * | |
  671. * | |
  672. * |-----------------------------|
  673. */
  674. if (qdf_unlikely((msdu_info->exception_fw)) ||
  675. (vdev->opmode == wlan_op_mode_ocb)) {
  676. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  677. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  678. DP_STATS_INC(vdev,
  679. tx_i.dropped.headroom_insufficient, 1);
  680. goto failure;
  681. }
  682. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  683. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  684. "qdf_nbuf_push_head failed");
  685. goto failure;
  686. }
  687. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  688. msdu_info->meta_data);
  689. if (htt_hdr_size == 0)
  690. goto failure;
  691. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  692. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  693. is_exception = 1;
  694. }
  695. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  696. qdf_nbuf_map(soc->osdev, nbuf,
  697. QDF_DMA_TO_DEVICE))) {
  698. /* Handle failure */
  699. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  700. "qdf_nbuf_map failed");
  701. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  702. goto failure;
  703. }
  704. if (qdf_unlikely(vdev->nawds_enabled)) {
  705. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  706. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  707. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  708. is_exception = 1;
  709. }
  710. }
  711. #if !TQM_BYPASS_WAR
  712. if (is_exception || tx_exc_metadata)
  713. #endif
  714. {
  715. /* Temporary WAR due to TQM VP issues */
  716. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  717. qdf_atomic_inc(&pdev->num_tx_exception);
  718. }
  719. return tx_desc;
  720. failure:
  721. dp_tx_desc_release(tx_desc, desc_pool_id);
  722. return NULL;
  723. }
  724. /**
  725. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  726. * @vdev: DP vdev handle
  727. * @nbuf: skb
  728. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  729. * @desc_pool_id : Descriptor Pool ID
  730. *
  731. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  732. * information. For frames wth fragments, allocate and prepare
  733. * an MSDU extension descriptor
  734. *
  735. * Return: Pointer to Tx Descriptor on success,
  736. * NULL on failure
  737. */
  738. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  739. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  740. uint8_t desc_pool_id)
  741. {
  742. struct dp_tx_desc_s *tx_desc;
  743. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  744. struct dp_pdev *pdev = vdev->pdev;
  745. struct dp_soc *soc = pdev->soc;
  746. if (dp_tx_pdev_pflow_control(vdev))
  747. return NULL;
  748. /* Allocate software Tx descriptor */
  749. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  750. if (!tx_desc) {
  751. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  752. return NULL;
  753. }
  754. /* Flow control/Congestion Control counters */
  755. qdf_atomic_inc(&pdev->num_tx_outstanding);
  756. /* Initialize the SW tx descriptor */
  757. tx_desc->nbuf = nbuf;
  758. tx_desc->frm_type = msdu_info->frm_type;
  759. tx_desc->tx_encap_type = vdev->tx_encap_type;
  760. tx_desc->vdev = vdev;
  761. tx_desc->pdev = pdev;
  762. tx_desc->pkt_offset = 0;
  763. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  764. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  765. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  766. /* Handle scattered frames - TSO/SG/ME */
  767. /* Allocate and prepare an extension descriptor for scattered frames */
  768. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  769. if (!msdu_ext_desc) {
  770. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  771. "%s Tx Extension Descriptor Alloc Fail",
  772. __func__);
  773. goto failure;
  774. }
  775. #if TQM_BYPASS_WAR
  776. /* Temporary WAR due to TQM VP issues */
  777. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  778. qdf_atomic_inc(&pdev->num_tx_exception);
  779. #endif
  780. if (qdf_unlikely(msdu_info->exception_fw))
  781. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  782. tx_desc->msdu_ext_desc = msdu_ext_desc;
  783. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  784. return tx_desc;
  785. failure:
  786. dp_tx_desc_release(tx_desc, desc_pool_id);
  787. return NULL;
  788. }
  789. /**
  790. * dp_tx_prepare_raw() - Prepare RAW packet TX
  791. * @vdev: DP vdev handle
  792. * @nbuf: buffer pointer
  793. * @seg_info: Pointer to Segment info Descriptor to be prepared
  794. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  795. * descriptor
  796. *
  797. * Return:
  798. */
  799. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  800. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  801. {
  802. qdf_nbuf_t curr_nbuf = NULL;
  803. uint16_t total_len = 0;
  804. qdf_dma_addr_t paddr;
  805. int32_t i;
  806. int32_t mapped_buf_num = 0;
  807. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  808. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  809. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  810. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  811. if (vdev->raw_mode_war &&
  812. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  813. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  814. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  815. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  816. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  817. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  818. QDF_DMA_TO_DEVICE)) {
  819. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  820. "%s dma map error ", __func__);
  821. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  822. mapped_buf_num = i;
  823. goto error;
  824. }
  825. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  826. seg_info->frags[i].paddr_lo = paddr;
  827. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  828. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  829. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  830. total_len += qdf_nbuf_len(curr_nbuf);
  831. }
  832. seg_info->frag_cnt = i;
  833. seg_info->total_len = total_len;
  834. seg_info->next = NULL;
  835. sg_info->curr_seg = seg_info;
  836. msdu_info->frm_type = dp_tx_frm_raw;
  837. msdu_info->num_seg = 1;
  838. return nbuf;
  839. error:
  840. i = 0;
  841. while (nbuf) {
  842. curr_nbuf = nbuf;
  843. if (i < mapped_buf_num) {
  844. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  845. i++;
  846. }
  847. nbuf = qdf_nbuf_next(nbuf);
  848. qdf_nbuf_free(curr_nbuf);
  849. }
  850. return NULL;
  851. }
  852. /**
  853. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  854. * @soc: DP Soc Handle
  855. * @vdev: DP vdev handle
  856. * @tx_desc: Tx Descriptor Handle
  857. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  858. * @fw_metadata: Metadata to send to Target Firmware along with frame
  859. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  860. * @tx_exc_metadata: Handle that holds exception path meta data
  861. *
  862. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  863. * from software Tx descriptor
  864. *
  865. * Return:
  866. */
  867. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  868. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  869. uint16_t fw_metadata, uint8_t ring_id,
  870. struct cdp_tx_exception_metadata
  871. *tx_exc_metadata)
  872. {
  873. uint8_t type;
  874. uint16_t length;
  875. void *hal_tx_desc, *hal_tx_desc_cached;
  876. qdf_dma_addr_t dma_addr;
  877. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  878. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  879. tx_exc_metadata->sec_type : vdev->sec_type);
  880. /* Return Buffer Manager ID */
  881. uint8_t bm_id = ring_id;
  882. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  883. hal_tx_desc_cached = (void *) cached_desc;
  884. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  885. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  886. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  887. type = HAL_TX_BUF_TYPE_EXT_DESC;
  888. dma_addr = tx_desc->msdu_ext_desc->paddr;
  889. } else {
  890. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  891. type = HAL_TX_BUF_TYPE_BUFFER;
  892. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  893. }
  894. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  895. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  896. dma_addr, bm_id, tx_desc->id,
  897. type, soc->hal_soc);
  898. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  899. return QDF_STATUS_E_RESOURCES;
  900. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  901. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  902. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  903. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  904. vdev->pdev->lmac_id);
  905. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  906. vdev->search_type);
  907. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  908. vdev->bss_ast_hash);
  909. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  910. vdev->dscp_tid_map_id);
  911. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  912. sec_type_map[sec_type]);
  913. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  914. length, type, (uint64_t)dma_addr,
  915. tx_desc->pkt_offset, tx_desc->id);
  916. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  917. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  918. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  919. vdev->hal_desc_addr_search_flags);
  920. /* verify checksum offload configuration*/
  921. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  922. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  923. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  924. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  925. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  926. }
  927. if (tid != HTT_TX_EXT_TID_INVALID)
  928. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  929. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  930. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  931. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  932. /* Sync cached descriptor with HW */
  933. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  934. if (!hal_tx_desc) {
  935. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  936. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  937. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  938. return QDF_STATUS_E_RESOURCES;
  939. }
  940. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  941. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  942. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  943. return QDF_STATUS_SUCCESS;
  944. }
  945. /**
  946. * dp_cce_classify() - Classify the frame based on CCE rules
  947. * @vdev: DP vdev handle
  948. * @nbuf: skb
  949. *
  950. * Classify frames based on CCE rules
  951. * Return: bool( true if classified,
  952. * else false)
  953. */
  954. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  955. {
  956. qdf_ether_header_t *eh = NULL;
  957. uint16_t ether_type;
  958. qdf_llc_t *llcHdr;
  959. qdf_nbuf_t nbuf_clone = NULL;
  960. qdf_dot3_qosframe_t *qos_wh = NULL;
  961. /* for mesh packets don't do any classification */
  962. if (qdf_unlikely(vdev->mesh_vdev))
  963. return false;
  964. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  965. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  966. ether_type = eh->ether_type;
  967. llcHdr = (qdf_llc_t *)(nbuf->data +
  968. sizeof(qdf_ether_header_t));
  969. } else {
  970. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  971. /* For encrypted packets don't do any classification */
  972. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  973. return false;
  974. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  975. if (qdf_unlikely(
  976. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  977. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  978. ether_type = *(uint16_t *)(nbuf->data
  979. + QDF_IEEE80211_4ADDR_HDR_LEN
  980. + sizeof(qdf_llc_t)
  981. - sizeof(ether_type));
  982. llcHdr = (qdf_llc_t *)(nbuf->data +
  983. QDF_IEEE80211_4ADDR_HDR_LEN);
  984. } else {
  985. ether_type = *(uint16_t *)(nbuf->data
  986. + QDF_IEEE80211_3ADDR_HDR_LEN
  987. + sizeof(qdf_llc_t)
  988. - sizeof(ether_type));
  989. llcHdr = (qdf_llc_t *)(nbuf->data +
  990. QDF_IEEE80211_3ADDR_HDR_LEN);
  991. }
  992. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  993. && (ether_type ==
  994. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  995. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  996. return true;
  997. }
  998. }
  999. return false;
  1000. }
  1001. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1002. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1003. sizeof(*llcHdr));
  1004. nbuf_clone = qdf_nbuf_clone(nbuf);
  1005. if (qdf_unlikely(nbuf_clone)) {
  1006. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1007. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1008. qdf_nbuf_pull_head(nbuf_clone,
  1009. sizeof(qdf_net_vlanhdr_t));
  1010. }
  1011. }
  1012. } else {
  1013. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1014. nbuf_clone = qdf_nbuf_clone(nbuf);
  1015. if (qdf_unlikely(nbuf_clone)) {
  1016. qdf_nbuf_pull_head(nbuf_clone,
  1017. sizeof(qdf_net_vlanhdr_t));
  1018. }
  1019. }
  1020. }
  1021. if (qdf_unlikely(nbuf_clone))
  1022. nbuf = nbuf_clone;
  1023. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1024. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1025. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1026. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1027. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1028. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1029. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1030. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1031. if (qdf_unlikely(nbuf_clone))
  1032. qdf_nbuf_free(nbuf_clone);
  1033. return true;
  1034. }
  1035. if (qdf_unlikely(nbuf_clone))
  1036. qdf_nbuf_free(nbuf_clone);
  1037. return false;
  1038. }
  1039. /**
  1040. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1041. * @vdev: DP vdev handle
  1042. * @nbuf: skb
  1043. *
  1044. * Extract the DSCP or PCP information from frame and map into TID value.
  1045. *
  1046. * Return: void
  1047. */
  1048. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1049. struct dp_tx_msdu_info_s *msdu_info)
  1050. {
  1051. uint8_t tos = 0, dscp_tid_override = 0;
  1052. uint8_t *hdr_ptr, *L3datap;
  1053. uint8_t is_mcast = 0;
  1054. qdf_ether_header_t *eh = NULL;
  1055. qdf_ethervlan_header_t *evh = NULL;
  1056. uint16_t ether_type;
  1057. qdf_llc_t *llcHdr;
  1058. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1059. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1060. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1061. eh = (qdf_ether_header_t *)nbuf->data;
  1062. hdr_ptr = eh->ether_dhost;
  1063. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1064. } else {
  1065. qdf_dot3_qosframe_t *qos_wh =
  1066. (qdf_dot3_qosframe_t *) nbuf->data;
  1067. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1068. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1069. return;
  1070. }
  1071. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1072. ether_type = eh->ether_type;
  1073. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1074. /*
  1075. * Check if packet is dot3 or eth2 type.
  1076. */
  1077. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1078. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1079. sizeof(*llcHdr));
  1080. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1081. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1082. sizeof(*llcHdr);
  1083. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1084. + sizeof(*llcHdr) +
  1085. sizeof(qdf_net_vlanhdr_t));
  1086. } else {
  1087. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1088. sizeof(*llcHdr);
  1089. }
  1090. } else {
  1091. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1092. evh = (qdf_ethervlan_header_t *) eh;
  1093. ether_type = evh->ether_type;
  1094. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1095. }
  1096. }
  1097. /*
  1098. * Find priority from IP TOS DSCP field
  1099. */
  1100. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1101. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1102. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1103. /* Only for unicast frames */
  1104. if (!is_mcast) {
  1105. /* send it on VO queue */
  1106. msdu_info->tid = DP_VO_TID;
  1107. }
  1108. } else {
  1109. /*
  1110. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1111. * from TOS byte.
  1112. */
  1113. tos = ip->ip_tos;
  1114. dscp_tid_override = 1;
  1115. }
  1116. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1117. /* TODO
  1118. * use flowlabel
  1119. *igmpmld cases to be handled in phase 2
  1120. */
  1121. unsigned long ver_pri_flowlabel;
  1122. unsigned long pri;
  1123. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1124. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1125. DP_IPV6_PRIORITY_SHIFT;
  1126. tos = pri;
  1127. dscp_tid_override = 1;
  1128. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1129. msdu_info->tid = DP_VO_TID;
  1130. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1131. /* Only for unicast frames */
  1132. if (!is_mcast) {
  1133. /* send ucast arp on VO queue */
  1134. msdu_info->tid = DP_VO_TID;
  1135. }
  1136. }
  1137. /*
  1138. * Assign all MCAST packets to BE
  1139. */
  1140. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1141. if (is_mcast) {
  1142. tos = 0;
  1143. dscp_tid_override = 1;
  1144. }
  1145. }
  1146. if (dscp_tid_override == 1) {
  1147. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1148. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1149. }
  1150. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1151. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1152. return;
  1153. }
  1154. /**
  1155. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1156. * @vdev: DP vdev handle
  1157. * @nbuf: skb
  1158. *
  1159. * Software based TID classification is required when more than 2 DSCP-TID
  1160. * mapping tables are needed.
  1161. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1162. *
  1163. * Return: void
  1164. */
  1165. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1166. struct dp_tx_msdu_info_s *msdu_info)
  1167. {
  1168. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1169. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1170. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1171. return;
  1172. /* for mesh packets don't do any classification */
  1173. if (qdf_unlikely(vdev->mesh_vdev))
  1174. return;
  1175. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1176. }
  1177. #ifdef FEATURE_WLAN_TDLS
  1178. /**
  1179. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1180. * @tx_desc: TX descriptor
  1181. *
  1182. * Return: None
  1183. */
  1184. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1185. {
  1186. if (tx_desc->vdev) {
  1187. if (tx_desc->vdev->is_tdls_frame) {
  1188. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1189. tx_desc->vdev->is_tdls_frame = false;
  1190. }
  1191. }
  1192. }
  1193. /**
  1194. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1195. * @tx_desc: TX descriptor
  1196. * @vdev: datapath vdev handle
  1197. *
  1198. * Return: None
  1199. */
  1200. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1201. struct dp_vdev *vdev)
  1202. {
  1203. struct hal_tx_completion_status ts = {0};
  1204. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1205. if (qdf_unlikely(!vdev)) {
  1206. dp_err("vdev is null!");
  1207. return;
  1208. }
  1209. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1210. if (vdev->tx_non_std_data_callback.func) {
  1211. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1212. vdev->tx_non_std_data_callback.func(
  1213. vdev->tx_non_std_data_callback.ctxt,
  1214. nbuf, ts.status);
  1215. return;
  1216. }
  1217. }
  1218. #else
  1219. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1220. {
  1221. }
  1222. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1223. struct dp_vdev *vdev)
  1224. {
  1225. }
  1226. #endif
  1227. /**
  1228. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1229. * @vdev: DP vdev handle
  1230. * @nbuf: skb
  1231. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1232. * @meta_data: Metadata to the fw
  1233. * @tx_q: Tx queue to be used for this Tx frame
  1234. * @peer_id: peer_id of the peer in case of NAWDS frames
  1235. * @tx_exc_metadata: Handle that holds exception path metadata
  1236. *
  1237. * Return: NULL on success,
  1238. * nbuf when it fails to send
  1239. */
  1240. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1241. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1242. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1243. {
  1244. struct dp_pdev *pdev = vdev->pdev;
  1245. struct dp_soc *soc = pdev->soc;
  1246. struct dp_tx_desc_s *tx_desc;
  1247. QDF_STATUS status;
  1248. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1249. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1250. uint16_t htt_tcl_metadata = 0;
  1251. uint8_t tid = msdu_info->tid;
  1252. struct cdp_tid_tx_stats *tid_stats = NULL;
  1253. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1254. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1255. msdu_info, tx_exc_metadata);
  1256. if (!tx_desc) {
  1257. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1258. vdev, tx_q->desc_pool_id);
  1259. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1260. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1261. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1262. return nbuf;
  1263. }
  1264. if (qdf_unlikely(soc->cce_disable)) {
  1265. if (dp_cce_classify(vdev, nbuf) == true) {
  1266. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1267. tid = DP_VO_TID;
  1268. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1269. }
  1270. }
  1271. dp_tx_update_tdls_flags(tx_desc);
  1272. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1273. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1274. "%s %d : HAL RING Access Failed -- %pK",
  1275. __func__, __LINE__, hal_srng);
  1276. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1277. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1278. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1279. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1280. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1281. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1282. goto fail_return;
  1283. }
  1284. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1285. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1286. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1287. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1288. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1289. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1290. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1291. peer_id);
  1292. } else
  1293. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1294. if (msdu_info->exception_fw) {
  1295. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1296. }
  1297. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1298. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1299. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1300. if (status != QDF_STATUS_SUCCESS) {
  1301. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1302. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1303. __func__, tx_desc, tx_q->ring_id);
  1304. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1305. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1306. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1307. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1308. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1309. goto fail_return;
  1310. }
  1311. nbuf = NULL;
  1312. fail_return:
  1313. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1314. hal_srng_access_end(soc->hal_soc, hal_srng);
  1315. hif_pm_runtime_put(soc->hif_handle);
  1316. } else {
  1317. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1318. }
  1319. return nbuf;
  1320. }
  1321. /**
  1322. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1323. * @vdev: DP vdev handle
  1324. * @nbuf: skb
  1325. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1326. *
  1327. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1328. *
  1329. * Return: NULL on success,
  1330. * nbuf when it fails to send
  1331. */
  1332. #if QDF_LOCK_STATS
  1333. static noinline
  1334. #else
  1335. static
  1336. #endif
  1337. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1338. struct dp_tx_msdu_info_s *msdu_info)
  1339. {
  1340. uint8_t i;
  1341. struct dp_pdev *pdev = vdev->pdev;
  1342. struct dp_soc *soc = pdev->soc;
  1343. struct dp_tx_desc_s *tx_desc;
  1344. bool is_cce_classified = false;
  1345. QDF_STATUS status;
  1346. uint16_t htt_tcl_metadata = 0;
  1347. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1348. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1349. struct cdp_tid_tx_stats *tid_stats = NULL;
  1350. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1351. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1352. "%s %d : HAL RING Access Failed -- %pK",
  1353. __func__, __LINE__, hal_srng);
  1354. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1355. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1356. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1357. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1358. return nbuf;
  1359. }
  1360. if (qdf_unlikely(soc->cce_disable)) {
  1361. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1362. if (is_cce_classified) {
  1363. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1364. msdu_info->tid = DP_VO_TID;
  1365. }
  1366. }
  1367. if (msdu_info->frm_type == dp_tx_frm_me)
  1368. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1369. i = 0;
  1370. /* Print statement to track i and num_seg */
  1371. /*
  1372. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1373. * descriptors using information in msdu_info
  1374. */
  1375. while (i < msdu_info->num_seg) {
  1376. /*
  1377. * Setup Tx descriptor for an MSDU, and MSDU extension
  1378. * descriptor
  1379. */
  1380. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1381. tx_q->desc_pool_id);
  1382. if (!tx_desc) {
  1383. if (msdu_info->frm_type == dp_tx_frm_me) {
  1384. dp_tx_me_free_buf(pdev,
  1385. (void *)(msdu_info->u.sg_info
  1386. .curr_seg->frags[0].vaddr));
  1387. }
  1388. goto done;
  1389. }
  1390. if (msdu_info->frm_type == dp_tx_frm_me) {
  1391. tx_desc->me_buffer =
  1392. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1393. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1394. }
  1395. if (is_cce_classified)
  1396. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1397. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1398. if (msdu_info->exception_fw) {
  1399. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1400. }
  1401. /*
  1402. * Enqueue the Tx MSDU descriptor to HW for transmit
  1403. */
  1404. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1405. htt_tcl_metadata, tx_q->ring_id, NULL);
  1406. if (status != QDF_STATUS_SUCCESS) {
  1407. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1408. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1409. __func__, tx_desc, tx_q->ring_id);
  1410. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1411. tid_stats = &pdev->stats.tid_stats.
  1412. tid_tx_stats[msdu_info->tid];
  1413. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1414. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1415. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1416. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1417. goto done;
  1418. }
  1419. /*
  1420. * TODO
  1421. * if tso_info structure can be modified to have curr_seg
  1422. * as first element, following 2 blocks of code (for TSO and SG)
  1423. * can be combined into 1
  1424. */
  1425. /*
  1426. * For frames with multiple segments (TSO, ME), jump to next
  1427. * segment.
  1428. */
  1429. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1430. if (msdu_info->u.tso_info.curr_seg->next) {
  1431. msdu_info->u.tso_info.curr_seg =
  1432. msdu_info->u.tso_info.curr_seg->next;
  1433. /*
  1434. * If this is a jumbo nbuf, then increment the number of
  1435. * nbuf users for each additional segment of the msdu.
  1436. * This will ensure that the skb is freed only after
  1437. * receiving tx completion for all segments of an nbuf
  1438. */
  1439. qdf_nbuf_inc_users(nbuf);
  1440. /* Check with MCL if this is needed */
  1441. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1442. }
  1443. }
  1444. /*
  1445. * For Multicast-Unicast converted packets,
  1446. * each converted frame (for a client) is represented as
  1447. * 1 segment
  1448. */
  1449. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1450. (msdu_info->frm_type == dp_tx_frm_me)) {
  1451. if (msdu_info->u.sg_info.curr_seg->next) {
  1452. msdu_info->u.sg_info.curr_seg =
  1453. msdu_info->u.sg_info.curr_seg->next;
  1454. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1455. }
  1456. }
  1457. i++;
  1458. }
  1459. nbuf = NULL;
  1460. done:
  1461. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1462. hal_srng_access_end(soc->hal_soc, hal_srng);
  1463. hif_pm_runtime_put(soc->hif_handle);
  1464. } else {
  1465. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1466. }
  1467. return nbuf;
  1468. }
  1469. /**
  1470. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1471. * for SG frames
  1472. * @vdev: DP vdev handle
  1473. * @nbuf: skb
  1474. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1475. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1476. *
  1477. * Return: NULL on success,
  1478. * nbuf when it fails to send
  1479. */
  1480. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1481. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1482. {
  1483. uint32_t cur_frag, nr_frags;
  1484. qdf_dma_addr_t paddr;
  1485. struct dp_tx_sg_info_s *sg_info;
  1486. sg_info = &msdu_info->u.sg_info;
  1487. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1488. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1489. QDF_DMA_TO_DEVICE)) {
  1490. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1491. "dma map error");
  1492. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1493. qdf_nbuf_free(nbuf);
  1494. return NULL;
  1495. }
  1496. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1497. seg_info->frags[0].paddr_lo = paddr;
  1498. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1499. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1500. seg_info->frags[0].vaddr = (void *) nbuf;
  1501. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1502. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1503. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1504. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1505. "frag dma map error");
  1506. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1507. qdf_nbuf_free(nbuf);
  1508. return NULL;
  1509. }
  1510. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1511. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1512. seg_info->frags[cur_frag + 1].paddr_hi =
  1513. ((uint64_t) paddr) >> 32;
  1514. seg_info->frags[cur_frag + 1].len =
  1515. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1516. }
  1517. seg_info->frag_cnt = (cur_frag + 1);
  1518. seg_info->total_len = qdf_nbuf_len(nbuf);
  1519. seg_info->next = NULL;
  1520. sg_info->curr_seg = seg_info;
  1521. msdu_info->frm_type = dp_tx_frm_sg;
  1522. msdu_info->num_seg = 1;
  1523. return nbuf;
  1524. }
  1525. #ifdef MESH_MODE_SUPPORT
  1526. /**
  1527. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1528. and prepare msdu_info for mesh frames.
  1529. * @vdev: DP vdev handle
  1530. * @nbuf: skb
  1531. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1532. *
  1533. * Return: NULL on failure,
  1534. * nbuf when extracted successfully
  1535. */
  1536. static
  1537. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1538. struct dp_tx_msdu_info_s *msdu_info)
  1539. {
  1540. struct meta_hdr_s *mhdr;
  1541. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1542. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1543. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1544. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1545. msdu_info->exception_fw = 0;
  1546. goto remove_meta_hdr;
  1547. }
  1548. msdu_info->exception_fw = 1;
  1549. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1550. meta_data->host_tx_desc_pool = 1;
  1551. meta_data->update_peer_cache = 1;
  1552. meta_data->learning_frame = 1;
  1553. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1554. meta_data->power = mhdr->power;
  1555. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1556. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1557. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1558. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1559. meta_data->dyn_bw = 1;
  1560. meta_data->valid_pwr = 1;
  1561. meta_data->valid_mcs_mask = 1;
  1562. meta_data->valid_nss_mask = 1;
  1563. meta_data->valid_preamble_type = 1;
  1564. meta_data->valid_retries = 1;
  1565. meta_data->valid_bw_info = 1;
  1566. }
  1567. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1568. meta_data->encrypt_type = 0;
  1569. meta_data->valid_encrypt_type = 1;
  1570. meta_data->learning_frame = 0;
  1571. }
  1572. meta_data->valid_key_flags = 1;
  1573. meta_data->key_flags = (mhdr->keyix & 0x3);
  1574. remove_meta_hdr:
  1575. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1576. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1577. "qdf_nbuf_pull_head failed");
  1578. qdf_nbuf_free(nbuf);
  1579. return NULL;
  1580. }
  1581. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1582. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1583. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1584. " tid %d to_fw %d",
  1585. __func__, msdu_info->meta_data[0],
  1586. msdu_info->meta_data[1],
  1587. msdu_info->meta_data[2],
  1588. msdu_info->meta_data[3],
  1589. msdu_info->meta_data[4],
  1590. msdu_info->meta_data[5],
  1591. msdu_info->tid, msdu_info->exception_fw);
  1592. return nbuf;
  1593. }
  1594. #else
  1595. static
  1596. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1597. struct dp_tx_msdu_info_s *msdu_info)
  1598. {
  1599. return nbuf;
  1600. }
  1601. #endif
  1602. /**
  1603. * dp_check_exc_metadata() - Checks if parameters are valid
  1604. * @tx_exc - holds all exception path parameters
  1605. *
  1606. * Returns true when all the parameters are valid else false
  1607. *
  1608. */
  1609. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1610. {
  1611. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1612. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1613. tx_exc->sec_type > cdp_num_sec_types) {
  1614. return false;
  1615. }
  1616. return true;
  1617. }
  1618. /**
  1619. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1620. * @vap_dev: DP vdev handle
  1621. * @nbuf: skb
  1622. * @tx_exc_metadata: Handle that holds exception path meta data
  1623. *
  1624. * Entry point for Core Tx layer (DP_TX) invoked from
  1625. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1626. *
  1627. * Return: NULL on success,
  1628. * nbuf when it fails to send
  1629. */
  1630. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1631. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1632. {
  1633. qdf_ether_header_t *eh = NULL;
  1634. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1635. struct dp_tx_msdu_info_s msdu_info;
  1636. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1637. msdu_info.tid = tx_exc_metadata->tid;
  1638. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1639. dp_verbose_debug("skb %pM", nbuf->data);
  1640. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1641. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1642. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1643. "Invalid parameters in exception path");
  1644. goto fail;
  1645. }
  1646. /* Basic sanity checks for unsupported packets */
  1647. /* MESH mode */
  1648. if (qdf_unlikely(vdev->mesh_vdev)) {
  1649. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1650. "Mesh mode is not supported in exception path");
  1651. goto fail;
  1652. }
  1653. /* TSO or SG */
  1654. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1655. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1656. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1657. "TSO and SG are not supported in exception path");
  1658. goto fail;
  1659. }
  1660. /* RAW */
  1661. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1662. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1663. "Raw frame is not supported in exception path");
  1664. goto fail;
  1665. }
  1666. /* Mcast enhancement*/
  1667. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1668. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1669. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1670. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1671. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1672. }
  1673. }
  1674. /*
  1675. * Get HW Queue to use for this frame.
  1676. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1677. * dedicated for data and 1 for command.
  1678. * "queue_id" maps to one hardware ring.
  1679. * With each ring, we also associate a unique Tx descriptor pool
  1680. * to minimize lock contention for these resources.
  1681. */
  1682. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1683. /* Single linear frame */
  1684. /*
  1685. * If nbuf is a simple linear frame, use send_single function to
  1686. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1687. * SRNG. There is no need to setup a MSDU extension descriptor.
  1688. */
  1689. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1690. tx_exc_metadata->peer_id, tx_exc_metadata);
  1691. return nbuf;
  1692. fail:
  1693. dp_verbose_debug("pkt send failed");
  1694. return nbuf;
  1695. }
  1696. /**
  1697. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1698. * @vap_dev: DP vdev handle
  1699. * @nbuf: skb
  1700. *
  1701. * Entry point for Core Tx layer (DP_TX) invoked from
  1702. * hard_start_xmit in OSIF/HDD
  1703. *
  1704. * Return: NULL on success,
  1705. * nbuf when it fails to send
  1706. */
  1707. #ifdef MESH_MODE_SUPPORT
  1708. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1709. {
  1710. struct meta_hdr_s *mhdr;
  1711. qdf_nbuf_t nbuf_mesh = NULL;
  1712. qdf_nbuf_t nbuf_clone = NULL;
  1713. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1714. uint8_t no_enc_frame = 0;
  1715. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1716. if (!nbuf_mesh) {
  1717. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1718. "qdf_nbuf_unshare failed");
  1719. return nbuf;
  1720. }
  1721. nbuf = nbuf_mesh;
  1722. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1723. if ((vdev->sec_type != cdp_sec_type_none) &&
  1724. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1725. no_enc_frame = 1;
  1726. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1727. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1728. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1729. !no_enc_frame) {
  1730. nbuf_clone = qdf_nbuf_clone(nbuf);
  1731. if (!nbuf_clone) {
  1732. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1733. "qdf_nbuf_clone failed");
  1734. return nbuf;
  1735. }
  1736. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1737. }
  1738. if (nbuf_clone) {
  1739. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1740. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1741. } else {
  1742. qdf_nbuf_free(nbuf_clone);
  1743. }
  1744. }
  1745. if (no_enc_frame)
  1746. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1747. else
  1748. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1749. nbuf = dp_tx_send(vap_dev, nbuf);
  1750. if ((!nbuf) && no_enc_frame) {
  1751. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1752. }
  1753. return nbuf;
  1754. }
  1755. #else
  1756. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1757. {
  1758. return dp_tx_send(vap_dev, nbuf);
  1759. }
  1760. #endif
  1761. /**
  1762. * dp_tx_send() - Transmit a frame on a given VAP
  1763. * @vap_dev: DP vdev handle
  1764. * @nbuf: skb
  1765. *
  1766. * Entry point for Core Tx layer (DP_TX) invoked from
  1767. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1768. * cases
  1769. *
  1770. * Return: NULL on success,
  1771. * nbuf when it fails to send
  1772. */
  1773. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1774. {
  1775. qdf_ether_header_t *eh = NULL;
  1776. struct dp_tx_msdu_info_s msdu_info;
  1777. struct dp_tx_seg_info_s seg_info;
  1778. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1779. uint16_t peer_id = HTT_INVALID_PEER;
  1780. qdf_nbuf_t nbuf_mesh = NULL;
  1781. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1782. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1783. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1784. dp_verbose_debug("skb %pM", nbuf->data);
  1785. /*
  1786. * Set Default Host TID value to invalid TID
  1787. * (TID override disabled)
  1788. */
  1789. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1790. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1791. if (qdf_unlikely(vdev->mesh_vdev)) {
  1792. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1793. &msdu_info);
  1794. if (!nbuf_mesh) {
  1795. dp_verbose_debug("Extracting mesh metadata failed");
  1796. return nbuf;
  1797. }
  1798. nbuf = nbuf_mesh;
  1799. }
  1800. /*
  1801. * Get HW Queue to use for this frame.
  1802. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1803. * dedicated for data and 1 for command.
  1804. * "queue_id" maps to one hardware ring.
  1805. * With each ring, we also associate a unique Tx descriptor pool
  1806. * to minimize lock contention for these resources.
  1807. */
  1808. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1809. /*
  1810. * TCL H/W supports 2 DSCP-TID mapping tables.
  1811. * Table 1 - Default DSCP-TID mapping table
  1812. * Table 2 - 1 DSCP-TID override table
  1813. *
  1814. * If we need a different DSCP-TID mapping for this vap,
  1815. * call tid_classify to extract DSCP/ToS from frame and
  1816. * map to a TID and store in msdu_info. This is later used
  1817. * to fill in TCL Input descriptor (per-packet TID override).
  1818. */
  1819. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1820. /*
  1821. * Classify the frame and call corresponding
  1822. * "prepare" function which extracts the segment (TSO)
  1823. * and fragmentation information (for TSO , SG, ME, or Raw)
  1824. * into MSDU_INFO structure which is later used to fill
  1825. * SW and HW descriptors.
  1826. */
  1827. if (qdf_nbuf_is_tso(nbuf)) {
  1828. dp_verbose_debug("TSO frame %pK", vdev);
  1829. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1830. qdf_nbuf_len(nbuf));
  1831. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1832. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1833. qdf_nbuf_len(nbuf));
  1834. return nbuf;
  1835. }
  1836. goto send_multiple;
  1837. }
  1838. /* SG */
  1839. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1840. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1841. if (!nbuf)
  1842. return NULL;
  1843. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1844. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1845. qdf_nbuf_len(nbuf));
  1846. goto send_multiple;
  1847. }
  1848. #ifdef ATH_SUPPORT_IQUE
  1849. /* Mcast to Ucast Conversion*/
  1850. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1851. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1852. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1853. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1854. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1855. DP_STATS_INC_PKT(vdev,
  1856. tx_i.mcast_en.mcast_pkt, 1,
  1857. qdf_nbuf_len(nbuf));
  1858. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1859. QDF_STATUS_SUCCESS) {
  1860. return NULL;
  1861. }
  1862. }
  1863. }
  1864. #endif
  1865. /* RAW */
  1866. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1867. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1868. if (!nbuf)
  1869. return NULL;
  1870. dp_verbose_debug("Raw frame %pK", vdev);
  1871. goto send_multiple;
  1872. }
  1873. /* Single linear frame */
  1874. /*
  1875. * If nbuf is a simple linear frame, use send_single function to
  1876. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1877. * SRNG. There is no need to setup a MSDU extension descriptor.
  1878. */
  1879. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1880. return nbuf;
  1881. send_multiple:
  1882. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1883. return nbuf;
  1884. }
  1885. /**
  1886. * dp_tx_reinject_handler() - Tx Reinject Handler
  1887. * @tx_desc: software descriptor head pointer
  1888. * @status : Tx completion status from HTT descriptor
  1889. *
  1890. * This function reinjects frames back to Target.
  1891. * Todo - Host queue needs to be added
  1892. *
  1893. * Return: none
  1894. */
  1895. static
  1896. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1897. {
  1898. struct dp_vdev *vdev;
  1899. struct dp_peer *peer = NULL;
  1900. uint32_t peer_id = HTT_INVALID_PEER;
  1901. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1902. qdf_nbuf_t nbuf_copy = NULL;
  1903. struct dp_tx_msdu_info_s msdu_info;
  1904. struct dp_peer *sa_peer = NULL;
  1905. struct dp_ast_entry *ast_entry = NULL;
  1906. struct dp_soc *soc = NULL;
  1907. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1908. #ifdef WDS_VENDOR_EXTENSION
  1909. int is_mcast = 0, is_ucast = 0;
  1910. int num_peers_3addr = 0;
  1911. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1912. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1913. #endif
  1914. vdev = tx_desc->vdev;
  1915. soc = vdev->pdev->soc;
  1916. qdf_assert(vdev);
  1917. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1918. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1919. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1920. "%s Tx reinject path", __func__);
  1921. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1922. qdf_nbuf_len(tx_desc->nbuf));
  1923. qdf_spin_lock_bh(&(soc->ast_lock));
  1924. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1925. (soc,
  1926. (uint8_t *)(eh->ether_shost),
  1927. vdev->pdev->pdev_id);
  1928. if (ast_entry)
  1929. sa_peer = ast_entry->peer;
  1930. qdf_spin_unlock_bh(&(soc->ast_lock));
  1931. #ifdef WDS_VENDOR_EXTENSION
  1932. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1933. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1934. } else {
  1935. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1936. }
  1937. is_ucast = !is_mcast;
  1938. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1939. if (peer->bss_peer)
  1940. continue;
  1941. /* Detect wds peers that use 3-addr framing for mcast.
  1942. * if there are any, the bss_peer is used to send the
  1943. * the mcast frame using 3-addr format. all wds enabled
  1944. * peers that use 4-addr framing for mcast frames will
  1945. * be duplicated and sent as 4-addr frames below.
  1946. */
  1947. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1948. num_peers_3addr = 1;
  1949. break;
  1950. }
  1951. }
  1952. #endif
  1953. if (qdf_unlikely(vdev->mesh_vdev)) {
  1954. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1955. } else {
  1956. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1957. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1958. #ifdef WDS_VENDOR_EXTENSION
  1959. /*
  1960. * . if 3-addr STA, then send on BSS Peer
  1961. * . if Peer WDS enabled and accept 4-addr mcast,
  1962. * send mcast on that peer only
  1963. * . if Peer WDS enabled and accept 4-addr ucast,
  1964. * send ucast on that peer only
  1965. */
  1966. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1967. (peer->wds_enabled &&
  1968. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1969. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1970. #else
  1971. ((peer->bss_peer &&
  1972. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1973. peer->nawds_enabled)) {
  1974. #endif
  1975. peer_id = DP_INVALID_PEER;
  1976. if (peer->nawds_enabled) {
  1977. peer_id = peer->peer_ids[0];
  1978. if (sa_peer == peer) {
  1979. QDF_TRACE(
  1980. QDF_MODULE_ID_DP,
  1981. QDF_TRACE_LEVEL_DEBUG,
  1982. " %s: multicast packet",
  1983. __func__);
  1984. DP_STATS_INC(peer,
  1985. tx.nawds_mcast_drop, 1);
  1986. continue;
  1987. }
  1988. }
  1989. nbuf_copy = qdf_nbuf_copy(nbuf);
  1990. if (!nbuf_copy) {
  1991. QDF_TRACE(QDF_MODULE_ID_DP,
  1992. QDF_TRACE_LEVEL_DEBUG,
  1993. FL("nbuf copy failed"));
  1994. break;
  1995. }
  1996. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1997. nbuf_copy,
  1998. &msdu_info,
  1999. peer_id,
  2000. NULL);
  2001. if (nbuf_copy) {
  2002. QDF_TRACE(QDF_MODULE_ID_DP,
  2003. QDF_TRACE_LEVEL_DEBUG,
  2004. FL("pkt send failed"));
  2005. qdf_nbuf_free(nbuf_copy);
  2006. } else {
  2007. if (peer_id != DP_INVALID_PEER)
  2008. DP_STATS_INC_PKT(peer,
  2009. tx.nawds_mcast,
  2010. 1, qdf_nbuf_len(nbuf));
  2011. }
  2012. }
  2013. }
  2014. }
  2015. if (vdev->nawds_enabled) {
  2016. peer_id = DP_INVALID_PEER;
  2017. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2018. 1, qdf_nbuf_len(nbuf));
  2019. nbuf = dp_tx_send_msdu_single(vdev,
  2020. nbuf,
  2021. &msdu_info,
  2022. peer_id, NULL);
  2023. if (nbuf) {
  2024. QDF_TRACE(QDF_MODULE_ID_DP,
  2025. QDF_TRACE_LEVEL_DEBUG,
  2026. FL("pkt send failed"));
  2027. qdf_nbuf_free(nbuf);
  2028. }
  2029. } else
  2030. qdf_nbuf_free(nbuf);
  2031. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2032. }
  2033. /**
  2034. * dp_tx_inspect_handler() - Tx Inspect Handler
  2035. * @tx_desc: software descriptor head pointer
  2036. * @status : Tx completion status from HTT descriptor
  2037. *
  2038. * Handles Tx frames sent back to Host for inspection
  2039. * (ProxyARP)
  2040. *
  2041. * Return: none
  2042. */
  2043. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2044. {
  2045. struct dp_soc *soc;
  2046. struct dp_pdev *pdev = tx_desc->pdev;
  2047. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2048. "%s Tx inspect path",
  2049. __func__);
  2050. qdf_assert(pdev);
  2051. soc = pdev->soc;
  2052. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2053. qdf_nbuf_len(tx_desc->nbuf));
  2054. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2055. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2056. }
  2057. #ifdef FEATURE_PERPKT_INFO
  2058. /**
  2059. * dp_get_completion_indication_for_stack() - send completion to stack
  2060. * @soc : dp_soc handle
  2061. * @pdev: dp_pdev handle
  2062. * @peer: dp peer handle
  2063. * @ts: transmit completion status structure
  2064. * @netbuf: Buffer pointer for free
  2065. *
  2066. * This function is used for indication whether buffer needs to be
  2067. * sent to stack for freeing or not
  2068. */
  2069. QDF_STATUS
  2070. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2071. struct dp_pdev *pdev,
  2072. struct dp_peer *peer,
  2073. struct hal_tx_completion_status *ts,
  2074. qdf_nbuf_t netbuf,
  2075. uint64_t time_latency)
  2076. {
  2077. struct tx_capture_hdr *ppdu_hdr;
  2078. uint16_t peer_id = ts->peer_id;
  2079. uint32_t ppdu_id = ts->ppdu_id;
  2080. uint8_t first_msdu = ts->first_msdu;
  2081. uint8_t last_msdu = ts->last_msdu;
  2082. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2083. !pdev->latency_capture_enable))
  2084. return QDF_STATUS_E_NOSUPPORT;
  2085. if (!peer) {
  2086. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2087. FL("Peer Invalid"));
  2088. return QDF_STATUS_E_INVAL;
  2089. }
  2090. if (pdev->mcopy_mode) {
  2091. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2092. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2093. return QDF_STATUS_E_INVAL;
  2094. }
  2095. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2096. pdev->m_copy_id.tx_peer_id = peer_id;
  2097. }
  2098. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2099. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2100. FL("No headroom"));
  2101. return QDF_STATUS_E_NOMEM;
  2102. }
  2103. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2104. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2105. QDF_MAC_ADDR_SIZE);
  2106. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2107. QDF_MAC_ADDR_SIZE);
  2108. ppdu_hdr->ppdu_id = ppdu_id;
  2109. ppdu_hdr->peer_id = peer_id;
  2110. ppdu_hdr->first_msdu = first_msdu;
  2111. ppdu_hdr->last_msdu = last_msdu;
  2112. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2113. ppdu_hdr->tsf = ts->tsf;
  2114. ppdu_hdr->time_latency = time_latency;
  2115. }
  2116. return QDF_STATUS_SUCCESS;
  2117. }
  2118. /**
  2119. * dp_send_completion_to_stack() - send completion to stack
  2120. * @soc : dp_soc handle
  2121. * @pdev: dp_pdev handle
  2122. * @peer_id: peer_id of the peer for which completion came
  2123. * @ppdu_id: ppdu_id
  2124. * @netbuf: Buffer pointer for free
  2125. *
  2126. * This function is used to send completion to stack
  2127. * to free buffer
  2128. */
  2129. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2130. uint16_t peer_id, uint32_t ppdu_id,
  2131. qdf_nbuf_t netbuf)
  2132. {
  2133. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2134. netbuf, peer_id,
  2135. WDI_NO_VAL, pdev->pdev_id);
  2136. }
  2137. #else
  2138. static QDF_STATUS
  2139. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2140. struct dp_pdev *pdev,
  2141. struct dp_peer *peer,
  2142. struct hal_tx_completion_status *ts,
  2143. qdf_nbuf_t netbuf,
  2144. uint64_t time_latency)
  2145. {
  2146. return QDF_STATUS_E_NOSUPPORT;
  2147. }
  2148. static void
  2149. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2150. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2151. {
  2152. }
  2153. #endif
  2154. /**
  2155. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2156. * @soc: Soc handle
  2157. * @desc: software Tx descriptor to be processed
  2158. *
  2159. * Return: none
  2160. */
  2161. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2162. struct dp_tx_desc_s *desc)
  2163. {
  2164. struct dp_vdev *vdev = desc->vdev;
  2165. qdf_nbuf_t nbuf = desc->nbuf;
  2166. /* nbuf already freed in vdev detach path */
  2167. if (!nbuf)
  2168. return;
  2169. /* If it is TDLS mgmt, don't unmap or free the frame */
  2170. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2171. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2172. /* 0 : MSDU buffer, 1 : MLE */
  2173. if (desc->msdu_ext_desc) {
  2174. /* TSO free */
  2175. if (hal_tx_ext_desc_get_tso_enable(
  2176. desc->msdu_ext_desc->vaddr)) {
  2177. /* unmap eash TSO seg before free the nbuf */
  2178. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2179. desc->tso_num_desc);
  2180. qdf_nbuf_free(nbuf);
  2181. return;
  2182. }
  2183. }
  2184. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2185. if (qdf_unlikely(!vdev)) {
  2186. qdf_nbuf_free(nbuf);
  2187. return;
  2188. }
  2189. if (qdf_likely(!vdev->mesh_vdev))
  2190. qdf_nbuf_free(nbuf);
  2191. else {
  2192. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2193. qdf_nbuf_free(nbuf);
  2194. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2195. } else
  2196. vdev->osif_tx_free_ext((nbuf));
  2197. }
  2198. }
  2199. /**
  2200. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2201. * @vdev: pointer to dp dev handler
  2202. * @status : Tx completion status from HTT descriptor
  2203. *
  2204. * Handles MEC notify event sent from fw to Host
  2205. *
  2206. * Return: none
  2207. */
  2208. #ifdef FEATURE_WDS
  2209. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2210. {
  2211. struct dp_soc *soc;
  2212. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2213. struct dp_peer *peer;
  2214. uint8_t mac_addr[QDF_MAC_ADDR_SIZE], i;
  2215. if (!vdev->mec_enabled)
  2216. return;
  2217. /* MEC required only in STA mode */
  2218. if (vdev->opmode != wlan_op_mode_sta)
  2219. return;
  2220. soc = vdev->pdev->soc;
  2221. peer = vdev->vap_bss_peer;
  2222. if (!peer) {
  2223. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2224. FL("peer is NULL"));
  2225. return;
  2226. }
  2227. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2228. "%s Tx MEC Handler",
  2229. __func__);
  2230. for (i = 0; i < QDF_MAC_ADDR_SIZE; i++)
  2231. mac_addr[(QDF_MAC_ADDR_SIZE - 1) - i] =
  2232. status[(QDF_MAC_ADDR_SIZE - 2) + i];
  2233. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  2234. dp_peer_add_ast(soc,
  2235. peer,
  2236. mac_addr,
  2237. CDP_TXRX_AST_TYPE_MEC,
  2238. flags);
  2239. }
  2240. #endif
  2241. #ifdef MESH_MODE_SUPPORT
  2242. /**
  2243. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2244. * in mesh meta header
  2245. * @tx_desc: software descriptor head pointer
  2246. * @ts: pointer to tx completion stats
  2247. * Return: none
  2248. */
  2249. static
  2250. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2251. struct hal_tx_completion_status *ts)
  2252. {
  2253. struct meta_hdr_s *mhdr;
  2254. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2255. if (!tx_desc->msdu_ext_desc) {
  2256. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2257. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2258. "netbuf %pK offset %d",
  2259. netbuf, tx_desc->pkt_offset);
  2260. return;
  2261. }
  2262. }
  2263. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2264. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2265. "netbuf %pK offset %lu", netbuf,
  2266. sizeof(struct meta_hdr_s));
  2267. return;
  2268. }
  2269. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2270. mhdr->rssi = ts->ack_frame_rssi;
  2271. mhdr->channel = tx_desc->pdev->operating_channel;
  2272. }
  2273. #else
  2274. static
  2275. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2276. struct hal_tx_completion_status *ts)
  2277. {
  2278. }
  2279. #endif
  2280. /**
  2281. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2282. * to pass in correct fields
  2283. *
  2284. * @vdev: pdev handle
  2285. * @tx_desc: tx descriptor
  2286. * @tid: tid value
  2287. * Return: none
  2288. */
  2289. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2290. struct dp_tx_desc_s *tx_desc, uint8_t tid)
  2291. {
  2292. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2293. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2294. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2295. return;
  2296. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2297. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2298. timestamp_hw_enqueue = tx_desc->timestamp;
  2299. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2300. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2301. timestamp_hw_enqueue);
  2302. interframe_delay = (uint32_t)(timestamp_ingress -
  2303. vdev->prev_tx_enq_tstamp);
  2304. /*
  2305. * Delay in software enqueue
  2306. */
  2307. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2308. CDP_DELAY_STATS_SW_ENQ);
  2309. /*
  2310. * Delay between packet enqueued to HW and Tx completion
  2311. */
  2312. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2313. CDP_DELAY_STATS_FW_HW_TRANSMIT);
  2314. /*
  2315. * Update interframe delay stats calculated at hardstart receive point.
  2316. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2317. * interframe delay will not be calculate correctly for 1st frame.
  2318. * On the other side, this will help in avoiding extra per packet check
  2319. * of !vdev->prev_tx_enq_tstamp.
  2320. */
  2321. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2322. CDP_DELAY_STATS_TX_INTERFRAME);
  2323. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2324. }
  2325. /**
  2326. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2327. * @tx_desc: software descriptor head pointer
  2328. * @ts: Tx completion status
  2329. * @peer: peer handle
  2330. *
  2331. * Return: None
  2332. */
  2333. static inline void
  2334. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2335. struct hal_tx_completion_status *ts,
  2336. struct dp_peer *peer)
  2337. {
  2338. struct dp_pdev *pdev = peer->vdev->pdev;
  2339. struct dp_soc *soc = NULL;
  2340. uint8_t mcs, pkt_type;
  2341. uint8_t tid = ts->tid;
  2342. uint32_t length;
  2343. struct cdp_tid_tx_stats *tid_stats;
  2344. if (!pdev)
  2345. return;
  2346. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2347. tid = CDP_MAX_DATA_TIDS - 1;
  2348. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[tid];
  2349. soc = pdev->soc;
  2350. mcs = ts->mcs;
  2351. pkt_type = ts->pkt_type;
  2352. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2353. dp_err("Release source is not from TQM");
  2354. return;
  2355. }
  2356. length = qdf_nbuf_len(tx_desc->nbuf);
  2357. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2358. if (qdf_unlikely(pdev->delay_stats_flag))
  2359. dp_tx_compute_delay(peer->vdev, tx_desc, tid);
  2360. tid_stats->complete_cnt++;
  2361. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2362. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2363. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2364. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2365. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2366. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2367. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2368. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2369. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2370. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2371. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2372. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2373. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2374. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2375. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2376. tid_stats->comp_fail_cnt++;
  2377. return;
  2378. }
  2379. tid_stats->success_cnt++;
  2380. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2381. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2382. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2383. /*
  2384. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2385. * Return from here if HTT PPDU events are enabled.
  2386. */
  2387. if (!(soc->process_tx_status))
  2388. return;
  2389. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2390. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2391. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2392. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2393. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2394. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2395. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2396. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2397. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2398. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2399. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2400. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2401. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2402. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2403. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2404. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2405. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2406. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2407. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2408. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2409. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2410. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2411. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2412. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2413. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2414. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2415. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2416. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2417. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2418. &peer->stats, ts->peer_id,
  2419. UPDATE_PEER_STATS, pdev->pdev_id);
  2420. #endif
  2421. }
  2422. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2423. /**
  2424. * dp_tx_flow_pool_lock() - take flow pool lock
  2425. * @soc: core txrx main context
  2426. * @tx_desc: tx desc
  2427. *
  2428. * Return: None
  2429. */
  2430. static inline
  2431. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2432. struct dp_tx_desc_s *tx_desc)
  2433. {
  2434. struct dp_tx_desc_pool_s *pool;
  2435. uint8_t desc_pool_id;
  2436. desc_pool_id = tx_desc->pool_id;
  2437. pool = &soc->tx_desc[desc_pool_id];
  2438. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2439. }
  2440. /**
  2441. * dp_tx_flow_pool_unlock() - release flow pool lock
  2442. * @soc: core txrx main context
  2443. * @tx_desc: tx desc
  2444. *
  2445. * Return: None
  2446. */
  2447. static inline
  2448. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2449. struct dp_tx_desc_s *tx_desc)
  2450. {
  2451. struct dp_tx_desc_pool_s *pool;
  2452. uint8_t desc_pool_id;
  2453. desc_pool_id = tx_desc->pool_id;
  2454. pool = &soc->tx_desc[desc_pool_id];
  2455. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2456. }
  2457. #else
  2458. static inline
  2459. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2460. {
  2461. }
  2462. static inline
  2463. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2464. {
  2465. }
  2466. #endif
  2467. /**
  2468. * dp_tx_notify_completion() - Notify tx completion for this desc
  2469. * @soc: core txrx main context
  2470. * @tx_desc: tx desc
  2471. * @netbuf: buffer
  2472. *
  2473. * Return: none
  2474. */
  2475. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2476. struct dp_tx_desc_s *tx_desc,
  2477. qdf_nbuf_t netbuf)
  2478. {
  2479. void *osif_dev;
  2480. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2481. qdf_assert(tx_desc);
  2482. dp_tx_flow_pool_lock(soc, tx_desc);
  2483. if (!tx_desc->vdev ||
  2484. !tx_desc->vdev->osif_vdev) {
  2485. dp_tx_flow_pool_unlock(soc, tx_desc);
  2486. return;
  2487. }
  2488. osif_dev = tx_desc->vdev->osif_vdev;
  2489. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2490. dp_tx_flow_pool_unlock(soc, tx_desc);
  2491. if (tx_compl_cbk)
  2492. tx_compl_cbk(netbuf, osif_dev);
  2493. }
  2494. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2495. * @pdev: pdev handle
  2496. * @tid: tid value
  2497. * @txdesc_ts: timestamp from txdesc
  2498. * @ppdu_id: ppdu id
  2499. *
  2500. * Return: none
  2501. */
  2502. #ifdef FEATURE_PERPKT_INFO
  2503. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2504. struct dp_peer *peer,
  2505. uint8_t tid,
  2506. uint64_t txdesc_ts,
  2507. uint32_t ppdu_id)
  2508. {
  2509. uint64_t delta_ms;
  2510. struct cdp_tx_sojourn_stats *sojourn_stats;
  2511. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2512. return;
  2513. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2514. tid >= CDP_DATA_TID_MAX))
  2515. return;
  2516. if (qdf_unlikely(!pdev->sojourn_buf))
  2517. return;
  2518. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2519. qdf_nbuf_data(pdev->sojourn_buf);
  2520. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2521. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2522. txdesc_ts;
  2523. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2524. delta_ms);
  2525. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2526. sojourn_stats->num_msdus[tid] = 1;
  2527. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2528. peer->avg_sojourn_msdu[tid].internal;
  2529. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2530. pdev->sojourn_buf, HTT_INVALID_PEER,
  2531. WDI_NO_VAL, pdev->pdev_id);
  2532. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2533. sojourn_stats->num_msdus[tid] = 0;
  2534. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2535. }
  2536. #else
  2537. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2538. uint8_t tid,
  2539. uint64_t txdesc_ts,
  2540. uint32_t ppdu_id)
  2541. {
  2542. }
  2543. #endif
  2544. /**
  2545. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2546. * @soc: DP Soc handle
  2547. * @tx_desc: software Tx descriptor
  2548. * @ts : Tx completion status from HAL/HTT descriptor
  2549. *
  2550. * Return: none
  2551. */
  2552. static inline void
  2553. dp_tx_comp_process_desc(struct dp_soc *soc,
  2554. struct dp_tx_desc_s *desc,
  2555. struct hal_tx_completion_status *ts,
  2556. struct dp_peer *peer)
  2557. {
  2558. uint64_t time_latency = 0;
  2559. /*
  2560. * m_copy/tx_capture modes are not supported for
  2561. * scatter gather packets
  2562. */
  2563. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2564. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2565. desc->timestamp);
  2566. }
  2567. if (!(desc->msdu_ext_desc)) {
  2568. if (QDF_STATUS_SUCCESS ==
  2569. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2570. return;
  2571. }
  2572. if (QDF_STATUS_SUCCESS ==
  2573. dp_get_completion_indication_for_stack(soc,
  2574. desc->pdev,
  2575. peer, ts,
  2576. desc->nbuf,
  2577. time_latency)) {
  2578. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2579. QDF_DMA_TO_DEVICE);
  2580. dp_send_completion_to_stack(soc,
  2581. desc->pdev,
  2582. ts->peer_id,
  2583. ts->ppdu_id,
  2584. desc->nbuf);
  2585. return;
  2586. }
  2587. }
  2588. dp_tx_comp_free_buf(soc, desc);
  2589. }
  2590. /**
  2591. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2592. * @tx_desc: software descriptor head pointer
  2593. * @ts: Tx completion status
  2594. * @peer: peer handle
  2595. *
  2596. * Return: none
  2597. */
  2598. static inline
  2599. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2600. struct hal_tx_completion_status *ts,
  2601. struct dp_peer *peer)
  2602. {
  2603. uint32_t length;
  2604. qdf_ether_header_t *eh;
  2605. struct dp_soc *soc = NULL;
  2606. struct dp_vdev *vdev = tx_desc->vdev;
  2607. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2608. if (!vdev || !nbuf) {
  2609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2610. "invalid tx descriptor. vdev or nbuf NULL");
  2611. goto out;
  2612. }
  2613. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2614. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2615. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2616. QDF_TRACE_DEFAULT_PDEV_ID,
  2617. qdf_nbuf_data_addr(nbuf),
  2618. sizeof(qdf_nbuf_data(nbuf)),
  2619. tx_desc->id,
  2620. ts->status));
  2621. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2622. "-------------------- \n"
  2623. "Tx Completion Stats: \n"
  2624. "-------------------- \n"
  2625. "ack_frame_rssi = %d \n"
  2626. "first_msdu = %d \n"
  2627. "last_msdu = %d \n"
  2628. "msdu_part_of_amsdu = %d \n"
  2629. "rate_stats valid = %d \n"
  2630. "bw = %d \n"
  2631. "pkt_type = %d \n"
  2632. "stbc = %d \n"
  2633. "ldpc = %d \n"
  2634. "sgi = %d \n"
  2635. "mcs = %d \n"
  2636. "ofdma = %d \n"
  2637. "tones_in_ru = %d \n"
  2638. "tsf = %d \n"
  2639. "ppdu_id = %d \n"
  2640. "transmit_cnt = %d \n"
  2641. "tid = %d \n"
  2642. "peer_id = %d\n",
  2643. ts->ack_frame_rssi, ts->first_msdu,
  2644. ts->last_msdu, ts->msdu_part_of_amsdu,
  2645. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2646. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2647. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2648. ts->transmit_cnt, ts->tid, ts->peer_id);
  2649. soc = vdev->pdev->soc;
  2650. /* Update SoC level stats */
  2651. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2652. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2653. /* Update per-packet stats for mesh mode */
  2654. if (qdf_unlikely(vdev->mesh_vdev) &&
  2655. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2656. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2657. length = qdf_nbuf_len(nbuf);
  2658. /* Update peer level stats */
  2659. if (!peer) {
  2660. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2661. "peer is null or deletion in progress");
  2662. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2663. goto out;
  2664. }
  2665. if (qdf_likely(!peer->bss_peer)) {
  2666. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2667. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2668. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2669. } else {
  2670. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2671. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2672. if ((peer->vdev->tx_encap_type ==
  2673. htt_cmn_pkt_type_ethernet) &&
  2674. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2675. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2676. }
  2677. }
  2678. }
  2679. dp_tx_update_peer_stats(tx_desc, ts, peer);
  2680. #ifdef QCA_SUPPORT_RDK_STATS
  2681. if (soc->wlanstats_enabled)
  2682. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2683. tx_desc->timestamp,
  2684. ts->ppdu_id);
  2685. #endif
  2686. out:
  2687. return;
  2688. }
  2689. /**
  2690. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2691. * @soc: core txrx main context
  2692. * @comp_head: software descriptor head pointer
  2693. *
  2694. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2695. * and release the software descriptors after processing is complete
  2696. *
  2697. * Return: none
  2698. */
  2699. static void
  2700. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2701. struct dp_tx_desc_s *comp_head)
  2702. {
  2703. struct dp_tx_desc_s *desc;
  2704. struct dp_tx_desc_s *next;
  2705. struct hal_tx_completion_status ts = {0};
  2706. struct dp_peer *peer;
  2707. qdf_nbuf_t netbuf;
  2708. desc = comp_head;
  2709. while (desc) {
  2710. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2711. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2712. dp_tx_comp_process_tx_status(desc, &ts, peer);
  2713. netbuf = desc->nbuf;
  2714. /* check tx complete notification */
  2715. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2716. dp_tx_notify_completion(soc, desc, netbuf);
  2717. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2718. if (peer)
  2719. dp_peer_unref_del_find_by_id(peer);
  2720. next = desc->next;
  2721. dp_tx_desc_release(desc, desc->pool_id);
  2722. desc = next;
  2723. }
  2724. }
  2725. /**
  2726. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2727. * @tx_desc: software descriptor head pointer
  2728. * @status : Tx completion status from HTT descriptor
  2729. *
  2730. * This function will process HTT Tx indication messages from Target
  2731. *
  2732. * Return: none
  2733. */
  2734. static
  2735. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2736. {
  2737. uint8_t tx_status;
  2738. struct dp_pdev *pdev;
  2739. struct dp_vdev *vdev;
  2740. struct dp_soc *soc;
  2741. struct hal_tx_completion_status ts = {0};
  2742. uint32_t *htt_desc = (uint32_t *)status;
  2743. struct dp_peer *peer;
  2744. struct cdp_tid_tx_stats *tid_stats = NULL;
  2745. qdf_assert(tx_desc->pdev);
  2746. pdev = tx_desc->pdev;
  2747. vdev = tx_desc->vdev;
  2748. soc = pdev->soc;
  2749. if (!vdev)
  2750. return;
  2751. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2752. switch (tx_status) {
  2753. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2754. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2755. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2756. {
  2757. uint8_t tid;
  2758. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2759. ts.peer_id =
  2760. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2761. htt_desc[2]);
  2762. ts.tid =
  2763. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2764. htt_desc[2]);
  2765. } else {
  2766. ts.peer_id = HTT_INVALID_PEER;
  2767. ts.tid = HTT_INVALID_TID;
  2768. }
  2769. ts.ppdu_id =
  2770. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2771. htt_desc[1]);
  2772. ts.ack_frame_rssi =
  2773. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2774. htt_desc[1]);
  2775. ts.first_msdu = 1;
  2776. ts.last_msdu = 1;
  2777. tid = ts.tid;
  2778. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2779. tid = CDP_MAX_DATA_TIDS - 1;
  2780. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[tid];
  2781. if (qdf_unlikely(pdev->delay_stats_flag))
  2782. dp_tx_compute_delay(vdev, tx_desc, tid);
  2783. tid_stats->complete_cnt++;
  2784. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2785. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2786. tid_stats->comp_fail_cnt++;
  2787. } else {
  2788. tid_stats->success_cnt++;
  2789. }
  2790. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2791. if (qdf_likely(peer))
  2792. dp_peer_unref_del_find_by_id(peer);
  2793. dp_tx_comp_process_tx_status(tx_desc, &ts, peer);
  2794. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2795. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2796. break;
  2797. }
  2798. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2799. {
  2800. dp_tx_reinject_handler(tx_desc, status);
  2801. break;
  2802. }
  2803. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2804. {
  2805. dp_tx_inspect_handler(tx_desc, status);
  2806. break;
  2807. }
  2808. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2809. {
  2810. dp_tx_mec_handler(vdev, status);
  2811. break;
  2812. }
  2813. default:
  2814. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2815. "%s Invalid HTT tx_status %d\n",
  2816. __func__, tx_status);
  2817. break;
  2818. }
  2819. }
  2820. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2821. static inline
  2822. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2823. {
  2824. bool limit_hit = false;
  2825. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2826. limit_hit =
  2827. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2828. if (limit_hit)
  2829. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2830. return limit_hit;
  2831. }
  2832. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2833. {
  2834. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2835. }
  2836. #else
  2837. static inline
  2838. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2839. {
  2840. return false;
  2841. }
  2842. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2843. {
  2844. return false;
  2845. }
  2846. #endif
  2847. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2848. void *hal_srng, uint32_t quota)
  2849. {
  2850. void *tx_comp_hal_desc;
  2851. uint8_t buffer_src;
  2852. uint8_t pool_id;
  2853. uint32_t tx_desc_id;
  2854. struct dp_tx_desc_s *tx_desc = NULL;
  2855. struct dp_tx_desc_s *head_desc = NULL;
  2856. struct dp_tx_desc_s *tail_desc = NULL;
  2857. uint32_t num_processed = 0;
  2858. uint32_t count = 0;
  2859. bool force_break = false;
  2860. DP_HIST_INIT();
  2861. more_data:
  2862. /* Re-initialize local variables to be re-used */
  2863. head_desc = NULL;
  2864. tail_desc = NULL;
  2865. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2866. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2867. "%s %d : HAL RING Access Failed -- %pK",
  2868. __func__, __LINE__, hal_srng);
  2869. return 0;
  2870. }
  2871. /* Find head descriptor from completion ring */
  2872. while (qdf_likely(tx_comp_hal_desc =
  2873. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2874. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2875. /* If this buffer was not released by TQM or FW, then it is not
  2876. * Tx completion indication, assert */
  2877. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2878. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2879. QDF_TRACE(QDF_MODULE_ID_DP,
  2880. QDF_TRACE_LEVEL_FATAL,
  2881. "Tx comp release_src != TQM | FW but from %d",
  2882. buffer_src);
  2883. hal_dump_comp_desc(tx_comp_hal_desc);
  2884. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2885. qdf_assert_always(0);
  2886. }
  2887. /* Get descriptor id */
  2888. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2889. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2890. DP_TX_DESC_ID_POOL_OS;
  2891. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2892. continue;
  2893. /* Find Tx descriptor */
  2894. tx_desc = dp_tx_desc_find(soc, pool_id,
  2895. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2896. DP_TX_DESC_ID_PAGE_OS,
  2897. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2898. DP_TX_DESC_ID_OFFSET_OS);
  2899. /*
  2900. * If the descriptor is already freed in vdev_detach,
  2901. * continue to next descriptor
  2902. */
  2903. if (!tx_desc->vdev && !tx_desc->flags) {
  2904. QDF_TRACE(QDF_MODULE_ID_DP,
  2905. QDF_TRACE_LEVEL_INFO,
  2906. "Descriptor freed in vdev_detach %d",
  2907. tx_desc_id);
  2908. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2909. count++;
  2910. continue;
  2911. }
  2912. /*
  2913. * If the release source is FW, process the HTT status
  2914. */
  2915. if (qdf_unlikely(buffer_src ==
  2916. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2917. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2918. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2919. htt_tx_status);
  2920. dp_tx_process_htt_completion(tx_desc,
  2921. htt_tx_status);
  2922. } else {
  2923. /* Pool id is not matching. Error */
  2924. if (tx_desc->pool_id != pool_id) {
  2925. QDF_TRACE(QDF_MODULE_ID_DP,
  2926. QDF_TRACE_LEVEL_FATAL,
  2927. "Tx Comp pool id %d not matched %d",
  2928. pool_id, tx_desc->pool_id);
  2929. qdf_assert_always(0);
  2930. }
  2931. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2932. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2933. QDF_TRACE(QDF_MODULE_ID_DP,
  2934. QDF_TRACE_LEVEL_FATAL,
  2935. "Txdesc invalid, flgs = %x,id = %d",
  2936. tx_desc->flags, tx_desc_id);
  2937. qdf_assert_always(0);
  2938. }
  2939. /* First ring descriptor on the cycle */
  2940. if (!head_desc) {
  2941. head_desc = tx_desc;
  2942. tail_desc = tx_desc;
  2943. }
  2944. tail_desc->next = tx_desc;
  2945. tx_desc->next = NULL;
  2946. tail_desc = tx_desc;
  2947. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  2948. /* Collect hw completion contents */
  2949. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2950. &tx_desc->comp, 1);
  2951. }
  2952. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2953. /*
  2954. * Processed packet count is more than given quota
  2955. * stop to processing
  2956. */
  2957. if (num_processed >= quota) {
  2958. force_break = true;
  2959. break;
  2960. }
  2961. count++;
  2962. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  2963. break;
  2964. }
  2965. hal_srng_access_end(soc->hal_soc, hal_srng);
  2966. /* Process the reaped descriptors */
  2967. if (head_desc)
  2968. dp_tx_comp_process_desc_list(soc, head_desc);
  2969. if (dp_tx_comp_enable_eol_data_check(soc)) {
  2970. if (!force_break &&
  2971. hal_srng_dst_peek_sync_locked(soc, hal_srng)) {
  2972. DP_STATS_INC(soc, tx.hp_oos2, 1);
  2973. if (!hif_exec_should_yield(soc->hif_handle,
  2974. int_ctx->dp_intr_id))
  2975. goto more_data;
  2976. }
  2977. }
  2978. DP_TX_HIST_STATS_PER_PDEV();
  2979. return num_processed;
  2980. }
  2981. #ifdef FEATURE_WLAN_TDLS
  2982. /**
  2983. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2984. *
  2985. * @data_vdev - which vdev should transmit the tx data frames
  2986. * @tx_spec - what non-standard handling to apply to the tx data frames
  2987. * @msdu_list - NULL-terminated list of tx MSDUs
  2988. *
  2989. * Return: NULL on success,
  2990. * nbuf when it fails to send
  2991. */
  2992. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2993. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2994. {
  2995. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2996. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2997. vdev->is_tdls_frame = true;
  2998. return dp_tx_send(vdev_handle, msdu_list);
  2999. }
  3000. #endif
  3001. /**
  3002. * dp_tx_vdev_attach() - attach vdev to dp tx
  3003. * @vdev: virtual device instance
  3004. *
  3005. * Return: QDF_STATUS_SUCCESS: success
  3006. * QDF_STATUS_E_RESOURCES: Error return
  3007. */
  3008. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3009. {
  3010. /*
  3011. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3012. */
  3013. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3014. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3015. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3016. vdev->vdev_id);
  3017. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3018. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3019. /*
  3020. * Set HTT Extension Valid bit to 0 by default
  3021. */
  3022. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3023. dp_tx_vdev_update_search_flags(vdev);
  3024. return QDF_STATUS_SUCCESS;
  3025. }
  3026. #ifdef FEATURE_WDS
  3027. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3028. {
  3029. struct dp_soc *soc = vdev->pdev->soc;
  3030. /*
  3031. * If AST index override support is available (HKv2 etc),
  3032. * DA search flag be enabled always
  3033. *
  3034. * If AST index override support is not available (HKv1),
  3035. * DA search flag should be used for all modes except QWRAP
  3036. */
  3037. if (soc->ast_override_support || !vdev->proxysta_vdev)
  3038. return true;
  3039. return false;
  3040. }
  3041. #else
  3042. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3043. {
  3044. return false;
  3045. }
  3046. #endif
  3047. /**
  3048. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3049. * @vdev: virtual device instance
  3050. *
  3051. * Return: void
  3052. *
  3053. */
  3054. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3055. {
  3056. struct dp_soc *soc = vdev->pdev->soc;
  3057. /*
  3058. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3059. * for TDLS link
  3060. *
  3061. * Enable AddrY (SA based search) only for non-WDS STA and
  3062. * ProxySTA VAP (in HKv1) modes.
  3063. *
  3064. * In all other VAP modes, only DA based search should be
  3065. * enabled
  3066. */
  3067. if (vdev->opmode == wlan_op_mode_sta &&
  3068. vdev->tdls_link_connected)
  3069. vdev->hal_desc_addr_search_flags =
  3070. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3071. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3072. !dp_tx_da_search_override(vdev))
  3073. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3074. else
  3075. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3076. /* Set search type only when peer map v2 messaging is enabled
  3077. * as we will have the search index (AST hash) only when v2 is
  3078. * enabled
  3079. */
  3080. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3081. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3082. else
  3083. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3084. }
  3085. static inline bool
  3086. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3087. struct dp_vdev *vdev,
  3088. struct dp_tx_desc_s *tx_desc)
  3089. {
  3090. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3091. return false;
  3092. /*
  3093. * if vdev is given, then only check whether desc
  3094. * vdev match. if vdev is NULL, then check whether
  3095. * desc pdev match.
  3096. */
  3097. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3098. }
  3099. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3100. /**
  3101. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3102. *
  3103. * @soc: Handle to DP SoC structure
  3104. * @tx_desc: pointer of one TX desc
  3105. * @desc_pool_id: TX Desc pool id
  3106. */
  3107. static inline void
  3108. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3109. uint8_t desc_pool_id)
  3110. {
  3111. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3112. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3113. tx_desc->vdev = NULL;
  3114. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3115. }
  3116. /**
  3117. * dp_tx_desc_flush() - release resources associated
  3118. * to TX Desc
  3119. *
  3120. * @dp_pdev: Handle to DP pdev structure
  3121. * @vdev: virtual device instance
  3122. * NULL: no specific Vdev is required and check all allcated TX desc
  3123. * on this pdev.
  3124. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3125. *
  3126. * @force_free:
  3127. * true: flush the TX desc.
  3128. * false: only reset the Vdev in each allocated TX desc
  3129. * that associated to current Vdev.
  3130. *
  3131. * This function will go through the TX desc pool to flush
  3132. * the outstanding TX data or reset Vdev to NULL in associated TX
  3133. * Desc.
  3134. */
  3135. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3136. struct dp_vdev *vdev,
  3137. bool force_free)
  3138. {
  3139. uint8_t i;
  3140. uint32_t j;
  3141. uint32_t num_desc, page_id, offset;
  3142. uint16_t num_desc_per_page;
  3143. struct dp_soc *soc = pdev->soc;
  3144. struct dp_tx_desc_s *tx_desc = NULL;
  3145. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3146. if (!vdev && !force_free) {
  3147. dp_err("Reset TX desc vdev, Vdev param is required!");
  3148. return;
  3149. }
  3150. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3151. tx_desc_pool = &soc->tx_desc[i];
  3152. if (!(tx_desc_pool->pool_size) ||
  3153. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3154. !(tx_desc_pool->desc_pages.cacheable_pages))
  3155. continue;
  3156. num_desc = tx_desc_pool->pool_size;
  3157. num_desc_per_page =
  3158. tx_desc_pool->desc_pages.num_element_per_page;
  3159. for (j = 0; j < num_desc; j++) {
  3160. page_id = j / num_desc_per_page;
  3161. offset = j % num_desc_per_page;
  3162. if (qdf_unlikely(!(tx_desc_pool->
  3163. desc_pages.cacheable_pages)))
  3164. break;
  3165. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3166. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3167. /*
  3168. * Free TX desc if force free is
  3169. * required, otherwise only reset vdev
  3170. * in this TX desc.
  3171. */
  3172. if (force_free) {
  3173. dp_tx_comp_free_buf(soc, tx_desc);
  3174. dp_tx_desc_release(tx_desc, i);
  3175. } else {
  3176. dp_tx_desc_reset_vdev(soc, tx_desc,
  3177. i);
  3178. }
  3179. }
  3180. }
  3181. }
  3182. }
  3183. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3184. static inline void
  3185. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3186. uint8_t desc_pool_id)
  3187. {
  3188. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3189. tx_desc->vdev = NULL;
  3190. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3191. }
  3192. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3193. struct dp_vdev *vdev,
  3194. bool force_free)
  3195. {
  3196. uint8_t i, num_pool;
  3197. uint32_t j;
  3198. uint32_t num_desc, page_id, offset;
  3199. uint16_t num_desc_per_page;
  3200. struct dp_soc *soc = pdev->soc;
  3201. struct dp_tx_desc_s *tx_desc = NULL;
  3202. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3203. if (!vdev && !force_free) {
  3204. dp_err("Reset TX desc vdev, Vdev param is required!");
  3205. return;
  3206. }
  3207. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3208. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3209. for (i = 0; i < num_pool; i++) {
  3210. tx_desc_pool = &soc->tx_desc[i];
  3211. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3212. continue;
  3213. num_desc_per_page =
  3214. tx_desc_pool->desc_pages.num_element_per_page;
  3215. for (j = 0; j < num_desc; j++) {
  3216. page_id = j / num_desc_per_page;
  3217. offset = j % num_desc_per_page;
  3218. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3219. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3220. if (force_free) {
  3221. dp_tx_comp_free_buf(soc, tx_desc);
  3222. dp_tx_desc_release(tx_desc, i);
  3223. } else {
  3224. dp_tx_desc_reset_vdev(soc, tx_desc,
  3225. i);
  3226. }
  3227. }
  3228. }
  3229. }
  3230. }
  3231. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3232. /**
  3233. * dp_tx_vdev_detach() - detach vdev from dp tx
  3234. * @vdev: virtual device instance
  3235. *
  3236. * Return: QDF_STATUS_SUCCESS: success
  3237. * QDF_STATUS_E_RESOURCES: Error return
  3238. */
  3239. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3240. {
  3241. struct dp_pdev *pdev = vdev->pdev;
  3242. /* Reset TX desc associated to this Vdev as NULL */
  3243. dp_tx_desc_flush(pdev, vdev, false);
  3244. return QDF_STATUS_SUCCESS;
  3245. }
  3246. /**
  3247. * dp_tx_pdev_attach() - attach pdev to dp tx
  3248. * @pdev: physical device instance
  3249. *
  3250. * Return: QDF_STATUS_SUCCESS: success
  3251. * QDF_STATUS_E_RESOURCES: Error return
  3252. */
  3253. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3254. {
  3255. struct dp_soc *soc = pdev->soc;
  3256. /* Initialize Flow control counters */
  3257. qdf_atomic_init(&pdev->num_tx_exception);
  3258. qdf_atomic_init(&pdev->num_tx_outstanding);
  3259. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3260. /* Initialize descriptors in TCL Ring */
  3261. hal_tx_init_data_ring(soc->hal_soc,
  3262. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3263. }
  3264. return QDF_STATUS_SUCCESS;
  3265. }
  3266. /**
  3267. * dp_tx_pdev_detach() - detach pdev from dp tx
  3268. * @pdev: physical device instance
  3269. *
  3270. * Return: QDF_STATUS_SUCCESS: success
  3271. * QDF_STATUS_E_RESOURCES: Error return
  3272. */
  3273. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3274. {
  3275. /* flush TX outstanding data per pdev */
  3276. dp_tx_desc_flush(pdev, NULL, true);
  3277. dp_tx_me_exit(pdev);
  3278. return QDF_STATUS_SUCCESS;
  3279. }
  3280. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3281. /* Pools will be allocated dynamically */
  3282. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3283. int num_desc)
  3284. {
  3285. uint8_t i;
  3286. for (i = 0; i < num_pool; i++) {
  3287. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3288. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3289. }
  3290. return 0;
  3291. }
  3292. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3293. {
  3294. uint8_t i;
  3295. for (i = 0; i < num_pool; i++)
  3296. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3297. }
  3298. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3299. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3300. int num_desc)
  3301. {
  3302. uint8_t i;
  3303. /* Allocate software Tx descriptor pools */
  3304. for (i = 0; i < num_pool; i++) {
  3305. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3306. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3307. "%s Tx Desc Pool alloc %d failed %pK",
  3308. __func__, i, soc);
  3309. return ENOMEM;
  3310. }
  3311. }
  3312. return 0;
  3313. }
  3314. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3315. {
  3316. uint8_t i;
  3317. for (i = 0; i < num_pool; i++) {
  3318. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3319. if (dp_tx_desc_pool_free(soc, i)) {
  3320. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3321. "%s Tx Desc Pool Free failed", __func__);
  3322. }
  3323. }
  3324. }
  3325. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3326. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3327. /**
  3328. * dp_tso_attach_wifi3() - TSO attach handler
  3329. * @txrx_soc: Opaque Dp handle
  3330. *
  3331. * Reserve TSO descriptor buffers
  3332. *
  3333. * Return: QDF_STATUS_E_FAILURE on failure or
  3334. * QDF_STATUS_SUCCESS on success
  3335. */
  3336. static
  3337. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3338. {
  3339. return dp_tso_soc_attach(txrx_soc);
  3340. }
  3341. /**
  3342. * dp_tso_detach_wifi3() - TSO Detach handler
  3343. * @txrx_soc: Opaque Dp handle
  3344. *
  3345. * Deallocate TSO descriptor buffers
  3346. *
  3347. * Return: QDF_STATUS_E_FAILURE on failure or
  3348. * QDF_STATUS_SUCCESS on success
  3349. */
  3350. static
  3351. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3352. {
  3353. return dp_tso_soc_detach(txrx_soc);
  3354. }
  3355. #else
  3356. static
  3357. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3358. {
  3359. return QDF_STATUS_SUCCESS;
  3360. }
  3361. static
  3362. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3363. {
  3364. return QDF_STATUS_SUCCESS;
  3365. }
  3366. #endif
  3367. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3368. {
  3369. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3370. uint8_t i;
  3371. uint8_t num_pool;
  3372. uint32_t num_desc;
  3373. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3374. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3375. for (i = 0; i < num_pool; i++)
  3376. dp_tx_tso_desc_pool_free(soc, i);
  3377. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3378. __func__, num_pool, num_desc);
  3379. for (i = 0; i < num_pool; i++)
  3380. dp_tx_tso_num_seg_pool_free(soc, i);
  3381. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3382. __func__, num_pool, num_desc);
  3383. return QDF_STATUS_SUCCESS;
  3384. }
  3385. /**
  3386. * dp_tso_attach() - TSO attach handler
  3387. * @txrx_soc: Opaque Dp handle
  3388. *
  3389. * Reserve TSO descriptor buffers
  3390. *
  3391. * Return: QDF_STATUS_E_FAILURE on failure or
  3392. * QDF_STATUS_SUCCESS on success
  3393. */
  3394. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3395. {
  3396. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3397. uint8_t i;
  3398. uint8_t num_pool;
  3399. uint32_t num_desc;
  3400. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3401. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3402. for (i = 0; i < num_pool; i++) {
  3403. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3404. dp_err("TSO Desc Pool alloc %d failed %pK",
  3405. i, soc);
  3406. return QDF_STATUS_E_FAILURE;
  3407. }
  3408. }
  3409. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3410. __func__, num_pool, num_desc);
  3411. for (i = 0; i < num_pool; i++) {
  3412. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3413. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3414. i, soc);
  3415. return QDF_STATUS_E_FAILURE;
  3416. }
  3417. }
  3418. return QDF_STATUS_SUCCESS;
  3419. }
  3420. /**
  3421. * dp_tx_soc_detach() - detach soc from dp tx
  3422. * @soc: core txrx main context
  3423. *
  3424. * This function will detach dp tx into main device context
  3425. * will free dp tx resource and initialize resources
  3426. *
  3427. * Return: QDF_STATUS_SUCCESS: success
  3428. * QDF_STATUS_E_RESOURCES: Error return
  3429. */
  3430. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3431. {
  3432. uint8_t num_pool;
  3433. uint16_t num_desc;
  3434. uint16_t num_ext_desc;
  3435. uint8_t i;
  3436. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3437. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3438. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3439. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3440. dp_tx_flow_control_deinit(soc);
  3441. dp_tx_delete_static_pools(soc, num_pool);
  3442. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3443. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3444. __func__, num_pool, num_desc);
  3445. for (i = 0; i < num_pool; i++) {
  3446. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3447. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3448. "%s Tx Ext Desc Pool Free failed",
  3449. __func__);
  3450. return QDF_STATUS_E_RESOURCES;
  3451. }
  3452. }
  3453. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3454. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3455. __func__, num_pool, num_ext_desc);
  3456. status = dp_tso_detach_wifi3(soc);
  3457. if (status != QDF_STATUS_SUCCESS)
  3458. return status;
  3459. return QDF_STATUS_SUCCESS;
  3460. }
  3461. /**
  3462. * dp_tx_soc_attach() - attach soc to dp tx
  3463. * @soc: core txrx main context
  3464. *
  3465. * This function will attach dp tx into main device context
  3466. * will allocate dp tx resource and initialize resources
  3467. *
  3468. * Return: QDF_STATUS_SUCCESS: success
  3469. * QDF_STATUS_E_RESOURCES: Error return
  3470. */
  3471. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3472. {
  3473. uint8_t i;
  3474. uint8_t num_pool;
  3475. uint32_t num_desc;
  3476. uint32_t num_ext_desc;
  3477. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3478. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3479. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3480. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3481. if (num_pool > MAX_TXDESC_POOLS)
  3482. goto fail;
  3483. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3484. goto fail;
  3485. dp_tx_flow_control_init(soc);
  3486. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3487. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3488. __func__, num_pool, num_desc);
  3489. /* Allocate extension tx descriptor pools */
  3490. for (i = 0; i < num_pool; i++) {
  3491. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3492. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3493. "MSDU Ext Desc Pool alloc %d failed %pK",
  3494. i, soc);
  3495. goto fail;
  3496. }
  3497. }
  3498. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3499. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3500. __func__, num_pool, num_ext_desc);
  3501. status = dp_tso_attach_wifi3((void *)soc);
  3502. if (status != QDF_STATUS_SUCCESS)
  3503. goto fail;
  3504. /* Initialize descriptors in TCL Rings */
  3505. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3506. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3507. hal_tx_init_data_ring(soc->hal_soc,
  3508. soc->tcl_data_ring[i].hal_srng);
  3509. }
  3510. }
  3511. /*
  3512. * todo - Add a runtime config option to enable this.
  3513. */
  3514. /*
  3515. * Due to multiple issues on NPR EMU, enable it selectively
  3516. * only for NPR EMU, should be removed, once NPR platforms
  3517. * are stable.
  3518. */
  3519. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3520. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3521. "%s HAL Tx init Success", __func__);
  3522. return QDF_STATUS_SUCCESS;
  3523. fail:
  3524. /* Detach will take care of freeing only allocated resources */
  3525. dp_tx_soc_detach(soc);
  3526. return QDF_STATUS_E_RESOURCES;
  3527. }
  3528. /*
  3529. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3530. * pdev: pointer to DP PDEV structure
  3531. * seg_info_head: Pointer to the head of list
  3532. *
  3533. * return: void
  3534. */
  3535. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3536. struct dp_tx_seg_info_s *seg_info_head)
  3537. {
  3538. struct dp_tx_me_buf_t *mc_uc_buf;
  3539. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3540. qdf_nbuf_t nbuf = NULL;
  3541. uint64_t phy_addr;
  3542. while (seg_info_head) {
  3543. nbuf = seg_info_head->nbuf;
  3544. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3545. seg_info_head->frags[0].vaddr;
  3546. phy_addr = seg_info_head->frags[0].paddr_hi;
  3547. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3548. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3549. phy_addr,
  3550. QDF_DMA_TO_DEVICE , QDF_MAC_ADDR_SIZE);
  3551. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3552. qdf_nbuf_free(nbuf);
  3553. seg_info_new = seg_info_head;
  3554. seg_info_head = seg_info_head->next;
  3555. qdf_mem_free(seg_info_new);
  3556. }
  3557. }
  3558. /**
  3559. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3560. * @vdev: DP VDEV handle
  3561. * @nbuf: Multicast nbuf
  3562. * @newmac: Table of the clients to which packets have to be sent
  3563. * @new_mac_cnt: No of clients
  3564. *
  3565. * return: no of converted packets
  3566. */
  3567. uint16_t
  3568. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3569. uint8_t newmac[][QDF_MAC_ADDR_SIZE], uint8_t new_mac_cnt)
  3570. {
  3571. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3572. struct dp_pdev *pdev = vdev->pdev;
  3573. qdf_ether_header_t *eh;
  3574. uint8_t *data;
  3575. uint16_t len;
  3576. /* reference to frame dst addr */
  3577. uint8_t *dstmac;
  3578. /* copy of original frame src addr */
  3579. uint8_t srcmac[QDF_MAC_ADDR_SIZE];
  3580. /* local index into newmac */
  3581. uint8_t new_mac_idx = 0;
  3582. struct dp_tx_me_buf_t *mc_uc_buf;
  3583. qdf_nbuf_t nbuf_clone;
  3584. struct dp_tx_msdu_info_s msdu_info;
  3585. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3586. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3587. struct dp_tx_seg_info_s *seg_info_new;
  3588. qdf_dma_addr_t paddr_data;
  3589. qdf_dma_addr_t paddr_mcbuf = 0;
  3590. uint8_t empty_entry_mac[QDF_MAC_ADDR_SIZE] = {0};
  3591. QDF_STATUS status;
  3592. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3593. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3594. eh = (qdf_ether_header_t *)nbuf;
  3595. qdf_mem_copy(srcmac, eh->ether_shost, QDF_MAC_ADDR_SIZE);
  3596. len = qdf_nbuf_len(nbuf);
  3597. data = qdf_nbuf_data(nbuf);
  3598. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3599. QDF_DMA_TO_DEVICE);
  3600. if (status) {
  3601. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3602. "Mapping failure Error:%d", status);
  3603. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3604. qdf_nbuf_free(nbuf);
  3605. return 1;
  3606. }
  3607. paddr_data = qdf_nbuf_mapped_paddr_get(nbuf) + QDF_MAC_ADDR_SIZE;
  3608. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3609. dstmac = newmac[new_mac_idx];
  3610. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3611. "added mac addr (%pM)", dstmac);
  3612. /* Check for NULL Mac Address */
  3613. if (!qdf_mem_cmp(dstmac, empty_entry_mac, QDF_MAC_ADDR_SIZE))
  3614. continue;
  3615. /* frame to self mac. skip */
  3616. if (!qdf_mem_cmp(dstmac, srcmac, QDF_MAC_ADDR_SIZE))
  3617. continue;
  3618. /*
  3619. * TODO: optimize to avoid malloc in per-packet path
  3620. * For eg. seg_pool can be made part of vdev structure
  3621. */
  3622. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3623. if (!seg_info_new) {
  3624. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3625. "alloc failed");
  3626. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3627. goto fail_seg_alloc;
  3628. }
  3629. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3630. if (!mc_uc_buf)
  3631. goto fail_buf_alloc;
  3632. /*
  3633. * TODO: Check if we need to clone the nbuf
  3634. * Or can we just use the reference for all cases
  3635. */
  3636. if (new_mac_idx < (new_mac_cnt - 1)) {
  3637. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3638. if (!nbuf_clone) {
  3639. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3640. goto fail_clone;
  3641. }
  3642. } else {
  3643. /*
  3644. * Update the ref
  3645. * to account for frame sent without cloning
  3646. */
  3647. qdf_nbuf_ref(nbuf);
  3648. nbuf_clone = nbuf;
  3649. }
  3650. qdf_mem_copy(mc_uc_buf->data, dstmac, QDF_MAC_ADDR_SIZE);
  3651. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3652. QDF_DMA_TO_DEVICE, QDF_MAC_ADDR_SIZE,
  3653. &paddr_mcbuf);
  3654. if (status) {
  3655. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3656. "Mapping failure Error:%d", status);
  3657. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3658. goto fail_map;
  3659. }
  3660. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3661. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3662. seg_info_new->frags[0].paddr_hi =
  3663. (uint16_t)((uint64_t)paddr_mcbuf >> 32);
  3664. seg_info_new->frags[0].len = QDF_MAC_ADDR_SIZE;
  3665. /*preparing data fragment*/
  3666. seg_info_new->frags[1].vaddr =
  3667. qdf_nbuf_data(nbuf) + QDF_MAC_ADDR_SIZE;
  3668. seg_info_new->frags[1].paddr_lo = (uint32_t)paddr_data;
  3669. seg_info_new->frags[1].paddr_hi =
  3670. (uint16_t)(((uint64_t)paddr_data) >> 32);
  3671. seg_info_new->frags[1].len = len - QDF_MAC_ADDR_SIZE;
  3672. seg_info_new->nbuf = nbuf_clone;
  3673. seg_info_new->frag_cnt = 2;
  3674. seg_info_new->total_len = len;
  3675. seg_info_new->next = NULL;
  3676. if (!seg_info_head)
  3677. seg_info_head = seg_info_new;
  3678. else
  3679. seg_info_tail->next = seg_info_new;
  3680. seg_info_tail = seg_info_new;
  3681. }
  3682. if (!seg_info_head) {
  3683. goto free_return;
  3684. }
  3685. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3686. msdu_info.num_seg = new_mac_cnt;
  3687. msdu_info.frm_type = dp_tx_frm_me;
  3688. msdu_info.tid = HTT_INVALID_TID;
  3689. if (qdf_unlikely(vdev->mcast_enhancement_en > 0) &&
  3690. qdf_unlikely(pdev->hmmc_tid_override_en))
  3691. msdu_info.tid = pdev->hmmc_tid;
  3692. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3693. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3694. while (seg_info_head->next) {
  3695. seg_info_new = seg_info_head;
  3696. seg_info_head = seg_info_head->next;
  3697. qdf_mem_free(seg_info_new);
  3698. }
  3699. qdf_mem_free(seg_info_head);
  3700. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3701. qdf_nbuf_free(nbuf);
  3702. return new_mac_cnt;
  3703. fail_map:
  3704. qdf_nbuf_free(nbuf_clone);
  3705. fail_clone:
  3706. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3707. fail_buf_alloc:
  3708. qdf_mem_free(seg_info_new);
  3709. fail_seg_alloc:
  3710. dp_tx_me_mem_free(pdev, seg_info_head);
  3711. free_return:
  3712. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3713. qdf_nbuf_free(nbuf);
  3714. return 1;
  3715. }