sde_plane.c 128 KB

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  1. /*
  2. * Copyright (C) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/debugfs.h>
  20. #include <linux/dma-buf.h>
  21. #include <drm/sde_drm.h>
  22. #include <drm/msm_drm_pp.h>
  23. #include "msm_prop.h"
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include "sde_fence.h"
  27. #include "sde_formats.h"
  28. #include "sde_hw_sspp.h"
  29. #include "sde_hw_catalog_format.h"
  30. #include "sde_trace.h"
  31. #include "sde_crtc.h"
  32. #include "sde_vbif.h"
  33. #include "sde_plane.h"
  34. #include "sde_color_processing.h"
  35. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  36. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  37. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  40. #define PHASE_STEP_SHIFT 21
  41. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  42. #define PHASE_RESIDUAL 15
  43. #define SHARP_STRENGTH_DEFAULT 32
  44. #define SHARP_EDGE_THR_DEFAULT 112
  45. #define SHARP_SMOOTH_THR_DEFAULT 8
  46. #define SHARP_NOISE_THR_DEFAULT 2
  47. #define SDE_NAME_SIZE 12
  48. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  49. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  50. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  51. /* multirect rect index */
  52. enum {
  53. R0,
  54. R1,
  55. R_MAX
  56. };
  57. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  58. #define DEFAULT_REFRESH_RATE 60
  59. /**
  60. * enum sde_plane_qos - Different qos configurations for each pipe
  61. *
  62. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  63. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  64. * this configuration is mutually exclusive from VBLANK_CTRL.
  65. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  66. */
  67. enum sde_plane_qos {
  68. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  69. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  70. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  71. };
  72. /*
  73. * struct sde_plane - local sde plane structure
  74. * @aspace: address space pointer
  75. * @csc_cfg: Decoded user configuration for csc
  76. * @csc_usr_ptr: Points to csc_cfg if valid user config available
  77. * @csc_ptr: Points to sde_csc_cfg structure to use for current
  78. * @mplane_list: List of multirect planes of the same pipe
  79. * @catalog: Points to sde catalog structure
  80. * @revalidate: force revalidation of all the plane properties
  81. * @xin_halt_forced_clk: whether or not clocks were forced on for xin halt
  82. * @blob_rot_caps: Pointer to rotator capability blob
  83. */
  84. struct sde_plane {
  85. struct drm_plane base;
  86. struct mutex lock;
  87. enum sde_sspp pipe;
  88. uint32_t features; /* capabilities from catalog */
  89. uint32_t perf_features; /* perf capabilities from catalog */
  90. uint32_t nformats;
  91. uint32_t formats[64];
  92. struct sde_hw_pipe *pipe_hw;
  93. struct sde_hw_pipe_cfg pipe_cfg;
  94. struct sde_hw_sharp_cfg sharp_cfg;
  95. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  96. uint32_t color_fill;
  97. bool is_error;
  98. bool is_rt_pipe;
  99. bool is_virtual;
  100. struct list_head mplane_list;
  101. struct sde_mdss_cfg *catalog;
  102. bool revalidate;
  103. bool xin_halt_forced_clk;
  104. struct sde_csc_cfg csc_cfg;
  105. struct sde_csc_cfg *csc_usr_ptr;
  106. struct sde_csc_cfg *csc_ptr;
  107. const struct sde_sspp_sub_blks *pipe_sblk;
  108. char pipe_name[SDE_NAME_SIZE];
  109. struct msm_property_info property_info;
  110. struct msm_property_data property_data[PLANE_PROP_COUNT];
  111. struct drm_property_blob *blob_info;
  112. struct drm_property_blob *blob_rot_caps;
  113. /* debugfs related stuff */
  114. struct dentry *debugfs_root;
  115. bool debugfs_default_scale;
  116. };
  117. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  118. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  119. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  120. {
  121. struct msm_drm_private *priv;
  122. if (!plane || !plane->dev)
  123. return NULL;
  124. priv = plane->dev->dev_private;
  125. if (!priv)
  126. return NULL;
  127. return to_sde_kms(priv->kms);
  128. }
  129. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  130. {
  131. struct drm_plane_state *pstate = NULL;
  132. struct drm_crtc *drm_crtc = NULL;
  133. struct sde_crtc *sde_crtc = NULL;
  134. struct sde_crtc_mixer *mixer = NULL;
  135. struct sde_hw_ctl *ctl = NULL;
  136. if (!plane) {
  137. DRM_ERROR("Invalid plane %pK\n", plane);
  138. return NULL;
  139. }
  140. pstate = plane->state;
  141. if (!pstate) {
  142. DRM_ERROR("Invalid plane state %pK\n", pstate);
  143. return NULL;
  144. }
  145. drm_crtc = pstate->crtc;
  146. if (!drm_crtc) {
  147. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  148. return NULL;
  149. }
  150. sde_crtc = to_sde_crtc(drm_crtc);
  151. if (!sde_crtc) {
  152. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  153. return NULL;
  154. }
  155. /* it will always return the first mixer and single CTL */
  156. mixer = sde_crtc->mixers;
  157. if (!mixer) {
  158. DRM_ERROR("invalid mixer %pK\n", mixer);
  159. return NULL;
  160. }
  161. ctl = mixer->hw_ctl;
  162. if (!mixer) {
  163. DRM_ERROR("invalid ctl %pK\n", ctl);
  164. return NULL;
  165. }
  166. return ctl;
  167. }
  168. static bool sde_plane_enabled(const struct drm_plane_state *state)
  169. {
  170. return state && state->fb && state->crtc;
  171. }
  172. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  173. {
  174. struct sde_plane *psde;
  175. if (!plane)
  176. return false;
  177. psde = to_sde_plane(plane);
  178. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  179. }
  180. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  181. enum sde_sspp_multirect_index rect_mode, bool enable)
  182. {
  183. struct sde_plane *psde;
  184. if (!plane)
  185. return;
  186. psde = to_sde_plane(plane);
  187. if (psde->pipe_hw->ops.set_src_split_order)
  188. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  189. rect_mode, enable);
  190. }
  191. /**
  192. * _sde_plane_set_qos_lut - set danger, safe and creq LUT of the given plane
  193. * @plane: Pointer to drm plane
  194. * @crtc: Pointer to drm crtc to find refresh rate on mode
  195. * @fb: Pointer to framebuffer associated with the given plane
  196. */
  197. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  198. struct drm_crtc *crtc,
  199. struct drm_framebuffer *fb)
  200. {
  201. struct sde_plane *psde;
  202. const struct sde_format *fmt = NULL;
  203. u32 frame_rate, qos_count, fps_index = 0, lut_index, index;
  204. struct sde_perf_cfg *perf;
  205. struct sde_plane_state *pstate;
  206. if (!plane || !fb) {
  207. SDE_ERROR("invalid arguments\n");
  208. return;
  209. }
  210. psde = to_sde_plane(plane);
  211. pstate = to_sde_plane_state(plane->state);
  212. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  213. SDE_ERROR("invalid arguments\n");
  214. return;
  215. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  216. return;
  217. }
  218. frame_rate = crtc->mode.vrefresh;
  219. perf = &psde->catalog->perf;
  220. qos_count = perf->qos_refresh_count;
  221. while (qos_count && perf->qos_refresh_rate) {
  222. if (frame_rate >= perf->qos_refresh_rate[qos_count - 1]) {
  223. fps_index = qos_count - 1;
  224. break;
  225. }
  226. qos_count--;
  227. }
  228. if (!psde->is_rt_pipe) {
  229. lut_index = SDE_QOS_LUT_USAGE_NRT;
  230. } else {
  231. fmt = sde_get_sde_format_ext(
  232. fb->format->format,
  233. fb->modifier);
  234. if (fmt && SDE_FORMAT_IS_LINEAR(fmt) &&
  235. pstate->scaler3_cfg.enable)
  236. lut_index = SDE_QOS_LUT_USAGE_LINEAR_QSEED;
  237. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  238. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  239. else if (pstate->scaler3_cfg.enable)
  240. lut_index = SDE_QOS_LUT_USAGE_MACROTILE_QSEED;
  241. else
  242. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  243. }
  244. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  245. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[index];
  246. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[index];
  247. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[index];
  248. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
  249. (fmt) ? fmt->base.pixel_format : 0,
  250. (fmt) ? fmt->fetch_mode : 0,
  251. psde->pipe_qos_cfg.danger_lut,
  252. psde->pipe_qos_cfg.safe_lut,
  253. psde->pipe_qos_cfg.creq_lut);
  254. SDE_DEBUG(
  255. "plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  256. plane->base.id,
  257. psde->pipe - SSPP_VIG0,
  258. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  259. fmt ? fmt->fetch_mode : -1,
  260. psde->pipe_qos_cfg.danger_lut,
  261. psde->pipe_qos_cfg.safe_lut,
  262. psde->pipe_qos_cfg.creq_lut);
  263. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  264. }
  265. /**
  266. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  267. * @plane: Pointer to drm plane
  268. * @enable: true to enable QoS control
  269. * @flags: QoS control mode (enum sde_plane_qos)
  270. */
  271. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  272. bool enable, u32 flags)
  273. {
  274. struct sde_plane *psde;
  275. if (!plane) {
  276. SDE_ERROR("invalid arguments\n");
  277. return;
  278. }
  279. psde = to_sde_plane(plane);
  280. if (!psde->pipe_hw || !psde->pipe_sblk) {
  281. SDE_ERROR("invalid arguments\n");
  282. return;
  283. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  284. return;
  285. }
  286. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  287. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  288. psde->pipe_qos_cfg.danger_vblank =
  289. psde->pipe_sblk->danger_vblank;
  290. psde->pipe_qos_cfg.vblank_en = enable;
  291. }
  292. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  293. /* this feature overrules previous VBLANK_CTRL */
  294. psde->pipe_qos_cfg.vblank_en = false;
  295. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  296. }
  297. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  298. psde->pipe_qos_cfg.danger_safe_en = enable;
  299. if (!psde->is_rt_pipe) {
  300. psde->pipe_qos_cfg.vblank_en = false;
  301. psde->pipe_qos_cfg.danger_safe_en = false;
  302. }
  303. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  304. plane->base.id,
  305. psde->pipe - SSPP_VIG0,
  306. psde->pipe_qos_cfg.danger_safe_en,
  307. psde->pipe_qos_cfg.vblank_en,
  308. psde->pipe_qos_cfg.creq_vblank,
  309. psde->pipe_qos_cfg.danger_vblank,
  310. psde->is_rt_pipe);
  311. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  312. &psde->pipe_qos_cfg);
  313. }
  314. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  315. {
  316. struct sde_plane *psde;
  317. if (!plane)
  318. return;
  319. psde = to_sde_plane(plane);
  320. psde->revalidate = enable;
  321. }
  322. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  323. {
  324. struct sde_plane *psde;
  325. int rc;
  326. if (!plane) {
  327. SDE_ERROR("invalid arguments\n");
  328. return -EINVAL;
  329. }
  330. psde = to_sde_plane(plane);
  331. if (!psde->is_rt_pipe)
  332. goto end;
  333. rc = pm_runtime_get_sync(plane->dev->dev);
  334. if (rc < 0) {
  335. SDE_ERROR("failed to enable power resource %d\n", rc);
  336. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  337. return rc;
  338. }
  339. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  340. pm_runtime_put_sync(plane->dev->dev);
  341. end:
  342. return 0;
  343. }
  344. /**
  345. * _sde_plane_set_ot_limit - set OT limit for the given plane
  346. * @plane: Pointer to drm plane
  347. * @crtc: Pointer to drm crtc
  348. */
  349. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  350. struct drm_crtc *crtc)
  351. {
  352. struct sde_plane *psde;
  353. struct sde_vbif_set_ot_params ot_params;
  354. struct msm_drm_private *priv;
  355. struct sde_kms *sde_kms;
  356. if (!plane || !plane->dev || !crtc) {
  357. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  358. !plane, !crtc);
  359. return;
  360. }
  361. priv = plane->dev->dev_private;
  362. if (!priv || !priv->kms) {
  363. SDE_ERROR("invalid KMS reference\n");
  364. return;
  365. }
  366. sde_kms = to_sde_kms(priv->kms);
  367. psde = to_sde_plane(plane);
  368. if (!psde->pipe_hw) {
  369. SDE_ERROR("invalid pipe reference\n");
  370. return;
  371. }
  372. memset(&ot_params, 0, sizeof(ot_params));
  373. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  374. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  375. ot_params.width = psde->pipe_cfg.src_rect.w;
  376. ot_params.height = psde->pipe_cfg.src_rect.h;
  377. ot_params.is_wfd = !psde->is_rt_pipe;
  378. ot_params.frame_rate = crtc->mode.vrefresh;
  379. ot_params.vbif_idx = VBIF_RT;
  380. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  381. ot_params.rd = true;
  382. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  383. }
  384. /**
  385. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  386. * @plane: Pointer to drm plane
  387. */
  388. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  389. {
  390. struct sde_plane *psde;
  391. struct sde_vbif_set_qos_params qos_params;
  392. struct msm_drm_private *priv;
  393. struct sde_kms *sde_kms;
  394. if (!plane || !plane->dev) {
  395. SDE_ERROR("invalid arguments\n");
  396. return;
  397. }
  398. priv = plane->dev->dev_private;
  399. if (!priv || !priv->kms) {
  400. SDE_ERROR("invalid KMS reference\n");
  401. return;
  402. }
  403. sde_kms = to_sde_kms(priv->kms);
  404. psde = to_sde_plane(plane);
  405. if (!psde->pipe_hw) {
  406. SDE_ERROR("invalid pipe reference\n");
  407. return;
  408. }
  409. memset(&qos_params, 0, sizeof(qos_params));
  410. qos_params.vbif_idx = VBIF_RT;
  411. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  412. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  413. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  414. qos_params.client_type = psde->is_rt_pipe ?
  415. VBIF_RT_CLIENT : VBIF_NRT_CLIENT;
  416. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  417. plane->base.id, qos_params.num,
  418. qos_params.vbif_idx,
  419. qos_params.xin_id, qos_params.client_type,
  420. qos_params.clk_ctrl);
  421. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  422. }
  423. /**
  424. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  425. * @plane: Pointer to drm plane
  426. * @pstate: Pointer to sde plane state
  427. */
  428. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  429. struct sde_plane_state *pstate)
  430. {
  431. struct sde_plane *psde;
  432. struct sde_hw_pipe_ts_cfg cfg;
  433. struct msm_drm_private *priv;
  434. struct sde_kms *sde_kms;
  435. if (!plane || !plane->dev) {
  436. SDE_ERROR("invalid arguments");
  437. return;
  438. }
  439. priv = plane->dev->dev_private;
  440. if (!priv || !priv->kms) {
  441. SDE_ERROR("invalid KMS reference\n");
  442. return;
  443. }
  444. sde_kms = to_sde_kms(priv->kms);
  445. psde = to_sde_plane(plane);
  446. if (!psde->pipe_hw) {
  447. SDE_ERROR("invalid pipe reference\n");
  448. return;
  449. }
  450. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  451. return;
  452. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  453. memset(&cfg, 0, sizeof(cfg));
  454. cfg.size = sde_plane_get_property(pstate,
  455. PLANE_PROP_PREFILL_SIZE);
  456. cfg.time = sde_plane_get_property(pstate,
  457. PLANE_PROP_PREFILL_TIME);
  458. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  459. plane->base.id, cfg.size, cfg.time);
  460. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  461. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  462. pstate->multirect_index);
  463. }
  464. /* helper to update a state's input fence pointer from the property */
  465. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  466. struct sde_plane_state *pstate, uint64_t fd)
  467. {
  468. if (!psde || !pstate) {
  469. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  470. !psde, !pstate);
  471. return;
  472. }
  473. /* clear previous reference */
  474. if (pstate->input_fence)
  475. sde_sync_put(pstate->input_fence);
  476. /* get fence pointer for later */
  477. if (fd == 0)
  478. pstate->input_fence = NULL;
  479. else
  480. pstate->input_fence = sde_sync_get(fd);
  481. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  482. }
  483. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  484. {
  485. struct sde_plane *psde;
  486. struct sde_plane_state *pstate;
  487. uint32_t prefix;
  488. void *input_fence;
  489. int ret = -EINVAL;
  490. signed long rc;
  491. if (!plane) {
  492. SDE_ERROR("invalid plane\n");
  493. } else if (!plane->state) {
  494. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  495. } else {
  496. psde = to_sde_plane(plane);
  497. pstate = to_sde_plane_state(plane->state);
  498. input_fence = pstate->input_fence;
  499. if (input_fence) {
  500. prefix = sde_sync_get_name_prefix(input_fence);
  501. rc = sde_sync_wait(input_fence, wait_ms);
  502. switch (rc) {
  503. case 0:
  504. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %d\n",
  505. wait_ms, prefix, sde_plane_get_property(pstate,
  506. PLANE_PROP_INPUT_FENCE));
  507. psde->is_error = true;
  508. sde_kms_timeline_status(plane->dev);
  509. ret = -ETIMEDOUT;
  510. break;
  511. case -ERESTARTSYS:
  512. SDE_ERROR_PLANE(psde,
  513. "%ums wait interrupted on %08X\n",
  514. wait_ms, prefix);
  515. psde->is_error = true;
  516. ret = -ERESTARTSYS;
  517. break;
  518. case -EINVAL:
  519. SDE_ERROR_PLANE(psde,
  520. "invalid fence param for %08X\n",
  521. prefix);
  522. psde->is_error = true;
  523. ret = -EINVAL;
  524. break;
  525. default:
  526. SDE_DEBUG_PLANE(psde, "signaled\n");
  527. ret = 0;
  528. break;
  529. }
  530. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  531. } else {
  532. ret = 0;
  533. }
  534. }
  535. return ret;
  536. }
  537. /**
  538. * _sde_plane_get_aspace: gets the address space based on the
  539. * fb_translation mode property
  540. */
  541. static int _sde_plane_get_aspace(
  542. struct sde_plane *psde,
  543. struct sde_plane_state *pstate,
  544. struct msm_gem_address_space **aspace)
  545. {
  546. struct sde_kms *kms;
  547. int mode;
  548. if (!psde || !pstate || !aspace) {
  549. SDE_ERROR("invalid parameters\n");
  550. return -EINVAL;
  551. }
  552. kms = _sde_plane_get_kms(&psde->base);
  553. if (!kms) {
  554. SDE_ERROR("invalid kms\n");
  555. return -EINVAL;
  556. }
  557. mode = sde_plane_get_property(pstate,
  558. PLANE_PROP_FB_TRANSLATION_MODE);
  559. switch (mode) {
  560. case SDE_DRM_FB_NON_SEC:
  561. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  562. if (!aspace)
  563. return -EINVAL;
  564. break;
  565. case SDE_DRM_FB_SEC:
  566. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  567. if (!aspace)
  568. return -EINVAL;
  569. break;
  570. case SDE_DRM_FB_SEC_DIR_TRANS:
  571. *aspace = NULL;
  572. break;
  573. default:
  574. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  575. return -EFAULT;
  576. }
  577. return 0;
  578. }
  579. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  580. struct sde_plane_state *pstate,
  581. struct sde_hw_pipe_cfg *pipe_cfg,
  582. struct drm_framebuffer *fb)
  583. {
  584. struct sde_plane *psde;
  585. struct msm_gem_address_space *aspace = NULL;
  586. int ret, mode;
  587. bool secure = false;
  588. if (!plane || !pstate || !pipe_cfg || !fb) {
  589. SDE_ERROR(
  590. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  591. !plane, !pstate, !pipe_cfg, !fb);
  592. return;
  593. }
  594. psde = to_sde_plane(plane);
  595. if (!psde->pipe_hw) {
  596. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  597. return;
  598. }
  599. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  600. if (ret) {
  601. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  602. return;
  603. }
  604. /*
  605. * framebuffer prepare is deferred for prepare_fb calls that
  606. * happen during the transition from secure to non-secure.
  607. * Handle the prepare at this point for such cases. This can be
  608. * expected for one or two frames during the transition.
  609. */
  610. if (aspace && pstate->defer_prepare_fb) {
  611. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  612. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  613. if (ret) {
  614. SDE_ERROR_PLANE(psde,
  615. "failed to prepare framebuffer %d\n", ret);
  616. return;
  617. }
  618. pstate->defer_prepare_fb = false;
  619. }
  620. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  621. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  622. secure = true;
  623. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  624. if (ret == -EAGAIN)
  625. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  626. else if (ret) {
  627. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  628. /*
  629. * Force solid fill color on error. This is to prevent
  630. * smmu faults during secure session transition.
  631. */
  632. psde->is_error = true;
  633. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  634. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  635. pipe_cfg->layout.width,
  636. pipe_cfg->layout.height,
  637. pipe_cfg->layout.plane_addr[0],
  638. pipe_cfg->layout.plane_size[0],
  639. pipe_cfg->layout.plane_addr[1],
  640. pipe_cfg->layout.plane_size[1],
  641. pipe_cfg->layout.plane_addr[2],
  642. pipe_cfg->layout.plane_size[2],
  643. pipe_cfg->layout.plane_addr[3],
  644. pipe_cfg->layout.plane_size[3],
  645. pstate->multirect_index,
  646. secure);
  647. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  648. pstate->multirect_index);
  649. }
  650. }
  651. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  652. struct sde_plane_state *pstate)
  653. {
  654. struct sde_hw_scaler3_cfg *cfg;
  655. int ret = 0;
  656. if (!psde || !pstate) {
  657. SDE_ERROR("invalid args\n");
  658. return -EINVAL;
  659. }
  660. cfg = &pstate->scaler3_cfg;
  661. cfg->dir_lut = msm_property_get_blob(
  662. &psde->property_info,
  663. &pstate->property_state, &cfg->dir_len,
  664. PLANE_PROP_SCALER_LUT_ED);
  665. cfg->cir_lut = msm_property_get_blob(
  666. &psde->property_info,
  667. &pstate->property_state, &cfg->cir_len,
  668. PLANE_PROP_SCALER_LUT_CIR);
  669. cfg->sep_lut = msm_property_get_blob(
  670. &psde->property_info,
  671. &pstate->property_state, &cfg->sep_len,
  672. PLANE_PROP_SCALER_LUT_SEP);
  673. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  674. ret = -ENODATA;
  675. return ret;
  676. }
  677. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  678. struct sde_plane_state *pstate)
  679. {
  680. struct sde_hw_scaler3_cfg *cfg;
  681. cfg = &pstate->scaler3_cfg;
  682. cfg->sep_lut = msm_property_get_blob(
  683. &psde->property_info,
  684. &pstate->property_state, &cfg->sep_len,
  685. PLANE_PROP_SCALER_LUT_SEP);
  686. return cfg->sep_lut ? 0 : -ENODATA;
  687. }
  688. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  689. struct sde_plane_state *pstate, const struct sde_format *fmt,
  690. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  691. {
  692. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  693. struct sde_hw_scaler3_cfg *scale_cfg;
  694. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  695. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  696. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  697. if (!psde || !pstate || !fmt ||
  698. !chroma_subsmpl_h || !chroma_subsmpl_v) {
  699. SDE_ERROR("psde %d pstate %d fmt %d smp_h %d smp_v %d\n",
  700. !!psde, !!pstate, !!fmt, chroma_subsmpl_h,
  701. chroma_subsmpl_v);
  702. return;
  703. }
  704. scale_cfg = &pstate->scaler3_cfg;
  705. pd_cfg = &pstate->pre_down;
  706. src_w = psde->pipe_cfg.src_rect.w;
  707. src_h = psde->pipe_cfg.src_rect.h;
  708. dst_w = psde->pipe_cfg.dst_rect.w;
  709. dst_h = psde->pipe_cfg.dst_rect.h;
  710. memset(scale_cfg, 0, sizeof(*scale_cfg));
  711. memset(&pstate->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  712. /*
  713. * For inline rotation cases, scaler config is post-rotation,
  714. * so swap the dimensions here. However, pixel extension will
  715. * need pre-rotation settings, this will be corrected below
  716. * when calculating pixel extension settings.
  717. */
  718. if (inline_rotation)
  719. swap(src_w, src_h);
  720. decimated = DECIMATED_DIMENSION(src_w,
  721. psde->pipe_cfg.horz_decimation);
  722. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  723. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  724. decimated = DECIMATED_DIMENSION(src_h,
  725. psde->pipe_cfg.vert_decimation);
  726. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  727. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  728. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  729. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  730. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  731. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  732. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  733. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  734. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  735. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  736. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  737. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  738. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  739. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  740. for (i = 0; i < SDE_MAX_PLANES; i++) {
  741. /*
  742. * For inline rotation cases with pre-downscaling enabled
  743. * set x pre-downscale value if required. Only x direction
  744. * is currently supported. Use src_h as values have been swapped
  745. * and x direction corresponds to height value.
  746. */
  747. src_h_pre_down = src_h;
  748. if (pre_down_supported && inline_rotation) {
  749. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  750. src_h_pre_down = src_h / 2;
  751. }
  752. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  753. psde->pipe_cfg.horz_decimation);
  754. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  755. psde->pipe_cfg.vert_decimation);
  756. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  757. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  758. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  759. }
  760. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  761. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  762. /* For pixel extension we need the pre-rotated orientation */
  763. if (inline_rotation) {
  764. pstate->pixel_ext.num_ext_pxls_top[i] =
  765. scale_cfg->src_width[i];
  766. pstate->pixel_ext.num_ext_pxls_left[i] =
  767. scale_cfg->src_height[i];
  768. } else {
  769. pstate->pixel_ext.num_ext_pxls_top[i] =
  770. scale_cfg->src_height[i];
  771. pstate->pixel_ext.num_ext_pxls_left[i] =
  772. scale_cfg->src_width[i];
  773. }
  774. }
  775. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  776. && (src_w == dst_w) && !inline_rotation) ||
  777. pstate->multirect_mode)
  778. return;
  779. SDE_DEBUG_PLANE(psde,
  780. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  781. src_w, src_h, dst_w, dst_h,
  782. chroma_subsmpl_v, chroma_subsmpl_h,
  783. fmt->base.pixel_format);
  784. scale_cfg->dst_width = dst_w;
  785. scale_cfg->dst_height = dst_h;
  786. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  787. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  788. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  789. scale_cfg->lut_flag = 0;
  790. scale_cfg->blend_cfg = 1;
  791. scale_cfg->enable = 1;
  792. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  793. }
  794. /**
  795. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  796. * @psde: Pointer to SDE plane object
  797. * @src: Source size
  798. * @dst: Destination size
  799. * @phase_steps: Pointer to output array for phase steps
  800. * @filter: Pointer to output array for filter type
  801. * @fmt: Pointer to format definition
  802. * @chroma_subsampling: Subsampling amount for chroma channel
  803. *
  804. * Returns: 0 on success
  805. */
  806. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  807. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  808. enum sde_hw_filter *filter, const struct sde_format *fmt,
  809. uint32_t chroma_subsampling)
  810. {
  811. if (!psde || !phase_steps || !filter || !fmt) {
  812. SDE_ERROR(
  813. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  814. !psde, !phase_steps, !filter, !fmt);
  815. return -EINVAL;
  816. }
  817. /* calculate phase steps, leave init phase as zero */
  818. phase_steps[SDE_SSPP_COMP_0] =
  819. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  820. phase_steps[SDE_SSPP_COMP_1_2] =
  821. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  822. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  823. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  824. /* calculate scaler config, if necessary */
  825. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  826. filter[SDE_SSPP_COMP_3] =
  827. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  828. SDE_SCALE_FILTER_PCMN;
  829. if (SDE_FORMAT_IS_YUV(fmt)) {
  830. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  831. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  832. } else {
  833. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  834. filter[SDE_SSPP_COMP_1_2] =
  835. SDE_SCALE_FILTER_NEAREST;
  836. }
  837. } else {
  838. /* disable scaler */
  839. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  840. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  841. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  842. }
  843. return 0;
  844. }
  845. /**
  846. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  847. * @psde: Pointer to SDE plane object
  848. * @src: Source size
  849. * @dst: Destination size
  850. * @decimated_src: Source size after decimation, if any
  851. * @phase_steps: Pointer to output array for phase steps
  852. * @out_src: Output array for pixel extension values
  853. * @out_edge1: Output array for pixel extension first edge
  854. * @out_edge2: Output array for pixel extension second edge
  855. * @filter: Pointer to array for filter type
  856. * @fmt: Pointer to format definition
  857. * @chroma_subsampling: Subsampling amount for chroma channel
  858. * @post_compare: Whether to chroma subsampled source size for comparisions
  859. */
  860. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  861. uint32_t src, uint32_t dst, uint32_t decimated_src,
  862. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  863. int *out_edge2, enum sde_hw_filter *filter,
  864. const struct sde_format *fmt, uint32_t chroma_subsampling,
  865. bool post_compare)
  866. {
  867. int64_t edge1, edge2, caf;
  868. uint32_t src_work;
  869. int i, tmp;
  870. if (psde && phase_steps && out_src && out_edge1 &&
  871. out_edge2 && filter && fmt) {
  872. /* handle CAF for YUV formats */
  873. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  874. caf = PHASE_STEP_UNIT_SCALE;
  875. else
  876. caf = 0;
  877. for (i = 0; i < SDE_MAX_PLANES; i++) {
  878. src_work = decimated_src;
  879. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  880. src_work /= chroma_subsampling;
  881. if (post_compare)
  882. src = src_work;
  883. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  884. /* unity */
  885. edge1 = 0;
  886. edge2 = 0;
  887. } else if (dst >= src) {
  888. /* upscale */
  889. edge1 = (1 << PHASE_RESIDUAL);
  890. edge1 -= caf;
  891. edge2 = (1 << PHASE_RESIDUAL);
  892. edge2 += (dst - 1) * *(phase_steps + i);
  893. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  894. edge2 += caf;
  895. edge2 = -(edge2);
  896. } else {
  897. /* downscale */
  898. edge1 = 0;
  899. edge2 = (dst - 1) * *(phase_steps + i);
  900. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  901. edge2 += *(phase_steps + i);
  902. edge2 = -(edge2);
  903. }
  904. /* only enable CAF for luma plane */
  905. caf = 0;
  906. /* populate output arrays */
  907. *(out_src + i) = src_work;
  908. /* edge updates taken from __pxl_extn_helper */
  909. if (edge1 >= 0) {
  910. tmp = (uint32_t)edge1;
  911. tmp >>= PHASE_STEP_SHIFT;
  912. *(out_edge1 + i) = -tmp;
  913. } else {
  914. tmp = (uint32_t)(-edge1);
  915. *(out_edge1 + i) =
  916. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  917. PHASE_STEP_SHIFT;
  918. }
  919. if (edge2 >= 0) {
  920. tmp = (uint32_t)edge2;
  921. tmp >>= PHASE_STEP_SHIFT;
  922. *(out_edge2 + i) = -tmp;
  923. } else {
  924. tmp = (uint32_t)(-edge2);
  925. *(out_edge2 + i) =
  926. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  927. PHASE_STEP_SHIFT;
  928. }
  929. }
  930. }
  931. }
  932. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  933. {
  934. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  935. {
  936. /* S15.16 format */
  937. 0x00012A00, 0x00000000, 0x00019880,
  938. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  939. 0x00012A00, 0x00020480, 0x00000000,
  940. },
  941. /* signed bias */
  942. { 0xfff0, 0xff80, 0xff80,},
  943. { 0x0, 0x0, 0x0,},
  944. /* unsigned clamp */
  945. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  946. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  947. };
  948. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  949. {
  950. /* S15.16 format */
  951. 0x00012A00, 0x00000000, 0x00019880,
  952. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  953. 0x00012A00, 0x00020480, 0x00000000,
  954. },
  955. /* signed bias */
  956. { 0xffc0, 0xfe00, 0xfe00,},
  957. { 0x0, 0x0, 0x0,},
  958. /* unsigned clamp */
  959. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  960. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  961. };
  962. if (!psde) {
  963. SDE_ERROR("invalid plane\n");
  964. return;
  965. }
  966. /* revert to kernel default if override not available */
  967. if (psde->csc_usr_ptr)
  968. psde->csc_ptr = psde->csc_usr_ptr;
  969. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  970. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  971. else
  972. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  973. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  974. psde->csc_ptr->csc_mv[0],
  975. psde->csc_ptr->csc_mv[1],
  976. psde->csc_ptr->csc_mv[2]);
  977. }
  978. static void sde_color_process_plane_setup(struct drm_plane *plane)
  979. {
  980. struct sde_plane *psde;
  981. struct sde_plane_state *pstate;
  982. uint32_t hue, saturation, value, contrast;
  983. struct drm_msm_memcol *memcol = NULL;
  984. struct drm_msm_3d_gamut *vig_gamut = NULL;
  985. struct drm_msm_igc_lut *igc = NULL;
  986. struct drm_msm_pgc_lut *gc = NULL;
  987. size_t memcol_sz = 0, size = 0;
  988. struct sde_hw_cp_cfg hw_cfg = {};
  989. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  990. psde = to_sde_plane(plane);
  991. pstate = to_sde_plane_state(plane->state);
  992. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  993. if (psde->pipe_hw->ops.setup_pa_hue)
  994. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  995. saturation = (uint32_t) sde_plane_get_property(pstate,
  996. PLANE_PROP_SATURATION_ADJUST);
  997. if (psde->pipe_hw->ops.setup_pa_sat)
  998. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  999. value = (uint32_t) sde_plane_get_property(pstate,
  1000. PLANE_PROP_VALUE_ADJUST);
  1001. if (psde->pipe_hw->ops.setup_pa_val)
  1002. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1003. contrast = (uint32_t) sde_plane_get_property(pstate,
  1004. PLANE_PROP_CONTRAST_ADJUST);
  1005. if (psde->pipe_hw->ops.setup_pa_cont)
  1006. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1007. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1008. /* Skin memory color setup */
  1009. memcol = msm_property_get_blob(&psde->property_info,
  1010. &pstate->property_state,
  1011. &memcol_sz,
  1012. PLANE_PROP_SKIN_COLOR);
  1013. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1014. MEMCOLOR_SKIN, memcol);
  1015. /* Sky memory color setup */
  1016. memcol = msm_property_get_blob(&psde->property_info,
  1017. &pstate->property_state,
  1018. &memcol_sz,
  1019. PLANE_PROP_SKY_COLOR);
  1020. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1021. MEMCOLOR_SKY, memcol);
  1022. /* Foliage memory color setup */
  1023. memcol = msm_property_get_blob(&psde->property_info,
  1024. &pstate->property_state,
  1025. &memcol_sz,
  1026. PLANE_PROP_FOLIAGE_COLOR);
  1027. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1028. MEMCOLOR_FOLIAGE, memcol);
  1029. }
  1030. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1031. psde->pipe_hw->ops.setup_vig_gamut) {
  1032. vig_gamut = msm_property_get_blob(&psde->property_info,
  1033. &pstate->property_state,
  1034. &size,
  1035. PLANE_PROP_VIG_GAMUT);
  1036. hw_cfg.last_feature = 0;
  1037. hw_cfg.ctl = ctl;
  1038. hw_cfg.len = sizeof(struct drm_msm_3d_gamut);
  1039. hw_cfg.payload = vig_gamut;
  1040. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1041. }
  1042. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1043. psde->pipe_hw->ops.setup_vig_igc) {
  1044. igc = msm_property_get_blob(&psde->property_info,
  1045. &pstate->property_state,
  1046. &size,
  1047. PLANE_PROP_VIG_IGC);
  1048. hw_cfg.last_feature = 0;
  1049. hw_cfg.ctl = ctl;
  1050. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1051. hw_cfg.payload = igc;
  1052. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1053. }
  1054. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1055. psde->pipe_hw->ops.setup_dma_igc) {
  1056. igc = msm_property_get_blob(&psde->property_info,
  1057. &pstate->property_state,
  1058. &size,
  1059. PLANE_PROP_DMA_IGC);
  1060. hw_cfg.last_feature = 0;
  1061. hw_cfg.ctl = ctl;
  1062. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1063. hw_cfg.payload = igc;
  1064. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1065. pstate->multirect_index);
  1066. }
  1067. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1068. psde->pipe_hw->ops.setup_dma_gc) {
  1069. gc = msm_property_get_blob(&psde->property_info,
  1070. &pstate->property_state,
  1071. &size,
  1072. PLANE_PROP_DMA_GC);
  1073. hw_cfg.last_feature = 0;
  1074. hw_cfg.ctl = ctl;
  1075. hw_cfg.len = sizeof(struct drm_msm_pgc_lut);
  1076. hw_cfg.payload = gc;
  1077. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1078. pstate->multirect_index);
  1079. }
  1080. }
  1081. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1082. struct sde_plane_state *pstate,
  1083. const struct sde_format *fmt, bool color_fill)
  1084. {
  1085. struct sde_hw_pixel_ext *pe;
  1086. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1087. const struct drm_format_info *info = NULL;
  1088. if (!psde || !fmt || !pstate) {
  1089. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1090. !psde, !fmt, !pstate);
  1091. return;
  1092. }
  1093. info = drm_format_info(fmt->base.pixel_format);
  1094. pe = &pstate->pixel_ext;
  1095. psde->pipe_cfg.horz_decimation =
  1096. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1097. psde->pipe_cfg.vert_decimation =
  1098. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1099. /* don't chroma subsample if decimating */
  1100. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1101. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1102. /* update scaler */
  1103. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1104. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1105. int rc = -EINVAL;
  1106. if (!color_fill && !psde->debugfs_default_scale)
  1107. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1108. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1109. _sde_plane_setup_scaler3_lut(psde, pstate);
  1110. if (rc || pstate->scaler_check_state !=
  1111. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1112. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1113. pstate->scaler_check_state,
  1114. psde->debugfs_default_scale, rc,
  1115. psde->pipe_cfg.src_rect.w,
  1116. psde->pipe_cfg.src_rect.h,
  1117. psde->pipe_cfg.dst_rect.w,
  1118. psde->pipe_cfg.dst_rect.h,
  1119. pstate->multirect_mode);
  1120. /* calculate default config for QSEED3 */
  1121. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1122. chroma_subsmpl_h, chroma_subsmpl_v);
  1123. }
  1124. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1125. color_fill || psde->debugfs_default_scale) {
  1126. uint32_t deci_dim, i;
  1127. /* calculate default configuration for QSEED2 */
  1128. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1129. SDE_DEBUG_PLANE(psde, "default config\n");
  1130. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1131. psde->pipe_cfg.horz_decimation);
  1132. _sde_plane_setup_scaler2(psde,
  1133. deci_dim,
  1134. psde->pipe_cfg.dst_rect.w,
  1135. pe->phase_step_x,
  1136. pe->horz_filter, fmt, chroma_subsmpl_h);
  1137. if (SDE_FORMAT_IS_YUV(fmt))
  1138. deci_dim &= ~0x1;
  1139. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1140. psde->pipe_cfg.dst_rect.w, deci_dim,
  1141. pe->phase_step_x,
  1142. pe->roi_w,
  1143. pe->num_ext_pxls_left,
  1144. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1145. chroma_subsmpl_h, 0);
  1146. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1147. psde->pipe_cfg.vert_decimation);
  1148. _sde_plane_setup_scaler2(psde,
  1149. deci_dim,
  1150. psde->pipe_cfg.dst_rect.h,
  1151. pe->phase_step_y,
  1152. pe->vert_filter, fmt, chroma_subsmpl_v);
  1153. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1154. psde->pipe_cfg.dst_rect.h, deci_dim,
  1155. pe->phase_step_y,
  1156. pe->roi_h,
  1157. pe->num_ext_pxls_top,
  1158. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1159. chroma_subsmpl_v, 1);
  1160. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1161. if (pe->num_ext_pxls_left[i] >= 0)
  1162. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1163. else
  1164. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1165. if (pe->num_ext_pxls_right[i] >= 0)
  1166. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1167. else
  1168. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1169. if (pe->num_ext_pxls_top[i] >= 0)
  1170. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1171. else
  1172. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1173. if (pe->num_ext_pxls_btm[i] >= 0)
  1174. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1175. else
  1176. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1177. }
  1178. }
  1179. if (psde->pipe_hw->ops.setup_pre_downscale)
  1180. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1181. &pstate->pre_down);
  1182. }
  1183. /**
  1184. * _sde_plane_color_fill - enables color fill on plane
  1185. * @psde: Pointer to SDE plane object
  1186. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1187. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1188. * Returns: 0 on success
  1189. */
  1190. static int _sde_plane_color_fill(struct sde_plane *psde,
  1191. uint32_t color, uint32_t alpha)
  1192. {
  1193. const struct sde_format *fmt;
  1194. const struct drm_plane *plane;
  1195. struct sde_plane_state *pstate;
  1196. bool blend_enable = true;
  1197. if (!psde || !psde->base.state) {
  1198. SDE_ERROR("invalid plane\n");
  1199. return -EINVAL;
  1200. }
  1201. if (!psde->pipe_hw) {
  1202. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1203. return -EINVAL;
  1204. }
  1205. plane = &psde->base;
  1206. pstate = to_sde_plane_state(plane->state);
  1207. SDE_DEBUG_PLANE(psde, "\n");
  1208. /*
  1209. * select fill format to match user property expectation,
  1210. * h/w only supports RGB variants
  1211. */
  1212. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1213. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1214. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1215. /* update sspp */
  1216. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1217. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1218. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1219. pstate->multirect_index);
  1220. /* override scaler/decimation if solid fill */
  1221. psde->pipe_cfg.src_rect.x = 0;
  1222. psde->pipe_cfg.src_rect.y = 0;
  1223. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1224. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1225. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1226. if (psde->pipe_hw->ops.setup_format)
  1227. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1228. fmt, blend_enable,
  1229. SDE_SSPP_SOLID_FILL,
  1230. pstate->multirect_index);
  1231. if (psde->pipe_hw->ops.setup_rects)
  1232. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1233. &psde->pipe_cfg,
  1234. pstate->multirect_index);
  1235. if (psde->pipe_hw->ops.setup_pe)
  1236. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1237. &pstate->pixel_ext);
  1238. if (psde->pipe_hw->ops.setup_scaler &&
  1239. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1240. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1241. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1242. &psde->pipe_cfg, &pstate->pixel_ext,
  1243. &pstate->scaler3_cfg);
  1244. }
  1245. }
  1246. return 0;
  1247. }
  1248. /**
  1249. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1250. * @plane: Pointer to drm plane
  1251. * @state: Pointer to drm plane state to be validated
  1252. * return: 0 if success; error code otherwise
  1253. */
  1254. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1255. struct drm_plane_state *state)
  1256. {
  1257. struct sde_plane *psde;
  1258. struct sde_plane_state *pstate, *old_pstate;
  1259. int ret = 0;
  1260. u32 rotation;
  1261. if (!plane || !state) {
  1262. SDE_ERROR("invalid plane/state\n");
  1263. return -EINVAL;
  1264. }
  1265. psde = to_sde_plane(plane);
  1266. pstate = to_sde_plane_state(state);
  1267. old_pstate = to_sde_plane_state(plane->state);
  1268. /* check inline rotation and simplify the transform */
  1269. rotation = drm_rotation_simplify(
  1270. state->rotation,
  1271. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1272. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1273. if ((rotation & DRM_MODE_ROTATE_180) ||
  1274. (rotation & DRM_MODE_ROTATE_270)) {
  1275. SDE_ERROR_PLANE(psde,
  1276. "invalid rotation transform must be simplified 0x%x\n",
  1277. rotation);
  1278. ret = -EINVAL;
  1279. goto exit;
  1280. }
  1281. if (rotation & DRM_MODE_ROTATE_90) {
  1282. struct msm_drm_private *priv = plane->dev->dev_private;
  1283. struct sde_kms *sde_kms;
  1284. const struct msm_format *msm_fmt;
  1285. const struct sde_format *fmt;
  1286. struct sde_rect src;
  1287. bool q16_data = true;
  1288. POPULATE_RECT(&src, state->src_x, state->src_y,
  1289. state->src_w, state->src_h, q16_data);
  1290. /*
  1291. * DRM framework expects rotation flag in counter-clockwise
  1292. * direction and the HW expects in clockwise direction.
  1293. * Flip the flags to match with HW.
  1294. */
  1295. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1296. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1297. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1298. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1299. !psde->pipe_sblk->in_rot_maxheight ||
  1300. !psde->pipe_sblk->in_rot_format_list ||
  1301. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1302. SDE_ERROR_PLANE(psde,
  1303. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1304. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1305. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1306. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1307. !psde->pipe_sblk->in_rot_format_list,
  1308. !psde->pipe_sblk->in_rot_maxheight,
  1309. psde->features);
  1310. ret = -EINVAL;
  1311. goto exit;
  1312. }
  1313. /* check for valid height */
  1314. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1315. SDE_ERROR_PLANE(psde,
  1316. "invalid height for inline rot:%d max:%d\n",
  1317. src.h, psde->pipe_sblk->in_rot_maxheight);
  1318. ret = -EINVAL;
  1319. goto exit;
  1320. }
  1321. if (!sde_plane_enabled(state))
  1322. goto exit;
  1323. /* check for valid formats supported by inline rot */
  1324. sde_kms = to_sde_kms(priv->kms);
  1325. msm_fmt = msm_framebuffer_format(state->fb);
  1326. fmt = to_sde_format(msm_fmt);
  1327. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1328. psde->pipe_sblk->in_rot_format_list);
  1329. }
  1330. exit:
  1331. pstate->rotation = rotation;
  1332. return ret;
  1333. }
  1334. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1335. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1336. {
  1337. struct sde_plane *psde;
  1338. struct msm_drm_private *priv;
  1339. struct sde_vbif_set_xin_halt_params halt_params;
  1340. if (!plane || !plane->dev) {
  1341. SDE_ERROR("invalid arguments\n");
  1342. return false;
  1343. }
  1344. psde = to_sde_plane(plane);
  1345. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1346. SDE_ERROR("invalid pipe reference\n");
  1347. return false;
  1348. }
  1349. priv = plane->dev->dev_private;
  1350. if (!priv || !priv->kms) {
  1351. SDE_ERROR("invalid KMS reference\n");
  1352. return false;
  1353. }
  1354. memset(&halt_params, 0, sizeof(halt_params));
  1355. halt_params.vbif_idx = VBIF_RT;
  1356. halt_params.xin_id = xin_id;
  1357. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1358. halt_params.forced_on = halt_forced_clk;
  1359. halt_params.enable = enable;
  1360. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1361. }
  1362. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1363. {
  1364. struct sde_plane *psde;
  1365. if (!plane) {
  1366. SDE_ERROR("invalid plane\n");
  1367. return;
  1368. }
  1369. psde = to_sde_plane(plane);
  1370. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1371. SDE_ERROR("invalid pipe reference\n");
  1372. return;
  1373. }
  1374. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1375. psde->xin_halt_forced_clk =
  1376. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1377. psde->xin_halt_forced_clk, enable);
  1378. }
  1379. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1380. struct drm_crtc *crtc)
  1381. {
  1382. struct sde_plane *psde;
  1383. if (!plane || !crtc) {
  1384. SDE_ERROR("invalid plane/crtc\n");
  1385. return;
  1386. }
  1387. psde = to_sde_plane(plane);
  1388. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1389. return;
  1390. /* do all VBIF programming for the sec-ui allowed SSPP */
  1391. _sde_plane_set_qos_remap(plane);
  1392. _sde_plane_set_ot_limit(plane, crtc);
  1393. }
  1394. /**
  1395. * sde_plane_rot_install_properties - install plane rotator properties
  1396. * @plane: Pointer to drm plane
  1397. * @catalog: Pointer to mdss configuration
  1398. * return: none
  1399. */
  1400. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1401. struct sde_mdss_cfg *catalog)
  1402. {
  1403. struct sde_plane *psde = to_sde_plane(plane);
  1404. unsigned long supported_rotations = DRM_MODE_ROTATE_0 |
  1405. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1406. int ret = 0;
  1407. if (!plane || !psde) {
  1408. SDE_ERROR("invalid plane\n");
  1409. return;
  1410. } else if (!catalog) {
  1411. SDE_ERROR("invalid catalog\n");
  1412. return;
  1413. }
  1414. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1415. supported_rotations |= DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1416. DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
  1417. ret = drm_plane_create_rotation_property(plane,
  1418. DRM_MODE_ROTATE_0, supported_rotations);
  1419. if (ret) {
  1420. DRM_ERROR("create rotation property failed: %d\n", ret);
  1421. return;
  1422. }
  1423. }
  1424. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1425. {
  1426. struct sde_plane_state *pstate;
  1427. if (!drm_state)
  1428. return;
  1429. pstate = to_sde_plane_state(drm_state);
  1430. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1431. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1432. }
  1433. /**
  1434. * multi_rect validate API allows to validate only R0 and R1 RECT
  1435. * passing for each plane. Client of this API must not pass multiple
  1436. * plane which are not sharing same XIN client. Such calls will fail
  1437. * even though kernel client is passing valid multirect configuration.
  1438. */
  1439. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1440. {
  1441. struct sde_plane_state *pstate[R_MAX];
  1442. const struct drm_plane_state *drm_state[R_MAX];
  1443. struct sde_rect src[R_MAX], dst[R_MAX];
  1444. struct sde_plane *sde_plane[R_MAX];
  1445. const struct sde_format *fmt[R_MAX];
  1446. int xin_id[R_MAX];
  1447. bool q16_data = true;
  1448. int i, j, buffer_lines, width_threshold[R_MAX];
  1449. unsigned int max_tile_height = 1;
  1450. bool parallel_fetch_qualified = true;
  1451. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1452. const struct msm_format *msm_fmt;
  1453. bool const_alpha_enable = true;
  1454. for (i = 0; i < R_MAX; i++) {
  1455. drm_state[i] = i ? plane->r1 : plane->r0;
  1456. if (!drm_state[i]) {
  1457. SDE_ERROR("drm plane state is NULL\n");
  1458. return -EINVAL;
  1459. }
  1460. pstate[i] = to_sde_plane_state(drm_state[i]);
  1461. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1462. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1463. for (j = 0; j < i; j++) {
  1464. if (xin_id[i] != xin_id[j]) {
  1465. SDE_ERROR_PLANE(sde_plane[i],
  1466. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1467. j, xin_id[j], i, xin_id[i]);
  1468. return -EINVAL;
  1469. }
  1470. }
  1471. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1472. if (!msm_fmt) {
  1473. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1474. return -EINVAL;
  1475. }
  1476. fmt[i] = to_sde_format(msm_fmt);
  1477. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1478. (fmt[i]->tile_height > max_tile_height))
  1479. max_tile_height = fmt[i]->tile_height;
  1480. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1481. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1482. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1483. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1484. drm_state[i]->crtc_h, !q16_data);
  1485. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1486. SDE_ERROR_PLANE(sde_plane[i],
  1487. "scaling is not supported in multirect mode\n");
  1488. return -EINVAL;
  1489. }
  1490. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1491. SDE_ERROR_PLANE(sde_plane[i],
  1492. "inline rotation is not supported in mulirect mode\n");
  1493. return -EINVAL;
  1494. }
  1495. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1496. SDE_ERROR_PLANE(sde_plane[i],
  1497. "Unsupported format for multirect mode\n");
  1498. return -EINVAL;
  1499. }
  1500. /**
  1501. * SSPP PD_MEM is split half - one for each RECT.
  1502. * Tiled formats need 5 lines of buffering while fetching
  1503. * whereas linear formats need only 2 lines.
  1504. * So we cannot support more than half of the supported SSPP
  1505. * width for tiled formats.
  1506. */
  1507. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1508. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1509. width_threshold[i] /= 2;
  1510. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1511. parallel_fetch_qualified = false;
  1512. if (sde_plane[i]->is_virtual)
  1513. mode = sde_plane_get_property(pstate[i],
  1514. PLANE_PROP_MULTIRECT_MODE);
  1515. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1516. const_alpha_enable = false;
  1517. }
  1518. buffer_lines = 2 * max_tile_height;
  1519. /**
  1520. * fallback to driver mode selection logic if client is using
  1521. * multirect plane without setting property.
  1522. *
  1523. * validate multirect mode configuration based on rectangle
  1524. */
  1525. switch (mode) {
  1526. case SDE_SSPP_MULTIRECT_NONE:
  1527. if (parallel_fetch_qualified)
  1528. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1529. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1530. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1531. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1532. else
  1533. SDE_ERROR(
  1534. "planes(%d - %d) multirect mode selection fail\n",
  1535. drm_state[R0]->plane->base.id,
  1536. drm_state[R1]->plane->base.id);
  1537. break;
  1538. case SDE_SSPP_MULTIRECT_PARALLEL:
  1539. if (!parallel_fetch_qualified) {
  1540. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1541. drm_state[R0]->plane->base.id,
  1542. width_threshold[R0], src[R0].w);
  1543. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1544. drm_state[R1]->plane->base.id,
  1545. width_threshold[R1], src[R1].w);
  1546. SDE_ERROR("parallel fetch not qualified\n");
  1547. mode = SDE_SSPP_MULTIRECT_NONE;
  1548. }
  1549. break;
  1550. case SDE_SSPP_MULTIRECT_TIME_MX:
  1551. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1552. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1553. SDE_ERROR(
  1554. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1555. buffer_lines, drm_state[R0]->plane->base.id,
  1556. dst[R0].y, dst[R0].h);
  1557. SDE_ERROR(
  1558. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1559. buffer_lines, drm_state[R1]->plane->base.id,
  1560. dst[R1].y, dst[R1].h);
  1561. SDE_ERROR("time multiplexed fetch not qualified\n");
  1562. mode = SDE_SSPP_MULTIRECT_NONE;
  1563. }
  1564. break;
  1565. default:
  1566. SDE_ERROR("bad mode:%d selection\n", mode);
  1567. mode = SDE_SSPP_MULTIRECT_NONE;
  1568. break;
  1569. }
  1570. for (i = 0; i < R_MAX; i++) {
  1571. pstate[i]->multirect_mode = mode;
  1572. pstate[i]->const_alpha_en = const_alpha_enable;
  1573. }
  1574. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1575. return -EINVAL;
  1576. if (sde_plane[R0]->is_virtual) {
  1577. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1578. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1579. } else {
  1580. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1581. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1582. }
  1583. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1584. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1585. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1586. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1587. return 0;
  1588. }
  1589. /**
  1590. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1591. * @plane: Pointer to drm plane structure
  1592. * @ctl: Pointer to hardware control driver
  1593. * @set: set if true else clear
  1594. */
  1595. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1596. bool set)
  1597. {
  1598. if (!plane || !ctl) {
  1599. SDE_ERROR("invalid parameters\n");
  1600. return;
  1601. }
  1602. if (!ctl->ops.update_bitmask_sspp) {
  1603. SDE_ERROR("invalid ops\n");
  1604. return;
  1605. }
  1606. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1607. }
  1608. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1609. struct drm_plane_state *new_state)
  1610. {
  1611. struct drm_framebuffer *fb = new_state->fb;
  1612. struct sde_plane *psde = to_sde_plane(plane);
  1613. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1614. struct sde_hw_fmt_layout layout;
  1615. struct msm_gem_address_space *aspace;
  1616. int ret;
  1617. if (!fb)
  1618. return 0;
  1619. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1620. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1621. if (ret) {
  1622. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1623. return ret;
  1624. }
  1625. /* cache aspace */
  1626. pstate->aspace = aspace;
  1627. /*
  1628. * when transitioning from secure to non-secure,
  1629. * plane->prepare_fb happens before the commit. In such case,
  1630. * defer the prepare_fb and handled it late, during the commit
  1631. * after attaching the domains as part of the transition
  1632. */
  1633. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1634. true : false;
  1635. if (pstate->defer_prepare_fb) {
  1636. SDE_EVT32(DRMID(plane), psde->pipe);
  1637. SDE_DEBUG_PLANE(psde,
  1638. "domain not attached, prepare_fb handled later\n");
  1639. return 0;
  1640. }
  1641. if (pstate->aspace && fb) {
  1642. ret = msm_framebuffer_prepare(fb,
  1643. pstate->aspace);
  1644. if (ret) {
  1645. SDE_ERROR("failed to prepare framebuffer\n");
  1646. return ret;
  1647. }
  1648. }
  1649. /* validate framebuffer layout before commit */
  1650. ret = sde_format_populate_layout(pstate->aspace,
  1651. fb, &layout);
  1652. if (ret) {
  1653. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1654. return ret;
  1655. }
  1656. return 0;
  1657. }
  1658. /**
  1659. * _sde_plane_fetch_halt - halts vbif transactions for a plane
  1660. * @plane: Pointer to plane
  1661. * Returns: 0 on success
  1662. */
  1663. static int _sde_plane_fetch_halt(struct drm_plane *plane)
  1664. {
  1665. struct sde_plane *psde;
  1666. int xin_id;
  1667. enum sde_clk_ctrl_type clk_ctrl;
  1668. struct msm_drm_private *priv;
  1669. struct sde_kms *sde_kms;
  1670. psde = to_sde_plane(plane);
  1671. if (!plane || !plane->dev || !psde->pipe_hw) {
  1672. SDE_ERROR("invalid arguments\n");
  1673. return -EINVAL;
  1674. }
  1675. priv = plane->dev->dev_private;
  1676. if (!priv || !priv->kms) {
  1677. SDE_ERROR("invalid KMS reference\n");
  1678. return -EINVAL;
  1679. }
  1680. sde_kms = to_sde_kms(priv->kms);
  1681. clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1682. xin_id = psde->pipe_hw->cap->xin_id;
  1683. SDE_DEBUG_PLANE(psde, "pipe:%d xin_id:%d clk_ctrl:%d\n",
  1684. psde->pipe - SSPP_VIG0, xin_id, clk_ctrl);
  1685. SDE_EVT32_VERBOSE(psde, psde->pipe - SSPP_VIG0, xin_id, clk_ctrl);
  1686. return sde_vbif_halt_plane_xin(sde_kms, xin_id, clk_ctrl);
  1687. }
  1688. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1689. struct drm_plane_state *old_state)
  1690. {
  1691. struct sde_plane *psde = to_sde_plane(plane);
  1692. struct sde_plane_state *old_pstate;
  1693. int ret;
  1694. if (!old_state || !old_state->fb || !plane || !plane->state)
  1695. return;
  1696. old_pstate = to_sde_plane_state(old_state);
  1697. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1698. /*
  1699. * plane->state gets populated for next frame after swap_state. If
  1700. * plane->state->crtc pointer is not populated then it is not used in
  1701. * the next frame, hence making it an unused plane.
  1702. */
  1703. if ((plane->state->crtc == NULL) && !psde->is_virtual) {
  1704. SDE_DEBUG_PLANE(psde, "unused pipe:%u\n",
  1705. psde->pipe - SSPP_VIG0);
  1706. /* halt this plane now */
  1707. ret = pm_runtime_get_sync(plane->dev->dev);
  1708. if (ret < 0) {
  1709. SDE_ERROR("power resource enable failed with %d", ret);
  1710. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  1711. return;
  1712. }
  1713. ret = _sde_plane_fetch_halt(plane);
  1714. if (ret) {
  1715. SDE_ERROR_PLANE(psde,
  1716. "unused pipe %u halt failed\n",
  1717. psde->pipe - SSPP_VIG0);
  1718. SDE_EVT32(DRMID(plane), psde->pipe - SSPP_VIG0,
  1719. ret, SDE_EVTLOG_ERROR);
  1720. }
  1721. pm_runtime_put_sync(plane->dev->dev);
  1722. }
  1723. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1724. }
  1725. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1726. struct drm_plane_state *state,
  1727. struct drm_plane_state *old_state)
  1728. {
  1729. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1730. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1731. struct drm_framebuffer *fb, *old_fb;
  1732. /* no need to check it again */
  1733. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1734. return;
  1735. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1736. || psde->is_error) {
  1737. SDE_DEBUG_PLANE(psde,
  1738. "enabling/disabling full modeset required\n");
  1739. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1740. } else if (to_sde_plane_state(old_state)->pending) {
  1741. SDE_DEBUG_PLANE(psde, "still pending\n");
  1742. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1743. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1744. pstate->multirect_mode != old_pstate->multirect_mode) {
  1745. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1746. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1747. } else if (state->src_w != old_state->src_w ||
  1748. state->src_h != old_state->src_h ||
  1749. state->src_x != old_state->src_x ||
  1750. state->src_y != old_state->src_y) {
  1751. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1752. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1753. } else if (state->crtc_w != old_state->crtc_w ||
  1754. state->crtc_h != old_state->crtc_h ||
  1755. state->crtc_x != old_state->crtc_x ||
  1756. state->crtc_y != old_state->crtc_y) {
  1757. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1758. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1759. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1760. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1761. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1762. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1763. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1764. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1765. } else if (pstate->rotation != old_pstate->rotation) {
  1766. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1767. pstate->rotation, old_pstate->rotation);
  1768. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1769. }
  1770. fb = state->fb;
  1771. old_fb = old_state->fb;
  1772. if (!fb || !old_fb) {
  1773. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1774. } else if ((fb->format->format != old_fb->format->format) ||
  1775. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1776. SDE_DEBUG_PLANE(psde, "format change\n");
  1777. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1778. } else {
  1779. uint64_t new_mod = fb->modifier;
  1780. uint64_t old_mod = old_fb->modifier;
  1781. uint32_t *new_pitches = fb->pitches;
  1782. uint32_t *old_pitches = old_fb->pitches;
  1783. uint32_t *new_offset = fb->offsets;
  1784. uint32_t *old_offset = old_fb->offsets;
  1785. int i;
  1786. if (new_mod != old_mod) {
  1787. SDE_DEBUG_PLANE(psde,
  1788. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1789. new_mod, old_mod);
  1790. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1791. SDE_PLANE_DIRTY_RECTS;
  1792. }
  1793. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1794. if (new_pitches[i] != old_pitches[i]) {
  1795. SDE_DEBUG_PLANE(psde,
  1796. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1797. i, old_pitches[i], new_pitches[i]);
  1798. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1799. break;
  1800. }
  1801. }
  1802. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1803. if (new_offset[i] != old_offset[i]) {
  1804. SDE_DEBUG_PLANE(psde,
  1805. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1806. i, old_offset[i], new_offset[i]);
  1807. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1808. SDE_PLANE_DIRTY_RECTS;
  1809. break;
  1810. }
  1811. }
  1812. }
  1813. }
  1814. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1815. unsigned long base_addr, u32 size)
  1816. {
  1817. int ret = -EINVAL;
  1818. u32 addr;
  1819. struct sde_plane *psde = to_sde_plane(plane);
  1820. if (!psde || !base_addr || !size) {
  1821. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1822. return ret;
  1823. }
  1824. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1825. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1826. is_sde_plane_virtual(plane));
  1827. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1828. ret = 0;
  1829. }
  1830. return ret;
  1831. }
  1832. static inline bool _sde_plane_is_pre_downscale_enabled(
  1833. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1834. {
  1835. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1836. }
  1837. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1838. struct sde_plane_state *pstate,
  1839. const struct sde_format *fmt,
  1840. uint32_t img_w, uint32_t img_h,
  1841. uint32_t src_w, uint32_t src_h,
  1842. uint32_t deci_w, uint32_t deci_h)
  1843. {
  1844. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1845. bool pre_down_en;
  1846. int i;
  1847. if (!psde || !pstate || !fmt) {
  1848. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1849. return -EINVAL;
  1850. }
  1851. if (psde->debugfs_default_scale ||
  1852. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1853. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1854. return 0;
  1855. pd_cfg = &pstate->pre_down;
  1856. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1857. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1858. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1859. uint32_t hor_req_pixels, hor_fetch_pixels;
  1860. uint32_t vert_req_pixels, vert_fetch_pixels;
  1861. uint32_t src_w_tmp, src_h_tmp;
  1862. uint32_t scaler_w, scaler_h;
  1863. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1864. bool rot;
  1865. /* re-use color plane 1's config for plane 2 */
  1866. if (i == 2)
  1867. continue;
  1868. if (pre_down_en) {
  1869. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1870. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1871. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1872. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1873. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1874. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1875. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1876. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1877. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1878. i, pre_down_ratio_x, pre_down_ratio_y);
  1879. }
  1880. src_w_tmp = src_w;
  1881. src_h_tmp = src_h;
  1882. /*
  1883. * For chroma plane, width is half for the following sub sampled
  1884. * formats. Except in case of decimation, where hardware avoids
  1885. * 1 line of decimation instead of downsampling.
  1886. */
  1887. if (i == 1) {
  1888. if (!deci_w &&
  1889. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1890. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1891. src_w_tmp >>= 1;
  1892. if (!deci_h &&
  1893. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1894. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1895. src_h_tmp >>= 1;
  1896. }
  1897. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1898. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1899. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1900. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1901. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1902. deci_w);
  1903. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1904. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1905. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1906. deci_h);
  1907. if ((hor_req_pixels != hor_fetch_pixels) ||
  1908. (hor_fetch_pixels > img_w) ||
  1909. (vert_req_pixels != vert_fetch_pixels) ||
  1910. (vert_fetch_pixels > img_h)) {
  1911. SDE_ERROR_PLANE(psde,
  1912. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1913. hor_req_pixels, vert_req_pixels,
  1914. hor_fetch_pixels, vert_fetch_pixels,
  1915. img_w, img_h);
  1916. return -EINVAL;
  1917. }
  1918. /*
  1919. * swap the scaler src width & height for inline-rotation 90
  1920. * comparison with Pixel-Extension, as PE is based on
  1921. * pre-rotation and QSEED is based on post-rotation
  1922. */
  1923. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1924. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1925. : pstate->scaler3_cfg.src_width[i];
  1926. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1927. : pstate->scaler3_cfg.src_height[i];
  1928. /*
  1929. * Alpha plane can only be scaled using bilinear or pixel
  1930. * repeat/drop, src_width and src_height are only specified
  1931. * for Y and UV plane
  1932. */
  1933. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1934. vert_req_pixels / pre_down_ratio_y !=
  1935. scaler_h)) {
  1936. SDE_ERROR_PLANE(psde,
  1937. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1938. i, pstate->pixel_ext.roi_w[i],
  1939. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1940. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1941. return -EINVAL;
  1942. }
  1943. /*
  1944. * SSPP fetch , unpack output and QSEED3 input lines need
  1945. * to match for Y plane
  1946. */
  1947. if (i == 0 &&
  1948. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1949. BIT(SDE_DRM_DEINTERLACE)) &&
  1950. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1951. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1952. SDE_ERROR_PLANE(psde,
  1953. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1954. i, pstate->pixel_ext.roi_w[i],
  1955. pstate->pixel_ext.roi_h[i],
  1956. pstate->scaler3_cfg.src_width[i],
  1957. pstate->scaler3_cfg.src_height[i],
  1958. src_w, src_h);
  1959. return -EINVAL;
  1960. }
  1961. }
  1962. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1963. return 0;
  1964. }
  1965. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1966. {
  1967. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1968. }
  1969. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1970. struct sde_plane_state *pstate, struct sde_rect *dst,
  1971. u32 src_w, u32 src_h)
  1972. {
  1973. int ret = 0;
  1974. u32 min_ratio_numer, min_ratio_denom;
  1975. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1976. bool pd_x;
  1977. bool pd_y;
  1978. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1979. return ret;
  1980. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1981. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1982. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1983. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1984. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  1985. SDE_ERROR_PLANE(psde,
  1986. "hw does not support pre-downscale X: 0x%x\n",
  1987. psde->features);
  1988. ret = -EINVAL;
  1989. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  1990. SDE_ERROR_PLANE(psde,
  1991. "hw does not support pre-downscale Y: 0x%x\n",
  1992. psde->features);
  1993. ret = -EINVAL;
  1994. } else if (!min_ratio_numer || !min_ratio_denom) {
  1995. SDE_ERROR_PLANE(psde,
  1996. "min downscale ratio not set! %u / %u\n",
  1997. min_ratio_numer, min_ratio_denom);
  1998. ret = -EINVAL;
  1999. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2000. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2001. min_ratio_denom))) {
  2002. SDE_ERROR_PLANE(psde,
  2003. "failed min downscale-x check %u->%u, %u/%u\n",
  2004. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2005. ret = -EINVAL;
  2006. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2007. min_ratio_denom))) {
  2008. SDE_ERROR_PLANE(psde,
  2009. "failed min downscale-y check %u->%u, %u/%u\n",
  2010. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2011. ret = -EINVAL;
  2012. }
  2013. return ret;
  2014. }
  2015. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2016. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2017. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2018. u32 *max_numer_h, u32 *max_denom_h)
  2019. {
  2020. bool rotated, has_predown;
  2021. const struct sde_sspp_sub_blks *sblk;
  2022. struct sde_hw_inline_pre_downscale_cfg *pd;
  2023. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2024. sblk = psde->pipe_sblk;
  2025. *max_numer_w = sblk->maxdwnscale;
  2026. *max_denom_w = 1;
  2027. *max_numer_h = sblk->maxdwnscale;
  2028. *max_denom_h = 1;
  2029. has_predown = _sde_plane_has_pre_downscale(psde);
  2030. if (has_predown)
  2031. pd = &pstate->pre_down;
  2032. /**
  2033. * Inline rotation has different max vertical downscaling limits since
  2034. * the source-width becomes the scaler's pre-downscaled source-height.
  2035. **/
  2036. if (rotated) {
  2037. if (rt_client && has_predown) {
  2038. pd->pre_downscale_x_0 = (src_h >
  2039. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2040. *max_numer_h = pd->pre_downscale_x_0 ?
  2041. sblk->in_rot_maxdwnscale_rt_num :
  2042. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2043. *max_denom_h = pd->pre_downscale_x_0 ?
  2044. sblk->in_rot_maxdwnscale_rt_denom :
  2045. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2046. } else if (rt_client) {
  2047. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2048. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2049. } else {
  2050. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2051. }
  2052. }
  2053. }
  2054. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2055. struct sde_plane *psde, const struct sde_format *fmt,
  2056. struct sde_plane_state *pstate, struct sde_rect *src,
  2057. struct sde_rect *dst, u32 width, u32 height)
  2058. {
  2059. int ret = 0;
  2060. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2061. uint32_t scaler_src_w, scaler_src_h;
  2062. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2063. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2064. uint32_t max_upscale, max_linewidth;
  2065. bool inline_rotation, rt_client;
  2066. struct drm_crtc *crtc;
  2067. struct drm_crtc_state *new_cstate;
  2068. const struct sde_sspp_sub_blks *sblk;
  2069. if (!state || !state->state || !state->crtc) {
  2070. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2071. return -EINVAL;
  2072. }
  2073. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2074. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2075. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2076. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2077. /* with inline rotator, the source of the scaler is post-rotated */
  2078. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2079. if (inline_rotation) {
  2080. scaler_src_w = src_deci_h;
  2081. scaler_src_h = src_deci_w;
  2082. } else {
  2083. scaler_src_w = src_deci_w;
  2084. scaler_src_h = src_deci_h;
  2085. }
  2086. sblk = psde->pipe_sblk;
  2087. max_upscale = sblk->maxupscale;
  2088. if (inline_rotation)
  2089. max_linewidth = sblk->in_rot_maxheight;
  2090. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2091. max_linewidth = sblk->scaling_linewidth;
  2092. else
  2093. max_linewidth = sblk->maxlinewidth;
  2094. crtc = state->crtc;
  2095. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2096. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2097. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2098. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2099. &max_downscale_num_h, &max_downscale_denom_h);
  2100. /* decimation validation */
  2101. if ((deci_w || deci_h)
  2102. && ((deci_w > sblk->maxhdeciexp)
  2103. || (deci_h > sblk->maxvdeciexp))) {
  2104. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2105. ret = -EINVAL;
  2106. } else if ((deci_w || deci_h)
  2107. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2108. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2109. ret = -EINVAL;
  2110. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2111. ((src->w != dst->w) || (src->h != dst->h))) {
  2112. SDE_ERROR_PLANE(psde,
  2113. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2114. src->w, src->h, dst->w, dst->h);
  2115. ret = -EINVAL;
  2116. /* check scaler source width */
  2117. } else if (scaler_src_w > max_linewidth) {
  2118. SDE_ERROR_PLANE(psde,
  2119. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2120. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2121. ret = -E2BIG;
  2122. /* check max scaler capability */
  2123. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2124. ((scaler_src_h * max_upscale) < dst->h) ||
  2125. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2126. < scaler_src_w) ||
  2127. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2128. < scaler_src_h)) {
  2129. SDE_ERROR_PLANE(psde,
  2130. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2131. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2132. inline_rotation, max_downscale_num_w,
  2133. max_downscale_denom_w, max_downscale_num_h,
  2134. max_downscale_denom_h);
  2135. ret = -E2BIG;
  2136. /* check inline pre-downscale support */
  2137. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2138. pstate, dst, src_deci_w, src_deci_h)) {
  2139. ret = -EINVAL;
  2140. /* QSEED validation */
  2141. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2142. width, height, src->w, src->h,
  2143. deci_w, deci_h)) {
  2144. ret = -EINVAL;
  2145. }
  2146. return ret;
  2147. }
  2148. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2149. struct sde_plane_state *pstate, struct sde_rect *src,
  2150. const struct sde_format *fmt, int ret)
  2151. {
  2152. /* check excl rect configs */
  2153. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2154. struct sde_rect intersect;
  2155. /*
  2156. * Check exclusion rect against src rect.
  2157. * it must intersect with source rect.
  2158. */
  2159. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2160. if (intersect.w != pstate->excl_rect.w ||
  2161. intersect.h != pstate->excl_rect.h ||
  2162. SDE_FORMAT_IS_YUV(fmt)) {
  2163. SDE_ERROR_PLANE(psde,
  2164. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2165. pstate->excl_rect.x, pstate->excl_rect.y,
  2166. pstate->excl_rect.w, pstate->excl_rect.h,
  2167. src->x, src->y, src->w, src->h,
  2168. (char *)&fmt->base.pixel_format);
  2169. ret = -EINVAL;
  2170. }
  2171. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2172. pstate->excl_rect.x, pstate->excl_rect.y,
  2173. pstate->excl_rect.w, pstate->excl_rect.h);
  2174. }
  2175. return ret;
  2176. }
  2177. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2178. struct drm_plane_state *state)
  2179. {
  2180. struct sde_kms *sde_kms;
  2181. struct sde_splash_display *splash_display;
  2182. int i, j;
  2183. sde_kms = _sde_plane_get_kms(&psde->base);
  2184. if (!sde_kms || !state->crtc)
  2185. return 0;
  2186. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2187. splash_display = &sde_kms->splash_data.splash_display[i];
  2188. if (splash_display && splash_display->cont_splash_enabled &&
  2189. splash_display->encoder &&
  2190. state->crtc != splash_display->encoder->crtc) {
  2191. for (j = 0; j < MAX_DATA_PATH_PER_DSIPLAY; j++) {
  2192. if (splash_display->pipes[j].sspp ==
  2193. psde->pipe) {
  2194. SDE_ERROR_PLANE(psde,
  2195. "pipe:%d used in cont-splash on crtc:%d\n",
  2196. psde->pipe,
  2197. splash_display->encoder->crtc->base.id);
  2198. return -EINVAL;
  2199. }
  2200. }
  2201. }
  2202. }
  2203. return 0;
  2204. }
  2205. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2206. struct drm_plane_state *state)
  2207. {
  2208. int ret = 0;
  2209. struct sde_plane *psde;
  2210. struct sde_plane_state *pstate;
  2211. const struct msm_format *msm_fmt;
  2212. const struct sde_format *fmt;
  2213. struct sde_rect src, dst;
  2214. uint32_t min_src_size;
  2215. bool q16_data = true;
  2216. struct drm_framebuffer *fb;
  2217. u32 width;
  2218. u32 height;
  2219. psde = to_sde_plane(plane);
  2220. pstate = to_sde_plane_state(state);
  2221. if (!psde->pipe_sblk) {
  2222. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2223. return -EINVAL;
  2224. }
  2225. /* src values are in Q16 fixed point, convert to integer */
  2226. POPULATE_RECT(&src, state->src_x, state->src_y,
  2227. state->src_w, state->src_h, q16_data);
  2228. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2229. state->crtc_h, !q16_data);
  2230. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2231. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2232. if (!sde_plane_enabled(state))
  2233. goto modeset_update;
  2234. fb = state->fb;
  2235. width = fb ? state->fb->width : 0x0;
  2236. height = fb ? state->fb->height : 0x0;
  2237. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2238. plane->base.id,
  2239. pstate->rotation,
  2240. width, height,
  2241. fb ? (char *) &state->fb->format->format : 0x0,
  2242. fb ? state->fb->modifier : 0x0);
  2243. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2244. state->src_w >> 16, state->src_h >> 16,
  2245. state->src_x >> 16, state->src_y >> 16,
  2246. state->crtc_w, state->crtc_h,
  2247. state->crtc_x, state->crtc_y);
  2248. msm_fmt = msm_framebuffer_format(fb);
  2249. fmt = to_sde_format(msm_fmt);
  2250. min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2251. if (SDE_FORMAT_IS_YUV(fmt) &&
  2252. (!(psde->features & SDE_SSPP_SCALER) ||
  2253. !(psde->features & (BIT(SDE_SSPP_CSC)
  2254. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2255. SDE_ERROR_PLANE(psde,
  2256. "plane doesn't have scaler/csc for yuv\n");
  2257. ret = -EINVAL;
  2258. /* check src bounds */
  2259. } else if (width > MAX_IMG_WIDTH ||
  2260. height > MAX_IMG_HEIGHT ||
  2261. src.w < min_src_size || src.h < min_src_size ||
  2262. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2263. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2264. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2265. src.x, src.y, src.w, src.h);
  2266. ret = -E2BIG;
  2267. /* valid yuv image */
  2268. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2269. (src.w & 0x1) || (src.h & 0x1))) {
  2270. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2271. src.x, src.y, src.w, src.h);
  2272. ret = -EINVAL;
  2273. /* min dst support */
  2274. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2275. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2276. dst.x, dst.y, dst.w, dst.h);
  2277. ret = -EINVAL;
  2278. }
  2279. if (ret)
  2280. return ret;
  2281. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2282. &src, &dst, width, height);
  2283. if (ret)
  2284. return ret;
  2285. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2286. &src, fmt, ret);
  2287. if (ret)
  2288. return ret;
  2289. ret = _sde_plane_validate_shared_crtc(psde, state);
  2290. if (ret)
  2291. return ret;
  2292. pstate->const_alpha_en = fmt->alpha_enable &&
  2293. (SDE_DRM_BLEND_OP_OPAQUE !=
  2294. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2295. (pstate->stage != SDE_STAGE_0);
  2296. modeset_update:
  2297. if (!ret)
  2298. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2299. state, plane->state);
  2300. return ret;
  2301. }
  2302. static int sde_plane_atomic_check(struct drm_plane *plane,
  2303. struct drm_plane_state *state)
  2304. {
  2305. int ret = 0;
  2306. struct sde_plane *psde;
  2307. struct sde_plane_state *pstate;
  2308. if (!plane || !state) {
  2309. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2310. !plane, !state);
  2311. ret = -EINVAL;
  2312. goto exit;
  2313. }
  2314. psde = to_sde_plane(plane);
  2315. pstate = to_sde_plane_state(state);
  2316. SDE_DEBUG_PLANE(psde, "\n");
  2317. ret = sde_plane_rot_atomic_check(plane, state);
  2318. if (ret)
  2319. goto exit;
  2320. ret = sde_plane_sspp_atomic_check(plane, state);
  2321. exit:
  2322. return ret;
  2323. }
  2324. void sde_plane_flush(struct drm_plane *plane)
  2325. {
  2326. struct sde_plane *psde;
  2327. struct sde_plane_state *pstate;
  2328. if (!plane || !plane->state) {
  2329. SDE_ERROR("invalid plane\n");
  2330. return;
  2331. }
  2332. psde = to_sde_plane(plane);
  2333. pstate = to_sde_plane_state(plane->state);
  2334. /*
  2335. * These updates have to be done immediately before the plane flush
  2336. * timing, and may not be moved to the atomic_update/mode_set functions.
  2337. */
  2338. if (psde->is_error)
  2339. /* force white frame with 100% alpha pipe output on error */
  2340. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2341. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2342. /* force 100% alpha */
  2343. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2344. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2345. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2346. /* flag h/w flush complete */
  2347. if (plane->state)
  2348. pstate->pending = false;
  2349. }
  2350. /**
  2351. * sde_plane_set_error: enable/disable error condition
  2352. * @plane: pointer to drm_plane structure
  2353. */
  2354. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2355. {
  2356. struct sde_plane *psde;
  2357. if (!plane)
  2358. return;
  2359. psde = to_sde_plane(plane);
  2360. psde->is_error = error;
  2361. }
  2362. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2363. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2364. {
  2365. if (!psde->pipe_hw->ops.setup_sys_cache ||
  2366. !(psde->perf_features & BIT(SDE_PERF_SSPP_SYS_CACHE)))
  2367. return;
  2368. SDE_DEBUG("features:0x%x rotation:0x%x\n",
  2369. psde->features, pstate->rotation);
  2370. if ((pstate->rotation & DRM_MODE_ROTATE_90) &&
  2371. sde_format_is_tp10_ubwc(fmt)) {
  2372. pstate->sc_cfg.rd_en = true;
  2373. pstate->sc_cfg.rd_scid =
  2374. psde->pipe_sblk->llcc_scid;
  2375. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2376. SSPP_SYS_CACHE_SCID;
  2377. } else {
  2378. pstate->sc_cfg.rd_en = false;
  2379. pstate->sc_cfg.rd_scid = 0x0;
  2380. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2381. SSPP_SYS_CACHE_SCID;
  2382. }
  2383. psde->pipe_hw->ops.setup_sys_cache(
  2384. psde->pipe_hw, &pstate->sc_cfg);
  2385. }
  2386. static void _sde_plane_map_prop_to_dirty_bits(void)
  2387. {
  2388. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2389. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2390. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2391. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2392. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2393. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2394. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2395. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2396. plane_prop_array[PLANE_PROP_ZPOS] =
  2397. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2398. SDE_PLANE_DIRTY_RECTS;
  2399. plane_prop_array[PLANE_PROP_CSC_V1] =
  2400. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2401. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2402. SDE_PLANE_DIRTY_FORMAT;
  2403. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2404. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2405. SDE_PLANE_DIRTY_ALL;
  2406. /* no special action required */
  2407. plane_prop_array[PLANE_PROP_INFO] =
  2408. plane_prop_array[PLANE_PROP_ALPHA] =
  2409. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2410. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2411. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2412. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2413. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2414. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2415. SDE_PLANE_DIRTY_PERF;
  2416. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2417. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2418. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2419. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2420. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2421. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2422. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2423. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2424. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2425. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2426. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2427. SDE_PLANE_DIRTY_ALL;
  2428. }
  2429. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2430. struct sde_rect *src, struct sde_rect *dst)
  2431. {
  2432. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2433. u32 downscale = (src->h * 1000)/dst->h;
  2434. return (downscale > max_downscale) ? false : true;
  2435. }
  2436. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2437. struct sde_plane *psde, struct sde_plane_state *pstate,
  2438. struct sde_rect *src, struct sde_rect *dst)
  2439. {
  2440. struct sde_hw_pipe_uidle_cfg cfg;
  2441. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2442. u32 line_time = sde_get_linetime(&crtc->mode,
  2443. sde_crtc->src_bpp, sde_crtc->target_bpp); /* nS */
  2444. u32 fal1_target_idle_time_ns =
  2445. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2446. u32 fal10_target_idle_time_ns =
  2447. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2448. u32 fal10_threshold =
  2449. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2450. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2451. fal1_target_idle_time_ns) {
  2452. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2453. cfg.fal10_threshold = fal10_threshold;
  2454. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2455. cfg.fal1_threshold = 1 +
  2456. (fal1_target_idle_time_ns*1000/line_time*2)/1000;
  2457. cfg.fal_allowed_threshold = fal10_threshold +
  2458. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2459. } else {
  2460. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2461. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2462. fal1_target_idle_time_ns);
  2463. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2464. }
  2465. SDE_DEBUG_PLANE(psde,
  2466. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",
  2467. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2468. cfg.fal1_threshold, cfg.fal_allowed_threshold);
  2469. SDE_DEBUG_PLANE(psde,
  2470. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2471. line_time, fal1_target_idle_time_ns,
  2472. fal10_target_idle_time_ns,
  2473. psde->catalog->uidle_cfg.max_dwnscale);
  2474. SDE_EVT32_VERBOSE(cfg.enable,
  2475. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2476. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2477. psde->catalog->uidle_cfg.max_dwnscale);
  2478. psde->pipe_hw->ops.setup_uidle(
  2479. psde->pipe_hw, &cfg,
  2480. pstate->multirect_index);
  2481. }
  2482. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2483. struct sde_plane_state *pstate)
  2484. {
  2485. bool enable = false;
  2486. int mode = sde_plane_get_property(pstate,
  2487. PLANE_PROP_FB_TRANSLATION_MODE);
  2488. if ((mode == SDE_DRM_FB_SEC) ||
  2489. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2490. enable = true;
  2491. /* update secure session flag */
  2492. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2493. pstate->multirect_index,
  2494. enable);
  2495. }
  2496. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2497. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2498. {
  2499. const struct sde_format *fmt;
  2500. const struct msm_format *msm_fmt;
  2501. struct sde_plane *psde;
  2502. struct drm_plane_state *state;
  2503. struct sde_plane_state *pstate;
  2504. struct sde_rect src, dst;
  2505. const struct sde_rect *crtc_roi;
  2506. bool q16_data = true;
  2507. int idx;
  2508. psde = to_sde_plane(plane);
  2509. state = plane->state;
  2510. pstate = to_sde_plane_state(state);
  2511. msm_fmt = msm_framebuffer_format(fb);
  2512. if (!msm_fmt) {
  2513. SDE_ERROR("crtc%d plane%d: null format\n",
  2514. DRMID(crtc), DRMID(plane));
  2515. return;
  2516. }
  2517. fmt = to_sde_format(msm_fmt);
  2518. POPULATE_RECT(&src, state->src_x, state->src_y,
  2519. state->src_w, state->src_h, q16_data);
  2520. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2521. state->crtc_w, state->crtc_h, !q16_data);
  2522. SDE_DEBUG_PLANE(psde,
  2523. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2524. fb->base.id, src.x, src.y, src.w, src.h,
  2525. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2526. (char *)&fmt->base.pixel_format,
  2527. SDE_FORMAT_IS_UBWC(fmt));
  2528. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2529. BIT(SDE_DRM_DEINTERLACE)) {
  2530. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2531. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2532. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2533. src.h /= 2;
  2534. src.y = DIV_ROUND_UP(src.y, 2);
  2535. src.y &= ~0x1;
  2536. }
  2537. /*
  2538. * adjust layer mixer position of the sspp in the presence
  2539. * of a partial update to the active lm origin
  2540. */
  2541. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2542. dst.x -= crtc_roi->x;
  2543. dst.y -= crtc_roi->y;
  2544. /* check for UIDLE */
  2545. if (psde->pipe_hw->ops.setup_uidle)
  2546. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2547. psde->pipe_cfg.src_rect = src;
  2548. psde->pipe_cfg.dst_rect = dst;
  2549. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2550. /* check for color fill */
  2551. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2552. PLANE_PROP_COLOR_FILL);
  2553. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2554. /* skip remaining processing on color fill */
  2555. pstate->dirty = 0x0;
  2556. } else if (psde->pipe_hw->ops.setup_rects) {
  2557. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2558. &psde->pipe_cfg,
  2559. pstate->multirect_index);
  2560. }
  2561. if (psde->pipe_hw->ops.setup_pe &&
  2562. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2563. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2564. &pstate->pixel_ext);
  2565. /**
  2566. * when programmed in multirect mode, scalar block will be
  2567. * bypassed. Still we need to update alpha and bitwidth
  2568. * ONLY for RECT0
  2569. */
  2570. if (psde->pipe_hw->ops.setup_scaler &&
  2571. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2572. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2573. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2574. &psde->pipe_cfg, &pstate->pixel_ext,
  2575. &pstate->scaler3_cfg);
  2576. }
  2577. /* update excl rect */
  2578. if (psde->pipe_hw->ops.setup_excl_rect)
  2579. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2580. &pstate->excl_rect,
  2581. pstate->multirect_index);
  2582. if (psde->pipe_hw->ops.setup_multirect)
  2583. psde->pipe_hw->ops.setup_multirect(
  2584. psde->pipe_hw,
  2585. pstate->multirect_index,
  2586. pstate->multirect_mode);
  2587. }
  2588. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2589. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2590. {
  2591. uint32_t src_flags = 0;
  2592. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2593. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2594. src_flags |= SDE_SSPP_FLIP_LR;
  2595. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2596. src_flags |= SDE_SSPP_FLIP_UD;
  2597. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2598. src_flags |= SDE_SSPP_ROT_90;
  2599. /* update format */
  2600. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2601. pstate->const_alpha_en, src_flags,
  2602. pstate->multirect_index);
  2603. if (psde->pipe_hw->ops.setup_cdp) {
  2604. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2605. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2606. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2607. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2608. cdp_cfg->ubwc_meta_enable =
  2609. SDE_FORMAT_IS_UBWC(fmt);
  2610. cdp_cfg->tile_amortize_enable =
  2611. SDE_FORMAT_IS_UBWC(fmt) ||
  2612. SDE_FORMAT_IS_TILE(fmt);
  2613. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2614. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2615. pstate->multirect_index);
  2616. }
  2617. _sde_plane_sspp_setup_sys_cache(psde, pstate, fmt);
  2618. /* update csc */
  2619. if (SDE_FORMAT_IS_YUV(fmt))
  2620. _sde_plane_setup_csc(psde);
  2621. else
  2622. psde->csc_ptr = 0;
  2623. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2624. uint32_t pma_mode = 0;
  2625. if (fmt->alpha_enable)
  2626. pma_mode = (uint32_t) sde_plane_get_property(
  2627. pstate, PLANE_PROP_INVERSE_PMA);
  2628. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2629. pstate->multirect_index, pma_mode);
  2630. }
  2631. if (psde->pipe_hw->ops.setup_dgm_csc)
  2632. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2633. pstate->multirect_index, psde->csc_usr_ptr);
  2634. }
  2635. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2636. {
  2637. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2638. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2639. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2640. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2641. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2642. &psde->sharp_cfg);
  2643. }
  2644. static void _sde_plane_update_properties(struct drm_plane *plane,
  2645. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2646. {
  2647. uint32_t nplanes;
  2648. const struct msm_format *msm_fmt;
  2649. const struct sde_format *fmt;
  2650. struct sde_plane *psde;
  2651. struct drm_plane_state *state;
  2652. struct sde_plane_state *pstate;
  2653. psde = to_sde_plane(plane);
  2654. state = plane->state;
  2655. pstate = to_sde_plane_state(state);
  2656. if (!pstate) {
  2657. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2658. return;
  2659. }
  2660. msm_fmt = msm_framebuffer_format(fb);
  2661. if (!msm_fmt) {
  2662. SDE_ERROR("crtc%d plane%d: null format\n",
  2663. DRMID(crtc), DRMID(plane));
  2664. return;
  2665. }
  2666. fmt = to_sde_format(msm_fmt);
  2667. nplanes = fmt->num_planes;
  2668. /* update secure session flag */
  2669. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2670. _sde_plane_update_secure_session(psde, pstate);
  2671. /* update roi config */
  2672. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2673. _sde_plane_update_roi_config(plane, crtc, fb);
  2674. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2675. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2676. psde->pipe_hw->ops.setup_format)
  2677. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2678. sde_color_process_plane_setup(plane);
  2679. /* update sharpening */
  2680. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2681. psde->pipe_hw->ops.setup_sharpening)
  2682. _sde_plane_update_sharpening(psde);
  2683. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2684. SDE_PLANE_DIRTY_FORMAT))
  2685. _sde_plane_set_qos_lut(plane, crtc, fb);
  2686. if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  2687. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2688. _sde_plane_set_ot_limit(plane, crtc);
  2689. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2690. _sde_plane_set_ts_prefill(plane, pstate);
  2691. }
  2692. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2693. _sde_plane_set_qos_remap(plane);
  2694. /* clear dirty */
  2695. pstate->dirty = 0x0;
  2696. }
  2697. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2698. struct drm_plane_state *old_state)
  2699. {
  2700. struct sde_plane *psde;
  2701. struct drm_plane_state *state;
  2702. struct sde_plane_state *pstate;
  2703. struct sde_plane_state *old_pstate;
  2704. struct drm_crtc *crtc;
  2705. struct drm_framebuffer *fb;
  2706. int idx;
  2707. int dirty_prop_flag;
  2708. bool is_rt;
  2709. if (!plane) {
  2710. SDE_ERROR("invalid plane\n");
  2711. return -EINVAL;
  2712. } else if (!plane->state) {
  2713. SDE_ERROR("invalid plane state\n");
  2714. return -EINVAL;
  2715. } else if (!old_state) {
  2716. SDE_ERROR("invalid old state\n");
  2717. return -EINVAL;
  2718. }
  2719. psde = to_sde_plane(plane);
  2720. state = plane->state;
  2721. pstate = to_sde_plane_state(state);
  2722. old_pstate = to_sde_plane_state(old_state);
  2723. crtc = state->crtc;
  2724. fb = state->fb;
  2725. if (!crtc || !fb) {
  2726. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2727. !crtc, !fb);
  2728. return -EINVAL;
  2729. }
  2730. SDE_DEBUG(
  2731. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2732. plane->base.id,
  2733. state->fb->width, state->fb->height,
  2734. (char *) &state->fb->format->format,
  2735. state->fb->modifier,
  2736. state->src_w >> 16, state->src_h >> 16,
  2737. state->src_x >> 16, state->src_y >> 16,
  2738. pstate->rotation,
  2739. state->crtc_w, state->crtc_h,
  2740. state->crtc_x, state->crtc_y);
  2741. /* force reprogramming of all the parameters, if the flag is set */
  2742. if (psde->revalidate) {
  2743. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2744. plane->base.id);
  2745. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2746. psde->revalidate = false;
  2747. }
  2748. /* determine what needs to be refreshed */
  2749. mutex_lock(&psde->property_info.property_lock);
  2750. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2751. &pstate->property_state)) >= 0) {
  2752. dirty_prop_flag = plane_prop_array[idx];
  2753. pstate->dirty |= dirty_prop_flag;
  2754. }
  2755. mutex_unlock(&psde->property_info.property_lock);
  2756. /**
  2757. * since plane_atomic_check is invoked before crtc_atomic_check
  2758. * in the commit sequence, all the parameters for updating the
  2759. * plane dirty flag will not be available during
  2760. * plane_atomic_check as some features params are updated
  2761. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2762. * before sspp update.
  2763. */
  2764. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2765. old_state);
  2766. /* re-program the output rects always if partial update roi changed */
  2767. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2768. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2769. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2770. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2771. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2772. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2773. if (is_rt != psde->is_rt_pipe) {
  2774. psde->is_rt_pipe = is_rt;
  2775. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2776. }
  2777. /* early out if nothing dirty */
  2778. if (!pstate->dirty)
  2779. return 0;
  2780. pstate->pending = true;
  2781. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2782. _sde_plane_update_properties(plane, crtc, fb);
  2783. return 0;
  2784. }
  2785. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2786. struct drm_plane_state *old_state)
  2787. {
  2788. struct sde_plane *psde;
  2789. struct drm_plane_state *state;
  2790. struct sde_plane_state *pstate;
  2791. if (!plane) {
  2792. SDE_ERROR("invalid plane\n");
  2793. return;
  2794. } else if (!plane->state) {
  2795. SDE_ERROR("invalid plane state\n");
  2796. return;
  2797. } else if (!old_state) {
  2798. SDE_ERROR("invalid old state\n");
  2799. return;
  2800. }
  2801. psde = to_sde_plane(plane);
  2802. state = plane->state;
  2803. pstate = to_sde_plane_state(state);
  2804. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2805. pstate->multirect_mode);
  2806. pstate->pending = true;
  2807. if (is_sde_plane_virtual(plane) &&
  2808. psde->pipe_hw && psde->pipe_hw->ops.setup_multirect)
  2809. psde->pipe_hw->ops.setup_multirect(psde->pipe_hw,
  2810. SDE_SSPP_RECT_SOLO, SDE_SSPP_MULTIRECT_NONE);
  2811. }
  2812. static void sde_plane_atomic_update(struct drm_plane *plane,
  2813. struct drm_plane_state *old_state)
  2814. {
  2815. struct sde_plane *psde;
  2816. struct drm_plane_state *state;
  2817. if (!plane) {
  2818. SDE_ERROR("invalid plane\n");
  2819. return;
  2820. } else if (!plane->state) {
  2821. SDE_ERROR("invalid plane state\n");
  2822. return;
  2823. }
  2824. psde = to_sde_plane(plane);
  2825. psde->is_error = false;
  2826. state = plane->state;
  2827. SDE_DEBUG_PLANE(psde, "\n");
  2828. if (!sde_plane_enabled(state)) {
  2829. _sde_plane_atomic_disable(plane, old_state);
  2830. } else {
  2831. int ret;
  2832. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2833. /* atomic_check should have ensured that this doesn't fail */
  2834. WARN_ON(ret < 0);
  2835. }
  2836. }
  2837. void sde_plane_restore(struct drm_plane *plane)
  2838. {
  2839. struct sde_plane *psde;
  2840. if (!plane || !plane->state) {
  2841. SDE_ERROR("invalid plane\n");
  2842. return;
  2843. }
  2844. psde = to_sde_plane(plane);
  2845. /*
  2846. * Revalidate is only true here if idle PC occurred and
  2847. * there is no plane state update in current commit cycle.
  2848. */
  2849. if (!psde->revalidate)
  2850. return;
  2851. SDE_DEBUG_PLANE(psde, "\n");
  2852. /* last plane state is same as current state */
  2853. sde_plane_atomic_update(plane, plane->state);
  2854. }
  2855. bool sde_plane_is_cache_required(struct drm_plane *plane)
  2856. {
  2857. struct sde_plane_state *pstate;
  2858. if (!plane || !plane->state) {
  2859. SDE_ERROR("invalid plane\n");
  2860. return false;
  2861. }
  2862. pstate = to_sde_plane_state(plane->state);
  2863. /* check if llcc is required for the plane */
  2864. if (pstate->sc_cfg.rd_en)
  2865. return true;
  2866. else
  2867. return false;
  2868. }
  2869. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  2870. {
  2871. char feature_name[256];
  2872. if (psde->pipe_sblk->maxhdeciexp) {
  2873. msm_property_install_range(&psde->property_info,
  2874. "h_decimate", 0x0, 0,
  2875. psde->pipe_sblk->maxhdeciexp, 0,
  2876. PLANE_PROP_H_DECIMATE);
  2877. }
  2878. if (psde->pipe_sblk->maxvdeciexp) {
  2879. msm_property_install_range(&psde->property_info,
  2880. "v_decimate", 0x0, 0,
  2881. psde->pipe_sblk->maxvdeciexp, 0,
  2882. PLANE_PROP_V_DECIMATE);
  2883. }
  2884. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  2885. msm_property_install_range(
  2886. &psde->property_info, "scaler_v2",
  2887. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2888. msm_property_install_blob(&psde->property_info,
  2889. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  2890. msm_property_install_blob(&psde->property_info,
  2891. "lut_cir", 0,
  2892. PLANE_PROP_SCALER_LUT_CIR);
  2893. msm_property_install_blob(&psde->property_info,
  2894. "lut_sep", 0,
  2895. PLANE_PROP_SCALER_LUT_SEP);
  2896. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  2897. msm_property_install_range(
  2898. &psde->property_info, "scaler_v2",
  2899. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2900. msm_property_install_blob(&psde->property_info,
  2901. "lut_sep", 0,
  2902. PLANE_PROP_SCALER_LUT_SEP);
  2903. } else if (psde->features & SDE_SSPP_SCALER) {
  2904. msm_property_install_range(
  2905. &psde->property_info, "scaler_v1", 0x0,
  2906. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  2907. }
  2908. if (psde->features & BIT(SDE_SSPP_CSC) ||
  2909. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  2910. msm_property_install_volatile_range(
  2911. &psde->property_info, "csc_v1", 0x0,
  2912. 0, ~0, 0, PLANE_PROP_CSC_V1);
  2913. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  2914. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2915. "SDE_SSPP_HUE_V",
  2916. psde->pipe_sblk->hsic_blk.version >> 16);
  2917. msm_property_install_range(&psde->property_info,
  2918. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2919. PLANE_PROP_HUE_ADJUST);
  2920. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2921. "SDE_SSPP_SATURATION_V",
  2922. psde->pipe_sblk->hsic_blk.version >> 16);
  2923. msm_property_install_range(&psde->property_info,
  2924. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2925. PLANE_PROP_SATURATION_ADJUST);
  2926. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2927. "SDE_SSPP_VALUE_V",
  2928. psde->pipe_sblk->hsic_blk.version >> 16);
  2929. msm_property_install_range(&psde->property_info,
  2930. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2931. PLANE_PROP_VALUE_ADJUST);
  2932. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2933. "SDE_SSPP_CONTRAST_V",
  2934. psde->pipe_sblk->hsic_blk.version >> 16);
  2935. msm_property_install_range(&psde->property_info,
  2936. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2937. PLANE_PROP_CONTRAST_ADJUST);
  2938. }
  2939. }
  2940. /* helper to install properties which are common to planes and crtcs */
  2941. static void _sde_plane_install_properties(struct drm_plane *plane,
  2942. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  2943. {
  2944. static const struct drm_prop_enum_list e_blend_op[] = {
  2945. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  2946. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  2947. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  2948. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  2949. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  2950. };
  2951. static const struct drm_prop_enum_list e_src_config[] = {
  2952. {SDE_DRM_DEINTERLACE, "deinterlace"}
  2953. };
  2954. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  2955. {SDE_DRM_FB_NON_SEC, "non_sec"},
  2956. {SDE_DRM_FB_SEC, "sec"},
  2957. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  2958. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  2959. };
  2960. static const struct drm_prop_enum_list e_multirect_mode[] = {
  2961. {SDE_SSPP_MULTIRECT_NONE, "none"},
  2962. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  2963. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  2964. };
  2965. const struct sde_format_extended *format_list;
  2966. struct sde_kms_info *info;
  2967. struct sde_plane *psde = to_sde_plane(plane);
  2968. bool is_master;
  2969. int zpos_max = 255;
  2970. int zpos_def = 0;
  2971. char feature_name[256];
  2972. uint32_t index;
  2973. if (!plane || !psde) {
  2974. SDE_ERROR("invalid plane\n");
  2975. return;
  2976. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  2977. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  2978. !psde->pipe_hw, !psde->pipe_sblk);
  2979. return;
  2980. } else if (!catalog) {
  2981. SDE_ERROR("invalid catalog\n");
  2982. return;
  2983. }
  2984. psde->catalog = catalog;
  2985. is_master = !psde->is_virtual;
  2986. if (sde_is_custom_client()) {
  2987. if (catalog->mixer_count &&
  2988. catalog->mixer[0].sblk->maxblendstages) {
  2989. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  2990. if (catalog->has_base_layer &&
  2991. (zpos_max > SDE_STAGE_MAX - 1))
  2992. zpos_max = SDE_STAGE_MAX - 1;
  2993. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  2994. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  2995. }
  2996. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  2997. /* reserve zpos == 0 for primary planes */
  2998. zpos_def = drm_plane_index(plane) + 1;
  2999. }
  3000. msm_property_install_range(&psde->property_info, "zpos",
  3001. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3002. msm_property_install_range(&psde->property_info, "alpha",
  3003. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3004. /* linux default file descriptor range on each process */
  3005. msm_property_install_range(&psde->property_info, "input_fence",
  3006. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3007. if (is_master)
  3008. _sde_plane_install_master_only_properties(psde);
  3009. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3010. msm_property_install_volatile_range(&psde->property_info,
  3011. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3012. sde_plane_rot_install_properties(plane, catalog);
  3013. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3014. e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
  3015. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3016. e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
  3017. if (psde->pipe_hw->ops.setup_solidfill)
  3018. msm_property_install_range(&psde->property_info, "color_fill",
  3019. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3020. msm_property_install_range(&psde->property_info,
  3021. "prefill_size", 0x0, 0, ~0, 0,
  3022. PLANE_PROP_PREFILL_SIZE);
  3023. msm_property_install_range(&psde->property_info,
  3024. "prefill_time", 0x0, 0, ~0, 0,
  3025. PLANE_PROP_PREFILL_TIME);
  3026. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3027. if (!info) {
  3028. SDE_ERROR("failed to allocate info memory\n");
  3029. return;
  3030. }
  3031. msm_property_install_blob(&psde->property_info, "capabilities",
  3032. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3033. sde_kms_info_reset(info);
  3034. if (is_master) {
  3035. format_list = psde->pipe_sblk->format_list;
  3036. } else {
  3037. format_list = psde->pipe_sblk->virt_format_list;
  3038. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3039. master_plane_id);
  3040. msm_property_install_enum(&psde->property_info,
  3041. "multirect_mode", 0x0, 0, e_multirect_mode,
  3042. ARRAY_SIZE(e_multirect_mode),
  3043. PLANE_PROP_MULTIRECT_MODE);
  3044. }
  3045. if (format_list) {
  3046. sde_kms_info_start(info, "pixel_formats");
  3047. while (format_list->fourcc_format) {
  3048. sde_kms_info_append_format(info,
  3049. format_list->fourcc_format,
  3050. format_list->modifier);
  3051. ++format_list;
  3052. }
  3053. sde_kms_info_stop(info);
  3054. }
  3055. if (psde->pipe_hw && psde->pipe_hw->ops.get_scaler_ver)
  3056. sde_kms_info_add_keyint(info, "scaler_step_ver",
  3057. psde->pipe_hw->ops.get_scaler_ver(psde->pipe_hw));
  3058. sde_kms_info_add_keyint(info, "max_linewidth",
  3059. psde->pipe_sblk->maxlinewidth);
  3060. sde_kms_info_add_keyint(info, "max_upscale",
  3061. psde->pipe_sblk->maxupscale);
  3062. sde_kms_info_add_keyint(info, "max_downscale",
  3063. psde->pipe_sblk->maxdwnscale);
  3064. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3065. psde->pipe_sblk->maxhdeciexp);
  3066. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3067. psde->pipe_sblk->maxvdeciexp);
  3068. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3069. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3070. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3071. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3072. index = (master_plane_id == 0) ? 0 : 1;
  3073. if (catalog->has_demura &&
  3074. catalog->demura_supported[psde->pipe][index] != ~0x0) {
  3075. sde_kms_info_add_keyint(info, "demura_block", index);
  3076. sde_kms_info_add_keyint(info, "demura_pipe_id",
  3077. psde->pipe - SSPP_DMA0);
  3078. }
  3079. if ((is_master &&
  3080. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3081. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3082. msm_property_install_range(&psde->property_info,
  3083. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3084. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3085. }
  3086. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3087. msm_property_install_volatile_range(
  3088. &psde->property_info, "csc_dma_v1", 0x0,
  3089. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3090. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3091. }
  3092. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3093. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3094. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3095. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3096. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3097. const struct sde_format_extended *inline_rot_fmt_list;
  3098. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3099. catalog->true_inline_rot_rev);
  3100. sde_kms_info_add_keyint(info,
  3101. "true_inline_dwnscale_rt",
  3102. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3103. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3104. sde_kms_info_add_keyint(info,
  3105. "true_inline_dwnscale_rt_numerator",
  3106. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3107. sde_kms_info_add_keyint(info,
  3108. "true_inline_dwnscale_rt_denominator",
  3109. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3110. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3111. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3112. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3113. psde->pipe_sblk->in_rot_maxheight);
  3114. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3115. if (inline_rot_fmt_list) {
  3116. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3117. while (inline_rot_fmt_list->fourcc_format) {
  3118. sde_kms_info_append_format(info,
  3119. inline_rot_fmt_list->fourcc_format,
  3120. inline_rot_fmt_list->modifier);
  3121. ++inline_rot_fmt_list;
  3122. }
  3123. sde_kms_info_stop(info);
  3124. }
  3125. }
  3126. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3127. info->data, SDE_KMS_INFO_DATALEN(info),
  3128. PLANE_PROP_INFO);
  3129. kfree(info);
  3130. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3131. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3132. "SDE_SSPP_SKIN_COLOR_V",
  3133. psde->pipe_sblk->memcolor_blk.version >> 16);
  3134. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3135. PLANE_PROP_SKIN_COLOR);
  3136. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3137. "SDE_SSPP_SKY_COLOR_V",
  3138. psde->pipe_sblk->memcolor_blk.version >> 16);
  3139. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3140. PLANE_PROP_SKY_COLOR);
  3141. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3142. "SDE_SSPP_FOLIAGE_COLOR_V",
  3143. psde->pipe_sblk->memcolor_blk.version >> 16);
  3144. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3145. PLANE_PROP_FOLIAGE_COLOR);
  3146. }
  3147. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3148. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3149. "SDE_VIG_3D_LUT_GAMUT_V",
  3150. psde->pipe_sblk->gamut_blk.version >> 16);
  3151. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3152. PLANE_PROP_VIG_GAMUT);
  3153. }
  3154. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3155. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3156. "SDE_VIG_1D_LUT_IGC_V",
  3157. psde->pipe_sblk->igc_blk[0].version >> 16);
  3158. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3159. PLANE_PROP_VIG_IGC);
  3160. }
  3161. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3162. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3163. "SDE_DGM_1D_LUT_IGC_V",
  3164. psde->pipe_sblk->igc_blk[0].version >> 16);
  3165. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3166. PLANE_PROP_DMA_IGC);
  3167. }
  3168. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3169. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3170. "SDE_DGM_1D_LUT_GC_V",
  3171. psde->pipe_sblk->gc_blk[0].version >> 16);
  3172. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3173. PLANE_PROP_DMA_GC);
  3174. }
  3175. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3176. 0x0,
  3177. 0, e_fb_translation_mode,
  3178. ARRAY_SIZE(e_fb_translation_mode),
  3179. PLANE_PROP_FB_TRANSLATION_MODE);
  3180. }
  3181. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3182. void __user *usr_ptr)
  3183. {
  3184. struct sde_drm_csc_v1 csc_v1;
  3185. int i;
  3186. if (!psde) {
  3187. SDE_ERROR("invalid plane\n");
  3188. return;
  3189. }
  3190. psde->csc_usr_ptr = NULL;
  3191. if (!usr_ptr) {
  3192. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3193. return;
  3194. }
  3195. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3196. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3197. return;
  3198. }
  3199. /* populate from user space */
  3200. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3201. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3202. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3203. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3204. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3205. }
  3206. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3207. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3208. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3209. }
  3210. psde->csc_usr_ptr = &psde->csc_cfg;
  3211. }
  3212. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3213. struct sde_plane_state *pstate, void __user *usr)
  3214. {
  3215. struct sde_drm_scaler_v1 scale_v1;
  3216. struct sde_hw_pixel_ext *pe;
  3217. int i;
  3218. if (!psde || !pstate) {
  3219. SDE_ERROR("invalid argument(s)\n");
  3220. return;
  3221. }
  3222. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3223. if (!usr) {
  3224. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3225. return;
  3226. }
  3227. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3228. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3229. return;
  3230. }
  3231. /* force property to be dirty, even if the pointer didn't change */
  3232. msm_property_set_dirty(&psde->property_info,
  3233. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3234. /* populate from user space */
  3235. pe = &pstate->pixel_ext;
  3236. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3237. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3238. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3239. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3240. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3241. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3242. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3243. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3244. }
  3245. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3246. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3247. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3248. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3249. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3250. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3251. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3252. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3253. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3254. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3255. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3256. }
  3257. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3258. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3259. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3260. }
  3261. static void _sde_plane_clear_predownscale_settings(
  3262. struct sde_plane_state *pstate)
  3263. {
  3264. pstate->pre_down.pre_downscale_x_0 = 0;
  3265. pstate->pre_down.pre_downscale_x_1 = 0;
  3266. pstate->pre_down.pre_downscale_y_0 = 0;
  3267. pstate->pre_down.pre_downscale_y_1 = 0;
  3268. }
  3269. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3270. struct sde_plane_state *pstate, void __user *usr)
  3271. {
  3272. struct sde_drm_scaler_v2 scale_v2;
  3273. struct sde_hw_pixel_ext *pe;
  3274. int i;
  3275. struct sde_hw_scaler3_cfg *cfg;
  3276. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3277. if (!psde || !pstate) {
  3278. SDE_ERROR("invalid argument(s)\n");
  3279. return;
  3280. }
  3281. cfg = &pstate->scaler3_cfg;
  3282. pd_cfg = &pstate->pre_down;
  3283. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3284. if (!usr) {
  3285. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3286. cfg->enable = 0;
  3287. _sde_plane_clear_predownscale_settings(pstate);
  3288. goto end;
  3289. }
  3290. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3291. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3292. return;
  3293. }
  3294. /* detach/ignore user data if 'disabled' */
  3295. if (!scale_v2.enable) {
  3296. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3297. cfg->enable = 0;
  3298. _sde_plane_clear_predownscale_settings(pstate);
  3299. goto end;
  3300. }
  3301. /* populate from user space */
  3302. sde_set_scaler_v2(cfg, &scale_v2);
  3303. if (_sde_plane_has_pre_downscale(psde)) {
  3304. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3305. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3306. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3307. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3308. }
  3309. pe = &pstate->pixel_ext;
  3310. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3311. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3312. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3313. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3314. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3315. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3316. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3317. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3318. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3319. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3320. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3321. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3322. }
  3323. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3324. end:
  3325. /* force property to be dirty, even if the pointer didn't change */
  3326. msm_property_set_dirty(&psde->property_info,
  3327. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3328. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3329. cfg->src_width[0], cfg->src_height[0],
  3330. cfg->dst_width, cfg->dst_height);
  3331. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3332. }
  3333. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3334. struct sde_plane_state *pstate, void __user *usr_ptr)
  3335. {
  3336. struct drm_clip_rect excl_rect_v1;
  3337. if (!psde || !pstate) {
  3338. SDE_ERROR("invalid argument(s)\n");
  3339. return;
  3340. }
  3341. if (!usr_ptr) {
  3342. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3343. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3344. return;
  3345. }
  3346. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3347. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3348. return;
  3349. }
  3350. /* populate from user space */
  3351. pstate->excl_rect.x = excl_rect_v1.x1;
  3352. pstate->excl_rect.y = excl_rect_v1.y1;
  3353. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3354. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3355. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3356. pstate->excl_rect.x, pstate->excl_rect.y,
  3357. pstate->excl_rect.w, pstate->excl_rect.h);
  3358. }
  3359. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3360. struct drm_plane_state *state, struct drm_property *property,
  3361. uint64_t val)
  3362. {
  3363. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3364. struct sde_plane_state *pstate;
  3365. int idx, ret = -EINVAL;
  3366. SDE_DEBUG_PLANE(psde, "\n");
  3367. if (!plane) {
  3368. SDE_ERROR("invalid plane\n");
  3369. } else if (!state) {
  3370. SDE_ERROR_PLANE(psde, "invalid state\n");
  3371. } else {
  3372. pstate = to_sde_plane_state(state);
  3373. ret = msm_property_atomic_set(&psde->property_info,
  3374. &pstate->property_state, property, val);
  3375. if (!ret) {
  3376. idx = msm_property_index(&psde->property_info,
  3377. property);
  3378. switch (idx) {
  3379. case PLANE_PROP_INPUT_FENCE:
  3380. _sde_plane_set_input_fence(psde, pstate, val);
  3381. break;
  3382. case PLANE_PROP_CSC_V1:
  3383. case PLANE_PROP_CSC_DMA_V1:
  3384. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3385. break;
  3386. case PLANE_PROP_SCALER_V1:
  3387. _sde_plane_set_scaler_v1(psde, pstate,
  3388. (void *)(uintptr_t)val);
  3389. break;
  3390. case PLANE_PROP_SCALER_V2:
  3391. _sde_plane_set_scaler_v2(psde, pstate,
  3392. (void *)(uintptr_t)val);
  3393. break;
  3394. case PLANE_PROP_EXCL_RECT_V1:
  3395. _sde_plane_set_excl_rect_v1(psde, pstate,
  3396. (void *)(uintptr_t)val);
  3397. break;
  3398. default:
  3399. /* nothing to do */
  3400. break;
  3401. }
  3402. }
  3403. }
  3404. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3405. property->name, property->base.id, val, ret);
  3406. return ret;
  3407. }
  3408. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3409. const struct drm_plane_state *state,
  3410. struct drm_property *property, uint64_t *val)
  3411. {
  3412. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3413. struct sde_plane_state *pstate;
  3414. int ret = -EINVAL;
  3415. if (!plane) {
  3416. SDE_ERROR("invalid plane\n");
  3417. } else if (!state) {
  3418. SDE_ERROR("invalid state\n");
  3419. } else {
  3420. SDE_DEBUG_PLANE(psde, "\n");
  3421. pstate = to_sde_plane_state(state);
  3422. ret = msm_property_atomic_get(&psde->property_info,
  3423. &pstate->property_state, property, val);
  3424. }
  3425. return ret;
  3426. }
  3427. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3428. struct drm_plane_state *plane_state)
  3429. {
  3430. struct sde_plane *psde;
  3431. struct sde_plane_state *pstate;
  3432. struct drm_property *drm_prop;
  3433. enum msm_mdp_plane_property prop_idx;
  3434. if (!plane || !plane_state) {
  3435. SDE_ERROR("invalid params\n");
  3436. return -EINVAL;
  3437. }
  3438. psde = to_sde_plane(plane);
  3439. pstate = to_sde_plane_state(plane_state);
  3440. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3441. uint64_t val = pstate->property_values[prop_idx].value;
  3442. uint64_t def;
  3443. int ret;
  3444. drm_prop = msm_property_index_to_drm_property(
  3445. &psde->property_info, prop_idx);
  3446. if (!drm_prop) {
  3447. /* not all props will be installed, based on caps */
  3448. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3449. prop_idx);
  3450. continue;
  3451. }
  3452. def = msm_property_get_default(&psde->property_info, prop_idx);
  3453. if (val == def)
  3454. continue;
  3455. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3456. drm_prop->name, prop_idx, val, def);
  3457. ret = sde_plane_atomic_set_property(plane, plane_state,
  3458. drm_prop, def);
  3459. if (ret) {
  3460. SDE_ERROR_PLANE(psde,
  3461. "set property failed, idx %d ret %d\n",
  3462. prop_idx, ret);
  3463. continue;
  3464. }
  3465. }
  3466. return 0;
  3467. }
  3468. static void sde_plane_destroy(struct drm_plane *plane)
  3469. {
  3470. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3471. SDE_DEBUG_PLANE(psde, "\n");
  3472. if (psde) {
  3473. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3474. if (psde->blob_info)
  3475. drm_property_blob_put(psde->blob_info);
  3476. msm_property_destroy(&psde->property_info);
  3477. mutex_destroy(&psde->lock);
  3478. /* this will destroy the states as well */
  3479. drm_plane_cleanup(plane);
  3480. if (psde->pipe_hw)
  3481. sde_hw_sspp_destroy(psde->pipe_hw);
  3482. kfree(psde);
  3483. }
  3484. }
  3485. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3486. {
  3487. struct sde_plane_state *pstate;
  3488. if (!state) {
  3489. SDE_ERROR("invalid arg state %d\n", !state);
  3490. return;
  3491. }
  3492. pstate = to_sde_plane_state(state);
  3493. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3494. SDE_DRM_FB_SEC) {
  3495. /* remove ref count for frame buffers */
  3496. if (state->fb) {
  3497. drm_framebuffer_put(state->fb);
  3498. state->fb = NULL;
  3499. }
  3500. }
  3501. }
  3502. static void sde_plane_destroy_state(struct drm_plane *plane,
  3503. struct drm_plane_state *state)
  3504. {
  3505. struct sde_plane *psde;
  3506. struct sde_plane_state *pstate;
  3507. if (!plane || !state) {
  3508. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3509. !plane, !state);
  3510. return;
  3511. }
  3512. psde = to_sde_plane(plane);
  3513. pstate = to_sde_plane_state(state);
  3514. SDE_DEBUG_PLANE(psde, "\n");
  3515. /* remove ref count for frame buffers */
  3516. if (state->fb)
  3517. drm_framebuffer_put(state->fb);
  3518. /* remove ref count for fence */
  3519. if (pstate->input_fence)
  3520. sde_sync_put(pstate->input_fence);
  3521. /* destroy value helper */
  3522. msm_property_destroy_state(&psde->property_info, pstate,
  3523. &pstate->property_state);
  3524. }
  3525. static struct drm_plane_state *
  3526. sde_plane_duplicate_state(struct drm_plane *plane)
  3527. {
  3528. struct sde_plane *psde;
  3529. struct sde_plane_state *pstate;
  3530. struct sde_plane_state *old_state;
  3531. struct drm_property *drm_prop;
  3532. uint64_t input_fence_default;
  3533. if (!plane) {
  3534. SDE_ERROR("invalid plane\n");
  3535. return NULL;
  3536. } else if (!plane->state) {
  3537. SDE_ERROR("invalid plane state\n");
  3538. return NULL;
  3539. }
  3540. old_state = to_sde_plane_state(plane->state);
  3541. psde = to_sde_plane(plane);
  3542. pstate = msm_property_alloc_state(&psde->property_info);
  3543. if (!pstate) {
  3544. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3545. return NULL;
  3546. }
  3547. SDE_DEBUG_PLANE(psde, "\n");
  3548. /* duplicate value helper */
  3549. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3550. &pstate->property_state, pstate->property_values);
  3551. /* clear out any input fence */
  3552. pstate->input_fence = 0;
  3553. input_fence_default = msm_property_get_default(
  3554. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3555. drm_prop = msm_property_index_to_drm_property(
  3556. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3557. if (msm_property_atomic_set(&psde->property_info,
  3558. &pstate->property_state, drm_prop,
  3559. input_fence_default))
  3560. SDE_DEBUG_PLANE(psde,
  3561. "error clearing duplicated input fence\n");
  3562. pstate->dirty = 0x0;
  3563. pstate->pending = false;
  3564. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3565. return &pstate->base;
  3566. }
  3567. static void sde_plane_reset(struct drm_plane *plane)
  3568. {
  3569. struct sde_plane *psde;
  3570. struct sde_plane_state *pstate;
  3571. if (!plane) {
  3572. SDE_ERROR("invalid plane\n");
  3573. return;
  3574. }
  3575. psde = to_sde_plane(plane);
  3576. SDE_DEBUG_PLANE(psde, "\n");
  3577. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3578. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3579. return;
  3580. }
  3581. /* remove previous state, if present */
  3582. if (plane->state) {
  3583. sde_plane_destroy_state(plane, plane->state);
  3584. plane->state = 0;
  3585. }
  3586. pstate = msm_property_alloc_state(&psde->property_info);
  3587. if (!pstate) {
  3588. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3589. return;
  3590. }
  3591. /* reset value helper */
  3592. msm_property_reset_state(&psde->property_info, pstate,
  3593. &pstate->property_state,
  3594. pstate->property_values);
  3595. pstate->base.plane = plane;
  3596. plane->state = &pstate->base;
  3597. }
  3598. u32 sde_plane_get_ubwc_error(struct drm_plane *plane)
  3599. {
  3600. u32 ubwc_error = 0;
  3601. struct sde_plane *psde;
  3602. if (!plane) {
  3603. SDE_ERROR("invalid plane\n");
  3604. return 0;
  3605. }
  3606. psde = to_sde_plane(plane);
  3607. if (!psde->is_virtual && psde->pipe_hw->ops.get_ubwc_error)
  3608. ubwc_error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw);
  3609. return ubwc_error;
  3610. }
  3611. void sde_plane_clear_ubwc_error(struct drm_plane *plane)
  3612. {
  3613. struct sde_plane *psde;
  3614. if (!plane) {
  3615. SDE_ERROR("invalid plane\n");
  3616. return;
  3617. }
  3618. psde = to_sde_plane(plane);
  3619. if (psde->pipe_hw->ops.clear_ubwc_error)
  3620. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw);
  3621. }
  3622. #ifdef CONFIG_DEBUG_FS
  3623. static ssize_t _sde_plane_danger_read(struct file *file,
  3624. char __user *buff, size_t count, loff_t *ppos)
  3625. {
  3626. struct sde_kms *kms = file->private_data;
  3627. struct sde_mdss_cfg *cfg = kms->catalog;
  3628. int len = 0;
  3629. char buf[40] = {'\0'};
  3630. if (!cfg)
  3631. return -ENODEV;
  3632. if (*ppos)
  3633. return 0; /* the end */
  3634. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3635. if (len < 0 || len >= sizeof(buf))
  3636. return 0;
  3637. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3638. return -EFAULT;
  3639. *ppos += len; /* increase offset */
  3640. return len;
  3641. }
  3642. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3643. {
  3644. struct drm_plane *plane;
  3645. drm_for_each_plane(plane, kms->dev) {
  3646. if (plane->fb && plane->state) {
  3647. sde_plane_danger_signal_ctrl(plane, enable);
  3648. SDE_DEBUG("plane:%d img:%dx%d ",
  3649. plane->base.id, plane->fb->width,
  3650. plane->fb->height);
  3651. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3652. plane->state->src_x >> 16,
  3653. plane->state->src_y >> 16,
  3654. plane->state->src_w >> 16,
  3655. plane->state->src_h >> 16,
  3656. plane->state->crtc_x, plane->state->crtc_y,
  3657. plane->state->crtc_w, plane->state->crtc_h);
  3658. } else {
  3659. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3660. }
  3661. }
  3662. }
  3663. static ssize_t _sde_plane_danger_write(struct file *file,
  3664. const char __user *user_buf, size_t count, loff_t *ppos)
  3665. {
  3666. struct sde_kms *kms = file->private_data;
  3667. struct sde_mdss_cfg *cfg = kms->catalog;
  3668. int disable_panic;
  3669. char buf[10];
  3670. if (!cfg)
  3671. return -EFAULT;
  3672. if (count >= sizeof(buf))
  3673. return -EFAULT;
  3674. if (copy_from_user(buf, user_buf, count))
  3675. return -EFAULT;
  3676. buf[count] = 0; /* end of string */
  3677. if (kstrtoint(buf, 0, &disable_panic))
  3678. return -EFAULT;
  3679. if (disable_panic) {
  3680. /* Disable panic signal for all active pipes */
  3681. SDE_DEBUG("Disabling danger:\n");
  3682. _sde_plane_set_danger_state(kms, false);
  3683. kms->has_danger_ctrl = false;
  3684. } else {
  3685. /* Enable panic signal for all active pipes */
  3686. SDE_DEBUG("Enabling danger:\n");
  3687. kms->has_danger_ctrl = true;
  3688. _sde_plane_set_danger_state(kms, true);
  3689. }
  3690. return count;
  3691. }
  3692. static const struct file_operations sde_plane_danger_enable = {
  3693. .open = simple_open,
  3694. .read = _sde_plane_danger_read,
  3695. .write = _sde_plane_danger_write,
  3696. };
  3697. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3698. {
  3699. struct sde_plane *psde;
  3700. struct sde_kms *kms;
  3701. struct msm_drm_private *priv;
  3702. const struct sde_sspp_sub_blks *sblk = 0;
  3703. const struct sde_sspp_cfg *cfg = 0;
  3704. if (!plane || !plane->dev) {
  3705. SDE_ERROR("invalid arguments\n");
  3706. return -EINVAL;
  3707. }
  3708. priv = plane->dev->dev_private;
  3709. if (!priv || !priv->kms) {
  3710. SDE_ERROR("invalid KMS reference\n");
  3711. return -EINVAL;
  3712. }
  3713. kms = to_sde_kms(priv->kms);
  3714. psde = to_sde_plane(plane);
  3715. if (psde && psde->pipe_hw)
  3716. cfg = psde->pipe_hw->cap;
  3717. if (cfg)
  3718. sblk = cfg->sblk;
  3719. if (!sblk)
  3720. return 0;
  3721. /* create overall sub-directory for the pipe */
  3722. psde->debugfs_root =
  3723. debugfs_create_dir(psde->pipe_name,
  3724. plane->dev->primary->debugfs_root);
  3725. if (!psde->debugfs_root)
  3726. return -ENOMEM;
  3727. /* don't error check these */
  3728. debugfs_create_x32("features", 0400,
  3729. psde->debugfs_root, &psde->features);
  3730. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3731. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3732. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3733. debugfs_create_bool("default_scaling",
  3734. 0600,
  3735. psde->debugfs_root,
  3736. &psde->debugfs_default_scale);
  3737. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3738. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3739. 0600,
  3740. psde->debugfs_root,
  3741. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3742. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3743. 0600,
  3744. psde->debugfs_root,
  3745. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3746. debugfs_create_u32("in_rot_max_downscale_nrt",
  3747. 0600,
  3748. psde->debugfs_root,
  3749. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3750. debugfs_create_u32("in_rot_max_height",
  3751. 0600,
  3752. psde->debugfs_root,
  3753. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3754. }
  3755. debugfs_create_u32("xin_id",
  3756. 0400,
  3757. psde->debugfs_root,
  3758. (u32 *) &cfg->xin_id);
  3759. debugfs_create_x32("creq_vblank",
  3760. 0600,
  3761. psde->debugfs_root,
  3762. (u32 *) &sblk->creq_vblank);
  3763. debugfs_create_x32("danger_vblank",
  3764. 0600,
  3765. psde->debugfs_root,
  3766. (u32 *) &sblk->danger_vblank);
  3767. debugfs_create_file("disable_danger",
  3768. 0600,
  3769. psde->debugfs_root,
  3770. kms, &sde_plane_danger_enable);
  3771. return 0;
  3772. }
  3773. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3774. {
  3775. struct sde_plane *psde;
  3776. if (!plane)
  3777. return;
  3778. psde = to_sde_plane(plane);
  3779. debugfs_remove_recursive(psde->debugfs_root);
  3780. }
  3781. #else
  3782. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3783. {
  3784. return 0;
  3785. }
  3786. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3787. {
  3788. }
  3789. #endif
  3790. static int sde_plane_late_register(struct drm_plane *plane)
  3791. {
  3792. return _sde_plane_init_debugfs(plane);
  3793. }
  3794. static void sde_plane_early_unregister(struct drm_plane *plane)
  3795. {
  3796. _sde_plane_destroy_debugfs(plane);
  3797. }
  3798. static const struct drm_plane_funcs sde_plane_funcs = {
  3799. .update_plane = drm_atomic_helper_update_plane,
  3800. .disable_plane = drm_atomic_helper_disable_plane,
  3801. .destroy = sde_plane_destroy,
  3802. .atomic_set_property = sde_plane_atomic_set_property,
  3803. .atomic_get_property = sde_plane_atomic_get_property,
  3804. .reset = sde_plane_reset,
  3805. .atomic_duplicate_state = sde_plane_duplicate_state,
  3806. .atomic_destroy_state = sde_plane_destroy_state,
  3807. .late_register = sde_plane_late_register,
  3808. .early_unregister = sde_plane_early_unregister,
  3809. };
  3810. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  3811. .prepare_fb = sde_plane_prepare_fb,
  3812. .cleanup_fb = sde_plane_cleanup_fb,
  3813. .atomic_check = sde_plane_atomic_check,
  3814. .atomic_update = sde_plane_atomic_update,
  3815. };
  3816. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  3817. {
  3818. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  3819. }
  3820. bool is_sde_plane_virtual(struct drm_plane *plane)
  3821. {
  3822. return plane ? to_sde_plane(plane)->is_virtual : false;
  3823. }
  3824. /* initialize plane */
  3825. struct drm_plane *sde_plane_init(struct drm_device *dev,
  3826. uint32_t pipe, bool primary_plane,
  3827. unsigned long possible_crtcs, u32 master_plane_id)
  3828. {
  3829. struct drm_plane *plane = NULL, *master_plane = NULL;
  3830. const struct sde_format_extended *format_list;
  3831. struct sde_plane *psde;
  3832. struct msm_drm_private *priv;
  3833. struct sde_kms *kms;
  3834. enum drm_plane_type type;
  3835. int ret = -EINVAL;
  3836. if (!dev) {
  3837. SDE_ERROR("[%u]device is NULL\n", pipe);
  3838. goto exit;
  3839. }
  3840. priv = dev->dev_private;
  3841. if (!priv) {
  3842. SDE_ERROR("[%u]private data is NULL\n", pipe);
  3843. goto exit;
  3844. }
  3845. if (!priv->kms) {
  3846. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  3847. goto exit;
  3848. }
  3849. kms = to_sde_kms(priv->kms);
  3850. if (!kms->catalog) {
  3851. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  3852. goto exit;
  3853. }
  3854. /* create and zero local structure */
  3855. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  3856. if (!psde) {
  3857. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  3858. ret = -ENOMEM;
  3859. goto exit;
  3860. }
  3861. /* cache local stuff for later */
  3862. plane = &psde->base;
  3863. psde->pipe = pipe;
  3864. psde->is_virtual = (master_plane_id != 0);
  3865. INIT_LIST_HEAD(&psde->mplane_list);
  3866. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  3867. if (master_plane) {
  3868. struct sde_plane *mpsde = to_sde_plane(master_plane);
  3869. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  3870. }
  3871. /* initialize underlying h/w driver */
  3872. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog,
  3873. psde->is_virtual);
  3874. if (IS_ERR(psde->pipe_hw)) {
  3875. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  3876. ret = PTR_ERR(psde->pipe_hw);
  3877. goto clean_plane;
  3878. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  3879. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  3880. goto clean_sspp;
  3881. }
  3882. /* cache features mask for later */
  3883. psde->features = psde->pipe_hw->cap->features;
  3884. psde->perf_features = psde->pipe_hw->cap->perf_features;
  3885. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  3886. if (!psde->pipe_sblk) {
  3887. SDE_ERROR("[%u]invalid sblk\n", pipe);
  3888. goto clean_sspp;
  3889. }
  3890. if (psde->is_virtual)
  3891. format_list = psde->pipe_sblk->virt_format_list;
  3892. else
  3893. format_list = psde->pipe_sblk->format_list;
  3894. psde->nformats = sde_populate_formats(format_list,
  3895. psde->formats,
  3896. 0,
  3897. ARRAY_SIZE(psde->formats));
  3898. if (!psde->nformats) {
  3899. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  3900. goto clean_sspp;
  3901. }
  3902. if (psde->features & BIT(SDE_SSPP_CURSOR))
  3903. type = DRM_PLANE_TYPE_CURSOR;
  3904. else if (primary_plane)
  3905. type = DRM_PLANE_TYPE_PRIMARY;
  3906. else
  3907. type = DRM_PLANE_TYPE_OVERLAY;
  3908. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  3909. psde->formats, psde->nformats,
  3910. NULL, type, NULL);
  3911. if (ret)
  3912. goto clean_sspp;
  3913. /* Populate static array of plane property flags */
  3914. _sde_plane_map_prop_to_dirty_bits();
  3915. /* success! finalize initialization */
  3916. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  3917. msm_property_init(&psde->property_info, &plane->base, dev,
  3918. priv->plane_property, psde->property_data,
  3919. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  3920. sizeof(struct sde_plane_state));
  3921. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  3922. /* save user friendly pipe name for later */
  3923. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  3924. mutex_init(&psde->lock);
  3925. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  3926. pipe, plane->base.id, master_plane_id);
  3927. return plane;
  3928. clean_sspp:
  3929. if (psde && psde->pipe_hw)
  3930. sde_hw_sspp_destroy(psde->pipe_hw);
  3931. clean_plane:
  3932. kfree(psde);
  3933. exit:
  3934. return ERR_PTR(ret);
  3935. }