hfi.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/delay.h>
  7. #include <linux/slab.h>
  8. #include <linux/random.h>
  9. #include <asm/errno.h>
  10. #include <linux/timer.h>
  11. #include <media/cam_icp.h>
  12. #include <linux/iopoll.h>
  13. #include "cam_io_util.h"
  14. #include "hfi_reg.h"
  15. #include "hfi_sys_defs.h"
  16. #include "hfi_session_defs.h"
  17. #include "hfi_intf.h"
  18. #include "cam_icp_hw_mgr_intf.h"
  19. #include "cam_debug_util.h"
  20. #include "cam_compat.h"
  21. #define HFI_VERSION_INFO_MAJOR_VAL 1
  22. #define HFI_VERSION_INFO_MINOR_VAL 1
  23. #define HFI_VERSION_INFO_STEP_VAL 0
  24. #define HFI_VERSION_INFO_STEP_VAL 0
  25. #define HFI_VERSION_INFO_MAJOR_BMSK 0xFF000000
  26. #define HFI_VERSION_INFO_MAJOR_SHFT 24
  27. #define HFI_VERSION_INFO_MINOR_BMSK 0xFFFF00
  28. #define HFI_VERSION_INFO_MINOR_SHFT 8
  29. #define HFI_VERSION_INFO_STEP_BMSK 0xFF
  30. #define HFI_VERSION_INFO_STEP_SHFT 0
  31. /* TO DO Lower timeout value */
  32. #define HFI_POLL_DELAY_US 10
  33. #define HFI_POLL_TIMEOUT_US 1500000
  34. static struct hfi_info *g_hfi;
  35. unsigned int g_icp_mmu_hdl;
  36. static DEFINE_MUTEX(hfi_cmd_q_mutex);
  37. static DEFINE_MUTEX(hfi_msg_q_mutex);
  38. static void hfi_irq_raise(struct hfi_info *hfi)
  39. {
  40. if (hfi->ops.irq_raise)
  41. hfi->ops.irq_raise(hfi->priv);
  42. }
  43. static void hfi_irq_enable(struct hfi_info *hfi)
  44. {
  45. if (hfi->ops.irq_enable)
  46. hfi->ops.irq_enable(hfi->priv);
  47. }
  48. static void __iomem *hfi_iface_addr(struct hfi_info *hfi)
  49. {
  50. void __iomem *ret = NULL;
  51. if (hfi->ops.iface_addr)
  52. ret = hfi->ops.iface_addr(hfi->priv);
  53. return IS_ERR_OR_NULL(ret) ? NULL : ret;
  54. }
  55. static void hfi_queue_dump(uint32_t *dwords, int count)
  56. {
  57. int i;
  58. int rows;
  59. int remaining;
  60. rows = count / 4;
  61. remaining = count % 4;
  62. for (i = 0; i < rows; i++, dwords += 4)
  63. CAM_DBG(CAM_HFI,
  64. "word[%04d]: 0x%08x 0x%08x 0x%08x 0x%08x",
  65. i * 4, dwords[0], dwords[1], dwords[2], dwords[3]);
  66. if (remaining == 1)
  67. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x", rows * 4, dwords[0]);
  68. else if (remaining == 2)
  69. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x 0x%08x",
  70. rows * 4, dwords[0], dwords[1]);
  71. else if (remaining == 3)
  72. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x 0x%08x 0x%08x",
  73. rows * 4, dwords[0], dwords[1], dwords[2]);
  74. }
  75. void cam_hfi_mini_dump(struct hfi_mini_dump_info *dst)
  76. {
  77. struct hfi_mem_info *hfi_mem = &g_hfi->map;
  78. struct hfi_qtbl *qtbl;
  79. struct hfi_q_hdr *q_hdr;
  80. uint32_t *dwords;
  81. int num_dwords;
  82. if (!hfi_mem) {
  83. CAM_ERR(CAM_HFI, "hfi mem info NULL... unable to dump queues");
  84. return;
  85. }
  86. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  87. q_hdr = &qtbl->q_hdr[Q_CMD];
  88. dwords = (uint32_t *)hfi_mem->cmd_q.kva;
  89. num_dwords = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  90. memcpy(dst->cmd_q, dwords, ICP_CMD_Q_SIZE_IN_BYTES);
  91. q_hdr = &qtbl->q_hdr[Q_MSG];
  92. dwords = (uint32_t *)hfi_mem->msg_q.kva;
  93. memcpy(dst->msg_q, dwords, ICP_CMD_Q_SIZE_IN_BYTES);
  94. dst->msg_q_state = g_hfi->msg_q_state;
  95. dst->cmd_q_state = g_hfi->cmd_q_state;
  96. }
  97. void cam_hfi_queue_dump(void)
  98. {
  99. struct hfi_mem_info *hfi_mem = &g_hfi->map;
  100. struct hfi_qtbl *qtbl;
  101. struct hfi_q_hdr *q_hdr;
  102. uint32_t *dwords;
  103. int num_dwords;
  104. if (!hfi_mem) {
  105. CAM_ERR(CAM_HFI, "hfi mem info NULL... unable to dump queues");
  106. return;
  107. }
  108. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  109. CAM_DBG(CAM_HFI,
  110. "qtbl header: version=0x%08x tbl_size=%u numq=%u qhdr_size=%u",
  111. qtbl->q_tbl_hdr.qtbl_version,
  112. qtbl->q_tbl_hdr.qtbl_size,
  113. qtbl->q_tbl_hdr.qtbl_num_q,
  114. qtbl->q_tbl_hdr.qtbl_qhdr_size);
  115. q_hdr = &qtbl->q_hdr[Q_CMD];
  116. CAM_DBG(CAM_HFI,
  117. "cmd_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
  118. hfi_mem->cmd_q.iova,
  119. q_hdr->qhdr_q_size,
  120. q_hdr->qhdr_read_idx,
  121. q_hdr->qhdr_write_idx);
  122. dwords = (uint32_t *)hfi_mem->cmd_q.kva;
  123. num_dwords = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  124. hfi_queue_dump(dwords, num_dwords);
  125. q_hdr = &qtbl->q_hdr[Q_MSG];
  126. CAM_DBG(CAM_HFI,
  127. "msg_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
  128. hfi_mem->msg_q.iova,
  129. q_hdr->qhdr_q_size,
  130. q_hdr->qhdr_read_idx,
  131. q_hdr->qhdr_write_idx);
  132. dwords = (uint32_t *)hfi_mem->msg_q.kva;
  133. num_dwords = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  134. hfi_queue_dump(dwords, num_dwords);
  135. }
  136. int hfi_write_cmd(void *cmd_ptr)
  137. {
  138. uint32_t size_in_words, empty_space, new_write_idx, read_idx, temp;
  139. uint32_t *write_q, *write_ptr;
  140. struct hfi_qtbl *q_tbl;
  141. struct hfi_q_hdr *q;
  142. int rc = 0;
  143. if (!cmd_ptr) {
  144. CAM_ERR(CAM_HFI, "command is null");
  145. return -EINVAL;
  146. }
  147. mutex_lock(&hfi_cmd_q_mutex);
  148. if (!g_hfi) {
  149. CAM_ERR(CAM_HFI, "HFI interface not setup");
  150. rc = -ENODEV;
  151. goto err;
  152. }
  153. if (g_hfi->hfi_state != HFI_READY ||
  154. !g_hfi->cmd_q_state) {
  155. CAM_ERR(CAM_HFI, "HFI state: %u, cmd q state: %u",
  156. g_hfi->hfi_state, g_hfi->cmd_q_state);
  157. rc = -ENODEV;
  158. goto err;
  159. }
  160. q_tbl = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  161. q = &q_tbl->q_hdr[Q_CMD];
  162. write_q = (uint32_t *)g_hfi->map.cmd_q.kva;
  163. size_in_words = (*(uint32_t *)cmd_ptr) >> BYTE_WORD_SHIFT;
  164. if (!size_in_words) {
  165. CAM_DBG(CAM_HFI, "failed");
  166. rc = -EINVAL;
  167. goto err;
  168. }
  169. read_idx = q->qhdr_read_idx;
  170. empty_space = (q->qhdr_write_idx >= read_idx) ?
  171. (q->qhdr_q_size - (q->qhdr_write_idx - read_idx)) :
  172. (read_idx - q->qhdr_write_idx);
  173. if (empty_space <= size_in_words) {
  174. CAM_ERR(CAM_HFI, "failed: empty space %u, size_in_words %u",
  175. empty_space, size_in_words);
  176. rc = -EIO;
  177. goto err;
  178. }
  179. new_write_idx = q->qhdr_write_idx + size_in_words;
  180. write_ptr = (uint32_t *)(write_q + q->qhdr_write_idx);
  181. if (new_write_idx < q->qhdr_q_size) {
  182. memcpy(write_ptr, (uint8_t *)cmd_ptr,
  183. size_in_words << BYTE_WORD_SHIFT);
  184. } else {
  185. new_write_idx -= q->qhdr_q_size;
  186. temp = (size_in_words - new_write_idx) << BYTE_WORD_SHIFT;
  187. memcpy(write_ptr, (uint8_t *)cmd_ptr, temp);
  188. memcpy(write_q, (uint8_t *)cmd_ptr + temp,
  189. new_write_idx << BYTE_WORD_SHIFT);
  190. }
  191. /*
  192. * To make sure command data in a command queue before
  193. * updating write index
  194. */
  195. wmb();
  196. q->qhdr_write_idx = new_write_idx;
  197. /*
  198. * Before raising interrupt make sure command data is ready for
  199. * firmware to process
  200. */
  201. wmb();
  202. hfi_irq_raise(g_hfi);
  203. /* Ensure HOST2ICP trigger is received by FW */
  204. wmb();
  205. err:
  206. mutex_unlock(&hfi_cmd_q_mutex);
  207. return rc;
  208. }
  209. int hfi_read_message(uint32_t *pmsg, uint8_t q_id,
  210. uint32_t *words_read)
  211. {
  212. struct hfi_qtbl *q_tbl_ptr;
  213. struct hfi_q_hdr *q;
  214. uint32_t new_read_idx, size_in_words, word_diff, temp;
  215. uint32_t *read_q, *read_ptr, *write_ptr;
  216. uint32_t size_upper_bound = 0;
  217. int rc = 0;
  218. if (!pmsg) {
  219. CAM_ERR(CAM_HFI, "Invalid msg");
  220. return -EINVAL;
  221. }
  222. if (q_id > Q_DBG) {
  223. CAM_ERR(CAM_HFI, "Invalid q :%u", q_id);
  224. return -EINVAL;
  225. }
  226. mutex_lock(&hfi_msg_q_mutex);
  227. if (!g_hfi) {
  228. CAM_ERR(CAM_HFI, "hfi not set up yet");
  229. rc = -ENODEV;
  230. goto err;
  231. }
  232. if ((g_hfi->hfi_state != HFI_READY) ||
  233. !g_hfi->msg_q_state) {
  234. CAM_ERR(CAM_HFI, "hfi state: %u, msg q state: %u",
  235. g_hfi->hfi_state, g_hfi->msg_q_state);
  236. rc = -ENODEV;
  237. goto err;
  238. }
  239. q_tbl_ptr = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  240. q = &q_tbl_ptr->q_hdr[q_id];
  241. if (q->qhdr_read_idx == q->qhdr_write_idx) {
  242. CAM_DBG(CAM_HFI, "Q not ready, state:%u, r idx:%u, w idx:%u",
  243. g_hfi->hfi_state, q->qhdr_read_idx, q->qhdr_write_idx);
  244. rc = -EIO;
  245. goto err;
  246. }
  247. if (q_id == Q_MSG) {
  248. read_q = (uint32_t *)g_hfi->map.msg_q.kva;
  249. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS;
  250. } else {
  251. read_q = (uint32_t *)g_hfi->map.dbg_q.kva;
  252. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_IN_WORDS;
  253. }
  254. read_ptr = (uint32_t *)(read_q + q->qhdr_read_idx);
  255. write_ptr = (uint32_t *)(read_q + q->qhdr_write_idx);
  256. if (write_ptr > read_ptr)
  257. size_in_words = write_ptr - read_ptr;
  258. else {
  259. word_diff = read_ptr - write_ptr;
  260. if (q_id == Q_MSG)
  261. size_in_words = (ICP_MSG_Q_SIZE_IN_BYTES >>
  262. BYTE_WORD_SHIFT) - word_diff;
  263. else
  264. size_in_words = (ICP_DBG_Q_SIZE_IN_BYTES >>
  265. BYTE_WORD_SHIFT) - word_diff;
  266. }
  267. if ((size_in_words == 0) ||
  268. (size_in_words > size_upper_bound)) {
  269. CAM_ERR(CAM_HFI, "invalid HFI message packet size - 0x%08x",
  270. size_in_words << BYTE_WORD_SHIFT);
  271. q->qhdr_read_idx = q->qhdr_write_idx;
  272. rc = -EIO;
  273. goto err;
  274. }
  275. new_read_idx = q->qhdr_read_idx + size_in_words;
  276. if (new_read_idx < q->qhdr_q_size) {
  277. memcpy(pmsg, read_ptr, size_in_words << BYTE_WORD_SHIFT);
  278. } else {
  279. new_read_idx -= q->qhdr_q_size;
  280. temp = (size_in_words - new_read_idx) << BYTE_WORD_SHIFT;
  281. memcpy(pmsg, read_ptr, temp);
  282. memcpy((uint8_t *)pmsg + temp, read_q,
  283. new_read_idx << BYTE_WORD_SHIFT);
  284. }
  285. q->qhdr_read_idx = new_read_idx;
  286. *words_read = size_in_words;
  287. /* Memory Barrier to make sure message
  288. * queue parameters are updated after read
  289. */
  290. wmb();
  291. err:
  292. mutex_unlock(&hfi_msg_q_mutex);
  293. return rc;
  294. }
  295. int hfi_cmd_ubwc_config(uint32_t *ubwc_cfg)
  296. {
  297. uint8_t *prop;
  298. struct hfi_cmd_prop *dbg_prop;
  299. uint32_t size = 0;
  300. size = sizeof(struct hfi_cmd_prop) +
  301. sizeof(struct hfi_cmd_ubwc_cfg);
  302. CAM_DBG(CAM_HFI,
  303. "size of ubwc %u, ubwc_cfg [rd-0x%x,wr-0x%x]",
  304. size, ubwc_cfg[0], ubwc_cfg[1]);
  305. prop = kzalloc(size, GFP_KERNEL);
  306. if (!prop)
  307. return -ENOMEM;
  308. dbg_prop = (struct hfi_cmd_prop *)prop;
  309. dbg_prop->size = size;
  310. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  311. dbg_prop->num_prop = 1;
  312. dbg_prop->prop_data[0] = HFI_PROP_SYS_UBWC_CFG;
  313. dbg_prop->prop_data[1] = ubwc_cfg[0];
  314. dbg_prop->prop_data[2] = ubwc_cfg[1];
  315. hfi_write_cmd(prop);
  316. kfree(prop);
  317. return 0;
  318. }
  319. int hfi_cmd_ubwc_config_ext(uint32_t *ubwc_ipe_cfg,
  320. uint32_t *ubwc_bps_cfg)
  321. {
  322. uint8_t *prop;
  323. struct hfi_cmd_prop *dbg_prop;
  324. uint32_t size = 0;
  325. size = sizeof(struct hfi_cmd_prop) +
  326. sizeof(struct hfi_cmd_ubwc_cfg_ext);
  327. CAM_DBG(CAM_HFI,
  328. "size of ubwc %u, ubwc_ipe_cfg[rd-0x%x,wr-0x%x] ubwc_bps_cfg[rd-0x%x,wr-0x%x]",
  329. size, ubwc_ipe_cfg[0], ubwc_ipe_cfg[1],
  330. ubwc_bps_cfg[0], ubwc_bps_cfg[1]);
  331. prop = kzalloc(size, GFP_KERNEL);
  332. if (!prop)
  333. return -ENOMEM;
  334. dbg_prop = (struct hfi_cmd_prop *)prop;
  335. dbg_prop->size = size;
  336. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  337. dbg_prop->num_prop = 1;
  338. dbg_prop->prop_data[0] = HFI_PROPERTY_SYS_UBWC_CONFIG_EX;
  339. dbg_prop->prop_data[1] = ubwc_bps_cfg[0];
  340. dbg_prop->prop_data[2] = ubwc_bps_cfg[1];
  341. dbg_prop->prop_data[3] = ubwc_ipe_cfg[0];
  342. dbg_prop->prop_data[4] = ubwc_ipe_cfg[1];
  343. hfi_write_cmd(prop);
  344. kfree(prop);
  345. return 0;
  346. }
  347. int hfi_enable_ipe_bps_pc(bool enable, uint32_t core_info)
  348. {
  349. uint8_t *prop;
  350. struct hfi_cmd_prop *dbg_prop;
  351. uint32_t size = 0;
  352. size = sizeof(struct hfi_cmd_prop) +
  353. sizeof(struct hfi_ipe_bps_pc);
  354. prop = kzalloc(size, GFP_KERNEL);
  355. if (!prop)
  356. return -ENOMEM;
  357. dbg_prop = (struct hfi_cmd_prop *)prop;
  358. dbg_prop->size = size;
  359. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  360. dbg_prop->num_prop = 1;
  361. dbg_prop->prop_data[0] = HFI_PROP_SYS_IPEBPS_PC;
  362. dbg_prop->prop_data[1] = enable;
  363. dbg_prop->prop_data[2] = core_info;
  364. hfi_write_cmd(prop);
  365. kfree(prop);
  366. return 0;
  367. }
  368. int hfi_set_debug_level(u64 icp_dbg_type, uint32_t lvl)
  369. {
  370. uint8_t *prop;
  371. struct hfi_cmd_prop *dbg_prop;
  372. uint32_t size = 0, val;
  373. val = HFI_DEBUG_MSG_LOW |
  374. HFI_DEBUG_MSG_MEDIUM |
  375. HFI_DEBUG_MSG_HIGH |
  376. HFI_DEBUG_MSG_ERROR |
  377. HFI_DEBUG_MSG_FATAL |
  378. HFI_DEBUG_MSG_PERF |
  379. HFI_DEBUG_CFG_WFI |
  380. HFI_DEBUG_CFG_ARM9WD;
  381. if (lvl > val)
  382. return -EINVAL;
  383. size = sizeof(struct hfi_cmd_prop) +
  384. sizeof(struct hfi_debug);
  385. prop = kzalloc(size, GFP_KERNEL);
  386. if (!prop)
  387. return -ENOMEM;
  388. dbg_prop = (struct hfi_cmd_prop *)prop;
  389. dbg_prop->size = size;
  390. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  391. dbg_prop->num_prop = 1;
  392. dbg_prop->prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  393. dbg_prop->prop_data[1] = lvl;
  394. dbg_prop->prop_data[2] = icp_dbg_type;
  395. hfi_write_cmd(prop);
  396. kfree(prop);
  397. return 0;
  398. }
  399. int hfi_set_fw_dump_level(uint32_t lvl)
  400. {
  401. uint8_t *prop = NULL;
  402. struct hfi_cmd_prop *fw_dump_level_switch_prop = NULL;
  403. uint32_t size = 0;
  404. CAM_DBG(CAM_HFI, "fw dump ENTER");
  405. size = sizeof(struct hfi_cmd_prop) + sizeof(lvl);
  406. prop = kzalloc(size, GFP_KERNEL);
  407. if (!prop)
  408. return -ENOMEM;
  409. fw_dump_level_switch_prop = (struct hfi_cmd_prop *)prop;
  410. fw_dump_level_switch_prop->size = size;
  411. fw_dump_level_switch_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  412. fw_dump_level_switch_prop->num_prop = 1;
  413. fw_dump_level_switch_prop->prop_data[0] = HFI_PROP_SYS_FW_DUMP_CFG;
  414. fw_dump_level_switch_prop->prop_data[1] = lvl;
  415. CAM_DBG(CAM_HFI, "prop->size = %d\n"
  416. "prop->pkt_type = %d\n"
  417. "prop->num_prop = %d\n"
  418. "prop->prop_data[0] = %d\n"
  419. "prop->prop_data[1] = %d\n",
  420. fw_dump_level_switch_prop->size,
  421. fw_dump_level_switch_prop->pkt_type,
  422. fw_dump_level_switch_prop->num_prop,
  423. fw_dump_level_switch_prop->prop_data[0],
  424. fw_dump_level_switch_prop->prop_data[1]);
  425. hfi_write_cmd(prop);
  426. kfree(prop);
  427. return 0;
  428. }
  429. void hfi_send_system_cmd(uint32_t type, uint64_t data, uint32_t size)
  430. {
  431. switch (type) {
  432. case HFI_CMD_SYS_INIT: {
  433. struct hfi_cmd_sys_init init;
  434. memset(&init, 0, sizeof(init));
  435. init.size = sizeof(struct hfi_cmd_sys_init);
  436. init.pkt_type = type;
  437. hfi_write_cmd(&init);
  438. }
  439. break;
  440. case HFI_CMD_SYS_PC_PREP: {
  441. struct hfi_cmd_pc_prep prep;
  442. prep.size = sizeof(struct hfi_cmd_pc_prep);
  443. prep.pkt_type = type;
  444. hfi_write_cmd(&prep);
  445. }
  446. break;
  447. case HFI_CMD_SYS_SET_PROPERTY: {
  448. struct hfi_cmd_prop prop;
  449. if ((uint32_t)data == (uint32_t)HFI_PROP_SYS_DEBUG_CFG) {
  450. prop.size = sizeof(struct hfi_cmd_prop);
  451. prop.pkt_type = type;
  452. prop.num_prop = 1;
  453. prop.prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  454. hfi_write_cmd(&prop);
  455. }
  456. }
  457. break;
  458. case HFI_CMD_SYS_GET_PROPERTY:
  459. break;
  460. case HFI_CMD_SYS_PING: {
  461. struct hfi_cmd_ping_pkt ping;
  462. ping.size = sizeof(struct hfi_cmd_ping_pkt);
  463. ping.pkt_type = type;
  464. ping.user_data = (uint64_t)data;
  465. hfi_write_cmd(&ping);
  466. }
  467. break;
  468. case HFI_CMD_SYS_RESET: {
  469. struct hfi_cmd_sys_reset_pkt reset;
  470. reset.size = sizeof(struct hfi_cmd_sys_reset_pkt);
  471. reset.pkt_type = type;
  472. reset.user_data = (uint64_t)data;
  473. hfi_write_cmd(&reset);
  474. }
  475. break;
  476. case HFI_CMD_IPEBPS_CREATE_HANDLE: {
  477. struct hfi_cmd_create_handle handle;
  478. handle.size = sizeof(struct hfi_cmd_create_handle);
  479. handle.pkt_type = type;
  480. handle.handle_type = (uint32_t)data;
  481. handle.user_data1 = 0;
  482. hfi_write_cmd(&handle);
  483. }
  484. break;
  485. case HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT:
  486. break;
  487. default:
  488. CAM_ERR(CAM_HFI, "command not supported :%d", type);
  489. break;
  490. }
  491. }
  492. int hfi_get_hw_caps(void *query_buf)
  493. {
  494. int i = 0;
  495. struct cam_icp_query_cap_cmd *query_cmd = NULL;
  496. if (!query_buf) {
  497. CAM_ERR(CAM_HFI, "query buf is NULL");
  498. return -EINVAL;
  499. }
  500. query_cmd = (struct cam_icp_query_cap_cmd *)query_buf;
  501. query_cmd->fw_version.major = 0x12;
  502. query_cmd->fw_version.minor = 0x12;
  503. query_cmd->fw_version.revision = 0x12;
  504. query_cmd->api_version.major = 0x13;
  505. query_cmd->api_version.minor = 0x13;
  506. query_cmd->api_version.revision = 0x13;
  507. query_cmd->num_ipe = 2;
  508. query_cmd->num_bps = 1;
  509. for (i = 0; i < CAM_ICP_DEV_TYPE_MAX; i++) {
  510. query_cmd->dev_ver[i].dev_type = i;
  511. query_cmd->dev_ver[i].hw_ver.major = 0x34 + i;
  512. query_cmd->dev_ver[i].hw_ver.minor = 0x34 + i;
  513. query_cmd->dev_ver[i].hw_ver.incr = 0x34 + i;
  514. }
  515. return 0;
  516. }
  517. int cam_hfi_resume(struct hfi_mem_info *hfi_mem)
  518. {
  519. int rc = 0;
  520. uint32_t fw_version, status = 0;
  521. void __iomem *icp_base = hfi_iface_addr(g_hfi);
  522. if (!icp_base) {
  523. CAM_ERR(CAM_HFI, "invalid HFI interface address");
  524. return -EINVAL;
  525. }
  526. if (cam_common_read_poll_timeout(icp_base +
  527. HFI_REG_ICP_HOST_INIT_RESPONSE,
  528. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
  529. 0x1, ICP_INIT_RESP_SUCCESS, &status)) {
  530. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  531. status);
  532. return -ETIMEDOUT;
  533. }
  534. hfi_irq_enable(g_hfi);
  535. fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION);
  536. CAM_DBG(CAM_HFI, "fw version : [%x]", fw_version);
  537. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova, icp_base + HFI_REG_QTBL_PTR);
  538. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  539. icp_base + HFI_REG_SFR_PTR);
  540. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  541. icp_base + HFI_REG_SHARED_MEM_PTR);
  542. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  543. icp_base + HFI_REG_SHARED_MEM_SIZE);
  544. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  545. icp_base + HFI_REG_SECONDARY_HEAP_PTR);
  546. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  547. icp_base + HFI_REG_SECONDARY_HEAP_SIZE);
  548. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  549. icp_base + HFI_REG_QDSS_IOVA);
  550. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  551. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  552. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  553. icp_base + HFI_REG_IO_REGION_IOVA);
  554. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  555. icp_base + HFI_REG_IO_REGION_SIZE);
  556. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  557. icp_base + HFI_REG_IO2_REGION_IOVA);
  558. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  559. icp_base + HFI_REG_IO2_REGION_SIZE);
  560. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.iova,
  561. icp_base + HFI_REG_FWUNCACHED_REGION_IOVA);
  562. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.len,
  563. icp_base + HFI_REG_FWUNCACHED_REGION_SIZE);
  564. CAM_DBG(CAM_HFI, "IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  565. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  566. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  567. CAM_DBG(CAM_HFI, "FwUncached : [0x%x 0x%x] Shared [0x%x 0x%x]",
  568. hfi_mem->fw_uncached.iova, hfi_mem->fw_uncached.len,
  569. hfi_mem->shmem.iova, hfi_mem->shmem.len);
  570. CAM_DBG(CAM_HFI, "SecHeap : [0x%x 0x%x] QDSS [0x%x 0x%x]",
  571. hfi_mem->sec_heap.iova, hfi_mem->sec_heap.len,
  572. hfi_mem->qdss.iova, hfi_mem->qdss.len);
  573. CAM_DBG(CAM_HFI, "QTbl : [0x%x 0x%x] Sfr [0x%x 0x%x]",
  574. hfi_mem->qtbl.iova, hfi_mem->qtbl.len,
  575. hfi_mem->sfr_buf.iova, hfi_mem->sfr_buf.len);
  576. return rc;
  577. }
  578. int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
  579. void *priv, uint8_t event_driven_mode)
  580. {
  581. int rc = 0;
  582. uint32_t status = 0;
  583. struct hfi_qtbl *qtbl;
  584. struct hfi_qtbl_hdr *qtbl_hdr;
  585. struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr, *dbg_q_hdr;
  586. struct sfr_buf *sfr_buffer;
  587. void __iomem *icp_base;
  588. if (!hfi_mem || !hfi_ops || !priv) {
  589. CAM_ERR(CAM_HFI,
  590. "invalid arg: hfi_mem=%pK hfi_ops=%pK priv=%pK",
  591. hfi_mem, hfi_ops, priv);
  592. return -EINVAL;
  593. }
  594. mutex_lock(&hfi_cmd_q_mutex);
  595. mutex_lock(&hfi_msg_q_mutex);
  596. if (!g_hfi) {
  597. g_hfi = kzalloc(sizeof(struct hfi_info), GFP_KERNEL);
  598. if (!g_hfi) {
  599. rc = -ENOMEM;
  600. goto alloc_fail;
  601. }
  602. }
  603. if (g_hfi->hfi_state != HFI_DEINIT) {
  604. CAM_ERR(CAM_HFI, "hfi_init: invalid state");
  605. rc = -EINVAL;
  606. goto regions_fail;
  607. }
  608. memcpy(&g_hfi->map, hfi_mem, sizeof(g_hfi->map));
  609. g_hfi->hfi_state = HFI_DEINIT;
  610. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  611. qtbl_hdr = &qtbl->q_tbl_hdr;
  612. qtbl_hdr->qtbl_version = 0xFFFFFFFF;
  613. qtbl_hdr->qtbl_size = sizeof(struct hfi_qtbl);
  614. qtbl_hdr->qtbl_qhdr0_offset = sizeof(struct hfi_qtbl_hdr);
  615. qtbl_hdr->qtbl_qhdr_size = sizeof(struct hfi_q_hdr);
  616. qtbl_hdr->qtbl_num_q = ICP_HFI_NUMBER_OF_QS;
  617. qtbl_hdr->qtbl_num_active_q = ICP_HFI_NUMBER_OF_QS;
  618. /* setup host-to-firmware command queue */
  619. cmd_q_hdr = &qtbl->q_hdr[Q_CMD];
  620. cmd_q_hdr->qhdr_status = QHDR_ACTIVE;
  621. cmd_q_hdr->qhdr_start_addr = hfi_mem->cmd_q.iova;
  622. cmd_q_hdr->qhdr_q_size = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  623. cmd_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  624. cmd_q_hdr->qhdr_pkt_drop_cnt = RESET;
  625. cmd_q_hdr->qhdr_read_idx = RESET;
  626. cmd_q_hdr->qhdr_write_idx = RESET;
  627. /* setup firmware-to-Host message queue */
  628. msg_q_hdr = &qtbl->q_hdr[Q_MSG];
  629. msg_q_hdr->qhdr_status = QHDR_ACTIVE;
  630. msg_q_hdr->qhdr_start_addr = hfi_mem->msg_q.iova;
  631. msg_q_hdr->qhdr_q_size = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  632. msg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  633. msg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  634. msg_q_hdr->qhdr_read_idx = RESET;
  635. msg_q_hdr->qhdr_write_idx = RESET;
  636. /* setup firmware-to-Host message queue */
  637. dbg_q_hdr = &qtbl->q_hdr[Q_DBG];
  638. dbg_q_hdr->qhdr_status = QHDR_ACTIVE;
  639. dbg_q_hdr->qhdr_start_addr = hfi_mem->dbg_q.iova;
  640. dbg_q_hdr->qhdr_q_size = ICP_DBG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  641. dbg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  642. dbg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  643. dbg_q_hdr->qhdr_read_idx = RESET;
  644. dbg_q_hdr->qhdr_write_idx = RESET;
  645. sfr_buffer = (struct sfr_buf *)hfi_mem->sfr_buf.kva;
  646. sfr_buffer->size = ICP_MSG_SFR_SIZE_IN_BYTES;
  647. switch (event_driven_mode) {
  648. case INTR_MODE:
  649. cmd_q_hdr->qhdr_type = Q_CMD;
  650. cmd_q_hdr->qhdr_rx_wm = SET;
  651. cmd_q_hdr->qhdr_tx_wm = SET;
  652. cmd_q_hdr->qhdr_rx_req = SET;
  653. cmd_q_hdr->qhdr_tx_req = RESET;
  654. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  655. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  656. msg_q_hdr->qhdr_type = Q_MSG;
  657. msg_q_hdr->qhdr_rx_wm = SET;
  658. msg_q_hdr->qhdr_tx_wm = SET;
  659. msg_q_hdr->qhdr_rx_req = SET;
  660. msg_q_hdr->qhdr_tx_req = RESET;
  661. msg_q_hdr->qhdr_rx_irq_status = RESET;
  662. msg_q_hdr->qhdr_tx_irq_status = RESET;
  663. dbg_q_hdr->qhdr_type = Q_DBG;
  664. dbg_q_hdr->qhdr_rx_wm = SET;
  665. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  666. dbg_q_hdr->qhdr_rx_req = RESET;
  667. dbg_q_hdr->qhdr_tx_req = RESET;
  668. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  669. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  670. break;
  671. case POLL_MODE:
  672. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_POLL_MODE_2 |
  673. RX_EVENT_POLL_MODE_2;
  674. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_POLL_MODE_2 |
  675. RX_EVENT_POLL_MODE_2;
  676. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_POLL_MODE_2 |
  677. RX_EVENT_POLL_MODE_2;
  678. break;
  679. case WM_MODE:
  680. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_DRIVEN_MODE_2 |
  681. RX_EVENT_DRIVEN_MODE_2;
  682. cmd_q_hdr->qhdr_rx_wm = SET;
  683. cmd_q_hdr->qhdr_tx_wm = SET;
  684. cmd_q_hdr->qhdr_rx_req = RESET;
  685. cmd_q_hdr->qhdr_tx_req = SET;
  686. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  687. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  688. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_DRIVEN_MODE_2 |
  689. RX_EVENT_DRIVEN_MODE_2;
  690. msg_q_hdr->qhdr_rx_wm = SET;
  691. msg_q_hdr->qhdr_tx_wm = SET;
  692. msg_q_hdr->qhdr_rx_req = SET;
  693. msg_q_hdr->qhdr_tx_req = RESET;
  694. msg_q_hdr->qhdr_rx_irq_status = RESET;
  695. msg_q_hdr->qhdr_tx_irq_status = RESET;
  696. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_DRIVEN_MODE_2 |
  697. RX_EVENT_DRIVEN_MODE_2;
  698. dbg_q_hdr->qhdr_rx_wm = SET;
  699. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  700. dbg_q_hdr->qhdr_rx_req = RESET;
  701. dbg_q_hdr->qhdr_tx_req = RESET;
  702. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  703. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  704. break;
  705. default:
  706. CAM_ERR(CAM_HFI, "Invalid event driven mode :%u",
  707. event_driven_mode);
  708. break;
  709. }
  710. g_hfi->ops = *hfi_ops;
  711. g_hfi->priv = priv;
  712. icp_base = hfi_iface_addr(g_hfi);
  713. if (!icp_base) {
  714. CAM_ERR(CAM_HFI, "invalid HFI interface address");
  715. rc = -EINVAL;
  716. goto regions_fail;
  717. }
  718. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova,
  719. icp_base + HFI_REG_QTBL_PTR);
  720. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  721. icp_base + HFI_REG_SFR_PTR);
  722. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  723. icp_base + HFI_REG_SHARED_MEM_PTR);
  724. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  725. icp_base + HFI_REG_SHARED_MEM_SIZE);
  726. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  727. icp_base + HFI_REG_SECONDARY_HEAP_PTR);
  728. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  729. icp_base + HFI_REG_SECONDARY_HEAP_SIZE);
  730. cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET,
  731. icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
  732. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  733. icp_base + HFI_REG_QDSS_IOVA);
  734. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  735. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  736. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  737. icp_base + HFI_REG_IO_REGION_IOVA);
  738. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  739. icp_base + HFI_REG_IO_REGION_SIZE);
  740. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  741. icp_base + HFI_REG_IO2_REGION_IOVA);
  742. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  743. icp_base + HFI_REG_IO2_REGION_SIZE);
  744. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.iova,
  745. icp_base + HFI_REG_FWUNCACHED_REGION_IOVA);
  746. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.len,
  747. icp_base + HFI_REG_FWUNCACHED_REGION_SIZE);
  748. CAM_DBG(CAM_HFI, "IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  749. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  750. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  751. CAM_DBG(CAM_HFI, "FwUncached : [0x%x 0x%x] Shared [0x%x 0x%x]",
  752. hfi_mem->fw_uncached.iova, hfi_mem->fw_uncached.len,
  753. hfi_mem->shmem.iova, hfi_mem->shmem.len);
  754. CAM_DBG(CAM_HFI, "SecHeap : [0x%x 0x%x] QDSS [0x%x 0x%x]",
  755. hfi_mem->sec_heap.iova, hfi_mem->sec_heap.len,
  756. hfi_mem->qdss.iova, hfi_mem->qdss.len);
  757. CAM_DBG(CAM_HFI, "QTbl : [0x%x 0x%x] Sfr [0x%x 0x%x]",
  758. hfi_mem->qtbl.iova, hfi_mem->qtbl.len,
  759. hfi_mem->sfr_buf.iova, hfi_mem->sfr_buf.len);
  760. if (cam_common_read_poll_timeout(icp_base +
  761. HFI_REG_ICP_HOST_INIT_RESPONSE,
  762. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
  763. 0x1, ICP_INIT_RESP_SUCCESS, &status)) {
  764. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  765. status);
  766. rc = -ETIMEDOUT;
  767. goto regions_fail;
  768. }
  769. CAM_DBG(CAM_HFI, "ICP fw version: 0x%x",
  770. cam_io_r(icp_base + HFI_REG_FW_VERSION));
  771. g_hfi->hfi_state = HFI_READY;
  772. g_hfi->cmd_q_state = true;
  773. g_hfi->msg_q_state = true;
  774. hfi_irq_enable(g_hfi);
  775. mutex_unlock(&hfi_cmd_q_mutex);
  776. mutex_unlock(&hfi_msg_q_mutex);
  777. return rc;
  778. regions_fail:
  779. kfree(g_hfi);
  780. g_hfi = NULL;
  781. alloc_fail:
  782. mutex_unlock(&hfi_cmd_q_mutex);
  783. mutex_unlock(&hfi_msg_q_mutex);
  784. return rc;
  785. }
  786. void cam_hfi_deinit(void)
  787. {
  788. mutex_lock(&hfi_cmd_q_mutex);
  789. mutex_lock(&hfi_msg_q_mutex);
  790. if (!g_hfi) {
  791. CAM_ERR(CAM_HFI, "hfi path not established yet");
  792. goto err;
  793. }
  794. g_hfi->cmd_q_state = false;
  795. g_hfi->msg_q_state = false;
  796. cam_free_clear((void *)g_hfi);
  797. g_hfi = NULL;
  798. err:
  799. mutex_unlock(&hfi_cmd_q_mutex);
  800. mutex_unlock(&hfi_msg_q_mutex);
  801. }