qca6750def.c 8.4 KB

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  1. /*
  2. * Copyright (c) 2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  8. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  9. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  12. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  13. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14. */
  15. #if defined(QCA6750_HEADERS_DEF)
  16. #undef UMAC
  17. #define WLAN_HEADERS 1
  18. #include "lithium_top_reg.h"
  19. #include "wfss_ce_reg_seq_hwioreg.h"
  20. #include "wcss_version.h"
  21. #define MISSING 0
  22. #define SOC_RESET_CONTROL_OFFSET MISSING
  23. #define GPIO_PIN0_OFFSET MISSING
  24. #define GPIO_PIN1_OFFSET MISSING
  25. #define GPIO_PIN0_CONFIG_MASK MISSING
  26. #define GPIO_PIN1_CONFIG_MASK MISSING
  27. #define LOCAL_SCRATCH_OFFSET 0x18
  28. #define GPIO_PIN10_OFFSET MISSING
  29. #define GPIO_PIN11_OFFSET MISSING
  30. #define GPIO_PIN12_OFFSET MISSING
  31. #define GPIO_PIN13_OFFSET MISSING
  32. #define MBOX_BASE_ADDRESS MISSING
  33. #define INT_STATUS_ENABLE_ERROR_LSB MISSING
  34. #define INT_STATUS_ENABLE_ERROR_MASK MISSING
  35. #define INT_STATUS_ENABLE_CPU_LSB MISSING
  36. #define INT_STATUS_ENABLE_CPU_MASK MISSING
  37. #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
  38. #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
  39. #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
  40. #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
  41. #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
  42. #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
  43. #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
  44. #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
  45. #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
  46. #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
  47. #define INT_STATUS_ENABLE_ADDRESS MISSING
  48. #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
  49. #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
  50. #define HOST_INT_STATUS_ADDRESS MISSING
  51. #define CPU_INT_STATUS_ADDRESS MISSING
  52. #define ERROR_INT_STATUS_ADDRESS MISSING
  53. #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
  54. #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
  55. #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
  56. #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
  57. #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
  58. #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
  59. #define COUNT_DEC_ADDRESS MISSING
  60. #define HOST_INT_STATUS_CPU_MASK MISSING
  61. #define HOST_INT_STATUS_CPU_LSB MISSING
  62. #define HOST_INT_STATUS_ERROR_MASK MISSING
  63. #define HOST_INT_STATUS_ERROR_LSB MISSING
  64. #define HOST_INT_STATUS_COUNTER_MASK MISSING
  65. #define HOST_INT_STATUS_COUNTER_LSB MISSING
  66. #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
  67. #define WINDOW_DATA_ADDRESS MISSING
  68. #define WINDOW_READ_ADDR_ADDRESS MISSING
  69. #define WINDOW_WRITE_ADDR_ADDRESS MISSING
  70. /* GPIO Register */
  71. #define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING
  72. #define GPIO_PIN0_CONFIG_LSB MISSING
  73. #define GPIO_PIN0_PAD_PULL_LSB MISSING
  74. #define GPIO_PIN0_PAD_PULL_MASK MISSING
  75. /* SI reg */
  76. #define SI_CONFIG_ERR_INT_MASK MISSING
  77. #define SI_CONFIG_ERR_INT_LSB MISSING
  78. #define RTC_SOC_BASE_ADDRESS MISSING
  79. #define RTC_WMAC_BASE_ADDRESS MISSING
  80. #define SOC_CORE_BASE_ADDRESS MISSING
  81. #define WLAN_MAC_BASE_ADDRESS MISSING
  82. #define GPIO_BASE_ADDRESS MISSING
  83. #define ANALOG_INTF_BASE_ADDRESS MISSING
  84. #define CE0_BASE_ADDRESS MISSING
  85. #define CE1_BASE_ADDRESS MISSING
  86. #define CE_COUNT 12
  87. #define CE_WRAPPER_BASE_ADDRESS MISSING
  88. #define SI_BASE_ADDRESS MISSING
  89. #define DRAM_BASE_ADDRESS MISSING
  90. #define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
  91. #define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
  92. #define CLOCK_CONTROL_OFFSET MISSING
  93. #define CLOCK_CONTROL_SI0_CLK_MASK MISSING
  94. #define RESET_CONTROL_SI0_RST_MASK MISSING
  95. #define WLAN_RESET_CONTROL_OFFSET MISSING
  96. #define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
  97. #define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
  98. #define CPU_CLOCK_OFFSET MISSING
  99. #define CPU_CLOCK_STANDARD_LSB MISSING
  100. #define CPU_CLOCK_STANDARD_MASK MISSING
  101. #define LPO_CAL_ENABLE_LSB MISSING
  102. #define LPO_CAL_ENABLE_MASK MISSING
  103. #define WLAN_SYSTEM_SLEEP_OFFSET MISSING
  104. #define SOC_CHIP_ID_ADDRESS MISSING
  105. #define SOC_CHIP_ID_REVISION_MASK MISSING
  106. #define SOC_CHIP_ID_REVISION_LSB MISSING
  107. #define SOC_CHIP_ID_REVISION_MSB MISSING
  108. #define FW_IND_EVENT_PENDING MISSING
  109. #define FW_IND_INITIALIZED MISSING
  110. #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
  111. #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
  112. #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
  113. #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
  114. #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
  115. #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
  116. #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
  117. #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
  118. #define SR_WR_INDEX_ADDRESS MISSING
  119. #define DST_WATERMARK_ADDRESS MISSING
  120. #define DST_WR_INDEX_ADDRESS MISSING
  121. #define SRC_WATERMARK_ADDRESS MISSING
  122. #define SRC_WATERMARK_LOW_MASK MISSING
  123. #define SRC_WATERMARK_HIGH_MASK MISSING
  124. #define DST_WATERMARK_LOW_MASK MISSING
  125. #define DST_WATERMARK_HIGH_MASK MISSING
  126. #define CURRENT_SRRI_ADDRESS MISSING
  127. #define CURRENT_DRRI_ADDRESS MISSING
  128. #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
  129. #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
  130. #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
  131. #define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
  132. #define HOST_IS_ADDRESS MISSING
  133. #define MISC_IS_ADDRESS MISSING
  134. #define HOST_IS_COPY_COMPLETE_MASK MISSING
  135. #define CE_WRAPPER_BASE_ADDRESS MISSING
  136. #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
  137. #define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
  138. #define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
  139. #define HOST_IE_ADDRESS HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR
  140. #define HOST_IE_ADDRESS_2 HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR
  141. #define HOST_IE_COPY_COMPLETE_MASK MISSING
  142. #define SR_BA_ADDRESS MISSING
  143. #define SR_BA_ADDRESS_HIGH MISSING
  144. #define SR_SIZE_ADDRESS MISSING
  145. #define CE_CTRL1_ADDRESS MISSING
  146. #define CE_CTRL1_DMAX_LENGTH_MASK MISSING
  147. #define DR_BA_ADDRESS MISSING
  148. #define DR_BA_ADDRESS_HIGH MISSING
  149. #define DR_SIZE_ADDRESS MISSING
  150. #define CE_CMD_REGISTER MISSING
  151. #define CE_MSI_ADDRESS MISSING
  152. #define CE_MSI_ADDRESS_HIGH MISSING
  153. #define CE_MSI_DATA MISSING
  154. #define CE_MSI_ENABLE_BIT MISSING
  155. #define MISC_IE_ADDRESS MISSING
  156. #define MISC_IS_AXI_ERR_MASK MISSING
  157. #define MISC_IS_DST_ADDR_ERR_MASK MISSING
  158. #define MISC_IS_SRC_LEN_ERR_MASK MISSING
  159. #define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
  160. #define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
  161. #define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
  162. #define SRC_WATERMARK_LOW_LSB MISSING
  163. #define SRC_WATERMARK_HIGH_LSB MISSING
  164. #define DST_WATERMARK_LOW_LSB MISSING
  165. #define DST_WATERMARK_HIGH_LSB MISSING
  166. #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
  167. #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
  168. #define CE_CTRL1_DMAX_LENGTH_LSB MISSING
  169. #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
  170. #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
  171. #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
  172. #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
  173. #define CE_CTRL1_IDX_UPD_EN_MASK MISSING
  174. #define CE_WRAPPER_DEBUG_OFFSET MISSING
  175. #define CE_WRAPPER_DEBUG_SEL_MSB MISSING
  176. #define CE_WRAPPER_DEBUG_SEL_LSB MISSING
  177. #define CE_WRAPPER_DEBUG_SEL_MASK MISSING
  178. #define CE_DEBUG_OFFSET MISSING
  179. #define CE_DEBUG_SEL_MSB MISSING
  180. #define CE_DEBUG_SEL_LSB MISSING
  181. #define CE_DEBUG_SEL_MASK MISSING
  182. #define CE0_BASE_ADDRESS MISSING
  183. #define CE1_BASE_ADDRESS MISSING
  184. #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
  185. #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
  186. #define QCA6750_BOARD_DATA_SZ MISSING
  187. #define QCA6750_BOARD_EXT_DATA_SZ MISSING
  188. #define MY_TARGET_DEF QCA6750_TARGETdef
  189. #define MY_HOST_DEF QCA6750_HOSTdef
  190. #define MY_CEREG_DEF QCA6750_CE_TARGETdef
  191. #define MY_TARGET_BOARD_DATA_SZ QCA6750_BOARD_DATA_SZ
  192. #define MY_TARGET_BOARD_EXT_DATA_SZ QCA6750_BOARD_EXT_DATA_SZ
  193. #include "targetdef.h"
  194. #include "hostdef.h"
  195. #else
  196. #include "common_drv.h"
  197. #include "targetdef.h"
  198. #include "hostdef.h"
  199. struct targetdef_s *QCA6750_TARGETdef;
  200. struct hostdef_s *QCA6750_HOSTdef;
  201. #endif /*QCA6750_HEADERS_DEF */