hal_tx_hw_defines.h 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143
  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_TX_HW_DEFINES_H_
  19. #define _HAL_TX_HW_DEFINES_H_
  20. #define HAL_TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000
  21. #define HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0
  22. #define HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001
  23. #define HAL_TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000
  24. #define HAL_TX_MSDU_EXTENSION_TCP_FLAG_LSB 7
  25. #define HAL_TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80
  26. #define HAL_TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000
  27. #define HAL_TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16
  28. #define HAL_TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000
  29. #define HAL_TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004
  30. #define HAL_TX_MSDU_EXTENSION_L2_LENGTH_LSB 0
  31. #define HAL_TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff
  32. #define HAL_TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004
  33. #define HAL_TX_MSDU_EXTENSION_IP_LENGTH_LSB 16
  34. #define HAL_TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000
  35. #define HAL_TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008
  36. #define HAL_TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0
  37. #define HAL_TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff
  38. #define HAL_TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c
  39. #define HAL_TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0
  40. #define HAL_TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff
  41. #define HAL_TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018
  42. #define HAL_TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0
  43. #define HAL_TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff
  44. #define HAL_TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c
  45. #define HAL_TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0
  46. #define HAL_TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff
  47. #define HAL_TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c
  48. #define HAL_TX_MSDU_EXTENSION_BUF0_LEN_LSB 16
  49. #define HAL_TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000
  50. #define HAL_TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020
  51. #define HAL_TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0
  52. #define HAL_TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff
  53. #define HAL_TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024
  54. #define HAL_TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0
  55. #define HAL_TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff
  56. #define HAL_TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024
  57. #define HAL_TX_MSDU_EXTENSION_BUF1_LEN_LSB 16
  58. #define HAL_TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000
  59. #define HAL_TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028
  60. #define HAL_TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0
  61. #define HAL_TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff
  62. #define HAL_TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c
  63. #define HAL_TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0
  64. #define HAL_TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff
  65. #define HAL_TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c
  66. #define HAL_TX_MSDU_EXTENSION_BUF2_LEN_LSB 16
  67. #define HAL_TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000
  68. #define HAL_TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030
  69. #define HAL_TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0
  70. #define HAL_TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff
  71. #define HAL_TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034
  72. #define HAL_TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0
  73. #define HAL_TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff
  74. #define HAL_TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034
  75. #define HAL_TX_MSDU_EXTENSION_BUF3_LEN_LSB 16
  76. #define HAL_TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000
  77. #define HAL_TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038
  78. #define HAL_TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0
  79. #define HAL_TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff
  80. #define HAL_TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c
  81. #define HAL_TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0
  82. #define HAL_TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff
  83. #define HAL_TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c
  84. #define HAL_TX_MSDU_EXTENSION_BUF4_LEN_LSB 16
  85. #define HAL_TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000
  86. #define HAL_TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040
  87. #define HAL_TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0
  88. #define HAL_TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff
  89. #define HAL_TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044
  90. #define HAL_TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0
  91. #define HAL_TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff
  92. #define HAL_TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044
  93. #define HAL_TX_MSDU_EXTENSION_BUF5_LEN_LSB 16
  94. #define HAL_TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000
  95. /* TX completion ring MACROS */
  96. #define HAL_TX_COMP_TX_RATE_STATS_OFFSET 0x00000014
  97. #define HAL_TX_COMP_TX_RATE_STATS_LSB 0
  98. #define HAL_TX_COMP_TX_RATE_STATS_MASK 0xffffffff
  99. #define HAL_TX_COMP_SW_PEER_ID_OFFSET 0x1c
  100. #define HAL_TX_COMP_SW_PEER_ID_LSB 0
  101. #define HAL_TX_COMP_SW_PEER_ID_MASK 0x0000ffff
  102. #define HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET 0x8
  103. #define HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB 0x6
  104. #define HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
  105. #define HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET 0x8
  106. #define HAL_TX_COMP_TQM_RELEASE_REASON_LSB 13
  107. #define HAL_TX_COMP_TQM_RELEASE_REASON_MASK 0x0001e000
  108. #define HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET 0x8
  109. #define HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB 0
  110. #define HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007
  111. #endif /* _HAL_TX_HW_DEFINES_H_ */