hal_srng.c 58 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "hal_hw_headers.h"
  20. #include "hal_api.h"
  21. #include "hal_reo.h"
  22. #include "target_type.h"
  23. #include "qdf_module.h"
  24. #include "wcss_version.h"
  25. #include <qdf_tracepoint.h>
  26. #include "qdf_ssr_driver_dump.h"
  27. struct tcl_data_cmd gtcl_data_symbol __attribute__((used));
  28. #ifdef QCA_WIFI_QCA8074
  29. void hal_qca6290_attach(struct hal_soc *hal);
  30. #endif
  31. #ifdef QCA_WIFI_QCA8074
  32. void hal_qca8074_attach(struct hal_soc *hal);
  33. #endif
  34. #if defined(QCA_WIFI_QCA8074V2) || defined(QCA_WIFI_QCA6018) || \
  35. defined(QCA_WIFI_QCA9574)
  36. void hal_qca8074v2_attach(struct hal_soc *hal);
  37. #endif
  38. #ifdef QCA_WIFI_QCA6390
  39. void hal_qca6390_attach(struct hal_soc *hal);
  40. #endif
  41. #ifdef QCA_WIFI_QCA6490
  42. void hal_qca6490_attach(struct hal_soc *hal);
  43. #endif
  44. #ifdef QCA_WIFI_QCN9000
  45. void hal_qcn9000_attach(struct hal_soc *hal);
  46. #endif
  47. #ifdef QCA_WIFI_QCN9224
  48. void hal_qcn9224v2_attach(struct hal_soc *hal);
  49. #endif
  50. #if defined(QCA_WIFI_QCN6122) || defined(QCA_WIFI_QCN9160)
  51. void hal_qcn6122_attach(struct hal_soc *hal);
  52. #endif
  53. #ifdef QCA_WIFI_QCN6432
  54. void hal_qcn6432_attach(struct hal_soc *hal);
  55. #endif
  56. #ifdef QCA_WIFI_QCA6750
  57. void hal_qca6750_attach(struct hal_soc *hal);
  58. #endif
  59. #ifdef QCA_WIFI_QCA5018
  60. void hal_qca5018_attach(struct hal_soc *hal);
  61. #endif
  62. #ifdef QCA_WIFI_QCA5332
  63. void hal_qca5332_attach(struct hal_soc *hal);
  64. #endif
  65. #ifdef QCA_WIFI_KIWI
  66. void hal_kiwi_attach(struct hal_soc *hal);
  67. #endif
  68. #ifdef ENABLE_VERBOSE_DEBUG
  69. bool is_hal_verbose_debug_enabled;
  70. #endif
  71. #define HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x4)
  72. #define HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x8)
  73. #define HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc)
  74. #define HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10)
  75. #ifdef ENABLE_HAL_REG_WR_HISTORY
  76. struct hal_reg_write_fail_history hal_reg_wr_hist;
  77. void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc,
  78. uint32_t offset,
  79. uint32_t wr_val, uint32_t rd_val)
  80. {
  81. struct hal_reg_write_fail_entry *record;
  82. int idx;
  83. idx = hal_history_get_next_index(&hal_soc->reg_wr_fail_hist->index,
  84. HAL_REG_WRITE_HIST_SIZE);
  85. record = &hal_soc->reg_wr_fail_hist->record[idx];
  86. record->timestamp = qdf_get_log_timestamp();
  87. record->reg_offset = offset;
  88. record->write_val = wr_val;
  89. record->read_val = rd_val;
  90. }
  91. static void hal_reg_write_fail_history_init(struct hal_soc *hal)
  92. {
  93. hal->reg_wr_fail_hist = &hal_reg_wr_hist;
  94. qdf_atomic_set(&hal->reg_wr_fail_hist->index, -1);
  95. }
  96. #else
  97. static void hal_reg_write_fail_history_init(struct hal_soc *hal)
  98. {
  99. }
  100. #endif
  101. /**
  102. * hal_get_srng_ring_id() - get the ring id of a described ring
  103. * @hal: hal_soc data structure
  104. * @ring_type: type enum describing the ring
  105. * @ring_num: which ring of the ring type
  106. * @mac_id: which mac does the ring belong to (or 0 for non-lmac rings)
  107. *
  108. * Return: the ring id or -EINVAL if the ring does not exist.
  109. */
  110. static int hal_get_srng_ring_id(struct hal_soc *hal, int ring_type,
  111. int ring_num, int mac_id)
  112. {
  113. struct hal_hw_srng_config *ring_config =
  114. HAL_SRNG_CONFIG(hal, ring_type);
  115. int ring_id;
  116. if (ring_num >= ring_config->max_rings) {
  117. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO,
  118. "%s: ring_num exceeded maximum no. of supported rings",
  119. __func__);
  120. /* TODO: This is a programming error. Assert if this happens */
  121. return -EINVAL;
  122. }
  123. /*
  124. * Some DMAC rings share a common source ring, hence don't provide them
  125. * with separate ring IDs per LMAC.
  126. */
  127. if (ring_config->lmac_ring && !ring_config->dmac_cmn_ring) {
  128. ring_id = (ring_config->start_ring_id + ring_num +
  129. (mac_id * HAL_MAX_RINGS_PER_LMAC));
  130. } else {
  131. ring_id = ring_config->start_ring_id + ring_num;
  132. }
  133. return ring_id;
  134. }
  135. static struct hal_srng *hal_get_srng(struct hal_soc *hal, int ring_id)
  136. {
  137. /* TODO: Should we allocate srng structures dynamically? */
  138. return &(hal->srng_list[ring_id]);
  139. }
  140. #ifndef SHADOW_REG_CONFIG_DISABLED
  141. #define HP_OFFSET_IN_REG_START 1
  142. #define OFFSET_FROM_HP_TO_TP 4
  143. static void hal_update_srng_hp_tp_address(struct hal_soc *hal_soc,
  144. int shadow_config_index,
  145. int ring_type,
  146. int ring_num)
  147. {
  148. struct hal_srng *srng;
  149. int ring_id;
  150. struct hal_hw_srng_config *ring_config =
  151. HAL_SRNG_CONFIG(hal_soc, ring_type);
  152. ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, 0);
  153. if (ring_id < 0)
  154. return;
  155. srng = hal_get_srng(hal_soc, ring_id);
  156. if (ring_config->ring_dir == HAL_SRNG_DST_RING) {
  157. srng->u.dst_ring.tp_addr = SHADOW_REGISTER(shadow_config_index)
  158. + hal_soc->dev_base_addr;
  159. hal_debug("tp_addr=%pK dev base addr %pK index %u",
  160. srng->u.dst_ring.tp_addr, hal_soc->dev_base_addr,
  161. shadow_config_index);
  162. } else {
  163. srng->u.src_ring.hp_addr = SHADOW_REGISTER(shadow_config_index)
  164. + hal_soc->dev_base_addr;
  165. hal_debug("hp_addr=%pK dev base addr %pK index %u",
  166. srng->u.src_ring.hp_addr,
  167. hal_soc->dev_base_addr, shadow_config_index);
  168. }
  169. }
  170. #endif
  171. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  172. void hal_set_one_target_reg_config(struct hal_soc *hal,
  173. uint32_t target_reg_offset,
  174. int list_index)
  175. {
  176. int i = list_index;
  177. qdf_assert_always(i < MAX_GENERIC_SHADOW_REG);
  178. hal->list_shadow_reg_config[i].target_register =
  179. target_reg_offset;
  180. hal->num_generic_shadow_regs_configured++;
  181. }
  182. qdf_export_symbol(hal_set_one_target_reg_config);
  183. #define REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET 0x4
  184. #define MAX_REO_REMAP_SHADOW_REGS 4
  185. QDF_STATUS hal_set_shadow_regs(void *hal_soc)
  186. {
  187. uint32_t target_reg_offset;
  188. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  189. int i;
  190. struct hal_hw_srng_config *srng_config =
  191. &hal->hw_srng_table[WBM2SW_RELEASE];
  192. uint32_t reo_reg_base;
  193. reo_reg_base = hal_get_reo_reg_base_offset(hal_soc);
  194. target_reg_offset =
  195. HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(reo_reg_base);
  196. for (i = 0; i < MAX_REO_REMAP_SHADOW_REGS; i++) {
  197. hal_set_one_target_reg_config(hal, target_reg_offset, i);
  198. target_reg_offset += REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET;
  199. }
  200. target_reg_offset = srng_config->reg_start[HP_OFFSET_IN_REG_START];
  201. target_reg_offset += (srng_config->reg_size[HP_OFFSET_IN_REG_START]
  202. * HAL_IPA_TX_COMP_RING_IDX);
  203. hal_set_one_target_reg_config(hal, target_reg_offset, i);
  204. return QDF_STATUS_SUCCESS;
  205. }
  206. qdf_export_symbol(hal_set_shadow_regs);
  207. QDF_STATUS hal_construct_shadow_regs(void *hal_soc)
  208. {
  209. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  210. int shadow_config_index = hal->num_shadow_registers_configured;
  211. int i;
  212. int num_regs = hal->num_generic_shadow_regs_configured;
  213. for (i = 0; i < num_regs; i++) {
  214. qdf_assert_always(shadow_config_index < MAX_SHADOW_REGISTERS);
  215. hal->shadow_config[shadow_config_index].addr =
  216. hal->list_shadow_reg_config[i].target_register;
  217. hal->list_shadow_reg_config[i].shadow_config_index =
  218. shadow_config_index;
  219. hal->list_shadow_reg_config[i].va =
  220. SHADOW_REGISTER(shadow_config_index) +
  221. (uintptr_t)hal->dev_base_addr;
  222. hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x",
  223. hal->shadow_config[shadow_config_index].addr,
  224. SHADOW_REGISTER(shadow_config_index),
  225. shadow_config_index);
  226. shadow_config_index++;
  227. hal->num_shadow_registers_configured++;
  228. }
  229. return QDF_STATUS_SUCCESS;
  230. }
  231. qdf_export_symbol(hal_construct_shadow_regs);
  232. #endif
  233. #ifndef SHADOW_REG_CONFIG_DISABLED
  234. QDF_STATUS hal_set_one_shadow_config(void *hal_soc,
  235. int ring_type,
  236. int ring_num)
  237. {
  238. uint32_t target_register;
  239. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  240. struct hal_hw_srng_config *srng_config = &hal->hw_srng_table[ring_type];
  241. int shadow_config_index = hal->num_shadow_registers_configured;
  242. if (shadow_config_index >= MAX_SHADOW_REGISTERS) {
  243. QDF_ASSERT(0);
  244. return QDF_STATUS_E_RESOURCES;
  245. }
  246. hal->num_shadow_registers_configured++;
  247. target_register = srng_config->reg_start[HP_OFFSET_IN_REG_START];
  248. target_register += (srng_config->reg_size[HP_OFFSET_IN_REG_START]
  249. *ring_num);
  250. /* if the ring is a dst ring, we need to shadow the tail pointer */
  251. if (srng_config->ring_dir == HAL_SRNG_DST_RING)
  252. target_register += OFFSET_FROM_HP_TO_TP;
  253. hal->shadow_config[shadow_config_index].addr = target_register;
  254. /* update hp/tp addr in the hal_soc structure*/
  255. hal_update_srng_hp_tp_address(hal_soc, shadow_config_index, ring_type,
  256. ring_num);
  257. hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x, ring_type %d, ring num %d",
  258. target_register,
  259. SHADOW_REGISTER(shadow_config_index),
  260. shadow_config_index,
  261. ring_type, ring_num);
  262. return QDF_STATUS_SUCCESS;
  263. }
  264. qdf_export_symbol(hal_set_one_shadow_config);
  265. QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc)
  266. {
  267. int ring_type, ring_num;
  268. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  269. for (ring_type = 0; ring_type < MAX_RING_TYPES; ring_type++) {
  270. struct hal_hw_srng_config *srng_config =
  271. &hal->hw_srng_table[ring_type];
  272. if (ring_type == CE_SRC ||
  273. ring_type == CE_DST ||
  274. ring_type == CE_DST_STATUS)
  275. continue;
  276. if (srng_config->lmac_ring)
  277. continue;
  278. for (ring_num = 0; ring_num < srng_config->max_rings;
  279. ring_num++)
  280. hal_set_one_shadow_config(hal_soc, ring_type, ring_num);
  281. }
  282. return QDF_STATUS_SUCCESS;
  283. }
  284. qdf_export_symbol(hal_construct_srng_shadow_regs);
  285. #else
  286. QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc)
  287. {
  288. return QDF_STATUS_SUCCESS;
  289. }
  290. qdf_export_symbol(hal_construct_srng_shadow_regs);
  291. QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type,
  292. int ring_num)
  293. {
  294. return QDF_STATUS_SUCCESS;
  295. }
  296. qdf_export_symbol(hal_set_one_shadow_config);
  297. #endif
  298. void hal_get_shadow_config(void *hal_soc,
  299. struct pld_shadow_reg_v2_cfg **shadow_config,
  300. int *num_shadow_registers_configured)
  301. {
  302. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  303. *shadow_config = &hal->shadow_config[0].v2;
  304. *num_shadow_registers_configured =
  305. hal->num_shadow_registers_configured;
  306. }
  307. qdf_export_symbol(hal_get_shadow_config);
  308. #ifdef CONFIG_SHADOW_V3
  309. void hal_get_shadow_v3_config(void *hal_soc,
  310. struct pld_shadow_reg_v3_cfg **shadow_config,
  311. int *num_shadow_registers_configured)
  312. {
  313. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  314. *shadow_config = &hal->shadow_config[0].v3;
  315. *num_shadow_registers_configured =
  316. hal->num_shadow_registers_configured;
  317. }
  318. qdf_export_symbol(hal_get_shadow_v3_config);
  319. #endif
  320. static bool hal_validate_shadow_register(struct hal_soc *hal,
  321. uint32_t *destination,
  322. uint32_t *shadow_address)
  323. {
  324. unsigned int index;
  325. uint32_t *shadow_0_offset = SHADOW_REGISTER(0) + hal->dev_base_addr;
  326. int destination_ba_offset =
  327. ((char *)destination) - (char *)hal->dev_base_addr;
  328. index = shadow_address - shadow_0_offset;
  329. if (index >= MAX_SHADOW_REGISTERS) {
  330. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  331. "%s: index %x out of bounds", __func__, index);
  332. goto error;
  333. } else if (hal->shadow_config[index].addr != destination_ba_offset) {
  334. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  335. "%s: sanity check failure, expected %x, found %x",
  336. __func__, destination_ba_offset,
  337. hal->shadow_config[index].addr);
  338. goto error;
  339. }
  340. return true;
  341. error:
  342. qdf_print("baddr %pK, destination %pK, shadow_address %pK s0offset %pK index %x",
  343. hal->dev_base_addr, destination, shadow_address,
  344. shadow_0_offset, index);
  345. QDF_BUG(0);
  346. return false;
  347. }
  348. static void hal_target_based_configure(struct hal_soc *hal)
  349. {
  350. /*
  351. * Indicate Initialization of srngs to avoid force wake
  352. * as umac power collapse is not enabled yet
  353. */
  354. hal->init_phase = true;
  355. switch (hal->target_type) {
  356. #ifdef QCA_WIFI_QCA6290
  357. case TARGET_TYPE_QCA6290:
  358. hal->use_register_windowing = true;
  359. hal_qca6290_attach(hal);
  360. break;
  361. #endif
  362. #ifdef QCA_WIFI_QCA6390
  363. case TARGET_TYPE_QCA6390:
  364. hal->use_register_windowing = true;
  365. hal_qca6390_attach(hal);
  366. break;
  367. #endif
  368. #ifdef QCA_WIFI_QCA6490
  369. case TARGET_TYPE_QCA6490:
  370. hal->use_register_windowing = true;
  371. hal_qca6490_attach(hal);
  372. break;
  373. #endif
  374. #ifdef QCA_WIFI_QCA6750
  375. case TARGET_TYPE_QCA6750:
  376. hal->use_register_windowing = true;
  377. hal->static_window_map = true;
  378. hal_qca6750_attach(hal);
  379. break;
  380. #endif
  381. #ifdef QCA_WIFI_KIWI
  382. case TARGET_TYPE_KIWI:
  383. case TARGET_TYPE_MANGO:
  384. case TARGET_TYPE_PEACH:
  385. hal->use_register_windowing = true;
  386. hal_kiwi_attach(hal);
  387. break;
  388. #endif
  389. #if defined(QCA_WIFI_QCA8074) && defined(WIFI_TARGET_TYPE_3_0)
  390. case TARGET_TYPE_QCA8074:
  391. hal_qca8074_attach(hal);
  392. break;
  393. #endif
  394. #if defined(QCA_WIFI_QCA8074V2)
  395. case TARGET_TYPE_QCA8074V2:
  396. hal_qca8074v2_attach(hal);
  397. break;
  398. #endif
  399. #if defined(QCA_WIFI_QCA6018)
  400. case TARGET_TYPE_QCA6018:
  401. hal_qca8074v2_attach(hal);
  402. break;
  403. #endif
  404. #if defined(QCA_WIFI_QCA9574)
  405. case TARGET_TYPE_QCA9574:
  406. hal_qca8074v2_attach(hal);
  407. break;
  408. #endif
  409. #if defined(QCA_WIFI_QCN6122)
  410. case TARGET_TYPE_QCN6122:
  411. hal->use_register_windowing = true;
  412. /*
  413. * Static window map is enabled for qcn9000 to use 2mb bar
  414. * size and use multiple windows to write into registers.
  415. */
  416. hal->static_window_map = true;
  417. hal_qcn6122_attach(hal);
  418. break;
  419. #endif
  420. #if defined(QCA_WIFI_QCN9160)
  421. case TARGET_TYPE_QCN9160:
  422. hal->use_register_windowing = true;
  423. /*
  424. * Static window map is enabled for qcn9160 to use 2mb bar
  425. * size and use multiple windows to write into registers.
  426. */
  427. hal->static_window_map = true;
  428. hal_qcn6122_attach(hal);
  429. break;
  430. #endif
  431. #if defined(QCA_WIFI_QCN6432)
  432. case TARGET_TYPE_QCN6432:
  433. hal->use_register_windowing = true;
  434. /*
  435. * Static window map is enabled for qcn6432 to use 2mb bar
  436. * size and use multiple windows to write into registers.
  437. */
  438. hal->static_window_map = true;
  439. hal_qcn6432_attach(hal);
  440. break;
  441. #endif
  442. #ifdef QCA_WIFI_QCN9000
  443. case TARGET_TYPE_QCN9000:
  444. hal->use_register_windowing = true;
  445. /*
  446. * Static window map is enabled for qcn9000 to use 2mb bar
  447. * size and use multiple windows to write into registers.
  448. */
  449. hal->static_window_map = true;
  450. hal_qcn9000_attach(hal);
  451. break;
  452. #endif
  453. #ifdef QCA_WIFI_QCA5018
  454. case TARGET_TYPE_QCA5018:
  455. hal->use_register_windowing = true;
  456. hal->static_window_map = true;
  457. hal_qca5018_attach(hal);
  458. break;
  459. #endif
  460. #ifdef QCA_WIFI_QCN9224
  461. case TARGET_TYPE_QCN9224:
  462. hal->use_register_windowing = true;
  463. hal->static_window_map = true;
  464. if (hal->version == 1)
  465. qdf_assert_always(0);
  466. else
  467. hal_qcn9224v2_attach(hal);
  468. break;
  469. #endif
  470. #ifdef QCA_WIFI_QCA5332
  471. case TARGET_TYPE_QCA5332:
  472. hal->use_register_windowing = true;
  473. hal->static_window_map = true;
  474. hal_qca5332_attach(hal);
  475. break;
  476. #endif
  477. #ifdef QCA_WIFI_WCN6450
  478. case TARGET_TYPE_WCN6450:
  479. hal->use_register_windowing = true;
  480. hal->static_window_map = true;
  481. hal_wcn6450_attach(hal);
  482. break;
  483. #endif
  484. default:
  485. break;
  486. }
  487. }
  488. uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl)
  489. {
  490. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  491. struct hif_target_info *tgt_info =
  492. hif_get_target_info_handle(hal_soc->hif_handle);
  493. return tgt_info->target_type;
  494. }
  495. qdf_export_symbol(hal_get_target_type);
  496. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  497. /**
  498. * hal_is_reg_write_tput_level_high() - throughput level for delayed reg writes
  499. * @hal: hal_soc pointer
  500. *
  501. * Return: true if throughput is high, else false.
  502. */
  503. static inline bool hal_is_reg_write_tput_level_high(struct hal_soc *hal)
  504. {
  505. int bw_level = hif_get_bandwidth_level(hal->hif_handle);
  506. return (bw_level >= PLD_BUS_WIDTH_MEDIUM) ? true : false;
  507. }
  508. static inline
  509. char *hal_fill_reg_write_srng_stats(struct hal_srng *srng,
  510. char *buf, qdf_size_t size)
  511. {
  512. qdf_scnprintf(buf, size, "enq %u deq %u coal %u direct %u",
  513. srng->wstats.enqueues, srng->wstats.dequeues,
  514. srng->wstats.coalesces, srng->wstats.direct);
  515. return buf;
  516. }
  517. /* bytes for local buffer */
  518. #define HAL_REG_WRITE_SRNG_STATS_LEN 100
  519. #ifndef WLAN_SOFTUMAC_SUPPORT
  520. void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
  521. {
  522. struct hal_srng *srng;
  523. char buf[HAL_REG_WRITE_SRNG_STATS_LEN];
  524. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  525. srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1);
  526. hal_debug("SW2TCL1: %s",
  527. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  528. srng = hal_get_srng(hal, HAL_SRNG_WBM2SW0_RELEASE);
  529. hal_debug("WBM2SW0: %s",
  530. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  531. srng = hal_get_srng(hal, HAL_SRNG_REO2SW1);
  532. hal_debug("REO2SW1: %s",
  533. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  534. srng = hal_get_srng(hal, HAL_SRNG_REO2SW2);
  535. hal_debug("REO2SW2: %s",
  536. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  537. srng = hal_get_srng(hal, HAL_SRNG_REO2SW3);
  538. hal_debug("REO2SW3: %s",
  539. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  540. }
  541. void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
  542. {
  543. uint32_t *hist;
  544. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  545. hist = hal->stats.wstats.sched_delay;
  546. hal_debug("wstats: enq %u deq %u coal %u direct %u q_depth %u max_q %u sched-delay hist %u %u %u %u",
  547. qdf_atomic_read(&hal->stats.wstats.enqueues),
  548. hal->stats.wstats.dequeues,
  549. qdf_atomic_read(&hal->stats.wstats.coalesces),
  550. qdf_atomic_read(&hal->stats.wstats.direct),
  551. qdf_atomic_read(&hal->stats.wstats.q_depth),
  552. hal->stats.wstats.max_q_depth,
  553. hist[REG_WRITE_SCHED_DELAY_SUB_100us],
  554. hist[REG_WRITE_SCHED_DELAY_SUB_1000us],
  555. hist[REG_WRITE_SCHED_DELAY_SUB_5000us],
  556. hist[REG_WRITE_SCHED_DELAY_GT_5000us]);
  557. }
  558. #else
  559. void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
  560. {
  561. }
  562. /* TODO: Need separate logic for Evros */
  563. void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
  564. {
  565. }
  566. #endif
  567. int hal_get_reg_write_pending_work(void *hal_soc)
  568. {
  569. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  570. return qdf_atomic_read(&hal->active_work_cnt);
  571. }
  572. #endif
  573. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  574. #ifdef MEMORY_DEBUG
  575. /*
  576. * Length of the queue(array) used to hold delayed register writes.
  577. * Must be a multiple of 2.
  578. */
  579. #define HAL_REG_WRITE_QUEUE_LEN 128
  580. #else
  581. #define HAL_REG_WRITE_QUEUE_LEN 32
  582. #endif
  583. #ifdef QCA_WIFI_QCA6750
  584. #define HAL_DEL_WRITE_FORCE_UPDATE_THRES 5
  585. static inline void hal_srng_update_last_hptp(struct hal_srng *srng)
  586. {
  587. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  588. srng->updated_hp = srng->u.src_ring.hp;
  589. else
  590. srng->updated_tp = srng->u.dst_ring.tp;
  591. srng->force_cnt = 0;
  592. }
  593. /* If HP/TP register updates are delayed due to delayed reg
  594. * write work not getting scheduled, hardware would see HP/TP
  595. * delta and will fire interrupts until the HP/TP updates reach
  596. * the hardware.
  597. *
  598. * When system is heavily stressed, this delay in HP/TP updates
  599. * would result in IRQ storm further stressing the system. Force
  600. * update HP/TP to the hardware under such scenarios to avoid this.
  601. */
  602. void hal_srng_check_and_update_hptp(struct hal_soc *hal_soc,
  603. struct hal_srng *srng, bool update)
  604. {
  605. uint32_t value;
  606. if (!update)
  607. return;
  608. SRNG_LOCK(&srng->lock);
  609. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  610. value = srng->u.src_ring.hp;
  611. if (value == srng->updated_hp ||
  612. srng->force_cnt++ < HAL_DEL_WRITE_FORCE_UPDATE_THRES)
  613. goto out_unlock;
  614. hal_write_address_32_mb(hal_soc, srng->u.src_ring.hp_addr,
  615. value, false);
  616. } else {
  617. value = srng->u.dst_ring.tp;
  618. if (value == srng->updated_tp ||
  619. srng->force_cnt++ < HAL_DEL_WRITE_FORCE_UPDATE_THRES)
  620. goto out_unlock;
  621. hal_write_address_32_mb(hal_soc, srng->u.dst_ring.tp_addr,
  622. value, false);
  623. }
  624. hal_srng_update_last_hptp(srng);
  625. hal_srng_reg_his_add(srng, value);
  626. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  627. srng->wstats.direct++;
  628. out_unlock:
  629. SRNG_UNLOCK(&srng->lock);
  630. }
  631. #else
  632. static inline void hal_srng_update_last_hptp(struct hal_srng *srng)
  633. {
  634. }
  635. #endif /* QCA_WIFI_QCA6750 */
  636. /**
  637. * hal_process_reg_write_q_elem() - process a register write queue element
  638. * @hal: hal_soc pointer
  639. * @q_elem: pointer to hal register write queue element
  640. *
  641. * Return: The value which was written to the address
  642. */
  643. static uint32_t
  644. hal_process_reg_write_q_elem(struct hal_soc *hal,
  645. struct hal_reg_write_q_elem *q_elem)
  646. {
  647. struct hal_srng *srng = q_elem->srng;
  648. uint32_t write_val;
  649. SRNG_LOCK(&srng->lock);
  650. srng->reg_write_in_progress = false;
  651. srng->wstats.dequeues++;
  652. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  653. q_elem->dequeue_val = srng->u.src_ring.hp;
  654. hal_write_address_32_mb(hal,
  655. srng->u.src_ring.hp_addr,
  656. srng->u.src_ring.hp, false);
  657. write_val = srng->u.src_ring.hp;
  658. } else {
  659. q_elem->dequeue_val = srng->u.dst_ring.tp;
  660. hal_write_address_32_mb(hal,
  661. srng->u.dst_ring.tp_addr,
  662. srng->u.dst_ring.tp, false);
  663. write_val = srng->u.dst_ring.tp;
  664. }
  665. hal_srng_update_last_hptp(srng);
  666. hal_srng_reg_his_add(srng, write_val);
  667. q_elem->valid = 0;
  668. srng->last_dequeue_time = q_elem->dequeue_time;
  669. SRNG_UNLOCK(&srng->lock);
  670. return write_val;
  671. }
  672. /**
  673. * hal_reg_write_fill_sched_delay_hist() - fill reg write delay histogram in hal
  674. * @hal: hal_soc pointer
  675. * @delay_us: delay in us
  676. *
  677. * Return: None
  678. */
  679. static inline void hal_reg_write_fill_sched_delay_hist(struct hal_soc *hal,
  680. uint64_t delay_us)
  681. {
  682. uint32_t *hist;
  683. hist = hal->stats.wstats.sched_delay;
  684. if (delay_us < 100)
  685. hist[REG_WRITE_SCHED_DELAY_SUB_100us]++;
  686. else if (delay_us < 1000)
  687. hist[REG_WRITE_SCHED_DELAY_SUB_1000us]++;
  688. else if (delay_us < 5000)
  689. hist[REG_WRITE_SCHED_DELAY_SUB_5000us]++;
  690. else
  691. hist[REG_WRITE_SCHED_DELAY_GT_5000us]++;
  692. }
  693. #ifdef SHADOW_WRITE_DELAY
  694. #define SHADOW_WRITE_MIN_DELTA_US 5
  695. #define SHADOW_WRITE_DELAY_US 50
  696. /*
  697. * Never add those srngs which are performance relate.
  698. * The delay itself will hit performance heavily.
  699. */
  700. #define IS_SRNG_MATCH(s) ((s)->ring_id == HAL_SRNG_CE_1_DST_STATUS || \
  701. (s)->ring_id == HAL_SRNG_CE_1_DST)
  702. static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem)
  703. {
  704. struct hal_srng *srng = elem->srng;
  705. struct hal_soc *hal;
  706. qdf_time_t now;
  707. qdf_iomem_t real_addr;
  708. if (qdf_unlikely(!srng))
  709. return false;
  710. hal = srng->hal_soc;
  711. if (qdf_unlikely(!hal))
  712. return false;
  713. /* Check if it is target srng, and valid shadow reg */
  714. if (qdf_likely(!IS_SRNG_MATCH(srng)))
  715. return false;
  716. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  717. real_addr = SRNG_SRC_ADDR(srng, HP);
  718. else
  719. real_addr = SRNG_DST_ADDR(srng, TP);
  720. if (!hal_validate_shadow_register(hal, real_addr, elem->addr))
  721. return false;
  722. /* Check the time delta from last write of same srng */
  723. now = qdf_get_log_timestamp();
  724. if (qdf_log_timestamp_to_usecs(now - srng->last_dequeue_time) >
  725. SHADOW_WRITE_MIN_DELTA_US)
  726. return false;
  727. /* Delay dequeue, and record */
  728. qdf_udelay(SHADOW_WRITE_DELAY_US);
  729. srng->wstats.dequeue_delay++;
  730. hal->stats.wstats.dequeue_delay++;
  731. return true;
  732. }
  733. #else
  734. static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem)
  735. {
  736. return false;
  737. }
  738. #endif
  739. #define MAX_DELAYED_REG_WRITE_RETRY 5
  740. /**
  741. * hal_reg_write_work() - Worker to process delayed writes
  742. * @arg: hal_soc pointer
  743. *
  744. * Return: None
  745. */
  746. static void hal_reg_write_work(void *arg)
  747. {
  748. int32_t q_depth, write_val;
  749. struct hal_soc *hal = arg;
  750. struct hal_reg_write_q_elem *q_elem;
  751. uint64_t delta_us;
  752. uint8_t ring_id;
  753. uint32_t *addr;
  754. uint32_t num_processed = 0;
  755. uint8_t retry_count = 0;
  756. q_elem = &hal->reg_write_queue[(hal->read_idx)];
  757. q_elem->work_scheduled_time = qdf_get_log_timestamp();
  758. q_elem->cpu_id = qdf_get_cpu();
  759. /* Make sure q_elem consistent in the memory for multi-cores */
  760. qdf_rmb();
  761. if (!q_elem->valid)
  762. return;
  763. q_depth = qdf_atomic_read(&hal->stats.wstats.q_depth);
  764. if (q_depth > hal->stats.wstats.max_q_depth)
  765. hal->stats.wstats.max_q_depth = q_depth;
  766. if (hif_prevent_link_low_power_states(hal->hif_handle)) {
  767. hal->stats.wstats.prevent_l1_fails++;
  768. return;
  769. }
  770. while (true) {
  771. qdf_rmb();
  772. if (!q_elem->valid)
  773. break;
  774. qdf_rmb();
  775. /* buy some more time to make sure all fields
  776. * in q_elem is updated per different CPUs, in
  777. * case wmb/rmb is not taken effect
  778. */
  779. if (qdf_unlikely(!q_elem->srng ||
  780. (qdf_atomic_read(&q_elem->ring_id) !=
  781. q_elem->srng->ring_id))) {
  782. hal_err_rl("q_elem fields not up to date 0x%x 0x%x",
  783. q_elem->srng ? q_elem->srng->ring_id : 0xDEAD,
  784. qdf_atomic_read(&q_elem->ring_id));
  785. if (retry_count++ < MAX_DELAYED_REG_WRITE_RETRY) {
  786. /* Sleep for 1ms before retry */
  787. qdf_sleep(1);
  788. continue;
  789. }
  790. qdf_assert_always(0);
  791. }
  792. q_elem->dequeue_time = qdf_get_log_timestamp();
  793. ring_id = q_elem->srng->ring_id;
  794. addr = q_elem->addr;
  795. delta_us = qdf_log_timestamp_to_usecs(q_elem->dequeue_time -
  796. q_elem->enqueue_time);
  797. hal_reg_write_fill_sched_delay_hist(hal, delta_us);
  798. hal->stats.wstats.dequeues++;
  799. qdf_atomic_dec(&hal->stats.wstats.q_depth);
  800. if (hal_reg_write_need_delay(q_elem))
  801. hal_verbose_debug("Delay reg writer for srng 0x%x, addr 0x%pK",
  802. q_elem->srng->ring_id, q_elem->addr);
  803. write_val = hal_process_reg_write_q_elem(hal, q_elem);
  804. hal_verbose_debug("read_idx %u srng 0x%x, addr 0x%pK dequeue_val %u sched delay %llu us",
  805. hal->read_idx, ring_id, addr, write_val, delta_us);
  806. qdf_trace_dp_del_reg_write(ring_id, q_elem->enqueue_val,
  807. q_elem->dequeue_val,
  808. q_elem->enqueue_time,
  809. q_elem->dequeue_time);
  810. num_processed++;
  811. hal->read_idx = (hal->read_idx + 1) &
  812. (HAL_REG_WRITE_QUEUE_LEN - 1);
  813. q_elem = &hal->reg_write_queue[(hal->read_idx)];
  814. retry_count = 0;
  815. }
  816. hif_allow_link_low_power_states(hal->hif_handle);
  817. /*
  818. * Decrement active_work_cnt by the number of elements dequeued after
  819. * hif_allow_link_low_power_states.
  820. * This makes sure that hif_try_complete_tasks will wait till we make
  821. * the bus access in hif_allow_link_low_power_states. This will avoid
  822. * race condition between delayed register worker and bus suspend
  823. * (system suspend or runtime suspend).
  824. *
  825. * The following decrement should be done at the end!
  826. */
  827. qdf_atomic_sub(num_processed, &hal->active_work_cnt);
  828. }
  829. static void __hal_flush_reg_write_work(struct hal_soc *hal)
  830. {
  831. qdf_flush_work(&hal->reg_write_work);
  832. qdf_disable_work(&hal->reg_write_work);
  833. }
  834. void hal_flush_reg_write_work(hal_soc_handle_t hal_handle)
  835. { __hal_flush_reg_write_work((struct hal_soc *)hal_handle);
  836. }
  837. /**
  838. * hal_reg_write_enqueue() - enqueue register writes into kworker
  839. * @hal_soc: hal_soc pointer
  840. * @srng: srng pointer
  841. * @addr: iomem address of register
  842. * @value: value to be written to iomem address
  843. *
  844. * This function executes from within the SRNG LOCK
  845. *
  846. * Return: None
  847. */
  848. static void hal_reg_write_enqueue(struct hal_soc *hal_soc,
  849. struct hal_srng *srng,
  850. void __iomem *addr,
  851. uint32_t value)
  852. {
  853. struct hal_reg_write_q_elem *q_elem;
  854. uint32_t write_idx;
  855. if (srng->reg_write_in_progress) {
  856. hal_verbose_debug("Already in progress srng ring id 0x%x addr 0x%pK val %u",
  857. srng->ring_id, addr, value);
  858. qdf_atomic_inc(&hal_soc->stats.wstats.coalesces);
  859. srng->wstats.coalesces++;
  860. return;
  861. }
  862. write_idx = qdf_atomic_inc_return(&hal_soc->write_idx);
  863. write_idx = write_idx & (HAL_REG_WRITE_QUEUE_LEN - 1);
  864. q_elem = &hal_soc->reg_write_queue[write_idx];
  865. if (q_elem->valid) {
  866. hal_err("queue full");
  867. QDF_BUG(0);
  868. return;
  869. }
  870. qdf_atomic_inc(&hal_soc->stats.wstats.enqueues);
  871. srng->wstats.enqueues++;
  872. qdf_atomic_inc(&hal_soc->stats.wstats.q_depth);
  873. q_elem->srng = srng;
  874. q_elem->addr = addr;
  875. qdf_atomic_set(&q_elem->ring_id, srng->ring_id);
  876. q_elem->enqueue_val = value;
  877. q_elem->enqueue_time = qdf_get_log_timestamp();
  878. /*
  879. * Before the valid flag is set to true, all the other
  880. * fields in the q_elem needs to be updated in memory.
  881. * Else there is a chance that the dequeuing worker thread
  882. * might read stale entries and process incorrect srng.
  883. */
  884. qdf_wmb();
  885. q_elem->valid = true;
  886. /*
  887. * After all other fields in the q_elem has been updated
  888. * in memory successfully, the valid flag needs to be updated
  889. * in memory in time too.
  890. * Else there is a chance that the dequeuing worker thread
  891. * might read stale valid flag and the work will be bypassed
  892. * for this round. And if there is no other work scheduled
  893. * later, this hal register writing won't be updated any more.
  894. */
  895. qdf_wmb();
  896. srng->reg_write_in_progress = true;
  897. qdf_atomic_inc(&hal_soc->active_work_cnt);
  898. hal_verbose_debug("write_idx %u srng ring id 0x%x addr 0x%pK val %u",
  899. write_idx, srng->ring_id, addr, value);
  900. qdf_queue_work(hal_soc->qdf_dev, hal_soc->reg_write_wq,
  901. &hal_soc->reg_write_work);
  902. }
  903. /**
  904. * hal_delayed_reg_write_init() - Initialization function for delayed reg writes
  905. * @hal: hal_soc pointer
  906. *
  907. * Initialize main data structures to process register writes in a delayed
  908. * workqueue.
  909. *
  910. * Return: QDF_STATUS_SUCCESS on success else a QDF error.
  911. */
  912. static QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal)
  913. {
  914. hal->reg_write_wq =
  915. qdf_alloc_high_prior_ordered_workqueue("hal_register_write_wq");
  916. qdf_create_work(0, &hal->reg_write_work, hal_reg_write_work, hal);
  917. hal->reg_write_queue = qdf_mem_malloc(HAL_REG_WRITE_QUEUE_LEN *
  918. sizeof(*hal->reg_write_queue));
  919. if (!hal->reg_write_queue) {
  920. hal_err("unable to allocate memory");
  921. QDF_BUG(0);
  922. return QDF_STATUS_E_NOMEM;
  923. }
  924. /* Initial value of indices */
  925. hal->read_idx = 0;
  926. qdf_atomic_set(&hal->write_idx, -1);
  927. return QDF_STATUS_SUCCESS;
  928. }
  929. /**
  930. * hal_delayed_reg_write_deinit() - De-Initialize delayed reg write processing
  931. * @hal: hal_soc pointer
  932. *
  933. * De-initialize main data structures to process register writes in a delayed
  934. * workqueue.
  935. *
  936. * Return: None
  937. */
  938. static void hal_delayed_reg_write_deinit(struct hal_soc *hal)
  939. {
  940. __hal_flush_reg_write_work(hal);
  941. qdf_flush_workqueue(0, hal->reg_write_wq);
  942. qdf_destroy_workqueue(0, hal->reg_write_wq);
  943. qdf_mem_free(hal->reg_write_queue);
  944. }
  945. #else
  946. static inline QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal)
  947. {
  948. return QDF_STATUS_SUCCESS;
  949. }
  950. static inline void hal_delayed_reg_write_deinit(struct hal_soc *hal)
  951. {
  952. }
  953. #endif
  954. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  955. #ifdef HAL_RECORD_SUSPEND_WRITE
  956. static struct hal_suspend_write_history
  957. g_hal_suspend_write_history[HAL_SUSPEND_WRITE_HISTORY_MAX];
  958. static
  959. void hal_event_suspend_record(uint8_t ring_id, uint32_t value, uint32_t count)
  960. {
  961. uint32_t index = qdf_atomic_read(g_hal_suspend_write_history.index) &
  962. (HAL_SUSPEND_WRITE_HISTORY_MAX - 1);
  963. struct hal_suspend_write_record *cur_event =
  964. &hal_suspend_write_event.record[index];
  965. cur_event->ts = qdf_get_log_timestamp();
  966. cur_event->ring_id = ring_id;
  967. cur_event->value = value;
  968. cur_event->direct_wcount = count;
  969. qdf_atomic_inc(g_hal_suspend_write_history.index);
  970. }
  971. static inline
  972. void hal_record_suspend_write(uint8_t ring_id, uint32_t value, uint32_t count)
  973. {
  974. if (hif_rtpm_get_state() >= HIF_RTPM_STATE_SUSPENDING)
  975. hal_event_suspend_record(ring_id, value, count);
  976. }
  977. #else
  978. static inline
  979. void hal_record_suspend_write(uint8_t ring_id, uint32_t value, uint32_t count)
  980. {
  981. }
  982. #endif
  983. #ifdef QCA_WIFI_QCA6750
  984. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  985. struct hal_srng *srng,
  986. void __iomem *addr,
  987. uint32_t value)
  988. {
  989. uint8_t vote_access;
  990. switch (srng->ring_type) {
  991. case CE_SRC:
  992. case CE_DST:
  993. case CE_DST_STATUS:
  994. vote_access = hif_get_ep_vote_access(hal_soc->hif_handle,
  995. HIF_EP_VOTE_NONDP_ACCESS);
  996. if ((vote_access == HIF_EP_VOTE_ACCESS_DISABLE) ||
  997. (vote_access == HIF_EP_VOTE_INTERMEDIATE_ACCESS &&
  998. PLD_MHI_STATE_L0 ==
  999. pld_get_mhi_state(hal_soc->qdf_dev->dev))) {
  1000. hal_write_address_32_mb(hal_soc, addr, value, false);
  1001. hal_srng_update_last_hptp(srng);
  1002. hal_srng_reg_his_add(srng, value);
  1003. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  1004. srng->wstats.direct++;
  1005. } else {
  1006. hal_reg_write_enqueue(hal_soc, srng, addr, value);
  1007. }
  1008. break;
  1009. default:
  1010. if (hif_get_ep_vote_access(hal_soc->hif_handle,
  1011. HIF_EP_VOTE_DP_ACCESS) ==
  1012. HIF_EP_VOTE_ACCESS_DISABLE ||
  1013. hal_is_reg_write_tput_level_high(hal_soc) ||
  1014. PLD_MHI_STATE_L0 ==
  1015. pld_get_mhi_state(hal_soc->qdf_dev->dev)) {
  1016. hal_write_address_32_mb(hal_soc, addr, value, false);
  1017. hal_srng_reg_his_add(srng, value);
  1018. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  1019. srng->wstats.direct++;
  1020. } else {
  1021. hal_reg_write_enqueue(hal_soc, srng, addr, value);
  1022. }
  1023. break;
  1024. }
  1025. }
  1026. #else
  1027. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  1028. struct hal_srng *srng,
  1029. void __iomem *addr,
  1030. uint32_t value)
  1031. {
  1032. if (hal_is_reg_write_tput_level_high(hal_soc) ||
  1033. pld_is_device_awake(hal_soc->qdf_dev->dev)) {
  1034. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  1035. srng->wstats.direct++;
  1036. hal_write_address_32_mb(hal_soc, addr, value, false);
  1037. hal_srng_update_last_hptp(srng);
  1038. hal_srng_reg_his_add(srng, value);
  1039. } else {
  1040. hal_reg_write_enqueue(hal_soc, srng, addr, value);
  1041. }
  1042. hal_record_suspend_write(srng->ring_id, value, srng->wstats.direct);
  1043. }
  1044. #endif
  1045. #endif
  1046. #ifdef HAL_SRNG_REG_HIS_DEBUG
  1047. inline void hal_free_srng_history(struct hal_soc *hal)
  1048. {
  1049. int i;
  1050. for (i = 0; i < HAL_SRNG_ID_MAX; i++)
  1051. qdf_mem_free(hal->srng_list[i].reg_his_ctx);
  1052. }
  1053. inline bool hal_alloc_srng_history(struct hal_soc *hal)
  1054. {
  1055. int i;
  1056. for (i = 0; i < HAL_SRNG_ID_MAX; i++) {
  1057. hal->srng_list[i].reg_his_ctx =
  1058. qdf_mem_malloc(sizeof(struct hal_srng_reg_his_ctx));
  1059. if (!hal->srng_list[i].reg_his_ctx) {
  1060. hal_err("srng_hist alloc failed");
  1061. hal_free_srng_history(hal);
  1062. return false;
  1063. }
  1064. }
  1065. return true;
  1066. }
  1067. #else
  1068. inline void hal_free_srng_history(struct hal_soc *hal)
  1069. {
  1070. }
  1071. inline bool hal_alloc_srng_history(struct hal_soc *hal)
  1072. {
  1073. return true;
  1074. }
  1075. #endif
  1076. void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev)
  1077. {
  1078. struct hal_soc *hal;
  1079. int i;
  1080. hal = qdf_mem_common_alloc(sizeof(*hal));
  1081. if (!hal) {
  1082. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1083. "%s: hal_soc allocation failed", __func__);
  1084. goto fail0;
  1085. }
  1086. hal->hif_handle = hif_handle;
  1087. hal->dev_base_addr = hif_get_dev_ba(hif_handle); /* UMAC */
  1088. hal->dev_base_addr_ce = hif_get_dev_ba_ce(hif_handle); /* CE */
  1089. hal->dev_base_addr_cmem = hif_get_dev_ba_cmem(hif_handle); /* CMEM */
  1090. hal->dev_base_addr_pmm = hif_get_dev_ba_pmm(hif_handle); /* PMM */
  1091. hal->qdf_dev = qdf_dev;
  1092. hal->shadow_rdptr_mem_vaddr = (uint32_t *)qdf_mem_alloc_consistent(
  1093. qdf_dev, qdf_dev->dev, sizeof(*(hal->shadow_rdptr_mem_vaddr)) *
  1094. HAL_SRNG_ID_MAX, &(hal->shadow_rdptr_mem_paddr));
  1095. if (!hal->shadow_rdptr_mem_paddr) {
  1096. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1097. "%s: hal->shadow_rdptr_mem_paddr allocation failed",
  1098. __func__);
  1099. goto fail1;
  1100. }
  1101. qdf_mem_zero(hal->shadow_rdptr_mem_vaddr,
  1102. sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX);
  1103. hal->shadow_wrptr_mem_vaddr =
  1104. (uint32_t *)qdf_mem_alloc_consistent(qdf_dev, qdf_dev->dev,
  1105. sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS,
  1106. &(hal->shadow_wrptr_mem_paddr));
  1107. if (!hal->shadow_wrptr_mem_vaddr) {
  1108. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1109. "%s: hal->shadow_wrptr_mem_vaddr allocation failed",
  1110. __func__);
  1111. goto fail2;
  1112. }
  1113. qdf_mem_zero(hal->shadow_wrptr_mem_vaddr,
  1114. sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS);
  1115. if (!hal_alloc_srng_history(hal))
  1116. goto fail2;
  1117. for (i = 0; i < HAL_SRNG_ID_MAX; i++) {
  1118. hal->srng_list[i].initialized = 0;
  1119. hal->srng_list[i].ring_id = i;
  1120. }
  1121. qdf_spinlock_create(&hal->register_access_lock);
  1122. hal->register_window = 0;
  1123. hal->target_type = hal_get_target_type(hal_soc_to_hal_soc_handle(hal));
  1124. hal->version = hif_get_soc_version(hif_handle);
  1125. hal->ops = qdf_mem_malloc(sizeof(*hal->ops));
  1126. if (!hal->ops) {
  1127. hal_err("unable to allocable memory for HAL ops");
  1128. goto fail3;
  1129. }
  1130. hal_target_based_configure(hal);
  1131. hal_reg_write_fail_history_init(hal);
  1132. qdf_minidump_log(hal, sizeof(*hal), "hal_soc");
  1133. qdf_ssr_driver_dump_register_region("hal_soc", hal, sizeof(*hal));
  1134. qdf_atomic_init(&hal->active_work_cnt);
  1135. if (hal_delayed_reg_write_init(hal) != QDF_STATUS_SUCCESS) {
  1136. hal_err("unable to initialize delayed reg write");
  1137. goto fail4;
  1138. }
  1139. hif_rtpm_register(HIF_RTPM_ID_HAL_REO_CMD, NULL);
  1140. return (void *)hal;
  1141. fail4:
  1142. qdf_ssr_driver_dump_unregister_region("hal_soc");
  1143. qdf_minidump_remove(hal, sizeof(*hal), "hal_soc");
  1144. qdf_mem_free(hal->ops);
  1145. fail3:
  1146. qdf_mem_free_consistent(qdf_dev, qdf_dev->dev,
  1147. sizeof(*hal->shadow_wrptr_mem_vaddr) *
  1148. HAL_MAX_LMAC_RINGS,
  1149. hal->shadow_wrptr_mem_vaddr,
  1150. hal->shadow_wrptr_mem_paddr, 0);
  1151. fail2:
  1152. qdf_mem_free_consistent(qdf_dev, qdf_dev->dev,
  1153. sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX,
  1154. hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0);
  1155. fail1:
  1156. qdf_mem_common_free(hal);
  1157. fail0:
  1158. return NULL;
  1159. }
  1160. qdf_export_symbol(hal_attach);
  1161. void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem)
  1162. {
  1163. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  1164. mem->dev_base_addr = (void *)hal->dev_base_addr;
  1165. mem->shadow_rdptr_mem_vaddr = (void *)hal->shadow_rdptr_mem_vaddr;
  1166. mem->shadow_wrptr_mem_vaddr = (void *)hal->shadow_wrptr_mem_vaddr;
  1167. mem->shadow_rdptr_mem_paddr = (void *)hal->shadow_rdptr_mem_paddr;
  1168. mem->shadow_wrptr_mem_paddr = (void *)hal->shadow_wrptr_mem_paddr;
  1169. hif_read_phy_mem_base((void *)hal->hif_handle,
  1170. (qdf_dma_addr_t *)&mem->dev_base_paddr);
  1171. mem->lmac_srng_start_id = HAL_SRNG_LMAC1_ID_START;
  1172. return;
  1173. }
  1174. qdf_export_symbol(hal_get_meminfo);
  1175. void hal_detach(void *hal_soc)
  1176. {
  1177. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1178. hif_rtpm_deregister(HIF_RTPM_ID_HAL_REO_CMD);
  1179. hal_delayed_reg_write_deinit(hal);
  1180. hal_reo_shared_qaddr_detach((hal_soc_handle_t)hal);
  1181. qdf_ssr_driver_dump_unregister_region("hal_soc");
  1182. qdf_minidump_remove(hal, sizeof(*hal), "hal_soc");
  1183. qdf_mem_free(hal->ops);
  1184. hal_free_srng_history(hal);
  1185. qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
  1186. sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX,
  1187. hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0);
  1188. qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
  1189. sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS,
  1190. hal->shadow_wrptr_mem_vaddr, hal->shadow_wrptr_mem_paddr, 0);
  1191. qdf_mem_common_free(hal);
  1192. return;
  1193. }
  1194. qdf_export_symbol(hal_detach);
  1195. #define HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
  1196. #define HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff
  1197. #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
  1198. #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
  1199. /**
  1200. * hal_ce_dst_setup() - Initialize CE destination ring registers
  1201. * @hal: HAL SOC handle
  1202. * @srng: SRNG ring pointer
  1203. * @ring_num: ring number
  1204. */
  1205. static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng,
  1206. int ring_num)
  1207. {
  1208. uint32_t reg_val = 0;
  1209. uint32_t reg_addr;
  1210. struct hal_hw_srng_config *ring_config =
  1211. HAL_SRNG_CONFIG(hal, CE_DST);
  1212. /* set DEST_MAX_LENGTH according to ce assignment */
  1213. reg_addr = HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR(
  1214. ring_config->reg_start[R0_INDEX] +
  1215. (ring_num * ring_config->reg_size[R0_INDEX]));
  1216. reg_val = HAL_REG_READ(hal, reg_addr);
  1217. reg_val &= ~HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK;
  1218. reg_val |= srng->u.dst_ring.max_buffer_length &
  1219. HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK;
  1220. HAL_REG_WRITE(hal, reg_addr, reg_val);
  1221. if (srng->prefetch_timer) {
  1222. reg_addr = HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(
  1223. ring_config->reg_start[R0_INDEX] +
  1224. (ring_num * ring_config->reg_size[R0_INDEX]));
  1225. reg_val = HAL_REG_READ(hal, reg_addr);
  1226. reg_val &= ~HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK;
  1227. reg_val |= srng->prefetch_timer;
  1228. HAL_REG_WRITE(hal, reg_addr, reg_val);
  1229. reg_val = HAL_REG_READ(hal, reg_addr);
  1230. }
  1231. }
  1232. void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read,
  1233. uint32_t *ix0, uint32_t *ix1,
  1234. uint32_t *ix2, uint32_t *ix3)
  1235. {
  1236. uint32_t reg_offset;
  1237. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  1238. uint32_t reo_reg_base;
  1239. reo_reg_base = hal_get_reo_reg_base_offset(hal_soc_hdl);
  1240. if (read) {
  1241. if (ix0) {
  1242. reg_offset =
  1243. HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(
  1244. reo_reg_base);
  1245. *ix0 = HAL_REG_READ(hal, reg_offset);
  1246. }
  1247. if (ix1) {
  1248. reg_offset =
  1249. HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(
  1250. reo_reg_base);
  1251. *ix1 = HAL_REG_READ(hal, reg_offset);
  1252. }
  1253. if (ix2) {
  1254. reg_offset =
  1255. HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(
  1256. reo_reg_base);
  1257. *ix2 = HAL_REG_READ(hal, reg_offset);
  1258. }
  1259. if (ix3) {
  1260. reg_offset =
  1261. HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(
  1262. reo_reg_base);
  1263. *ix3 = HAL_REG_READ(hal, reg_offset);
  1264. }
  1265. } else {
  1266. if (ix0) {
  1267. reg_offset =
  1268. HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(
  1269. reo_reg_base);
  1270. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1271. *ix0, true);
  1272. }
  1273. if (ix1) {
  1274. reg_offset =
  1275. HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(
  1276. reo_reg_base);
  1277. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1278. *ix1, true);
  1279. }
  1280. if (ix2) {
  1281. reg_offset =
  1282. HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(
  1283. reo_reg_base);
  1284. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1285. *ix2, true);
  1286. }
  1287. if (ix3) {
  1288. reg_offset =
  1289. HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(
  1290. reo_reg_base);
  1291. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1292. *ix3, true);
  1293. }
  1294. }
  1295. }
  1296. qdf_export_symbol(hal_reo_read_write_ctrl_ix);
  1297. void hal_srng_dst_set_hp_paddr_confirm(struct hal_srng *srng, uint64_t paddr)
  1298. {
  1299. SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_LSB, paddr & 0xffffffff);
  1300. SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_MSB, paddr >> 32);
  1301. }
  1302. qdf_export_symbol(hal_srng_dst_set_hp_paddr_confirm);
  1303. void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc,
  1304. struct hal_srng *srng,
  1305. uint32_t *vaddr)
  1306. {
  1307. uint32_t reg_offset;
  1308. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1309. if (!srng)
  1310. return;
  1311. srng->u.dst_ring.hp_addr = vaddr;
  1312. reg_offset = SRNG_DST_ADDR(srng, HP) - hal->dev_base_addr;
  1313. HAL_REG_WRITE_CONFIRM_RETRY(
  1314. hal, reg_offset, srng->u.dst_ring.cached_hp, true);
  1315. if (vaddr) {
  1316. *srng->u.dst_ring.hp_addr = srng->u.dst_ring.cached_hp;
  1317. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1318. "hp_addr=%pK, cached_hp=%d",
  1319. (void *)srng->u.dst_ring.hp_addr,
  1320. srng->u.dst_ring.cached_hp);
  1321. }
  1322. }
  1323. qdf_export_symbol(hal_srng_dst_init_hp);
  1324. void hal_srng_dst_update_hp_addr(struct hal_soc_handle *hal_soc,
  1325. hal_ring_handle_t hal_ring_hdl)
  1326. {
  1327. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1328. int32_t hw_hp;
  1329. int32_t hw_tp;
  1330. if (!srng)
  1331. return;
  1332. if (srng->u.dst_ring.hp_addr) {
  1333. hal_get_hw_hptp(hal_soc, hal_ring_hdl, &hw_hp, &hw_tp,
  1334. WBM2SW_RELEASE);
  1335. *srng->u.dst_ring.hp_addr = hw_hp;
  1336. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1337. "hw_hp=%d", hw_hp);
  1338. }
  1339. }
  1340. qdf_export_symbol(hal_srng_dst_update_hp_addr);
  1341. /**
  1342. * hal_srng_hw_init - Private function to initialize SRNG HW
  1343. * @hal: HAL SOC handle
  1344. * @srng: SRNG ring pointer
  1345. * @idle_check: Check if ring is idle
  1346. * @idx: ring index
  1347. */
  1348. static inline void hal_srng_hw_init(struct hal_soc *hal,
  1349. struct hal_srng *srng, bool idle_check, uint32_t idx)
  1350. {
  1351. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1352. hal_srng_src_hw_init(hal, srng, idle_check, idx);
  1353. else
  1354. hal_srng_dst_hw_init(hal, srng, idle_check, idx);
  1355. }
  1356. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1357. bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc,
  1358. int ring_type, int ring_num)
  1359. {
  1360. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1361. struct hal_hw_srng_config *ring_config =
  1362. HAL_SRNG_CONFIG(hal, ring_type);
  1363. return ring_config->nf_irq_support;
  1364. }
  1365. /**
  1366. * hal_srng_set_msi2_params() - Set MSI2 params to SRNG data structure from
  1367. * ring params
  1368. * @srng: SRNG handle
  1369. * @ring_params: ring params for this SRNG
  1370. *
  1371. * Return: None
  1372. */
  1373. static inline void
  1374. hal_srng_set_msi2_params(struct hal_srng *srng,
  1375. struct hal_srng_params *ring_params)
  1376. {
  1377. srng->msi2_addr = ring_params->msi2_addr;
  1378. srng->msi2_data = ring_params->msi2_data;
  1379. }
  1380. /**
  1381. * hal_srng_get_nf_params() - Get the near full MSI2 params from srng
  1382. * @srng: SRNG handle
  1383. * @ring_params: ring params for this SRNG
  1384. *
  1385. * Return: None
  1386. */
  1387. static inline void
  1388. hal_srng_get_nf_params(struct hal_srng *srng,
  1389. struct hal_srng_params *ring_params)
  1390. {
  1391. ring_params->msi2_addr = srng->msi2_addr;
  1392. ring_params->msi2_data = srng->msi2_data;
  1393. }
  1394. /**
  1395. * hal_srng_set_nf_thresholds() - Set the near full thresholds in SRNG
  1396. * @srng: SRNG handle where the params are to be set
  1397. * @ring_params: ring params, from where threshold is to be fetched
  1398. *
  1399. * Return: None
  1400. */
  1401. static inline void
  1402. hal_srng_set_nf_thresholds(struct hal_srng *srng,
  1403. struct hal_srng_params *ring_params)
  1404. {
  1405. srng->u.dst_ring.nf_irq_support = ring_params->nf_irq_support;
  1406. srng->u.dst_ring.high_thresh = ring_params->high_thresh;
  1407. }
  1408. #else
  1409. static inline void
  1410. hal_srng_set_msi2_params(struct hal_srng *srng,
  1411. struct hal_srng_params *ring_params)
  1412. {
  1413. }
  1414. static inline void
  1415. hal_srng_get_nf_params(struct hal_srng *srng,
  1416. struct hal_srng_params *ring_params)
  1417. {
  1418. }
  1419. static inline void
  1420. hal_srng_set_nf_thresholds(struct hal_srng *srng,
  1421. struct hal_srng_params *ring_params)
  1422. {
  1423. }
  1424. #endif
  1425. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  1426. /**
  1427. * hal_srng_last_desc_cleared_init - Initialize SRNG last_desc_cleared ptr
  1428. * @srng: Source ring pointer
  1429. *
  1430. * Return: None
  1431. */
  1432. static inline
  1433. void hal_srng_last_desc_cleared_init(struct hal_srng *srng)
  1434. {
  1435. srng->last_desc_cleared = srng->ring_size - srng->entry_size;
  1436. }
  1437. #else
  1438. static inline
  1439. void hal_srng_last_desc_cleared_init(struct hal_srng *srng)
  1440. {
  1441. }
  1442. #endif /* CLEAR_SW2TCL_CONSUMED_DESC */
  1443. #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING
  1444. static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng)
  1445. {
  1446. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100] =
  1447. ((srng->num_entries * 90) / 100);
  1448. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90] =
  1449. ((srng->num_entries * 80) / 100);
  1450. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80] =
  1451. ((srng->num_entries * 70) / 100);
  1452. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70] =
  1453. ((srng->num_entries * 60) / 100);
  1454. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60] =
  1455. ((srng->num_entries * 50) / 100);
  1456. /* Below 50% threshold is not needed */
  1457. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT] = 0;
  1458. hal_info("ring_id: %u, wm_thresh- <50:%u, 50-60:%u, 60-70:%u, 70-80:%u, 80-90:%u, 90-100:%u",
  1459. srng->ring_id,
  1460. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT],
  1461. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60],
  1462. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70],
  1463. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80],
  1464. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90],
  1465. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100]);
  1466. }
  1467. #else
  1468. static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng)
  1469. {
  1470. }
  1471. #endif
  1472. void *hal_srng_setup_idx(void *hal_soc, int ring_type, int ring_num, int mac_id,
  1473. struct hal_srng_params *ring_params, bool idle_check,
  1474. uint32_t idx)
  1475. {
  1476. int ring_id;
  1477. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1478. hal_soc_handle_t hal_hdl = (hal_soc_handle_t)hal;
  1479. struct hal_srng *srng;
  1480. struct hal_hw_srng_config *ring_config =
  1481. HAL_SRNG_CONFIG(hal, ring_type);
  1482. void *dev_base_addr;
  1483. int i;
  1484. ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, mac_id);
  1485. if (ring_id < 0)
  1486. return NULL;
  1487. hal_verbose_debug("mac_id %d ring_id %d", mac_id, ring_id);
  1488. srng = hal_get_srng(hal_soc, ring_id);
  1489. if (srng->initialized) {
  1490. hal_verbose_debug("Ring (ring_type, ring_num) already initialized");
  1491. return NULL;
  1492. }
  1493. hal_srng_reg_his_init(srng);
  1494. dev_base_addr = hal->dev_base_addr;
  1495. srng->ring_id = ring_id;
  1496. srng->ring_type = ring_type;
  1497. srng->ring_dir = ring_config->ring_dir;
  1498. srng->ring_base_paddr = ring_params->ring_base_paddr;
  1499. srng->ring_base_vaddr = ring_params->ring_base_vaddr;
  1500. srng->entry_size = ring_config->entry_size;
  1501. srng->num_entries = ring_params->num_entries;
  1502. srng->ring_size = srng->num_entries * srng->entry_size;
  1503. srng->ring_size_mask = srng->ring_size - 1;
  1504. srng->ring_vaddr_end = srng->ring_base_vaddr + srng->ring_size;
  1505. srng->msi_addr = ring_params->msi_addr;
  1506. srng->msi_data = ring_params->msi_data;
  1507. srng->intr_timer_thres_us = ring_params->intr_timer_thres_us;
  1508. srng->intr_batch_cntr_thres_entries =
  1509. ring_params->intr_batch_cntr_thres_entries;
  1510. srng->pointer_timer_threshold =
  1511. ring_params->pointer_timer_threshold;
  1512. srng->pointer_num_threshold =
  1513. ring_params->pointer_num_threshold;
  1514. if (!idle_check)
  1515. srng->prefetch_timer = ring_params->prefetch_timer;
  1516. srng->hal_soc = hal_soc;
  1517. hal_srng_set_msi2_params(srng, ring_params);
  1518. hal_srng_update_high_wm_thresholds(srng);
  1519. for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) {
  1520. srng->hwreg_base[i] = dev_base_addr + ring_config->reg_start[i]
  1521. + (ring_num * ring_config->reg_size[i]);
  1522. }
  1523. /* Zero out the entire ring memory */
  1524. qdf_mem_zero(srng->ring_base_vaddr, (srng->entry_size *
  1525. srng->num_entries) << 2);
  1526. srng->flags = ring_params->flags;
  1527. /* For cached descriptors flush and invalidate the memory*/
  1528. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1529. qdf_nbuf_dma_clean_range(
  1530. srng->ring_base_vaddr,
  1531. srng->ring_base_vaddr +
  1532. ((srng->entry_size * srng->num_entries)));
  1533. qdf_nbuf_dma_inv_range(
  1534. srng->ring_base_vaddr,
  1535. srng->ring_base_vaddr +
  1536. ((srng->entry_size * srng->num_entries)));
  1537. }
  1538. #ifdef BIG_ENDIAN_HOST
  1539. /* TODO: See if we should we get these flags from caller */
  1540. srng->flags |= HAL_SRNG_DATA_TLV_SWAP;
  1541. srng->flags |= HAL_SRNG_MSI_SWAP;
  1542. srng->flags |= HAL_SRNG_RING_PTR_SWAP;
  1543. #endif
  1544. hal_srng_last_desc_cleared_init(srng);
  1545. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1546. srng->u.src_ring.hp = 0;
  1547. srng->u.src_ring.reap_hp = srng->ring_size -
  1548. srng->entry_size;
  1549. srng->u.src_ring.tp_addr =
  1550. &(hal->shadow_rdptr_mem_vaddr[ring_id]);
  1551. srng->u.src_ring.low_threshold =
  1552. ring_params->low_threshold * srng->entry_size;
  1553. if (srng->u.src_ring.tp_addr)
  1554. qdf_mem_zero(srng->u.src_ring.tp_addr,
  1555. sizeof(*hal->shadow_rdptr_mem_vaddr));
  1556. if (ring_config->lmac_ring) {
  1557. /* For LMAC rings, head pointer updates will be done
  1558. * through FW by writing to a shared memory location
  1559. */
  1560. srng->u.src_ring.hp_addr =
  1561. &(hal->shadow_wrptr_mem_vaddr[ring_id -
  1562. HAL_SRNG_LMAC1_ID_START]);
  1563. srng->flags |= HAL_SRNG_LMAC_RING;
  1564. if (srng->u.src_ring.hp_addr)
  1565. qdf_mem_zero(srng->u.src_ring.hp_addr,
  1566. sizeof(*hal->shadow_wrptr_mem_vaddr));
  1567. } else if (ignore_shadow || (srng->u.src_ring.hp_addr == 0)) {
  1568. srng->u.src_ring.hp_addr =
  1569. hal_get_window_address(hal,
  1570. SRNG_SRC_ADDR(srng, HP));
  1571. if (CHECK_SHADOW_REGISTERS) {
  1572. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1573. QDF_TRACE_LEVEL_ERROR,
  1574. "%s: Ring (%d, %d) missing shadow config",
  1575. __func__, ring_type, ring_num);
  1576. }
  1577. } else {
  1578. hal_validate_shadow_register(hal,
  1579. SRNG_SRC_ADDR(srng, HP),
  1580. srng->u.src_ring.hp_addr);
  1581. }
  1582. } else {
  1583. /* During initialization loop count in all the descriptors
  1584. * will be set to zero, and HW will set it to 1 on completing
  1585. * descriptor update in first loop, and increments it by 1 on
  1586. * subsequent loops (loop count wraps around after reaching
  1587. * 0xffff). The 'loop_cnt' in SW ring state is the expected
  1588. * loop count in descriptors updated by HW (to be processed
  1589. * by SW).
  1590. */
  1591. hal_srng_set_nf_thresholds(srng, ring_params);
  1592. srng->u.dst_ring.loop_cnt = 1;
  1593. srng->u.dst_ring.tp = 0;
  1594. srng->u.dst_ring.hp_addr =
  1595. &(hal->shadow_rdptr_mem_vaddr[ring_id]);
  1596. if (srng->u.dst_ring.hp_addr)
  1597. qdf_mem_zero(srng->u.dst_ring.hp_addr,
  1598. sizeof(*hal->shadow_rdptr_mem_vaddr));
  1599. if (ring_config->lmac_ring) {
  1600. /* For LMAC rings, tail pointer updates will be done
  1601. * through FW by writing to a shared memory location
  1602. */
  1603. srng->u.dst_ring.tp_addr =
  1604. &(hal->shadow_wrptr_mem_vaddr[ring_id -
  1605. HAL_SRNG_LMAC1_ID_START]);
  1606. srng->flags |= HAL_SRNG_LMAC_RING;
  1607. if (srng->u.dst_ring.tp_addr)
  1608. qdf_mem_zero(srng->u.dst_ring.tp_addr,
  1609. sizeof(*hal->shadow_wrptr_mem_vaddr));
  1610. } else if (ignore_shadow || srng->u.dst_ring.tp_addr == 0) {
  1611. srng->u.dst_ring.tp_addr =
  1612. hal_get_window_address(hal,
  1613. SRNG_DST_ADDR(srng, TP));
  1614. if (CHECK_SHADOW_REGISTERS) {
  1615. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1616. QDF_TRACE_LEVEL_ERROR,
  1617. "%s: Ring (%d, %d) missing shadow config",
  1618. __func__, ring_type, ring_num);
  1619. }
  1620. } else {
  1621. hal_validate_shadow_register(hal,
  1622. SRNG_DST_ADDR(srng, TP),
  1623. srng->u.dst_ring.tp_addr);
  1624. }
  1625. }
  1626. if (!(ring_config->lmac_ring)) {
  1627. /*
  1628. * UMAC reset has idle check enabled.
  1629. * During UMAC reset Tx ring halt is set
  1630. * by Wi-Fi FW during pre-reset stage,
  1631. * avoid Tx ring halt again.
  1632. */
  1633. if (idle_check && idx) {
  1634. if (!hal->ops->hal_tx_ring_halt_get(hal_hdl)) {
  1635. qdf_print("\nTx ring halt not set:Ring(%d, %d)",
  1636. ring_type, ring_num);
  1637. qdf_assert_always(0);
  1638. }
  1639. hal_srng_hw_init(hal, srng, idle_check, idx);
  1640. goto ce_setup;
  1641. }
  1642. if (idx) {
  1643. hal->ops->hal_tx_ring_halt_set(hal_hdl);
  1644. do {
  1645. hal_info("Waiting for ring reset");
  1646. } while (!(hal->ops->hal_tx_ring_halt_poll(hal_hdl)));
  1647. }
  1648. hal_srng_hw_init(hal, srng, idle_check, idx);
  1649. if (idx) {
  1650. hal->ops->hal_tx_ring_halt_reset(hal_hdl);
  1651. }
  1652. ce_setup:
  1653. if (ring_type == CE_DST) {
  1654. srng->u.dst_ring.max_buffer_length = ring_params->max_buffer_length;
  1655. hal_ce_dst_setup(hal, srng, ring_num);
  1656. }
  1657. }
  1658. SRNG_LOCK_INIT(&srng->lock);
  1659. srng->srng_event = 0;
  1660. srng->initialized = true;
  1661. return (void *)srng;
  1662. }
  1663. qdf_export_symbol(hal_srng_setup_idx);
  1664. /**
  1665. * hal_srng_setup - Initialize HW SRNG ring.
  1666. * @hal_soc: Opaque HAL SOC handle
  1667. * @ring_type: one of the types from hal_ring_type
  1668. * @ring_num: Ring number if there are multiple rings of same type (staring
  1669. * from 0)
  1670. * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  1671. * @ring_params: SRNG ring params in hal_srng_params structure.
  1672. * @idle_check: Check if ring is idle
  1673. *
  1674. * Callers are expected to allocate contiguous ring memory of size
  1675. * 'num_entries * entry_size' bytes and pass the physical and virtual base
  1676. * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in
  1677. * hal_srng_params structure. Ring base address should be 8 byte aligned
  1678. * and size of each ring entry should be queried using the API
  1679. * hal_srng_get_entrysize
  1680. *
  1681. * Return: Opaque pointer to ring on success
  1682. * NULL on failure (if given ring is not available)
  1683. */
  1684. void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
  1685. int mac_id, struct hal_srng_params *ring_params,
  1686. bool idle_check)
  1687. {
  1688. return hal_srng_setup_idx(hal_soc, ring_type, ring_num, mac_id,
  1689. ring_params, idle_check, 0);
  1690. }
  1691. qdf_export_symbol(hal_srng_setup);
  1692. void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl,
  1693. bool umac_reset_inprogress)
  1694. {
  1695. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1696. SRNG_LOCK_DESTROY(&srng->lock);
  1697. srng->initialized = 0;
  1698. if (umac_reset_inprogress)
  1699. hal_srng_hw_disable(hal_soc, srng);
  1700. }
  1701. qdf_export_symbol(hal_srng_cleanup);
  1702. uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type)
  1703. {
  1704. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1705. struct hal_hw_srng_config *ring_config =
  1706. HAL_SRNG_CONFIG(hal, ring_type);
  1707. return ring_config->entry_size << 2;
  1708. }
  1709. qdf_export_symbol(hal_srng_get_entrysize);
  1710. uint32_t hal_srng_max_entries(void *hal_soc, int ring_type)
  1711. {
  1712. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1713. struct hal_hw_srng_config *ring_config =
  1714. HAL_SRNG_CONFIG(hal, ring_type);
  1715. return ring_config->max_size / ring_config->entry_size;
  1716. }
  1717. qdf_export_symbol(hal_srng_max_entries);
  1718. enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type)
  1719. {
  1720. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1721. struct hal_hw_srng_config *ring_config =
  1722. HAL_SRNG_CONFIG(hal, ring_type);
  1723. return ring_config->ring_dir;
  1724. }
  1725. void hal_srng_dump(struct hal_srng *srng)
  1726. {
  1727. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1728. hal_debug("=== SRC RING %d ===", srng->ring_id);
  1729. hal_debug("hp %u, reap_hp %u, tp %u, cached tp %u",
  1730. srng->u.src_ring.hp,
  1731. srng->u.src_ring.reap_hp,
  1732. *srng->u.src_ring.tp_addr,
  1733. srng->u.src_ring.cached_tp);
  1734. } else {
  1735. hal_debug("=== DST RING %d ===", srng->ring_id);
  1736. hal_debug("tp %u, hp %u, cached tp %u, loop_cnt %u",
  1737. srng->u.dst_ring.tp,
  1738. *srng->u.dst_ring.hp_addr,
  1739. srng->u.dst_ring.cached_hp,
  1740. srng->u.dst_ring.loop_cnt);
  1741. }
  1742. }
  1743. void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl,
  1744. hal_ring_handle_t hal_ring_hdl,
  1745. struct hal_srng_params *ring_params)
  1746. {
  1747. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1748. int i =0;
  1749. ring_params->ring_id = srng->ring_id;
  1750. ring_params->ring_dir = srng->ring_dir;
  1751. ring_params->entry_size = srng->entry_size;
  1752. ring_params->ring_base_paddr = srng->ring_base_paddr;
  1753. ring_params->ring_base_vaddr = srng->ring_base_vaddr;
  1754. ring_params->num_entries = srng->num_entries;
  1755. ring_params->msi_addr = srng->msi_addr;
  1756. ring_params->msi_data = srng->msi_data;
  1757. ring_params->intr_timer_thres_us = srng->intr_timer_thres_us;
  1758. ring_params->intr_batch_cntr_thres_entries =
  1759. srng->intr_batch_cntr_thres_entries;
  1760. ring_params->low_threshold = srng->u.src_ring.low_threshold;
  1761. ring_params->flags = srng->flags;
  1762. ring_params->ring_id = srng->ring_id;
  1763. for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++)
  1764. ring_params->hwreg_base[i] = srng->hwreg_base[i];
  1765. hal_srng_get_nf_params(srng, ring_params);
  1766. }
  1767. qdf_export_symbol(hal_get_srng_params);
  1768. void hal_set_low_threshold(hal_ring_handle_t hal_ring_hdl,
  1769. uint32_t low_threshold)
  1770. {
  1771. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1772. srng->u.src_ring.low_threshold = low_threshold * srng->entry_size;
  1773. }
  1774. qdf_export_symbol(hal_set_low_threshold);
  1775. #ifdef FEATURE_RUNTIME_PM
  1776. void
  1777. hal_srng_rtpm_access_end(hal_soc_handle_t hal_soc_hdl,
  1778. hal_ring_handle_t hal_ring_hdl,
  1779. uint32_t rtpm_id)
  1780. {
  1781. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1782. if (qdf_unlikely(!hal_ring_hdl)) {
  1783. qdf_print("Error: Invalid hal_ring\n");
  1784. return;
  1785. }
  1786. if (hif_rtpm_get(HIF_RTPM_GET_ASYNC, rtpm_id) == 0) {
  1787. if (hif_system_pm_state_check(hal_soc->hif_handle)) {
  1788. hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
  1789. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1790. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1791. } else {
  1792. hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
  1793. }
  1794. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, rtpm_id);
  1795. } else {
  1796. hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
  1797. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1798. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1799. }
  1800. }
  1801. qdf_export_symbol(hal_srng_rtpm_access_end);
  1802. #endif /* FEATURE_RUNTIME_PM */
  1803. #ifdef FORCE_WAKE
  1804. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase)
  1805. {
  1806. struct hal_soc *hal_soc = (struct hal_soc *)soc;
  1807. hal_soc->init_phase = init_phase;
  1808. }
  1809. #endif /* FORCE_WAKE */