dp_ipa.c 125 KB

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  1. /*
  2. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifdef IPA_OFFLOAD
  18. #include <wlan_ipa_ucfg_api.h>
  19. #include <wlan_ipa_core.h>
  20. #include <qdf_ipa_wdi3.h>
  21. #include <qdf_types.h>
  22. #include <qdf_lock.h>
  23. #include <hal_hw_headers.h>
  24. #include <hal_api.h>
  25. #include <hal_reo.h>
  26. #include <hif.h>
  27. #include <htt.h>
  28. #include <wdi_event.h>
  29. #include <queue.h>
  30. #include "dp_types.h"
  31. #include "dp_htt.h"
  32. #include "dp_tx.h"
  33. #include "dp_rx.h"
  34. #include "dp_ipa.h"
  35. #include "dp_internal.h"
  36. #ifdef WIFI_MONITOR_SUPPORT
  37. #include "dp_mon.h"
  38. #endif
  39. #ifdef FEATURE_WDS
  40. #include "dp_txrx_wds.h"
  41. #endif
  42. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  43. #include <pld_common.h>
  44. #endif
  45. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  46. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  47. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  48. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  49. * This causes back pressure, resulting in a FW crash.
  50. * By leaving some entries with no buffer attached, WBM will be able to write
  51. * to the ring, and from dumps we can figure out the buffer which is causing
  52. * this issue.
  53. */
  54. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  55. /**
  56. * struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  57. * @timestamp: Timestamp when remap occurs
  58. * @ix0_reg: reo destination ring IX0 value
  59. * @ix2_reg: reo destination ring IX2 value
  60. * @ix3_reg: reo destination ring IX3 value
  61. */
  62. struct dp_ipa_reo_remap_record {
  63. uint64_t timestamp;
  64. uint32_t ix0_reg;
  65. uint32_t ix2_reg;
  66. uint32_t ix3_reg;
  67. };
  68. #define WLAN_IPA_AST_META_DATA_MASK htonl(0x000000FF)
  69. #define WLAN_IPA_META_DATA_MASK htonl(0x00FF0000)
  70. #define REO_REMAP_HISTORY_SIZE 32
  71. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  72. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  73. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  74. {
  75. int next = qdf_atomic_inc_return(index);
  76. if (next == REO_REMAP_HISTORY_SIZE)
  77. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  78. return next % REO_REMAP_HISTORY_SIZE;
  79. }
  80. /**
  81. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  82. * @ix0_val: reo destination ring IX0 value
  83. * @ix2_val: reo destination ring IX2 value
  84. * @ix3_val: reo destination ring IX3 value
  85. *
  86. * Return: None
  87. */
  88. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  89. uint32_t ix3_val)
  90. {
  91. int idx = dp_ipa_reo_remap_record_index_next(
  92. &dp_ipa_reo_remap_history_index);
  93. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  94. record->timestamp = qdf_get_log_timestamp();
  95. record->ix0_reg = ix0_val;
  96. record->ix2_reg = ix2_val;
  97. record->ix3_reg = ix3_val;
  98. }
  99. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  100. qdf_nbuf_t nbuf,
  101. uint32_t size,
  102. bool create,
  103. const char *func,
  104. uint32_t line)
  105. {
  106. qdf_mem_info_t mem_map_table = {0};
  107. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  108. qdf_ipa_wdi_hdl_t hdl;
  109. /* Need to handle the case when one soc will
  110. * have multiple pdev(radio's), Currently passing
  111. * pdev_id as 0 assuming 1 soc has only 1 radio.
  112. */
  113. hdl = wlan_ipa_get_hdl(soc->ctrl_psoc, 0);
  114. if (hdl == DP_IPA_HDL_INVALID) {
  115. dp_err("IPA handle is invalid");
  116. return QDF_STATUS_E_INVAL;
  117. }
  118. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  119. qdf_nbuf_get_frag_paddr(nbuf, 0),
  120. size);
  121. if (create) {
  122. /* Assert if PA is zero */
  123. qdf_assert_always(mem_map_table.pa);
  124. ret = qdf_nbuf_smmu_map_debug(nbuf, hdl, 1, &mem_map_table,
  125. func, line);
  126. } else {
  127. ret = qdf_nbuf_smmu_unmap_debug(nbuf, hdl, 1, &mem_map_table,
  128. func, line);
  129. }
  130. qdf_assert_always(!ret);
  131. /* Return status of mapping/unmapping is stored in
  132. * mem_map_table.result field, assert if the result
  133. * is failure
  134. */
  135. if (create)
  136. qdf_assert_always(!mem_map_table.result);
  137. else
  138. qdf_assert_always(mem_map_table.result >= mem_map_table.size);
  139. return ret;
  140. }
  141. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  142. qdf_nbuf_t nbuf,
  143. uint32_t size,
  144. bool create, const char *func,
  145. uint32_t line)
  146. {
  147. struct dp_pdev *pdev;
  148. int i;
  149. for (i = 0; i < soc->pdev_count; i++) {
  150. pdev = soc->pdev_list[i];
  151. if (pdev && dp_monitor_is_configured(pdev))
  152. return QDF_STATUS_SUCCESS;
  153. }
  154. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  155. !qdf_mem_smmu_s1_enabled(soc->osdev))
  156. return QDF_STATUS_SUCCESS;
  157. /*
  158. * Even if ipa pipes is disabled, but if it's unmap
  159. * operation and nbuf has done ipa smmu map before,
  160. * do ipa smmu unmap as well.
  161. */
  162. if (!(qdf_atomic_read(&soc->ipa_pipes_enabled) &&
  163. qdf_atomic_read(&soc->ipa_map_allowed))) {
  164. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  165. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  166. } else {
  167. return QDF_STATUS_SUCCESS;
  168. }
  169. }
  170. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  171. if (create) {
  172. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  173. } else {
  174. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  175. }
  176. return QDF_STATUS_E_INVAL;
  177. }
  178. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  179. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create,
  180. func, line);
  181. }
  182. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  183. struct dp_soc *soc,
  184. struct dp_pdev *pdev,
  185. bool create,
  186. const char *func,
  187. uint32_t line)
  188. {
  189. uint32_t index;
  190. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  191. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  192. qdf_nbuf_t nbuf;
  193. uint32_t buf_len;
  194. if (!ipa_is_ready()) {
  195. dp_info("IPA is not READY");
  196. return 0;
  197. }
  198. for (index = 0; index < tx_buffer_cnt; index++) {
  199. nbuf = (qdf_nbuf_t)
  200. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  201. if (!nbuf)
  202. continue;
  203. buf_len = qdf_nbuf_get_data_len(nbuf);
  204. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  205. create, func, line);
  206. }
  207. return ret;
  208. }
  209. #ifndef QCA_OL_DP_SRNG_LOCK_LESS_ACCESS
  210. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  211. bool lock_required)
  212. {
  213. hal_ring_handle_t hal_ring_hdl;
  214. int ring;
  215. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  216. hal_ring_hdl = soc->reo_dest_ring[ring].hal_srng;
  217. hal_srng_lock(hal_ring_hdl);
  218. soc->ipa_reo_ctx_lock_required[ring] = lock_required;
  219. hal_srng_unlock(hal_ring_hdl);
  220. }
  221. }
  222. #else
  223. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  224. bool lock_required)
  225. {
  226. }
  227. #endif
  228. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  229. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  230. struct dp_pdev *pdev,
  231. bool create,
  232. const char *func,
  233. uint32_t line)
  234. {
  235. struct rx_desc_pool *rx_pool;
  236. uint8_t pdev_id;
  237. uint32_t num_desc, page_id, offset, i;
  238. uint16_t num_desc_per_page;
  239. union dp_rx_desc_list_elem_t *rx_desc_elem;
  240. struct dp_rx_desc *rx_desc;
  241. qdf_nbuf_t nbuf;
  242. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  243. if (!qdf_ipa_is_ready())
  244. return ret;
  245. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  246. return ret;
  247. pdev_id = pdev->pdev_id;
  248. rx_pool = &soc->rx_desc_buf[pdev_id];
  249. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  250. qdf_spin_lock_bh(&rx_pool->lock);
  251. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  252. num_desc = rx_pool->pool_size;
  253. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  254. for (i = 0; i < num_desc; i++) {
  255. page_id = i / num_desc_per_page;
  256. offset = i % num_desc_per_page;
  257. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  258. break;
  259. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  260. rx_desc = &rx_desc_elem->rx_desc;
  261. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  262. continue;
  263. nbuf = rx_desc->nbuf;
  264. if (qdf_unlikely(create ==
  265. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  266. if (create) {
  267. DP_STATS_INC(soc,
  268. rx.err.ipa_smmu_map_dup, 1);
  269. } else {
  270. DP_STATS_INC(soc,
  271. rx.err.ipa_smmu_unmap_dup, 1);
  272. }
  273. continue;
  274. }
  275. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  276. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  277. rx_pool->buf_size,
  278. create, func, line);
  279. }
  280. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  281. qdf_spin_unlock_bh(&rx_pool->lock);
  282. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  283. return ret;
  284. }
  285. #else
  286. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(
  287. struct dp_soc *soc,
  288. struct dp_pdev *pdev,
  289. bool create,
  290. const char *func,
  291. uint32_t line)
  292. {
  293. struct rx_desc_pool *rx_pool;
  294. uint8_t pdev_id;
  295. qdf_nbuf_t nbuf;
  296. int i;
  297. if (!qdf_ipa_is_ready())
  298. return QDF_STATUS_SUCCESS;
  299. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  300. return QDF_STATUS_SUCCESS;
  301. pdev_id = pdev->pdev_id;
  302. rx_pool = &soc->rx_desc_buf[pdev_id];
  303. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  304. qdf_spin_lock_bh(&rx_pool->lock);
  305. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  306. for (i = 0; i < rx_pool->pool_size; i++) {
  307. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  308. rx_pool->array[i].rx_desc.unmapped)
  309. continue;
  310. nbuf = rx_pool->array[i].rx_desc.nbuf;
  311. if (qdf_unlikely(create ==
  312. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  313. if (create) {
  314. DP_STATS_INC(soc,
  315. rx.err.ipa_smmu_map_dup, 1);
  316. } else {
  317. DP_STATS_INC(soc,
  318. rx.err.ipa_smmu_unmap_dup, 1);
  319. }
  320. continue;
  321. }
  322. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  323. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, rx_pool->buf_size,
  324. create, func, line);
  325. }
  326. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  327. qdf_spin_unlock_bh(&rx_pool->lock);
  328. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  329. return QDF_STATUS_SUCCESS;
  330. }
  331. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  332. QDF_STATUS dp_ipa_set_smmu_mapped(struct cdp_soc_t *soc_hdl, int val)
  333. {
  334. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  335. qdf_atomic_set(&soc->ipa_map_allowed, val);
  336. return QDF_STATUS_SUCCESS;
  337. }
  338. int dp_ipa_get_smmu_mapped(struct cdp_soc_t *soc_hdl)
  339. {
  340. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  341. return qdf_atomic_read(&soc->ipa_map_allowed);
  342. }
  343. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  344. qdf_shared_mem_t *shared_mem,
  345. void *cpu_addr,
  346. qdf_dma_addr_t dma_addr,
  347. uint32_t size)
  348. {
  349. qdf_dma_addr_t paddr;
  350. int ret;
  351. shared_mem->vaddr = cpu_addr;
  352. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  353. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  354. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  355. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  356. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  357. shared_mem->vaddr, dma_addr, size);
  358. if (ret) {
  359. dp_err("Unable to get DMA sgtable");
  360. return QDF_STATUS_E_NOMEM;
  361. }
  362. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  363. return QDF_STATUS_SUCCESS;
  364. }
  365. /**
  366. * dp_ipa_get_tx_bank_id() - API to get TCL bank id
  367. * @soc: dp_soc handle
  368. * @bank_id: out parameter for bank id
  369. *
  370. * Return: QDF_STATUS
  371. */
  372. static QDF_STATUS dp_ipa_get_tx_bank_id(struct dp_soc *soc, uint8_t *bank_id)
  373. {
  374. if (soc->arch_ops.ipa_get_bank_id) {
  375. *bank_id = soc->arch_ops.ipa_get_bank_id(soc);
  376. if (*bank_id < 0) {
  377. return QDF_STATUS_E_INVAL;
  378. } else {
  379. dp_info("bank_id %u", *bank_id);
  380. return QDF_STATUS_SUCCESS;
  381. }
  382. } else {
  383. return QDF_STATUS_E_NOSUPPORT;
  384. }
  385. }
  386. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  387. defined(CONFIG_IPA_WDI_UNIFIED_API)
  388. static void dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  389. qdf_ipa_wdi_pipe_setup_info_t *tx)
  390. {
  391. uint8_t bank_id;
  392. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  393. QDF_IPA_WDI_SETUP_INFO_RX_BANK_ID(tx, bank_id);
  394. }
  395. static void
  396. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  397. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  398. {
  399. uint8_t bank_id;
  400. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  401. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_BANK_ID(tx_smmu, bank_id);
  402. }
  403. #else
  404. static inline void
  405. dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  406. qdf_ipa_wdi_pipe_setup_info_t *tx)
  407. {
  408. }
  409. static inline void
  410. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  411. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  412. {
  413. }
  414. #endif
  415. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  416. static void
  417. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  418. qdf_ipa_wdi_pipe_setup_info_t *tx)
  419. {
  420. uint8_t pmac_id = 0;
  421. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  422. if (soc->pdev_count > 1)
  423. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  424. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  425. }
  426. static void
  427. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  428. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  429. {
  430. uint8_t pmac_id = 0;
  431. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  432. if (soc->pdev_count > 1)
  433. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  434. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  435. }
  436. static void
  437. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  438. qdf_ipa_wdi_pipe_setup_info_t *tx)
  439. {
  440. uint8_t pmac_id;
  441. pmac_id = soc->pdev_list[0]->lmac_id;
  442. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  443. }
  444. static void
  445. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  446. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  447. {
  448. uint8_t pmac_id;
  449. pmac_id = soc->pdev_list[0]->lmac_id;
  450. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  451. }
  452. #else
  453. static inline void
  454. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  455. qdf_ipa_wdi_pipe_setup_info_t *tx)
  456. {
  457. }
  458. static inline void
  459. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  460. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  461. {
  462. }
  463. static inline void
  464. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  465. qdf_ipa_wdi_pipe_setup_info_t *tx)
  466. {
  467. }
  468. static inline void
  469. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  470. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  471. {
  472. }
  473. #endif
  474. #ifdef IPA_WDI3_TX_TWO_PIPES
  475. static void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  476. {
  477. struct dp_ipa_resources *ipa_res;
  478. qdf_nbuf_t nbuf;
  479. int idx;
  480. for (idx = 0; idx < soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt; idx++) {
  481. nbuf = (qdf_nbuf_t)
  482. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx];
  483. if (!nbuf)
  484. continue;
  485. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  486. qdf_mem_dp_tx_skb_cnt_dec();
  487. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  488. qdf_nbuf_free(nbuf);
  489. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx] =
  490. (void *)NULL;
  491. }
  492. qdf_mem_free(soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  493. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  494. ipa_res = &pdev->ipa_resource;
  495. if (!ipa_res->is_db_ddr_mapped && ipa_res->tx_alt_comp_doorbell_vaddr)
  496. iounmap(ipa_res->tx_alt_comp_doorbell_vaddr);
  497. qdf_mem_free_sgtable(&ipa_res->tx_alt_ring.sgtable);
  498. qdf_mem_free_sgtable(&ipa_res->tx_alt_comp_ring.sgtable);
  499. }
  500. static int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  501. {
  502. uint32_t tx_buffer_count;
  503. uint32_t ring_base_align = 8;
  504. qdf_dma_addr_t buffer_paddr;
  505. struct hal_srng *wbm_srng = (struct hal_srng *)
  506. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  507. struct hal_srng_params srng_params;
  508. uint32_t wbm_bm_id;
  509. void *ring_entry;
  510. int num_entries;
  511. qdf_nbuf_t nbuf;
  512. int retval = QDF_STATUS_SUCCESS;
  513. int max_alloc_count = 0;
  514. /*
  515. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  516. * unsigned int uc_tx_buf_sz =
  517. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  518. */
  519. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  520. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  521. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  522. IPA_TX_ALT_RING_IDX);
  523. hal_get_srng_params(soc->hal_soc,
  524. hal_srng_to_hal_ring_handle(wbm_srng),
  525. &srng_params);
  526. num_entries = srng_params.num_entries;
  527. max_alloc_count =
  528. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  529. if (max_alloc_count <= 0) {
  530. dp_err("incorrect value for buffer count %u", max_alloc_count);
  531. return -EINVAL;
  532. }
  533. dp_info("requested %d buffers to be posted to wbm ring",
  534. max_alloc_count);
  535. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned =
  536. qdf_mem_malloc(num_entries *
  537. sizeof(*soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned));
  538. if (!soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned) {
  539. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  540. return -ENOMEM;
  541. }
  542. hal_srng_access_start_unlocked(soc->hal_soc,
  543. hal_srng_to_hal_ring_handle(wbm_srng));
  544. /*
  545. * Allocate Tx buffers as many as possible.
  546. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  547. * Populate Tx buffers into WBM2IPA ring
  548. * This initial buffer population will simulate H/W as source ring,
  549. * and update HP
  550. */
  551. for (tx_buffer_count = 0;
  552. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  553. nbuf = qdf_nbuf_frag_alloc(soc->osdev, alloc_size, 0,
  554. 256, FALSE);
  555. if (!nbuf)
  556. break;
  557. ring_entry = hal_srng_dst_get_next_hp(
  558. soc->hal_soc,
  559. hal_srng_to_hal_ring_handle(wbm_srng));
  560. if (!ring_entry) {
  561. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  562. "%s: Failed to get WBM ring entry",
  563. __func__);
  564. qdf_nbuf_free(nbuf);
  565. break;
  566. }
  567. qdf_nbuf_map_single(soc->osdev, nbuf,
  568. QDF_DMA_BIDIRECTIONAL);
  569. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  570. qdf_mem_dp_tx_skb_cnt_inc();
  571. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  572. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  573. buffer_paddr, 0, wbm_bm_id);
  574. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[
  575. tx_buffer_count] = (void *)nbuf;
  576. }
  577. hal_srng_access_end_unlocked(soc->hal_soc,
  578. hal_srng_to_hal_ring_handle(wbm_srng));
  579. soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt = tx_buffer_count;
  580. if (tx_buffer_count) {
  581. dp_info("IPA TX buffer pool2: %d allocated", tx_buffer_count);
  582. } else {
  583. dp_err("Failed to allocate IPA TX buffer pool2");
  584. qdf_mem_free(
  585. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  586. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  587. retval = -ENOMEM;
  588. }
  589. return retval;
  590. }
  591. static QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  592. {
  593. struct dp_soc *soc = pdev->soc;
  594. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  595. ipa_res->tx_alt_ring_num_alloc_buffer =
  596. (uint32_t)soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt;
  597. dp_ipa_get_shared_mem_info(
  598. soc->osdev, &ipa_res->tx_alt_ring,
  599. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  600. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  601. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  602. dp_ipa_get_shared_mem_info(
  603. soc->osdev, &ipa_res->tx_alt_comp_ring,
  604. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  605. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  606. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  607. if (!qdf_mem_get_dma_addr(soc->osdev,
  608. &ipa_res->tx_alt_comp_ring.mem_info))
  609. return QDF_STATUS_E_FAILURE;
  610. return QDF_STATUS_SUCCESS;
  611. }
  612. static void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  613. {
  614. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  615. struct hal_srng *hal_srng;
  616. struct hal_srng_params srng_params;
  617. unsigned long addr_offset, dev_base_paddr;
  618. /* IPA TCL_DATA Alternative Ring - HAL_SRNG_SW2TCL2 */
  619. hal_srng = (struct hal_srng *)
  620. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng;
  621. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  622. hal_srng_to_hal_ring_handle(hal_srng),
  623. &srng_params);
  624. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr =
  625. srng_params.ring_base_paddr;
  626. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr =
  627. srng_params.ring_base_vaddr;
  628. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size =
  629. (srng_params.num_entries * srng_params.entry_size) << 2;
  630. /*
  631. * For the register backed memory addresses, use the scn->mem_pa to
  632. * calculate the physical address of the shadow registers
  633. */
  634. dev_base_paddr =
  635. (unsigned long)
  636. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  637. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  638. (unsigned long)(hal_soc->dev_base_addr);
  639. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr =
  640. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  641. dp_info("IPA TCL_DATA Alt Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  642. (unsigned int)addr_offset,
  643. (unsigned int)dev_base_paddr,
  644. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr),
  645. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  646. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  647. srng_params.num_entries,
  648. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  649. /* IPA TX Alternative COMP Ring - HAL_SRNG_WBM2SW4_RELEASE */
  650. hal_srng = (struct hal_srng *)
  651. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  652. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  653. hal_srng_to_hal_ring_handle(hal_srng),
  654. &srng_params);
  655. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr =
  656. srng_params.ring_base_paddr;
  657. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr =
  658. srng_params.ring_base_vaddr;
  659. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size =
  660. (srng_params.num_entries * srng_params.entry_size) << 2;
  661. soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr =
  662. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  663. hal_srng_to_hal_ring_handle(hal_srng));
  664. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  665. (unsigned long)(hal_soc->dev_base_addr);
  666. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr =
  667. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  668. dp_info("IPA TX Alt COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  669. (unsigned int)addr_offset,
  670. (unsigned int)dev_base_paddr,
  671. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr),
  672. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  673. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  674. srng_params.num_entries,
  675. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  676. }
  677. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  678. {
  679. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  680. uint32_t rx_ready_doorbell_dmaaddr;
  681. uint32_t tx_comp_doorbell_dmaaddr;
  682. struct dp_soc *soc = pdev->soc;
  683. int ret = 0;
  684. if (ipa_res->is_db_ddr_mapped)
  685. ipa_res->tx_comp_doorbell_vaddr =
  686. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  687. else
  688. ipa_res->tx_comp_doorbell_vaddr =
  689. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  690. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  691. ret = pld_smmu_map(soc->osdev->dev,
  692. ipa_res->tx_comp_doorbell_paddr,
  693. &tx_comp_doorbell_dmaaddr,
  694. sizeof(uint32_t));
  695. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  696. qdf_assert_always(!ret);
  697. ret = pld_smmu_map(soc->osdev->dev,
  698. ipa_res->rx_ready_doorbell_paddr,
  699. &rx_ready_doorbell_dmaaddr,
  700. sizeof(uint32_t));
  701. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  702. qdf_assert_always(!ret);
  703. }
  704. /* Setup for alternative TX pipe */
  705. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  706. return;
  707. if (ipa_res->is_db_ddr_mapped)
  708. ipa_res->tx_alt_comp_doorbell_vaddr =
  709. phys_to_virt(ipa_res->tx_alt_comp_doorbell_paddr);
  710. else
  711. ipa_res->tx_alt_comp_doorbell_vaddr =
  712. ioremap(ipa_res->tx_alt_comp_doorbell_paddr, 4);
  713. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  714. ret = pld_smmu_map(soc->osdev->dev,
  715. ipa_res->tx_alt_comp_doorbell_paddr,
  716. &tx_comp_doorbell_dmaaddr,
  717. sizeof(uint32_t));
  718. ipa_res->tx_alt_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  719. qdf_assert_always(!ret);
  720. }
  721. }
  722. static void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  723. {
  724. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  725. struct dp_soc *soc = pdev->soc;
  726. int ret = 0;
  727. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  728. return;
  729. /* Unmap must be in reverse order of map */
  730. if (ipa_res->tx_alt_comp_doorbell_paddr) {
  731. ret = pld_smmu_unmap(soc->osdev->dev,
  732. ipa_res->tx_alt_comp_doorbell_paddr,
  733. sizeof(uint32_t));
  734. qdf_assert_always(!ret);
  735. }
  736. ret = pld_smmu_unmap(soc->osdev->dev,
  737. ipa_res->rx_ready_doorbell_paddr,
  738. sizeof(uint32_t));
  739. qdf_assert_always(!ret);
  740. ret = pld_smmu_unmap(soc->osdev->dev,
  741. ipa_res->tx_comp_doorbell_paddr,
  742. sizeof(uint32_t));
  743. qdf_assert_always(!ret);
  744. }
  745. static QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  746. struct dp_pdev *pdev,
  747. bool create, const char *func,
  748. uint32_t line)
  749. {
  750. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  751. struct ipa_dp_tx_rsc *rsc;
  752. uint32_t tx_buffer_cnt;
  753. uint32_t buf_len;
  754. qdf_nbuf_t nbuf;
  755. uint32_t index;
  756. if (!ipa_is_ready()) {
  757. dp_info("IPA is not READY");
  758. return QDF_STATUS_SUCCESS;
  759. }
  760. rsc = &soc->ipa_uc_tx_rsc_alt;
  761. tx_buffer_cnt = rsc->alloc_tx_buf_cnt;
  762. for (index = 0; index < tx_buffer_cnt; index++) {
  763. nbuf = (qdf_nbuf_t)rsc->tx_buf_pool_vaddr_unaligned[index];
  764. if (!nbuf)
  765. continue;
  766. buf_len = qdf_nbuf_get_data_len(nbuf);
  767. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  768. create, func, line);
  769. }
  770. return ret;
  771. }
  772. static void dp_ipa_wdi_tx_alt_pipe_params(struct dp_soc *soc,
  773. struct dp_ipa_resources *ipa_res,
  774. qdf_ipa_wdi_pipe_setup_info_t *tx)
  775. {
  776. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS1;
  777. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  778. qdf_mem_get_dma_addr(soc->osdev,
  779. &ipa_res->tx_alt_comp_ring.mem_info);
  780. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  781. qdf_mem_get_dma_size(soc->osdev,
  782. &ipa_res->tx_alt_comp_ring.mem_info);
  783. /* WBM Tail Pointer Address */
  784. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  785. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  786. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  787. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  788. qdf_mem_get_dma_addr(soc->osdev,
  789. &ipa_res->tx_alt_ring.mem_info);
  790. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  791. qdf_mem_get_dma_size(soc->osdev,
  792. &ipa_res->tx_alt_ring.mem_info);
  793. /* TCL Head Pointer Address */
  794. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  795. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  796. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  797. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  798. ipa_res->tx_alt_ring_num_alloc_buffer;
  799. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  800. dp_ipa_setup_tx_params_bank_id(soc, tx);
  801. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  802. dp_ipa_setup_tx_alt_params_pmac_id(soc, tx);
  803. }
  804. static void
  805. dp_ipa_wdi_tx_alt_pipe_smmu_params(struct dp_soc *soc,
  806. struct dp_ipa_resources *ipa_res,
  807. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  808. {
  809. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) = IPA_CLIENT_WLAN2_CONS1;
  810. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  811. &ipa_res->tx_alt_comp_ring.sgtable,
  812. sizeof(sgtable_t));
  813. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  814. qdf_mem_get_dma_size(soc->osdev,
  815. &ipa_res->tx_alt_comp_ring.mem_info);
  816. /* WBM Tail Pointer Address */
  817. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  818. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  819. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  820. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  821. &ipa_res->tx_alt_ring.sgtable,
  822. sizeof(sgtable_t));
  823. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  824. qdf_mem_get_dma_size(soc->osdev,
  825. &ipa_res->tx_alt_ring.mem_info);
  826. /* TCL Head Pointer Address */
  827. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  828. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  829. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  830. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  831. ipa_res->tx_alt_ring_num_alloc_buffer;
  832. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  833. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  834. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  835. dp_ipa_setup_tx_alt_smmu_params_pmac_id(soc, tx_smmu);
  836. }
  837. static void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc,
  838. struct dp_ipa_resources *res,
  839. qdf_ipa_wdi_conn_in_params_t *in)
  840. {
  841. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu = NULL;
  842. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  843. qdf_ipa_ep_cfg_t *tx_cfg;
  844. QDF_IPA_WDI_CONN_IN_PARAMS_IS_TX1_USED(in) = true;
  845. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  846. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE_SMMU(in);
  847. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  848. dp_ipa_wdi_tx_alt_pipe_smmu_params(soc, res, tx_smmu);
  849. } else {
  850. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE(in);
  851. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx);
  852. dp_ipa_wdi_tx_alt_pipe_params(soc, res, tx);
  853. }
  854. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  855. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  856. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  857. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  858. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  859. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  860. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  861. }
  862. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  863. qdf_ipa_wdi_conn_out_params_t *out)
  864. {
  865. res->tx_comp_doorbell_paddr =
  866. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  867. res->rx_ready_doorbell_paddr =
  868. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  869. res->tx_alt_comp_doorbell_paddr =
  870. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_ALT_DB_PA(out);
  871. }
  872. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  873. uint8_t session_id)
  874. {
  875. bool is_2g_iface = session_id & IPA_SESSION_ID_SHIFT;
  876. session_id = session_id >> IPA_SESSION_ID_SHIFT;
  877. dp_debug("session_id %u is_2g_iface %d", session_id, is_2g_iface);
  878. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  879. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_TX1_USED(in) = is_2g_iface;
  880. }
  881. static void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  882. struct dp_ipa_resources *res)
  883. {
  884. struct hal_srng *wbm_srng;
  885. /* Init first TX comp ring */
  886. wbm_srng = (struct hal_srng *)
  887. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  888. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  889. res->tx_comp_doorbell_vaddr);
  890. /* Init the alternate TX comp ring */
  891. if (!res->tx_alt_comp_doorbell_paddr)
  892. return;
  893. wbm_srng = (struct hal_srng *)
  894. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  895. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  896. res->tx_alt_comp_doorbell_vaddr);
  897. }
  898. static void
  899. dp_ipa_tx_comp_ring_update_hp_addr(struct dp_soc *soc,
  900. struct dp_ipa_resources *res)
  901. {
  902. hal_ring_handle_t wbm_srng;
  903. /* Ring doorbell to WBM2IPA ring with current HW HP value */
  904. wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  905. hal_srng_dst_update_hp_addr(soc->hal_soc, wbm_srng);
  906. if (!res->tx_alt_comp_doorbell_paddr)
  907. return;
  908. wbm_srng = soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  909. hal_srng_dst_update_hp_addr(soc->hal_soc, wbm_srng);
  910. }
  911. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  912. struct dp_ipa_resources *ipa_res)
  913. {
  914. struct hal_srng *wbm_srng;
  915. wbm_srng = (struct hal_srng *)
  916. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  917. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  918. ipa_res->tx_comp_doorbell_paddr);
  919. dp_info("paddr %pK vaddr %pK",
  920. (void *)ipa_res->tx_comp_doorbell_paddr,
  921. (void *)ipa_res->tx_comp_doorbell_vaddr);
  922. /* Setup for alternative TX comp ring */
  923. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  924. return;
  925. wbm_srng = (struct hal_srng *)
  926. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  927. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  928. ipa_res->tx_alt_comp_doorbell_paddr);
  929. dp_info("paddr %pK vaddr %pK",
  930. (void *)ipa_res->tx_alt_comp_doorbell_paddr,
  931. (void *)ipa_res->tx_alt_comp_doorbell_vaddr);
  932. }
  933. #ifdef IPA_SET_RESET_TX_DB_PA
  934. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  935. struct dp_ipa_resources *ipa_res)
  936. {
  937. hal_ring_handle_t wbm_srng;
  938. qdf_dma_addr_t hp_addr;
  939. wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  940. if (!wbm_srng)
  941. return QDF_STATUS_E_FAILURE;
  942. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  943. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  944. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  945. /* Reset alternative TX comp ring */
  946. wbm_srng = soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  947. if (!wbm_srng)
  948. return QDF_STATUS_E_FAILURE;
  949. hp_addr = soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr;
  950. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  951. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  952. return QDF_STATUS_SUCCESS;
  953. }
  954. #endif /* IPA_SET_RESET_TX_DB_PA */
  955. #else /* !IPA_WDI3_TX_TWO_PIPES */
  956. static inline
  957. void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  958. {
  959. }
  960. static inline void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  961. {
  962. }
  963. static inline int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  964. {
  965. return 0;
  966. }
  967. static inline QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  968. {
  969. return QDF_STATUS_SUCCESS;
  970. }
  971. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  972. {
  973. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  974. uint32_t rx_ready_doorbell_dmaaddr;
  975. uint32_t tx_comp_doorbell_dmaaddr;
  976. struct dp_soc *soc = pdev->soc;
  977. int ret = 0;
  978. if (ipa_res->is_db_ddr_mapped)
  979. ipa_res->tx_comp_doorbell_vaddr =
  980. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  981. else
  982. ipa_res->tx_comp_doorbell_vaddr =
  983. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  984. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  985. ret = pld_smmu_map(soc->osdev->dev,
  986. ipa_res->tx_comp_doorbell_paddr,
  987. &tx_comp_doorbell_dmaaddr,
  988. sizeof(uint32_t));
  989. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  990. qdf_assert_always(!ret);
  991. ret = pld_smmu_map(soc->osdev->dev,
  992. ipa_res->rx_ready_doorbell_paddr,
  993. &rx_ready_doorbell_dmaaddr,
  994. sizeof(uint32_t));
  995. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  996. qdf_assert_always(!ret);
  997. }
  998. }
  999. static inline void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  1000. {
  1001. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1002. struct dp_soc *soc = pdev->soc;
  1003. int ret = 0;
  1004. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  1005. return;
  1006. ret = pld_smmu_unmap(soc->osdev->dev,
  1007. ipa_res->rx_ready_doorbell_paddr,
  1008. sizeof(uint32_t));
  1009. qdf_assert_always(!ret);
  1010. ret = pld_smmu_unmap(soc->osdev->dev,
  1011. ipa_res->tx_comp_doorbell_paddr,
  1012. sizeof(uint32_t));
  1013. qdf_assert_always(!ret);
  1014. }
  1015. static inline QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  1016. struct dp_pdev *pdev,
  1017. bool create,
  1018. const char *func,
  1019. uint32_t line)
  1020. {
  1021. return QDF_STATUS_SUCCESS;
  1022. }
  1023. static inline
  1024. void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc, struct dp_ipa_resources *res,
  1025. qdf_ipa_wdi_conn_in_params_t *in)
  1026. {
  1027. }
  1028. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  1029. qdf_ipa_wdi_conn_out_params_t *out)
  1030. {
  1031. res->tx_comp_doorbell_paddr =
  1032. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  1033. res->rx_ready_doorbell_paddr =
  1034. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  1035. }
  1036. #ifdef IPA_WDS_EASYMESH_FEATURE
  1037. /**
  1038. * dp_ipa_setup_iface_session_id() - Pass vdev id to IPA
  1039. * @in: ipa in params
  1040. * @session_id: vdev id
  1041. *
  1042. * Pass Vdev id to IPA, IPA metadata order is changed and vdev id
  1043. * is stored at higher nibble so, no shift is required.
  1044. *
  1045. * Return: none
  1046. */
  1047. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1048. uint8_t session_id)
  1049. {
  1050. if (ucfg_ipa_is_wds_enabled())
  1051. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id);
  1052. else
  1053. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1054. }
  1055. #else
  1056. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1057. uint8_t session_id)
  1058. {
  1059. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1060. }
  1061. #endif
  1062. static inline void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  1063. struct dp_ipa_resources *res)
  1064. {
  1065. struct hal_srng *wbm_srng = (struct hal_srng *)
  1066. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1067. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  1068. res->tx_comp_doorbell_vaddr);
  1069. }
  1070. static void
  1071. dp_ipa_tx_comp_ring_update_hp_addr(struct dp_soc *soc,
  1072. struct dp_ipa_resources *res)
  1073. {
  1074. hal_ring_handle_t wbm_srng;
  1075. /* Ring doorbell to WBM2IPA ring with current HW HP value */
  1076. wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1077. hal_srng_dst_update_hp_addr(soc->hal_soc, wbm_srng);
  1078. }
  1079. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  1080. struct dp_ipa_resources *ipa_res)
  1081. {
  1082. struct hal_srng *wbm_srng = (struct hal_srng *)
  1083. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1084. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  1085. ipa_res->tx_comp_doorbell_paddr);
  1086. dp_info("paddr %pK vaddr %pK",
  1087. (void *)ipa_res->tx_comp_doorbell_paddr,
  1088. (void *)ipa_res->tx_comp_doorbell_vaddr);
  1089. }
  1090. #ifdef IPA_SET_RESET_TX_DB_PA
  1091. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  1092. struct dp_ipa_resources *ipa_res)
  1093. {
  1094. hal_ring_handle_t wbm_srng =
  1095. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1096. qdf_dma_addr_t hp_addr;
  1097. if (!wbm_srng)
  1098. return QDF_STATUS_E_FAILURE;
  1099. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  1100. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  1101. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  1102. return QDF_STATUS_SUCCESS;
  1103. }
  1104. #endif /* IPA_SET_RESET_TX_DB_PA */
  1105. #endif /* IPA_WDI3_TX_TWO_PIPES */
  1106. /**
  1107. * dp_tx_ipa_uc_detach() - Free autonomy TX resources
  1108. * @soc: data path instance
  1109. * @pdev: core txrx pdev context
  1110. *
  1111. * Free allocated TX buffers with WBM SRNG
  1112. *
  1113. * Return: none
  1114. */
  1115. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1116. {
  1117. int idx;
  1118. qdf_nbuf_t nbuf;
  1119. struct dp_ipa_resources *ipa_res;
  1120. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  1121. nbuf = (qdf_nbuf_t)
  1122. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  1123. if (!nbuf)
  1124. continue;
  1125. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  1126. qdf_mem_dp_tx_skb_cnt_dec();
  1127. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  1128. qdf_nbuf_free(nbuf);
  1129. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  1130. (void *)NULL;
  1131. }
  1132. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1133. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1134. ipa_res = &pdev->ipa_resource;
  1135. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  1136. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  1137. }
  1138. /**
  1139. * dp_rx_ipa_uc_detach() - free autonomy RX resources
  1140. * @soc: data path instance
  1141. * @pdev: core txrx pdev context
  1142. *
  1143. * This function will detach DP RX into main device context
  1144. * will free DP Rx resources.
  1145. *
  1146. * Return: none
  1147. */
  1148. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1149. {
  1150. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1151. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  1152. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  1153. }
  1154. /**
  1155. * dp_rx_alt_ipa_uc_detach() - free autonomy RX resources
  1156. * @soc: data path instance
  1157. * @pdev: core txrx pdev context
  1158. *
  1159. * This function will detach DP RX into main device context
  1160. * will free DP Rx resources.
  1161. *
  1162. * Return: none
  1163. */
  1164. #ifdef IPA_WDI3_VLAN_SUPPORT
  1165. static void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1166. {
  1167. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1168. if (!wlan_ipa_is_vlan_enabled())
  1169. return;
  1170. qdf_mem_free_sgtable(&ipa_res->rx_alt_rdy_ring.sgtable);
  1171. qdf_mem_free_sgtable(&ipa_res->rx_alt_refill_ring.sgtable);
  1172. }
  1173. #else
  1174. static inline
  1175. void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1176. { }
  1177. #endif
  1178. /**
  1179. * dp_ipa_opt_wifi_dp_cleanup() - Cleanup ipa opt wifi dp filter setup
  1180. * @soc: data path instance
  1181. * @pdev: core txrx pdev context
  1182. *
  1183. * This function will cleanup filter setup for optional wifi dp.
  1184. *
  1185. * Return: none
  1186. */
  1187. #ifdef IPA_OPT_WIFI_DP
  1188. static void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1189. {
  1190. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1191. struct hif_softc *hif = (struct hif_softc *)(hal_soc->hif_handle);
  1192. int count = qdf_atomic_read(&hif->opt_wifi_dp_rtpm_cnt);
  1193. int i;
  1194. for (i = count; i > 0; i--) {
  1195. dp_info("opt_dp: cleanup call pcie link down");
  1196. dp_ipa_pcie_link_down((struct cdp_soc_t *)soc);
  1197. }
  1198. }
  1199. #else
  1200. static inline
  1201. void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1202. {
  1203. }
  1204. #endif
  1205. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1206. {
  1207. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1208. return QDF_STATUS_SUCCESS;
  1209. /* TX resource detach */
  1210. dp_tx_ipa_uc_detach(soc, pdev);
  1211. /* Cleanup 2nd TX pipe resources */
  1212. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1213. /* RX resource detach */
  1214. dp_rx_ipa_uc_detach(soc, pdev);
  1215. /* Cleanup 2nd RX pipe resources */
  1216. dp_rx_alt_ipa_uc_detach(soc, pdev);
  1217. dp_ipa_opt_wifi_dp_cleanup(soc, pdev);
  1218. return QDF_STATUS_SUCCESS; /* success */
  1219. }
  1220. /**
  1221. * dp_tx_ipa_uc_attach() - Allocate autonomy TX resources
  1222. * @soc: data path instance
  1223. * @pdev: Physical device handle
  1224. *
  1225. * Allocate TX buffer from non-cacheable memory
  1226. * Attach allocated TX buffers with WBM SRNG
  1227. *
  1228. * Return: int
  1229. */
  1230. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1231. {
  1232. uint32_t tx_buffer_count;
  1233. uint32_t ring_base_align = 8;
  1234. qdf_dma_addr_t buffer_paddr;
  1235. struct hal_srng *wbm_srng = (struct hal_srng *)
  1236. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1237. struct hal_srng_params srng_params;
  1238. void *ring_entry;
  1239. int num_entries;
  1240. qdf_nbuf_t nbuf;
  1241. int retval = QDF_STATUS_SUCCESS;
  1242. int max_alloc_count = 0;
  1243. uint32_t wbm_bm_id;
  1244. /*
  1245. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  1246. * unsigned int uc_tx_buf_sz =
  1247. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  1248. */
  1249. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  1250. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  1251. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  1252. IPA_TCL_DATA_RING_IDX);
  1253. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  1254. &srng_params);
  1255. num_entries = srng_params.num_entries;
  1256. max_alloc_count =
  1257. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  1258. if (max_alloc_count <= 0) {
  1259. dp_err("incorrect value for buffer count %u", max_alloc_count);
  1260. return -EINVAL;
  1261. }
  1262. dp_info("requested %d buffers to be posted to wbm ring",
  1263. max_alloc_count);
  1264. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  1265. qdf_mem_malloc(num_entries *
  1266. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  1267. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  1268. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  1269. return -ENOMEM;
  1270. }
  1271. hal_srng_access_start_unlocked(soc->hal_soc,
  1272. hal_srng_to_hal_ring_handle(wbm_srng));
  1273. /*
  1274. * Allocate Tx buffers as many as possible.
  1275. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  1276. * Populate Tx buffers into WBM2IPA ring
  1277. * This initial buffer population will simulate H/W as source ring,
  1278. * and update HP
  1279. */
  1280. for (tx_buffer_count = 0;
  1281. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  1282. nbuf = qdf_nbuf_frag_alloc(soc->osdev, alloc_size, 0,
  1283. 256, FALSE);
  1284. if (!nbuf)
  1285. break;
  1286. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  1287. hal_srng_to_hal_ring_handle(wbm_srng));
  1288. if (!ring_entry) {
  1289. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1290. "%s: Failed to get WBM ring entry",
  1291. __func__);
  1292. qdf_nbuf_free(nbuf);
  1293. break;
  1294. }
  1295. retval = qdf_nbuf_map_single(soc->osdev, nbuf,
  1296. QDF_DMA_BIDIRECTIONAL);
  1297. if (qdf_unlikely(retval != QDF_STATUS_SUCCESS)) {
  1298. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1299. "%s: nbuf map failed", __func__);
  1300. qdf_nbuf_free(nbuf);
  1301. retval = -EFAULT;
  1302. break;
  1303. }
  1304. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1305. qdf_mem_dp_tx_skb_cnt_inc();
  1306. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  1307. /*
  1308. * TODO - KIWI code can directly call the be handler
  1309. * instead of hal soc ops.
  1310. */
  1311. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  1312. buffer_paddr, 0, wbm_bm_id);
  1313. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  1314. = (void *)nbuf;
  1315. }
  1316. hal_srng_access_end_unlocked(soc->hal_soc,
  1317. hal_srng_to_hal_ring_handle(wbm_srng));
  1318. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  1319. if (tx_buffer_count) {
  1320. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  1321. } else {
  1322. dp_err("No IPA WDI TX buffer allocated!");
  1323. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1324. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1325. retval = -ENOMEM;
  1326. }
  1327. return retval;
  1328. }
  1329. /**
  1330. * dp_rx_ipa_uc_attach() - Allocate autonomy RX resources
  1331. * @soc: data path instance
  1332. * @pdev: core txrx pdev context
  1333. *
  1334. * This function will attach a DP RX instance into the main
  1335. * device (SOC) context.
  1336. *
  1337. * Return: QDF_STATUS_SUCCESS: success
  1338. * QDF_STATUS_E_RESOURCES: Error return
  1339. */
  1340. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1341. {
  1342. return QDF_STATUS_SUCCESS;
  1343. }
  1344. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1345. {
  1346. int error;
  1347. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1348. return QDF_STATUS_SUCCESS;
  1349. /* TX resource attach */
  1350. error = dp_tx_ipa_uc_attach(soc, pdev);
  1351. if (error) {
  1352. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1353. "%s: DP IPA UC TX attach fail code %d",
  1354. __func__, error);
  1355. if (error == -EFAULT)
  1356. dp_tx_ipa_uc_detach(soc, pdev);
  1357. return error;
  1358. }
  1359. /* Setup 2nd TX pipe */
  1360. error = dp_ipa_tx_alt_pool_attach(soc);
  1361. if (error) {
  1362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1363. "%s: DP IPA TX pool2 attach fail code %d",
  1364. __func__, error);
  1365. dp_tx_ipa_uc_detach(soc, pdev);
  1366. return error;
  1367. }
  1368. /* RX resource attach */
  1369. error = dp_rx_ipa_uc_attach(soc, pdev);
  1370. if (error) {
  1371. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1372. "%s: DP IPA UC RX attach fail code %d",
  1373. __func__, error);
  1374. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1375. dp_tx_ipa_uc_detach(soc, pdev);
  1376. return error;
  1377. }
  1378. return QDF_STATUS_SUCCESS; /* success */
  1379. }
  1380. #ifdef IPA_WDI3_VLAN_SUPPORT
  1381. /**
  1382. * dp_ipa_rx_alt_ring_resource_setup() - setup IPA 2nd RX ring resources
  1383. * @soc: data path SoC handle
  1384. * @pdev: data path pdev handle
  1385. *
  1386. * Return: none
  1387. */
  1388. static
  1389. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1390. {
  1391. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1392. struct hal_srng *hal_srng;
  1393. struct hal_srng_params srng_params;
  1394. unsigned long addr_offset, dev_base_paddr;
  1395. qdf_dma_addr_t hp_addr;
  1396. if (!wlan_ipa_is_vlan_enabled())
  1397. return;
  1398. dev_base_paddr =
  1399. (unsigned long)
  1400. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1401. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW3 */
  1402. hal_srng = (struct hal_srng *)
  1403. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1404. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1405. hal_srng_to_hal_ring_handle(hal_srng),
  1406. &srng_params);
  1407. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr =
  1408. srng_params.ring_base_paddr;
  1409. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr =
  1410. srng_params.ring_base_vaddr;
  1411. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size =
  1412. (srng_params.num_entries * srng_params.entry_size) << 2;
  1413. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1414. (unsigned long)(hal_soc->dev_base_addr);
  1415. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr =
  1416. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1417. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1418. (unsigned int)addr_offset,
  1419. (unsigned int)dev_base_paddr,
  1420. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr),
  1421. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1422. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1423. srng_params.num_entries,
  1424. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1425. hal_srng = (struct hal_srng *)
  1426. pdev->rx_refill_buf_ring3.hal_srng;
  1427. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1428. hal_srng_to_hal_ring_handle(hal_srng),
  1429. &srng_params);
  1430. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr =
  1431. srng_params.ring_base_paddr;
  1432. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr =
  1433. srng_params.ring_base_vaddr;
  1434. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size =
  1435. (srng_params.num_entries * srng_params.entry_size) << 2;
  1436. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1437. hal_srng_to_hal_ring_handle(hal_srng));
  1438. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr =
  1439. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1440. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1441. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr),
  1442. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1443. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1444. srng_params.num_entries,
  1445. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1446. }
  1447. #else
  1448. static inline
  1449. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1450. { }
  1451. #endif
  1452. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1453. struct dp_pdev *pdev)
  1454. {
  1455. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1456. struct hal_srng *hal_srng;
  1457. struct hal_srng_params srng_params;
  1458. qdf_dma_addr_t hp_addr;
  1459. unsigned long addr_offset, dev_base_paddr;
  1460. uint32_t ix0;
  1461. uint8_t ix0_map[8];
  1462. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1463. return QDF_STATUS_SUCCESS;
  1464. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  1465. hal_srng = (struct hal_srng *)
  1466. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1467. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1468. hal_srng_to_hal_ring_handle(hal_srng),
  1469. &srng_params);
  1470. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1471. srng_params.ring_base_paddr;
  1472. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1473. srng_params.ring_base_vaddr;
  1474. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1475. (srng_params.num_entries * srng_params.entry_size) << 2;
  1476. /*
  1477. * For the register backed memory addresses, use the scn->mem_pa to
  1478. * calculate the physical address of the shadow registers
  1479. */
  1480. dev_base_paddr =
  1481. (unsigned long)
  1482. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1483. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  1484. (unsigned long)(hal_soc->dev_base_addr);
  1485. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  1486. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1487. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1488. (unsigned int)addr_offset,
  1489. (unsigned int)dev_base_paddr,
  1490. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  1491. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1492. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1493. srng_params.num_entries,
  1494. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1495. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  1496. hal_srng = (struct hal_srng *)
  1497. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1498. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1499. hal_srng_to_hal_ring_handle(hal_srng),
  1500. &srng_params);
  1501. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1502. srng_params.ring_base_paddr;
  1503. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1504. srng_params.ring_base_vaddr;
  1505. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1506. (srng_params.num_entries * srng_params.entry_size) << 2;
  1507. soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr =
  1508. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1509. hal_srng_to_hal_ring_handle(hal_srng));
  1510. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1511. (unsigned long)(hal_soc->dev_base_addr);
  1512. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  1513. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1514. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  1515. (unsigned int)addr_offset,
  1516. (unsigned int)dev_base_paddr,
  1517. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  1518. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1519. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1520. srng_params.num_entries,
  1521. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1522. dp_ipa_tx_alt_ring_resource_setup(soc);
  1523. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1524. hal_srng = (struct hal_srng *)
  1525. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1526. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1527. hal_srng_to_hal_ring_handle(hal_srng),
  1528. &srng_params);
  1529. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1530. srng_params.ring_base_paddr;
  1531. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1532. srng_params.ring_base_vaddr;
  1533. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1534. (srng_params.num_entries * srng_params.entry_size) << 2;
  1535. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1536. (unsigned long)(hal_soc->dev_base_addr);
  1537. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  1538. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1539. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1540. (unsigned int)addr_offset,
  1541. (unsigned int)dev_base_paddr,
  1542. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  1543. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1544. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1545. srng_params.num_entries,
  1546. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1547. hal_srng = (struct hal_srng *)
  1548. pdev->rx_refill_buf_ring2.hal_srng;
  1549. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1550. hal_srng_to_hal_ring_handle(hal_srng),
  1551. &srng_params);
  1552. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1553. srng_params.ring_base_paddr;
  1554. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1555. srng_params.ring_base_vaddr;
  1556. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1557. (srng_params.num_entries * srng_params.entry_size) << 2;
  1558. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1559. hal_srng_to_hal_ring_handle(hal_srng));
  1560. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  1561. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1562. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1563. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  1564. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1565. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1566. srng_params.num_entries,
  1567. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1568. /*
  1569. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  1570. * DESTINATION_RING_CTRL_IX_0.
  1571. */
  1572. ix0_map[0] = REO_REMAP_SW1;
  1573. ix0_map[1] = REO_REMAP_SW1;
  1574. ix0_map[2] = REO_REMAP_SW2;
  1575. ix0_map[3] = REO_REMAP_SW3;
  1576. ix0_map[4] = REO_REMAP_SW2;
  1577. ix0_map[5] = REO_REMAP_RELEASE;
  1578. ix0_map[6] = REO_REMAP_FW;
  1579. ix0_map[7] = REO_REMAP_FW;
  1580. dp_ipa_opt_dp_ixo_remap(ix0_map);
  1581. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1582. ix0_map);
  1583. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  1584. dp_ipa_rx_alt_ring_resource_setup(soc, pdev);
  1585. return 0;
  1586. }
  1587. #ifdef IPA_WDI3_VLAN_SUPPORT
  1588. /**
  1589. * dp_ipa_rx_alt_ring_get_resource() - get IPA 2nd RX ring resources
  1590. * @pdev: data path pdev handle
  1591. *
  1592. * Return: Success if resourece is found
  1593. */
  1594. static QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1595. {
  1596. struct dp_soc *soc = pdev->soc;
  1597. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1598. if (!wlan_ipa_is_vlan_enabled())
  1599. return QDF_STATUS_SUCCESS;
  1600. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_alt_rdy_ring,
  1601. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1602. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1603. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1604. dp_ipa_get_shared_mem_info(
  1605. soc->osdev, &ipa_res->rx_alt_refill_ring,
  1606. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1607. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1608. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1609. if (!qdf_mem_get_dma_addr(soc->osdev,
  1610. &ipa_res->rx_alt_rdy_ring.mem_info) ||
  1611. !qdf_mem_get_dma_addr(soc->osdev,
  1612. &ipa_res->rx_alt_refill_ring.mem_info))
  1613. return QDF_STATUS_E_FAILURE;
  1614. return QDF_STATUS_SUCCESS;
  1615. }
  1616. #else
  1617. static inline QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1618. {
  1619. return QDF_STATUS_SUCCESS;
  1620. }
  1621. #endif
  1622. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1623. {
  1624. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1625. struct dp_pdev *pdev =
  1626. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1627. struct dp_ipa_resources *ipa_res;
  1628. if (!pdev) {
  1629. dp_err("Invalid instance");
  1630. return QDF_STATUS_E_FAILURE;
  1631. }
  1632. ipa_res = &pdev->ipa_resource;
  1633. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1634. return QDF_STATUS_SUCCESS;
  1635. ipa_res->tx_num_alloc_buffer =
  1636. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  1637. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  1638. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1639. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1640. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1641. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  1642. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1643. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1644. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1645. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  1646. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1647. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1648. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1649. dp_ipa_get_shared_mem_info(
  1650. soc->osdev, &ipa_res->rx_refill_ring,
  1651. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1652. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1653. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1654. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  1655. !qdf_mem_get_dma_addr(soc->osdev,
  1656. &ipa_res->tx_comp_ring.mem_info) ||
  1657. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  1658. !qdf_mem_get_dma_addr(soc->osdev,
  1659. &ipa_res->rx_refill_ring.mem_info))
  1660. return QDF_STATUS_E_FAILURE;
  1661. if (dp_ipa_tx_alt_ring_get_resource(pdev))
  1662. return QDF_STATUS_E_FAILURE;
  1663. if (dp_ipa_rx_alt_ring_get_resource(pdev))
  1664. return QDF_STATUS_E_FAILURE;
  1665. return QDF_STATUS_SUCCESS;
  1666. }
  1667. #ifdef IPA_SET_RESET_TX_DB_PA
  1668. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res)
  1669. #else
  1670. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res) \
  1671. dp_ipa_set_tx_doorbell_paddr(soc, ipa_res)
  1672. #endif
  1673. #ifdef IPA_WDI3_VLAN_SUPPORT
  1674. /**
  1675. * dp_ipa_map_rx_alt_ring_doorbell_paddr() - Map 2nd rx ring doorbell paddr
  1676. * @pdev: data path pdev handle
  1677. *
  1678. * Return: none
  1679. */
  1680. static void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1681. {
  1682. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1683. uint32_t rx_ready_doorbell_dmaaddr;
  1684. struct dp_soc *soc = pdev->soc;
  1685. struct hal_srng *reo_srng = (struct hal_srng *)
  1686. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1687. int ret = 0;
  1688. if (!wlan_ipa_is_vlan_enabled())
  1689. return;
  1690. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1691. ret = pld_smmu_map(soc->osdev->dev,
  1692. ipa_res->rx_alt_ready_doorbell_paddr,
  1693. &rx_ready_doorbell_dmaaddr,
  1694. sizeof(uint32_t));
  1695. ipa_res->rx_alt_ready_doorbell_paddr =
  1696. rx_ready_doorbell_dmaaddr;
  1697. qdf_assert_always(!ret);
  1698. }
  1699. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1700. ipa_res->rx_alt_ready_doorbell_paddr);
  1701. }
  1702. /**
  1703. * dp_ipa_unmap_rx_alt_ring_doorbell_paddr() - Unmap 2nd rx ring doorbell paddr
  1704. * @pdev: data path pdev handle
  1705. *
  1706. * Return: none
  1707. */
  1708. static void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1709. {
  1710. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1711. struct dp_soc *soc = pdev->soc;
  1712. int ret = 0;
  1713. if (!wlan_ipa_is_vlan_enabled())
  1714. return;
  1715. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  1716. return;
  1717. ret = pld_smmu_unmap(soc->osdev->dev,
  1718. ipa_res->rx_alt_ready_doorbell_paddr,
  1719. sizeof(uint32_t));
  1720. qdf_assert_always(!ret);
  1721. }
  1722. #else
  1723. static inline void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1724. { }
  1725. static inline void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1726. { }
  1727. #endif
  1728. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1729. {
  1730. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1731. struct dp_pdev *pdev =
  1732. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1733. struct dp_ipa_resources *ipa_res;
  1734. struct hal_srng *reo_srng = (struct hal_srng *)
  1735. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1736. if (!pdev) {
  1737. dp_err("Invalid instance");
  1738. return QDF_STATUS_E_FAILURE;
  1739. }
  1740. ipa_res = &pdev->ipa_resource;
  1741. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1742. return QDF_STATUS_SUCCESS;
  1743. dp_ipa_map_ring_doorbell_paddr(pdev);
  1744. dp_ipa_map_rx_alt_ring_doorbell_paddr(pdev);
  1745. DP_IPA_SET_TX_DB_PADDR(soc, ipa_res);
  1746. /*
  1747. * For RX, REO module on Napier/Hastings does reordering on incoming
  1748. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  1749. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  1750. * to IPA.
  1751. * Set the doorbell addr for the REO ring.
  1752. */
  1753. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1754. ipa_res->rx_ready_doorbell_paddr);
  1755. return QDF_STATUS_SUCCESS;
  1756. }
  1757. QDF_STATUS dp_ipa_iounmap_doorbell_vaddr(struct cdp_soc_t *soc_hdl,
  1758. uint8_t pdev_id)
  1759. {
  1760. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1761. struct dp_pdev *pdev =
  1762. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1763. struct dp_ipa_resources *ipa_res;
  1764. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1765. return QDF_STATUS_SUCCESS;
  1766. if (!pdev) {
  1767. dp_err("Invalid instance");
  1768. return QDF_STATUS_E_FAILURE;
  1769. }
  1770. ipa_res = &pdev->ipa_resource;
  1771. if (!ipa_res->is_db_ddr_mapped)
  1772. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  1773. return QDF_STATUS_SUCCESS;
  1774. }
  1775. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1776. uint8_t *op_msg)
  1777. {
  1778. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1779. struct dp_pdev *pdev =
  1780. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1781. if (!pdev) {
  1782. dp_err("Invalid instance");
  1783. return QDF_STATUS_E_FAILURE;
  1784. }
  1785. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1786. return QDF_STATUS_SUCCESS;
  1787. if (pdev->ipa_uc_op_cb) {
  1788. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  1789. } else {
  1790. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1791. "%s: IPA callback function is not registered", __func__);
  1792. qdf_mem_free(op_msg);
  1793. return QDF_STATUS_E_FAILURE;
  1794. }
  1795. return QDF_STATUS_SUCCESS;
  1796. }
  1797. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1798. ipa_uc_op_cb_type op_cb,
  1799. void *usr_ctxt)
  1800. {
  1801. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1802. struct dp_pdev *pdev =
  1803. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1804. if (!pdev) {
  1805. dp_err("Invalid instance");
  1806. return QDF_STATUS_E_FAILURE;
  1807. }
  1808. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1809. return QDF_STATUS_SUCCESS;
  1810. pdev->ipa_uc_op_cb = op_cb;
  1811. pdev->usr_ctxt = usr_ctxt;
  1812. return QDF_STATUS_SUCCESS;
  1813. }
  1814. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1815. {
  1816. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1817. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1818. if (!pdev) {
  1819. dp_err("Invalid instance");
  1820. return;
  1821. }
  1822. dp_debug("Deregister OP handler callback");
  1823. pdev->ipa_uc_op_cb = NULL;
  1824. pdev->usr_ctxt = NULL;
  1825. }
  1826. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1827. {
  1828. /* TBD */
  1829. return QDF_STATUS_SUCCESS;
  1830. }
  1831. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1832. qdf_nbuf_t skb)
  1833. {
  1834. qdf_nbuf_t ret;
  1835. /* Terminate the (single-element) list of tx frames */
  1836. qdf_nbuf_set_next(skb, NULL);
  1837. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  1838. if (ret) {
  1839. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1840. "%s: Failed to tx", __func__);
  1841. return ret;
  1842. }
  1843. return NULL;
  1844. }
  1845. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  1846. /**
  1847. * dp_ipa_is_target_ready() - check if target is ready or not
  1848. * @soc: datapath soc handle
  1849. *
  1850. * Return: true if target is ready
  1851. */
  1852. static inline
  1853. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1854. {
  1855. if (hif_get_target_status(soc->hif_handle) == TARGET_STATUS_RESET)
  1856. return false;
  1857. else
  1858. return true;
  1859. }
  1860. /**
  1861. * dp_ipa_update_txr_db_status() - Indicate transfer ring DB is SMMU mapped or not
  1862. * @dev: Pointer to device
  1863. * @txrx_smmu: WDI TX/RX configuration
  1864. *
  1865. * Return: None
  1866. */
  1867. static inline
  1868. void dp_ipa_update_txr_db_status(struct device *dev,
  1869. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1870. {
  1871. int pcie_slot = pld_get_pci_slot(dev);
  1872. if (pcie_slot)
  1873. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1874. else
  1875. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1876. }
  1877. /**
  1878. * dp_ipa_update_evt_db_status() - Indicate evt ring DB is SMMU mapped or not
  1879. * @dev: Pointer to device
  1880. * @txrx_smmu: WDI TX/RX configuration
  1881. *
  1882. * Return: None
  1883. */
  1884. static inline
  1885. void dp_ipa_update_evt_db_status(struct device *dev,
  1886. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1887. {
  1888. int pcie_slot = pld_get_pci_slot(dev);
  1889. if (pcie_slot)
  1890. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1891. else
  1892. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1893. }
  1894. #else
  1895. static inline
  1896. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1897. {
  1898. return true;
  1899. }
  1900. static inline
  1901. void dp_ipa_update_txr_db_status(struct device *dev,
  1902. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1903. {
  1904. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1905. }
  1906. static inline
  1907. void dp_ipa_update_evt_db_status(struct device *dev,
  1908. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1909. {
  1910. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1911. }
  1912. #endif
  1913. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1914. {
  1915. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1916. struct dp_pdev *pdev =
  1917. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1918. uint32_t ix0;
  1919. uint32_t ix2;
  1920. uint8_t ix_map[8];
  1921. if (!pdev) {
  1922. dp_err("Invalid instance");
  1923. return QDF_STATUS_E_FAILURE;
  1924. }
  1925. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1926. return QDF_STATUS_SUCCESS;
  1927. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1928. return QDF_STATUS_E_AGAIN;
  1929. if (!dp_ipa_is_target_ready(soc))
  1930. return QDF_STATUS_E_AGAIN;
  1931. /* Call HAL API to remap REO rings to REO2IPA ring */
  1932. ix_map[0] = REO_REMAP_SW1;
  1933. ix_map[1] = REO_REMAP_SW4;
  1934. ix_map[2] = REO_REMAP_SW1;
  1935. if (wlan_ipa_is_vlan_enabled())
  1936. ix_map[3] = REO_REMAP_SW3;
  1937. else
  1938. ix_map[3] = REO_REMAP_SW4;
  1939. ix_map[4] = REO_REMAP_SW4;
  1940. ix_map[5] = REO_REMAP_RELEASE;
  1941. ix_map[6] = REO_REMAP_FW;
  1942. ix_map[7] = REO_REMAP_FW;
  1943. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1944. ix_map);
  1945. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1946. ix_map[0] = REO_REMAP_SW4;
  1947. ix_map[1] = REO_REMAP_SW4;
  1948. ix_map[2] = REO_REMAP_SW4;
  1949. ix_map[3] = REO_REMAP_SW4;
  1950. ix_map[4] = REO_REMAP_SW4;
  1951. ix_map[5] = REO_REMAP_SW4;
  1952. ix_map[6] = REO_REMAP_SW4;
  1953. ix_map[7] = REO_REMAP_SW4;
  1954. ix2 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX2,
  1955. ix_map);
  1956. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1957. &ix2, &ix2);
  1958. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  1959. } else {
  1960. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1961. NULL, NULL);
  1962. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1963. }
  1964. return QDF_STATUS_SUCCESS;
  1965. }
  1966. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1967. {
  1968. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1969. struct dp_pdev *pdev =
  1970. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1971. uint8_t ix0_map[8];
  1972. uint32_t ix0;
  1973. uint32_t ix1;
  1974. uint32_t ix2;
  1975. uint32_t ix3;
  1976. if (!pdev) {
  1977. dp_err("Invalid instance");
  1978. return QDF_STATUS_E_FAILURE;
  1979. }
  1980. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1981. return QDF_STATUS_SUCCESS;
  1982. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1983. return QDF_STATUS_E_AGAIN;
  1984. if (!dp_ipa_is_target_ready(soc))
  1985. return QDF_STATUS_E_AGAIN;
  1986. ix0_map[0] = REO_REMAP_SW1;
  1987. ix0_map[1] = REO_REMAP_SW1;
  1988. ix0_map[2] = REO_REMAP_SW2;
  1989. ix0_map[3] = REO_REMAP_SW3;
  1990. ix0_map[4] = REO_REMAP_SW2;
  1991. ix0_map[5] = REO_REMAP_RELEASE;
  1992. ix0_map[6] = REO_REMAP_FW;
  1993. ix0_map[7] = REO_REMAP_FW;
  1994. /* Call HAL API to remap REO rings to REO2IPA ring */
  1995. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1996. ix0_map);
  1997. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1998. dp_reo_remap_config(soc, &ix1, &ix2, &ix3);
  1999. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  2000. &ix2, &ix3);
  2001. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  2002. } else {
  2003. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  2004. NULL, NULL);
  2005. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  2006. }
  2007. return QDF_STATUS_SUCCESS;
  2008. }
  2009. /* This should be configurable per H/W configuration enable status */
  2010. #define L3_HEADER_PADDING 2
  2011. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  2012. defined(CONFIG_IPA_WDI_UNIFIED_API)
  2013. #if !defined(QCA_LL_TX_FLOW_CONTROL_V2) && !defined(QCA_IPA_LL_TX_FLOW_CONTROL)
  2014. static inline void dp_setup_mcc_sys_pipes(
  2015. qdf_ipa_sys_connect_params_t *sys_in,
  2016. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  2017. {
  2018. int i = 0;
  2019. /* Setup MCC sys pipe */
  2020. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  2021. DP_IPA_MAX_IFACE;
  2022. for (i = 0; i < DP_IPA_MAX_IFACE; i++)
  2023. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  2024. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  2025. }
  2026. #else
  2027. static inline void dp_setup_mcc_sys_pipes(
  2028. qdf_ipa_sys_connect_params_t *sys_in,
  2029. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  2030. {
  2031. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  2032. }
  2033. #endif
  2034. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  2035. struct dp_ipa_resources *ipa_res,
  2036. qdf_ipa_wdi_pipe_setup_info_t *tx,
  2037. bool over_gsi)
  2038. {
  2039. if (over_gsi)
  2040. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  2041. else
  2042. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2043. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2044. qdf_mem_get_dma_addr(soc->osdev,
  2045. &ipa_res->tx_comp_ring.mem_info);
  2046. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2047. qdf_mem_get_dma_size(soc->osdev,
  2048. &ipa_res->tx_comp_ring.mem_info);
  2049. /* WBM Tail Pointer Address */
  2050. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2051. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2052. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  2053. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2054. qdf_mem_get_dma_addr(soc->osdev,
  2055. &ipa_res->tx_ring.mem_info);
  2056. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  2057. qdf_mem_get_dma_size(soc->osdev,
  2058. &ipa_res->tx_ring.mem_info);
  2059. /* TCL Head Pointer Address */
  2060. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2061. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2062. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  2063. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2064. ipa_res->tx_num_alloc_buffer;
  2065. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2066. dp_ipa_setup_tx_params_bank_id(soc, tx);
  2067. /* Set Pmac ID, extract pmac_id from pdev_id 0 for TX ring */
  2068. dp_ipa_setup_tx_params_pmac_id(soc, tx);
  2069. }
  2070. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  2071. struct dp_ipa_resources *ipa_res,
  2072. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2073. bool over_gsi)
  2074. {
  2075. if (over_gsi)
  2076. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2077. IPA_CLIENT_WLAN2_PROD;
  2078. else
  2079. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2080. IPA_CLIENT_WLAN1_PROD;
  2081. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2082. qdf_mem_get_dma_addr(soc->osdev,
  2083. &ipa_res->rx_rdy_ring.mem_info);
  2084. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2085. qdf_mem_get_dma_size(soc->osdev,
  2086. &ipa_res->rx_rdy_ring.mem_info);
  2087. /* REO Tail Pointer Address */
  2088. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2089. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2090. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2091. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2092. qdf_mem_get_dma_addr(soc->osdev,
  2093. &ipa_res->rx_refill_ring.mem_info);
  2094. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2095. qdf_mem_get_dma_size(soc->osdev,
  2096. &ipa_res->rx_refill_ring.mem_info);
  2097. /* FW Head Pointer Address */
  2098. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2099. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2100. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2101. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2102. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2103. }
  2104. static void
  2105. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  2106. struct dp_ipa_resources *ipa_res,
  2107. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  2108. bool over_gsi,
  2109. qdf_ipa_wdi_hdl_t hdl)
  2110. {
  2111. if (over_gsi) {
  2112. if (hdl == DP_IPA_HDL_FIRST)
  2113. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2114. IPA_CLIENT_WLAN2_CONS;
  2115. else if (hdl == DP_IPA_HDL_SECOND)
  2116. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2117. IPA_CLIENT_WLAN4_CONS;
  2118. else if (hdl == DP_IPA_HDL_THIRD)
  2119. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2120. IPA_CLIENT_WLAN1_CONS;
  2121. } else {
  2122. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2123. IPA_CLIENT_WLAN1_CONS;
  2124. }
  2125. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  2126. &ipa_res->tx_comp_ring.sgtable,
  2127. sizeof(sgtable_t));
  2128. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  2129. qdf_mem_get_dma_size(soc->osdev,
  2130. &ipa_res->tx_comp_ring.mem_info);
  2131. /* WBM Tail Pointer Address */
  2132. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  2133. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2134. dp_ipa_update_txr_db_status(soc->osdev->dev, tx_smmu);
  2135. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  2136. &ipa_res->tx_ring.sgtable,
  2137. sizeof(sgtable_t));
  2138. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  2139. qdf_mem_get_dma_size(soc->osdev,
  2140. &ipa_res->tx_ring.mem_info);
  2141. /* TCL Head Pointer Address */
  2142. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  2143. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2144. dp_ipa_update_evt_db_status(soc->osdev->dev, tx_smmu);
  2145. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  2146. ipa_res->tx_num_alloc_buffer;
  2147. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  2148. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  2149. /* Set Pmac ID, extract pmac_id from first pdev for TX ring */
  2150. dp_ipa_setup_tx_smmu_params_pmac_id(soc, tx_smmu);
  2151. }
  2152. static void
  2153. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  2154. struct dp_ipa_resources *ipa_res,
  2155. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2156. bool over_gsi,
  2157. qdf_ipa_wdi_hdl_t hdl)
  2158. {
  2159. if (over_gsi) {
  2160. if (hdl == DP_IPA_HDL_FIRST)
  2161. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2162. IPA_CLIENT_WLAN2_PROD;
  2163. else if (hdl == DP_IPA_HDL_SECOND)
  2164. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2165. IPA_CLIENT_WLAN3_PROD;
  2166. else if (hdl == DP_IPA_HDL_THIRD)
  2167. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2168. IPA_CLIENT_WLAN1_PROD;
  2169. } else {
  2170. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2171. IPA_CLIENT_WLAN1_PROD;
  2172. }
  2173. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2174. &ipa_res->rx_rdy_ring.sgtable,
  2175. sizeof(sgtable_t));
  2176. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2177. qdf_mem_get_dma_size(soc->osdev,
  2178. &ipa_res->rx_rdy_ring.mem_info);
  2179. /* REO Tail Pointer Address */
  2180. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2181. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2182. dp_ipa_update_txr_db_status(soc->osdev->dev, rx_smmu);
  2183. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2184. &ipa_res->rx_refill_ring.sgtable,
  2185. sizeof(sgtable_t));
  2186. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2187. qdf_mem_get_dma_size(soc->osdev,
  2188. &ipa_res->rx_refill_ring.mem_info);
  2189. /* FW Head Pointer Address */
  2190. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2191. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2192. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2193. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2194. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2195. }
  2196. #ifdef IPA_WDI3_VLAN_SUPPORT
  2197. /**
  2198. * dp_ipa_wdi_rx_alt_pipe_smmu_params() - Setup 2nd rx pipe smmu params
  2199. * @soc: data path soc handle
  2200. * @ipa_res: ipa resource pointer
  2201. * @rx_smmu: smmu pipe info handle
  2202. * @over_gsi: flag for IPA offload over gsi
  2203. * @hdl: ipa registered handle
  2204. *
  2205. * Return: none
  2206. */
  2207. static void
  2208. dp_ipa_wdi_rx_alt_pipe_smmu_params(struct dp_soc *soc,
  2209. struct dp_ipa_resources *ipa_res,
  2210. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2211. bool over_gsi,
  2212. qdf_ipa_wdi_hdl_t hdl)
  2213. {
  2214. if (!wlan_ipa_is_vlan_enabled())
  2215. return;
  2216. if (over_gsi) {
  2217. if (hdl == DP_IPA_HDL_FIRST)
  2218. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2219. IPA_CLIENT_WLAN2_PROD1;
  2220. else if (hdl == DP_IPA_HDL_SECOND)
  2221. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2222. IPA_CLIENT_WLAN3_PROD1;
  2223. else if (hdl == DP_IPA_HDL_THIRD)
  2224. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx_smmu) =
  2225. IPA_CLIENT_WLAN1_PROD1;
  2226. } else {
  2227. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2228. IPA_CLIENT_WLAN1_PROD;
  2229. }
  2230. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2231. &ipa_res->rx_alt_rdy_ring.sgtable,
  2232. sizeof(sgtable_t));
  2233. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2234. qdf_mem_get_dma_size(soc->osdev,
  2235. &ipa_res->rx_alt_rdy_ring.mem_info);
  2236. /* REO Tail Pointer Address */
  2237. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2238. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2239. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  2240. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2241. &ipa_res->rx_alt_refill_ring.sgtable,
  2242. sizeof(sgtable_t));
  2243. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2244. qdf_mem_get_dma_size(soc->osdev,
  2245. &ipa_res->rx_alt_refill_ring.mem_info);
  2246. /* FW Head Pointer Address */
  2247. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2248. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2249. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2250. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2251. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2252. }
  2253. /**
  2254. * dp_ipa_wdi_rx_alt_pipe_params() - Setup 2nd rx pipe params
  2255. * @soc: data path soc handle
  2256. * @ipa_res: ipa resource pointer
  2257. * @rx: pipe info handle
  2258. * @over_gsi: flag for IPA offload over gsi
  2259. * @hdl: ipa registered handle
  2260. *
  2261. * Return: none
  2262. */
  2263. static void dp_ipa_wdi_rx_alt_pipe_params(struct dp_soc *soc,
  2264. struct dp_ipa_resources *ipa_res,
  2265. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2266. bool over_gsi,
  2267. qdf_ipa_wdi_hdl_t hdl)
  2268. {
  2269. if (!wlan_ipa_is_vlan_enabled())
  2270. return;
  2271. if (over_gsi) {
  2272. if (hdl == DP_IPA_HDL_FIRST)
  2273. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2274. IPA_CLIENT_WLAN2_PROD1;
  2275. else if (hdl == DP_IPA_HDL_SECOND)
  2276. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2277. IPA_CLIENT_WLAN3_PROD1;
  2278. else if (hdl == DP_IPA_HDL_THIRD)
  2279. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2280. IPA_CLIENT_WLAN1_PROD1;
  2281. } else {
  2282. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2283. IPA_CLIENT_WLAN1_PROD;
  2284. }
  2285. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2286. qdf_mem_get_dma_addr(soc->osdev,
  2287. &ipa_res->rx_alt_rdy_ring.mem_info);
  2288. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2289. qdf_mem_get_dma_size(soc->osdev,
  2290. &ipa_res->rx_alt_rdy_ring.mem_info);
  2291. /* REO Tail Pointer Address */
  2292. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2293. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2294. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2295. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2296. qdf_mem_get_dma_addr(soc->osdev,
  2297. &ipa_res->rx_alt_refill_ring.mem_info);
  2298. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2299. qdf_mem_get_dma_size(soc->osdev,
  2300. &ipa_res->rx_alt_refill_ring.mem_info);
  2301. /* FW Head Pointer Address */
  2302. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2303. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2304. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2305. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2306. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2307. }
  2308. /**
  2309. * dp_ipa_setup_rx_alt_pipe() - Setup 2nd rx pipe for IPA offload
  2310. * @soc: data path soc handle
  2311. * @res: ipa resource pointer
  2312. * @in: pipe in handle
  2313. * @over_gsi: flag for IPA offload over gsi
  2314. * @hdl: ipa registered handle
  2315. *
  2316. * Return: none
  2317. */
  2318. static void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2319. struct dp_ipa_resources *res,
  2320. qdf_ipa_wdi_conn_in_params_t *in,
  2321. bool over_gsi,
  2322. qdf_ipa_wdi_hdl_t hdl)
  2323. {
  2324. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2325. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2326. qdf_ipa_ep_cfg_t *rx_cfg;
  2327. if (!wlan_ipa_is_vlan_enabled())
  2328. return;
  2329. QDF_IPA_WDI_CONN_IN_PARAMS_IS_RX1_USED(in) = true;
  2330. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  2331. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT_SMMU(in);
  2332. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2333. dp_ipa_wdi_rx_alt_pipe_smmu_params(soc, res, rx_smmu,
  2334. over_gsi, hdl);
  2335. } else {
  2336. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT(in);
  2337. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx);
  2338. dp_ipa_wdi_rx_alt_pipe_params(soc, res, rx, over_gsi, hdl);
  2339. }
  2340. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2341. /* Update with wds len(96) + 4 if wds support is enabled */
  2342. if (ucfg_ipa_is_wds_enabled())
  2343. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST_VLAN;
  2344. else
  2345. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2346. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2347. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2348. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2349. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2350. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2351. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2352. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2353. }
  2354. /**
  2355. * dp_ipa_set_rx_alt_pipe_db() - Setup 2nd rx pipe doorbell
  2356. * @res: ipa resource pointer
  2357. * @out: pipe out handle
  2358. *
  2359. * Return: none
  2360. */
  2361. static void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2362. qdf_ipa_wdi_conn_out_params_t *out)
  2363. {
  2364. if (!wlan_ipa_is_vlan_enabled())
  2365. return;
  2366. res->rx_alt_ready_doorbell_paddr =
  2367. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_ALT_UC_DB_PA(out);
  2368. dp_debug("Setting DB 0x%x for RX alt pipe",
  2369. res->rx_alt_ready_doorbell_paddr);
  2370. }
  2371. #else
  2372. static inline
  2373. void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2374. struct dp_ipa_resources *res,
  2375. qdf_ipa_wdi_conn_in_params_t *in,
  2376. bool over_gsi,
  2377. qdf_ipa_wdi_hdl_t hdl)
  2378. { }
  2379. static inline
  2380. void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2381. qdf_ipa_wdi_conn_out_params_t *out)
  2382. { }
  2383. #endif
  2384. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2385. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2386. void *ipa_wdi_meter_notifier_cb,
  2387. uint32_t ipa_desc_size, void *ipa_priv,
  2388. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2389. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  2390. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi,
  2391. qdf_ipa_wdi_hdl_t hdl, qdf_ipa_wdi_hdl_t id,
  2392. void *ipa_ast_notify_cb)
  2393. {
  2394. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2395. struct dp_pdev *pdev =
  2396. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2397. struct dp_ipa_resources *ipa_res;
  2398. qdf_ipa_ep_cfg_t *tx_cfg;
  2399. qdf_ipa_ep_cfg_t *rx_cfg;
  2400. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  2401. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2402. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  2403. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2404. qdf_ipa_wdi_conn_in_params_t *pipe_in = NULL;
  2405. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2406. int ret;
  2407. if (!pdev) {
  2408. dp_err("Invalid instance");
  2409. return QDF_STATUS_E_FAILURE;
  2410. }
  2411. ipa_res = &pdev->ipa_resource;
  2412. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2413. return QDF_STATUS_SUCCESS;
  2414. pipe_in = qdf_mem_malloc(sizeof(*pipe_in));
  2415. if (!pipe_in)
  2416. return QDF_STATUS_E_NOMEM;
  2417. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2418. if (is_smmu_enabled)
  2419. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = true;
  2420. else
  2421. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = false;
  2422. dp_setup_mcc_sys_pipes(sys_in, pipe_in);
  2423. /* TX PIPE */
  2424. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2425. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(pipe_in);
  2426. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  2427. } else {
  2428. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(pipe_in);
  2429. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  2430. }
  2431. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  2432. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2433. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  2434. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  2435. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  2436. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  2437. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  2438. /*
  2439. * Transfer Ring: WBM Ring
  2440. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2441. * Event Ring: TCL ring
  2442. * Event Ring Doorbell PA: TCL Head Pointer Address
  2443. */
  2444. if (is_smmu_enabled)
  2445. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi, id);
  2446. else
  2447. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  2448. dp_ipa_setup_tx_alt_pipe(soc, ipa_res, pipe_in);
  2449. /* RX PIPE */
  2450. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2451. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(pipe_in);
  2452. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2453. } else {
  2454. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(pipe_in);
  2455. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  2456. }
  2457. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2458. if (ucfg_ipa_is_wds_enabled())
  2459. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST;
  2460. else
  2461. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2462. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2463. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2464. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2465. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2466. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2467. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2468. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2469. /*
  2470. * Transfer Ring: REO Ring
  2471. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2472. * Event Ring: FW ring
  2473. * Event Ring Doorbell PA: FW Head Pointer Address
  2474. */
  2475. if (is_smmu_enabled)
  2476. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi, id);
  2477. else
  2478. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  2479. /* setup 2nd rx pipe */
  2480. dp_ipa_setup_rx_alt_pipe(soc, ipa_res, pipe_in, over_gsi, id);
  2481. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(pipe_in) = ipa_w2i_cb;
  2482. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(pipe_in) = ipa_priv;
  2483. QDF_IPA_WDI_CONN_IN_PARAMS_HANDLE(pipe_in) = hdl;
  2484. dp_ipa_ast_notify_cb(pipe_in, ipa_ast_notify_cb);
  2485. /* Connect WDI IPA PIPEs */
  2486. ret = qdf_ipa_wdi_conn_pipes(pipe_in, &pipe_out);
  2487. if (ret) {
  2488. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2489. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2490. __func__, ret);
  2491. qdf_mem_free(pipe_in);
  2492. return QDF_STATUS_E_FAILURE;
  2493. }
  2494. /* IPA uC Doorbell registers */
  2495. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  2496. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2497. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2498. dp_ipa_set_pipe_db(ipa_res, &pipe_out);
  2499. dp_ipa_set_rx_alt_pipe_db(ipa_res, &pipe_out);
  2500. ipa_res->is_db_ddr_mapped =
  2501. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  2502. soc->ipa_first_tx_db_access = true;
  2503. qdf_mem_free(pipe_in);
  2504. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2505. soc->ipa_rx_buf_map_lock_initialized = true;
  2506. return QDF_STATUS_SUCCESS;
  2507. }
  2508. #ifdef IPA_WDI3_VLAN_SUPPORT
  2509. /**
  2510. * dp_ipa_set_rx1_used() - Set rx1 used flag for 2nd rx offload ring
  2511. * @in: pipe in handle
  2512. *
  2513. * Return: none
  2514. */
  2515. static inline
  2516. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2517. {
  2518. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_RX1_USED(in) = true;
  2519. }
  2520. /**
  2521. * dp_ipa_set_v4_vlan_hdr() - Set v4 vlan hdr
  2522. * @in: pipe in handle
  2523. * @hdr: pointer to hdr
  2524. *
  2525. * Return: none
  2526. */
  2527. static inline
  2528. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2529. qdf_ipa_wdi_hdr_info_t *hdr)
  2530. {
  2531. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v4_VLAN]),
  2532. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2533. }
  2534. /**
  2535. * dp_ipa_set_v6_vlan_hdr() - Set v6 vlan hdr
  2536. * @in: pipe in handle
  2537. * @hdr: pointer to hdr
  2538. *
  2539. * Return: none
  2540. */
  2541. static inline
  2542. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2543. qdf_ipa_wdi_hdr_info_t *hdr)
  2544. {
  2545. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v6_VLAN]),
  2546. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2547. }
  2548. #else
  2549. static inline
  2550. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2551. { }
  2552. static inline
  2553. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2554. qdf_ipa_wdi_hdr_info_t *hdr)
  2555. { }
  2556. static inline
  2557. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2558. qdf_ipa_wdi_hdr_info_t *hdr)
  2559. { }
  2560. #endif
  2561. #ifdef IPA_WDS_EASYMESH_FEATURE
  2562. /**
  2563. * dp_ipa_set_wdi_hdr_type() - Set wdi hdr type for IPA
  2564. * @hdr_info: Header info
  2565. *
  2566. * Return: None
  2567. */
  2568. static inline void
  2569. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2570. {
  2571. if (ucfg_ipa_is_wds_enabled())
  2572. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2573. IPA_HDR_L2_ETHERNET_II_AST;
  2574. else
  2575. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2576. IPA_HDR_L2_ETHERNET_II;
  2577. }
  2578. /**
  2579. * dp_ipa_setup_meta_data_mask() - Pass meta data mask to IPA
  2580. * @in: ipa in params
  2581. *
  2582. * Pass meta data mask to IPA.
  2583. *
  2584. * Return: none
  2585. */
  2586. static void dp_ipa_setup_meta_data_mask(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2587. {
  2588. if (ucfg_ipa_is_wds_enabled())
  2589. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_AST_META_DATA_MASK;
  2590. else
  2591. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_META_DATA_MASK;
  2592. }
  2593. #else
  2594. static inline void
  2595. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2596. {
  2597. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2598. }
  2599. static void dp_ipa_setup_meta_data_mask(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2600. {
  2601. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(in) = WLAN_IPA_META_DATA_MASK;
  2602. }
  2603. #endif
  2604. #ifdef IPA_WDI3_VLAN_SUPPORT
  2605. /**
  2606. * dp_ipa_set_wdi_vlan_hdr_type() - Set wdi vlan hdr type for IPA
  2607. * @hdr_info: Header info
  2608. *
  2609. * Return: None
  2610. */
  2611. static inline void
  2612. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2613. {
  2614. if (ucfg_ipa_is_wds_enabled())
  2615. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2616. IPA_HDR_L2_802_1Q_AST;
  2617. else
  2618. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2619. IPA_HDR_L2_802_1Q;
  2620. }
  2621. #else
  2622. static inline void
  2623. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2624. { }
  2625. #endif
  2626. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2627. qdf_ipa_client_type_t prod_client,
  2628. qdf_ipa_client_type_t cons_client,
  2629. uint8_t session_id, bool is_ipv6_enabled,
  2630. qdf_ipa_wdi_hdl_t hdl)
  2631. {
  2632. qdf_ipa_wdi_reg_intf_in_params_t in;
  2633. qdf_ipa_wdi_hdr_info_t hdr_info;
  2634. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2635. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2636. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr;
  2637. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr_v6;
  2638. int ret = -EINVAL;
  2639. qdf_mem_zero(&in, sizeof(qdf_ipa_wdi_reg_intf_in_params_t));
  2640. /* Need to reset the values to 0 as all the fields are not
  2641. * updated in the Header, Unused fields will be set to 0.
  2642. */
  2643. qdf_mem_zero(&uc_tx_vlan_hdr, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2644. qdf_mem_zero(&uc_tx_vlan_hdr_v6, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2645. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  2646. QDF_MAC_ADDR_REF(mac_addr));
  2647. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2648. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2649. /* IPV4 header */
  2650. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2651. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2652. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2653. dp_ipa_set_wdi_hdr_type(&hdr_info);
  2654. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2655. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2656. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2657. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2658. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2659. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  2660. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2661. dp_ipa_setup_meta_data_mask(&in);
  2662. QDF_IPA_WDI_REG_INTF_IN_PARAMS_HANDLE(&in) = hdl;
  2663. dp_ipa_setup_iface_session_id(&in, session_id);
  2664. dp_debug("registering for session_id: %u", session_id);
  2665. /* IPV6 header */
  2666. if (is_ipv6_enabled) {
  2667. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2668. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2669. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2670. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2671. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2672. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2673. }
  2674. if (wlan_ipa_is_vlan_enabled()) {
  2675. /* Add vlan specific headers if vlan supporti is enabled */
  2676. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2677. dp_ipa_set_rx1_used(&in);
  2678. qdf_ether_addr_copy(uc_tx_vlan_hdr.eth.h_source, mac_addr);
  2679. /* IPV4 Vlan header */
  2680. uc_tx_vlan_hdr.eth.h_vlan_proto = qdf_htons(ETH_P_8021Q);
  2681. uc_tx_vlan_hdr.eth.h_vlan_encapsulated_proto = qdf_htons(ETH_P_IP);
  2682. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2683. (uint8_t *)&uc_tx_vlan_hdr;
  2684. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) =
  2685. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2686. dp_ipa_set_wdi_vlan_hdr_type(&hdr_info);
  2687. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2688. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2689. dp_ipa_set_v4_vlan_hdr(&in, &hdr_info);
  2690. /* IPV6 Vlan header */
  2691. if (is_ipv6_enabled) {
  2692. qdf_mem_copy(&uc_tx_vlan_hdr_v6, &uc_tx_vlan_hdr,
  2693. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN);
  2694. uc_tx_vlan_hdr_v6.eth.h_vlan_proto =
  2695. qdf_htons(ETH_P_8021Q);
  2696. uc_tx_vlan_hdr_v6.eth.h_vlan_encapsulated_proto =
  2697. qdf_htons(ETH_P_IPV6);
  2698. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2699. (uint8_t *)&uc_tx_vlan_hdr_v6;
  2700. dp_ipa_set_v6_vlan_hdr(&in, &hdr_info);
  2701. }
  2702. }
  2703. ret = qdf_ipa_wdi_reg_intf(&in);
  2704. if (ret) {
  2705. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2706. "%s: ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2707. __func__, ret);
  2708. return QDF_STATUS_E_FAILURE;
  2709. }
  2710. return QDF_STATUS_SUCCESS;
  2711. }
  2712. #else /* !CONFIG_IPA_WDI_UNIFIED_API */
  2713. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2714. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2715. void *ipa_wdi_meter_notifier_cb,
  2716. uint32_t ipa_desc_size, void *ipa_priv,
  2717. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2718. uint32_t *rx_pipe_handle)
  2719. {
  2720. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2721. struct dp_pdev *pdev =
  2722. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2723. struct dp_ipa_resources *ipa_res;
  2724. qdf_ipa_wdi_pipe_setup_info_t *tx;
  2725. qdf_ipa_wdi_pipe_setup_info_t *rx;
  2726. qdf_ipa_wdi_conn_in_params_t pipe_in;
  2727. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2728. struct tcl_data_cmd *tcl_desc_ptr;
  2729. uint8_t *desc_addr;
  2730. uint32_t desc_size;
  2731. int ret;
  2732. if (!pdev) {
  2733. dp_err("Invalid instance");
  2734. return QDF_STATUS_E_FAILURE;
  2735. }
  2736. ipa_res = &pdev->ipa_resource;
  2737. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2738. return QDF_STATUS_SUCCESS;
  2739. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2740. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2741. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  2742. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2743. /* TX PIPE */
  2744. /*
  2745. * Transfer Ring: WBM Ring
  2746. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2747. * Event Ring: TCL ring
  2748. * Event Ring Doorbell PA: TCL Head Pointer Address
  2749. */
  2750. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  2751. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  2752. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2753. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  2754. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  2755. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  2756. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  2757. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  2758. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2759. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2760. ipa_res->tx_comp_ring_base_paddr;
  2761. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2762. ipa_res->tx_comp_ring_size;
  2763. /* WBM Tail Pointer Address */
  2764. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2765. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2766. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2767. ipa_res->tx_ring_base_paddr;
  2768. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  2769. /* TCL Head Pointer Address */
  2770. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2771. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2772. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2773. ipa_res->tx_num_alloc_buffer;
  2774. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2775. /* Preprogram TCL descriptor */
  2776. desc_addr =
  2777. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  2778. desc_size = sizeof(struct tcl_data_cmd);
  2779. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  2780. tcl_desc_ptr = (struct tcl_data_cmd *)
  2781. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  2782. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  2783. HAL_RX_BUF_RBM_SW2_BM;
  2784. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  2785. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  2786. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  2787. /* RX PIPE */
  2788. /*
  2789. * Transfer Ring: REO Ring
  2790. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2791. * Event Ring: FW ring
  2792. * Event Ring Doorbell PA: FW Head Pointer Address
  2793. */
  2794. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  2795. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  2796. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2797. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  2798. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  2799. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  2800. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  2801. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  2802. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  2803. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  2804. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  2805. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2806. ipa_res->rx_rdy_ring_base_paddr;
  2807. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2808. ipa_res->rx_rdy_ring_size;
  2809. /* REO Tail Pointer Address */
  2810. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2811. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2812. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2813. ipa_res->rx_refill_ring_base_paddr;
  2814. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2815. ipa_res->rx_refill_ring_size;
  2816. /* FW Head Pointer Address */
  2817. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2818. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2819. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = soc->rx_pkt_tlv_size +
  2820. L3_HEADER_PADDING;
  2821. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  2822. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  2823. /* Connect WDI IPA PIPE */
  2824. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  2825. if (ret) {
  2826. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2827. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2828. __func__, ret);
  2829. return QDF_STATUS_E_FAILURE;
  2830. }
  2831. /* IPA uC Doorbell registers */
  2832. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2833. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  2834. __func__,
  2835. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2836. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2837. ipa_res->tx_comp_doorbell_paddr =
  2838. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  2839. ipa_res->tx_comp_doorbell_vaddr =
  2840. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  2841. ipa_res->rx_ready_doorbell_paddr =
  2842. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  2843. soc->ipa_first_tx_db_access = true;
  2844. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2845. soc->ipa_rx_buf_map_lock_initialized = true;
  2846. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2847. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2848. __func__,
  2849. "transfer_ring_base_pa",
  2850. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  2851. "transfer_ring_size",
  2852. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  2853. "transfer_ring_doorbell_pa",
  2854. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  2855. "event_ring_base_pa",
  2856. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  2857. "event_ring_size",
  2858. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  2859. "event_ring_doorbell_pa",
  2860. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  2861. "num_pkt_buffers",
  2862. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  2863. "tx_comp_doorbell_paddr",
  2864. (void *)ipa_res->tx_comp_doorbell_paddr);
  2865. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2866. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2867. __func__,
  2868. "transfer_ring_base_pa",
  2869. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  2870. "transfer_ring_size",
  2871. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  2872. "transfer_ring_doorbell_pa",
  2873. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  2874. "event_ring_base_pa",
  2875. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  2876. "event_ring_size",
  2877. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  2878. "event_ring_doorbell_pa",
  2879. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  2880. "num_pkt_buffers",
  2881. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  2882. "tx_comp_doorbell_paddr",
  2883. (void *)ipa_res->rx_ready_doorbell_paddr);
  2884. return QDF_STATUS_SUCCESS;
  2885. }
  2886. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2887. qdf_ipa_client_type_t prod_client,
  2888. qdf_ipa_client_type_t cons_client,
  2889. uint8_t session_id, bool is_ipv6_enabled,
  2890. qdf_ipa_wdi_hdl_t hdl)
  2891. {
  2892. qdf_ipa_wdi_reg_intf_in_params_t in;
  2893. qdf_ipa_wdi_hdr_info_t hdr_info;
  2894. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2895. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2896. int ret = -EINVAL;
  2897. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2898. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  2899. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  2900. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2901. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2902. /* IPV4 header */
  2903. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2904. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2905. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2906. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2907. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2908. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2909. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2910. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2911. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2912. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2913. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  2914. htonl(session_id << 16);
  2915. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  2916. /* IPV6 header */
  2917. if (is_ipv6_enabled) {
  2918. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2919. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2920. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2921. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2922. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2923. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2924. }
  2925. ret = qdf_ipa_wdi_reg_intf(&in);
  2926. if (ret) {
  2927. dp_err("ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2928. ret);
  2929. return QDF_STATUS_E_FAILURE;
  2930. }
  2931. return QDF_STATUS_SUCCESS;
  2932. }
  2933. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  2934. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2935. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle,
  2936. qdf_ipa_wdi_hdl_t hdl)
  2937. {
  2938. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2939. QDF_STATUS status = QDF_STATUS_SUCCESS;
  2940. struct dp_pdev *pdev;
  2941. int ret;
  2942. ret = qdf_ipa_wdi_disconn_pipes(hdl);
  2943. if (ret) {
  2944. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  2945. ret);
  2946. status = QDF_STATUS_E_FAILURE;
  2947. }
  2948. if (soc->ipa_rx_buf_map_lock_initialized) {
  2949. qdf_spinlock_destroy(&soc->ipa_rx_buf_map_lock);
  2950. soc->ipa_rx_buf_map_lock_initialized = false;
  2951. }
  2952. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2953. if (qdf_unlikely(!pdev)) {
  2954. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  2955. status = QDF_STATUS_E_FAILURE;
  2956. goto exit;
  2957. }
  2958. dp_ipa_unmap_ring_doorbell_paddr(pdev);
  2959. dp_ipa_unmap_rx_alt_ring_doorbell_paddr(pdev);
  2960. exit:
  2961. return status;
  2962. }
  2963. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled,
  2964. qdf_ipa_wdi_hdl_t hdl)
  2965. {
  2966. int ret;
  2967. ret = qdf_ipa_wdi_dereg_intf(ifname, hdl);
  2968. if (ret) {
  2969. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2970. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  2971. __func__, ret);
  2972. return QDF_STATUS_E_FAILURE;
  2973. }
  2974. return QDF_STATUS_SUCCESS;
  2975. }
  2976. #ifdef IPA_SET_RESET_TX_DB_PA
  2977. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res) \
  2978. dp_ipa_set_tx_doorbell_paddr((soc), (ipa_res))
  2979. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res) \
  2980. dp_ipa_reset_tx_doorbell_pa((soc), (ipa_res))
  2981. #else
  2982. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res)
  2983. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res)
  2984. #endif
  2985. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2986. qdf_ipa_wdi_hdl_t hdl)
  2987. {
  2988. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2989. struct dp_pdev *pdev =
  2990. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2991. struct dp_ipa_resources *ipa_res;
  2992. QDF_STATUS result;
  2993. if (!pdev) {
  2994. dp_err("Invalid instance");
  2995. return QDF_STATUS_E_FAILURE;
  2996. }
  2997. ipa_res = &pdev->ipa_resource;
  2998. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  2999. DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res);
  3000. if (!ipa_config_is_opt_wifi_dp_enabled()) {
  3001. qdf_atomic_set(&soc->ipa_map_allowed, 1);
  3002. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true,
  3003. __func__, __LINE__);
  3004. }
  3005. result = qdf_ipa_wdi_enable_pipes(hdl);
  3006. if (result) {
  3007. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3008. "%s: Enable WDI PIPE fail, code %d",
  3009. __func__, result);
  3010. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  3011. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  3012. if (qdf_atomic_read(&soc->ipa_map_allowed)) {
  3013. qdf_atomic_set(&soc->ipa_map_allowed, 0);
  3014. dp_ipa_handle_rx_buf_pool_smmu_mapping(
  3015. soc, pdev, false, __func__, __LINE__);
  3016. }
  3017. return QDF_STATUS_E_FAILURE;
  3018. }
  3019. if (soc->ipa_first_tx_db_access) {
  3020. dp_ipa_tx_comp_ring_init_hp(soc, ipa_res);
  3021. soc->ipa_first_tx_db_access = false;
  3022. } else {
  3023. dp_ipa_tx_comp_ring_update_hp_addr(soc, ipa_res);
  3024. }
  3025. return QDF_STATUS_SUCCESS;
  3026. }
  3027. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3028. qdf_ipa_wdi_hdl_t hdl)
  3029. {
  3030. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3031. struct dp_pdev *pdev =
  3032. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3033. QDF_STATUS result;
  3034. struct dp_ipa_resources *ipa_res;
  3035. if (!pdev) {
  3036. dp_err("Invalid instance");
  3037. return QDF_STATUS_E_FAILURE;
  3038. }
  3039. ipa_res = &pdev->ipa_resource;
  3040. qdf_sleep(TX_COMP_DRAIN_WAIT_TIMEOUT_MS);
  3041. /*
  3042. * Reset the tx completion doorbell address before invoking IPA disable
  3043. * pipes API to ensure that there is no access to IPA tx doorbell
  3044. * address post disable pipes.
  3045. */
  3046. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  3047. result = qdf_ipa_wdi_disable_pipes(hdl);
  3048. if (result) {
  3049. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3050. "%s: Disable WDI PIPE fail, code %d",
  3051. __func__, result);
  3052. qdf_assert_always(0);
  3053. return QDF_STATUS_E_FAILURE;
  3054. }
  3055. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  3056. if (!ipa_config_is_opt_wifi_dp_enabled()) {
  3057. qdf_atomic_set(&soc->ipa_map_allowed, 0);
  3058. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  3059. __func__, __LINE__);
  3060. }
  3061. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  3062. }
  3063. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps,
  3064. qdf_ipa_wdi_hdl_t hdl)
  3065. {
  3066. qdf_ipa_wdi_perf_profile_t profile;
  3067. QDF_STATUS result;
  3068. profile.client = client;
  3069. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  3070. result = qdf_ipa_wdi_set_perf_profile(hdl, &profile);
  3071. if (result) {
  3072. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3073. "%s: ipa_wdi_set_perf_profile fail, code %d",
  3074. __func__, result);
  3075. return QDF_STATUS_E_FAILURE;
  3076. }
  3077. return QDF_STATUS_SUCCESS;
  3078. }
  3079. #ifdef QCA_SUPPORT_WDS_EXTENDED
  3080. /**
  3081. * dp_ipa_rx_wdsext_iface() - Forward RX exception packets to wdsext interface
  3082. * @soc_hdl: data path soc handle
  3083. * @peer_id: Peer id to get respective peer
  3084. * @skb: socket buffer
  3085. *
  3086. * Return: true on success, else false
  3087. */
  3088. bool dp_ipa_rx_wdsext_iface(struct cdp_soc_t *soc_hdl, uint8_t peer_id,
  3089. qdf_nbuf_t skb)
  3090. {
  3091. struct dp_txrx_peer *txrx_peer;
  3092. dp_txrx_ref_handle txrx_ref_handle = NULL;
  3093. struct dp_soc *dp_soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3094. bool status = false;
  3095. txrx_peer = dp_tgt_txrx_peer_get_ref_by_id(soc_hdl, peer_id,
  3096. &txrx_ref_handle,
  3097. DP_MOD_ID_IPA);
  3098. if (qdf_likely(txrx_peer)) {
  3099. if (dp_rx_deliver_to_stack_ext(dp_soc, txrx_peer->vdev,
  3100. txrx_peer, skb)
  3101. status = true;
  3102. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_IPA);
  3103. }
  3104. return status;
  3105. }
  3106. #endif
  3107. /**
  3108. * dp_ipa_intrabss_send() - send IPA RX intra-bss frames
  3109. * @pdev: pdev
  3110. * @vdev: vdev
  3111. * @nbuf: skb
  3112. *
  3113. * Return: nbuf if TX fails and NULL if TX succeeds
  3114. */
  3115. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  3116. struct dp_vdev *vdev,
  3117. qdf_nbuf_t nbuf)
  3118. {
  3119. struct dp_peer *vdev_peer;
  3120. uint16_t len;
  3121. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  3122. if (qdf_unlikely(!vdev_peer))
  3123. return nbuf;
  3124. if (qdf_unlikely(!vdev_peer->txrx_peer)) {
  3125. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3126. return nbuf;
  3127. }
  3128. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  3129. len = qdf_nbuf_len(nbuf);
  3130. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  3131. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3132. rx.intra_bss.fail, 1, len,
  3133. 0);
  3134. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3135. return nbuf;
  3136. }
  3137. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3138. rx.intra_bss.pkts, 1, len, 0);
  3139. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3140. return NULL;
  3141. }
  3142. #ifdef IPA_OPT_WIFI_DP
  3143. /**
  3144. * dp_ipa_rx_super_rule_setup()- pass cce super rule params to fw from ipa
  3145. *
  3146. * @soc_hdl: cdp soc
  3147. * @flt_params: filter tuple
  3148. *
  3149. * Return: QDF_STATUS
  3150. */
  3151. QDF_STATUS dp_ipa_rx_super_rule_setup(struct cdp_soc_t *soc_hdl,
  3152. void *flt_params)
  3153. {
  3154. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3155. return htt_h2t_rx_cce_super_rule_setup(soc->htt_handle, flt_params);
  3156. }
  3157. /**
  3158. * dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb()- send cce super rule filter
  3159. * add/remove result to ipa
  3160. *
  3161. * @flt0_rslt : result for filter0 add/remove
  3162. * @flt1_rslt : result for filter1 add/remove
  3163. *
  3164. * Return: void
  3165. */
  3166. void dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(int flt0_rslt, int flt1_rslt)
  3167. {
  3168. wlan_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(flt0_rslt, flt1_rslt);
  3169. }
  3170. int dp_ipa_pcie_link_up(struct cdp_soc_t *soc_hdl)
  3171. {
  3172. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3173. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3174. int response = 0;
  3175. response = hif_prevent_l1((hal_soc->hif_handle));
  3176. return response;
  3177. }
  3178. void dp_ipa_pcie_link_down(struct cdp_soc_t *soc_hdl)
  3179. {
  3180. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3181. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3182. hif_allow_l1(hal_soc->hif_handle);
  3183. }
  3184. /**
  3185. * dp_ipa_wdi_opt_dpath_notify_flt_rlsd()- send cce super rule release
  3186. * notification to ipa
  3187. *
  3188. * @flt0_rslt : result for filter0 release
  3189. * @flt1_rslt : result for filter1 release
  3190. *
  3191. *Return: void
  3192. */
  3193. void dp_ipa_wdi_opt_dpath_notify_flt_rlsd(int flt0_rslt, int flt1_rslt)
  3194. {
  3195. wlan_ipa_wdi_opt_dpath_notify_flt_rlsd(flt0_rslt, flt1_rslt);
  3196. }
  3197. /**
  3198. * dp_ipa_wdi_opt_dpath_notify_flt_rsvd()- send cce super rule reserve
  3199. * notification to ipa
  3200. *
  3201. *@is_success : result of filter reservatiom
  3202. *
  3203. *Return: void
  3204. */
  3205. void dp_ipa_wdi_opt_dpath_notify_flt_rsvd(bool is_success)
  3206. {
  3207. wlan_ipa_wdi_opt_dpath_notify_flt_rsvd(is_success);
  3208. }
  3209. #endif
  3210. #ifdef IPA_WDS_EASYMESH_FEATURE
  3211. /**
  3212. * dp_ipa_peer_check() - Check for peer for given mac
  3213. * @soc: dp soc object
  3214. * @peer_mac_addr: peer mac address
  3215. * @vdev_id: vdev id
  3216. *
  3217. * Return: true if peer is found, else false
  3218. */
  3219. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3220. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3221. {
  3222. struct dp_ast_entry *ast_entry = NULL;
  3223. struct dp_peer *peer = NULL;
  3224. qdf_spin_lock_bh(&soc->ast_lock);
  3225. ast_entry = dp_peer_ast_hash_find_soc(soc, peer_mac_addr);
  3226. if ((!ast_entry) ||
  3227. (ast_entry->delete_in_progress && !ast_entry->callback)) {
  3228. qdf_spin_unlock_bh(&soc->ast_lock);
  3229. return false;
  3230. }
  3231. peer = dp_peer_get_ref_by_id(soc, ast_entry->peer_id,
  3232. DP_MOD_ID_IPA);
  3233. if (!peer) {
  3234. qdf_spin_unlock_bh(&soc->ast_lock);
  3235. return false;
  3236. } else {
  3237. if (peer->vdev->vdev_id == vdev_id) {
  3238. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3239. qdf_spin_unlock_bh(&soc->ast_lock);
  3240. return true;
  3241. }
  3242. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3243. qdf_spin_unlock_bh(&soc->ast_lock);
  3244. return false;
  3245. }
  3246. }
  3247. #else
  3248. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3249. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3250. {
  3251. struct cdp_peer_info peer_info = {0};
  3252. struct dp_peer *peer = NULL;
  3253. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac_addr, false,
  3254. CDP_WILD_PEER_TYPE);
  3255. peer = dp_peer_hash_find_wrapper(soc, &peer_info, DP_MOD_ID_IPA);
  3256. if (peer) {
  3257. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3258. return true;
  3259. } else {
  3260. return false;
  3261. }
  3262. }
  3263. #endif
  3264. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3265. qdf_nbuf_t nbuf, bool *fwd_success)
  3266. {
  3267. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3268. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3269. DP_MOD_ID_IPA);
  3270. struct dp_pdev *pdev;
  3271. qdf_nbuf_t nbuf_copy;
  3272. uint8_t da_is_bcmc;
  3273. struct ethhdr *eh;
  3274. bool status = false;
  3275. *fwd_success = false; /* set default as failure */
  3276. /*
  3277. * WDI 3.0 skb->cb[] info from IPA driver
  3278. * skb->cb[0] = vdev_id
  3279. * skb->cb[1].bit#1 = da_is_bcmc
  3280. */
  3281. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3282. if (qdf_unlikely(!vdev))
  3283. return false;
  3284. pdev = vdev->pdev;
  3285. if (qdf_unlikely(!pdev))
  3286. goto out;
  3287. /* no fwd for station mode and just pass up to stack */
  3288. if (vdev->opmode == wlan_op_mode_sta)
  3289. goto out;
  3290. if (da_is_bcmc) {
  3291. nbuf_copy = qdf_nbuf_copy(nbuf);
  3292. if (!nbuf_copy)
  3293. goto out;
  3294. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  3295. qdf_nbuf_free(nbuf_copy);
  3296. else
  3297. *fwd_success = true;
  3298. /* return false to pass original pkt up to stack */
  3299. goto out;
  3300. }
  3301. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  3302. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  3303. goto out;
  3304. if (!dp_ipa_peer_check(soc, eh->h_dest, vdev->vdev_id))
  3305. goto out;
  3306. if (!dp_ipa_peer_check(soc, eh->h_source, vdev->vdev_id))
  3307. goto out;
  3308. /*
  3309. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  3310. * Need to add skb to internal tracking table to avoid nbuf memory
  3311. * leak check for unallocated skb.
  3312. */
  3313. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  3314. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  3315. qdf_nbuf_free(nbuf);
  3316. else
  3317. *fwd_success = true;
  3318. status = true;
  3319. out:
  3320. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3321. return status;
  3322. }
  3323. #ifdef MDM_PLATFORM
  3324. bool dp_ipa_is_mdm_platform(void)
  3325. {
  3326. return true;
  3327. }
  3328. #else
  3329. bool dp_ipa_is_mdm_platform(void)
  3330. {
  3331. return false;
  3332. }
  3333. #endif
  3334. /**
  3335. * dp_ipa_frag_nbuf_linearize() - linearize nbuf for IPA
  3336. * @soc: soc
  3337. * @nbuf: source skb
  3338. *
  3339. * Return: new nbuf if success and otherwise NULL
  3340. */
  3341. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  3342. qdf_nbuf_t nbuf)
  3343. {
  3344. uint8_t *src_nbuf_data;
  3345. uint8_t *dst_nbuf_data;
  3346. qdf_nbuf_t dst_nbuf;
  3347. qdf_nbuf_t temp_nbuf = nbuf;
  3348. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  3349. bool is_nbuf_head = true;
  3350. uint32_t copy_len = 0;
  3351. uint16_t buf_size;
  3352. buf_size = wlan_cfg_rx_buffer_size(soc->wlan_cfg_ctx);
  3353. dst_nbuf = qdf_nbuf_alloc(soc->osdev, buf_size,
  3354. RX_BUFFER_RESERVATION,
  3355. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  3356. if (!dst_nbuf) {
  3357. dp_err_rl("nbuf allocate fail");
  3358. return NULL;
  3359. }
  3360. if ((nbuf_len + L3_HEADER_PADDING) > buf_size) {
  3361. qdf_nbuf_free(dst_nbuf);
  3362. dp_err_rl("nbuf is jumbo data");
  3363. return NULL;
  3364. }
  3365. /* prepeare to copy all data into new skb */
  3366. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  3367. while (temp_nbuf) {
  3368. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  3369. /* first head nbuf */
  3370. if (is_nbuf_head) {
  3371. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  3372. soc->rx_pkt_tlv_size);
  3373. /* leave extra 2 bytes L3_HEADER_PADDING */
  3374. dst_nbuf_data += (soc->rx_pkt_tlv_size +
  3375. L3_HEADER_PADDING);
  3376. src_nbuf_data += soc->rx_pkt_tlv_size;
  3377. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  3378. soc->rx_pkt_tlv_size;
  3379. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  3380. is_nbuf_head = false;
  3381. } else {
  3382. copy_len = qdf_nbuf_len(temp_nbuf);
  3383. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  3384. }
  3385. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  3386. dst_nbuf_data += copy_len;
  3387. }
  3388. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  3389. /* copy is done, free original nbuf */
  3390. qdf_nbuf_free(nbuf);
  3391. return dst_nbuf;
  3392. }
  3393. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  3394. {
  3395. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3396. return nbuf;
  3397. /* WLAN IPA is run-time disabled */
  3398. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  3399. return nbuf;
  3400. if (!qdf_nbuf_is_frag(nbuf))
  3401. return nbuf;
  3402. /* linearize skb for IPA */
  3403. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  3404. }
  3405. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  3406. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3407. const char *func, uint32_t line)
  3408. {
  3409. QDF_STATUS ret;
  3410. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3411. struct dp_pdev *pdev =
  3412. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3413. if (!pdev) {
  3414. dp_err("Invalid instance");
  3415. return QDF_STATUS_E_FAILURE;
  3416. }
  3417. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3418. dp_debug("SMMU S1 disabled");
  3419. return QDF_STATUS_SUCCESS;
  3420. }
  3421. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true, func, line);
  3422. if (ret)
  3423. return ret;
  3424. ret = dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, true, func, line);
  3425. if (ret)
  3426. __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line);
  3427. return ret;
  3428. }
  3429. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  3430. struct cdp_soc_t *soc_hdl, uint8_t pdev_id, const char *func,
  3431. uint32_t line)
  3432. {
  3433. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3434. struct dp_pdev *pdev =
  3435. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3436. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3437. dp_debug("SMMU S1 disabled");
  3438. return QDF_STATUS_SUCCESS;
  3439. }
  3440. if (!pdev) {
  3441. dp_err("Invalid pdev instance pdev_id:%d", pdev_id);
  3442. return QDF_STATUS_E_FAILURE;
  3443. }
  3444. if (__dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line) ||
  3445. dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, false, func, line))
  3446. return QDF_STATUS_E_FAILURE;
  3447. return QDF_STATUS_SUCCESS;
  3448. }
  3449. QDF_STATUS dp_ipa_rx_buf_pool_smmu_mapping(
  3450. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3451. bool create, const char *func, uint32_t line)
  3452. {
  3453. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3454. struct dp_pdev *pdev =
  3455. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3456. if (!pdev) {
  3457. dp_err("Invalid instance");
  3458. return QDF_STATUS_E_FAILURE;
  3459. }
  3460. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3461. dp_debug("SMMU S1 disabled");
  3462. return QDF_STATUS_SUCCESS;
  3463. }
  3464. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, create, func, line);
  3465. return QDF_STATUS_SUCCESS;
  3466. }
  3467. #ifdef IPA_WDS_EASYMESH_FEATURE
  3468. QDF_STATUS dp_ipa_ast_create(struct cdp_soc_t *soc_hdl,
  3469. qdf_ipa_ast_info_type_t *data)
  3470. {
  3471. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3472. uint8_t *rx_tlv_hdr;
  3473. struct dp_peer *peer;
  3474. struct hal_rx_msdu_metadata msdu_metadata;
  3475. qdf_ipa_ast_info_type_t *ast_info;
  3476. if (!data) {
  3477. dp_err("Data is NULL !!!");
  3478. return QDF_STATUS_E_FAILURE;
  3479. }
  3480. ast_info = data;
  3481. rx_tlv_hdr = qdf_nbuf_data(ast_info->skb);
  3482. peer = dp_peer_get_ref_by_id(soc, ast_info->ta_peer_id,
  3483. DP_MOD_ID_IPA);
  3484. if (!peer) {
  3485. dp_err("Peer is NULL !!!!");
  3486. return QDF_STATUS_E_FAILURE;
  3487. }
  3488. hal_rx_msdu_metadata_get(soc->hal_soc, rx_tlv_hdr, &msdu_metadata);
  3489. dp_rx_ipa_wds_srcport_learn(soc, peer, ast_info->skb, msdu_metadata,
  3490. ast_info->mac_addr_ad4_valid,
  3491. ast_info->first_msdu_in_mpdu_flag);
  3492. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3493. return QDF_STATUS_SUCCESS;
  3494. }
  3495. #endif
  3496. #ifdef QCA_ENHANCED_STATS_SUPPORT
  3497. QDF_STATUS dp_ipa_update_peer_rx_stats(struct cdp_soc_t *soc,
  3498. uint8_t vdev_id, uint8_t *peer_mac,
  3499. qdf_nbuf_t nbuf)
  3500. {
  3501. struct dp_peer *peer = dp_peer_find_hash_find((struct dp_soc *)soc,
  3502. peer_mac, 0, vdev_id,
  3503. DP_MOD_ID_IPA);
  3504. struct dp_txrx_peer *txrx_peer;
  3505. uint8_t da_is_bcmc;
  3506. qdf_ether_header_t *eh;
  3507. if (!peer)
  3508. return QDF_STATUS_E_FAILURE;
  3509. txrx_peer = dp_get_txrx_peer(peer);
  3510. if (!txrx_peer) {
  3511. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3512. return QDF_STATUS_E_FAILURE;
  3513. }
  3514. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3515. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3516. if (da_is_bcmc) {
  3517. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.multicast, 1,
  3518. qdf_nbuf_len(nbuf), 0);
  3519. if (QDF_IS_ADDR_BROADCAST(eh->ether_dhost))
  3520. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.bcast,
  3521. 1, qdf_nbuf_len(nbuf), 0);
  3522. }
  3523. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3524. return QDF_STATUS_SUCCESS;
  3525. }
  3526. void
  3527. dp_peer_aggregate_tid_stats(struct dp_peer *peer)
  3528. {
  3529. uint8_t i = 0;
  3530. struct dp_rx_tid *rx_tid = NULL;
  3531. struct cdp_pkt_info rx_total = {0};
  3532. struct dp_txrx_peer *txrx_peer = NULL;
  3533. if (!peer->rx_tid)
  3534. return;
  3535. txrx_peer = dp_get_txrx_peer(peer);
  3536. if (!txrx_peer)
  3537. return;
  3538. for (i = 0; i < DP_MAX_TIDS; i++) {
  3539. rx_tid = &peer->rx_tid[i];
  3540. rx_total.num += rx_tid->rx_msdu_cnt.num;
  3541. rx_total.bytes += rx_tid->rx_msdu_cnt.bytes;
  3542. }
  3543. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.num,
  3544. rx_total.num, 0);
  3545. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.bytes,
  3546. rx_total.bytes, 0);
  3547. }
  3548. /**
  3549. * dp_ipa_update_vdev_stats(): update vdev stats
  3550. * @soc: soc handle
  3551. * @srcobj: DP_PEER object
  3552. * @arg: point to vdev stats structure
  3553. *
  3554. * Return: void
  3555. */
  3556. static inline
  3557. void dp_ipa_update_vdev_stats(struct dp_soc *soc, struct dp_peer *srcobj,
  3558. void *arg)
  3559. {
  3560. dp_peer_aggregate_tid_stats(srcobj);
  3561. dp_update_vdev_stats(soc, srcobj, arg);
  3562. }
  3563. /**
  3564. * dp_ipa_aggregate_vdev_stats - Aggregate vdev_stats
  3565. * @vdev: Data path vdev
  3566. * @vdev_stats: buffer to hold vdev stats
  3567. *
  3568. * Return: void
  3569. */
  3570. static inline
  3571. void dp_ipa_aggregate_vdev_stats(struct dp_vdev *vdev,
  3572. struct cdp_vdev_stats *vdev_stats)
  3573. {
  3574. struct dp_soc *soc = NULL;
  3575. if (!vdev || !vdev->pdev)
  3576. return;
  3577. soc = vdev->pdev->soc;
  3578. dp_update_vdev_ingress_stats(vdev);
  3579. dp_copy_vdev_stats_to_tgt_buf(vdev_stats, &vdev->stats, DP_XMIT_LINK);
  3580. dp_vdev_iterate_peer(vdev, dp_ipa_update_vdev_stats, vdev_stats,
  3581. DP_MOD_ID_GENERIC_STATS);
  3582. dp_update_vdev_rate_stats(vdev_stats, &vdev->stats);
  3583. vdev_stats->tx.ucast.num = vdev_stats->tx.tx_ucast_total.num;
  3584. vdev_stats->tx.ucast.bytes = vdev_stats->tx.tx_ucast_total.bytes;
  3585. vdev_stats->tx.tx_success.num = vdev_stats->tx.tx_ucast_success.num;
  3586. vdev_stats->tx.tx_success.bytes = vdev_stats->tx.tx_ucast_success.bytes;
  3587. if (vdev_stats->rx.rx_total.num >= vdev_stats->rx.multicast.num)
  3588. vdev_stats->rx.unicast.num = vdev_stats->rx.rx_total.num -
  3589. vdev_stats->rx.multicast.num;
  3590. if (vdev_stats->rx.rx_total.bytes >= vdev_stats->rx.multicast.bytes)
  3591. vdev_stats->rx.unicast.bytes = vdev_stats->rx.rx_total.bytes -
  3592. vdev_stats->rx.multicast.bytes;
  3593. vdev_stats->rx.to_stack.num = vdev_stats->rx.rx_total.num;
  3594. vdev_stats->rx.to_stack.bytes = vdev_stats->rx.rx_total.bytes;
  3595. }
  3596. /**
  3597. * dp_ipa_aggregate_pdev_stats - Aggregate pdev stats
  3598. * @pdev: Data path pdev
  3599. *
  3600. * Return: void
  3601. */
  3602. static inline
  3603. void dp_ipa_aggregate_pdev_stats(struct dp_pdev *pdev)
  3604. {
  3605. struct dp_vdev *vdev = NULL;
  3606. struct dp_soc *soc;
  3607. struct cdp_vdev_stats *vdev_stats =
  3608. qdf_mem_malloc_atomic(sizeof(struct cdp_vdev_stats));
  3609. if (!vdev_stats) {
  3610. dp_err("%pK: DP alloc failure - unable to get alloc vdev stats",
  3611. pdev->soc);
  3612. return;
  3613. }
  3614. soc = pdev->soc;
  3615. qdf_mem_zero(&pdev->stats.tx, sizeof(pdev->stats.tx));
  3616. qdf_mem_zero(&pdev->stats.rx, sizeof(pdev->stats.rx));
  3617. qdf_mem_zero(&pdev->stats.tx_i, sizeof(pdev->stats.tx_i));
  3618. qdf_mem_zero(&pdev->stats.rx_i, sizeof(pdev->stats.rx_i));
  3619. qdf_spin_lock_bh(&pdev->vdev_list_lock);
  3620. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3621. dp_ipa_aggregate_vdev_stats(vdev, vdev_stats);
  3622. dp_update_pdev_stats(pdev, vdev_stats);
  3623. dp_update_pdev_ingress_stats(pdev, vdev);
  3624. }
  3625. qdf_spin_unlock_bh(&pdev->vdev_list_lock);
  3626. qdf_mem_free(vdev_stats);
  3627. }
  3628. /**
  3629. * dp_ipa_get_peer_stats - Get peer stats
  3630. * @peer: Data path peer
  3631. * @peer_stats: buffer to hold peer stats
  3632. *
  3633. * Return: void
  3634. */
  3635. static
  3636. void dp_ipa_get_peer_stats(struct dp_peer *peer,
  3637. struct cdp_peer_stats *peer_stats)
  3638. {
  3639. dp_peer_aggregate_tid_stats(peer);
  3640. dp_get_peer_stats(peer, peer_stats);
  3641. peer_stats->tx.tx_success.num =
  3642. peer_stats->tx.tx_ucast_success.num;
  3643. peer_stats->tx.tx_success.bytes =
  3644. peer_stats->tx.tx_ucast_success.bytes;
  3645. peer_stats->tx.ucast.num =
  3646. peer_stats->tx.tx_ucast_total.num;
  3647. peer_stats->tx.ucast.bytes =
  3648. peer_stats->tx.tx_ucast_total.bytes;
  3649. if (peer_stats->rx.rx_total.num >= peer_stats->rx.multicast.num)
  3650. peer_stats->rx.unicast.num = peer_stats->rx.rx_total.num -
  3651. peer_stats->rx.multicast.num;
  3652. if (peer_stats->rx.rx_total.bytes >= peer_stats->rx.multicast.bytes)
  3653. peer_stats->rx.unicast.bytes = peer_stats->rx.rx_total.bytes -
  3654. peer_stats->rx.multicast.bytes;
  3655. }
  3656. QDF_STATUS
  3657. dp_ipa_txrx_get_pdev_stats(struct cdp_soc_t *soc, uint8_t pdev_id,
  3658. struct cdp_pdev_stats *pdev_stats)
  3659. {
  3660. struct dp_pdev *pdev =
  3661. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)soc,
  3662. pdev_id);
  3663. if (!pdev)
  3664. return QDF_STATUS_E_FAILURE;
  3665. dp_ipa_aggregate_pdev_stats(pdev);
  3666. qdf_mem_copy(pdev_stats, &pdev->stats, sizeof(struct cdp_pdev_stats));
  3667. return QDF_STATUS_SUCCESS;
  3668. }
  3669. int dp_ipa_txrx_get_vdev_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3670. void *buf, bool is_aggregate)
  3671. {
  3672. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3673. struct cdp_vdev_stats *vdev_stats;
  3674. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3675. DP_MOD_ID_IPA);
  3676. if (!vdev)
  3677. return 1;
  3678. vdev_stats = (struct cdp_vdev_stats *)buf;
  3679. dp_ipa_aggregate_vdev_stats(vdev, buf);
  3680. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3681. return 0;
  3682. }
  3683. QDF_STATUS dp_ipa_txrx_get_peer_stats(struct cdp_soc_t *soc, uint8_t vdev_id,
  3684. uint8_t *peer_mac,
  3685. struct cdp_peer_stats *peer_stats)
  3686. {
  3687. struct dp_peer *peer = NULL;
  3688. struct cdp_peer_info peer_info = { 0 };
  3689. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac, false,
  3690. CDP_WILD_PEER_TYPE);
  3691. peer = dp_peer_hash_find_wrapper((struct dp_soc *)soc, &peer_info,
  3692. DP_MOD_ID_IPA);
  3693. qdf_mem_zero(peer_stats, sizeof(struct cdp_peer_stats));
  3694. if (!peer)
  3695. return QDF_STATUS_E_FAILURE;
  3696. dp_ipa_get_peer_stats(peer, peer_stats);
  3697. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3698. return QDF_STATUS_SUCCESS;
  3699. }
  3700. #endif
  3701. /**
  3702. * dp_ipa_get_wdi_version() - Get WDI version
  3703. * @soc_hdl: data path soc handle
  3704. * @wdi_ver: Out parameter for wdi version
  3705. *
  3706. * Get WDI version based on soc arch
  3707. *
  3708. * Return: None
  3709. */
  3710. void dp_ipa_get_wdi_version(struct cdp_soc_t *soc_hdl, uint8_t *wdi_ver)
  3711. {
  3712. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3713. if (soc->arch_ops.ipa_get_wdi_ver)
  3714. soc->arch_ops.ipa_get_wdi_ver(wdi_ver);
  3715. else
  3716. *wdi_ver = IPA_WDI_3;
  3717. }
  3718. #ifdef IPA_WDI3_TX_TWO_PIPES
  3719. bool dp_ipa_is_ring_ipa_tx(struct dp_soc *soc, uint8_t ring_id)
  3720. {
  3721. if (!soc->wlan_cfg_ctx->ipa_enabled)
  3722. return false;
  3723. return (ring_id == IPA_TCL_DATA_RING_IDX) ||
  3724. ((ring_id == IPA_TX_ALT_RING_IDX) &&
  3725. wlan_cfg_is_ipa_two_tx_pipes_enabled(soc->wlan_cfg_ctx));
  3726. }
  3727. #else
  3728. bool dp_ipa_is_ring_ipa_tx(struct dp_soc *soc, uint8_t ring_id)
  3729. {
  3730. if (!soc->wlan_cfg_ctx->ipa_enabled)
  3731. return false;
  3732. return (ring_id == IPA_TCL_DATA_RING_IDX);
  3733. }
  3734. #endif /* IPA_WDI3_TX_TWO_PIPES */
  3735. #endif