wcd937x.c 91 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <asoc/wcdcal-hwdep.h>
  20. #include <asoc/msm-cdc-pinctrl.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include <asoc/msm-cdc-supply.h>
  23. #include "wcd937x-registers.h"
  24. #include "wcd937x.h"
  25. #include "internal.h"
  26. #define DRV_NAME "wcd937x_codec"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define WCD937X_VARIANT_ENTRY_SIZE 32
  30. #define NUM_SWRS_DT_PARAMS 5
  31. #define WCD937X_VERSION_1_0 1
  32. #define WCD937X_VERSION_ENTRY_SIZE 32
  33. #define EAR_RX_PATH_AUX 1
  34. enum {
  35. CODEC_TX = 0,
  36. CODEC_RX,
  37. };
  38. enum {
  39. ALLOW_BUCK_DISABLE,
  40. HPH_COMP_DELAY,
  41. HPH_PA_DELAY,
  42. AMIC2_BCS_ENABLE,
  43. };
  44. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  45. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  46. static int wcd937x_handle_post_irq(void *data);
  47. static int wcd937x_reset(struct device *dev);
  48. static int wcd937x_reset_low(struct device *dev);
  49. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  50. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  51. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  52. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  53. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  54. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  55. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  56. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  57. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  58. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  59. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  60. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  70. };
  71. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  72. .name = "wcd937x",
  73. .irqs = wcd937x_irqs,
  74. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  75. .num_regs = 3,
  76. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  77. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  78. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  79. .use_ack = 1,
  80. .clear_ack = 1,
  81. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  82. .runtime_pm = false,
  83. .handle_post_irq = wcd937x_handle_post_irq,
  84. .irq_drv_data = NULL,
  85. };
  86. static int wcd937x_handle_post_irq(void *data)
  87. {
  88. struct wcd937x_priv *wcd937x = data;
  89. u32 status1 = 0, status2 = 0, status3 = 0;
  90. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  91. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  92. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  93. wcd937x->tx_swr_dev->slave_irq_pending =
  94. ((status1 || status2 || status3) ? true : false);
  95. return IRQ_HANDLED;
  96. }
  97. static int wcd937x_init_reg(struct snd_soc_component *component)
  98. {
  99. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  100. 0x0E, 0x0E);
  101. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  102. 0x80, 0x80);
  103. usleep_range(1000, 1010);
  104. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  105. 0x40, 0x40);
  106. usleep_range(1000, 1010);
  107. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  108. 0x10, 0x00);
  109. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  110. 0xF0, 0x80);
  111. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  112. 0x80, 0x80);
  113. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  114. 0x40, 0x40);
  115. usleep_range(10000, 10010);
  116. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  117. 0x40, 0x00);
  118. snd_soc_component_update_bits(component,
  119. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  120. 0xFF, 0xD9);
  121. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  122. 0xFF, 0xFA);
  123. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  124. 0xFF, 0xFA);
  125. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  126. 0xFF, 0xFA);
  127. return 0;
  128. }
  129. static int wcd937x_set_port_params(struct snd_soc_component *component,
  130. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  131. u8 *ch_mask, u32 *ch_rate,
  132. u8 *port_type, u8 path)
  133. {
  134. int i, j;
  135. u8 num_ports = 0;
  136. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  137. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  138. switch (path) {
  139. case CODEC_RX:
  140. map = &wcd937x->rx_port_mapping;
  141. num_ports = wcd937x->num_rx_ports;
  142. break;
  143. case CODEC_TX:
  144. map = &wcd937x->tx_port_mapping;
  145. num_ports = wcd937x->num_tx_ports;
  146. break;
  147. }
  148. for (i = 0; i <= num_ports; i++) {
  149. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  150. if ((*map)[i][j].slave_port_type == slv_prt_type)
  151. goto found;
  152. }
  153. }
  154. found:
  155. if (i > num_ports || j == MAX_CH_PER_PORT) {
  156. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  157. __func__, slv_prt_type);
  158. return -EINVAL;
  159. }
  160. *port_id = i;
  161. *num_ch = (*map)[i][j].num_ch;
  162. *ch_mask = (*map)[i][j].ch_mask;
  163. *ch_rate = (*map)[i][j].ch_rate;
  164. *port_type = (*map)[i][j].master_port_type;
  165. return 0;
  166. }
  167. static int wcd937x_parse_port_mapping(struct device *dev,
  168. char *prop, u8 path)
  169. {
  170. u32 *dt_array, map_size, map_length;
  171. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  172. u32 slave_port_type, master_port_type;
  173. u32 i, ch_iter = 0;
  174. int ret = 0;
  175. u8 *num_ports = NULL;
  176. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  177. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  178. switch (path) {
  179. case CODEC_RX:
  180. map = &wcd937x->rx_port_mapping;
  181. num_ports = &wcd937x->num_rx_ports;
  182. break;
  183. case CODEC_TX:
  184. map = &wcd937x->tx_port_mapping;
  185. num_ports = &wcd937x->num_tx_ports;
  186. break;
  187. }
  188. if (!of_find_property(dev->of_node, prop,
  189. &map_size)) {
  190. dev_err(dev, "missing port mapping prop %s\n", prop);
  191. ret = -EINVAL;
  192. goto err;
  193. }
  194. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  195. dt_array = kzalloc(map_size, GFP_KERNEL);
  196. if (!dt_array) {
  197. ret = -ENOMEM;
  198. goto err;
  199. }
  200. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  201. NUM_SWRS_DT_PARAMS * map_length);
  202. if (ret) {
  203. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  204. __func__, prop);
  205. ret = -EINVAL;
  206. goto err_pdata_fail;
  207. }
  208. for (i = 0; i < map_length; i++) {
  209. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  210. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  211. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  212. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  213. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  214. if (port_num != old_port_num)
  215. ch_iter = 0;
  216. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  217. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  218. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  219. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  220. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  221. old_port_num = port_num;
  222. }
  223. *num_ports = port_num;
  224. kfree(dt_array);
  225. return 0;
  226. err_pdata_fail:
  227. kfree(dt_array);
  228. err:
  229. return ret;
  230. }
  231. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  232. u8 slv_port_type, u8 enable)
  233. {
  234. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  235. u8 port_id;
  236. u8 num_ch;
  237. u8 ch_mask;
  238. u32 ch_rate;
  239. u8 ch_type = 0;
  240. int slave_port_idx;
  241. u8 num_port = 1;
  242. int ret = 0;
  243. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  244. &num_ch, &ch_mask, &ch_rate,
  245. &ch_type, CODEC_TX);
  246. if (ret)
  247. return ret;
  248. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  249. if (slave_ch_idx != -EINVAL)
  250. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  251. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  252. __func__, slave_ch_idx, ch_type);
  253. if (enable)
  254. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  255. num_port, &ch_mask, &ch_rate,
  256. &num_ch, &ch_type);
  257. else
  258. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  259. num_port, &ch_mask, &ch_type);
  260. return ret;
  261. }
  262. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  263. u8 slv_port_type, u8 enable)
  264. {
  265. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  266. u8 port_id;
  267. u8 num_ch;
  268. u8 ch_mask;
  269. u32 ch_rate;
  270. u8 port_type;
  271. u8 num_port = 1;
  272. int ret = 0;
  273. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  274. &num_ch, &ch_mask, &ch_rate,
  275. &port_type, CODEC_RX);
  276. if (ret)
  277. return ret;
  278. if (enable)
  279. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  280. num_port, &ch_mask, &ch_rate,
  281. &num_ch, &port_type);
  282. else
  283. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  284. num_port, &ch_mask, &port_type);
  285. return ret;
  286. }
  287. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  288. {
  289. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  290. if (wcd937x->rx_clk_cnt == 0) {
  291. snd_soc_component_update_bits(component,
  292. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  293. snd_soc_component_update_bits(component,
  294. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  295. snd_soc_component_update_bits(component,
  296. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  297. snd_soc_component_update_bits(component,
  298. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  299. snd_soc_component_update_bits(component,
  300. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  301. snd_soc_component_update_bits(component,
  302. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  303. snd_soc_component_update_bits(component,
  304. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  305. }
  306. wcd937x->rx_clk_cnt++;
  307. return 0;
  308. }
  309. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  310. {
  311. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  312. if (wcd937x->rx_clk_cnt == 0) {
  313. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  314. return 0;
  315. }
  316. wcd937x->rx_clk_cnt--;
  317. if (wcd937x->rx_clk_cnt == 0) {
  318. snd_soc_component_update_bits(component,
  319. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  320. snd_soc_component_update_bits(component,
  321. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  322. 0x02, 0x00);
  323. snd_soc_component_update_bits(component,
  324. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  325. 0x01, 0x00);
  326. }
  327. return 0;
  328. }
  329. /*
  330. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  331. * @component: handle to snd_soc_component *
  332. *
  333. * return wcd937x_mbhc handle or error code in case of failure
  334. */
  335. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  336. {
  337. struct wcd937x_priv *wcd937x;
  338. if (!component) {
  339. pr_err("%s: Invalid params, NULL component\n", __func__);
  340. return NULL;
  341. }
  342. wcd937x = snd_soc_component_get_drvdata(component);
  343. if (!wcd937x) {
  344. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  345. return NULL;
  346. }
  347. return wcd937x->mbhc;
  348. }
  349. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  350. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  351. struct snd_kcontrol *kcontrol,
  352. int event)
  353. {
  354. struct snd_soc_component *component =
  355. snd_soc_dapm_to_component(w->dapm);
  356. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  357. int hph_mode = wcd937x->hph_mode;
  358. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  359. w->name, event);
  360. switch (event) {
  361. case SND_SOC_DAPM_PRE_PMU:
  362. wcd937x_rx_clk_enable(component);
  363. snd_soc_component_update_bits(component,
  364. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  365. 0x01, 0x01);
  366. snd_soc_component_update_bits(component,
  367. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  368. 0x04, 0x04);
  369. snd_soc_component_update_bits(component,
  370. WCD937X_HPH_RDAC_CLK_CTL1,
  371. 0x80, 0x00);
  372. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  373. break;
  374. case SND_SOC_DAPM_POST_PMU:
  375. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  376. snd_soc_component_update_bits(component,
  377. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  378. 0x0F, 0x02);
  379. else if (hph_mode == CLS_H_LOHIFI)
  380. snd_soc_component_update_bits(component,
  381. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  382. 0x0F, 0x06);
  383. if (wcd937x->comp1_enable) {
  384. snd_soc_component_update_bits(component,
  385. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  386. 0x02, 0x02);
  387. snd_soc_component_update_bits(component,
  388. WCD937X_HPH_L_EN, 0x20, 0x00);
  389. if (wcd937x->comp2_enable) {
  390. snd_soc_component_update_bits(component,
  391. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  392. 0x01, 0x01);
  393. snd_soc_component_update_bits(component,
  394. WCD937X_HPH_R_EN, 0x20, 0x00);
  395. }
  396. /*
  397. * 5ms sleep is required after COMP is enabled as per
  398. * HW requirement
  399. */
  400. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  401. usleep_range(5000, 5100);
  402. clear_bit(HPH_COMP_DELAY,
  403. &wcd937x->status_mask);
  404. }
  405. } else {
  406. snd_soc_component_update_bits(component,
  407. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  408. 0x02, 0x00);
  409. snd_soc_component_update_bits(component,
  410. WCD937X_HPH_L_EN, 0x20, 0x20);
  411. }
  412. snd_soc_component_update_bits(component,
  413. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  414. break;
  415. case SND_SOC_DAPM_POST_PMD:
  416. snd_soc_component_update_bits(component,
  417. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  418. 0x0F, 0x01);
  419. break;
  420. }
  421. return 0;
  422. }
  423. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  424. struct snd_kcontrol *kcontrol,
  425. int event)
  426. {
  427. struct snd_soc_component *component =
  428. snd_soc_dapm_to_component(w->dapm);
  429. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  430. int hph_mode = wcd937x->hph_mode;
  431. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  432. w->name, event);
  433. switch (event) {
  434. case SND_SOC_DAPM_PRE_PMU:
  435. wcd937x_rx_clk_enable(component);
  436. snd_soc_component_update_bits(component,
  437. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  438. snd_soc_component_update_bits(component,
  439. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  440. snd_soc_component_update_bits(component,
  441. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  442. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  443. break;
  444. case SND_SOC_DAPM_POST_PMU:
  445. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  446. snd_soc_component_update_bits(component,
  447. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  448. 0x0F, 0x02);
  449. else if (hph_mode == CLS_H_LOHIFI)
  450. snd_soc_component_update_bits(component,
  451. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  452. 0x0F, 0x06);
  453. if (wcd937x->comp2_enable) {
  454. snd_soc_component_update_bits(component,
  455. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  456. 0x01, 0x01);
  457. snd_soc_component_update_bits(component,
  458. WCD937X_HPH_R_EN, 0x20, 0x00);
  459. if (wcd937x->comp1_enable) {
  460. snd_soc_component_update_bits(component,
  461. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  462. 0x02, 0x02);
  463. snd_soc_component_update_bits(component,
  464. WCD937X_HPH_L_EN, 0x20, 0x00);
  465. }
  466. /*
  467. * 5ms sleep is required after COMP is enabled as per
  468. * HW requirement
  469. */
  470. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  471. usleep_range(5000, 5100);
  472. clear_bit(HPH_COMP_DELAY,
  473. &wcd937x->status_mask);
  474. }
  475. } else {
  476. snd_soc_component_update_bits(component,
  477. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  478. 0x01, 0x00);
  479. snd_soc_component_update_bits(component,
  480. WCD937X_HPH_R_EN, 0x20, 0x20);
  481. }
  482. snd_soc_component_update_bits(component,
  483. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  484. break;
  485. case SND_SOC_DAPM_POST_PMD:
  486. snd_soc_component_update_bits(component,
  487. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  488. 0x0F, 0x01);
  489. break;
  490. }
  491. return 0;
  492. }
  493. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  494. struct snd_kcontrol *kcontrol,
  495. int event)
  496. {
  497. struct snd_soc_component *component =
  498. snd_soc_dapm_to_component(w->dapm);
  499. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  500. int hph_mode = wcd937x->hph_mode;
  501. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  502. w->name, event);
  503. switch (event) {
  504. case SND_SOC_DAPM_PRE_PMU:
  505. wcd937x_rx_clk_enable(component);
  506. snd_soc_component_update_bits(component,
  507. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  508. 0x04, 0x04);
  509. snd_soc_component_update_bits(component,
  510. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  511. 0x01, 0x01);
  512. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  513. snd_soc_component_update_bits(component,
  514. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  515. 0x0F, 0x02);
  516. else if (hph_mode == CLS_H_LOHIFI)
  517. snd_soc_component_update_bits(component,
  518. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  519. 0x0F, 0x06);
  520. snd_soc_component_update_bits(component,
  521. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  522. 0x02, 0x02);
  523. usleep_range(5000, 5010);
  524. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  525. 0x04, 0x00);
  526. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  527. WCD_CLSH_EVENT_PRE_DAC,
  528. WCD_CLSH_STATE_EAR,
  529. hph_mode);
  530. break;
  531. case SND_SOC_DAPM_POST_PMD:
  532. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  533. hph_mode == CLS_H_HIFI)
  534. snd_soc_component_update_bits(component,
  535. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  536. 0x0F, 0x01);
  537. break;
  538. };
  539. return 0;
  540. }
  541. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  542. struct snd_kcontrol *kcontrol,
  543. int event)
  544. {
  545. struct snd_soc_component *component =
  546. snd_soc_dapm_to_component(w->dapm);
  547. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  548. int hph_mode = wcd937x->hph_mode;
  549. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  550. w->name, event);
  551. switch (event) {
  552. case SND_SOC_DAPM_PRE_PMU:
  553. wcd937x_rx_clk_enable(component);
  554. snd_soc_component_update_bits(component,
  555. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  556. 0x04, 0x04);
  557. snd_soc_component_update_bits(component,
  558. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  559. 0x04, 0x04);
  560. snd_soc_component_update_bits(component,
  561. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  562. 0x01, 0x01);
  563. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  564. WCD_CLSH_EVENT_PRE_DAC,
  565. WCD_CLSH_STATE_AUX,
  566. hph_mode);
  567. break;
  568. case SND_SOC_DAPM_POST_PMD:
  569. snd_soc_component_update_bits(component,
  570. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  571. 0x04, 0x00);
  572. break;
  573. };
  574. return 0;
  575. }
  576. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  577. struct snd_kcontrol *kcontrol,
  578. int event)
  579. {
  580. struct snd_soc_component *component =
  581. snd_soc_dapm_to_component(w->dapm);
  582. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  583. int ret = 0;
  584. int hph_mode = wcd937x->hph_mode;
  585. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  586. w->name, event);
  587. switch (event) {
  588. case SND_SOC_DAPM_PRE_PMU:
  589. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  590. wcd937x->rx_swr_dev->dev_num,
  591. true);
  592. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  593. WCD_CLSH_EVENT_PRE_DAC,
  594. WCD_CLSH_STATE_HPHR,
  595. hph_mode);
  596. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  597. 0x10, 0x10);
  598. usleep_range(100, 110);
  599. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  600. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  601. wcd937x->rx_swr_dev->dev_num,
  602. true);
  603. snd_soc_component_update_bits(component,
  604. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  605. break;
  606. case SND_SOC_DAPM_POST_PMU:
  607. /*
  608. * 7ms sleep is required after PA is enabled as per
  609. * HW requirement. If compander is disabled, then
  610. * 20ms delay is required.
  611. */
  612. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  613. if (!wcd937x->comp2_enable)
  614. usleep_range(20000, 20100);
  615. else
  616. usleep_range(7000, 7100);
  617. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  618. }
  619. snd_soc_component_update_bits(component,
  620. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  621. 0x02, 0x02);
  622. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  623. snd_soc_component_update_bits(component,
  624. WCD937X_ANA_RX_SUPPLIES,
  625. 0x02, 0x02);
  626. if (wcd937x->update_wcd_event)
  627. wcd937x->update_wcd_event(wcd937x->handle,
  628. WCD_BOLERO_EVT_RX_MUTE,
  629. (WCD_RX2 << 0x10));
  630. wcd_enable_irq(&wcd937x->irq_info,
  631. WCD937X_IRQ_HPHR_PDM_WD_INT);
  632. break;
  633. case SND_SOC_DAPM_PRE_PMD:
  634. wcd_disable_irq(&wcd937x->irq_info,
  635. WCD937X_IRQ_HPHR_PDM_WD_INT);
  636. if (wcd937x->update_wcd_event)
  637. wcd937x->update_wcd_event(wcd937x->handle,
  638. WCD_BOLERO_EVT_RX_MUTE,
  639. (WCD_RX2 << 0x10 | 0x1));
  640. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  641. WCD_EVENT_PRE_HPHR_PA_OFF,
  642. &wcd937x->mbhc->wcd_mbhc);
  643. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  644. break;
  645. case SND_SOC_DAPM_POST_PMD:
  646. /*
  647. * 7ms sleep is required after PA is disabled as per
  648. * HW requirement. If compander is disabled, then
  649. * 20ms delay is required.
  650. */
  651. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  652. if (!wcd937x->comp2_enable)
  653. usleep_range(20000, 20100);
  654. else
  655. usleep_range(7000, 7100);
  656. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  657. }
  658. snd_soc_component_update_bits(component,
  659. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  660. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  661. WCD_EVENT_POST_HPHR_PA_OFF,
  662. &wcd937x->mbhc->wcd_mbhc);
  663. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  664. 0x10, 0x00);
  665. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  666. WCD_CLSH_EVENT_POST_PA,
  667. WCD_CLSH_STATE_HPHR,
  668. hph_mode);
  669. break;
  670. };
  671. return ret;
  672. }
  673. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  674. struct snd_kcontrol *kcontrol,
  675. int event)
  676. {
  677. struct snd_soc_component *component =
  678. snd_soc_dapm_to_component(w->dapm);
  679. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  680. int ret = 0;
  681. int hph_mode = wcd937x->hph_mode;
  682. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  683. w->name, event);
  684. switch (event) {
  685. case SND_SOC_DAPM_PRE_PMU:
  686. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  687. wcd937x->rx_swr_dev->dev_num,
  688. true);
  689. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  690. WCD_CLSH_EVENT_PRE_DAC,
  691. WCD_CLSH_STATE_HPHL,
  692. hph_mode);
  693. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  694. 0x20, 0x20);
  695. usleep_range(100, 110);
  696. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  697. snd_soc_component_update_bits(component,
  698. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  699. break;
  700. case SND_SOC_DAPM_POST_PMU:
  701. /*
  702. * 7ms sleep is required after PA is enabled as per
  703. * HW requirement. If compander is disabled, then
  704. * 20ms delay is required.
  705. */
  706. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  707. if (!wcd937x->comp1_enable)
  708. usleep_range(20000, 20100);
  709. else
  710. usleep_range(7000, 7100);
  711. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  712. }
  713. snd_soc_component_update_bits(component,
  714. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  715. 0x02, 0x02);
  716. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  717. snd_soc_component_update_bits(component,
  718. WCD937X_ANA_RX_SUPPLIES,
  719. 0x02, 0x02);
  720. if (wcd937x->update_wcd_event)
  721. wcd937x->update_wcd_event(wcd937x->handle,
  722. WCD_BOLERO_EVT_RX_MUTE,
  723. (WCD_RX1 << 0x10));
  724. wcd_enable_irq(&wcd937x->irq_info,
  725. WCD937X_IRQ_HPHL_PDM_WD_INT);
  726. break;
  727. case SND_SOC_DAPM_PRE_PMD:
  728. wcd_disable_irq(&wcd937x->irq_info,
  729. WCD937X_IRQ_HPHL_PDM_WD_INT);
  730. if (wcd937x->update_wcd_event)
  731. wcd937x->update_wcd_event(wcd937x->handle,
  732. WCD_BOLERO_EVT_RX_MUTE,
  733. (WCD_RX1 << 0x10 | 0x1));
  734. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  735. WCD_EVENT_PRE_HPHL_PA_OFF,
  736. &wcd937x->mbhc->wcd_mbhc);
  737. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  738. break;
  739. case SND_SOC_DAPM_POST_PMD:
  740. /*
  741. * 7ms sleep is required after PA is disabled as per
  742. * HW requirement. If compander is disabled, then
  743. * 20ms delay is required.
  744. */
  745. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  746. if (!wcd937x->comp1_enable)
  747. usleep_range(20000, 20100);
  748. else
  749. usleep_range(7000, 7100);
  750. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  751. }
  752. snd_soc_component_update_bits(component,
  753. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  754. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  755. WCD_EVENT_POST_HPHL_PA_OFF,
  756. &wcd937x->mbhc->wcd_mbhc);
  757. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  758. 0x20, 0x00);
  759. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  760. WCD_CLSH_EVENT_POST_PA,
  761. WCD_CLSH_STATE_HPHL,
  762. hph_mode);
  763. break;
  764. };
  765. return ret;
  766. }
  767. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  768. struct snd_kcontrol *kcontrol,
  769. int event)
  770. {
  771. struct snd_soc_component *component =
  772. snd_soc_dapm_to_component(w->dapm);
  773. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  774. int hph_mode = wcd937x->hph_mode;
  775. int ret = 0;
  776. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  777. w->name, event);
  778. switch (event) {
  779. case SND_SOC_DAPM_PRE_PMU:
  780. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  781. wcd937x->rx_swr_dev->dev_num,
  782. true);
  783. snd_soc_component_update_bits(component,
  784. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  785. break;
  786. case SND_SOC_DAPM_POST_PMU:
  787. usleep_range(1000, 1010);
  788. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  789. snd_soc_component_update_bits(component,
  790. WCD937X_ANA_RX_SUPPLIES,
  791. 0x02, 0x02);
  792. if (wcd937x->update_wcd_event)
  793. wcd937x->update_wcd_event(wcd937x->handle,
  794. WCD_BOLERO_EVT_RX_MUTE,
  795. (WCD_RX3 << 0x10));
  796. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  797. break;
  798. case SND_SOC_DAPM_PRE_PMD:
  799. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  800. if (wcd937x->update_wcd_event)
  801. wcd937x->update_wcd_event(wcd937x->handle,
  802. WCD_BOLERO_EVT_RX_MUTE,
  803. (WCD_RX3 << 0x10 | 0x1));
  804. break;
  805. case SND_SOC_DAPM_POST_PMD:
  806. /* Add delay as per hw requirement */
  807. usleep_range(2000, 2010);
  808. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  809. WCD_CLSH_EVENT_POST_PA,
  810. WCD_CLSH_STATE_AUX,
  811. hph_mode);
  812. snd_soc_component_update_bits(component,
  813. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  814. break;
  815. };
  816. return ret;
  817. }
  818. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  819. struct snd_kcontrol *kcontrol,
  820. int event)
  821. {
  822. struct snd_soc_component *component =
  823. snd_soc_dapm_to_component(w->dapm);
  824. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  825. int hph_mode = wcd937x->hph_mode;
  826. int ret = 0;
  827. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  828. w->name, event);
  829. switch (event) {
  830. case SND_SOC_DAPM_PRE_PMU:
  831. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  832. wcd937x->rx_swr_dev->dev_num,
  833. true);
  834. /*
  835. * Enable watchdog interrupt for HPHL or AUX
  836. * depending on mux value
  837. */
  838. wcd937x->ear_rx_path =
  839. snd_soc_component_read32(
  840. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  841. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  842. snd_soc_component_update_bits(component,
  843. WCD937X_DIGITAL_PDM_WD_CTL2,
  844. 0x05, 0x05);
  845. else
  846. snd_soc_component_update_bits(component,
  847. WCD937X_DIGITAL_PDM_WD_CTL0,
  848. 0x17, 0x13);
  849. if (!wcd937x->comp1_enable)
  850. snd_soc_component_update_bits(component,
  851. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  852. break;
  853. case SND_SOC_DAPM_POST_PMU:
  854. usleep_range(6000, 6010);
  855. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  856. snd_soc_component_update_bits(component,
  857. WCD937X_ANA_RX_SUPPLIES,
  858. 0x02, 0x02);
  859. if (wcd937x->update_wcd_event)
  860. wcd937x->update_wcd_event(wcd937x->handle,
  861. WCD_BOLERO_EVT_RX_MUTE,
  862. (WCD_RX1 << 0x10));
  863. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  864. wcd_enable_irq(&wcd937x->irq_info,
  865. WCD937X_IRQ_AUX_PDM_WD_INT);
  866. else
  867. wcd_enable_irq(&wcd937x->irq_info,
  868. WCD937X_IRQ_HPHL_PDM_WD_INT);
  869. break;
  870. case SND_SOC_DAPM_PRE_PMD:
  871. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  872. wcd_disable_irq(&wcd937x->irq_info,
  873. WCD937X_IRQ_AUX_PDM_WD_INT);
  874. else
  875. wcd_disable_irq(&wcd937x->irq_info,
  876. WCD937X_IRQ_HPHL_PDM_WD_INT);
  877. if (wcd937x->update_wcd_event)
  878. wcd937x->update_wcd_event(wcd937x->handle,
  879. WCD_BOLERO_EVT_RX_MUTE,
  880. (WCD_RX1 << 0x10 | 0x1));
  881. break;
  882. case SND_SOC_DAPM_POST_PMD:
  883. if (!wcd937x->comp1_enable)
  884. snd_soc_component_update_bits(component,
  885. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  886. usleep_range(7000, 7010);
  887. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  888. WCD_CLSH_EVENT_POST_PA,
  889. WCD_CLSH_STATE_EAR,
  890. hph_mode);
  891. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  892. 0x04, 0x04);
  893. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  894. snd_soc_component_update_bits(component,
  895. WCD937X_DIGITAL_PDM_WD_CTL2,
  896. 0x05, 0x00);
  897. else
  898. snd_soc_component_update_bits(component,
  899. WCD937X_DIGITAL_PDM_WD_CTL0,
  900. 0x17, 0x00);
  901. break;
  902. };
  903. return ret;
  904. }
  905. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  906. struct snd_kcontrol *kcontrol,
  907. int event)
  908. {
  909. struct snd_soc_component *component =
  910. snd_soc_dapm_to_component(w->dapm);
  911. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  912. int mode = wcd937x->hph_mode;
  913. int ret = 0;
  914. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  915. w->name, event);
  916. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  917. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  918. wcd937x_rx_connect_port(component, CLSH,
  919. SND_SOC_DAPM_EVENT_ON(event));
  920. }
  921. if (SND_SOC_DAPM_EVENT_OFF(event))
  922. ret = swr_slvdev_datapath_control(
  923. wcd937x->rx_swr_dev,
  924. wcd937x->rx_swr_dev->dev_num,
  925. false);
  926. return ret;
  927. }
  928. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  929. struct snd_kcontrol *kcontrol,
  930. int event)
  931. {
  932. struct snd_soc_component *component =
  933. snd_soc_dapm_to_component(w->dapm);
  934. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  935. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  936. w->name, event);
  937. switch (event) {
  938. case SND_SOC_DAPM_PRE_PMU:
  939. wcd937x_rx_connect_port(component, HPH_L, true);
  940. if (wcd937x->comp1_enable)
  941. wcd937x_rx_connect_port(component, COMP_L, true);
  942. break;
  943. case SND_SOC_DAPM_POST_PMD:
  944. wcd937x_rx_connect_port(component, HPH_L, false);
  945. if (wcd937x->comp1_enable)
  946. wcd937x_rx_connect_port(component, COMP_L, false);
  947. wcd937x_rx_clk_disable(component);
  948. snd_soc_component_update_bits(component,
  949. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  950. 0x01, 0x00);
  951. break;
  952. };
  953. return 0;
  954. }
  955. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  956. struct snd_kcontrol *kcontrol, int event)
  957. {
  958. struct snd_soc_component *component =
  959. snd_soc_dapm_to_component(w->dapm);
  960. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  961. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  962. w->name, event);
  963. switch (event) {
  964. case SND_SOC_DAPM_PRE_PMU:
  965. wcd937x_rx_connect_port(component, HPH_R, true);
  966. if (wcd937x->comp2_enable)
  967. wcd937x_rx_connect_port(component, COMP_R, true);
  968. break;
  969. case SND_SOC_DAPM_POST_PMD:
  970. wcd937x_rx_connect_port(component, HPH_R, false);
  971. if (wcd937x->comp2_enable)
  972. wcd937x_rx_connect_port(component, COMP_R, false);
  973. wcd937x_rx_clk_disable(component);
  974. snd_soc_component_update_bits(component,
  975. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  976. 0x02, 0x00);
  977. break;
  978. };
  979. return 0;
  980. }
  981. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  982. struct snd_kcontrol *kcontrol,
  983. int event)
  984. {
  985. struct snd_soc_component *component =
  986. snd_soc_dapm_to_component(w->dapm);
  987. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  988. w->name, event);
  989. switch (event) {
  990. case SND_SOC_DAPM_PRE_PMU:
  991. wcd937x_rx_connect_port(component, LO, true);
  992. break;
  993. case SND_SOC_DAPM_POST_PMD:
  994. wcd937x_rx_connect_port(component, LO, false);
  995. usleep_range(6000, 6010);
  996. wcd937x_rx_clk_disable(component);
  997. snd_soc_component_update_bits(component,
  998. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  999. break;
  1000. }
  1001. return 0;
  1002. }
  1003. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1004. struct snd_kcontrol *kcontrol,
  1005. int event)
  1006. {
  1007. struct snd_soc_component *component =
  1008. snd_soc_dapm_to_component(w->dapm);
  1009. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1010. u16 dmic_clk_reg;
  1011. s32 *dmic_clk_cnt;
  1012. unsigned int dmic;
  1013. char *wname;
  1014. int ret = 0;
  1015. wname = strpbrk(w->name, "012345");
  1016. if (!wname) {
  1017. dev_err(component->dev, "%s: widget not found\n", __func__);
  1018. return -EINVAL;
  1019. }
  1020. ret = kstrtouint(wname, 10, &dmic);
  1021. if (ret < 0) {
  1022. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1023. __func__);
  1024. return -EINVAL;
  1025. }
  1026. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1027. w->name, event);
  1028. switch (dmic) {
  1029. case 0:
  1030. case 1:
  1031. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1032. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1033. break;
  1034. case 2:
  1035. case 3:
  1036. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1037. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1038. break;
  1039. case 4:
  1040. case 5:
  1041. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1042. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1043. break;
  1044. default:
  1045. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1046. __func__);
  1047. return -EINVAL;
  1048. };
  1049. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1050. __func__, event, dmic, *dmic_clk_cnt);
  1051. switch (event) {
  1052. case SND_SOC_DAPM_PRE_PMU:
  1053. snd_soc_component_update_bits(component,
  1054. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1055. snd_soc_component_update_bits(component,
  1056. dmic_clk_reg, 0x07, 0x02);
  1057. snd_soc_component_update_bits(component,
  1058. dmic_clk_reg, 0x08, 0x08);
  1059. snd_soc_component_update_bits(component,
  1060. dmic_clk_reg, 0x70, 0x20);
  1061. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1062. break;
  1063. case SND_SOC_DAPM_POST_PMD:
  1064. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1065. break;
  1066. };
  1067. return 0;
  1068. }
  1069. /*
  1070. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1071. * @micb_mv: micbias in mv
  1072. *
  1073. * return register value converted
  1074. */
  1075. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1076. {
  1077. /* min micbias voltage is 1V and maximum is 2.85V */
  1078. if (micb_mv < 1000 || micb_mv > 2850) {
  1079. pr_err("%s: unsupported micbias voltage\n", __func__);
  1080. return -EINVAL;
  1081. }
  1082. return (micb_mv - 1000) / 50;
  1083. }
  1084. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1085. /*
  1086. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1087. * @component: handle to snd_soc_component *
  1088. * @req_volt: micbias voltage to be set
  1089. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1090. *
  1091. * return 0 if adjustment is success or error code in case of failure
  1092. */
  1093. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1094. int req_volt, int micb_num)
  1095. {
  1096. struct wcd937x_priv *wcd937x =
  1097. snd_soc_component_get_drvdata(component);
  1098. int cur_vout_ctl, req_vout_ctl;
  1099. int micb_reg, micb_val, micb_en;
  1100. int ret = 0;
  1101. switch (micb_num) {
  1102. case MIC_BIAS_1:
  1103. micb_reg = WCD937X_ANA_MICB1;
  1104. break;
  1105. case MIC_BIAS_2:
  1106. micb_reg = WCD937X_ANA_MICB2;
  1107. break;
  1108. case MIC_BIAS_3:
  1109. micb_reg = WCD937X_ANA_MICB3;
  1110. break;
  1111. default:
  1112. return -EINVAL;
  1113. }
  1114. mutex_lock(&wcd937x->micb_lock);
  1115. /*
  1116. * If requested micbias voltage is same as current micbias
  1117. * voltage, then just return. Otherwise, adjust voltage as
  1118. * per requested value. If micbias is already enabled, then
  1119. * to avoid slow micbias ramp-up or down enable pull-up
  1120. * momentarily, change the micbias value and then re-enable
  1121. * micbias.
  1122. */
  1123. micb_val = snd_soc_component_read32(component, micb_reg);
  1124. micb_en = (micb_val & 0xC0) >> 6;
  1125. cur_vout_ctl = micb_val & 0x3F;
  1126. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1127. if (req_vout_ctl < 0) {
  1128. ret = -EINVAL;
  1129. goto exit;
  1130. }
  1131. if (cur_vout_ctl == req_vout_ctl) {
  1132. ret = 0;
  1133. goto exit;
  1134. }
  1135. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1136. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1137. req_volt, micb_en);
  1138. if (micb_en == 0x1)
  1139. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1140. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1141. if (micb_en == 0x1) {
  1142. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1143. /*
  1144. * Add 2ms delay as per HW requirement after enabling
  1145. * micbias
  1146. */
  1147. usleep_range(2000, 2100);
  1148. }
  1149. exit:
  1150. mutex_unlock(&wcd937x->micb_lock);
  1151. return ret;
  1152. }
  1153. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1154. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1155. struct snd_kcontrol *kcontrol,
  1156. int event)
  1157. {
  1158. struct snd_soc_component *component =
  1159. snd_soc_dapm_to_component(w->dapm);
  1160. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1161. int ret = 0;
  1162. switch (event) {
  1163. case SND_SOC_DAPM_PRE_PMU:
  1164. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1165. wcd937x->tx_swr_dev->dev_num,
  1166. true);
  1167. break;
  1168. case SND_SOC_DAPM_POST_PMD:
  1169. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1170. wcd937x->tx_swr_dev->dev_num,
  1171. false);
  1172. break;
  1173. };
  1174. return ret;
  1175. }
  1176. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1177. struct snd_kcontrol *kcontrol,
  1178. int event){
  1179. struct snd_soc_component *component =
  1180. snd_soc_dapm_to_component(w->dapm);
  1181. struct wcd937x_priv *wcd937x =
  1182. snd_soc_component_get_drvdata(component);
  1183. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1184. w->name, event);
  1185. switch (event) {
  1186. case SND_SOC_DAPM_PRE_PMU:
  1187. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1188. wcd937x->ana_clk_count++;
  1189. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1190. snd_soc_component_update_bits(component,
  1191. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1192. snd_soc_component_update_bits(component,
  1193. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1194. snd_soc_component_update_bits(component,
  1195. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1196. /* Enable BCS for Headset mic */
  1197. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1198. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1199. wcd937x_tx_connect_port(component, MBHC, true);
  1200. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1201. }
  1202. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1203. break;
  1204. case SND_SOC_DAPM_POST_PMD:
  1205. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1206. if (w->shift == 1 &&
  1207. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1208. wcd937x_tx_connect_port(component, MBHC, false);
  1209. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1210. }
  1211. snd_soc_component_update_bits(component,
  1212. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1213. break;
  1214. };
  1215. return 0;
  1216. }
  1217. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1218. struct snd_kcontrol *kcontrol, int event)
  1219. {
  1220. struct snd_soc_component *component =
  1221. snd_soc_dapm_to_component(w->dapm);
  1222. struct wcd937x_priv *wcd937x =
  1223. snd_soc_component_get_drvdata(component);
  1224. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1225. w->name, event);
  1226. switch (event) {
  1227. case SND_SOC_DAPM_PRE_PMU:
  1228. snd_soc_component_update_bits(component,
  1229. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1230. snd_soc_component_update_bits(component,
  1231. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1232. snd_soc_component_update_bits(component,
  1233. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1234. snd_soc_component_update_bits(component,
  1235. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1236. snd_soc_component_update_bits(component,
  1237. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1238. snd_soc_component_update_bits(component,
  1239. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1240. snd_soc_component_update_bits(component,
  1241. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1242. snd_soc_component_update_bits(component,
  1243. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1244. snd_soc_component_update_bits(component,
  1245. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1246. break;
  1247. case SND_SOC_DAPM_POST_PMD:
  1248. snd_soc_component_update_bits(component,
  1249. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1250. snd_soc_component_update_bits(component,
  1251. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1252. snd_soc_component_update_bits(component,
  1253. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1254. snd_soc_component_update_bits(component,
  1255. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1256. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1257. wcd937x->ana_clk_count--;
  1258. if (wcd937x->ana_clk_count <= 0) {
  1259. snd_soc_component_update_bits(component,
  1260. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1261. wcd937x->ana_clk_count = 0;
  1262. }
  1263. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1264. snd_soc_component_update_bits(component,
  1265. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1266. break;
  1267. };
  1268. return 0;
  1269. }
  1270. int wcd937x_micbias_control(struct snd_soc_component *component,
  1271. int micb_num, int req, bool is_dapm)
  1272. {
  1273. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1274. int micb_index = micb_num - 1;
  1275. u16 micb_reg;
  1276. int pre_off_event = 0, post_off_event = 0;
  1277. int post_on_event = 0, post_dapm_off = 0;
  1278. int post_dapm_on = 0;
  1279. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1280. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1281. __func__, micb_index);
  1282. return -EINVAL;
  1283. }
  1284. switch (micb_num) {
  1285. case MIC_BIAS_1:
  1286. micb_reg = WCD937X_ANA_MICB1;
  1287. break;
  1288. case MIC_BIAS_2:
  1289. micb_reg = WCD937X_ANA_MICB2;
  1290. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1291. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1292. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1293. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1294. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1295. break;
  1296. case MIC_BIAS_3:
  1297. micb_reg = WCD937X_ANA_MICB3;
  1298. break;
  1299. default:
  1300. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1301. __func__, micb_num);
  1302. return -EINVAL;
  1303. };
  1304. mutex_lock(&wcd937x->micb_lock);
  1305. switch (req) {
  1306. case MICB_PULLUP_ENABLE:
  1307. wcd937x->pullup_ref[micb_index]++;
  1308. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1309. (wcd937x->micb_ref[micb_index] == 0))
  1310. snd_soc_component_update_bits(component, micb_reg,
  1311. 0xC0, 0x80);
  1312. break;
  1313. case MICB_PULLUP_DISABLE:
  1314. if (wcd937x->pullup_ref[micb_index] > 0)
  1315. wcd937x->pullup_ref[micb_index]--;
  1316. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1317. (wcd937x->micb_ref[micb_index] == 0))
  1318. snd_soc_component_update_bits(component, micb_reg,
  1319. 0xC0, 0x00);
  1320. break;
  1321. case MICB_ENABLE:
  1322. wcd937x->micb_ref[micb_index]++;
  1323. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1324. wcd937x->ana_clk_count++;
  1325. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1326. if (wcd937x->micb_ref[micb_index] == 1) {
  1327. snd_soc_component_update_bits(component,
  1328. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1329. snd_soc_component_update_bits(component,
  1330. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1331. snd_soc_component_update_bits(component,
  1332. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1333. snd_soc_component_update_bits(component,
  1334. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1335. snd_soc_component_update_bits(component,
  1336. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1337. snd_soc_component_update_bits(component,
  1338. micb_reg, 0xC0, 0x40);
  1339. if (post_on_event)
  1340. blocking_notifier_call_chain(
  1341. &wcd937x->mbhc->notifier, post_on_event,
  1342. &wcd937x->mbhc->wcd_mbhc);
  1343. }
  1344. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1345. blocking_notifier_call_chain(
  1346. &wcd937x->mbhc->notifier, post_dapm_on,
  1347. &wcd937x->mbhc->wcd_mbhc);
  1348. break;
  1349. case MICB_DISABLE:
  1350. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1351. wcd937x->ana_clk_count--;
  1352. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1353. if (wcd937x->micb_ref[micb_index] > 0)
  1354. wcd937x->micb_ref[micb_index]--;
  1355. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1356. (wcd937x->pullup_ref[micb_index] > 0))
  1357. snd_soc_component_update_bits(component, micb_reg,
  1358. 0xC0, 0x80);
  1359. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1360. (wcd937x->pullup_ref[micb_index] == 0)) {
  1361. if (pre_off_event && wcd937x->mbhc)
  1362. blocking_notifier_call_chain(
  1363. &wcd937x->mbhc->notifier, pre_off_event,
  1364. &wcd937x->mbhc->wcd_mbhc);
  1365. snd_soc_component_update_bits(component, micb_reg,
  1366. 0xC0, 0x00);
  1367. if (post_off_event && wcd937x->mbhc)
  1368. blocking_notifier_call_chain(
  1369. &wcd937x->mbhc->notifier,
  1370. post_off_event,
  1371. &wcd937x->mbhc->wcd_mbhc);
  1372. }
  1373. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1374. if (wcd937x->ana_clk_count <= 0) {
  1375. snd_soc_component_update_bits(component,
  1376. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1377. 0x10, 0x00);
  1378. wcd937x->ana_clk_count = 0;
  1379. }
  1380. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1381. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1382. blocking_notifier_call_chain(
  1383. &wcd937x->mbhc->notifier, post_dapm_off,
  1384. &wcd937x->mbhc->wcd_mbhc);
  1385. break;
  1386. };
  1387. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1388. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1389. wcd937x->pullup_ref[micb_index]);
  1390. mutex_unlock(&wcd937x->micb_lock);
  1391. return 0;
  1392. }
  1393. EXPORT_SYMBOL(wcd937x_micbias_control);
  1394. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1395. bool bcs_disable)
  1396. {
  1397. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1398. if (wcd937x->update_wcd_event) {
  1399. if (bcs_disable)
  1400. wcd937x->update_wcd_event(wcd937x->handle,
  1401. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1402. else
  1403. wcd937x->update_wcd_event(wcd937x->handle,
  1404. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1405. }
  1406. }
  1407. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1408. {
  1409. int ret = 0;
  1410. uint8_t devnum = 0;
  1411. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1412. if (ret) {
  1413. dev_err(&swr_dev->dev,
  1414. "%s get devnum %d for dev addr %lx failed\n",
  1415. __func__, devnum, swr_dev->addr);
  1416. return ret;
  1417. }
  1418. swr_dev->dev_num = devnum;
  1419. return 0;
  1420. }
  1421. static int wcd937x_event_notify(struct notifier_block *block,
  1422. unsigned long val,
  1423. void *data)
  1424. {
  1425. u16 event = (val & 0xffff);
  1426. u16 amic = (val >> 0x10);
  1427. u16 mask = 0x40, reg = 0x0;
  1428. int ret = 0;
  1429. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1430. struct snd_soc_component *component = wcd937x->component;
  1431. struct wcd_mbhc *mbhc;
  1432. switch (event) {
  1433. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1434. if (amic == 0x1 || amic == 0x2)
  1435. reg = WCD937X_ANA_TX_CH2;
  1436. else if (amic == 0x3)
  1437. reg = WCD937X_ANA_TX_CH3_HPF;
  1438. else
  1439. return 0;
  1440. if (amic == 0x2)
  1441. mask = 0x20;
  1442. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1443. break;
  1444. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1445. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1446. 0xC0, 0x00);
  1447. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1448. 0x80, 0x00);
  1449. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1450. 0x80, 0x00);
  1451. break;
  1452. case BOLERO_WCD_EVT_SSR_DOWN:
  1453. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1454. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1455. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1456. wcd937x_reset_low(wcd937x->dev);
  1457. break;
  1458. case BOLERO_WCD_EVT_SSR_UP:
  1459. wcd937x_reset(wcd937x->dev);
  1460. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1461. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1462. regcache_mark_dirty(wcd937x->regmap);
  1463. regcache_sync(wcd937x->regmap);
  1464. /* Enable surge protection */
  1465. snd_soc_component_update_bits(component,
  1466. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  1467. 0xFF, 0xD9);
  1468. /* Initialize MBHC module */
  1469. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1470. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1471. if (ret) {
  1472. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1473. __func__);
  1474. } else {
  1475. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1476. }
  1477. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1478. break;
  1479. default:
  1480. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1481. event);
  1482. break;
  1483. }
  1484. return 0;
  1485. }
  1486. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1487. int event)
  1488. {
  1489. struct snd_soc_component *component =
  1490. snd_soc_dapm_to_component(w->dapm);
  1491. int micb_num;
  1492. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1493. __func__, w->name, event);
  1494. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1495. micb_num = MIC_BIAS_1;
  1496. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1497. micb_num = MIC_BIAS_2;
  1498. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1499. micb_num = MIC_BIAS_3;
  1500. else
  1501. return -EINVAL;
  1502. switch (event) {
  1503. case SND_SOC_DAPM_PRE_PMU:
  1504. wcd937x_micbias_control(component, micb_num,
  1505. MICB_ENABLE, true);
  1506. break;
  1507. case SND_SOC_DAPM_POST_PMU:
  1508. usleep_range(1000, 1100);
  1509. break;
  1510. case SND_SOC_DAPM_POST_PMD:
  1511. wcd937x_micbias_control(component, micb_num,
  1512. MICB_DISABLE, true);
  1513. break;
  1514. };
  1515. return 0;
  1516. }
  1517. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1518. struct snd_kcontrol *kcontrol,
  1519. int event)
  1520. {
  1521. return __wcd937x_codec_enable_micbias(w, event);
  1522. }
  1523. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1524. int event)
  1525. {
  1526. struct snd_soc_component *component =
  1527. snd_soc_dapm_to_component(w->dapm);
  1528. int micb_num;
  1529. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1530. __func__, w->name, event);
  1531. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1532. micb_num = MIC_BIAS_1;
  1533. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1534. micb_num = MIC_BIAS_2;
  1535. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1536. micb_num = MIC_BIAS_3;
  1537. else
  1538. return -EINVAL;
  1539. switch (event) {
  1540. case SND_SOC_DAPM_PRE_PMU:
  1541. wcd937x_micbias_control(component, micb_num,
  1542. MICB_PULLUP_ENABLE, true);
  1543. break;
  1544. case SND_SOC_DAPM_POST_PMU:
  1545. /* 1 msec delay as per HW requirement */
  1546. usleep_range(1000, 1100);
  1547. break;
  1548. case SND_SOC_DAPM_POST_PMD:
  1549. wcd937x_micbias_control(component, micb_num,
  1550. MICB_PULLUP_DISABLE, true);
  1551. break;
  1552. };
  1553. return 0;
  1554. }
  1555. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1556. struct snd_kcontrol *kcontrol,
  1557. int event)
  1558. {
  1559. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1560. }
  1561. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1562. struct snd_ctl_elem_value *ucontrol)
  1563. {
  1564. struct snd_soc_component *component =
  1565. snd_soc_kcontrol_component(kcontrol);
  1566. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1567. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1568. return 0;
  1569. }
  1570. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1571. struct snd_ctl_elem_value *ucontrol)
  1572. {
  1573. struct snd_soc_component *component =
  1574. snd_soc_kcontrol_component(kcontrol);
  1575. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1576. u32 mode_val;
  1577. mode_val = ucontrol->value.enumerated.item[0];
  1578. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1579. if (mode_val == 0) {
  1580. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1581. __func__);
  1582. mode_val = 3; /* enum will be updated later */
  1583. }
  1584. wcd937x->hph_mode = mode_val;
  1585. return 0;
  1586. }
  1587. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1588. struct snd_ctl_elem_value *ucontrol)
  1589. {
  1590. u8 ear_pa_gain = 0;
  1591. struct snd_soc_component *component =
  1592. snd_soc_kcontrol_component(kcontrol);
  1593. ear_pa_gain = snd_soc_component_read32(component,
  1594. WCD937X_ANA_EAR_COMPANDER_CTL);
  1595. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1596. ucontrol->value.integer.value[0] = ear_pa_gain;
  1597. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1598. ear_pa_gain);
  1599. return 0;
  1600. }
  1601. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1602. struct snd_ctl_elem_value *ucontrol)
  1603. {
  1604. u8 ear_pa_gain = 0;
  1605. struct snd_soc_component *component =
  1606. snd_soc_kcontrol_component(kcontrol);
  1607. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1608. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1609. __func__, ucontrol->value.integer.value[0]);
  1610. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1611. if (!wcd937x->comp1_enable) {
  1612. snd_soc_component_update_bits(component,
  1613. WCD937X_ANA_EAR_COMPANDER_CTL,
  1614. 0x7C, ear_pa_gain);
  1615. }
  1616. return 0;
  1617. }
  1618. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1619. struct snd_ctl_elem_value *ucontrol)
  1620. {
  1621. struct snd_soc_component *component =
  1622. snd_soc_kcontrol_component(kcontrol);
  1623. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1624. bool hphr;
  1625. struct soc_multi_mixer_control *mc;
  1626. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1627. hphr = mc->shift;
  1628. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1629. wcd937x->comp1_enable;
  1630. return 0;
  1631. }
  1632. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1633. struct snd_ctl_elem_value *ucontrol)
  1634. {
  1635. struct snd_soc_component *component =
  1636. snd_soc_kcontrol_component(kcontrol);
  1637. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1638. int value = ucontrol->value.integer.value[0];
  1639. bool hphr;
  1640. struct soc_multi_mixer_control *mc;
  1641. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1642. hphr = mc->shift;
  1643. if (hphr)
  1644. wcd937x->comp2_enable = value;
  1645. else
  1646. wcd937x->comp1_enable = value;
  1647. return 0;
  1648. }
  1649. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1650. struct snd_kcontrol *kcontrol,
  1651. int event)
  1652. {
  1653. struct snd_soc_component *component =
  1654. snd_soc_dapm_to_component(w->dapm);
  1655. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1656. struct wcd937x_pdata *pdata = NULL;
  1657. int ret = 0;
  1658. pdata = dev_get_platdata(wcd937x->dev);
  1659. if (!pdata) {
  1660. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1661. return -EINVAL;
  1662. }
  1663. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1664. w->name, event);
  1665. switch (event) {
  1666. case SND_SOC_DAPM_PRE_PMU:
  1667. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1668. dev_dbg(component->dev,
  1669. "%s: buck already in enabled state\n",
  1670. __func__);
  1671. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1672. return 0;
  1673. }
  1674. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1675. wcd937x->supplies,
  1676. pdata->regulator,
  1677. pdata->num_supplies,
  1678. "cdc-vdd-buck");
  1679. if (ret == -EINVAL) {
  1680. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1681. __func__);
  1682. return ret;
  1683. }
  1684. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1685. /*
  1686. * 200us sleep is required after LDO15 is enabled as per
  1687. * HW requirement
  1688. */
  1689. usleep_range(200, 250);
  1690. break;
  1691. case SND_SOC_DAPM_POST_PMD:
  1692. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1693. break;
  1694. }
  1695. return 0;
  1696. }
  1697. static const char * const rx_hph_mode_mux_text[] = {
  1698. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1699. "CLS_H_ULP", "CLS_AB_HIFI",
  1700. };
  1701. const char * const tx_master_ch_text[] = {
  1702. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1703. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1704. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1705. "SWRM_PCM_IN",
  1706. };
  1707. const struct soc_enum tx_master_ch_enum =
  1708. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1709. tx_master_ch_text);
  1710. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1711. {
  1712. u8 ch_type = 0;
  1713. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1714. ch_type = ADC1;
  1715. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1716. ch_type = ADC2;
  1717. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1718. ch_type = ADC3;
  1719. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1720. ch_type = DMIC0;
  1721. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1722. ch_type = DMIC1;
  1723. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1724. ch_type = MBHC;
  1725. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1726. ch_type = DMIC2;
  1727. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1728. ch_type = DMIC3;
  1729. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1730. ch_type = DMIC4;
  1731. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1732. ch_type = DMIC5;
  1733. else
  1734. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1735. if (ch_type)
  1736. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1737. else
  1738. *ch_idx = -EINVAL;
  1739. }
  1740. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1741. struct snd_ctl_elem_value *ucontrol)
  1742. {
  1743. struct snd_soc_component *component =
  1744. snd_soc_kcontrol_component(kcontrol);
  1745. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1746. int slave_ch_idx;
  1747. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1748. if (slave_ch_idx != -EINVAL)
  1749. ucontrol->value.integer.value[0] =
  1750. wcd937x_slave_get_master_ch_val(
  1751. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1752. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1753. __func__, ucontrol->value.integer.value[0]);
  1754. return 0;
  1755. }
  1756. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  1757. struct snd_ctl_elem_value *ucontrol)
  1758. {
  1759. struct snd_soc_component *component =
  1760. snd_soc_kcontrol_component(kcontrol);
  1761. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1762. int slave_ch_idx;
  1763. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1764. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  1765. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  1766. __func__, ucontrol->value.enumerated.item[0]);
  1767. if (slave_ch_idx != -EINVAL)
  1768. wcd937x->tx_master_ch_map[slave_ch_idx] =
  1769. wcd937x_slave_get_master_ch(
  1770. ucontrol->value.enumerated.item[0]);
  1771. return 0;
  1772. }
  1773. static const char * const wcd937x_ear_pa_gain_text[] = {
  1774. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1775. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1776. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1777. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1778. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1779. };
  1780. static const struct soc_enum rx_hph_mode_mux_enum =
  1781. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1782. rx_hph_mode_mux_text);
  1783. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1784. wcd937x_ear_pa_gain_text);
  1785. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1786. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1787. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1788. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1789. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1790. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1791. wcd937x_get_compander, wcd937x_set_compander),
  1792. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1793. wcd937x_get_compander, wcd937x_set_compander),
  1794. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1795. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1796. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1797. analog_gain),
  1798. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1799. analog_gain),
  1800. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1801. analog_gain),
  1802. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  1803. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1804. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  1805. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1806. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  1807. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1808. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  1809. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1810. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  1811. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1812. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  1813. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1814. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  1815. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1816. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  1817. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1818. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  1819. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1820. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  1821. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1822. };
  1823. static const struct snd_kcontrol_new adc1_switch[] = {
  1824. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1825. };
  1826. static const struct snd_kcontrol_new adc2_switch[] = {
  1827. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1828. };
  1829. static const struct snd_kcontrol_new adc3_switch[] = {
  1830. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1831. };
  1832. static const struct snd_kcontrol_new dmic1_switch[] = {
  1833. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1834. };
  1835. static const struct snd_kcontrol_new dmic2_switch[] = {
  1836. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1837. };
  1838. static const struct snd_kcontrol_new dmic3_switch[] = {
  1839. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1840. };
  1841. static const struct snd_kcontrol_new dmic4_switch[] = {
  1842. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1843. };
  1844. static const struct snd_kcontrol_new dmic5_switch[] = {
  1845. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1846. };
  1847. static const struct snd_kcontrol_new dmic6_switch[] = {
  1848. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1849. };
  1850. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1851. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1852. };
  1853. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1854. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1855. };
  1856. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1857. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1858. };
  1859. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1860. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1861. };
  1862. static const char * const adc2_mux_text[] = {
  1863. "INP2", "INP3"
  1864. };
  1865. static const char * const rdac3_mux_text[] = {
  1866. "RX1", "RX3"
  1867. };
  1868. static const struct soc_enum adc2_enum =
  1869. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1870. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1871. static const struct soc_enum rdac3_enum =
  1872. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1873. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1874. static const struct snd_kcontrol_new tx_adc2_mux =
  1875. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1876. static const struct snd_kcontrol_new rx_rdac3_mux =
  1877. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1878. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1879. /*input widgets*/
  1880. SND_SOC_DAPM_INPUT("AMIC1"),
  1881. SND_SOC_DAPM_INPUT("AMIC2"),
  1882. SND_SOC_DAPM_INPUT("AMIC3"),
  1883. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1884. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1885. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1886. /*tx widgets*/
  1887. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1888. wcd937x_codec_enable_adc,
  1889. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1890. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1891. wcd937x_codec_enable_adc,
  1892. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1893. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1894. NULL, 0, wcd937x_enable_req,
  1895. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1896. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1897. NULL, 0, wcd937x_enable_req,
  1898. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1899. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1900. &tx_adc2_mux),
  1901. /*tx mixers*/
  1902. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1903. adc1_switch, ARRAY_SIZE(adc1_switch),
  1904. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1905. SND_SOC_DAPM_POST_PMD),
  1906. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1907. adc2_switch, ARRAY_SIZE(adc2_switch),
  1908. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1909. SND_SOC_DAPM_POST_PMD),
  1910. /* micbias widgets*/
  1911. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1912. wcd937x_codec_enable_micbias,
  1913. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1914. SND_SOC_DAPM_POST_PMD),
  1915. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1916. wcd937x_codec_enable_micbias,
  1917. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1918. SND_SOC_DAPM_POST_PMD),
  1919. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1920. wcd937x_codec_enable_micbias,
  1921. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1922. SND_SOC_DAPM_POST_PMD),
  1923. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  1924. wcd937x_codec_enable_vdd_buck,
  1925. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1926. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1927. wcd937x_enable_clsh,
  1928. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1929. /*rx widgets*/
  1930. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  1931. wcd937x_codec_enable_ear_pa,
  1932. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1933. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1934. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  1935. wcd937x_codec_enable_aux_pa,
  1936. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1937. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1938. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  1939. wcd937x_codec_enable_hphl_pa,
  1940. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1941. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1942. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  1943. wcd937x_codec_enable_hphr_pa,
  1944. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1945. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1946. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1947. wcd937x_codec_hphl_dac_event,
  1948. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1949. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1950. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1951. wcd937x_codec_hphr_dac_event,
  1952. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1953. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1954. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1955. wcd937x_codec_ear_dac_event,
  1956. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1957. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1958. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1959. wcd937x_codec_aux_dac_event,
  1960. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1961. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1962. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1963. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1964. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1965. SND_SOC_DAPM_POST_PMD),
  1966. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1967. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1968. SND_SOC_DAPM_POST_PMD),
  1969. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1970. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1971. SND_SOC_DAPM_POST_PMD),
  1972. /* rx mixer widgets*/
  1973. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1974. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1975. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1976. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1977. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1978. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1979. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1980. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1981. /*output widgets tx*/
  1982. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1983. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1984. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  1985. /*output widgets rx*/
  1986. SND_SOC_DAPM_OUTPUT("EAR"),
  1987. SND_SOC_DAPM_OUTPUT("AUX"),
  1988. SND_SOC_DAPM_OUTPUT("HPHL"),
  1989. SND_SOC_DAPM_OUTPUT("HPHR"),
  1990. /* micbias pull up widgets*/
  1991. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1992. wcd937x_codec_enable_micbias_pullup,
  1993. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1994. SND_SOC_DAPM_POST_PMD),
  1995. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1996. wcd937x_codec_enable_micbias_pullup,
  1997. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1998. SND_SOC_DAPM_POST_PMD),
  1999. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2000. wcd937x_codec_enable_micbias_pullup,
  2001. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2002. SND_SOC_DAPM_POST_PMD),
  2003. };
  2004. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2005. /*input widgets*/
  2006. SND_SOC_DAPM_INPUT("AMIC4"),
  2007. /*tx widgets*/
  2008. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2009. wcd937x_codec_enable_adc,
  2010. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2011. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2012. NULL, 0, wcd937x_enable_req,
  2013. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2014. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2015. wcd937x_codec_enable_dmic,
  2016. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2017. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2018. wcd937x_codec_enable_dmic,
  2019. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2020. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2021. wcd937x_codec_enable_dmic,
  2022. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2023. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2024. wcd937x_codec_enable_dmic,
  2025. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2026. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2027. wcd937x_codec_enable_dmic,
  2028. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2029. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2030. wcd937x_codec_enable_dmic,
  2031. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2032. /*tx mixer widgets*/
  2033. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2034. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2035. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2036. SND_SOC_DAPM_POST_PMD),
  2037. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2038. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2039. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2040. SND_SOC_DAPM_POST_PMD),
  2041. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2042. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2043. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2044. SND_SOC_DAPM_POST_PMD),
  2045. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2046. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2047. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2048. SND_SOC_DAPM_POST_PMD),
  2049. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2050. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2051. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2052. SND_SOC_DAPM_POST_PMD),
  2053. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2054. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2055. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2056. SND_SOC_DAPM_POST_PMD),
  2057. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2058. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2059. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2060. /*output widgets*/
  2061. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2062. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2063. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2064. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2065. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2066. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2067. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2068. };
  2069. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2070. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2071. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2072. {"ADC1 REQ", NULL, "ADC1"},
  2073. {"ADC1", NULL, "AMIC1"},
  2074. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2075. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2076. {"ADC2 REQ", NULL, "ADC2"},
  2077. {"ADC2", NULL, "ADC2 MUX"},
  2078. {"ADC2 MUX", "INP3", "AMIC3"},
  2079. {"ADC2 MUX", "INP2", "AMIC2"},
  2080. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2081. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2082. {"RX1", NULL, "IN1_HPHL"},
  2083. {"RDAC1", NULL, "RX1"},
  2084. {"HPHL_RDAC", "Switch", "RDAC1"},
  2085. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2086. {"HPHL", NULL, "HPHL PGA"},
  2087. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2088. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2089. {"RX2", NULL, "IN2_HPHR"},
  2090. {"RDAC2", NULL, "RX2"},
  2091. {"HPHR_RDAC", "Switch", "RDAC2"},
  2092. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2093. {"HPHR", NULL, "HPHR PGA"},
  2094. {"IN3_AUX", NULL, "VDD_BUCK"},
  2095. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2096. {"RX3", NULL, "IN3_AUX"},
  2097. {"RDAC4", NULL, "RX3"},
  2098. {"AUX_RDAC", "Switch", "RDAC4"},
  2099. {"AUX PGA", NULL, "AUX_RDAC"},
  2100. {"AUX", NULL, "AUX PGA"},
  2101. {"RDAC3_MUX", "RX3", "RX3"},
  2102. {"RDAC3_MUX", "RX1", "RX1"},
  2103. {"RDAC3", NULL, "RDAC3_MUX"},
  2104. {"EAR_RDAC", "Switch", "RDAC3"},
  2105. {"EAR PGA", NULL, "EAR_RDAC"},
  2106. {"EAR", NULL, "EAR PGA"},
  2107. };
  2108. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2109. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2110. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2111. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2112. {"ADC3 REQ", NULL, "ADC3"},
  2113. {"ADC3", NULL, "AMIC4"},
  2114. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2115. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2116. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2117. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2118. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2119. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2120. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2121. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2122. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2123. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2124. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2125. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2126. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2127. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2128. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2129. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2130. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2131. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2132. };
  2133. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2134. void *file_private_data,
  2135. struct file *file,
  2136. char __user *buf, size_t count,
  2137. loff_t pos)
  2138. {
  2139. struct wcd937x_priv *priv;
  2140. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2141. int len = 0;
  2142. priv = (struct wcd937x_priv *) entry->private_data;
  2143. if (!priv) {
  2144. pr_err("%s: wcd937x priv is null\n", __func__);
  2145. return -EINVAL;
  2146. }
  2147. switch (priv->version) {
  2148. case WCD937X_VERSION_1_0:
  2149. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2150. break;
  2151. default:
  2152. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2153. }
  2154. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2155. }
  2156. static struct snd_info_entry_ops wcd937x_info_ops = {
  2157. .read = wcd937x_version_read,
  2158. };
  2159. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2160. void *file_private_data,
  2161. struct file *file,
  2162. char __user *buf, size_t count,
  2163. loff_t pos)
  2164. {
  2165. struct wcd937x_priv *priv;
  2166. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2167. int len = 0;
  2168. priv = (struct wcd937x_priv *) entry->private_data;
  2169. if (!priv) {
  2170. pr_err("%s: wcd937x priv is null\n", __func__);
  2171. return -EINVAL;
  2172. }
  2173. switch (priv->variant) {
  2174. case WCD9370_VARIANT:
  2175. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2176. break;
  2177. case WCD9375_VARIANT:
  2178. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2179. break;
  2180. default:
  2181. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2182. }
  2183. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2184. }
  2185. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2186. .read = wcd937x_variant_read,
  2187. };
  2188. /*
  2189. * wcd937x_info_create_codec_entry - creates wcd937x module
  2190. * @codec_root: The parent directory
  2191. * @component: component instance
  2192. *
  2193. * Creates wcd937x module, variant and version entry under the given
  2194. * parent directory.
  2195. *
  2196. * Return: 0 on success or negative error code on failure.
  2197. */
  2198. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2199. struct snd_soc_component *component)
  2200. {
  2201. struct snd_info_entry *version_entry;
  2202. struct snd_info_entry *variant_entry;
  2203. struct wcd937x_priv *priv;
  2204. struct snd_soc_card *card;
  2205. if (!codec_root || !component)
  2206. return -EINVAL;
  2207. priv = snd_soc_component_get_drvdata(component);
  2208. if (priv->entry) {
  2209. dev_dbg(priv->dev,
  2210. "%s:wcd937x module already created\n", __func__);
  2211. return 0;
  2212. }
  2213. card = component->card;
  2214. priv->entry = snd_info_create_subdir(codec_root->module,
  2215. "wcd937x", codec_root);
  2216. if (!priv->entry) {
  2217. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2218. __func__);
  2219. return -ENOMEM;
  2220. }
  2221. version_entry = snd_info_create_card_entry(card->snd_card,
  2222. "version",
  2223. priv->entry);
  2224. if (!version_entry) {
  2225. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2226. __func__);
  2227. return -ENOMEM;
  2228. }
  2229. version_entry->private_data = priv;
  2230. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2231. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2232. version_entry->c.ops = &wcd937x_info_ops;
  2233. if (snd_info_register(version_entry) < 0) {
  2234. snd_info_free_entry(version_entry);
  2235. return -ENOMEM;
  2236. }
  2237. priv->version_entry = version_entry;
  2238. variant_entry = snd_info_create_card_entry(card->snd_card,
  2239. "variant",
  2240. priv->entry);
  2241. if (!variant_entry) {
  2242. dev_dbg(component->dev,
  2243. "%s: failed to create wcd937x variant entry\n",
  2244. __func__);
  2245. return -ENOMEM;
  2246. }
  2247. variant_entry->private_data = priv;
  2248. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2249. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2250. variant_entry->c.ops = &wcd937x_variant_ops;
  2251. if (snd_info_register(variant_entry) < 0) {
  2252. snd_info_free_entry(variant_entry);
  2253. return -ENOMEM;
  2254. }
  2255. priv->variant_entry = variant_entry;
  2256. return 0;
  2257. }
  2258. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2259. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2260. struct wcd937x_pdata *pdata)
  2261. {
  2262. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2263. int rc = 0;
  2264. if (!pdata) {
  2265. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2266. return -ENODEV;
  2267. }
  2268. /* set micbias voltage */
  2269. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2270. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2271. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2272. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2273. rc = -EINVAL;
  2274. goto done;
  2275. }
  2276. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2277. vout_ctl_1);
  2278. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2279. vout_ctl_2);
  2280. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2281. vout_ctl_3);
  2282. done:
  2283. return rc;
  2284. }
  2285. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2286. {
  2287. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2288. struct snd_soc_dapm_context *dapm =
  2289. snd_soc_component_get_dapm(component);
  2290. int variant;
  2291. int ret = -EINVAL;
  2292. dev_info(component->dev, "%s()\n", __func__);
  2293. wcd937x = snd_soc_component_get_drvdata(component);
  2294. if (!wcd937x)
  2295. return -EINVAL;
  2296. wcd937x->component = component;
  2297. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2298. variant = (snd_soc_component_read32(
  2299. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2300. wcd937x->variant = variant;
  2301. wcd937x->fw_data = devm_kzalloc(component->dev,
  2302. sizeof(*(wcd937x->fw_data)),
  2303. GFP_KERNEL);
  2304. if (!wcd937x->fw_data) {
  2305. dev_err(component->dev, "Failed to allocate fw_data\n");
  2306. ret = -ENOMEM;
  2307. goto err;
  2308. }
  2309. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2310. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2311. WCD9XXX_CODEC_HWDEP_NODE, component);
  2312. if (ret < 0) {
  2313. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2314. goto err_hwdep;
  2315. }
  2316. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2317. if (ret) {
  2318. pr_err("%s: mbhc initialization failed\n", __func__);
  2319. goto err_hwdep;
  2320. }
  2321. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2322. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2323. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2324. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2325. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2326. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2327. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2328. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2329. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2330. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2331. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2332. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2333. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2334. snd_soc_dapm_sync(dapm);
  2335. wcd_cls_h_init(&wcd937x->clsh_info);
  2336. wcd937x_init_reg(component);
  2337. if (wcd937x->variant == WCD9375_VARIANT) {
  2338. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2339. ARRAY_SIZE(wcd9375_dapm_widgets));
  2340. if (ret < 0) {
  2341. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2342. __func__);
  2343. goto err_hwdep;
  2344. }
  2345. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2346. ARRAY_SIZE(wcd9375_audio_map));
  2347. if (ret < 0) {
  2348. dev_err(component->dev, "%s: Failed to add routes\n",
  2349. __func__);
  2350. goto err_hwdep;
  2351. }
  2352. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2353. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2354. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2355. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2356. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2357. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2358. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2359. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2360. snd_soc_dapm_sync(dapm);
  2361. }
  2362. wcd937x->version = WCD937X_VERSION_1_0;
  2363. /* Register event notifier */
  2364. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2365. if (wcd937x->register_notifier) {
  2366. ret = wcd937x->register_notifier(wcd937x->handle,
  2367. &wcd937x->nblock,
  2368. true);
  2369. if (ret) {
  2370. dev_err(component->dev,
  2371. "%s: Failed to register notifier %d\n",
  2372. __func__, ret);
  2373. return ret;
  2374. }
  2375. }
  2376. return ret;
  2377. err_hwdep:
  2378. wcd937x->fw_data = NULL;
  2379. err:
  2380. return ret;
  2381. }
  2382. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2383. {
  2384. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2385. if (!wcd937x)
  2386. return;
  2387. if (wcd937x->register_notifier)
  2388. wcd937x->register_notifier(wcd937x->handle,
  2389. &wcd937x->nblock,
  2390. false);
  2391. return;
  2392. }
  2393. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2394. .name = DRV_NAME,
  2395. .probe = wcd937x_soc_codec_probe,
  2396. .remove = wcd937x_soc_codec_remove,
  2397. .controls = wcd937x_snd_controls,
  2398. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2399. .dapm_widgets = wcd937x_dapm_widgets,
  2400. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2401. .dapm_routes = wcd937x_audio_map,
  2402. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2403. };
  2404. #ifdef CONFIG_PM_SLEEP
  2405. static int wcd937x_suspend(struct device *dev)
  2406. {
  2407. struct wcd937x_priv *wcd937x = NULL;
  2408. int ret = 0;
  2409. struct wcd937x_pdata *pdata = NULL;
  2410. if (!dev)
  2411. return -ENODEV;
  2412. wcd937x = dev_get_drvdata(dev);
  2413. if (!wcd937x)
  2414. return -EINVAL;
  2415. pdata = dev_get_platdata(wcd937x->dev);
  2416. if (!pdata) {
  2417. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2418. return -EINVAL;
  2419. }
  2420. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2421. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2422. wcd937x->supplies,
  2423. pdata->regulator,
  2424. pdata->num_supplies,
  2425. "cdc-vdd-buck");
  2426. if (ret == -EINVAL) {
  2427. dev_err(dev, "%s: vdd buck is not disabled\n",
  2428. __func__);
  2429. return 0;
  2430. }
  2431. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2432. }
  2433. return 0;
  2434. }
  2435. static int wcd937x_resume(struct device *dev)
  2436. {
  2437. return 0;
  2438. }
  2439. #endif
  2440. static int wcd937x_reset(struct device *dev)
  2441. {
  2442. struct wcd937x_priv *wcd937x = NULL;
  2443. int rc = 0;
  2444. int value = 0;
  2445. if (!dev)
  2446. return -ENODEV;
  2447. wcd937x = dev_get_drvdata(dev);
  2448. if (!wcd937x)
  2449. return -EINVAL;
  2450. if (!wcd937x->rst_np) {
  2451. dev_err(dev, "%s: reset gpio device node not specified\n",
  2452. __func__);
  2453. return -EINVAL;
  2454. }
  2455. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2456. if (value > 0)
  2457. return 0;
  2458. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2459. if (rc) {
  2460. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2461. __func__);
  2462. return rc;
  2463. }
  2464. /* 20ms sleep required after pulling the reset gpio to LOW */
  2465. usleep_range(20, 30);
  2466. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2467. if (rc) {
  2468. dev_err(dev, "%s: wcd active state request fail!\n",
  2469. __func__);
  2470. return rc;
  2471. }
  2472. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2473. usleep_range(20, 30);
  2474. return rc;
  2475. }
  2476. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2477. u32 *val)
  2478. {
  2479. int rc = 0;
  2480. rc = of_property_read_u32(dev->of_node, name, val);
  2481. if (rc)
  2482. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2483. __func__, name, dev->of_node->full_name);
  2484. return rc;
  2485. }
  2486. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2487. struct wcd937x_micbias_setting *mb)
  2488. {
  2489. u32 prop_val = 0;
  2490. int rc = 0;
  2491. /* MB1 */
  2492. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2493. NULL)) {
  2494. rc = wcd937x_read_of_property_u32(dev,
  2495. "qcom,cdc-micbias1-mv",
  2496. &prop_val);
  2497. if (!rc)
  2498. mb->micb1_mv = prop_val;
  2499. } else {
  2500. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2501. __func__);
  2502. }
  2503. /* MB2 */
  2504. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2505. NULL)) {
  2506. rc = wcd937x_read_of_property_u32(dev,
  2507. "qcom,cdc-micbias2-mv",
  2508. &prop_val);
  2509. if (!rc)
  2510. mb->micb2_mv = prop_val;
  2511. } else {
  2512. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2513. __func__);
  2514. }
  2515. /* MB3 */
  2516. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2517. NULL)) {
  2518. rc = wcd937x_read_of_property_u32(dev,
  2519. "qcom,cdc-micbias3-mv",
  2520. &prop_val);
  2521. if (!rc)
  2522. mb->micb3_mv = prop_val;
  2523. } else {
  2524. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2525. __func__);
  2526. }
  2527. }
  2528. static int wcd937x_reset_low(struct device *dev)
  2529. {
  2530. struct wcd937x_priv *wcd937x = NULL;
  2531. int rc = 0;
  2532. if (!dev)
  2533. return -ENODEV;
  2534. wcd937x = dev_get_drvdata(dev);
  2535. if (!wcd937x)
  2536. return -EINVAL;
  2537. if (!wcd937x->rst_np) {
  2538. dev_err(dev, "%s: reset gpio device node not specified\n",
  2539. __func__);
  2540. return -EINVAL;
  2541. }
  2542. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2543. if (rc) {
  2544. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2545. __func__);
  2546. return rc;
  2547. }
  2548. /* 20ms sleep required after pulling the reset gpio to LOW */
  2549. usleep_range(20, 30);
  2550. return rc;
  2551. }
  2552. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2553. {
  2554. struct wcd937x_pdata *pdata = NULL;
  2555. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2556. GFP_KERNEL);
  2557. if (!pdata)
  2558. return NULL;
  2559. pdata->rst_np = of_parse_phandle(dev->of_node,
  2560. "qcom,wcd-rst-gpio-node", 0);
  2561. if (!pdata->rst_np) {
  2562. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2563. __func__, "qcom,wcd-rst-gpio-node",
  2564. dev->of_node->full_name);
  2565. return NULL;
  2566. }
  2567. /* Parse power supplies */
  2568. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2569. &pdata->num_supplies);
  2570. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2571. dev_err(dev, "%s: no power supplies defined for codec\n",
  2572. __func__);
  2573. return NULL;
  2574. }
  2575. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2576. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2577. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2578. return pdata;
  2579. }
  2580. static int wcd937x_wakeup(void *handle, bool enable)
  2581. {
  2582. struct wcd937x_priv *priv;
  2583. if (!handle) {
  2584. pr_err("%s: NULL handle\n", __func__);
  2585. return -EINVAL;
  2586. }
  2587. priv = (struct wcd937x_priv *)handle;
  2588. if (!priv->tx_swr_dev) {
  2589. pr_err("%s: tx swr dev is NULL\n", __func__);
  2590. return -EINVAL;
  2591. }
  2592. if (enable)
  2593. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2594. else
  2595. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2596. }
  2597. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2598. {
  2599. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2600. __func__, irq);
  2601. return IRQ_HANDLED;
  2602. }
  2603. static int wcd937x_bind(struct device *dev)
  2604. {
  2605. int ret = 0, i = 0;
  2606. struct wcd937x_priv *wcd937x = NULL;
  2607. struct wcd937x_pdata *pdata = NULL;
  2608. struct wcd_ctrl_platform_data *plat_data = NULL;
  2609. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2610. if (!wcd937x)
  2611. return -ENOMEM;
  2612. dev_set_drvdata(dev, wcd937x);
  2613. pdata = wcd937x_populate_dt_data(dev);
  2614. if (!pdata) {
  2615. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2616. return -EINVAL;
  2617. }
  2618. wcd937x->dev = dev;
  2619. wcd937x->dev->platform_data = pdata;
  2620. wcd937x->rst_np = pdata->rst_np;
  2621. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2622. pdata->regulator, pdata->num_supplies);
  2623. if (!wcd937x->supplies) {
  2624. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2625. __func__);
  2626. goto err_bind_all;
  2627. }
  2628. plat_data = dev_get_platdata(dev->parent);
  2629. if (!plat_data) {
  2630. dev_err(dev, "%s: platform data from parent is NULL\n",
  2631. __func__);
  2632. ret = -EINVAL;
  2633. goto err_bind_all;
  2634. }
  2635. wcd937x->handle = (void *)plat_data->handle;
  2636. if (!wcd937x->handle) {
  2637. dev_err(dev, "%s: handle is NULL\n", __func__);
  2638. ret = -EINVAL;
  2639. goto err_bind_all;
  2640. }
  2641. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2642. if (!wcd937x->update_wcd_event) {
  2643. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2644. __func__);
  2645. ret = -EINVAL;
  2646. goto err_bind_all;
  2647. }
  2648. wcd937x->register_notifier = plat_data->register_notifier;
  2649. if (!wcd937x->register_notifier) {
  2650. dev_err(dev, "%s: register_notifier api is null!\n",
  2651. __func__);
  2652. ret = -EINVAL;
  2653. goto err_bind_all;
  2654. }
  2655. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2656. pdata->regulator,
  2657. pdata->num_supplies);
  2658. if (ret) {
  2659. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2660. __func__);
  2661. goto err_bind_all;
  2662. }
  2663. wcd937x_reset(dev);
  2664. /*
  2665. * Add 5msec delay to provide sufficient time for
  2666. * soundwire auto enumeration of slave devices as
  2667. * as per HW requirement.
  2668. */
  2669. usleep_range(5000, 5010);
  2670. wcd937x->wakeup = wcd937x_wakeup;
  2671. ret = component_bind_all(dev, wcd937x);
  2672. if (ret) {
  2673. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2674. __func__, ret);
  2675. goto err_bind_all;
  2676. }
  2677. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2678. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2679. if (ret) {
  2680. dev_err(dev, "Failed to read port mapping\n");
  2681. goto err;
  2682. }
  2683. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2684. if (!wcd937x->rx_swr_dev) {
  2685. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2686. __func__);
  2687. ret = -ENODEV;
  2688. goto err;
  2689. }
  2690. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2691. if (!wcd937x->tx_swr_dev) {
  2692. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2693. __func__);
  2694. ret = -ENODEV;
  2695. goto err;
  2696. }
  2697. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2698. &wcd937x_regmap_config);
  2699. if (!wcd937x->regmap) {
  2700. dev_err(dev, "%s: Regmap init failed\n",
  2701. __func__);
  2702. goto err;
  2703. }
  2704. /* Set all interupts as edge triggered */
  2705. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2706. regmap_write(wcd937x->regmap,
  2707. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2708. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2709. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2710. wcd937x->irq_info.codec_name = "WCD937X";
  2711. wcd937x->irq_info.regmap = wcd937x->regmap;
  2712. wcd937x->irq_info.dev = dev;
  2713. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2714. if (ret) {
  2715. dev_err(dev, "%s: IRQ init failed: %d\n",
  2716. __func__, ret);
  2717. goto err;
  2718. }
  2719. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2720. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2721. if (ret < 0) {
  2722. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2723. goto err_irq;
  2724. }
  2725. mutex_init(&wcd937x->micb_lock);
  2726. mutex_init(&wcd937x->ana_tx_clk_lock);
  2727. /* Request for watchdog interrupt */
  2728. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2729. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2730. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2731. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2732. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2733. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2734. /* Disable watchdog interrupt for HPH and AUX */
  2735. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2736. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2737. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2738. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2739. NULL, 0);
  2740. if (ret) {
  2741. dev_err(dev, "%s: Codec registration failed\n",
  2742. __func__);
  2743. goto err_irq;
  2744. }
  2745. return ret;
  2746. err_irq:
  2747. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2748. err:
  2749. component_unbind_all(dev, wcd937x);
  2750. err_bind_all:
  2751. dev_set_drvdata(dev, NULL);
  2752. kfree(pdata);
  2753. kfree(wcd937x);
  2754. return ret;
  2755. }
  2756. static void wcd937x_unbind(struct device *dev)
  2757. {
  2758. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2759. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2760. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2761. snd_soc_unregister_component(dev);
  2762. component_unbind_all(dev, wcd937x);
  2763. mutex_destroy(&wcd937x->micb_lock);
  2764. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2765. dev_set_drvdata(dev, NULL);
  2766. kfree(pdata);
  2767. kfree(wcd937x);
  2768. }
  2769. static const struct of_device_id wcd937x_dt_match[] = {
  2770. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  2771. {}
  2772. };
  2773. static const struct component_master_ops wcd937x_comp_ops = {
  2774. .bind = wcd937x_bind,
  2775. .unbind = wcd937x_unbind,
  2776. };
  2777. static int wcd937x_compare_of(struct device *dev, void *data)
  2778. {
  2779. return dev->of_node == data;
  2780. }
  2781. static void wcd937x_release_of(struct device *dev, void *data)
  2782. {
  2783. of_node_put(data);
  2784. }
  2785. static int wcd937x_add_slave_components(struct device *dev,
  2786. struct component_match **matchptr)
  2787. {
  2788. struct device_node *np, *rx_node, *tx_node;
  2789. np = dev->of_node;
  2790. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2791. if (!rx_node) {
  2792. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2793. return -ENODEV;
  2794. }
  2795. of_node_get(rx_node);
  2796. component_match_add_release(dev, matchptr,
  2797. wcd937x_release_of,
  2798. wcd937x_compare_of,
  2799. rx_node);
  2800. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2801. if (!tx_node) {
  2802. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2803. return -ENODEV;
  2804. }
  2805. of_node_get(tx_node);
  2806. component_match_add_release(dev, matchptr,
  2807. wcd937x_release_of,
  2808. wcd937x_compare_of,
  2809. tx_node);
  2810. return 0;
  2811. }
  2812. static int wcd937x_probe(struct platform_device *pdev)
  2813. {
  2814. struct component_match *match = NULL;
  2815. int ret;
  2816. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2817. if (ret)
  2818. return ret;
  2819. return component_master_add_with_match(&pdev->dev,
  2820. &wcd937x_comp_ops, match);
  2821. }
  2822. static int wcd937x_remove(struct platform_device *pdev)
  2823. {
  2824. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2825. dev_set_drvdata(&pdev->dev, NULL);
  2826. return 0;
  2827. }
  2828. #ifdef CONFIG_PM_SLEEP
  2829. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2830. SET_SYSTEM_SLEEP_PM_OPS(
  2831. wcd937x_suspend,
  2832. wcd937x_resume
  2833. )
  2834. };
  2835. #endif
  2836. static struct platform_driver wcd937x_codec_driver = {
  2837. .probe = wcd937x_probe,
  2838. .remove = wcd937x_remove,
  2839. .driver = {
  2840. .name = "wcd937x_codec",
  2841. .owner = THIS_MODULE,
  2842. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2843. #ifdef CONFIG_PM_SLEEP
  2844. .pm = &wcd937x_dev_pm_ops,
  2845. #endif
  2846. .suppress_bind_attrs = true,
  2847. },
  2848. };
  2849. module_platform_driver(wcd937x_codec_driver);
  2850. MODULE_DESCRIPTION("WCD937X Codec driver");
  2851. MODULE_LICENSE("GPL v2");