dp_tx.c 95 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include "qdf_net_types.h"
  27. #include <wlan_cfg.h>
  28. #ifdef MESH_MODE_SUPPORT
  29. #include "if_meta_hdr.h"
  30. #endif
  31. #ifdef TX_PER_PDEV_DESC_POOL
  32. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  33. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  34. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  35. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  36. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  37. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  38. #else
  39. #ifdef TX_PER_VDEV_DESC_POOL
  40. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  41. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  42. #else
  43. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  44. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  45. #endif /* TX_PER_VDEV_DESC_POOL */
  46. #endif /* TX_PER_PDEV_DESC_POOL */
  47. /* TODO Add support in TSO */
  48. #define DP_DESC_NUM_FRAG(x) 0
  49. /* disable TQM_BYPASS */
  50. #define TQM_BYPASS_WAR 0
  51. /* invalid peer id for reinject*/
  52. #define DP_INVALID_PEER 0XFFFE
  53. /*mapping between hal encrypt type and cdp_sec_type*/
  54. #define MAX_CDP_SEC_TYPE 12
  55. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  56. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  57. HAL_TX_ENCRYPT_TYPE_WEP_128,
  58. HAL_TX_ENCRYPT_TYPE_WEP_104,
  59. HAL_TX_ENCRYPT_TYPE_WEP_40,
  60. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  61. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  62. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  63. HAL_TX_ENCRYPT_TYPE_WAPI,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  65. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  66. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  68. /**
  69. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  70. * @vdev: DP Virtual device handle
  71. * @nbuf: Buffer pointer
  72. * @queue: queue ids container for nbuf
  73. *
  74. * TX packet queue has 2 instances, software descriptors id and dma ring id
  75. * Based on tx feature and hardware configuration queue id combination could be
  76. * different.
  77. * For example -
  78. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  79. * With no XPS,lock based resource protection, Descriptor pool ids are different
  80. * for each vdev, dma ring id will be same as single pdev id
  81. *
  82. * Return: None
  83. */
  84. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  85. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  86. {
  87. /* get flow id */
  88. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  89. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  91. "%s, pool_id:%d ring_id: %d",
  92. __func__, queue->desc_pool_id, queue->ring_id);
  93. return;
  94. }
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_desc_release() - Release the tso segment
  98. * after unmapping all the fragments
  99. *
  100. * @pdev - physical device handle
  101. * @tx_desc - Tx software descriptor
  102. */
  103. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  104. struct dp_tx_desc_s *tx_desc)
  105. {
  106. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  107. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  108. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  109. "%s %d TSO desc is NULL!",
  110. __func__, __LINE__);
  111. qdf_assert(0);
  112. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  113. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  114. "%s %d TSO common info is NULL!",
  115. __func__, __LINE__);
  116. qdf_assert(0);
  117. } else {
  118. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  119. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  120. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  121. tso_num_desc->num_seg.tso_cmn_num_seg--;
  122. qdf_nbuf_unmap_tso_segment(soc->osdev,
  123. tx_desc->tso_desc, false);
  124. } else {
  125. tso_num_desc->num_seg.tso_cmn_num_seg--;
  126. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  127. qdf_nbuf_unmap_tso_segment(soc->osdev,
  128. tx_desc->tso_desc, true);
  129. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  130. tx_desc->tso_num_desc);
  131. tx_desc->tso_num_desc = NULL;
  132. }
  133. dp_tx_tso_desc_free(soc,
  134. tx_desc->pool_id, tx_desc->tso_desc);
  135. tx_desc->tso_desc = NULL;
  136. }
  137. }
  138. #else
  139. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  140. struct dp_tx_desc_s *tx_desc)
  141. {
  142. return;
  143. }
  144. #endif
  145. /**
  146. * dp_tx_desc_release() - Release Tx Descriptor
  147. * @tx_desc : Tx Descriptor
  148. * @desc_pool_id: Descriptor Pool ID
  149. *
  150. * Deallocate all resources attached to Tx descriptor and free the Tx
  151. * descriptor.
  152. *
  153. * Return:
  154. */
  155. static void
  156. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  157. {
  158. struct dp_pdev *pdev = tx_desc->pdev;
  159. struct dp_soc *soc;
  160. uint8_t comp_status = 0;
  161. qdf_assert(pdev);
  162. soc = pdev->soc;
  163. if (tx_desc->frm_type == dp_tx_frm_tso)
  164. dp_tx_tso_desc_release(soc, tx_desc);
  165. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  166. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  167. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  168. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  169. qdf_atomic_dec(&pdev->num_tx_outstanding);
  170. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  171. qdf_atomic_dec(&pdev->num_tx_exception);
  172. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  173. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  174. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  175. else
  176. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  177. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  178. "Tx Completion Release desc %d status %d outstanding %d",
  179. tx_desc->id, comp_status,
  180. qdf_atomic_read(&pdev->num_tx_outstanding));
  181. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  182. return;
  183. }
  184. /**
  185. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  186. * @vdev: DP vdev Handle
  187. * @nbuf: skb
  188. *
  189. * Prepares and fills HTT metadata in the frame pre-header for special frames
  190. * that should be transmitted using varying transmit parameters.
  191. * There are 2 VDEV modes that currently needs this special metadata -
  192. * 1) Mesh Mode
  193. * 2) DSRC Mode
  194. *
  195. * Return: HTT metadata size
  196. *
  197. */
  198. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  199. uint32_t *meta_data)
  200. {
  201. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  202. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  203. uint8_t htt_desc_size;
  204. /* Size rounded of multiple of 8 bytes */
  205. uint8_t htt_desc_size_aligned;
  206. uint8_t *hdr = NULL;
  207. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  208. /*
  209. * Metadata - HTT MSDU Extension header
  210. */
  211. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  212. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  213. if (vdev->mesh_vdev) {
  214. /* Fill and add HTT metaheader */
  215. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  216. if (hdr == NULL) {
  217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  218. "Error in filling HTT metadata\n");
  219. return 0;
  220. }
  221. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  222. } else if (vdev->opmode == wlan_op_mode_ocb) {
  223. /* Todo - Add support for DSRC */
  224. }
  225. return htt_desc_size_aligned;
  226. }
  227. /**
  228. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  229. * @tso_seg: TSO segment to process
  230. * @ext_desc: Pointer to MSDU extension descriptor
  231. *
  232. * Return: void
  233. */
  234. #if defined(FEATURE_TSO)
  235. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  236. void *ext_desc)
  237. {
  238. uint8_t num_frag;
  239. uint32_t tso_flags;
  240. /*
  241. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  242. * tcp_flag_mask
  243. *
  244. * Checksum enable flags are set in TCL descriptor and not in Extension
  245. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  246. */
  247. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  248. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  249. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  250. tso_seg->tso_flags.ip_len);
  251. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  252. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  253. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  254. uint32_t lo = 0;
  255. uint32_t hi = 0;
  256. qdf_dmaaddr_to_32s(
  257. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  258. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  259. tso_seg->tso_frags[num_frag].length);
  260. }
  261. return;
  262. }
  263. #else
  264. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  265. void *ext_desc)
  266. {
  267. return;
  268. }
  269. #endif
  270. #if defined(FEATURE_TSO)
  271. /**
  272. * dp_tx_free_tso_seg() - Loop through the tso segments
  273. * allocated and free them
  274. *
  275. * @soc: soc handle
  276. * @free_seg: list of tso segments
  277. * @msdu_info: msdu descriptor
  278. *
  279. * Return - void
  280. */
  281. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  282. struct qdf_tso_seg_elem_t *free_seg,
  283. struct dp_tx_msdu_info_s *msdu_info)
  284. {
  285. struct qdf_tso_seg_elem_t *next_seg;
  286. while (free_seg) {
  287. next_seg = free_seg->next;
  288. dp_tx_tso_desc_free(soc,
  289. msdu_info->tx_queue.desc_pool_id,
  290. free_seg);
  291. free_seg = next_seg;
  292. }
  293. }
  294. /**
  295. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  296. * allocated and free them
  297. *
  298. * @soc: soc handle
  299. * @free_seg: list of tso segments
  300. * @msdu_info: msdu descriptor
  301. * Return - void
  302. */
  303. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  304. struct qdf_tso_num_seg_elem_t *free_seg,
  305. struct dp_tx_msdu_info_s *msdu_info)
  306. {
  307. struct qdf_tso_num_seg_elem_t *next_seg;
  308. while (free_seg) {
  309. next_seg = free_seg->next;
  310. dp_tso_num_seg_free(soc,
  311. msdu_info->tx_queue.desc_pool_id,
  312. free_seg);
  313. free_seg = next_seg;
  314. }
  315. }
  316. /**
  317. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  318. * @vdev: virtual device handle
  319. * @msdu: network buffer
  320. * @msdu_info: meta data associated with the msdu
  321. *
  322. * Return: QDF_STATUS_SUCCESS success
  323. */
  324. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  325. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  326. {
  327. struct qdf_tso_seg_elem_t *tso_seg;
  328. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  329. struct dp_soc *soc = vdev->pdev->soc;
  330. struct qdf_tso_info_t *tso_info;
  331. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  332. tso_info = &msdu_info->u.tso_info;
  333. tso_info->curr_seg = NULL;
  334. tso_info->tso_seg_list = NULL;
  335. tso_info->num_segs = num_seg;
  336. msdu_info->frm_type = dp_tx_frm_tso;
  337. tso_info->tso_num_seg_list = NULL;
  338. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  339. while (num_seg) {
  340. tso_seg = dp_tx_tso_desc_alloc(
  341. soc, msdu_info->tx_queue.desc_pool_id);
  342. if (tso_seg) {
  343. tso_seg->next = tso_info->tso_seg_list;
  344. tso_info->tso_seg_list = tso_seg;
  345. num_seg--;
  346. } else {
  347. struct qdf_tso_seg_elem_t *free_seg =
  348. tso_info->tso_seg_list;
  349. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  350. return QDF_STATUS_E_NOMEM;
  351. }
  352. }
  353. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  354. tso_num_seg = dp_tso_num_seg_alloc(soc,
  355. msdu_info->tx_queue.desc_pool_id);
  356. if (tso_num_seg) {
  357. tso_num_seg->next = tso_info->tso_num_seg_list;
  358. tso_info->tso_num_seg_list = tso_num_seg;
  359. } else {
  360. /* Bug: free tso_num_seg and tso_seg */
  361. /* Free the already allocated num of segments */
  362. struct qdf_tso_seg_elem_t *free_seg =
  363. tso_info->tso_seg_list;
  364. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  365. __func__);
  366. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  367. return QDF_STATUS_E_NOMEM;
  368. }
  369. msdu_info->num_seg =
  370. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  371. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  372. msdu_info->num_seg);
  373. if (!(msdu_info->num_seg)) {
  374. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  375. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  376. msdu_info);
  377. return QDF_STATUS_E_INVAL;
  378. }
  379. tso_info->curr_seg = tso_info->tso_seg_list;
  380. return QDF_STATUS_SUCCESS;
  381. }
  382. #else
  383. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  384. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  385. {
  386. return QDF_STATUS_E_NOMEM;
  387. }
  388. #endif
  389. /**
  390. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  391. * @vdev: DP Vdev handle
  392. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  393. * @desc_pool_id: Descriptor Pool ID
  394. *
  395. * Return:
  396. */
  397. static
  398. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  399. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  400. {
  401. uint8_t i;
  402. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  403. struct dp_tx_seg_info_s *seg_info;
  404. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  405. struct dp_soc *soc = vdev->pdev->soc;
  406. /* Allocate an extension descriptor */
  407. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  408. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  409. if (!msdu_ext_desc) {
  410. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  411. return NULL;
  412. }
  413. if (msdu_info->exception_fw &&
  414. qdf_unlikely(vdev->mesh_vdev)) {
  415. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  416. &msdu_info->meta_data[0],
  417. sizeof(struct htt_tx_msdu_desc_ext2_t));
  418. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  419. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  420. } else
  421. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  422. switch (msdu_info->frm_type) {
  423. case dp_tx_frm_sg:
  424. case dp_tx_frm_me:
  425. case dp_tx_frm_raw:
  426. seg_info = msdu_info->u.sg_info.curr_seg;
  427. /* Update the buffer pointers in MSDU Extension Descriptor */
  428. for (i = 0; i < seg_info->frag_cnt; i++) {
  429. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  430. seg_info->frags[i].paddr_lo,
  431. seg_info->frags[i].paddr_hi,
  432. seg_info->frags[i].len);
  433. }
  434. break;
  435. case dp_tx_frm_tso:
  436. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  437. &cached_ext_desc[0]);
  438. break;
  439. default:
  440. break;
  441. }
  442. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  443. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  444. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  445. msdu_ext_desc->vaddr);
  446. return msdu_ext_desc;
  447. }
  448. /**
  449. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  450. * @vdev: DP vdev handle
  451. * @nbuf: skb
  452. * @desc_pool_id: Descriptor pool ID
  453. * @meta_data: Metadata to the fw
  454. * @tx_exc_metadata: Handle that holds exception path metadata
  455. * Allocate and prepare Tx descriptor with msdu information.
  456. *
  457. * Return: Pointer to Tx Descriptor on success,
  458. * NULL on failure
  459. */
  460. static
  461. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  462. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  463. struct dp_tx_msdu_info_s *msdu_info,
  464. struct cdp_tx_exception_metadata *tx_exc_metadata)
  465. {
  466. uint8_t align_pad;
  467. uint8_t is_exception = 0;
  468. uint8_t htt_hdr_size;
  469. struct ether_header *eh;
  470. struct dp_tx_desc_s *tx_desc;
  471. struct dp_pdev *pdev = vdev->pdev;
  472. struct dp_soc *soc = pdev->soc;
  473. /* Allocate software Tx descriptor */
  474. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  475. if (qdf_unlikely(!tx_desc)) {
  476. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  477. return NULL;
  478. }
  479. /* Flow control/Congestion Control counters */
  480. qdf_atomic_inc(&pdev->num_tx_outstanding);
  481. /* Initialize the SW tx descriptor */
  482. tx_desc->nbuf = nbuf;
  483. tx_desc->frm_type = dp_tx_frm_std;
  484. tx_desc->tx_encap_type = (tx_exc_metadata ?
  485. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  486. tx_desc->vdev = vdev;
  487. tx_desc->pdev = pdev;
  488. tx_desc->msdu_ext_desc = NULL;
  489. tx_desc->pkt_offset = 0;
  490. /*
  491. * For special modes (vdev_type == ocb or mesh), data frames should be
  492. * transmitted using varying transmit parameters (tx spec) which include
  493. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  494. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  495. * These frames are sent as exception packets to firmware.
  496. *
  497. * HW requirement is that metadata should always point to a
  498. * 8-byte aligned address. So we add alignment pad to start of buffer.
  499. * HTT Metadata should be ensured to be multiple of 8-bytes,
  500. * to get 8-byte aligned start address along with align_pad added
  501. *
  502. * |-----------------------------|
  503. * | |
  504. * |-----------------------------| <-----Buffer Pointer Address given
  505. * | | ^ in HW descriptor (aligned)
  506. * | HTT Metadata | |
  507. * | | |
  508. * | | | Packet Offset given in descriptor
  509. * | | |
  510. * |-----------------------------| |
  511. * | Alignment Pad | v
  512. * |-----------------------------| <----- Actual buffer start address
  513. * | SKB Data | (Unaligned)
  514. * | |
  515. * | |
  516. * | |
  517. * | |
  518. * | |
  519. * |-----------------------------|
  520. */
  521. if (qdf_unlikely((msdu_info->exception_fw)) ||
  522. (vdev->opmode == wlan_op_mode_ocb)) {
  523. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  524. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  525. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  526. "qdf_nbuf_push_head failed\n");
  527. goto failure;
  528. }
  529. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  530. msdu_info->meta_data);
  531. if (htt_hdr_size == 0)
  532. goto failure;
  533. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  534. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  535. is_exception = 1;
  536. }
  537. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  538. qdf_nbuf_map(soc->osdev, nbuf,
  539. QDF_DMA_TO_DEVICE))) {
  540. /* Handle failure */
  541. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  542. "qdf_nbuf_map failed\n");
  543. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  544. goto failure;
  545. }
  546. if (qdf_unlikely(vdev->nawds_enabled)) {
  547. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  548. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  549. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  550. is_exception = 1;
  551. }
  552. }
  553. #if !TQM_BYPASS_WAR
  554. if (is_exception || tx_exc_metadata)
  555. #endif
  556. {
  557. /* Temporary WAR due to TQM VP issues */
  558. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  559. qdf_atomic_inc(&pdev->num_tx_exception);
  560. }
  561. return tx_desc;
  562. failure:
  563. dp_tx_desc_release(tx_desc, desc_pool_id);
  564. return NULL;
  565. }
  566. /**
  567. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  568. * @vdev: DP vdev handle
  569. * @nbuf: skb
  570. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  571. * @desc_pool_id : Descriptor Pool ID
  572. *
  573. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  574. * information. For frames wth fragments, allocate and prepare
  575. * an MSDU extension descriptor
  576. *
  577. * Return: Pointer to Tx Descriptor on success,
  578. * NULL on failure
  579. */
  580. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  581. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  582. uint8_t desc_pool_id)
  583. {
  584. struct dp_tx_desc_s *tx_desc;
  585. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  586. struct dp_pdev *pdev = vdev->pdev;
  587. struct dp_soc *soc = pdev->soc;
  588. /* Allocate software Tx descriptor */
  589. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  590. if (!tx_desc) {
  591. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  592. return NULL;
  593. }
  594. /* Flow control/Congestion Control counters */
  595. qdf_atomic_inc(&pdev->num_tx_outstanding);
  596. /* Initialize the SW tx descriptor */
  597. tx_desc->nbuf = nbuf;
  598. tx_desc->frm_type = msdu_info->frm_type;
  599. tx_desc->tx_encap_type = vdev->tx_encap_type;
  600. tx_desc->vdev = vdev;
  601. tx_desc->pdev = pdev;
  602. tx_desc->pkt_offset = 0;
  603. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  604. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  605. /* Handle scattered frames - TSO/SG/ME */
  606. /* Allocate and prepare an extension descriptor for scattered frames */
  607. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  608. if (!msdu_ext_desc) {
  609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  610. "%s Tx Extension Descriptor Alloc Fail\n",
  611. __func__);
  612. goto failure;
  613. }
  614. #if TQM_BYPASS_WAR
  615. /* Temporary WAR due to TQM VP issues */
  616. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  617. qdf_atomic_inc(&pdev->num_tx_exception);
  618. #endif
  619. if (qdf_unlikely(msdu_info->exception_fw))
  620. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  621. tx_desc->msdu_ext_desc = msdu_ext_desc;
  622. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  623. return tx_desc;
  624. failure:
  625. dp_tx_desc_release(tx_desc, desc_pool_id);
  626. return NULL;
  627. }
  628. /**
  629. * dp_tx_prepare_raw() - Prepare RAW packet TX
  630. * @vdev: DP vdev handle
  631. * @nbuf: buffer pointer
  632. * @seg_info: Pointer to Segment info Descriptor to be prepared
  633. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  634. * descriptor
  635. *
  636. * Return:
  637. */
  638. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  639. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  640. {
  641. qdf_nbuf_t curr_nbuf = NULL;
  642. uint16_t total_len = 0;
  643. qdf_dma_addr_t paddr;
  644. int32_t i;
  645. int32_t mapped_buf_num = 0;
  646. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  647. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  648. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  649. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  650. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  651. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  652. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  653. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  654. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  655. QDF_DMA_TO_DEVICE)) {
  656. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  657. "%s dma map error \n", __func__);
  658. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  659. mapped_buf_num = i;
  660. goto error;
  661. }
  662. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  663. seg_info->frags[i].paddr_lo = paddr;
  664. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  665. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  666. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  667. total_len += qdf_nbuf_len(curr_nbuf);
  668. }
  669. seg_info->frag_cnt = i;
  670. seg_info->total_len = total_len;
  671. seg_info->next = NULL;
  672. sg_info->curr_seg = seg_info;
  673. msdu_info->frm_type = dp_tx_frm_raw;
  674. msdu_info->num_seg = 1;
  675. return nbuf;
  676. error:
  677. i = 0;
  678. while (nbuf) {
  679. curr_nbuf = nbuf;
  680. if (i < mapped_buf_num) {
  681. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  682. i++;
  683. }
  684. nbuf = qdf_nbuf_next(nbuf);
  685. qdf_nbuf_free(curr_nbuf);
  686. }
  687. return NULL;
  688. }
  689. /**
  690. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  691. * @soc: DP Soc Handle
  692. * @vdev: DP vdev handle
  693. * @tx_desc: Tx Descriptor Handle
  694. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  695. * @fw_metadata: Metadata to send to Target Firmware along with frame
  696. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  697. * @tx_exc_metadata: Handle that holds exception path meta data
  698. *
  699. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  700. * from software Tx descriptor
  701. *
  702. * Return:
  703. */
  704. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  705. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  706. uint16_t fw_metadata, uint8_t ring_id,
  707. struct cdp_tx_exception_metadata
  708. *tx_exc_metadata)
  709. {
  710. uint8_t type;
  711. uint16_t length;
  712. void *hal_tx_desc, *hal_tx_desc_cached;
  713. qdf_dma_addr_t dma_addr;
  714. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  715. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  716. tx_exc_metadata->sec_type : vdev->sec_type);
  717. /* Return Buffer Manager ID */
  718. uint8_t bm_id = ring_id;
  719. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  720. hal_tx_desc_cached = (void *) cached_desc;
  721. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  722. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  723. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  724. type = HAL_TX_BUF_TYPE_EXT_DESC;
  725. dma_addr = tx_desc->msdu_ext_desc->paddr;
  726. } else {
  727. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  728. type = HAL_TX_BUF_TYPE_BUFFER;
  729. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  730. }
  731. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  732. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  733. dma_addr , bm_id, tx_desc->id, type);
  734. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  735. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  736. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  737. hal_tx_desc_set_lmac_id(hal_tx_desc_cached,
  738. HAL_TX_DESC_DEFAULT_LMAC_ID);
  739. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  740. vdev->dscp_tid_map_id);
  741. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  742. sec_type_map[sec_type]);
  743. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  744. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  745. __func__, length, type, (uint64_t)dma_addr,
  746. tx_desc->pkt_offset, tx_desc->id);
  747. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  748. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  749. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  750. vdev->hal_desc_addr_search_flags);
  751. /* verify checksum offload configuration*/
  752. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  753. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  754. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  755. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  756. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  757. }
  758. if (tid != HTT_TX_EXT_TID_INVALID)
  759. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  760. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  761. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  762. /* Sync cached descriptor with HW */
  763. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  764. if (!hal_tx_desc) {
  765. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  766. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  767. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  768. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  769. return QDF_STATUS_E_RESOURCES;
  770. }
  771. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  772. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  773. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  774. /*
  775. * If one packet is enqueued in HW, PM usage count needs to be
  776. * incremented by one to prevent future runtime suspend. This
  777. * should be tied with the success of enqueuing. It will be
  778. * decremented after the packet has been sent.
  779. */
  780. hif_pm_runtime_get_noresume(soc->hif_handle);
  781. return QDF_STATUS_SUCCESS;
  782. }
  783. /**
  784. * dp_cce_classify() - Classify the frame based on CCE rules
  785. * @vdev: DP vdev handle
  786. * @nbuf: skb
  787. *
  788. * Classify frames based on CCE rules
  789. * Return: bool( true if classified,
  790. * else false)
  791. */
  792. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  793. {
  794. struct ether_header *eh = NULL;
  795. uint16_t ether_type;
  796. qdf_llc_t *llcHdr;
  797. qdf_nbuf_t nbuf_clone = NULL;
  798. qdf_dot3_qosframe_t *qos_wh = NULL;
  799. /* for mesh packets don't do any classification */
  800. if (qdf_unlikely(vdev->mesh_vdev))
  801. return false;
  802. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  803. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  804. ether_type = eh->ether_type;
  805. llcHdr = (qdf_llc_t *)(nbuf->data +
  806. sizeof(struct ether_header));
  807. } else {
  808. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  809. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  810. if (qdf_unlikely(
  811. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  812. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  813. ether_type = *(uint16_t *)(nbuf->data
  814. + QDF_IEEE80211_4ADDR_HDR_LEN
  815. + sizeof(qdf_llc_t)
  816. - sizeof(ether_type));
  817. llcHdr = (qdf_llc_t *)(nbuf->data +
  818. QDF_IEEE80211_4ADDR_HDR_LEN);
  819. } else {
  820. ether_type = *(uint16_t *)(nbuf->data
  821. + QDF_IEEE80211_3ADDR_HDR_LEN
  822. + sizeof(qdf_llc_t)
  823. - sizeof(ether_type));
  824. llcHdr = (qdf_llc_t *)(nbuf->data +
  825. QDF_IEEE80211_3ADDR_HDR_LEN);
  826. }
  827. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  828. && (ether_type ==
  829. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  830. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  831. return true;
  832. }
  833. }
  834. return false;
  835. }
  836. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  837. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  838. sizeof(*llcHdr));
  839. nbuf_clone = qdf_nbuf_clone(nbuf);
  840. if (qdf_unlikely(nbuf_clone)) {
  841. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  842. if (ether_type == htons(ETHERTYPE_8021Q)) {
  843. qdf_nbuf_pull_head(nbuf_clone,
  844. sizeof(qdf_net_vlanhdr_t));
  845. }
  846. }
  847. } else {
  848. if (ether_type == htons(ETHERTYPE_8021Q)) {
  849. nbuf_clone = qdf_nbuf_clone(nbuf);
  850. if (qdf_unlikely(nbuf_clone)) {
  851. qdf_nbuf_pull_head(nbuf_clone,
  852. sizeof(qdf_net_vlanhdr_t));
  853. }
  854. }
  855. }
  856. if (qdf_unlikely(nbuf_clone))
  857. nbuf = nbuf_clone;
  858. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  859. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  860. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  861. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  862. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  863. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  864. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  865. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  866. if (qdf_unlikely(nbuf_clone != NULL))
  867. qdf_nbuf_free(nbuf_clone);
  868. return true;
  869. }
  870. if (qdf_unlikely(nbuf_clone != NULL))
  871. qdf_nbuf_free(nbuf_clone);
  872. return false;
  873. }
  874. /**
  875. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  876. * @vdev: DP vdev handle
  877. * @nbuf: skb
  878. *
  879. * Extract the DSCP or PCP information from frame and map into TID value.
  880. * Software based TID classification is required when more than 2 DSCP-TID
  881. * mapping tables are needed.
  882. * Hardware supports 2 DSCP-TID mapping tables
  883. *
  884. * Return: void
  885. */
  886. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  887. struct dp_tx_msdu_info_s *msdu_info)
  888. {
  889. uint8_t tos = 0, dscp_tid_override = 0;
  890. uint8_t *hdr_ptr, *L3datap;
  891. uint8_t is_mcast = 0;
  892. struct ether_header *eh = NULL;
  893. qdf_ethervlan_header_t *evh = NULL;
  894. uint16_t ether_type;
  895. qdf_llc_t *llcHdr;
  896. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  897. /* for mesh packets don't do any classification */
  898. if (qdf_unlikely(vdev->mesh_vdev))
  899. return;
  900. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  901. eh = (struct ether_header *) nbuf->data;
  902. hdr_ptr = eh->ether_dhost;
  903. L3datap = hdr_ptr + sizeof(struct ether_header);
  904. } else {
  905. qdf_dot3_qosframe_t *qos_wh =
  906. (qdf_dot3_qosframe_t *) nbuf->data;
  907. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  908. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  909. return;
  910. }
  911. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  912. ether_type = eh->ether_type;
  913. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  914. /*
  915. * Check if packet is dot3 or eth2 type.
  916. */
  917. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  918. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  919. sizeof(*llcHdr));
  920. if (ether_type == htons(ETHERTYPE_8021Q)) {
  921. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  922. sizeof(*llcHdr);
  923. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  924. + sizeof(*llcHdr) +
  925. sizeof(qdf_net_vlanhdr_t));
  926. } else {
  927. L3datap = hdr_ptr + sizeof(struct ether_header) +
  928. sizeof(*llcHdr);
  929. }
  930. } else {
  931. if (ether_type == htons(ETHERTYPE_8021Q)) {
  932. evh = (qdf_ethervlan_header_t *) eh;
  933. ether_type = evh->ether_type;
  934. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  935. }
  936. }
  937. /*
  938. * Find priority from IP TOS DSCP field
  939. */
  940. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  941. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  942. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  943. /* Only for unicast frames */
  944. if (!is_mcast) {
  945. /* send it on VO queue */
  946. msdu_info->tid = DP_VO_TID;
  947. }
  948. } else {
  949. /*
  950. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  951. * from TOS byte.
  952. */
  953. tos = ip->ip_tos;
  954. dscp_tid_override = 1;
  955. }
  956. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  957. /* TODO
  958. * use flowlabel
  959. *igmpmld cases to be handled in phase 2
  960. */
  961. unsigned long ver_pri_flowlabel;
  962. unsigned long pri;
  963. ver_pri_flowlabel = *(unsigned long *) L3datap;
  964. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  965. DP_IPV6_PRIORITY_SHIFT;
  966. tos = pri;
  967. dscp_tid_override = 1;
  968. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  969. msdu_info->tid = DP_VO_TID;
  970. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  971. /* Only for unicast frames */
  972. if (!is_mcast) {
  973. /* send ucast arp on VO queue */
  974. msdu_info->tid = DP_VO_TID;
  975. }
  976. }
  977. /*
  978. * Assign all MCAST packets to BE
  979. */
  980. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  981. if (is_mcast) {
  982. tos = 0;
  983. dscp_tid_override = 1;
  984. }
  985. }
  986. if (dscp_tid_override == 1) {
  987. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  988. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  989. }
  990. return;
  991. }
  992. #ifdef CONVERGED_TDLS_ENABLE
  993. /**
  994. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  995. * @tx_desc: TX descriptor
  996. *
  997. * Return: None
  998. */
  999. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1000. {
  1001. if (tx_desc->vdev) {
  1002. if (tx_desc->vdev->is_tdls_frame)
  1003. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1004. tx_desc->vdev->is_tdls_frame = false;
  1005. }
  1006. }
  1007. /**
  1008. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1009. * @tx_desc: TX descriptor
  1010. * @vdev: datapath vdev handle
  1011. *
  1012. * Return: None
  1013. */
  1014. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1015. struct dp_vdev *vdev)
  1016. {
  1017. struct hal_tx_completion_status ts = {0};
  1018. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1019. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1020. if (vdev->tx_non_std_data_callback.func) {
  1021. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1022. vdev->tx_non_std_data_callback.func(
  1023. vdev->tx_non_std_data_callback.ctxt,
  1024. nbuf, ts.status);
  1025. return;
  1026. }
  1027. }
  1028. #endif
  1029. /**
  1030. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1031. * @vdev: DP vdev handle
  1032. * @nbuf: skb
  1033. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1034. * @meta_data: Metadata to the fw
  1035. * @tx_q: Tx queue to be used for this Tx frame
  1036. * @peer_id: peer_id of the peer in case of NAWDS frames
  1037. * @tx_exc_metadata: Handle that holds exception path metadata
  1038. *
  1039. * Return: NULL on success,
  1040. * nbuf when it fails to send
  1041. */
  1042. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1043. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1044. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1045. {
  1046. struct dp_pdev *pdev = vdev->pdev;
  1047. struct dp_soc *soc = pdev->soc;
  1048. struct dp_tx_desc_s *tx_desc;
  1049. QDF_STATUS status;
  1050. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1051. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1052. uint16_t htt_tcl_metadata = 0;
  1053. uint8_t tid = msdu_info->tid;
  1054. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  1055. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1056. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1057. msdu_info, tx_exc_metadata);
  1058. if (!tx_desc) {
  1059. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1060. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1061. __func__, vdev, tx_q->desc_pool_id);
  1062. return nbuf;
  1063. }
  1064. if (qdf_unlikely(soc->cce_disable)) {
  1065. if (dp_cce_classify(vdev, nbuf) == true) {
  1066. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1067. tid = DP_VO_TID;
  1068. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1069. }
  1070. }
  1071. dp_tx_update_tdls_flags(tx_desc);
  1072. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1073. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1074. "%s %d : HAL RING Access Failed -- %pK\n",
  1075. __func__, __LINE__, hal_srng);
  1076. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1077. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1078. goto fail_return;
  1079. }
  1080. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1081. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1082. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1083. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1084. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1085. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1086. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1087. peer_id);
  1088. } else
  1089. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1090. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1091. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1092. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1093. if (status != QDF_STATUS_SUCCESS) {
  1094. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1095. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1096. __func__, tx_desc, tx_q->ring_id);
  1097. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1098. goto fail_return;
  1099. }
  1100. nbuf = NULL;
  1101. fail_return:
  1102. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1103. hal_srng_access_end(soc->hal_soc, hal_srng);
  1104. hif_pm_runtime_put(soc->hif_handle);
  1105. } else {
  1106. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1107. }
  1108. return nbuf;
  1109. }
  1110. /**
  1111. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1112. * @vdev: DP vdev handle
  1113. * @nbuf: skb
  1114. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1115. *
  1116. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1117. *
  1118. * Return: NULL on success,
  1119. * nbuf when it fails to send
  1120. */
  1121. #if QDF_LOCK_STATS
  1122. static noinline
  1123. #else
  1124. static
  1125. #endif
  1126. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1127. struct dp_tx_msdu_info_s *msdu_info)
  1128. {
  1129. uint8_t i;
  1130. struct dp_pdev *pdev = vdev->pdev;
  1131. struct dp_soc *soc = pdev->soc;
  1132. struct dp_tx_desc_s *tx_desc;
  1133. bool is_cce_classified = false;
  1134. QDF_STATUS status;
  1135. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1136. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1137. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1138. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1139. "%s %d : HAL RING Access Failed -- %pK\n",
  1140. __func__, __LINE__, hal_srng);
  1141. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1142. return nbuf;
  1143. }
  1144. if (qdf_unlikely(soc->cce_disable)) {
  1145. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1146. if (is_cce_classified) {
  1147. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1148. msdu_info->tid = DP_VO_TID;
  1149. }
  1150. }
  1151. if (msdu_info->frm_type == dp_tx_frm_me)
  1152. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1153. i = 0;
  1154. /* Print statement to track i and num_seg */
  1155. /*
  1156. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1157. * descriptors using information in msdu_info
  1158. */
  1159. while (i < msdu_info->num_seg) {
  1160. /*
  1161. * Setup Tx descriptor for an MSDU, and MSDU extension
  1162. * descriptor
  1163. */
  1164. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1165. tx_q->desc_pool_id);
  1166. if (!tx_desc) {
  1167. if (msdu_info->frm_type == dp_tx_frm_me) {
  1168. dp_tx_me_free_buf(pdev,
  1169. (void *)(msdu_info->u.sg_info
  1170. .curr_seg->frags[0].vaddr));
  1171. }
  1172. goto done;
  1173. }
  1174. if (msdu_info->frm_type == dp_tx_frm_me) {
  1175. tx_desc->me_buffer =
  1176. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1177. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1178. }
  1179. if (is_cce_classified)
  1180. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1181. /*
  1182. * Enqueue the Tx MSDU descriptor to HW for transmit
  1183. */
  1184. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1185. vdev->htt_tcl_metadata, tx_q->ring_id, NULL);
  1186. if (status != QDF_STATUS_SUCCESS) {
  1187. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1188. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1189. __func__, tx_desc, tx_q->ring_id);
  1190. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1191. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1192. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1193. goto done;
  1194. }
  1195. /*
  1196. * TODO
  1197. * if tso_info structure can be modified to have curr_seg
  1198. * as first element, following 2 blocks of code (for TSO and SG)
  1199. * can be combined into 1
  1200. */
  1201. /*
  1202. * For frames with multiple segments (TSO, ME), jump to next
  1203. * segment.
  1204. */
  1205. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1206. if (msdu_info->u.tso_info.curr_seg->next) {
  1207. msdu_info->u.tso_info.curr_seg =
  1208. msdu_info->u.tso_info.curr_seg->next;
  1209. /*
  1210. * If this is a jumbo nbuf, then increment the number of
  1211. * nbuf users for each additional segment of the msdu.
  1212. * This will ensure that the skb is freed only after
  1213. * receiving tx completion for all segments of an nbuf
  1214. */
  1215. qdf_nbuf_inc_users(nbuf);
  1216. /* Check with MCL if this is needed */
  1217. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1218. }
  1219. }
  1220. /*
  1221. * For Multicast-Unicast converted packets,
  1222. * each converted frame (for a client) is represented as
  1223. * 1 segment
  1224. */
  1225. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1226. (msdu_info->frm_type == dp_tx_frm_me)) {
  1227. if (msdu_info->u.sg_info.curr_seg->next) {
  1228. msdu_info->u.sg_info.curr_seg =
  1229. msdu_info->u.sg_info.curr_seg->next;
  1230. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1231. }
  1232. }
  1233. i++;
  1234. }
  1235. nbuf = NULL;
  1236. done:
  1237. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1238. hal_srng_access_end(soc->hal_soc, hal_srng);
  1239. hif_pm_runtime_put(soc->hif_handle);
  1240. } else {
  1241. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1242. }
  1243. return nbuf;
  1244. }
  1245. /**
  1246. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1247. * for SG frames
  1248. * @vdev: DP vdev handle
  1249. * @nbuf: skb
  1250. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1251. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1252. *
  1253. * Return: NULL on success,
  1254. * nbuf when it fails to send
  1255. */
  1256. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1257. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1258. {
  1259. uint32_t cur_frag, nr_frags;
  1260. qdf_dma_addr_t paddr;
  1261. struct dp_tx_sg_info_s *sg_info;
  1262. sg_info = &msdu_info->u.sg_info;
  1263. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1264. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1265. QDF_DMA_TO_DEVICE)) {
  1266. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1267. "dma map error\n");
  1268. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1269. qdf_nbuf_free(nbuf);
  1270. return NULL;
  1271. }
  1272. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1273. seg_info->frags[0].paddr_lo = paddr;
  1274. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1275. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1276. seg_info->frags[0].vaddr = (void *) nbuf;
  1277. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1278. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1279. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1280. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1281. "frag dma map error\n");
  1282. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1283. qdf_nbuf_free(nbuf);
  1284. return NULL;
  1285. }
  1286. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1287. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1288. seg_info->frags[cur_frag + 1].paddr_hi =
  1289. ((uint64_t) paddr) >> 32;
  1290. seg_info->frags[cur_frag + 1].len =
  1291. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1292. }
  1293. seg_info->frag_cnt = (cur_frag + 1);
  1294. seg_info->total_len = qdf_nbuf_len(nbuf);
  1295. seg_info->next = NULL;
  1296. sg_info->curr_seg = seg_info;
  1297. msdu_info->frm_type = dp_tx_frm_sg;
  1298. msdu_info->num_seg = 1;
  1299. return nbuf;
  1300. }
  1301. #ifdef MESH_MODE_SUPPORT
  1302. /**
  1303. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1304. and prepare msdu_info for mesh frames.
  1305. * @vdev: DP vdev handle
  1306. * @nbuf: skb
  1307. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1308. *
  1309. * Return: NULL on failure,
  1310. * nbuf when extracted successfully
  1311. */
  1312. static
  1313. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1314. struct dp_tx_msdu_info_s *msdu_info)
  1315. {
  1316. struct meta_hdr_s *mhdr;
  1317. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1318. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1319. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1320. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1321. msdu_info->exception_fw = 0;
  1322. goto remove_meta_hdr;
  1323. }
  1324. msdu_info->exception_fw = 1;
  1325. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1326. meta_data->host_tx_desc_pool = 1;
  1327. meta_data->update_peer_cache = 1;
  1328. meta_data->learning_frame = 1;
  1329. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1330. meta_data->power = mhdr->power;
  1331. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1332. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1333. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1334. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1335. meta_data->dyn_bw = 1;
  1336. meta_data->valid_pwr = 1;
  1337. meta_data->valid_mcs_mask = 1;
  1338. meta_data->valid_nss_mask = 1;
  1339. meta_data->valid_preamble_type = 1;
  1340. meta_data->valid_retries = 1;
  1341. meta_data->valid_bw_info = 1;
  1342. }
  1343. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1344. meta_data->encrypt_type = 0;
  1345. meta_data->valid_encrypt_type = 1;
  1346. meta_data->learning_frame = 0;
  1347. }
  1348. meta_data->valid_key_flags = 1;
  1349. meta_data->key_flags = (mhdr->keyix & 0x3);
  1350. remove_meta_hdr:
  1351. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1352. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1353. "qdf_nbuf_pull_head failed\n");
  1354. qdf_nbuf_free(nbuf);
  1355. return NULL;
  1356. }
  1357. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1358. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1359. else
  1360. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1361. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1362. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1363. " tid %d to_fw %d\n",
  1364. __func__, msdu_info->meta_data[0],
  1365. msdu_info->meta_data[1],
  1366. msdu_info->meta_data[2],
  1367. msdu_info->meta_data[3],
  1368. msdu_info->meta_data[4],
  1369. msdu_info->meta_data[5],
  1370. msdu_info->tid, msdu_info->exception_fw);
  1371. return nbuf;
  1372. }
  1373. #else
  1374. static
  1375. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1376. struct dp_tx_msdu_info_s *msdu_info)
  1377. {
  1378. return nbuf;
  1379. }
  1380. #endif
  1381. #ifdef DP_FEATURE_NAWDS_TX
  1382. /**
  1383. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1384. * @vdev: dp_vdev handle
  1385. * @nbuf: skb
  1386. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1387. * @tx_q: Tx queue to be used for this Tx frame
  1388. * @meta_data: Meta date for mesh
  1389. * @peer_id: peer_id of the peer in case of NAWDS frames
  1390. *
  1391. * return: NULL on success nbuf on failure
  1392. */
  1393. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1394. struct dp_tx_msdu_info_s *msdu_info)
  1395. {
  1396. struct dp_peer *peer = NULL;
  1397. struct dp_soc *soc = vdev->pdev->soc;
  1398. struct dp_ast_entry *ast_entry = NULL;
  1399. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1400. uint16_t peer_id = HTT_INVALID_PEER;
  1401. struct dp_peer *sa_peer = NULL;
  1402. qdf_nbuf_t nbuf_copy;
  1403. qdf_spin_lock_bh(&(soc->ast_lock));
  1404. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1405. if (ast_entry)
  1406. sa_peer = ast_entry->peer;
  1407. qdf_spin_unlock_bh(&(soc->ast_lock));
  1408. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1409. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1410. (peer->nawds_enabled)) {
  1411. if (sa_peer == peer) {
  1412. QDF_TRACE(QDF_MODULE_ID_DP,
  1413. QDF_TRACE_LEVEL_DEBUG,
  1414. " %s: broadcast multicast packet",
  1415. __func__);
  1416. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1417. continue;
  1418. }
  1419. nbuf_copy = qdf_nbuf_copy(nbuf);
  1420. if (!nbuf_copy) {
  1421. QDF_TRACE(QDF_MODULE_ID_DP,
  1422. QDF_TRACE_LEVEL_ERROR,
  1423. "nbuf copy failed");
  1424. }
  1425. peer_id = peer->peer_ids[0];
  1426. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1427. msdu_info, peer_id, NULL);
  1428. if (nbuf_copy != NULL) {
  1429. qdf_nbuf_free(nbuf_copy);
  1430. continue;
  1431. }
  1432. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1433. 1, qdf_nbuf_len(nbuf));
  1434. }
  1435. }
  1436. if (peer_id == HTT_INVALID_PEER)
  1437. return nbuf;
  1438. return NULL;
  1439. }
  1440. #endif
  1441. /**
  1442. * dp_check_exc_metadata() - Checks if parameters are valid
  1443. * @tx_exc - holds all exception path parameters
  1444. *
  1445. * Returns true when all the parameters are valid else false
  1446. *
  1447. */
  1448. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1449. {
  1450. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1451. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1452. tx_exc->sec_type > cdp_num_sec_types) {
  1453. return false;
  1454. }
  1455. return true;
  1456. }
  1457. /**
  1458. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1459. * @vap_dev: DP vdev handle
  1460. * @nbuf: skb
  1461. * @tx_exc_metadata: Handle that holds exception path meta data
  1462. *
  1463. * Entry point for Core Tx layer (DP_TX) invoked from
  1464. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1465. *
  1466. * Return: NULL on success,
  1467. * nbuf when it fails to send
  1468. */
  1469. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1470. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1471. {
  1472. struct ether_header *eh = NULL;
  1473. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1474. struct dp_tx_msdu_info_s msdu_info;
  1475. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1476. msdu_info.tid = tx_exc_metadata->tid;
  1477. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1478. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1479. "%s , skb %pM",
  1480. __func__, nbuf->data);
  1481. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1482. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1483. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1484. "Invalid parameters in exception path");
  1485. goto fail;
  1486. }
  1487. /* Basic sanity checks for unsupported packets */
  1488. /* MESH mode */
  1489. if (qdf_unlikely(vdev->mesh_vdev)) {
  1490. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1491. "Mesh mode is not supported in exception path");
  1492. goto fail;
  1493. }
  1494. /* TSO or SG */
  1495. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1496. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1497. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1498. "TSO and SG are not supported in exception path");
  1499. goto fail;
  1500. }
  1501. /* RAW */
  1502. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1503. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1504. "Raw frame is not supported in exception path");
  1505. goto fail;
  1506. }
  1507. /* Mcast enhancement*/
  1508. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1509. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1510. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1511. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW\n");
  1512. }
  1513. }
  1514. /*
  1515. * Get HW Queue to use for this frame.
  1516. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1517. * dedicated for data and 1 for command.
  1518. * "queue_id" maps to one hardware ring.
  1519. * With each ring, we also associate a unique Tx descriptor pool
  1520. * to minimize lock contention for these resources.
  1521. */
  1522. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1523. /* Reset the control block */
  1524. qdf_nbuf_reset_ctxt(nbuf);
  1525. /* Single linear frame */
  1526. /*
  1527. * If nbuf is a simple linear frame, use send_single function to
  1528. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1529. * SRNG. There is no need to setup a MSDU extension descriptor.
  1530. */
  1531. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1532. tx_exc_metadata->peer_id, tx_exc_metadata);
  1533. return nbuf;
  1534. fail:
  1535. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1536. "pkt send failed");
  1537. return nbuf;
  1538. }
  1539. /**
  1540. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1541. * @vap_dev: DP vdev handle
  1542. * @nbuf: skb
  1543. *
  1544. * Entry point for Core Tx layer (DP_TX) invoked from
  1545. * hard_start_xmit in OSIF/HDD
  1546. *
  1547. * Return: NULL on success,
  1548. * nbuf when it fails to send
  1549. */
  1550. #ifdef MESH_MODE_SUPPORT
  1551. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1552. {
  1553. struct meta_hdr_s *mhdr;
  1554. qdf_nbuf_t nbuf_mesh = NULL;
  1555. qdf_nbuf_t nbuf_clone = NULL;
  1556. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1557. uint8_t no_enc_frame = 0;
  1558. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1559. if (nbuf_mesh == NULL) {
  1560. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1561. "qdf_nbuf_unshare failed\n");
  1562. return nbuf;
  1563. }
  1564. nbuf = nbuf_mesh;
  1565. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1566. if ((vdev->sec_type != cdp_sec_type_none) &&
  1567. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1568. no_enc_frame = 1;
  1569. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1570. !no_enc_frame) {
  1571. nbuf_clone = qdf_nbuf_clone(nbuf);
  1572. if (nbuf_clone == NULL) {
  1573. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1574. "qdf_nbuf_clone failed\n");
  1575. return nbuf;
  1576. }
  1577. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1578. }
  1579. if (nbuf_clone) {
  1580. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1581. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1582. } else
  1583. qdf_nbuf_free(nbuf_clone);
  1584. }
  1585. if (no_enc_frame)
  1586. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1587. else
  1588. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1589. nbuf = dp_tx_send(vap_dev, nbuf);
  1590. if ((nbuf == NULL) && no_enc_frame) {
  1591. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1592. }
  1593. return nbuf;
  1594. }
  1595. #else
  1596. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1597. {
  1598. return dp_tx_send(vap_dev, nbuf);
  1599. }
  1600. #endif
  1601. /**
  1602. * dp_tx_send() - Transmit a frame on a given VAP
  1603. * @vap_dev: DP vdev handle
  1604. * @nbuf: skb
  1605. *
  1606. * Entry point for Core Tx layer (DP_TX) invoked from
  1607. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1608. * cases
  1609. *
  1610. * Return: NULL on success,
  1611. * nbuf when it fails to send
  1612. */
  1613. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1614. {
  1615. struct ether_header *eh = NULL;
  1616. struct dp_tx_msdu_info_s msdu_info;
  1617. struct dp_tx_seg_info_s seg_info;
  1618. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1619. uint16_t peer_id = HTT_INVALID_PEER;
  1620. qdf_nbuf_t nbuf_mesh = NULL;
  1621. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1622. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1623. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1624. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1625. "%s , skb %pM",
  1626. __func__, nbuf->data);
  1627. /*
  1628. * Set Default Host TID value to invalid TID
  1629. * (TID override disabled)
  1630. */
  1631. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1632. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1633. if (qdf_unlikely(vdev->mesh_vdev)) {
  1634. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1635. &msdu_info);
  1636. if (nbuf_mesh == NULL) {
  1637. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1638. "Extracting mesh metadata failed\n");
  1639. return nbuf;
  1640. }
  1641. nbuf = nbuf_mesh;
  1642. }
  1643. /*
  1644. * Get HW Queue to use for this frame.
  1645. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1646. * dedicated for data and 1 for command.
  1647. * "queue_id" maps to one hardware ring.
  1648. * With each ring, we also associate a unique Tx descriptor pool
  1649. * to minimize lock contention for these resources.
  1650. */
  1651. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1652. /*
  1653. * TCL H/W supports 2 DSCP-TID mapping tables.
  1654. * Table 1 - Default DSCP-TID mapping table
  1655. * Table 2 - 1 DSCP-TID override table
  1656. *
  1657. * If we need a different DSCP-TID mapping for this vap,
  1658. * call tid_classify to extract DSCP/ToS from frame and
  1659. * map to a TID and store in msdu_info. This is later used
  1660. * to fill in TCL Input descriptor (per-packet TID override).
  1661. */
  1662. if (vdev->dscp_tid_map_id > 1)
  1663. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1664. /* Reset the control block */
  1665. qdf_nbuf_reset_ctxt(nbuf);
  1666. /*
  1667. * Classify the frame and call corresponding
  1668. * "prepare" function which extracts the segment (TSO)
  1669. * and fragmentation information (for TSO , SG, ME, or Raw)
  1670. * into MSDU_INFO structure which is later used to fill
  1671. * SW and HW descriptors.
  1672. */
  1673. if (qdf_nbuf_is_tso(nbuf)) {
  1674. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1675. "%s TSO frame %pK\n", __func__, vdev);
  1676. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1677. qdf_nbuf_len(nbuf));
  1678. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1679. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1680. return nbuf;
  1681. }
  1682. goto send_multiple;
  1683. }
  1684. /* SG */
  1685. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1686. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1687. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1688. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1689. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1690. qdf_nbuf_len(nbuf));
  1691. goto send_multiple;
  1692. }
  1693. #ifdef ATH_SUPPORT_IQUE
  1694. /* Mcast to Ucast Conversion*/
  1695. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1696. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1697. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1698. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1699. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1700. DP_STATS_INC_PKT(vdev,
  1701. tx_i.mcast_en.mcast_pkt, 1,
  1702. qdf_nbuf_len(nbuf));
  1703. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1704. QDF_STATUS_SUCCESS) {
  1705. return NULL;
  1706. }
  1707. }
  1708. }
  1709. #endif
  1710. /* RAW */
  1711. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1712. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1713. if (nbuf == NULL)
  1714. return NULL;
  1715. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1716. "%s Raw frame %pK\n", __func__, vdev);
  1717. goto send_multiple;
  1718. }
  1719. /* Single linear frame */
  1720. /*
  1721. * If nbuf is a simple linear frame, use send_single function to
  1722. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1723. * SRNG. There is no need to setup a MSDU extension descriptor.
  1724. */
  1725. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1726. return nbuf;
  1727. send_multiple:
  1728. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1729. return nbuf;
  1730. }
  1731. /**
  1732. * dp_tx_reinject_handler() - Tx Reinject Handler
  1733. * @tx_desc: software descriptor head pointer
  1734. * @status : Tx completion status from HTT descriptor
  1735. *
  1736. * This function reinjects frames back to Target.
  1737. * Todo - Host queue needs to be added
  1738. *
  1739. * Return: none
  1740. */
  1741. static
  1742. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1743. {
  1744. struct dp_vdev *vdev;
  1745. struct dp_peer *peer = NULL;
  1746. uint32_t peer_id = HTT_INVALID_PEER;
  1747. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1748. qdf_nbuf_t nbuf_copy = NULL;
  1749. struct dp_tx_msdu_info_s msdu_info;
  1750. struct dp_peer *sa_peer = NULL;
  1751. struct dp_ast_entry *ast_entry = NULL;
  1752. struct dp_soc *soc = NULL;
  1753. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1754. #ifdef WDS_VENDOR_EXTENSION
  1755. int is_mcast = 0, is_ucast = 0;
  1756. int num_peers_3addr = 0;
  1757. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1758. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1759. #endif
  1760. vdev = tx_desc->vdev;
  1761. soc = vdev->pdev->soc;
  1762. qdf_assert(vdev);
  1763. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1764. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1765. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1766. "%s Tx reinject path\n", __func__);
  1767. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1768. qdf_nbuf_len(tx_desc->nbuf));
  1769. qdf_spin_lock_bh(&(soc->ast_lock));
  1770. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1771. if (ast_entry)
  1772. sa_peer = ast_entry->peer;
  1773. qdf_spin_unlock_bh(&(soc->ast_lock));
  1774. #ifdef WDS_VENDOR_EXTENSION
  1775. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1776. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1777. } else {
  1778. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1779. }
  1780. is_ucast = !is_mcast;
  1781. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1782. if (peer->bss_peer)
  1783. continue;
  1784. /* Detect wds peers that use 3-addr framing for mcast.
  1785. * if there are any, the bss_peer is used to send the
  1786. * the mcast frame using 3-addr format. all wds enabled
  1787. * peers that use 4-addr framing for mcast frames will
  1788. * be duplicated and sent as 4-addr frames below.
  1789. */
  1790. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1791. num_peers_3addr = 1;
  1792. break;
  1793. }
  1794. }
  1795. #endif
  1796. if (qdf_unlikely(vdev->mesh_vdev)) {
  1797. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1798. } else {
  1799. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1800. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1801. #ifdef WDS_VENDOR_EXTENSION
  1802. /*
  1803. * . if 3-addr STA, then send on BSS Peer
  1804. * . if Peer WDS enabled and accept 4-addr mcast,
  1805. * send mcast on that peer only
  1806. * . if Peer WDS enabled and accept 4-addr ucast,
  1807. * send ucast on that peer only
  1808. */
  1809. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1810. (peer->wds_enabled &&
  1811. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1812. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1813. #else
  1814. ((peer->bss_peer &&
  1815. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1816. peer->nawds_enabled)) {
  1817. #endif
  1818. peer_id = DP_INVALID_PEER;
  1819. if (peer->nawds_enabled) {
  1820. peer_id = peer->peer_ids[0];
  1821. if (sa_peer == peer) {
  1822. QDF_TRACE(
  1823. QDF_MODULE_ID_DP,
  1824. QDF_TRACE_LEVEL_DEBUG,
  1825. " %s: multicast packet",
  1826. __func__);
  1827. DP_STATS_INC(peer,
  1828. tx.nawds_mcast_drop, 1);
  1829. continue;
  1830. }
  1831. }
  1832. nbuf_copy = qdf_nbuf_copy(nbuf);
  1833. if (!nbuf_copy) {
  1834. QDF_TRACE(QDF_MODULE_ID_DP,
  1835. QDF_TRACE_LEVEL_DEBUG,
  1836. FL("nbuf copy failed"));
  1837. break;
  1838. }
  1839. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1840. nbuf_copy,
  1841. &msdu_info,
  1842. peer_id,
  1843. NULL);
  1844. if (nbuf_copy) {
  1845. QDF_TRACE(QDF_MODULE_ID_DP,
  1846. QDF_TRACE_LEVEL_DEBUG,
  1847. FL("pkt send failed"));
  1848. qdf_nbuf_free(nbuf_copy);
  1849. } else {
  1850. if (peer_id != DP_INVALID_PEER)
  1851. DP_STATS_INC_PKT(peer,
  1852. tx.nawds_mcast,
  1853. 1, qdf_nbuf_len(nbuf));
  1854. }
  1855. }
  1856. }
  1857. }
  1858. if (vdev->nawds_enabled) {
  1859. peer_id = DP_INVALID_PEER;
  1860. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1861. 1, qdf_nbuf_len(nbuf));
  1862. nbuf = dp_tx_send_msdu_single(vdev,
  1863. nbuf,
  1864. &msdu_info,
  1865. peer_id, NULL);
  1866. if (nbuf) {
  1867. QDF_TRACE(QDF_MODULE_ID_DP,
  1868. QDF_TRACE_LEVEL_DEBUG,
  1869. FL("pkt send failed"));
  1870. qdf_nbuf_free(nbuf);
  1871. }
  1872. } else
  1873. qdf_nbuf_free(nbuf);
  1874. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1875. }
  1876. /**
  1877. * dp_tx_inspect_handler() - Tx Inspect Handler
  1878. * @tx_desc: software descriptor head pointer
  1879. * @status : Tx completion status from HTT descriptor
  1880. *
  1881. * Handles Tx frames sent back to Host for inspection
  1882. * (ProxyARP)
  1883. *
  1884. * Return: none
  1885. */
  1886. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1887. {
  1888. struct dp_soc *soc;
  1889. struct dp_pdev *pdev = tx_desc->pdev;
  1890. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1891. "%s Tx inspect path\n",
  1892. __func__);
  1893. qdf_assert(pdev);
  1894. soc = pdev->soc;
  1895. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1896. qdf_nbuf_len(tx_desc->nbuf));
  1897. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1898. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1899. }
  1900. #ifdef FEATURE_PERPKT_INFO
  1901. /**
  1902. * dp_get_completion_indication_for_stack() - send completion to stack
  1903. * @soc : dp_soc handle
  1904. * @pdev: dp_pdev handle
  1905. * @peer_id: peer_id of the peer for which completion came
  1906. * @ppdu_id: ppdu_id
  1907. * @first_msdu: first msdu
  1908. * @last_msdu: last msdu
  1909. * @netbuf: Buffer pointer for free
  1910. *
  1911. * This function is used for indication whether buffer needs to be
  1912. * send to stack for free or not
  1913. */
  1914. QDF_STATUS
  1915. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1916. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1917. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1918. {
  1919. struct tx_capture_hdr *ppdu_hdr;
  1920. struct dp_peer *peer = NULL;
  1921. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1922. return QDF_STATUS_E_NOSUPPORT;
  1923. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1924. dp_peer_find_by_id(soc, peer_id);
  1925. if (!peer) {
  1926. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1927. FL("Peer Invalid"));
  1928. return QDF_STATUS_E_INVAL;
  1929. }
  1930. if (pdev->mcopy_mode) {
  1931. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  1932. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  1933. return QDF_STATUS_E_INVAL;
  1934. }
  1935. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  1936. pdev->m_copy_id.tx_peer_id = peer_id;
  1937. }
  1938. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1939. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1940. FL("No headroom"));
  1941. return QDF_STATUS_E_NOMEM;
  1942. }
  1943. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1944. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1945. IEEE80211_ADDR_LEN);
  1946. ppdu_hdr->ppdu_id = ppdu_id;
  1947. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1948. IEEE80211_ADDR_LEN);
  1949. ppdu_hdr->peer_id = peer_id;
  1950. ppdu_hdr->first_msdu = first_msdu;
  1951. ppdu_hdr->last_msdu = last_msdu;
  1952. return QDF_STATUS_SUCCESS;
  1953. }
  1954. /**
  1955. * dp_send_completion_to_stack() - send completion to stack
  1956. * @soc : dp_soc handle
  1957. * @pdev: dp_pdev handle
  1958. * @peer_id: peer_id of the peer for which completion came
  1959. * @ppdu_id: ppdu_id
  1960. * @netbuf: Buffer pointer for free
  1961. *
  1962. * This function is used to send completion to stack
  1963. * to free buffer
  1964. */
  1965. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1966. uint16_t peer_id, uint32_t ppdu_id,
  1967. qdf_nbuf_t netbuf)
  1968. {
  1969. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1970. netbuf, peer_id,
  1971. WDI_NO_VAL, pdev->pdev_id);
  1972. }
  1973. #else
  1974. static QDF_STATUS
  1975. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1976. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1977. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1978. {
  1979. return QDF_STATUS_E_NOSUPPORT;
  1980. }
  1981. static void
  1982. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1983. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1984. {
  1985. }
  1986. #endif
  1987. /**
  1988. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1989. * @soc: Soc handle
  1990. * @desc: software Tx descriptor to be processed
  1991. *
  1992. * Return: none
  1993. */
  1994. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1995. struct dp_tx_desc_s *desc)
  1996. {
  1997. struct dp_vdev *vdev = desc->vdev;
  1998. qdf_nbuf_t nbuf = desc->nbuf;
  1999. /* If it is TDLS mgmt, don't unmap or free the frame */
  2000. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2001. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2002. /* 0 : MSDU buffer, 1 : MLE */
  2003. if (desc->msdu_ext_desc) {
  2004. /* TSO free */
  2005. if (hal_tx_ext_desc_get_tso_enable(
  2006. desc->msdu_ext_desc->vaddr)) {
  2007. /* If remaining number of segment is 0
  2008. * actual TSO may unmap and free */
  2009. if (qdf_nbuf_get_users(nbuf) == 1)
  2010. __qdf_nbuf_unmap_single(soc->osdev,
  2011. nbuf,
  2012. QDF_DMA_TO_DEVICE);
  2013. qdf_nbuf_free(nbuf);
  2014. return;
  2015. }
  2016. }
  2017. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2018. if (qdf_likely(!vdev->mesh_vdev))
  2019. qdf_nbuf_free(nbuf);
  2020. else {
  2021. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2022. qdf_nbuf_free(nbuf);
  2023. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2024. } else
  2025. vdev->osif_tx_free_ext((nbuf));
  2026. }
  2027. }
  2028. /**
  2029. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2030. * @vdev: pointer to dp dev handler
  2031. * @status : Tx completion status from HTT descriptor
  2032. *
  2033. * Handles MEC notify event sent from fw to Host
  2034. *
  2035. * Return: none
  2036. */
  2037. #ifdef FEATURE_WDS
  2038. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2039. {
  2040. struct dp_soc *soc;
  2041. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2042. struct dp_peer *peer;
  2043. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2044. if (!vdev->wds_enabled)
  2045. return;
  2046. soc = vdev->pdev->soc;
  2047. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2048. peer = TAILQ_FIRST(&vdev->peer_list);
  2049. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2050. if (!peer) {
  2051. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2052. FL("peer is NULL"));
  2053. return;
  2054. }
  2055. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2056. "%s Tx MEC Handler\n",
  2057. __func__);
  2058. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2059. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2060. status[(DP_MAC_ADDR_LEN - 2) + i];
  2061. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2062. dp_peer_add_ast(soc,
  2063. peer,
  2064. mac_addr,
  2065. CDP_TXRX_AST_TYPE_MEC,
  2066. flags);
  2067. }
  2068. #endif
  2069. /**
  2070. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2071. * @tx_desc: software descriptor head pointer
  2072. * @status : Tx completion status from HTT descriptor
  2073. *
  2074. * This function will process HTT Tx indication messages from Target
  2075. *
  2076. * Return: none
  2077. */
  2078. static
  2079. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2080. {
  2081. uint8_t tx_status;
  2082. struct dp_pdev *pdev;
  2083. struct dp_vdev *vdev;
  2084. struct dp_soc *soc;
  2085. uint32_t *htt_status_word = (uint32_t *) status;
  2086. qdf_assert(tx_desc->pdev);
  2087. pdev = tx_desc->pdev;
  2088. vdev = tx_desc->vdev;
  2089. soc = pdev->soc;
  2090. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2091. switch (tx_status) {
  2092. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2093. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2094. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2095. {
  2096. dp_tx_comp_free_buf(soc, tx_desc);
  2097. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2098. break;
  2099. }
  2100. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2101. {
  2102. dp_tx_reinject_handler(tx_desc, status);
  2103. break;
  2104. }
  2105. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2106. {
  2107. dp_tx_inspect_handler(tx_desc, status);
  2108. break;
  2109. }
  2110. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2111. {
  2112. dp_tx_mec_handler(vdev, status);
  2113. break;
  2114. }
  2115. default:
  2116. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2117. "%s Invalid HTT tx_status %d\n",
  2118. __func__, tx_status);
  2119. break;
  2120. }
  2121. }
  2122. #ifdef MESH_MODE_SUPPORT
  2123. /**
  2124. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2125. * in mesh meta header
  2126. * @tx_desc: software descriptor head pointer
  2127. * @ts: pointer to tx completion stats
  2128. * Return: none
  2129. */
  2130. static
  2131. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2132. struct hal_tx_completion_status *ts)
  2133. {
  2134. struct meta_hdr_s *mhdr;
  2135. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2136. if (!tx_desc->msdu_ext_desc) {
  2137. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2138. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2139. "netbuf %pK offset %d\n",
  2140. netbuf, tx_desc->pkt_offset);
  2141. return;
  2142. }
  2143. }
  2144. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2145. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2146. "netbuf %pK offset %d\n", netbuf,
  2147. sizeof(struct meta_hdr_s));
  2148. return;
  2149. }
  2150. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2151. mhdr->rssi = ts->ack_frame_rssi;
  2152. mhdr->channel = tx_desc->pdev->operating_channel;
  2153. }
  2154. #else
  2155. static
  2156. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2157. struct hal_tx_completion_status *ts)
  2158. {
  2159. }
  2160. #endif
  2161. /**
  2162. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2163. * @peer: Handle to DP peer
  2164. * @ts: pointer to HAL Tx completion stats
  2165. * @length: MSDU length
  2166. *
  2167. * Return: None
  2168. */
  2169. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2170. struct hal_tx_completion_status *ts, uint32_t length)
  2171. {
  2172. struct dp_pdev *pdev = peer->vdev->pdev;
  2173. struct dp_soc *soc = pdev->soc;
  2174. uint8_t mcs, pkt_type;
  2175. mcs = ts->mcs;
  2176. pkt_type = ts->pkt_type;
  2177. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2178. return;
  2179. if (peer->bss_peer) {
  2180. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2181. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2182. } else {
  2183. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  2184. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2185. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2186. }
  2187. }
  2188. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2189. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2190. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2191. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2192. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2193. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2194. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2195. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2196. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2197. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2198. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2199. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2200. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2201. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2202. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2203. return;
  2204. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2205. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2206. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2207. if (!(soc->process_tx_status))
  2208. return;
  2209. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2210. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2211. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2212. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2213. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2214. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2215. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2216. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2217. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2218. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2219. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2220. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2221. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2222. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2223. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2224. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2225. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2226. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2227. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2228. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2229. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2230. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2231. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2232. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2233. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2234. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2235. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2236. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2237. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2238. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  2239. &peer->stats, ts->peer_id,
  2240. UPDATE_PEER_STATS);
  2241. }
  2242. }
  2243. /**
  2244. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2245. * @tx_desc: software descriptor head pointer
  2246. * @length: packet length
  2247. *
  2248. * Return: none
  2249. */
  2250. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2251. uint32_t length)
  2252. {
  2253. struct hal_tx_completion_status ts;
  2254. struct dp_soc *soc = NULL;
  2255. struct dp_vdev *vdev = tx_desc->vdev;
  2256. struct dp_peer *peer = NULL;
  2257. struct ether_header *eh =
  2258. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2259. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2260. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2261. "-------------------- \n"
  2262. "Tx Completion Stats: \n"
  2263. "-------------------- \n"
  2264. "ack_frame_rssi = %d \n"
  2265. "first_msdu = %d \n"
  2266. "last_msdu = %d \n"
  2267. "msdu_part_of_amsdu = %d \n"
  2268. "rate_stats valid = %d \n"
  2269. "bw = %d \n"
  2270. "pkt_type = %d \n"
  2271. "stbc = %d \n"
  2272. "ldpc = %d \n"
  2273. "sgi = %d \n"
  2274. "mcs = %d \n"
  2275. "ofdma = %d \n"
  2276. "tones_in_ru = %d \n"
  2277. "tsf = %d \n"
  2278. "ppdu_id = %d \n"
  2279. "transmit_cnt = %d \n"
  2280. "tid = %d \n"
  2281. "peer_id = %d \n",
  2282. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2283. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2284. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2285. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2286. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2287. ts.peer_id);
  2288. if (!vdev) {
  2289. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2290. "invalid vdev");
  2291. goto out;
  2292. }
  2293. soc = vdev->pdev->soc;
  2294. /* Update SoC level stats */
  2295. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2296. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2297. /* Update per-packet stats */
  2298. if (qdf_unlikely(vdev->mesh_vdev) &&
  2299. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2300. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2301. /* Update peer level stats */
  2302. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2303. if (!peer) {
  2304. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2305. "invalid peer");
  2306. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2307. goto out;
  2308. }
  2309. if (qdf_likely(peer->vdev->tx_encap_type ==
  2310. htt_cmn_pkt_type_ethernet)) {
  2311. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2312. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2313. }
  2314. dp_tx_update_peer_stats(peer, &ts, length);
  2315. out:
  2316. return;
  2317. }
  2318. /**
  2319. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2320. * @soc: core txrx main context
  2321. * @comp_head: software descriptor head pointer
  2322. *
  2323. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2324. * and release the software descriptors after processing is complete
  2325. *
  2326. * Return: none
  2327. */
  2328. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2329. struct dp_tx_desc_s *comp_head)
  2330. {
  2331. struct dp_tx_desc_s *desc;
  2332. struct dp_tx_desc_s *next;
  2333. struct hal_tx_completion_status ts = {0};
  2334. uint32_t length;
  2335. struct dp_peer *peer;
  2336. DP_HIST_INIT();
  2337. desc = comp_head;
  2338. while (desc) {
  2339. hal_tx_comp_get_status(&desc->comp, &ts);
  2340. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2341. length = qdf_nbuf_len(desc->nbuf);
  2342. dp_tx_comp_process_tx_status(desc, length);
  2343. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2344. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2345. desc->pdev, ts.peer_id, ts.ppdu_id,
  2346. ts.first_msdu, ts.last_msdu,
  2347. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2348. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2349. QDF_DMA_TO_DEVICE);
  2350. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2351. ts.ppdu_id, desc->nbuf);
  2352. } else {
  2353. dp_tx_comp_free_buf(soc, desc);
  2354. }
  2355. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2356. next = desc->next;
  2357. dp_tx_desc_release(desc, desc->pool_id);
  2358. desc = next;
  2359. }
  2360. DP_TX_HIST_STATS_PER_PDEV();
  2361. }
  2362. /**
  2363. * dp_tx_comp_handler() - Tx completion handler
  2364. * @soc: core txrx main context
  2365. * @ring_id: completion ring id
  2366. * @quota: No. of packets/descriptors that can be serviced in one loop
  2367. *
  2368. * This function will collect hardware release ring element contents and
  2369. * handle descriptor contents. Based on contents, free packet or handle error
  2370. * conditions
  2371. *
  2372. * Return: none
  2373. */
  2374. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2375. {
  2376. void *tx_comp_hal_desc;
  2377. uint8_t buffer_src;
  2378. uint8_t pool_id;
  2379. uint32_t tx_desc_id;
  2380. struct dp_tx_desc_s *tx_desc = NULL;
  2381. struct dp_tx_desc_s *head_desc = NULL;
  2382. struct dp_tx_desc_s *tail_desc = NULL;
  2383. uint32_t num_processed;
  2384. uint32_t count;
  2385. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2386. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2387. "%s %d : HAL RING Access Failed -- %pK\n",
  2388. __func__, __LINE__, hal_srng);
  2389. return 0;
  2390. }
  2391. num_processed = 0;
  2392. count = 0;
  2393. /* Find head descriptor from completion ring */
  2394. while (qdf_likely(tx_comp_hal_desc =
  2395. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2396. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2397. /* If this buffer was not released by TQM or FW, then it is not
  2398. * Tx completion indication, assert */
  2399. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2400. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2401. QDF_TRACE(QDF_MODULE_ID_DP,
  2402. QDF_TRACE_LEVEL_FATAL,
  2403. "Tx comp release_src != TQM | FW");
  2404. qdf_assert_always(0);
  2405. }
  2406. /* Get descriptor id */
  2407. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2408. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2409. DP_TX_DESC_ID_POOL_OS;
  2410. /* Pool ID is out of limit. Error */
  2411. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  2412. soc->wlan_cfg_ctx)) {
  2413. QDF_TRACE(QDF_MODULE_ID_DP,
  2414. QDF_TRACE_LEVEL_FATAL,
  2415. "Tx Comp pool id %d not valid",
  2416. pool_id);
  2417. qdf_assert_always(0);
  2418. }
  2419. /* Find Tx descriptor */
  2420. tx_desc = dp_tx_desc_find(soc, pool_id,
  2421. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2422. DP_TX_DESC_ID_PAGE_OS,
  2423. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2424. DP_TX_DESC_ID_OFFSET_OS);
  2425. /*
  2426. * If the release source is FW, process the HTT status
  2427. */
  2428. if (qdf_unlikely(buffer_src ==
  2429. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2430. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2431. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2432. htt_tx_status);
  2433. dp_tx_process_htt_completion(tx_desc,
  2434. htt_tx_status);
  2435. } else {
  2436. /* Pool id is not matching. Error */
  2437. if (tx_desc->pool_id != pool_id) {
  2438. QDF_TRACE(QDF_MODULE_ID_DP,
  2439. QDF_TRACE_LEVEL_FATAL,
  2440. "Tx Comp pool id %d not matched %d",
  2441. pool_id, tx_desc->pool_id);
  2442. qdf_assert_always(0);
  2443. }
  2444. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2445. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2446. QDF_TRACE(QDF_MODULE_ID_DP,
  2447. QDF_TRACE_LEVEL_FATAL,
  2448. "Txdesc invalid, flgs = %x,id = %d",
  2449. tx_desc->flags, tx_desc_id);
  2450. qdf_assert_always(0);
  2451. }
  2452. /* First ring descriptor on the cycle */
  2453. if (!head_desc) {
  2454. head_desc = tx_desc;
  2455. tail_desc = tx_desc;
  2456. }
  2457. tail_desc->next = tx_desc;
  2458. tx_desc->next = NULL;
  2459. tail_desc = tx_desc;
  2460. /* Collect hw completion contents */
  2461. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2462. &tx_desc->comp, 1);
  2463. }
  2464. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2465. /* Decrement PM usage count if the packet has been sent.*/
  2466. hif_pm_runtime_put(soc->hif_handle);
  2467. /*
  2468. * Processed packet count is more than given quota
  2469. * stop to processing
  2470. */
  2471. if ((num_processed >= quota))
  2472. break;
  2473. count++;
  2474. }
  2475. hal_srng_access_end(soc->hal_soc, hal_srng);
  2476. /* Process the reaped descriptors */
  2477. if (head_desc)
  2478. dp_tx_comp_process_desc(soc, head_desc);
  2479. return num_processed;
  2480. }
  2481. #ifdef CONVERGED_TDLS_ENABLE
  2482. /**
  2483. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2484. *
  2485. * @data_vdev - which vdev should transmit the tx data frames
  2486. * @tx_spec - what non-standard handling to apply to the tx data frames
  2487. * @msdu_list - NULL-terminated list of tx MSDUs
  2488. *
  2489. * Return: NULL on success,
  2490. * nbuf when it fails to send
  2491. */
  2492. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2493. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2494. {
  2495. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2496. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2497. vdev->is_tdls_frame = true;
  2498. return dp_tx_send(vdev_handle, msdu_list);
  2499. }
  2500. #endif
  2501. /**
  2502. * dp_tx_vdev_attach() - attach vdev to dp tx
  2503. * @vdev: virtual device instance
  2504. *
  2505. * Return: QDF_STATUS_SUCCESS: success
  2506. * QDF_STATUS_E_RESOURCES: Error return
  2507. */
  2508. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2509. {
  2510. /*
  2511. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2512. */
  2513. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2514. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2515. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2516. vdev->vdev_id);
  2517. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2518. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2519. /*
  2520. * Set HTT Extension Valid bit to 0 by default
  2521. */
  2522. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2523. dp_tx_vdev_update_search_flags(vdev);
  2524. return QDF_STATUS_SUCCESS;
  2525. }
  2526. /**
  2527. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2528. * @vdev: virtual device instance
  2529. *
  2530. * Return: void
  2531. *
  2532. */
  2533. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2534. {
  2535. /*
  2536. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2537. * for TDLS link
  2538. *
  2539. * Enable AddrY (SA based search) only for non-WDS STA and
  2540. * ProxySTA VAP modes.
  2541. *
  2542. * In all other VAP modes, only DA based search should be
  2543. * enabled
  2544. */
  2545. if (vdev->opmode == wlan_op_mode_sta &&
  2546. vdev->tdls_link_connected)
  2547. vdev->hal_desc_addr_search_flags =
  2548. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2549. else if ((vdev->opmode == wlan_op_mode_sta &&
  2550. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2551. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2552. else
  2553. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2554. }
  2555. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2556. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2557. {
  2558. }
  2559. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2560. /* dp_tx_desc_flush() - release resources associated
  2561. * to tx_desc
  2562. * @vdev: virtual device instance
  2563. *
  2564. * This function will free all outstanding Tx buffers,
  2565. * including ME buffer for which either free during
  2566. * completion didn't happened or completion is not
  2567. * received.
  2568. */
  2569. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2570. {
  2571. uint8_t i, num_pool;
  2572. uint32_t j;
  2573. uint32_t num_desc;
  2574. struct dp_soc *soc = vdev->pdev->soc;
  2575. struct dp_tx_desc_s *tx_desc = NULL;
  2576. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2577. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2578. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2579. for (i = 0; i < num_pool; i++) {
  2580. for (j = 0; j < num_desc; j++) {
  2581. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2582. if (tx_desc_pool &&
  2583. tx_desc_pool->desc_pages.cacheable_pages) {
  2584. tx_desc = dp_tx_desc_find(soc, i,
  2585. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2586. DP_TX_DESC_ID_PAGE_OS,
  2587. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2588. DP_TX_DESC_ID_OFFSET_OS);
  2589. if (tx_desc && (tx_desc->vdev == vdev) &&
  2590. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2591. dp_tx_comp_free_buf(soc, tx_desc);
  2592. dp_tx_desc_release(tx_desc, i);
  2593. }
  2594. }
  2595. }
  2596. }
  2597. }
  2598. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2599. /**
  2600. * dp_tx_vdev_detach() - detach vdev from dp tx
  2601. * @vdev: virtual device instance
  2602. *
  2603. * Return: QDF_STATUS_SUCCESS: success
  2604. * QDF_STATUS_E_RESOURCES: Error return
  2605. */
  2606. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2607. {
  2608. dp_tx_desc_flush(vdev);
  2609. return QDF_STATUS_SUCCESS;
  2610. }
  2611. /**
  2612. * dp_tx_pdev_attach() - attach pdev to dp tx
  2613. * @pdev: physical device instance
  2614. *
  2615. * Return: QDF_STATUS_SUCCESS: success
  2616. * QDF_STATUS_E_RESOURCES: Error return
  2617. */
  2618. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2619. {
  2620. struct dp_soc *soc = pdev->soc;
  2621. /* Initialize Flow control counters */
  2622. qdf_atomic_init(&pdev->num_tx_exception);
  2623. qdf_atomic_init(&pdev->num_tx_outstanding);
  2624. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2625. /* Initialize descriptors in TCL Ring */
  2626. hal_tx_init_data_ring(soc->hal_soc,
  2627. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2628. }
  2629. return QDF_STATUS_SUCCESS;
  2630. }
  2631. /**
  2632. * dp_tx_pdev_detach() - detach pdev from dp tx
  2633. * @pdev: physical device instance
  2634. *
  2635. * Return: QDF_STATUS_SUCCESS: success
  2636. * QDF_STATUS_E_RESOURCES: Error return
  2637. */
  2638. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2639. {
  2640. dp_tx_me_exit(pdev);
  2641. return QDF_STATUS_SUCCESS;
  2642. }
  2643. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2644. /* Pools will be allocated dynamically */
  2645. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2646. int num_desc)
  2647. {
  2648. uint8_t i;
  2649. for (i = 0; i < num_pool; i++) {
  2650. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2651. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2652. }
  2653. return 0;
  2654. }
  2655. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2656. {
  2657. uint8_t i;
  2658. for (i = 0; i < num_pool; i++)
  2659. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2660. }
  2661. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2662. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2663. int num_desc)
  2664. {
  2665. uint8_t i;
  2666. /* Allocate software Tx descriptor pools */
  2667. for (i = 0; i < num_pool; i++) {
  2668. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2669. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2670. "%s Tx Desc Pool alloc %d failed %pK\n",
  2671. __func__, i, soc);
  2672. return ENOMEM;
  2673. }
  2674. }
  2675. return 0;
  2676. }
  2677. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2678. {
  2679. uint8_t i;
  2680. for (i = 0; i < num_pool; i++) {
  2681. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2682. if (dp_tx_desc_pool_free(soc, i)) {
  2683. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2684. "%s Tx Desc Pool Free failed\n", __func__);
  2685. }
  2686. }
  2687. }
  2688. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2689. /**
  2690. * dp_tx_soc_detach() - detach soc from dp tx
  2691. * @soc: core txrx main context
  2692. *
  2693. * This function will detach dp tx into main device context
  2694. * will free dp tx resource and initialize resources
  2695. *
  2696. * Return: QDF_STATUS_SUCCESS: success
  2697. * QDF_STATUS_E_RESOURCES: Error return
  2698. */
  2699. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2700. {
  2701. uint8_t num_pool;
  2702. uint16_t num_desc;
  2703. uint16_t num_ext_desc;
  2704. uint8_t i;
  2705. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2706. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2707. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2708. dp_tx_flow_control_deinit(soc);
  2709. dp_tx_delete_static_pools(soc, num_pool);
  2710. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2711. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2712. __func__, num_pool, num_desc);
  2713. for (i = 0; i < num_pool; i++) {
  2714. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2715. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2716. "%s Tx Ext Desc Pool Free failed\n",
  2717. __func__);
  2718. return QDF_STATUS_E_RESOURCES;
  2719. }
  2720. }
  2721. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2722. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2723. __func__, num_pool, num_ext_desc);
  2724. for (i = 0; i < num_pool; i++) {
  2725. dp_tx_tso_desc_pool_free(soc, i);
  2726. }
  2727. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2728. "%s TSO Desc Pool %d Free descs = %d\n",
  2729. __func__, num_pool, num_desc);
  2730. for (i = 0; i < num_pool; i++)
  2731. dp_tx_tso_num_seg_pool_free(soc, i);
  2732. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2733. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2734. __func__, num_pool, num_desc);
  2735. return QDF_STATUS_SUCCESS;
  2736. }
  2737. /**
  2738. * dp_tx_soc_attach() - attach soc to dp tx
  2739. * @soc: core txrx main context
  2740. *
  2741. * This function will attach dp tx into main device context
  2742. * will allocate dp tx resource and initialize resources
  2743. *
  2744. * Return: QDF_STATUS_SUCCESS: success
  2745. * QDF_STATUS_E_RESOURCES: Error return
  2746. */
  2747. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2748. {
  2749. uint8_t i;
  2750. uint8_t num_pool;
  2751. uint32_t num_desc;
  2752. uint32_t num_ext_desc;
  2753. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2754. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2755. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2756. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2757. goto fail;
  2758. dp_tx_flow_control_init(soc);
  2759. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2760. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2761. __func__, num_pool, num_desc);
  2762. /* Allocate extension tx descriptor pools */
  2763. for (i = 0; i < num_pool; i++) {
  2764. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2765. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2766. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2767. i, soc);
  2768. goto fail;
  2769. }
  2770. }
  2771. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2772. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2773. __func__, num_pool, num_ext_desc);
  2774. for (i = 0; i < num_pool; i++) {
  2775. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2776. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2777. "TSO Desc Pool alloc %d failed %pK\n",
  2778. i, soc);
  2779. goto fail;
  2780. }
  2781. }
  2782. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2783. "%s TSO Desc Alloc %d, descs = %d\n",
  2784. __func__, num_pool, num_desc);
  2785. for (i = 0; i < num_pool; i++) {
  2786. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2787. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2788. "TSO Num of seg Pool alloc %d failed %pK\n",
  2789. i, soc);
  2790. goto fail;
  2791. }
  2792. }
  2793. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2794. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2795. __func__, num_pool, num_desc);
  2796. /* Initialize descriptors in TCL Rings */
  2797. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2798. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2799. hal_tx_init_data_ring(soc->hal_soc,
  2800. soc->tcl_data_ring[i].hal_srng);
  2801. }
  2802. }
  2803. /*
  2804. * todo - Add a runtime config option to enable this.
  2805. */
  2806. /*
  2807. * Due to multiple issues on NPR EMU, enable it selectively
  2808. * only for NPR EMU, should be removed, once NPR platforms
  2809. * are stable.
  2810. */
  2811. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2812. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2813. "%s HAL Tx init Success\n", __func__);
  2814. return QDF_STATUS_SUCCESS;
  2815. fail:
  2816. /* Detach will take care of freeing only allocated resources */
  2817. dp_tx_soc_detach(soc);
  2818. return QDF_STATUS_E_RESOURCES;
  2819. }
  2820. /*
  2821. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2822. * pdev: pointer to DP PDEV structure
  2823. * seg_info_head: Pointer to the head of list
  2824. *
  2825. * return: void
  2826. */
  2827. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2828. struct dp_tx_seg_info_s *seg_info_head)
  2829. {
  2830. struct dp_tx_me_buf_t *mc_uc_buf;
  2831. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2832. qdf_nbuf_t nbuf = NULL;
  2833. uint64_t phy_addr;
  2834. while (seg_info_head) {
  2835. nbuf = seg_info_head->nbuf;
  2836. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2837. seg_info_head->frags[0].vaddr;
  2838. phy_addr = seg_info_head->frags[0].paddr_hi;
  2839. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2840. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2841. phy_addr,
  2842. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2843. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2844. qdf_nbuf_free(nbuf);
  2845. seg_info_new = seg_info_head;
  2846. seg_info_head = seg_info_head->next;
  2847. qdf_mem_free(seg_info_new);
  2848. }
  2849. }
  2850. /**
  2851. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2852. * @vdev: DP VDEV handle
  2853. * @nbuf: Multicast nbuf
  2854. * @newmac: Table of the clients to which packets have to be sent
  2855. * @new_mac_cnt: No of clients
  2856. *
  2857. * return: no of converted packets
  2858. */
  2859. uint16_t
  2860. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2861. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2862. {
  2863. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2864. struct dp_pdev *pdev = vdev->pdev;
  2865. struct ether_header *eh;
  2866. uint8_t *data;
  2867. uint16_t len;
  2868. /* reference to frame dst addr */
  2869. uint8_t *dstmac;
  2870. /* copy of original frame src addr */
  2871. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2872. /* local index into newmac */
  2873. uint8_t new_mac_idx = 0;
  2874. struct dp_tx_me_buf_t *mc_uc_buf;
  2875. qdf_nbuf_t nbuf_clone;
  2876. struct dp_tx_msdu_info_s msdu_info;
  2877. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2878. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2879. struct dp_tx_seg_info_s *seg_info_new;
  2880. struct dp_tx_frag_info_s data_frag;
  2881. qdf_dma_addr_t paddr_data;
  2882. qdf_dma_addr_t paddr_mcbuf = 0;
  2883. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2884. QDF_STATUS status;
  2885. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2886. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2887. eh = (struct ether_header *) nbuf;
  2888. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2889. len = qdf_nbuf_len(nbuf);
  2890. data = qdf_nbuf_data(nbuf);
  2891. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2892. QDF_DMA_TO_DEVICE);
  2893. if (status) {
  2894. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2895. "Mapping failure Error:%d", status);
  2896. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2897. qdf_nbuf_free(nbuf);
  2898. return 1;
  2899. }
  2900. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2901. /*preparing data fragment*/
  2902. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2903. data_frag.paddr_lo = (uint32_t)paddr_data;
  2904. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2905. data_frag.len = len - DP_MAC_ADDR_LEN;
  2906. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2907. dstmac = newmac[new_mac_idx];
  2908. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2909. "added mac addr (%pM)", dstmac);
  2910. /* Check for NULL Mac Address */
  2911. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2912. continue;
  2913. /* frame to self mac. skip */
  2914. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2915. continue;
  2916. /*
  2917. * TODO: optimize to avoid malloc in per-packet path
  2918. * For eg. seg_pool can be made part of vdev structure
  2919. */
  2920. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2921. if (!seg_info_new) {
  2922. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2923. "alloc failed");
  2924. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2925. goto fail_seg_alloc;
  2926. }
  2927. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2928. if (mc_uc_buf == NULL)
  2929. goto fail_buf_alloc;
  2930. /*
  2931. * TODO: Check if we need to clone the nbuf
  2932. * Or can we just use the reference for all cases
  2933. */
  2934. if (new_mac_idx < (new_mac_cnt - 1)) {
  2935. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2936. if (nbuf_clone == NULL) {
  2937. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2938. goto fail_clone;
  2939. }
  2940. } else {
  2941. /*
  2942. * Update the ref
  2943. * to account for frame sent without cloning
  2944. */
  2945. qdf_nbuf_ref(nbuf);
  2946. nbuf_clone = nbuf;
  2947. }
  2948. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2949. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2950. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2951. &paddr_mcbuf);
  2952. if (status) {
  2953. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2954. "Mapping failure Error:%d", status);
  2955. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2956. goto fail_map;
  2957. }
  2958. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2959. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2960. seg_info_new->frags[0].paddr_hi =
  2961. ((uint64_t) paddr_mcbuf >> 32);
  2962. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2963. seg_info_new->frags[1] = data_frag;
  2964. seg_info_new->nbuf = nbuf_clone;
  2965. seg_info_new->frag_cnt = 2;
  2966. seg_info_new->total_len = len;
  2967. seg_info_new->next = NULL;
  2968. if (seg_info_head == NULL)
  2969. seg_info_head = seg_info_new;
  2970. else
  2971. seg_info_tail->next = seg_info_new;
  2972. seg_info_tail = seg_info_new;
  2973. }
  2974. if (!seg_info_head) {
  2975. goto free_return;
  2976. }
  2977. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2978. msdu_info.num_seg = new_mac_cnt;
  2979. msdu_info.frm_type = dp_tx_frm_me;
  2980. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2981. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2982. while (seg_info_head->next) {
  2983. seg_info_new = seg_info_head;
  2984. seg_info_head = seg_info_head->next;
  2985. qdf_mem_free(seg_info_new);
  2986. }
  2987. qdf_mem_free(seg_info_head);
  2988. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2989. qdf_nbuf_free(nbuf);
  2990. return new_mac_cnt;
  2991. fail_map:
  2992. qdf_nbuf_free(nbuf_clone);
  2993. fail_clone:
  2994. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2995. fail_buf_alloc:
  2996. qdf_mem_free(seg_info_new);
  2997. fail_seg_alloc:
  2998. dp_tx_me_mem_free(pdev, seg_info_head);
  2999. free_return:
  3000. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3001. qdf_nbuf_free(nbuf);
  3002. return 1;
  3003. }