dsi_display.c 213 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/list.h>
  6. #include <linux/of.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/err.h>
  9. #include "msm_drv.h"
  10. #include "sde_connector.h"
  11. #include "msm_mmu.h"
  12. #include "dsi_display.h"
  13. #include "dsi_panel.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_drm.h"
  17. #include "dsi_clk.h"
  18. #include "dsi_pwr.h"
  19. #include "sde_dbg.h"
  20. #include "dsi_parser.h"
  21. #define to_dsi_display(x) container_of(x, struct dsi_display, host)
  22. #define INT_BASE_10 10
  23. #define MISR_BUFF_SIZE 256
  24. #define ESD_MODE_STRING_MAX_LEN 256
  25. #define ESD_TRIGGER_STRING_MAX_LEN 10
  26. #define MAX_NAME_SIZE 64
  27. #define MAX_TE_RECHECKS 5
  28. #define DSI_CLOCK_BITRATE_RADIX 10
  29. #define MAX_TE_SOURCE_ID 2
  30. #define SEC_PANEL_NAME_MAX_LEN 256
  31. u8 dbgfs_tx_cmd_buf[SZ_4K];
  32. static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN];
  33. static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN];
  34. static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = {
  35. {.boot_param = dsi_display_primary},
  36. {.boot_param = dsi_display_secondary},
  37. };
  38. static void dsi_display_panel_id_notification(struct dsi_display *display);
  39. static const struct of_device_id dsi_display_dt_match[] = {
  40. {.compatible = "qcom,dsi-display"},
  41. {}
  42. };
  43. bool is_skip_op_required(struct dsi_display *display)
  44. {
  45. if (!display)
  46. return false;
  47. return (display->is_cont_splash_enabled || display->trusted_vm_env);
  48. }
  49. static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
  50. u32 mask, bool enable)
  51. {
  52. int i;
  53. struct dsi_display_ctrl *ctrl;
  54. if (!display)
  55. return;
  56. display_for_each_ctrl(i, display) {
  57. ctrl = &display->ctrl[i];
  58. if (!ctrl)
  59. continue;
  60. dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
  61. }
  62. }
  63. static int dsi_display_config_clk_gating(struct dsi_display *display,
  64. bool enable)
  65. {
  66. int rc = 0, i = 0;
  67. struct dsi_display_ctrl *mctrl, *ctrl;
  68. enum dsi_clk_gate_type clk_selection;
  69. enum dsi_clk_gate_type const default_clk_select = PIXEL_CLK | DSI_PHY;
  70. if (!display) {
  71. DSI_ERR("Invalid params\n");
  72. return -EINVAL;
  73. }
  74. if (display->panel->host_config.force_hs_clk_lane) {
  75. DSI_DEBUG("no dsi clock gating for continuous clock mode\n");
  76. return 0;
  77. }
  78. mctrl = &display->ctrl[display->clk_master_idx];
  79. if (!mctrl) {
  80. DSI_ERR("Invalid controller\n");
  81. return -EINVAL;
  82. }
  83. clk_selection = display->clk_gating_config;
  84. if (!enable) {
  85. /* for disable path, make sure to disable all clk gating */
  86. clk_selection = DSI_CLK_ALL;
  87. } else if (!clk_selection || clk_selection > DSI_CLK_NONE) {
  88. /* Default selection, no overrides */
  89. clk_selection = default_clk_select;
  90. } else if (clk_selection == DSI_CLK_NONE) {
  91. clk_selection = 0;
  92. }
  93. DSI_DEBUG("%s clock gating Byte:%s Pixel:%s PHY:%s\n",
  94. enable ? "Enabling" : "Disabling",
  95. clk_selection & BYTE_CLK ? "yes" : "no",
  96. clk_selection & PIXEL_CLK ? "yes" : "no",
  97. clk_selection & DSI_PHY ? "yes" : "no");
  98. rc = dsi_ctrl_config_clk_gating(mctrl->ctrl, enable, clk_selection);
  99. if (rc) {
  100. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  101. display->name, enable ? "enable" : "disable",
  102. clk_selection, rc);
  103. return rc;
  104. }
  105. display_for_each_ctrl(i, display) {
  106. ctrl = &display->ctrl[i];
  107. if (!ctrl->ctrl || (ctrl == mctrl))
  108. continue;
  109. /**
  110. * In Split DSI usecase we should not enable clock gating on
  111. * DSI PHY1 to ensure no display atrifacts are seen.
  112. */
  113. clk_selection &= ~DSI_PHY;
  114. rc = dsi_ctrl_config_clk_gating(ctrl->ctrl, enable,
  115. clk_selection);
  116. if (rc) {
  117. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  118. display->name, enable ? "enable" : "disable",
  119. clk_selection, rc);
  120. return rc;
  121. }
  122. }
  123. return 0;
  124. }
  125. static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
  126. bool enable)
  127. {
  128. int i;
  129. struct dsi_display_ctrl *ctrl;
  130. if (!display)
  131. return;
  132. display_for_each_ctrl(i, display) {
  133. ctrl = &display->ctrl[i];
  134. if (!ctrl)
  135. continue;
  136. ctrl->ctrl->esd_check_underway = enable;
  137. }
  138. }
  139. static void dsi_display_ctrl_irq_update(struct dsi_display *display, bool en)
  140. {
  141. int i;
  142. struct dsi_display_ctrl *ctrl;
  143. if (!display)
  144. return;
  145. display_for_each_ctrl(i, display) {
  146. ctrl = &display->ctrl[i];
  147. if (!ctrl)
  148. continue;
  149. dsi_ctrl_irq_update(ctrl->ctrl, en);
  150. }
  151. }
  152. void dsi_rect_intersect(const struct dsi_rect *r1,
  153. const struct dsi_rect *r2,
  154. struct dsi_rect *result)
  155. {
  156. int l, t, r, b;
  157. if (!r1 || !r2 || !result)
  158. return;
  159. l = max(r1->x, r2->x);
  160. t = max(r1->y, r2->y);
  161. r = min((r1->x + r1->w), (r2->x + r2->w));
  162. b = min((r1->y + r1->h), (r2->y + r2->h));
  163. if (r <= l || b <= t) {
  164. memset(result, 0, sizeof(*result));
  165. } else {
  166. result->x = l;
  167. result->y = t;
  168. result->w = r - l;
  169. result->h = b - t;
  170. }
  171. }
  172. int dsi_display_set_backlight(struct drm_connector *connector,
  173. void *display, u32 bl_lvl)
  174. {
  175. struct dsi_display *dsi_display = display;
  176. struct dsi_panel *panel;
  177. u32 bl_scale, bl_scale_sv;
  178. u64 bl_temp;
  179. int rc = 0;
  180. if (dsi_display == NULL || dsi_display->panel == NULL)
  181. return -EINVAL;
  182. panel = dsi_display->panel;
  183. mutex_lock(&panel->panel_lock);
  184. if (!dsi_panel_initialized(panel)) {
  185. rc = -EINVAL;
  186. goto error;
  187. }
  188. panel->bl_config.bl_level = bl_lvl;
  189. /* scale backlight */
  190. bl_scale = panel->bl_config.bl_scale;
  191. bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL;
  192. bl_scale_sv = panel->bl_config.bl_scale_sv;
  193. bl_temp = (u32)bl_temp * bl_scale_sv / MAX_SV_BL_SCALE_LEVEL;
  194. if (bl_temp > panel->bl_config.bl_max_level)
  195. bl_temp = panel->bl_config.bl_max_level;
  196. DSI_DEBUG("bl_scale = %u, bl_scale_sv = %u, bl_lvl = %u\n",
  197. bl_scale, bl_scale_sv, (u32)bl_temp);
  198. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  199. DSI_CORE_CLK, DSI_CLK_ON);
  200. if (rc) {
  201. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  202. dsi_display->name, rc);
  203. goto error;
  204. }
  205. rc = dsi_panel_set_backlight(panel, (u32)bl_temp);
  206. if (rc)
  207. DSI_ERR("unable to set backlight\n");
  208. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  209. DSI_CORE_CLK, DSI_CLK_OFF);
  210. if (rc) {
  211. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  212. dsi_display->name, rc);
  213. goto error;
  214. }
  215. error:
  216. mutex_unlock(&panel->panel_lock);
  217. return rc;
  218. }
  219. static int dsi_display_cmd_engine_enable(struct dsi_display *display)
  220. {
  221. int rc = 0;
  222. int i;
  223. struct dsi_display_ctrl *m_ctrl, *ctrl;
  224. bool skip_op = is_skip_op_required(display);
  225. m_ctrl = &display->ctrl[display->cmd_master_idx];
  226. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  227. if (display->cmd_engine_refcount > 0) {
  228. display->cmd_engine_refcount++;
  229. goto done;
  230. }
  231. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  232. DSI_CTRL_ENGINE_ON, skip_op);
  233. if (rc) {
  234. DSI_ERR("[%s] enable mcmd engine failed, skip_op:%d rc:%d\n",
  235. display->name, skip_op, rc);
  236. goto done;
  237. }
  238. display_for_each_ctrl(i, display) {
  239. ctrl = &display->ctrl[i];
  240. if (!ctrl->ctrl || (ctrl == m_ctrl))
  241. continue;
  242. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  243. DSI_CTRL_ENGINE_ON, skip_op);
  244. if (rc) {
  245. DSI_ERR(
  246. "[%s] enable cmd engine failed, skip_op:%d rc:%d\n",
  247. display->name, skip_op, rc);
  248. goto error_disable_master;
  249. }
  250. }
  251. display->cmd_engine_refcount++;
  252. goto done;
  253. error_disable_master:
  254. (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  255. DSI_CTRL_ENGINE_OFF, skip_op);
  256. done:
  257. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  258. return rc;
  259. }
  260. static int dsi_display_cmd_engine_disable(struct dsi_display *display)
  261. {
  262. int rc = 0;
  263. int i;
  264. struct dsi_display_ctrl *m_ctrl, *ctrl;
  265. bool skip_op = is_skip_op_required(display);
  266. m_ctrl = &display->ctrl[display->cmd_master_idx];
  267. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  268. if (display->cmd_engine_refcount == 0) {
  269. DSI_ERR("[%s] Invalid refcount\n", display->name);
  270. goto done;
  271. } else if (display->cmd_engine_refcount > 1) {
  272. display->cmd_engine_refcount--;
  273. goto done;
  274. }
  275. display_for_each_ctrl(i, display) {
  276. ctrl = &display->ctrl[i];
  277. if (!ctrl->ctrl || (ctrl == m_ctrl))
  278. continue;
  279. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  280. DSI_CTRL_ENGINE_OFF, skip_op);
  281. if (rc)
  282. DSI_ERR(
  283. "[%s] disable cmd engine failed, skip_op:%d rc:%d\n",
  284. display->name, skip_op, rc);
  285. }
  286. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  287. DSI_CTRL_ENGINE_OFF, skip_op);
  288. if (rc) {
  289. DSI_ERR("[%s] disable mcmd engine failed, skip_op:%d rc:%d\n",
  290. display->name, skip_op, rc);
  291. goto error;
  292. }
  293. error:
  294. display->cmd_engine_refcount = 0;
  295. done:
  296. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  297. return rc;
  298. }
  299. static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach)
  300. {
  301. struct dsi_display *display;
  302. struct dsi_display_ctrl *display_ctrl;
  303. int rc, cnt;
  304. if (!cb_data) {
  305. DSI_ERR("aspace cb called with invalid cb_data\n");
  306. return;
  307. }
  308. display = (struct dsi_display *)cb_data;
  309. /*
  310. * acquire panel_lock to make sure no commands are in-progress
  311. * while detaching the non-secure context banks
  312. */
  313. dsi_panel_acquire_panel_lock(display->panel);
  314. if (is_detach) {
  315. /* invalidate the stored iova */
  316. display->cmd_buffer_iova = 0;
  317. /* return the virtual address mapping */
  318. msm_gem_put_vaddr(display->tx_cmd_buf);
  319. msm_gem_vunmap(display->tx_cmd_buf, OBJ_LOCK_NORMAL);
  320. } else {
  321. rc = msm_gem_get_iova(display->tx_cmd_buf,
  322. display->aspace, &(display->cmd_buffer_iova));
  323. if (rc) {
  324. DSI_ERR("failed to get the iova rc %d\n", rc);
  325. goto end;
  326. }
  327. display->vaddr =
  328. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  329. if (IS_ERR_OR_NULL(display->vaddr)) {
  330. DSI_ERR("failed to get va rc %d\n", rc);
  331. goto end;
  332. }
  333. }
  334. display_for_each_ctrl(cnt, display) {
  335. display_ctrl = &display->ctrl[cnt];
  336. display_ctrl->ctrl->cmd_buffer_size = display->cmd_buffer_size;
  337. display_ctrl->ctrl->cmd_buffer_iova = display->cmd_buffer_iova;
  338. display_ctrl->ctrl->vaddr = display->vaddr;
  339. display_ctrl->ctrl->secure_mode = is_detach;
  340. }
  341. end:
  342. /* release panel_lock */
  343. dsi_panel_release_panel_lock(display->panel);
  344. }
  345. static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data)
  346. {
  347. struct dsi_display *display = (struct dsi_display *)data;
  348. /*
  349. * This irq handler is used for sole purpose of identifying
  350. * ESD attacks on panel and we can safely assume IRQ_HANDLED
  351. * in case of display not being initialized yet
  352. */
  353. if (!display)
  354. return IRQ_HANDLED;
  355. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  356. complete_all(&display->esd_te_gate);
  357. return IRQ_HANDLED;
  358. }
  359. static void dsi_display_change_te_irq_status(struct dsi_display *display,
  360. bool enable)
  361. {
  362. if (!display) {
  363. DSI_ERR("Invalid params\n");
  364. return;
  365. }
  366. /* Handle unbalanced irq enable/disable calls */
  367. if (enable && !display->is_te_irq_enabled) {
  368. enable_irq(gpio_to_irq(display->disp_te_gpio));
  369. display->is_te_irq_enabled = true;
  370. } else if (!enable && display->is_te_irq_enabled) {
  371. disable_irq(gpio_to_irq(display->disp_te_gpio));
  372. display->is_te_irq_enabled = false;
  373. }
  374. }
  375. static void dsi_display_register_te_irq(struct dsi_display *display)
  376. {
  377. int rc = 0;
  378. struct platform_device *pdev;
  379. struct device *dev;
  380. unsigned int te_irq;
  381. pdev = display->pdev;
  382. if (!pdev) {
  383. DSI_ERR("invalid platform device\n");
  384. return;
  385. }
  386. dev = &pdev->dev;
  387. if (!dev) {
  388. DSI_ERR("invalid device\n");
  389. return;
  390. }
  391. if (display->trusted_vm_env) {
  392. DSI_INFO("GPIO's are not enabled in trusted VM\n");
  393. return;
  394. }
  395. if (!gpio_is_valid(display->disp_te_gpio)) {
  396. rc = -EINVAL;
  397. goto error;
  398. }
  399. init_completion(&display->esd_te_gate);
  400. te_irq = gpio_to_irq(display->disp_te_gpio);
  401. /* Avoid deferred spurious irqs with disable_irq() */
  402. irq_set_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  403. rc = devm_request_irq(dev, te_irq, dsi_display_panel_te_irq_handler,
  404. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  405. "TE_GPIO", display);
  406. if (rc) {
  407. DSI_ERR("TE request_irq failed for ESD rc:%d\n", rc);
  408. irq_clear_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  409. goto error;
  410. }
  411. disable_irq(te_irq);
  412. display->is_te_irq_enabled = false;
  413. return;
  414. error:
  415. /* disable the TE based ESD check */
  416. DSI_WARN("Unable to register for TE IRQ\n");
  417. if (display->panel->esd_config.status_mode == ESD_MODE_PANEL_TE)
  418. display->panel->esd_config.esd_enabled = false;
  419. }
  420. /* Allocate memory for cmd dma tx buffer */
  421. static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display)
  422. {
  423. int rc = 0, cnt = 0;
  424. struct dsi_display_ctrl *display_ctrl;
  425. display->tx_cmd_buf = msm_gem_new(display->drm_dev,
  426. SZ_4K,
  427. MSM_BO_UNCACHED);
  428. if ((display->tx_cmd_buf) == NULL) {
  429. DSI_ERR("Failed to allocate cmd tx buf memory\n");
  430. rc = -ENOMEM;
  431. goto error;
  432. }
  433. display->cmd_buffer_size = SZ_4K;
  434. display->aspace = msm_gem_smmu_address_space_get(
  435. display->drm_dev, MSM_SMMU_DOMAIN_UNSECURE);
  436. if (PTR_ERR(display->aspace) == -ENODEV) {
  437. display->aspace = NULL;
  438. DSI_DEBUG("IOMMU not present, relying on VRAM\n");
  439. } else if (IS_ERR_OR_NULL(display->aspace)) {
  440. rc = PTR_ERR(display->aspace);
  441. display->aspace = NULL;
  442. DSI_ERR("failed to get aspace %d\n", rc);
  443. goto free_gem;
  444. } else if (display->aspace) {
  445. /* register to aspace */
  446. rc = msm_gem_address_space_register_cb(display->aspace,
  447. dsi_display_aspace_cb_locked, (void *)display);
  448. if (rc) {
  449. DSI_ERR("failed to register callback %d\n", rc);
  450. goto free_gem;
  451. }
  452. }
  453. rc = msm_gem_get_iova(display->tx_cmd_buf, display->aspace,
  454. &(display->cmd_buffer_iova));
  455. if (rc) {
  456. DSI_ERR("failed to get the iova rc %d\n", rc);
  457. goto free_aspace_cb;
  458. }
  459. display->vaddr =
  460. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  461. if (IS_ERR_OR_NULL(display->vaddr)) {
  462. DSI_ERR("failed to get va rc %d\n", rc);
  463. rc = -EINVAL;
  464. goto put_iova;
  465. }
  466. display_for_each_ctrl(cnt, display) {
  467. display_ctrl = &display->ctrl[cnt];
  468. display_ctrl->ctrl->cmd_buffer_size = SZ_4K;
  469. display_ctrl->ctrl->cmd_buffer_iova =
  470. display->cmd_buffer_iova;
  471. display_ctrl->ctrl->vaddr = display->vaddr;
  472. display_ctrl->ctrl->tx_cmd_buf = display->tx_cmd_buf;
  473. }
  474. return rc;
  475. put_iova:
  476. msm_gem_put_iova(display->tx_cmd_buf, display->aspace);
  477. free_aspace_cb:
  478. msm_gem_address_space_unregister_cb(display->aspace,
  479. dsi_display_aspace_cb_locked, display);
  480. free_gem:
  481. mutex_lock(&display->drm_dev->struct_mutex);
  482. msm_gem_free_object(display->tx_cmd_buf);
  483. mutex_unlock(&display->drm_dev->struct_mutex);
  484. error:
  485. return rc;
  486. }
  487. static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
  488. {
  489. int i, j = 0;
  490. int len = 0, *lenp;
  491. int group = 0, count = 0;
  492. struct drm_panel_esd_config *config;
  493. if (!panel)
  494. return false;
  495. config = &(panel->esd_config);
  496. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  497. count = config->status_cmd.count;
  498. for (i = 0; i < count; i++)
  499. len += lenp[i];
  500. for (i = 0; i < len; i++)
  501. j += len;
  502. for (j = 0; j < config->groups; ++j) {
  503. for (i = 0; i < len; ++i) {
  504. if (config->return_buf[i] !=
  505. config->status_value[group + i]) {
  506. DRM_ERROR("mismatch: 0x%x\n",
  507. config->return_buf[i]);
  508. break;
  509. }
  510. }
  511. if (i == len)
  512. return true;
  513. group += len;
  514. }
  515. return false;
  516. }
  517. static void dsi_display_parse_demura_data(struct dsi_display *display)
  518. {
  519. int rc = 0;
  520. display->panel_id = ~0x0;
  521. if (display->fw) {
  522. DSI_INFO("FW definition unsupported for Demura panel data\n");
  523. return;
  524. }
  525. rc = of_property_read_u64(display->pdev->dev.of_node,
  526. "qcom,demura-panel-id", &display->panel_id);
  527. if (rc) {
  528. DSI_INFO("No panel ID is present for this display\n");
  529. } else if (!display->panel_id) {
  530. DSI_INFO("Dummy panel ID node present for this display\n");
  531. display->panel_id = ~0x0;
  532. } else {
  533. DSI_INFO("panel id found: %lx\n", display->panel_id);
  534. }
  535. }
  536. static void dsi_display_parse_te_data(struct dsi_display *display)
  537. {
  538. struct platform_device *pdev;
  539. struct device *dev;
  540. int rc = 0;
  541. u32 val = 0;
  542. pdev = display->pdev;
  543. if (!pdev) {
  544. DSI_ERR("Invalid platform device\n");
  545. return;
  546. }
  547. dev = &pdev->dev;
  548. if (!dev) {
  549. DSI_ERR("Invalid platform device\n");
  550. return;
  551. }
  552. display->disp_te_gpio = of_get_named_gpio(dev->of_node,
  553. "qcom,platform-te-gpio", 0);
  554. if (display->fw)
  555. rc = dsi_parser_read_u32(display->parser_node,
  556. "qcom,panel-te-source", &val);
  557. else
  558. rc = of_property_read_u32(dev->of_node,
  559. "qcom,panel-te-source", &val);
  560. if (rc || (val > MAX_TE_SOURCE_ID)) {
  561. DSI_ERR("invalid vsync source selection\n");
  562. val = 0;
  563. }
  564. display->te_source = val;
  565. }
  566. static void dsi_display_set_cmd_tx_ctrl_flags(struct dsi_display *display,
  567. struct dsi_cmd_desc *cmd)
  568. {
  569. struct dsi_display_ctrl *ctrl, *m_ctrl;
  570. struct mipi_dsi_msg *msg = &cmd->msg;
  571. u32 flags = 0;
  572. int i = 0;
  573. m_ctrl = &display->ctrl[display->clk_master_idx];
  574. display_for_each_ctrl(i, display) {
  575. ctrl = &display->ctrl[i];
  576. if (!ctrl->ctrl)
  577. continue;
  578. /*
  579. * Set cmd transfer mode flags.
  580. * 1) Default selection is CMD fetch from memory.
  581. * 2) In secure session override and use FIFO rather than
  582. * memory.
  583. * 3) If cmd_len is greater than FIFO size non embedded mode of
  584. * tx is used.
  585. */
  586. flags = DSI_CTRL_CMD_FETCH_MEMORY;
  587. if (ctrl->ctrl->secure_mode) {
  588. flags &= ~DSI_CTRL_CMD_FETCH_MEMORY;
  589. flags |= DSI_CTRL_CMD_FIFO_STORE;
  590. } else if (msg->tx_len > DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES) {
  591. flags |= DSI_CTRL_CMD_NON_EMBEDDED_MODE;
  592. }
  593. /* Set flags needed for broadcast. Read commands are always unicast */
  594. if (!(msg->flags & MIPI_DSI_MSG_UNICAST_COMMAND) && (display->ctrl_count > 1))
  595. flags |= DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER;
  596. /*
  597. * Set flags for command scheduling.
  598. * 1) In video mode command DMA scheduling is default.
  599. * 2) In command mode command DMA scheduling depends on message
  600. * flag and TE needs to be running.
  601. */
  602. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  603. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  604. } else {
  605. if (msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED)
  606. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  607. if (!display->enabled)
  608. flags &= ~DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  609. }
  610. /* Set flags for last command */
  611. if (!(msg->flags & MIPI_DSI_MSG_BATCH_COMMAND))
  612. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  613. /*
  614. * Set flags for asynchronous wait.
  615. * Asynchronous wait is supported in the following scenarios
  616. * 1) queue_cmd_waits is set by connector and
  617. * - commands are not sent using DSI FIFO memory
  618. * - commands are not sent in non-embedded mode
  619. * - not a video mode panel
  620. * - no explicit msg post_wait_ms is specified
  621. * - not a read command
  622. * 2) if async override msg flag is present
  623. */
  624. if (display->queue_cmd_waits)
  625. if (!(flags & DSI_CTRL_CMD_FIFO_STORE) &&
  626. !(flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) &&
  627. !(display->panel->panel_mode == DSI_OP_VIDEO_MODE) &&
  628. (cmd->post_wait_ms == 0) &&
  629. !(cmd->ctrl_flags & DSI_CTRL_CMD_READ))
  630. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  631. if (msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE)
  632. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  633. }
  634. cmd->ctrl_flags |= flags;
  635. }
  636. static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
  637. struct dsi_display *display)
  638. {
  639. int i, rc = 0, count = 0, start = 0, *lenp;
  640. struct drm_panel_esd_config *config;
  641. struct dsi_cmd_desc *cmds;
  642. struct dsi_panel *panel;
  643. u32 flags = 0;
  644. if (!display->panel || !ctrl || !ctrl->ctrl)
  645. return -EINVAL;
  646. panel = display->panel;
  647. /*
  648. * When DSI controller is not in initialized state, we do not want to
  649. * report a false ESD failure and hence we defer until next read
  650. * happen.
  651. */
  652. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  653. return 1;
  654. config = &(panel->esd_config);
  655. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  656. count = config->status_cmd.count;
  657. cmds = config->status_cmd.cmds;
  658. flags = DSI_CTRL_CMD_READ;
  659. for (i = 0; i < count; ++i) {
  660. memset(config->status_buf, 0x0, SZ_4K);
  661. if (config->status_cmd.state == DSI_CMD_SET_STATE_LP)
  662. cmds[i].msg.flags |= MIPI_DSI_MSG_USE_LPM;
  663. cmds[i].msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  664. cmds[i].msg.rx_buf = config->status_buf;
  665. cmds[i].msg.rx_len = config->status_cmds_rlen[i];
  666. cmds[i].ctrl_flags = flags;
  667. dsi_display_set_cmd_tx_ctrl_flags(display,&cmds[i]);
  668. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i]);
  669. if (rc <= 0) {
  670. DSI_ERR("rx cmd transfer failed rc=%d\n", rc);
  671. return rc;
  672. }
  673. memcpy(config->return_buf + start,
  674. config->status_buf, lenp[i]);
  675. start += lenp[i];
  676. }
  677. return rc;
  678. }
  679. static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
  680. struct dsi_display *display)
  681. {
  682. int rc = 0;
  683. rc = dsi_display_read_status(ctrl, display);
  684. if (rc <= 0) {
  685. goto exit;
  686. } else {
  687. /*
  688. * panel status read successfully.
  689. * check for validity of the data read back.
  690. */
  691. rc = dsi_display_validate_reg_read(display->panel);
  692. if (!rc) {
  693. rc = -EINVAL;
  694. goto exit;
  695. }
  696. }
  697. exit:
  698. return rc;
  699. }
  700. static int dsi_display_status_reg_read(struct dsi_display *display)
  701. {
  702. int rc = 0, i;
  703. struct dsi_display_ctrl *m_ctrl, *ctrl;
  704. DSI_DEBUG(" ++\n");
  705. m_ctrl = &display->ctrl[display->cmd_master_idx];
  706. if (display->tx_cmd_buf == NULL) {
  707. rc = dsi_host_alloc_cmd_tx_buffer(display);
  708. if (rc) {
  709. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  710. goto done;
  711. }
  712. }
  713. rc = dsi_display_cmd_engine_enable(display);
  714. if (rc) {
  715. DSI_ERR("cmd engine enable failed\n");
  716. return -EPERM;
  717. }
  718. rc = dsi_display_validate_status(m_ctrl, display);
  719. if (rc <= 0) {
  720. DSI_ERR("[%s] read status failed on master,rc=%d\n",
  721. display->name, rc);
  722. goto exit;
  723. }
  724. if (!display->panel->sync_broadcast_en)
  725. goto exit;
  726. display_for_each_ctrl(i, display) {
  727. ctrl = &display->ctrl[i];
  728. if (ctrl == m_ctrl)
  729. continue;
  730. rc = dsi_display_validate_status(ctrl, display);
  731. if (rc <= 0) {
  732. DSI_ERR("[%s] read status failed on slave,rc=%d\n",
  733. display->name, rc);
  734. goto exit;
  735. }
  736. }
  737. exit:
  738. dsi_display_cmd_engine_disable(display);
  739. done:
  740. return rc;
  741. }
  742. static int dsi_display_status_bta_request(struct dsi_display *display)
  743. {
  744. int rc = 0;
  745. DSI_DEBUG(" ++\n");
  746. /* TODO: trigger SW BTA and wait for acknowledgment */
  747. return rc;
  748. }
  749. static int dsi_display_status_check_te(struct dsi_display *display,
  750. int rechecks)
  751. {
  752. int rc = 1, i = 0;
  753. int const esd_te_timeout = msecs_to_jiffies(3*20);
  754. if (!rechecks)
  755. return rc;
  756. dsi_display_change_te_irq_status(display, true);
  757. for (i = 0; i < rechecks; i++) {
  758. reinit_completion(&display->esd_te_gate);
  759. if (!wait_for_completion_timeout(&display->esd_te_gate,
  760. esd_te_timeout)) {
  761. DSI_ERR("TE check failed\n");
  762. dsi_display_change_te_irq_status(display, false);
  763. return -EINVAL;
  764. }
  765. }
  766. dsi_display_change_te_irq_status(display, false);
  767. return rc;
  768. }
  769. int dsi_display_check_status(struct drm_connector *connector, void *display,
  770. bool te_check_override)
  771. {
  772. struct dsi_display *dsi_display = display;
  773. struct dsi_panel *panel;
  774. u32 status_mode;
  775. int rc = 0x1, ret;
  776. u32 mask;
  777. int te_rechecks = 1;
  778. if (!dsi_display || !dsi_display->panel)
  779. return -EINVAL;
  780. panel = dsi_display->panel;
  781. dsi_panel_acquire_panel_lock(panel);
  782. if (!panel->panel_initialized) {
  783. DSI_DEBUG("Panel not initialized\n");
  784. goto release_panel_lock;
  785. }
  786. /* Prevent another ESD check,when ESD recovery is underway */
  787. if (atomic_read(&panel->esd_recovery_pending))
  788. goto release_panel_lock;
  789. status_mode = panel->esd_config.status_mode;
  790. if ((status_mode == ESD_MODE_SW_SIM_SUCCESS) ||
  791. (dsi_display->sw_te_using_wd))
  792. goto release_panel_lock;
  793. if (status_mode == ESD_MODE_SW_SIM_FAILURE) {
  794. rc = -EINVAL;
  795. goto release_panel_lock;
  796. }
  797. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, status_mode, te_check_override);
  798. if (te_check_override)
  799. te_rechecks = MAX_TE_RECHECKS;
  800. if ((dsi_display->trusted_vm_env) ||
  801. (panel->panel_mode == DSI_OP_VIDEO_MODE))
  802. te_rechecks = 0;
  803. ret = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  804. DSI_ALL_CLKS, DSI_CLK_ON);
  805. if (ret)
  806. goto release_panel_lock;
  807. /* Mask error interrupts before attempting ESD read */
  808. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  809. dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
  810. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask, true);
  811. if (status_mode == ESD_MODE_REG_READ) {
  812. rc = dsi_display_status_reg_read(dsi_display);
  813. } else if (status_mode == ESD_MODE_SW_BTA) {
  814. rc = dsi_display_status_bta_request(dsi_display);
  815. } else if (status_mode == ESD_MODE_PANEL_TE) {
  816. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  817. te_check_override = false;
  818. } else {
  819. DSI_WARN("Unsupported check status mode: %d\n", status_mode);
  820. panel->esd_config.esd_enabled = false;
  821. }
  822. if (rc <= 0 && te_check_override)
  823. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  824. /* Unmask error interrupts if check passed*/
  825. if (rc > 0) {
  826. dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
  827. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask,
  828. false);
  829. if (te_check_override && panel->esd_config.esd_enabled == false)
  830. rc = dsi_display_status_check_te(dsi_display,
  831. te_rechecks);
  832. }
  833. dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  834. DSI_ALL_CLKS, DSI_CLK_OFF);
  835. /* Handle Panel failures during display disable sequence */
  836. if (rc <=0)
  837. atomic_set(&panel->esd_recovery_pending, 1);
  838. release_panel_lock:
  839. dsi_panel_release_panel_lock(panel);
  840. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, rc);
  841. return rc;
  842. }
  843. static int dsi_display_ctrl_get_host_init_state(struct dsi_display *dsi_display,
  844. bool *state)
  845. {
  846. struct dsi_display_ctrl *ctrl;
  847. int i, rc = -EINVAL;
  848. display_for_each_ctrl(i, dsi_display) {
  849. ctrl = &dsi_display->ctrl[i];
  850. rc = dsi_ctrl_get_host_engine_init_state(ctrl->ctrl, state);
  851. if (rc)
  852. break;
  853. }
  854. return rc;
  855. }
  856. static int dsi_display_cmd_rx(struct dsi_display *display,
  857. struct dsi_cmd_desc *cmd)
  858. {
  859. struct dsi_display_ctrl *m_ctrl = NULL;
  860. u32 mask = 0, flags = 0;
  861. int rc = 0;
  862. if (!display || !display->panel)
  863. return -EINVAL;
  864. m_ctrl = &display->ctrl[display->cmd_master_idx];
  865. if (!m_ctrl || !m_ctrl->ctrl)
  866. return -EINVAL;
  867. /* acquire panel_lock to make sure no commands are in progress */
  868. dsi_panel_acquire_panel_lock(display->panel);
  869. if (!display->panel->panel_initialized) {
  870. DSI_DEBUG("panel not initialized\n");
  871. goto release_panel_lock;
  872. }
  873. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  874. DSI_ALL_CLKS, DSI_CLK_ON);
  875. if (rc)
  876. goto release_panel_lock;
  877. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  878. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  879. rc = dsi_display_cmd_engine_enable(display);
  880. if (rc) {
  881. DSI_ERR("cmd engine enable failed rc = %d\n", rc);
  882. goto error;
  883. }
  884. flags = DSI_CTRL_CMD_READ;
  885. cmd->ctrl_flags = flags;
  886. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  887. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  888. if (rc <= 0)
  889. DSI_ERR("rx cmd transfer failed rc = %d\n", rc);
  890. dsi_display_cmd_engine_disable(display);
  891. error:
  892. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  893. dsi_display_clk_ctrl(display->dsi_clk_handle,
  894. DSI_ALL_CLKS, DSI_CLK_OFF);
  895. release_panel_lock:
  896. dsi_panel_release_panel_lock(display->panel);
  897. return rc;
  898. }
  899. int dsi_display_cmd_transfer(struct drm_connector *connector,
  900. void *display, const char *cmd_buf,
  901. u32 cmd_buf_len)
  902. {
  903. struct dsi_display *dsi_display = display;
  904. int rc = 0, cnt = 0, i = 0;
  905. bool state = false, transfer = false;
  906. struct dsi_panel_cmd_set *set;
  907. if (!dsi_display || !cmd_buf) {
  908. DSI_ERR("[DSI] invalid params\n");
  909. return -EINVAL;
  910. }
  911. DSI_DEBUG("[DSI] Display command transfer\n");
  912. if (!(cmd_buf[3] & MIPI_DSI_MSG_BATCH_COMMAND))
  913. transfer = true;
  914. mutex_lock(&dsi_display->display_lock);
  915. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  916. /**
  917. * Handle scenario where a command transfer is initiated through
  918. * sysfs interface when device is in suepnd state.
  919. */
  920. if (!rc && !state) {
  921. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n"
  922. );
  923. rc = -EPERM;
  924. goto end;
  925. }
  926. if (rc || !state) {
  927. DSI_ERR("[DSI] Invalid host state %d rc %d\n",
  928. state, rc);
  929. rc = -EPERM;
  930. goto end;
  931. }
  932. /*
  933. * Reset the dbgfs buffer if the commands sent exceed the available
  934. * buffer size. For video mode, limiting the buffer size to 2K to
  935. * ensure no performance issues.
  936. */
  937. if (dsi_display->panel->panel_mode == DSI_OP_CMD_MODE) {
  938. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_4K) {
  939. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  940. dsi_display->tx_cmd_buf_ndx = 0;
  941. }
  942. } else {
  943. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_2K) {
  944. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  945. dsi_display->tx_cmd_buf_ndx = 0;
  946. }
  947. }
  948. memcpy(&dbgfs_tx_cmd_buf[dsi_display->tx_cmd_buf_ndx], cmd_buf,
  949. cmd_buf_len);
  950. dsi_display->tx_cmd_buf_ndx += cmd_buf_len;
  951. if (transfer) {
  952. struct dsi_cmd_desc *cmds;
  953. set = &dsi_display->cmd_set;
  954. set->count = 0;
  955. dsi_panel_get_cmd_pkt_count(dbgfs_tx_cmd_buf,
  956. dsi_display->tx_cmd_buf_ndx, &cnt);
  957. dsi_panel_alloc_cmd_packets(set, cnt);
  958. dsi_panel_create_cmd_packets(dbgfs_tx_cmd_buf,
  959. dsi_display->tx_cmd_buf_ndx, cnt, set->cmds);
  960. cmds = set->cmds;
  961. dsi_display->tx_cmd_buf_ndx = 0;
  962. for (i = 0; i < cnt; i++) {
  963. rc = dsi_host_transfer_sub(&dsi_display->host, cmds);
  964. if (rc < 0) {
  965. DSI_ERR("failed to send command, rc=%d\n", rc);
  966. break;
  967. }
  968. if (cmds->post_wait_ms)
  969. usleep_range(cmds->post_wait_ms*1000,
  970. ((cmds->post_wait_ms*1000)+10));
  971. cmds++;
  972. }
  973. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  974. dsi_panel_destroy_cmd_packets(set);
  975. dsi_panel_dealloc_cmd_packets(set);
  976. }
  977. end:
  978. mutex_unlock(&dsi_display->display_lock);
  979. return rc;
  980. }
  981. static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
  982. bool enable)
  983. {
  984. int i;
  985. struct dsi_display_ctrl *ctrl;
  986. if (!display || !display->panel->host_config.force_hs_clk_lane)
  987. return;
  988. display_for_each_ctrl(i, display) {
  989. ctrl = &display->ctrl[i];
  990. /*
  991. * For phy ver 4.0 chipsets, configure DSI controller and
  992. * DSI PHY to force clk lane to HS mode always whereas
  993. * for other phy ver chipsets, configure DSI controller only.
  994. */
  995. if (ctrl->phy->hw.ops.set_continuous_clk) {
  996. dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
  997. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  998. dsi_phy_set_continuous_clk(ctrl->phy, enable);
  999. } else {
  1000. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  1001. }
  1002. }
  1003. }
  1004. int dsi_display_cmd_receive(void *display, const char *cmd_buf,
  1005. u32 cmd_buf_len, u8 *recv_buf, u32 recv_buf_len)
  1006. {
  1007. struct dsi_display *dsi_display = display;
  1008. struct dsi_cmd_desc cmd = {};
  1009. bool state = false;
  1010. int rc = -1;
  1011. if (!dsi_display || !cmd_buf || !recv_buf) {
  1012. DSI_ERR("[DSI] invalid params\n");
  1013. return -EINVAL;
  1014. }
  1015. rc = dsi_panel_create_cmd_packets(cmd_buf, cmd_buf_len, 1, &cmd);
  1016. if (rc) {
  1017. DSI_ERR("[DSI] command packet create failed, rc = %d\n", rc);
  1018. return rc;
  1019. }
  1020. cmd.msg.rx_buf = recv_buf;
  1021. cmd.msg.rx_len = recv_buf_len;
  1022. cmd.msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  1023. mutex_lock(&dsi_display->display_lock);
  1024. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  1025. if (rc || !state) {
  1026. DSI_ERR("[DSI] Invalid host state = %d rc = %d\n",
  1027. state, rc);
  1028. rc = -EPERM;
  1029. goto end;
  1030. }
  1031. rc = dsi_display_cmd_rx(dsi_display, &cmd);
  1032. if (rc <= 0)
  1033. DSI_ERR("[DSI] Display command receive failed, rc=%d\n", rc);
  1034. end:
  1035. mutex_unlock(&dsi_display->display_lock);
  1036. return rc;
  1037. }
  1038. int dsi_display_soft_reset(void *display)
  1039. {
  1040. struct dsi_display *dsi_display;
  1041. struct dsi_display_ctrl *ctrl;
  1042. int rc = 0;
  1043. int i;
  1044. if (!display)
  1045. return -EINVAL;
  1046. dsi_display = display;
  1047. display_for_each_ctrl(i, dsi_display) {
  1048. ctrl = &dsi_display->ctrl[i];
  1049. rc = dsi_ctrl_soft_reset(ctrl->ctrl);
  1050. if (rc) {
  1051. DSI_ERR("[%s] failed to soft reset host_%d, rc=%d\n",
  1052. dsi_display->name, i, rc);
  1053. break;
  1054. }
  1055. }
  1056. return rc;
  1057. }
  1058. enum dsi_pixel_format dsi_display_get_dst_format(
  1059. struct drm_connector *connector,
  1060. void *display)
  1061. {
  1062. enum dsi_pixel_format format = DSI_PIXEL_FORMAT_MAX;
  1063. struct dsi_display *dsi_display = (struct dsi_display *)display;
  1064. if (!dsi_display || !dsi_display->panel) {
  1065. DSI_ERR("Invalid params(s) dsi_display %pK, panel %pK\n",
  1066. dsi_display,
  1067. ((dsi_display) ? dsi_display->panel : NULL));
  1068. return format;
  1069. }
  1070. format = dsi_display->panel->host_config.dst_format;
  1071. return format;
  1072. }
  1073. static void _dsi_display_setup_misr(struct dsi_display *display)
  1074. {
  1075. int i;
  1076. display_for_each_ctrl(i, display) {
  1077. dsi_ctrl_setup_misr(display->ctrl[i].ctrl,
  1078. display->misr_enable,
  1079. display->misr_frame_count);
  1080. }
  1081. }
  1082. int dsi_display_set_power(struct drm_connector *connector,
  1083. int power_mode, void *disp)
  1084. {
  1085. struct dsi_display *display = disp;
  1086. int rc = 0;
  1087. if (!display || !display->panel) {
  1088. DSI_ERR("invalid display/panel\n");
  1089. return -EINVAL;
  1090. }
  1091. switch (power_mode) {
  1092. case SDE_MODE_DPMS_LP1:
  1093. rc = dsi_panel_set_lp1(display->panel);
  1094. break;
  1095. case SDE_MODE_DPMS_LP2:
  1096. rc = dsi_panel_set_lp2(display->panel);
  1097. break;
  1098. case SDE_MODE_DPMS_ON:
  1099. if ((display->panel->power_mode == SDE_MODE_DPMS_LP1) ||
  1100. (display->panel->power_mode == SDE_MODE_DPMS_LP2))
  1101. rc = dsi_panel_set_nolp(display->panel);
  1102. break;
  1103. case SDE_MODE_DPMS_OFF:
  1104. default:
  1105. return rc;
  1106. }
  1107. SDE_EVT32(display->panel->power_mode, power_mode, rc);
  1108. DSI_DEBUG("Power mode transition from %d to %d %s",
  1109. display->panel->power_mode, power_mode,
  1110. rc ? "failed" : "successful");
  1111. if (!rc)
  1112. display->panel->power_mode = power_mode;
  1113. return rc;
  1114. }
  1115. #ifdef CONFIG_DEBUG_FS
  1116. static bool dsi_display_is_te_based_esd(struct dsi_display *display)
  1117. {
  1118. u32 status_mode = 0;
  1119. if (!display->panel) {
  1120. DSI_ERR("Invalid panel data\n");
  1121. return false;
  1122. }
  1123. status_mode = display->panel->esd_config.status_mode;
  1124. if (status_mode == ESD_MODE_PANEL_TE &&
  1125. gpio_is_valid(display->disp_te_gpio))
  1126. return true;
  1127. return false;
  1128. }
  1129. static ssize_t debugfs_dump_info_read(struct file *file,
  1130. char __user *user_buf,
  1131. size_t user_len,
  1132. loff_t *ppos)
  1133. {
  1134. struct dsi_display *display = file->private_data;
  1135. char *buf;
  1136. u32 len = 0;
  1137. int i;
  1138. if (!display)
  1139. return -ENODEV;
  1140. if (*ppos)
  1141. return 0;
  1142. buf = kzalloc(SZ_4K, GFP_KERNEL);
  1143. if (!buf)
  1144. return -ENOMEM;
  1145. len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
  1146. len += snprintf(buf + len, (SZ_4K - len),
  1147. "\tResolution = %dx%d\n",
  1148. display->config.video_timing.h_active,
  1149. display->config.video_timing.v_active);
  1150. display_for_each_ctrl(i, display) {
  1151. len += snprintf(buf + len, (SZ_4K - len),
  1152. "\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
  1153. i, display->ctrl[i].ctrl->name,
  1154. display->ctrl[i].phy->name);
  1155. }
  1156. len += snprintf(buf + len, (SZ_4K - len),
  1157. "\tPanel = %s\n", display->panel->name);
  1158. len += snprintf(buf + len, (SZ_4K - len),
  1159. "\tClock master = %s\n",
  1160. display->ctrl[display->clk_master_idx].ctrl->name);
  1161. if (len > user_len)
  1162. len = user_len;
  1163. if (copy_to_user(user_buf, buf, len)) {
  1164. kfree(buf);
  1165. return -EFAULT;
  1166. }
  1167. *ppos += len;
  1168. kfree(buf);
  1169. return len;
  1170. }
  1171. static ssize_t debugfs_misr_setup(struct file *file,
  1172. const char __user *user_buf,
  1173. size_t user_len,
  1174. loff_t *ppos)
  1175. {
  1176. struct dsi_display *display = file->private_data;
  1177. char *buf;
  1178. int rc = 0;
  1179. size_t len;
  1180. u32 enable, frame_count;
  1181. if (!display)
  1182. return -ENODEV;
  1183. if (*ppos)
  1184. return 0;
  1185. buf = kzalloc(MISR_BUFF_SIZE, GFP_KERNEL);
  1186. if (!buf)
  1187. return -ENOMEM;
  1188. /* leave room for termination char */
  1189. len = min_t(size_t, user_len, MISR_BUFF_SIZE - 1);
  1190. if (copy_from_user(buf, user_buf, len)) {
  1191. rc = -EINVAL;
  1192. goto error;
  1193. }
  1194. buf[len] = '\0'; /* terminate the string */
  1195. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) {
  1196. rc = -EINVAL;
  1197. goto error;
  1198. }
  1199. display->misr_enable = enable;
  1200. display->misr_frame_count = frame_count;
  1201. mutex_lock(&display->display_lock);
  1202. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1203. DSI_CORE_CLK, DSI_CLK_ON);
  1204. if (rc) {
  1205. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1206. display->name, rc);
  1207. goto unlock;
  1208. }
  1209. _dsi_display_setup_misr(display);
  1210. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1211. DSI_CORE_CLK, DSI_CLK_OFF);
  1212. if (rc) {
  1213. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1214. display->name, rc);
  1215. goto unlock;
  1216. }
  1217. rc = user_len;
  1218. unlock:
  1219. mutex_unlock(&display->display_lock);
  1220. error:
  1221. kfree(buf);
  1222. return rc;
  1223. }
  1224. static ssize_t debugfs_misr_read(struct file *file,
  1225. char __user *user_buf,
  1226. size_t user_len,
  1227. loff_t *ppos)
  1228. {
  1229. struct dsi_display *display = file->private_data;
  1230. char *buf;
  1231. u32 len = 0;
  1232. int rc = 0;
  1233. struct dsi_ctrl *dsi_ctrl;
  1234. int i;
  1235. u32 misr;
  1236. size_t max_len = min_t(size_t, user_len, MISR_BUFF_SIZE);
  1237. if (!display)
  1238. return -ENODEV;
  1239. if (*ppos)
  1240. return 0;
  1241. buf = kzalloc(max_len, GFP_KERNEL);
  1242. if (ZERO_OR_NULL_PTR(buf))
  1243. return -ENOMEM;
  1244. mutex_lock(&display->display_lock);
  1245. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1246. DSI_CORE_CLK, DSI_CLK_ON);
  1247. if (rc) {
  1248. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1249. display->name, rc);
  1250. goto error;
  1251. }
  1252. display_for_each_ctrl(i, display) {
  1253. dsi_ctrl = display->ctrl[i].ctrl;
  1254. misr = dsi_ctrl_collect_misr(display->ctrl[i].ctrl);
  1255. len += snprintf((buf + len), max_len - len,
  1256. "DSI_%d MISR: 0x%x\n", dsi_ctrl->cell_index, misr);
  1257. if (len >= max_len)
  1258. break;
  1259. }
  1260. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1261. DSI_CORE_CLK, DSI_CLK_OFF);
  1262. if (rc) {
  1263. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1264. display->name, rc);
  1265. goto error;
  1266. }
  1267. if (copy_to_user(user_buf, buf, max_len)) {
  1268. rc = -EFAULT;
  1269. goto error;
  1270. }
  1271. *ppos += len;
  1272. error:
  1273. mutex_unlock(&display->display_lock);
  1274. kfree(buf);
  1275. return len;
  1276. }
  1277. static ssize_t debugfs_esd_trigger_check(struct file *file,
  1278. const char __user *user_buf,
  1279. size_t user_len,
  1280. loff_t *ppos)
  1281. {
  1282. struct dsi_display *display = file->private_data;
  1283. char *buf;
  1284. int rc = 0;
  1285. struct drm_panel_esd_config *esd_config = &display->panel->esd_config;
  1286. u32 esd_trigger;
  1287. size_t len;
  1288. if (!display)
  1289. return -ENODEV;
  1290. if (*ppos)
  1291. return 0;
  1292. if (user_len > sizeof(u32))
  1293. return -EINVAL;
  1294. if (!user_len || !user_buf)
  1295. return -EINVAL;
  1296. if (!display->panel ||
  1297. atomic_read(&display->panel->esd_recovery_pending))
  1298. return user_len;
  1299. if (!esd_config->esd_enabled) {
  1300. DSI_ERR("ESD feature is not enabled\n");
  1301. return -EINVAL;
  1302. }
  1303. buf = kzalloc(ESD_TRIGGER_STRING_MAX_LEN, GFP_KERNEL);
  1304. if (!buf)
  1305. return -ENOMEM;
  1306. len = min_t(size_t, user_len, ESD_TRIGGER_STRING_MAX_LEN - 1);
  1307. if (copy_from_user(buf, user_buf, len)) {
  1308. rc = -EINVAL;
  1309. goto error;
  1310. }
  1311. buf[len] = '\0'; /* terminate the string */
  1312. if (kstrtouint(buf, 10, &esd_trigger)) {
  1313. rc = -EINVAL;
  1314. goto error;
  1315. }
  1316. if (esd_trigger != 1) {
  1317. rc = -EINVAL;
  1318. goto error;
  1319. }
  1320. display->esd_trigger = esd_trigger;
  1321. if (display->esd_trigger) {
  1322. DSI_INFO("ESD attack triggered by user\n");
  1323. rc = dsi_panel_trigger_esd_attack(display->panel,
  1324. display->trusted_vm_env);
  1325. if (rc) {
  1326. DSI_ERR("Failed to trigger ESD attack\n");
  1327. goto error;
  1328. }
  1329. }
  1330. rc = len;
  1331. error:
  1332. kfree(buf);
  1333. return rc;
  1334. }
  1335. static ssize_t debugfs_alter_esd_check_mode(struct file *file,
  1336. const char __user *user_buf,
  1337. size_t user_len,
  1338. loff_t *ppos)
  1339. {
  1340. struct dsi_display *display = file->private_data;
  1341. struct drm_panel_esd_config *esd_config;
  1342. char *buf;
  1343. int rc = 0;
  1344. size_t len;
  1345. if (!display)
  1346. return -ENODEV;
  1347. if (*ppos)
  1348. return 0;
  1349. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1350. if (ZERO_OR_NULL_PTR(buf))
  1351. return -ENOMEM;
  1352. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1353. if (copy_from_user(buf, user_buf, len)) {
  1354. rc = -EINVAL;
  1355. goto error;
  1356. }
  1357. buf[len] = '\0'; /* terminate the string */
  1358. if (!display->panel) {
  1359. rc = -EINVAL;
  1360. goto error;
  1361. }
  1362. esd_config = &display->panel->esd_config;
  1363. if (!esd_config) {
  1364. DSI_ERR("Invalid panel esd config\n");
  1365. rc = -EINVAL;
  1366. goto error;
  1367. }
  1368. if (!esd_config->esd_enabled) {
  1369. rc = -EINVAL;
  1370. goto error;
  1371. }
  1372. if (!strcmp(buf, "te_signal_check\n")) {
  1373. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  1374. DSI_INFO("TE based ESD check for Video Mode panels is not allowed\n");
  1375. rc = -EINVAL;
  1376. goto error;
  1377. }
  1378. DSI_INFO("ESD check is switched to TE mode by user\n");
  1379. esd_config->status_mode = ESD_MODE_PANEL_TE;
  1380. dsi_display_change_te_irq_status(display, true);
  1381. }
  1382. if (!strcmp(buf, "reg_read\n")) {
  1383. DSI_INFO("ESD check is switched to reg read by user\n");
  1384. rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
  1385. if (rc) {
  1386. DSI_ERR("failed to alter esd check mode,rc=%d\n",
  1387. rc);
  1388. rc = user_len;
  1389. goto error;
  1390. }
  1391. esd_config->status_mode = ESD_MODE_REG_READ;
  1392. if (dsi_display_is_te_based_esd(display))
  1393. dsi_display_change_te_irq_status(display, false);
  1394. }
  1395. if (!strcmp(buf, "esd_sw_sim_success\n"))
  1396. esd_config->status_mode = ESD_MODE_SW_SIM_SUCCESS;
  1397. if (!strcmp(buf, "esd_sw_sim_failure\n"))
  1398. esd_config->status_mode = ESD_MODE_SW_SIM_FAILURE;
  1399. rc = len;
  1400. error:
  1401. kfree(buf);
  1402. return rc;
  1403. }
  1404. static ssize_t debugfs_read_esd_check_mode(struct file *file,
  1405. char __user *user_buf,
  1406. size_t user_len,
  1407. loff_t *ppos)
  1408. {
  1409. struct dsi_display *display = file->private_data;
  1410. struct drm_panel_esd_config *esd_config;
  1411. char *buf;
  1412. int rc = 0;
  1413. size_t len = 0;
  1414. if (!display)
  1415. return -ENODEV;
  1416. if (*ppos)
  1417. return 0;
  1418. if (!display->panel) {
  1419. DSI_ERR("invalid panel data\n");
  1420. return -EINVAL;
  1421. }
  1422. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1423. if (ZERO_OR_NULL_PTR(buf))
  1424. return -ENOMEM;
  1425. esd_config = &display->panel->esd_config;
  1426. if (!esd_config) {
  1427. DSI_ERR("Invalid panel esd config\n");
  1428. rc = -EINVAL;
  1429. goto error;
  1430. }
  1431. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1432. if (!esd_config->esd_enabled) {
  1433. rc = snprintf(buf, len, "ESD feature not enabled");
  1434. goto output_mode;
  1435. }
  1436. switch (esd_config->status_mode) {
  1437. case ESD_MODE_REG_READ:
  1438. rc = snprintf(buf, len, "reg_read");
  1439. break;
  1440. case ESD_MODE_PANEL_TE:
  1441. rc = snprintf(buf, len, "te_signal_check");
  1442. break;
  1443. case ESD_MODE_SW_SIM_FAILURE:
  1444. rc = snprintf(buf, len, "esd_sw_sim_failure");
  1445. break;
  1446. case ESD_MODE_SW_SIM_SUCCESS:
  1447. rc = snprintf(buf, len, "esd_sw_sim_success");
  1448. break;
  1449. default:
  1450. rc = snprintf(buf, len, "invalid");
  1451. break;
  1452. }
  1453. output_mode:
  1454. if (!rc) {
  1455. rc = -EINVAL;
  1456. goto error;
  1457. }
  1458. if (copy_to_user(user_buf, buf, len)) {
  1459. rc = -EFAULT;
  1460. goto error;
  1461. }
  1462. *ppos += len;
  1463. error:
  1464. kfree(buf);
  1465. return len;
  1466. }
  1467. static ssize_t debugfs_update_cmd_scheduling_params(struct file *file,
  1468. const char __user *user_buf,
  1469. size_t user_len,
  1470. loff_t *ppos)
  1471. {
  1472. struct dsi_display *display = file->private_data;
  1473. struct dsi_display_ctrl *display_ctrl;
  1474. char *buf;
  1475. int rc = 0;
  1476. u32 line = 0, window = 0;
  1477. size_t len;
  1478. int i;
  1479. if (!display)
  1480. return -ENODEV;
  1481. if (*ppos)
  1482. return 0;
  1483. buf = kzalloc(256, GFP_KERNEL);
  1484. if (ZERO_OR_NULL_PTR(buf))
  1485. return -ENOMEM;
  1486. len = min_t(size_t, user_len, 255);
  1487. if (copy_from_user(buf, user_buf, len)) {
  1488. rc = -EINVAL;
  1489. goto error;
  1490. }
  1491. buf[len] = '\0'; /* terminate the string */
  1492. if (sscanf(buf, "%d %d", &line, &window) != 2)
  1493. return -EFAULT;
  1494. display_for_each_ctrl(i, display) {
  1495. struct dsi_ctrl *ctrl;
  1496. display_ctrl = &display->ctrl[i];
  1497. if (!display_ctrl->ctrl)
  1498. continue;
  1499. ctrl = display_ctrl->ctrl;
  1500. ctrl->host_config.common_config.dma_sched_line = line;
  1501. ctrl->host_config.common_config.dma_sched_window = window;
  1502. }
  1503. rc = len;
  1504. error:
  1505. kfree(buf);
  1506. return rc;
  1507. }
  1508. static ssize_t debugfs_read_cmd_scheduling_params(struct file *file,
  1509. char __user *user_buf,
  1510. size_t user_len,
  1511. loff_t *ppos)
  1512. {
  1513. struct dsi_display *display = file->private_data;
  1514. struct dsi_display_ctrl *m_ctrl;
  1515. struct dsi_ctrl *ctrl;
  1516. char *buf;
  1517. u32 len = 0;
  1518. int rc = 0;
  1519. size_t max_len = min_t(size_t, user_len, SZ_4K);
  1520. if (!display)
  1521. return -ENODEV;
  1522. if (*ppos)
  1523. return 0;
  1524. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1525. ctrl = m_ctrl->ctrl;
  1526. buf = kzalloc(max_len, GFP_KERNEL);
  1527. if (ZERO_OR_NULL_PTR(buf))
  1528. return -ENOMEM;
  1529. len += scnprintf(buf, max_len, "Schedule command window start: %d\n",
  1530. ctrl->host_config.common_config.dma_sched_line);
  1531. len += scnprintf((buf + len), max_len - len,
  1532. "Schedule command window width: %d\n",
  1533. ctrl->host_config.common_config.dma_sched_window);
  1534. if (len > max_len)
  1535. len = max_len;
  1536. if (copy_to_user(user_buf, buf, len)) {
  1537. rc = -EFAULT;
  1538. goto error;
  1539. }
  1540. *ppos += len;
  1541. error:
  1542. kfree(buf);
  1543. return len;
  1544. }
  1545. static const struct file_operations dump_info_fops = {
  1546. .open = simple_open,
  1547. .read = debugfs_dump_info_read,
  1548. };
  1549. static const struct file_operations misr_data_fops = {
  1550. .open = simple_open,
  1551. .read = debugfs_misr_read,
  1552. .write = debugfs_misr_setup,
  1553. };
  1554. static const struct file_operations esd_trigger_fops = {
  1555. .open = simple_open,
  1556. .write = debugfs_esd_trigger_check,
  1557. };
  1558. static const struct file_operations esd_check_mode_fops = {
  1559. .open = simple_open,
  1560. .write = debugfs_alter_esd_check_mode,
  1561. .read = debugfs_read_esd_check_mode,
  1562. };
  1563. static const struct file_operations dsi_command_scheduling_fops = {
  1564. .open = simple_open,
  1565. .write = debugfs_update_cmd_scheduling_params,
  1566. .read = debugfs_read_cmd_scheduling_params,
  1567. };
  1568. static int dsi_display_debugfs_init(struct dsi_display *display)
  1569. {
  1570. int rc = 0;
  1571. struct dentry *dir, *dump_file, *misr_data;
  1572. char name[MAX_NAME_SIZE];
  1573. char panel_name[SEC_PANEL_NAME_MAX_LEN];
  1574. char secondary_panel_str[] = "_secondary";
  1575. int i;
  1576. strlcpy(panel_name, display->name, SEC_PANEL_NAME_MAX_LEN);
  1577. if (strcmp(display->display_type, "secondary") == 0)
  1578. strlcat(panel_name, secondary_panel_str, SEC_PANEL_NAME_MAX_LEN);
  1579. dir = debugfs_create_dir(panel_name, NULL);
  1580. if (IS_ERR_OR_NULL(dir)) {
  1581. rc = PTR_ERR(dir);
  1582. DSI_ERR("[%s] debugfs create dir failed, rc = %d\n",
  1583. display->name, rc);
  1584. goto error;
  1585. }
  1586. dump_file = debugfs_create_file("dump_info",
  1587. 0400,
  1588. dir,
  1589. display,
  1590. &dump_info_fops);
  1591. if (IS_ERR_OR_NULL(dump_file)) {
  1592. rc = PTR_ERR(dump_file);
  1593. DSI_ERR("[%s] debugfs create dump info file failed, rc=%d\n",
  1594. display->name, rc);
  1595. goto error_remove_dir;
  1596. }
  1597. dump_file = debugfs_create_file("esd_trigger",
  1598. 0644,
  1599. dir,
  1600. display,
  1601. &esd_trigger_fops);
  1602. if (IS_ERR_OR_NULL(dump_file)) {
  1603. rc = PTR_ERR(dump_file);
  1604. DSI_ERR("[%s] debugfs for esd trigger file failed, rc=%d\n",
  1605. display->name, rc);
  1606. goto error_remove_dir;
  1607. }
  1608. dump_file = debugfs_create_file("esd_check_mode",
  1609. 0644,
  1610. dir,
  1611. display,
  1612. &esd_check_mode_fops);
  1613. if (IS_ERR_OR_NULL(dump_file)) {
  1614. rc = PTR_ERR(dump_file);
  1615. DSI_ERR("[%s] debugfs for esd check mode failed, rc=%d\n",
  1616. display->name, rc);
  1617. goto error_remove_dir;
  1618. }
  1619. dump_file = debugfs_create_file("cmd_sched_params",
  1620. 0644,
  1621. dir,
  1622. display,
  1623. &dsi_command_scheduling_fops);
  1624. if (IS_ERR_OR_NULL(dump_file)) {
  1625. rc = PTR_ERR(dump_file);
  1626. DSI_ERR("[%s] debugfs for cmd scheduling file failed, rc=%d\n",
  1627. display->name, rc);
  1628. goto error_remove_dir;
  1629. }
  1630. misr_data = debugfs_create_file("misr_data",
  1631. 0600,
  1632. dir,
  1633. display,
  1634. &misr_data_fops);
  1635. if (IS_ERR_OR_NULL(misr_data)) {
  1636. rc = PTR_ERR(misr_data);
  1637. DSI_ERR("[%s] debugfs create misr datafile failed, rc=%d\n",
  1638. display->name, rc);
  1639. goto error_remove_dir;
  1640. }
  1641. display_for_each_ctrl(i, display) {
  1642. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1643. if (!phy || !phy->name)
  1644. continue;
  1645. snprintf(name, ARRAY_SIZE(name),
  1646. "%s_allow_phy_power_off", phy->name);
  1647. dump_file = debugfs_create_bool(name, 0600, dir,
  1648. &phy->allow_phy_power_off);
  1649. if (IS_ERR_OR_NULL(dump_file)) {
  1650. rc = PTR_ERR(dump_file);
  1651. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1652. display->name, name, rc);
  1653. goto error_remove_dir;
  1654. }
  1655. snprintf(name, ARRAY_SIZE(name),
  1656. "%s_regulator_min_datarate_bps", phy->name);
  1657. debugfs_create_u32(name, 0600, dir, &phy->regulator_min_datarate_bps);
  1658. }
  1659. if (!debugfs_create_bool("ulps_feature_enable", 0600, dir,
  1660. &display->panel->ulps_feature_enabled)) {
  1661. DSI_ERR("[%s] debugfs create ulps feature enable file failed\n",
  1662. display->name);
  1663. goto error_remove_dir;
  1664. }
  1665. if (!debugfs_create_bool("ulps_suspend_feature_enable", 0600, dir,
  1666. &display->panel->ulps_suspend_enabled)) {
  1667. DSI_ERR("[%s] debugfs create ulps-suspend feature enable file failed\n",
  1668. display->name);
  1669. goto error_remove_dir;
  1670. }
  1671. if (!debugfs_create_bool("ulps_status", 0400, dir,
  1672. &display->ulps_enabled)) {
  1673. DSI_ERR("[%s] debugfs create ulps status file failed\n",
  1674. display->name);
  1675. goto error_remove_dir;
  1676. }
  1677. debugfs_create_u32("clk_gating_config", 0600, dir, &display->clk_gating_config);
  1678. display->root = dir;
  1679. dsi_parser_dbg_init(display->parser, dir);
  1680. return rc;
  1681. error_remove_dir:
  1682. debugfs_remove(dir);
  1683. error:
  1684. return rc;
  1685. }
  1686. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1687. {
  1688. debugfs_remove_recursive(display->root);
  1689. return 0;
  1690. }
  1691. #else
  1692. static int dsi_display_debugfs_init(struct dsi_display *display)
  1693. {
  1694. return 0;
  1695. }
  1696. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1697. {
  1698. return 0;
  1699. }
  1700. #endif /* CONFIG_DEBUG_FS */
  1701. static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
  1702. struct dsi_display_mode *mode)
  1703. {
  1704. struct dsi_host_common_cfg *host = &display->panel->host_config;
  1705. bool is_split_link = host->split_link.split_link_enabled;
  1706. u32 sublinks_count = host->split_link.num_sublinks;
  1707. if (is_split_link && sublinks_count > 1) {
  1708. mode->timing.h_active /= sublinks_count;
  1709. mode->timing.h_front_porch /= sublinks_count;
  1710. mode->timing.h_sync_width /= sublinks_count;
  1711. mode->timing.h_back_porch /= sublinks_count;
  1712. mode->timing.h_skew /= sublinks_count;
  1713. mode->pixel_clk_khz /= sublinks_count;
  1714. } else {
  1715. if (mode->priv_info->dsc_enabled)
  1716. mode->priv_info->dsc.config.pic_width =
  1717. mode->timing.h_active;
  1718. mode->timing.h_active /= display->ctrl_count;
  1719. mode->timing.h_front_porch /= display->ctrl_count;
  1720. mode->timing.h_sync_width /= display->ctrl_count;
  1721. mode->timing.h_back_porch /= display->ctrl_count;
  1722. mode->timing.h_skew /= display->ctrl_count;
  1723. mode->pixel_clk_khz /= display->ctrl_count;
  1724. }
  1725. }
  1726. static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
  1727. bool enable)
  1728. {
  1729. /* TODO: make checks based on cont. splash */
  1730. DSI_DEBUG("checking ulps req validity\n");
  1731. if (atomic_read(&display->panel->esd_recovery_pending)) {
  1732. DSI_DEBUG("%s: ESD recovery sequence underway\n", __func__);
  1733. return false;
  1734. }
  1735. if (!dsi_panel_ulps_feature_enabled(display->panel) &&
  1736. !display->panel->ulps_suspend_enabled) {
  1737. DSI_DEBUG("%s: ULPS feature is not enabled\n", __func__);
  1738. return false;
  1739. }
  1740. if (!dsi_panel_initialized(display->panel) &&
  1741. !display->panel->ulps_suspend_enabled) {
  1742. DSI_DEBUG("%s: panel not yet initialized\n", __func__);
  1743. return false;
  1744. }
  1745. if (enable && display->ulps_enabled) {
  1746. DSI_DEBUG("ULPS already enabled\n");
  1747. return false;
  1748. } else if (!enable && !display->ulps_enabled) {
  1749. DSI_DEBUG("ULPS already disabled\n");
  1750. return false;
  1751. }
  1752. /*
  1753. * No need to enter ULPS when transitioning from splash screen to
  1754. * boot animation or trusted vm environments since it is expected
  1755. * that the clocks would be turned right back on.
  1756. */
  1757. if (enable && is_skip_op_required(display))
  1758. return false;
  1759. return true;
  1760. }
  1761. /**
  1762. * dsi_display_set_ulps() - set ULPS state for DSI lanes.
  1763. * @dsi_display: DSI display handle.
  1764. * @enable: enable/disable ULPS.
  1765. *
  1766. * ULPS can be enabled/disabled after DSI host engine is turned on.
  1767. *
  1768. * Return: error code.
  1769. */
  1770. static int dsi_display_set_ulps(struct dsi_display *display, bool enable)
  1771. {
  1772. int rc = 0;
  1773. int i = 0;
  1774. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1775. if (!display) {
  1776. DSI_ERR("Invalid params\n");
  1777. return -EINVAL;
  1778. }
  1779. if (!dsi_display_is_ulps_req_valid(display, enable)) {
  1780. DSI_DEBUG("%s: skipping ULPS config, enable=%d\n",
  1781. __func__, enable);
  1782. return 0;
  1783. }
  1784. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1785. /*
  1786. * ULPS entry-exit can be either through the DSI controller or
  1787. * the DSI PHY depending on hardware variation. For some chipsets,
  1788. * both controller version and phy version ulps entry-exit ops can
  1789. * be present. To handle such cases, send ulps request through PHY,
  1790. * if ulps request is handled in PHY, then no need to send request
  1791. * through controller.
  1792. */
  1793. rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable,
  1794. display->clamp_enabled);
  1795. if (rc == DSI_PHY_ULPS_ERROR) {
  1796. DSI_ERR("Ulps PHY state change(%d) failed\n", enable);
  1797. return -EINVAL;
  1798. }
  1799. else if (rc == DSI_PHY_ULPS_HANDLED) {
  1800. display_for_each_ctrl(i, display) {
  1801. ctrl = &display->ctrl[i];
  1802. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1803. continue;
  1804. rc = dsi_phy_set_ulps(ctrl->phy, &display->config,
  1805. enable, display->clamp_enabled);
  1806. if (rc == DSI_PHY_ULPS_ERROR) {
  1807. DSI_ERR("Ulps PHY state change(%d) failed\n",
  1808. enable);
  1809. return -EINVAL;
  1810. }
  1811. }
  1812. }
  1813. else if (rc == DSI_PHY_ULPS_NOT_HANDLED) {
  1814. rc = dsi_ctrl_set_ulps(m_ctrl->ctrl, enable);
  1815. if (rc) {
  1816. DSI_ERR("Ulps controller state change(%d) failed\n",
  1817. enable);
  1818. return rc;
  1819. }
  1820. display_for_each_ctrl(i, display) {
  1821. ctrl = &display->ctrl[i];
  1822. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1823. continue;
  1824. rc = dsi_ctrl_set_ulps(ctrl->ctrl, enable);
  1825. if (rc) {
  1826. DSI_ERR("Ulps controller state change(%d) failed\n",
  1827. enable);
  1828. return rc;
  1829. }
  1830. }
  1831. }
  1832. display->ulps_enabled = enable;
  1833. return 0;
  1834. }
  1835. /**
  1836. * dsi_display_set_clamp() - set clamp state for DSI IO.
  1837. * @dsi_display: DSI display handle.
  1838. * @enable: enable/disable clamping.
  1839. *
  1840. * Return: error code.
  1841. */
  1842. static int dsi_display_set_clamp(struct dsi_display *display, bool enable)
  1843. {
  1844. int rc = 0;
  1845. int i = 0;
  1846. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1847. bool ulps_enabled = false;
  1848. if (!display) {
  1849. DSI_ERR("Invalid params\n");
  1850. return -EINVAL;
  1851. }
  1852. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1853. ulps_enabled = display->ulps_enabled;
  1854. /*
  1855. * Clamp control can be either through the DSI controller or
  1856. * the DSI PHY depending on hardware variation
  1857. */
  1858. rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);
  1859. if (rc) {
  1860. DSI_ERR("DSI ctrl clamp state change(%d) failed\n", enable);
  1861. return rc;
  1862. }
  1863. rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);
  1864. if (rc) {
  1865. DSI_ERR("DSI phy clamp state change(%d) failed\n", enable);
  1866. return rc;
  1867. }
  1868. display_for_each_ctrl(i, display) {
  1869. ctrl = &display->ctrl[i];
  1870. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1871. continue;
  1872. rc = dsi_ctrl_set_clamp_state(ctrl->ctrl, enable, ulps_enabled);
  1873. if (rc) {
  1874. DSI_ERR("DSI Clamp state change(%d) failed\n", enable);
  1875. return rc;
  1876. }
  1877. rc = dsi_phy_set_clamp_state(ctrl->phy, enable);
  1878. if (rc) {
  1879. DSI_ERR("DSI phy clamp state change(%d) failed\n",
  1880. enable);
  1881. return rc;
  1882. }
  1883. DSI_DEBUG("Clamps %s for ctrl%d\n",
  1884. enable ? "enabled" : "disabled", i);
  1885. }
  1886. display->clamp_enabled = enable;
  1887. return 0;
  1888. }
  1889. /**
  1890. * dsi_display_setup_ctrl() - setup DSI controller.
  1891. * @dsi_display: DSI display handle.
  1892. *
  1893. * Return: error code.
  1894. */
  1895. static int dsi_display_ctrl_setup(struct dsi_display *display)
  1896. {
  1897. int rc = 0;
  1898. int i = 0;
  1899. struct dsi_display_ctrl *ctrl, *m_ctrl;
  1900. if (!display) {
  1901. DSI_ERR("Invalid params\n");
  1902. return -EINVAL;
  1903. }
  1904. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1905. rc = dsi_ctrl_setup(m_ctrl->ctrl);
  1906. if (rc) {
  1907. DSI_ERR("DSI controller setup failed\n");
  1908. return rc;
  1909. }
  1910. display_for_each_ctrl(i, display) {
  1911. ctrl = &display->ctrl[i];
  1912. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1913. continue;
  1914. rc = dsi_ctrl_setup(ctrl->ctrl);
  1915. if (rc) {
  1916. DSI_ERR("DSI controller setup failed\n");
  1917. return rc;
  1918. }
  1919. }
  1920. return 0;
  1921. }
  1922. static int dsi_display_phy_enable(struct dsi_display *display);
  1923. /**
  1924. * dsi_display_phy_idle_on() - enable DSI PHY while coming out of idle screen.
  1925. * @dsi_display: DSI display handle.
  1926. * @mmss_clamp: True if clamp is enabled.
  1927. *
  1928. * Return: error code.
  1929. */
  1930. static int dsi_display_phy_idle_on(struct dsi_display *display,
  1931. bool mmss_clamp)
  1932. {
  1933. int rc = 0;
  1934. int i = 0;
  1935. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1936. if (!display) {
  1937. DSI_ERR("Invalid params\n");
  1938. return -EINVAL;
  1939. }
  1940. if (mmss_clamp && !display->phy_idle_power_off) {
  1941. dsi_display_phy_enable(display);
  1942. return 0;
  1943. }
  1944. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1945. rc = dsi_phy_idle_ctrl(m_ctrl->phy, true);
  1946. if (rc) {
  1947. DSI_ERR("DSI controller setup failed\n");
  1948. return rc;
  1949. }
  1950. display_for_each_ctrl(i, display) {
  1951. ctrl = &display->ctrl[i];
  1952. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1953. continue;
  1954. rc = dsi_phy_idle_ctrl(ctrl->phy, true);
  1955. if (rc) {
  1956. DSI_ERR("DSI controller setup failed\n");
  1957. return rc;
  1958. }
  1959. }
  1960. display->phy_idle_power_off = false;
  1961. return 0;
  1962. }
  1963. /**
  1964. * dsi_display_phy_idle_off() - disable DSI PHY while going to idle screen.
  1965. * @dsi_display: DSI display handle.
  1966. *
  1967. * Return: error code.
  1968. */
  1969. static int dsi_display_phy_idle_off(struct dsi_display *display)
  1970. {
  1971. int rc = 0;
  1972. int i = 0;
  1973. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1974. if (!display) {
  1975. DSI_ERR("Invalid params\n");
  1976. return -EINVAL;
  1977. }
  1978. display_for_each_ctrl(i, display) {
  1979. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1980. if (!phy)
  1981. continue;
  1982. if (!phy->allow_phy_power_off) {
  1983. DSI_DEBUG("phy doesn't support this feature\n");
  1984. return 0;
  1985. }
  1986. }
  1987. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1988. rc = dsi_phy_idle_ctrl(m_ctrl->phy, false);
  1989. if (rc) {
  1990. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  1991. display->name, rc);
  1992. return rc;
  1993. }
  1994. display_for_each_ctrl(i, display) {
  1995. ctrl = &display->ctrl[i];
  1996. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1997. continue;
  1998. rc = dsi_phy_idle_ctrl(ctrl->phy, false);
  1999. if (rc) {
  2000. DSI_ERR("DSI controller setup failed\n");
  2001. return rc;
  2002. }
  2003. }
  2004. display->phy_idle_power_off = true;
  2005. return 0;
  2006. }
  2007. void dsi_display_enable_event(struct drm_connector *connector,
  2008. struct dsi_display *display,
  2009. uint32_t event_idx, struct dsi_event_cb_info *event_info,
  2010. bool enable)
  2011. {
  2012. uint32_t irq_status_idx = DSI_STATUS_INTERRUPT_COUNT;
  2013. int i;
  2014. if (!display) {
  2015. DSI_ERR("invalid display\n");
  2016. return;
  2017. }
  2018. if (event_info)
  2019. event_info->event_idx = event_idx;
  2020. switch (event_idx) {
  2021. case SDE_CONN_EVENT_VID_DONE:
  2022. irq_status_idx = DSI_SINT_VIDEO_MODE_FRAME_DONE;
  2023. break;
  2024. case SDE_CONN_EVENT_CMD_DONE:
  2025. irq_status_idx = DSI_SINT_CMD_FRAME_DONE;
  2026. break;
  2027. case SDE_CONN_EVENT_VID_FIFO_OVERFLOW:
  2028. case SDE_CONN_EVENT_CMD_FIFO_UNDERFLOW:
  2029. if (event_info) {
  2030. display_for_each_ctrl(i, display)
  2031. display->ctrl[i].ctrl->recovery_cb =
  2032. *event_info;
  2033. }
  2034. break;
  2035. case SDE_CONN_EVENT_PANEL_ID:
  2036. if (event_info)
  2037. display_for_each_ctrl(i, display)
  2038. display->ctrl[i].ctrl->panel_id_cb
  2039. = *event_info;
  2040. dsi_display_panel_id_notification(display);
  2041. break;
  2042. default:
  2043. /* nothing to do */
  2044. DSI_DEBUG("[%s] unhandled event %d\n", display->name, event_idx);
  2045. return;
  2046. }
  2047. if (enable) {
  2048. display_for_each_ctrl(i, display)
  2049. dsi_ctrl_enable_status_interrupt(
  2050. display->ctrl[i].ctrl, irq_status_idx,
  2051. event_info);
  2052. } else {
  2053. display_for_each_ctrl(i, display)
  2054. dsi_ctrl_disable_status_interrupt(
  2055. display->ctrl[i].ctrl, irq_status_idx);
  2056. }
  2057. }
  2058. static int dsi_display_ctrl_power_on(struct dsi_display *display)
  2059. {
  2060. int rc = 0;
  2061. int i;
  2062. struct dsi_display_ctrl *ctrl;
  2063. /* Sequence does not matter for split dsi usecases */
  2064. display_for_each_ctrl(i, display) {
  2065. ctrl = &display->ctrl[i];
  2066. if (!ctrl->ctrl)
  2067. continue;
  2068. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2069. DSI_CTRL_POWER_VREG_ON);
  2070. if (rc) {
  2071. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2072. ctrl->ctrl->name, rc);
  2073. goto error;
  2074. }
  2075. }
  2076. return rc;
  2077. error:
  2078. for (i = i - 1; i >= 0; i--) {
  2079. ctrl = &display->ctrl[i];
  2080. if (!ctrl->ctrl)
  2081. continue;
  2082. (void)dsi_ctrl_set_power_state(ctrl->ctrl,
  2083. DSI_CTRL_POWER_VREG_OFF);
  2084. }
  2085. return rc;
  2086. }
  2087. static int dsi_display_ctrl_power_off(struct dsi_display *display)
  2088. {
  2089. int rc = 0;
  2090. int i;
  2091. struct dsi_display_ctrl *ctrl;
  2092. /* Sequence does not matter for split dsi usecases */
  2093. display_for_each_ctrl(i, display) {
  2094. ctrl = &display->ctrl[i];
  2095. if (!ctrl->ctrl)
  2096. continue;
  2097. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2098. DSI_CTRL_POWER_VREG_OFF);
  2099. if (rc) {
  2100. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2101. ctrl->ctrl->name, rc);
  2102. goto error;
  2103. }
  2104. }
  2105. error:
  2106. return rc;
  2107. }
  2108. static void dsi_display_parse_cmdline_topology(struct dsi_display *display,
  2109. unsigned int display_type)
  2110. {
  2111. char *boot_str = NULL;
  2112. char *str = NULL;
  2113. char *sw_te = NULL;
  2114. unsigned long cmdline_topology = NO_OVERRIDE;
  2115. unsigned long cmdline_timing = NO_OVERRIDE;
  2116. if (display_type >= MAX_DSI_ACTIVE_DISPLAY) {
  2117. DSI_ERR("display_type=%d not supported\n", display_type);
  2118. goto end;
  2119. }
  2120. if (display_type == DSI_PRIMARY)
  2121. boot_str = dsi_display_primary;
  2122. else
  2123. boot_str = dsi_display_secondary;
  2124. sw_te = strnstr(boot_str, ":sim-swte", strlen(boot_str));
  2125. if (sw_te)
  2126. display->sw_te_using_wd = true;
  2127. str = strnstr(boot_str, ":config", strlen(boot_str));
  2128. if (str) {
  2129. if (sscanf(str, ":config%lu", &cmdline_topology) != 1) {
  2130. DSI_ERR("invalid config index override: %s\n",
  2131. boot_str);
  2132. goto end;
  2133. }
  2134. }
  2135. str = strnstr(boot_str, ":timing", strlen(boot_str));
  2136. if (str) {
  2137. if (sscanf(str, ":timing%lu", &cmdline_timing) != 1) {
  2138. DSI_ERR("invalid timing index override: %s\n",
  2139. boot_str);
  2140. cmdline_topology = NO_OVERRIDE;
  2141. goto end;
  2142. }
  2143. }
  2144. DSI_DEBUG("successfully parsed command line topology and timing\n");
  2145. end:
  2146. display->cmdline_topology = cmdline_topology;
  2147. display->cmdline_timing = cmdline_timing;
  2148. }
  2149. /**
  2150. * dsi_display_parse_boot_display_selection()- Parse DSI boot display name
  2151. *
  2152. * Return: returns error status
  2153. */
  2154. static int dsi_display_parse_boot_display_selection(void)
  2155. {
  2156. char *pos = NULL;
  2157. char disp_buf[MAX_CMDLINE_PARAM_LEN] = {'\0'};
  2158. int i, j;
  2159. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  2160. strlcpy(disp_buf, boot_displays[i].boot_param,
  2161. MAX_CMDLINE_PARAM_LEN);
  2162. pos = strnstr(disp_buf, ":", MAX_CMDLINE_PARAM_LEN);
  2163. /* Use ':' as a delimiter to retrieve the display name */
  2164. if (!pos) {
  2165. DSI_DEBUG("display name[%s]is not valid\n", disp_buf);
  2166. continue;
  2167. }
  2168. for (j = 0; (disp_buf + j) < pos; j++)
  2169. boot_displays[i].name[j] = *(disp_buf + j);
  2170. boot_displays[i].name[j] = '\0';
  2171. boot_displays[i].boot_disp_en = true;
  2172. }
  2173. return 0;
  2174. }
  2175. static int dsi_display_phy_power_on(struct dsi_display *display)
  2176. {
  2177. int rc = 0;
  2178. int i;
  2179. struct dsi_display_ctrl *ctrl;
  2180. /* Sequence does not matter for split dsi usecases */
  2181. display_for_each_ctrl(i, display) {
  2182. ctrl = &display->ctrl[i];
  2183. if (!ctrl->ctrl)
  2184. continue;
  2185. rc = dsi_phy_set_power_state(ctrl->phy, true);
  2186. if (rc) {
  2187. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2188. ctrl->phy->name, rc);
  2189. goto error;
  2190. }
  2191. }
  2192. return rc;
  2193. error:
  2194. for (i = i - 1; i >= 0; i--) {
  2195. ctrl = &display->ctrl[i];
  2196. if (!ctrl->phy)
  2197. continue;
  2198. (void)dsi_phy_set_power_state(ctrl->phy, false);
  2199. }
  2200. return rc;
  2201. }
  2202. static int dsi_display_phy_power_off(struct dsi_display *display)
  2203. {
  2204. int rc = 0;
  2205. int i;
  2206. struct dsi_display_ctrl *ctrl;
  2207. /* Sequence does not matter for split dsi usecases */
  2208. display_for_each_ctrl(i, display) {
  2209. ctrl = &display->ctrl[i];
  2210. if (!ctrl->phy)
  2211. continue;
  2212. rc = dsi_phy_set_power_state(ctrl->phy, false);
  2213. if (rc) {
  2214. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2215. ctrl->ctrl->name, rc);
  2216. goto error;
  2217. }
  2218. }
  2219. error:
  2220. return rc;
  2221. }
  2222. static int dsi_display_set_clk_src(struct dsi_display *display, bool set_xo)
  2223. {
  2224. int rc = 0;
  2225. int i;
  2226. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2227. struct dsi_ctrl_clk_info *info;
  2228. if (display->trusted_vm_env)
  2229. return 0;
  2230. /*
  2231. * In case of split DSI usecases, the clock for master controller should
  2232. * be enabled before the other controller. Master controller in the
  2233. * clock context refers to the controller that sources the clock. While turning off the
  2234. * clocks, the source is set to xo.
  2235. */
  2236. m_ctrl = &display->ctrl[display->clk_master_idx];
  2237. info = &m_ctrl->ctrl->clk_info;
  2238. if (!set_xo)
  2239. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &display->clock_info.pll_clks);
  2240. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2241. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &info->xo_clk);
  2242. if (rc) {
  2243. DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n", display->name, rc);
  2244. return rc;
  2245. }
  2246. /* Set source for the rest of the controllers */
  2247. display_for_each_ctrl(i, display) {
  2248. ctrl = &display->ctrl[i];
  2249. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2250. continue;
  2251. info = &ctrl->ctrl->clk_info;
  2252. if (!set_xo)
  2253. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &display->clock_info.pll_clks);
  2254. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2255. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &info->xo_clk);
  2256. if (rc) {
  2257. DSI_ERR("[%s] failed to set source clocks, rc=%d\n", display->name, rc);
  2258. return rc;
  2259. }
  2260. }
  2261. return 0;
  2262. }
  2263. int dsi_display_phy_pll_toggle(void *priv, bool prepare)
  2264. {
  2265. int rc = 0;
  2266. struct dsi_display *display = priv;
  2267. struct dsi_display_ctrl *m_ctrl;
  2268. if (!display) {
  2269. DSI_ERR("invalid arguments\n");
  2270. return -EINVAL;
  2271. }
  2272. rc = dsi_display_set_clk_src(display, !prepare);
  2273. m_ctrl = &display->ctrl[display->clk_master_idx];
  2274. if (!m_ctrl->phy) {
  2275. DSI_ERR("[%s] PHY not found\n", display->name);
  2276. return -EINVAL;
  2277. }
  2278. rc = dsi_phy_pll_toggle(m_ctrl->phy, prepare);
  2279. return rc;
  2280. }
  2281. int dsi_display_phy_configure(void *priv, bool commit)
  2282. {
  2283. int rc = 0;
  2284. struct dsi_display *display = priv;
  2285. struct dsi_display_ctrl *m_ctrl;
  2286. struct dsi_pll_resource *pll_res;
  2287. struct dsi_ctrl *ctrl;
  2288. if (!display) {
  2289. DSI_ERR("invalid arguments\n");
  2290. return -EINVAL;
  2291. }
  2292. m_ctrl = &display->ctrl[display->clk_master_idx];
  2293. if ((!m_ctrl->phy) || (!m_ctrl->ctrl)) {
  2294. DSI_ERR("[%s] PHY not found\n", display->name);
  2295. return -EINVAL;
  2296. }
  2297. pll_res = m_ctrl->phy->pll;
  2298. if (!pll_res) {
  2299. DSI_ERR("[%s] PLL res not found\n", display->name);
  2300. return -EINVAL;
  2301. }
  2302. ctrl = m_ctrl->ctrl;
  2303. pll_res->byteclk_rate = ctrl->clk_freq.byte_clk_rate;
  2304. pll_res->pclk_rate = ctrl->clk_freq.pix_clk_rate;
  2305. rc = dsi_phy_configure(m_ctrl->phy, commit);
  2306. return rc;
  2307. }
  2308. static int dsi_display_phy_reset_config(struct dsi_display *display,
  2309. bool enable)
  2310. {
  2311. int rc = 0;
  2312. int i;
  2313. struct dsi_display_ctrl *ctrl;
  2314. display_for_each_ctrl(i, display) {
  2315. ctrl = &display->ctrl[i];
  2316. rc = dsi_ctrl_phy_reset_config(ctrl->ctrl, enable);
  2317. if (rc) {
  2318. DSI_ERR("[%s] failed to %s phy reset, rc=%d\n",
  2319. display->name, enable ? "mask" : "unmask", rc);
  2320. return rc;
  2321. }
  2322. }
  2323. return 0;
  2324. }
  2325. static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
  2326. {
  2327. struct dsi_display_ctrl *ctrl;
  2328. int i;
  2329. if (!display)
  2330. return;
  2331. display_for_each_ctrl(i, display) {
  2332. ctrl = &display->ctrl[i];
  2333. dsi_phy_toggle_resync_fifo(ctrl->phy);
  2334. }
  2335. /*
  2336. * After retime buffer synchronization we need to turn of clk_en_sel
  2337. * bit on each phy. Avoid this for Cphy.
  2338. */
  2339. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY)
  2340. return;
  2341. display_for_each_ctrl(i, display) {
  2342. ctrl = &display->ctrl[i];
  2343. dsi_phy_reset_clk_en_sel(ctrl->phy);
  2344. }
  2345. }
  2346. static int dsi_display_ctrl_update(struct dsi_display *display)
  2347. {
  2348. int rc = 0;
  2349. int i;
  2350. struct dsi_display_ctrl *ctrl;
  2351. display_for_each_ctrl(i, display) {
  2352. ctrl = &display->ctrl[i];
  2353. rc = dsi_ctrl_host_timing_update(ctrl->ctrl);
  2354. if (rc) {
  2355. DSI_ERR("[%s] failed to update host_%d, rc=%d\n",
  2356. display->name, i, rc);
  2357. goto error_host_deinit;
  2358. }
  2359. }
  2360. return 0;
  2361. error_host_deinit:
  2362. for (i = i - 1; i >= 0; i--) {
  2363. ctrl = &display->ctrl[i];
  2364. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2365. }
  2366. return rc;
  2367. }
  2368. static int dsi_display_ctrl_init(struct dsi_display *display)
  2369. {
  2370. int rc = 0;
  2371. int i;
  2372. struct dsi_display_ctrl *ctrl;
  2373. bool skip_op = is_skip_op_required(display);
  2374. /* when ULPS suspend feature is enabled, we will keep the lanes in
  2375. * ULPS during suspend state and clamp DSI phy. Hence while resuming
  2376. * we will programe DSI controller as part of core clock enable.
  2377. * After that we should not re-configure DSI controller again here for
  2378. * usecases where we are resuming from ulps suspend as it might put
  2379. * the HW in bad state.
  2380. */
  2381. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  2382. display_for_each_ctrl(i, display) {
  2383. ctrl = &display->ctrl[i];
  2384. rc = dsi_ctrl_host_init(ctrl->ctrl, skip_op);
  2385. if (rc) {
  2386. DSI_ERR(
  2387. "[%s] failed to init host_%d, skip_op=%d, rc=%d\n",
  2388. display->name, i, skip_op, rc);
  2389. goto error_host_deinit;
  2390. }
  2391. }
  2392. } else {
  2393. display_for_each_ctrl(i, display) {
  2394. ctrl = &display->ctrl[i];
  2395. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2396. DSI_CTRL_OP_HOST_INIT,
  2397. true);
  2398. if (rc)
  2399. DSI_DEBUG("host init update failed rc=%d\n",
  2400. rc);
  2401. }
  2402. }
  2403. return rc;
  2404. error_host_deinit:
  2405. for (i = i - 1; i >= 0; i--) {
  2406. ctrl = &display->ctrl[i];
  2407. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2408. }
  2409. return rc;
  2410. }
  2411. static int dsi_display_ctrl_deinit(struct dsi_display *display)
  2412. {
  2413. int rc = 0;
  2414. int i;
  2415. struct dsi_display_ctrl *ctrl;
  2416. display_for_each_ctrl(i, display) {
  2417. ctrl = &display->ctrl[i];
  2418. rc = dsi_ctrl_host_deinit(ctrl->ctrl);
  2419. if (rc) {
  2420. DSI_ERR("[%s] failed to deinit host_%d, rc=%d\n",
  2421. display->name, i, rc);
  2422. }
  2423. }
  2424. return rc;
  2425. }
  2426. static int dsi_display_ctrl_host_enable(struct dsi_display *display)
  2427. {
  2428. int rc = 0;
  2429. int i;
  2430. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2431. bool skip_op = is_skip_op_required(display);
  2432. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2433. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2434. DSI_CTRL_ENGINE_ON, skip_op);
  2435. if (rc) {
  2436. DSI_ERR("[%s]enable host engine failed, skip_op:%d rc:%d\n",
  2437. display->name, skip_op, rc);
  2438. goto error;
  2439. }
  2440. display_for_each_ctrl(i, display) {
  2441. ctrl = &display->ctrl[i];
  2442. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2443. continue;
  2444. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2445. DSI_CTRL_ENGINE_ON, skip_op);
  2446. if (rc) {
  2447. DSI_ERR(
  2448. "[%s] enable host engine failed, skip_op:%d rc:%d\n",
  2449. display->name, skip_op, rc);
  2450. goto error_disable_master;
  2451. }
  2452. }
  2453. return rc;
  2454. error_disable_master:
  2455. (void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2456. DSI_CTRL_ENGINE_OFF, skip_op);
  2457. error:
  2458. return rc;
  2459. }
  2460. static int dsi_display_ctrl_host_disable(struct dsi_display *display)
  2461. {
  2462. int rc = 0;
  2463. int i;
  2464. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2465. bool skip_op = is_skip_op_required(display);
  2466. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2467. /*
  2468. * For platforms where ULPS is controlled by DSI controller block,
  2469. * do not disable dsi controller block if lanes are to be
  2470. * kept in ULPS during suspend. So just update the SW state
  2471. * and return early.
  2472. */
  2473. if (display->panel->ulps_suspend_enabled &&
  2474. !m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
  2475. display_for_each_ctrl(i, display) {
  2476. ctrl = &display->ctrl[i];
  2477. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2478. DSI_CTRL_OP_HOST_ENGINE,
  2479. false);
  2480. if (rc)
  2481. DSI_DEBUG("host state update failed %d\n", rc);
  2482. }
  2483. return rc;
  2484. }
  2485. display_for_each_ctrl(i, display) {
  2486. ctrl = &display->ctrl[i];
  2487. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2488. continue;
  2489. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2490. DSI_CTRL_ENGINE_OFF, skip_op);
  2491. if (rc)
  2492. DSI_ERR(
  2493. "[%s] disable host engine failed, skip_op:%d rc:%d\n",
  2494. display->name, skip_op, rc);
  2495. }
  2496. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2497. DSI_CTRL_ENGINE_OFF, skip_op);
  2498. if (rc) {
  2499. DSI_ERR("[%s] disable mhost engine failed, skip_op:%d rc:%d\n",
  2500. display->name, skip_op, rc);
  2501. goto error;
  2502. }
  2503. error:
  2504. return rc;
  2505. }
  2506. static int dsi_display_vid_engine_enable(struct dsi_display *display)
  2507. {
  2508. int rc = 0;
  2509. int i;
  2510. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2511. bool skip_op = is_skip_op_required(display);
  2512. m_ctrl = &display->ctrl[display->video_master_idx];
  2513. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2514. DSI_CTRL_ENGINE_ON, skip_op);
  2515. if (rc) {
  2516. DSI_ERR("[%s] enable mvid engine failed, skip_op:%d rc:%d\n",
  2517. display->name, skip_op, rc);
  2518. goto error;
  2519. }
  2520. display_for_each_ctrl(i, display) {
  2521. ctrl = &display->ctrl[i];
  2522. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2523. continue;
  2524. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2525. DSI_CTRL_ENGINE_ON, skip_op);
  2526. if (rc) {
  2527. DSI_ERR(
  2528. "[%s] enable vid engine failed, skip_op:%d rc:%d\n",
  2529. display->name, skip_op, rc);
  2530. goto error_disable_master;
  2531. }
  2532. }
  2533. return rc;
  2534. error_disable_master:
  2535. (void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2536. DSI_CTRL_ENGINE_OFF, skip_op);
  2537. error:
  2538. return rc;
  2539. }
  2540. static int dsi_display_vid_engine_disable(struct dsi_display *display)
  2541. {
  2542. int rc = 0;
  2543. int i;
  2544. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2545. bool skip_op = is_skip_op_required(display);
  2546. m_ctrl = &display->ctrl[display->video_master_idx];
  2547. display_for_each_ctrl(i, display) {
  2548. ctrl = &display->ctrl[i];
  2549. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2550. continue;
  2551. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2552. DSI_CTRL_ENGINE_OFF, skip_op);
  2553. if (rc)
  2554. DSI_ERR(
  2555. "[%s] disable vid engine failed, skip_op:%d rc:%d\n",
  2556. display->name, skip_op, rc);
  2557. }
  2558. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2559. DSI_CTRL_ENGINE_OFF, skip_op);
  2560. if (rc)
  2561. DSI_ERR("[%s] disable mvid engine failed, skip_op:%d rc:%d\n",
  2562. display->name, skip_op, rc);
  2563. return rc;
  2564. }
  2565. static int dsi_display_phy_enable(struct dsi_display *display)
  2566. {
  2567. int rc = 0;
  2568. int i;
  2569. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2570. enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
  2571. bool skip_op = is_skip_op_required(display);
  2572. m_ctrl = &display->ctrl[display->clk_master_idx];
  2573. if (display->ctrl_count > 1)
  2574. m_src = DSI_PLL_SOURCE_NATIVE;
  2575. rc = dsi_phy_enable(m_ctrl->phy, &display->config,
  2576. m_src, true, skip_op);
  2577. if (rc) {
  2578. DSI_ERR("[%s] failed to enable DSI PHY, skip_op=%d rc=%d\n",
  2579. display->name, skip_op, rc);
  2580. goto error;
  2581. }
  2582. display_for_each_ctrl(i, display) {
  2583. ctrl = &display->ctrl[i];
  2584. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2585. continue;
  2586. rc = dsi_phy_enable(ctrl->phy, &display->config,
  2587. DSI_PLL_SOURCE_NON_NATIVE, true, skip_op);
  2588. if (rc) {
  2589. DSI_ERR(
  2590. "[%s] failed to enable DSI PHY, skip_op: %d rc=%d\n",
  2591. display->name, skip_op, rc);
  2592. goto error_disable_master;
  2593. }
  2594. }
  2595. return rc;
  2596. error_disable_master:
  2597. (void)dsi_phy_disable(m_ctrl->phy, skip_op);
  2598. error:
  2599. return rc;
  2600. }
  2601. static int dsi_display_phy_disable(struct dsi_display *display)
  2602. {
  2603. int rc = 0;
  2604. int i;
  2605. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2606. bool skip_op = is_skip_op_required(display);
  2607. m_ctrl = &display->ctrl[display->clk_master_idx];
  2608. display_for_each_ctrl(i, display) {
  2609. ctrl = &display->ctrl[i];
  2610. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2611. continue;
  2612. rc = dsi_phy_disable(ctrl->phy, skip_op);
  2613. if (rc)
  2614. DSI_ERR(
  2615. "[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2616. display->name, skip_op, rc);
  2617. }
  2618. rc = dsi_phy_disable(m_ctrl->phy, skip_op);
  2619. if (rc)
  2620. DSI_ERR("[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2621. display->name, skip_op, rc);
  2622. return rc;
  2623. }
  2624. static int dsi_display_wake_up(struct dsi_display *display)
  2625. {
  2626. return 0;
  2627. }
  2628. static void dsi_display_mask_overflow(struct dsi_display *display, u32 flags,
  2629. bool enable)
  2630. {
  2631. struct dsi_display_ctrl *ctrl;
  2632. int i;
  2633. if (!(flags & DSI_CTRL_CMD_LAST_COMMAND))
  2634. return;
  2635. display_for_each_ctrl(i, display) {
  2636. ctrl = &display->ctrl[i];
  2637. if (!ctrl)
  2638. continue;
  2639. dsi_ctrl_mask_overflow(ctrl->ctrl, enable);
  2640. }
  2641. }
  2642. static int dsi_display_broadcast_cmd(struct dsi_display *display, struct dsi_cmd_desc *cmd)
  2643. {
  2644. int rc = 0;
  2645. struct dsi_display_ctrl *ctrl, *m_ctrl;
  2646. int i;
  2647. /*
  2648. * 1. Setup commands in FIFO
  2649. * 2. Trigger commands
  2650. */
  2651. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2652. dsi_display_mask_overflow(display, cmd->ctrl_flags, true);
  2653. cmd->ctrl_flags |= DSI_CTRL_CMD_BROADCAST_MASTER;
  2654. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  2655. if (rc) {
  2656. DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n",
  2657. display->name, rc);
  2658. goto error;
  2659. }
  2660. cmd->ctrl_flags &= ~DSI_CTRL_CMD_BROADCAST_MASTER;
  2661. display_for_each_ctrl(i, display) {
  2662. ctrl = &display->ctrl[i];
  2663. if (ctrl == m_ctrl)
  2664. continue;
  2665. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, cmd);
  2666. if (rc) {
  2667. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2668. display->name, rc);
  2669. goto error;
  2670. }
  2671. rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl, cmd->ctrl_flags);
  2672. if (rc) {
  2673. DSI_ERR("[%s] cmd trigger failed, rc=%d\n",
  2674. display->name, rc);
  2675. goto error;
  2676. }
  2677. }
  2678. rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl, cmd->ctrl_flags | DSI_CTRL_CMD_BROADCAST_MASTER);
  2679. if (rc) {
  2680. DSI_ERR("[%s] cmd trigger failed for master, rc=%d\n",
  2681. display->name, rc);
  2682. goto error;
  2683. }
  2684. error:
  2685. dsi_display_mask_overflow(display, cmd->ctrl_flags, false);
  2686. return rc;
  2687. }
  2688. static int dsi_display_phy_sw_reset(struct dsi_display *display)
  2689. {
  2690. int rc = 0;
  2691. int i;
  2692. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2693. /*
  2694. * For continuous splash and trusted vm environment,
  2695. * ctrl states are updated separately and hence we do
  2696. * an early return
  2697. */
  2698. if (is_skip_op_required(display)) {
  2699. DSI_DEBUG(
  2700. "cont splash/trusted vm use case, phy sw reset not required\n");
  2701. return 0;
  2702. }
  2703. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2704. rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
  2705. if (rc) {
  2706. DSI_ERR("[%s] failed to reset phy, rc=%d\n", display->name, rc);
  2707. goto error;
  2708. }
  2709. display_for_each_ctrl(i, display) {
  2710. ctrl = &display->ctrl[i];
  2711. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2712. continue;
  2713. rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
  2714. if (rc) {
  2715. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  2716. display->name, rc);
  2717. goto error;
  2718. }
  2719. }
  2720. error:
  2721. return rc;
  2722. }
  2723. static int dsi_host_attach(struct mipi_dsi_host *host,
  2724. struct mipi_dsi_device *dsi)
  2725. {
  2726. return 0;
  2727. }
  2728. static int dsi_host_detach(struct mipi_dsi_host *host,
  2729. struct mipi_dsi_device *dsi)
  2730. {
  2731. return 0;
  2732. }
  2733. int dsi_host_transfer_sub(struct mipi_dsi_host *host, struct dsi_cmd_desc *cmd)
  2734. {
  2735. struct dsi_display *display;
  2736. int rc = 0, ret = 0;
  2737. if (!host || !cmd) {
  2738. DSI_ERR("Invalid params\n");
  2739. return 0;
  2740. }
  2741. display = to_dsi_display(host);
  2742. /* Avoid sending DCS commands when ESD recovery is pending */
  2743. if (atomic_read(&display->panel->esd_recovery_pending)) {
  2744. DSI_DEBUG("ESD recovery pending\n");
  2745. return 0;
  2746. }
  2747. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2748. DSI_ALL_CLKS, DSI_CLK_ON);
  2749. if (rc) {
  2750. DSI_ERR("[%s] failed to enable all DSI clocks, rc=%d\n",
  2751. display->name, rc);
  2752. goto error;
  2753. }
  2754. rc = dsi_display_wake_up(display);
  2755. if (rc) {
  2756. DSI_ERR("[%s] failed to wake up display, rc=%d\n",
  2757. display->name, rc);
  2758. goto error_disable_clks;
  2759. }
  2760. rc = dsi_display_cmd_engine_enable(display);
  2761. if (rc) {
  2762. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2763. display->name, rc);
  2764. goto error_disable_clks;
  2765. }
  2766. if (display->tx_cmd_buf == NULL) {
  2767. rc = dsi_host_alloc_cmd_tx_buffer(display);
  2768. if (rc) {
  2769. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  2770. goto error_disable_cmd_engine;
  2771. }
  2772. }
  2773. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  2774. if (cmd->ctrl_flags & DSI_CTRL_CMD_BROADCAST) {
  2775. rc = dsi_display_broadcast_cmd(display, cmd);
  2776. if (rc) {
  2777. DSI_ERR("[%s] cmd broadcast failed, rc=%d\n", display->name, rc);
  2778. goto error_disable_cmd_engine;
  2779. }
  2780. } else {
  2781. int idx = cmd->ctrl;
  2782. rc = dsi_ctrl_cmd_transfer(display->ctrl[idx].ctrl, cmd);
  2783. if (rc) {
  2784. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2785. display->name, rc);
  2786. goto error_disable_cmd_engine;
  2787. }
  2788. }
  2789. error_disable_cmd_engine:
  2790. ret = dsi_display_cmd_engine_disable(display);
  2791. if (ret) {
  2792. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  2793. display->name, ret);
  2794. }
  2795. error_disable_clks:
  2796. ret = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2797. DSI_ALL_CLKS, DSI_CLK_OFF);
  2798. if (ret) {
  2799. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  2800. display->name, ret);
  2801. }
  2802. error:
  2803. return rc;
  2804. }
  2805. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg)
  2806. {
  2807. int rc = 0;
  2808. struct dsi_cmd_desc cmd;
  2809. if (!msg) {
  2810. DSI_ERR("Invalid params\n");
  2811. return 0;
  2812. }
  2813. memcpy(&cmd.msg, msg, sizeof(*msg));
  2814. cmd.ctrl = 0;
  2815. cmd.post_wait_ms = 0;
  2816. cmd.ctrl_flags = 0;
  2817. rc = dsi_host_transfer_sub(host, &cmd);
  2818. return rc;
  2819. }
  2820. static struct mipi_dsi_host_ops dsi_host_ops = {
  2821. .attach = dsi_host_attach,
  2822. .detach = dsi_host_detach,
  2823. .transfer = dsi_host_transfer,
  2824. };
  2825. static int dsi_display_mipi_host_init(struct dsi_display *display)
  2826. {
  2827. int rc = 0;
  2828. struct mipi_dsi_host *host = &display->host;
  2829. host->dev = &display->pdev->dev;
  2830. host->ops = &dsi_host_ops;
  2831. rc = mipi_dsi_host_register(host);
  2832. if (rc) {
  2833. DSI_ERR("[%s] failed to register mipi dsi host, rc=%d\n",
  2834. display->name, rc);
  2835. goto error;
  2836. }
  2837. error:
  2838. return rc;
  2839. }
  2840. static int dsi_display_mipi_host_deinit(struct dsi_display *display)
  2841. {
  2842. int rc = 0;
  2843. struct mipi_dsi_host *host = &display->host;
  2844. mipi_dsi_host_unregister(host);
  2845. host->dev = NULL;
  2846. host->ops = NULL;
  2847. return rc;
  2848. }
  2849. static bool dsi_display_check_prefix(const char *clk_prefix,
  2850. const char *clk_name)
  2851. {
  2852. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  2853. }
  2854. static int dsi_display_get_clocks_count(struct dsi_display *display,
  2855. char *dsi_clk_name)
  2856. {
  2857. if (display->fw)
  2858. return dsi_parser_count_strings(display->parser_node,
  2859. dsi_clk_name);
  2860. else
  2861. return of_property_count_strings(display->panel_node,
  2862. dsi_clk_name);
  2863. }
  2864. static void dsi_display_get_clock_name(struct dsi_display *display,
  2865. char *dsi_clk_name, int index,
  2866. const char **clk_name)
  2867. {
  2868. if (display->fw)
  2869. dsi_parser_read_string_index(display->parser_node,
  2870. dsi_clk_name, index, clk_name);
  2871. else
  2872. of_property_read_string_index(display->panel_node,
  2873. dsi_clk_name, index, clk_name);
  2874. }
  2875. static int dsi_display_clocks_init(struct dsi_display *display)
  2876. {
  2877. int i, rc = 0, num_clk = 0;
  2878. const char *clk_name;
  2879. const char *pll_byte = "pll_byte", *pll_dsi = "pll_dsi";
  2880. struct clk *dsi_clk;
  2881. struct dsi_clk_link_set *pll = &display->clock_info.pll_clks;
  2882. char *dsi_clock_name;
  2883. if (!strcmp(display->display_type, "primary"))
  2884. dsi_clock_name = "qcom,dsi-select-clocks";
  2885. else
  2886. dsi_clock_name = "qcom,dsi-select-sec-clocks";
  2887. num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
  2888. for (i = 0; i < num_clk; i++) {
  2889. dsi_display_get_clock_name(display, dsi_clock_name, i,
  2890. &clk_name);
  2891. DSI_DEBUG("clock name:%s\n", clk_name);
  2892. dsi_clk = devm_clk_get(&display->pdev->dev, clk_name);
  2893. if (IS_ERR_OR_NULL(dsi_clk)) {
  2894. rc = PTR_ERR(dsi_clk);
  2895. DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
  2896. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2897. pll->byte_clk = NULL;
  2898. goto error;
  2899. }
  2900. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2901. pll->pixel_clk = NULL;
  2902. goto error;
  2903. }
  2904. }
  2905. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2906. pll->byte_clk = dsi_clk;
  2907. continue;
  2908. }
  2909. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2910. pll->pixel_clk = dsi_clk;
  2911. continue;
  2912. }
  2913. }
  2914. return 0;
  2915. error:
  2916. return rc;
  2917. }
  2918. static int dsi_display_clk_ctrl_cb(void *priv,
  2919. struct dsi_clk_ctrl_info clk_state_info)
  2920. {
  2921. int rc = 0;
  2922. struct dsi_display *display = NULL;
  2923. void *clk_handle = NULL;
  2924. if (!priv) {
  2925. DSI_ERR("Invalid params\n");
  2926. return -EINVAL;
  2927. }
  2928. display = priv;
  2929. if (clk_state_info.client == DSI_CLK_REQ_MDP_CLIENT) {
  2930. clk_handle = display->mdp_clk_handle;
  2931. } else if (clk_state_info.client == DSI_CLK_REQ_DSI_CLIENT) {
  2932. clk_handle = display->dsi_clk_handle;
  2933. } else {
  2934. DSI_ERR("invalid clk handle, return error\n");
  2935. return -EINVAL;
  2936. }
  2937. /*
  2938. * TODO: Wait for CMD_MDP_DONE interrupt if MDP client tries
  2939. * to turn off DSI clocks.
  2940. */
  2941. rc = dsi_display_clk_ctrl(clk_handle,
  2942. clk_state_info.clk_type, clk_state_info.clk_state);
  2943. if (rc) {
  2944. DSI_ERR("[%s] failed to %d DSI %d clocks, rc=%d\n",
  2945. display->name, clk_state_info.clk_state,
  2946. clk_state_info.clk_type, rc);
  2947. return rc;
  2948. }
  2949. return 0;
  2950. }
  2951. static void dsi_display_ctrl_isr_configure(struct dsi_display *display, bool en)
  2952. {
  2953. int i;
  2954. struct dsi_display_ctrl *ctrl;
  2955. if (!display)
  2956. return;
  2957. display_for_each_ctrl(i, display) {
  2958. ctrl = &display->ctrl[i];
  2959. if (!ctrl)
  2960. continue;
  2961. dsi_ctrl_isr_configure(ctrl->ctrl, en);
  2962. }
  2963. }
  2964. int dsi_pre_clkoff_cb(void *priv,
  2965. enum dsi_clk_type clk,
  2966. enum dsi_lclk_type l_type,
  2967. enum dsi_clk_state new_state)
  2968. {
  2969. int rc = 0, i;
  2970. struct dsi_display *display = priv;
  2971. struct dsi_display_ctrl *ctrl;
  2972. /*
  2973. * If Idle Power Collapse occurs immediately after a CMD
  2974. * transfer with an asynchronous wait for DMA done, ensure
  2975. * that the work queued is scheduled and completed before turning
  2976. * off the clocks and disabling interrupts to validate the command
  2977. * transfer.
  2978. */
  2979. display_for_each_ctrl(i, display) {
  2980. ctrl = &display->ctrl[i];
  2981. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  2982. continue;
  2983. flush_workqueue(display->dma_cmd_workq);
  2984. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  2985. ctrl->ctrl->dma_wait_queued = false;
  2986. }
  2987. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  2988. (l_type & DSI_LINK_LP_CLK)) {
  2989. /*
  2990. * If continuous clock is enabled then disable it
  2991. * before entering into ULPS Mode.
  2992. */
  2993. if (display->panel->host_config.force_hs_clk_lane)
  2994. _dsi_display_continuous_clk_ctrl(display, false);
  2995. /*
  2996. * If ULPS feature is enabled, enter ULPS first.
  2997. * However, when blanking the panel, we should enter ULPS
  2998. * only if ULPS during suspend feature is enabled.
  2999. */
  3000. if (!dsi_panel_initialized(display->panel)) {
  3001. if (display->panel->ulps_suspend_enabled)
  3002. rc = dsi_display_set_ulps(display, true);
  3003. } else if (dsi_panel_ulps_feature_enabled(display->panel)) {
  3004. rc = dsi_display_set_ulps(display, true);
  3005. }
  3006. if (rc)
  3007. DSI_ERR("%s: failed enable ulps, rc = %d\n",
  3008. __func__, rc);
  3009. }
  3010. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  3011. (l_type & DSI_LINK_HS_CLK)) {
  3012. /*
  3013. * PHY clock gating should be disabled before the PLL and the
  3014. * branch clocks are turned off. Otherwise, it is possible that
  3015. * the clock RCGs may not be turned off correctly resulting
  3016. * in clock warnings.
  3017. */
  3018. rc = dsi_display_config_clk_gating(display, false);
  3019. if (rc)
  3020. DSI_ERR("[%s] failed to disable clk gating, rc=%d\n",
  3021. display->name, rc);
  3022. }
  3023. if ((clk & DSI_CORE_CLK) && (new_state == DSI_CLK_OFF)) {
  3024. /*
  3025. * Enable DSI clamps only if entering idle power collapse or
  3026. * when ULPS during suspend is enabled..
  3027. */
  3028. if (dsi_panel_initialized(display->panel) ||
  3029. display->panel->ulps_suspend_enabled) {
  3030. dsi_display_phy_idle_off(display);
  3031. rc = dsi_display_set_clamp(display, true);
  3032. if (rc)
  3033. DSI_ERR("%s: Failed to enable dsi clamps. rc=%d\n",
  3034. __func__, rc);
  3035. rc = dsi_display_phy_reset_config(display, false);
  3036. if (rc)
  3037. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3038. __func__, rc);
  3039. } else {
  3040. /* Make sure that controller is not in ULPS state when
  3041. * the DSI link is not active.
  3042. */
  3043. rc = dsi_display_set_ulps(display, false);
  3044. if (rc)
  3045. DSI_ERR("%s: failed to disable ulps. rc=%d\n",
  3046. __func__, rc);
  3047. }
  3048. /* dsi will not be able to serve irqs from here on */
  3049. dsi_display_ctrl_irq_update(display, false);
  3050. /* cache the MISR values */
  3051. display_for_each_ctrl(i, display) {
  3052. ctrl = &display->ctrl[i];
  3053. if (!ctrl->ctrl)
  3054. continue;
  3055. dsi_ctrl_cache_misr(ctrl->ctrl);
  3056. }
  3057. }
  3058. return rc;
  3059. }
  3060. int dsi_post_clkon_cb(void *priv,
  3061. enum dsi_clk_type clk,
  3062. enum dsi_lclk_type l_type,
  3063. enum dsi_clk_state curr_state)
  3064. {
  3065. int rc = 0;
  3066. struct dsi_display *display = priv;
  3067. bool mmss_clamp = false;
  3068. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {
  3069. mmss_clamp = display->clamp_enabled;
  3070. /*
  3071. * controller setup is needed if coming out of idle
  3072. * power collapse with clamps enabled.
  3073. */
  3074. if (mmss_clamp)
  3075. dsi_display_ctrl_setup(display);
  3076. /*
  3077. * Phy setup is needed if coming out of idle
  3078. * power collapse with clamps enabled.
  3079. */
  3080. if (display->phy_idle_power_off || mmss_clamp)
  3081. dsi_display_phy_idle_on(display, mmss_clamp);
  3082. if (display->ulps_enabled && mmss_clamp) {
  3083. /*
  3084. * ULPS Entry Request. This is needed if the lanes were
  3085. * in ULPS prior to power collapse, since after
  3086. * power collapse and reset, the DSI controller resets
  3087. * back to idle state and not ULPS. This ulps entry
  3088. * request will transition the state of the DSI
  3089. * controller to ULPS which will match the state of the
  3090. * DSI phy. This needs to be done prior to disabling
  3091. * the DSI clamps.
  3092. *
  3093. * Also, reset the ulps flag so that ulps_config
  3094. * function would reconfigure the controller state to
  3095. * ULPS.
  3096. */
  3097. display->ulps_enabled = false;
  3098. rc = dsi_display_set_ulps(display, true);
  3099. if (rc) {
  3100. DSI_ERR("%s: Failed to enter ULPS. rc=%d\n",
  3101. __func__, rc);
  3102. goto error;
  3103. }
  3104. }
  3105. rc = dsi_display_phy_reset_config(display, true);
  3106. if (rc) {
  3107. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3108. __func__, rc);
  3109. goto error;
  3110. }
  3111. rc = dsi_display_set_clamp(display, false);
  3112. if (rc) {
  3113. DSI_ERR("%s: Failed to disable dsi clamps. rc=%d\n",
  3114. __func__, rc);
  3115. goto error;
  3116. }
  3117. }
  3118. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {
  3119. /*
  3120. * Toggle the resync FIFO everytime clock changes, except
  3121. * when cont-splash screen transition is going on.
  3122. * Toggling resync FIFO during cont splash transition
  3123. * can lead to blinks on the display.
  3124. */
  3125. if (!display->is_cont_splash_enabled)
  3126. dsi_display_toggle_resync_fifo(display);
  3127. if (display->ulps_enabled) {
  3128. rc = dsi_display_set_ulps(display, false);
  3129. if (rc) {
  3130. DSI_ERR("%s: failed to disable ulps, rc= %d\n",
  3131. __func__, rc);
  3132. goto error;
  3133. }
  3134. }
  3135. if (display->panel->host_config.force_hs_clk_lane)
  3136. _dsi_display_continuous_clk_ctrl(display, true);
  3137. rc = dsi_display_config_clk_gating(display, true);
  3138. if (rc) {
  3139. DSI_ERR("[%s] failed to enable clk gating %d\n",
  3140. display->name, rc);
  3141. goto error;
  3142. }
  3143. }
  3144. /* enable dsi to serve irqs */
  3145. if (clk & DSI_CORE_CLK)
  3146. dsi_display_ctrl_irq_update(display, true);
  3147. error:
  3148. return rc;
  3149. }
  3150. int dsi_post_clkoff_cb(void *priv,
  3151. enum dsi_clk_type clk_type,
  3152. enum dsi_lclk_type l_type,
  3153. enum dsi_clk_state curr_state)
  3154. {
  3155. int rc = 0;
  3156. struct dsi_display *display = priv;
  3157. if (!display) {
  3158. DSI_ERR("%s: Invalid arg\n", __func__);
  3159. return -EINVAL;
  3160. }
  3161. if ((clk_type & DSI_CORE_CLK) &&
  3162. (curr_state == DSI_CLK_OFF)) {
  3163. rc = dsi_display_phy_power_off(display);
  3164. if (rc)
  3165. DSI_ERR("[%s] failed to power off PHY, rc=%d\n",
  3166. display->name, rc);
  3167. rc = dsi_display_ctrl_power_off(display);
  3168. if (rc)
  3169. DSI_ERR("[%s] failed to power DSI vregs, rc=%d\n",
  3170. display->name, rc);
  3171. }
  3172. return rc;
  3173. }
  3174. int dsi_pre_clkon_cb(void *priv,
  3175. enum dsi_clk_type clk_type,
  3176. enum dsi_lclk_type l_type,
  3177. enum dsi_clk_state new_state)
  3178. {
  3179. int rc = 0;
  3180. struct dsi_display *display = priv;
  3181. if (!display) {
  3182. DSI_ERR("%s: invalid input\n", __func__);
  3183. return -EINVAL;
  3184. }
  3185. if ((clk_type & DSI_CORE_CLK) && (new_state == DSI_CLK_ON)) {
  3186. /*
  3187. * Enable DSI core power
  3188. * 1.> PANEL_PM are controlled as part of
  3189. * panel_power_ctrl. Needed not be handled here.
  3190. * 2.> CTRL_PM need to be enabled/disabled
  3191. * only during unblank/blank. Their state should
  3192. * not be changed during static screen.
  3193. */
  3194. DSI_DEBUG("updating power states for ctrl and phy\n");
  3195. rc = dsi_display_ctrl_power_on(display);
  3196. if (rc) {
  3197. DSI_ERR("[%s] failed to power on dsi controllers, rc=%d\n",
  3198. display->name, rc);
  3199. return rc;
  3200. }
  3201. rc = dsi_display_phy_power_on(display);
  3202. if (rc) {
  3203. DSI_ERR("[%s] failed to power on dsi phy, rc = %d\n",
  3204. display->name, rc);
  3205. return rc;
  3206. }
  3207. DSI_DEBUG("%s: Enable DSI core power\n", __func__);
  3208. }
  3209. return rc;
  3210. }
  3211. static void __set_lane_map_v2(u8 *lane_map_v2,
  3212. enum dsi_phy_data_lanes lane0,
  3213. enum dsi_phy_data_lanes lane1,
  3214. enum dsi_phy_data_lanes lane2,
  3215. enum dsi_phy_data_lanes lane3)
  3216. {
  3217. lane_map_v2[DSI_LOGICAL_LANE_0] = lane0;
  3218. lane_map_v2[DSI_LOGICAL_LANE_1] = lane1;
  3219. lane_map_v2[DSI_LOGICAL_LANE_2] = lane2;
  3220. lane_map_v2[DSI_LOGICAL_LANE_3] = lane3;
  3221. }
  3222. static int dsi_display_parse_lane_map(struct dsi_display *display)
  3223. {
  3224. int rc = 0, i = 0;
  3225. const char *data;
  3226. u8 temp[DSI_LANE_MAX - 1];
  3227. if (!display) {
  3228. DSI_ERR("invalid params\n");
  3229. return -EINVAL;
  3230. }
  3231. /* lane-map-v2 supersedes lane-map-v1 setting */
  3232. rc = of_property_read_u8_array(display->pdev->dev.of_node,
  3233. "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
  3234. if (!rc) {
  3235. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
  3236. display->lane_map.lane_map_v2[i] = BIT(temp[i]);
  3237. return 0;
  3238. } else if (rc != EINVAL) {
  3239. DSI_DEBUG("Incorrect mapping, configure default\n");
  3240. goto set_default;
  3241. }
  3242. /* lane-map older version, for DSI controller version < 2.0 */
  3243. data = of_get_property(display->pdev->dev.of_node,
  3244. "qcom,lane-map", NULL);
  3245. if (!data)
  3246. goto set_default;
  3247. if (!strcmp(data, "lane_map_3012")) {
  3248. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3012;
  3249. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3250. DSI_PHYSICAL_LANE_1,
  3251. DSI_PHYSICAL_LANE_2,
  3252. DSI_PHYSICAL_LANE_3,
  3253. DSI_PHYSICAL_LANE_0);
  3254. } else if (!strcmp(data, "lane_map_2301")) {
  3255. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2301;
  3256. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3257. DSI_PHYSICAL_LANE_2,
  3258. DSI_PHYSICAL_LANE_3,
  3259. DSI_PHYSICAL_LANE_0,
  3260. DSI_PHYSICAL_LANE_1);
  3261. } else if (!strcmp(data, "lane_map_1230")) {
  3262. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1230;
  3263. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3264. DSI_PHYSICAL_LANE_3,
  3265. DSI_PHYSICAL_LANE_0,
  3266. DSI_PHYSICAL_LANE_1,
  3267. DSI_PHYSICAL_LANE_2);
  3268. } else if (!strcmp(data, "lane_map_0321")) {
  3269. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0321;
  3270. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3271. DSI_PHYSICAL_LANE_0,
  3272. DSI_PHYSICAL_LANE_3,
  3273. DSI_PHYSICAL_LANE_2,
  3274. DSI_PHYSICAL_LANE_1);
  3275. } else if (!strcmp(data, "lane_map_1032")) {
  3276. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1032;
  3277. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3278. DSI_PHYSICAL_LANE_1,
  3279. DSI_PHYSICAL_LANE_0,
  3280. DSI_PHYSICAL_LANE_3,
  3281. DSI_PHYSICAL_LANE_2);
  3282. } else if (!strcmp(data, "lane_map_2103")) {
  3283. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2103;
  3284. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3285. DSI_PHYSICAL_LANE_2,
  3286. DSI_PHYSICAL_LANE_1,
  3287. DSI_PHYSICAL_LANE_0,
  3288. DSI_PHYSICAL_LANE_3);
  3289. } else if (!strcmp(data, "lane_map_3210")) {
  3290. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3210;
  3291. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3292. DSI_PHYSICAL_LANE_3,
  3293. DSI_PHYSICAL_LANE_2,
  3294. DSI_PHYSICAL_LANE_1,
  3295. DSI_PHYSICAL_LANE_0);
  3296. } else {
  3297. DSI_WARN("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
  3298. __func__, data);
  3299. goto set_default;
  3300. }
  3301. return 0;
  3302. set_default:
  3303. /* default lane mapping */
  3304. __set_lane_map_v2(display->lane_map.lane_map_v2, DSI_PHYSICAL_LANE_0,
  3305. DSI_PHYSICAL_LANE_1, DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
  3306. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0123;
  3307. return 0;
  3308. }
  3309. static int dsi_display_get_phandle_index(
  3310. struct dsi_display *display,
  3311. const char *propname, int count, int index)
  3312. {
  3313. struct device_node *disp_node = display->panel_node;
  3314. u32 *val = NULL;
  3315. int rc = 0;
  3316. val = kcalloc(count, sizeof(*val), GFP_KERNEL);
  3317. if (ZERO_OR_NULL_PTR(val)) {
  3318. rc = -ENOMEM;
  3319. goto end;
  3320. }
  3321. if (index >= count)
  3322. goto end;
  3323. if (display->fw)
  3324. rc = dsi_parser_read_u32_array(display->parser_node,
  3325. propname, val, count);
  3326. else
  3327. rc = of_property_read_u32_array(disp_node, propname,
  3328. val, count);
  3329. if (rc)
  3330. goto end;
  3331. rc = val[index];
  3332. DSI_DEBUG("%s index=%d\n", propname, rc);
  3333. end:
  3334. kfree(val);
  3335. return rc;
  3336. }
  3337. static int dsi_display_get_phandle_count(struct dsi_display *display,
  3338. const char *propname)
  3339. {
  3340. if (display->fw)
  3341. return dsi_parser_count_u32_elems(display->parser_node,
  3342. propname);
  3343. else
  3344. return of_property_count_u32_elems(display->panel_node,
  3345. propname);
  3346. }
  3347. static int dsi_display_parse_dt(struct dsi_display *display)
  3348. {
  3349. int i, rc = 0;
  3350. u32 phy_count = 0;
  3351. struct device_node *of_node = display->pdev->dev.of_node;
  3352. char *dsi_ctrl_name, *dsi_phy_name;
  3353. if (!strcmp(display->display_type, "primary")) {
  3354. dsi_ctrl_name = "qcom,dsi-ctrl-num";
  3355. dsi_phy_name = "qcom,dsi-phy-num";
  3356. } else {
  3357. dsi_ctrl_name = "qcom,dsi-sec-ctrl-num";
  3358. dsi_phy_name = "qcom,dsi-sec-phy-num";
  3359. }
  3360. display->ctrl_count = dsi_display_get_phandle_count(display,
  3361. dsi_ctrl_name);
  3362. phy_count = dsi_display_get_phandle_count(display, dsi_phy_name);
  3363. DSI_DEBUG("ctrl count=%d, phy count=%d\n",
  3364. display->ctrl_count, phy_count);
  3365. if (!phy_count || !display->ctrl_count) {
  3366. DSI_ERR("no ctrl/phys found\n");
  3367. rc = -ENODEV;
  3368. goto error;
  3369. }
  3370. if (phy_count != display->ctrl_count) {
  3371. DSI_ERR("different ctrl and phy counts\n");
  3372. rc = -ENODEV;
  3373. goto error;
  3374. }
  3375. display_for_each_ctrl(i, display) {
  3376. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  3377. int index;
  3378. index = dsi_display_get_phandle_index(display, dsi_ctrl_name,
  3379. display->ctrl_count, i);
  3380. ctrl->ctrl_of_node = of_parse_phandle(of_node,
  3381. "qcom,dsi-ctrl", index);
  3382. of_node_put(ctrl->ctrl_of_node);
  3383. index = dsi_display_get_phandle_index(display, dsi_phy_name,
  3384. display->ctrl_count, i);
  3385. ctrl->phy_of_node = of_parse_phandle(of_node,
  3386. "qcom,dsi-phy", index);
  3387. of_node_put(ctrl->phy_of_node);
  3388. }
  3389. /* Parse TE data */
  3390. dsi_display_parse_te_data(display);
  3391. /* Parse all external bridges from port 0 */
  3392. display_for_each_ctrl(i, display) {
  3393. display->ext_bridge[i].node_of =
  3394. of_graph_get_remote_node(of_node, 0, i);
  3395. if (display->ext_bridge[i].node_of)
  3396. display->ext_bridge_cnt++;
  3397. else
  3398. break;
  3399. }
  3400. /* Parse Demura data */
  3401. dsi_display_parse_demura_data(display);
  3402. DSI_DEBUG("success\n");
  3403. error:
  3404. return rc;
  3405. }
  3406. static int dsi_display_validate_resources(struct dsi_display *display)
  3407. {
  3408. int rc = 0;
  3409. int i;
  3410. struct dsi_display_ctrl *ctrl;
  3411. display_for_each_ctrl(i, display) {
  3412. ctrl = &display->ctrl[i];
  3413. ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
  3414. if (IS_ERR_OR_NULL(ctrl->ctrl)) {
  3415. rc = PTR_ERR(ctrl->ctrl);
  3416. DSI_ERR("failed to get dsi controller, rc=%d\n", rc);
  3417. ctrl->ctrl = NULL;
  3418. goto error;
  3419. }
  3420. ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
  3421. if (IS_ERR_OR_NULL(ctrl->phy)) {
  3422. rc = PTR_ERR(ctrl->phy);
  3423. DSI_ERR("failed to get phy controller, rc=%d\n", rc);
  3424. dsi_ctrl_put(ctrl->ctrl);
  3425. ctrl->phy = NULL;
  3426. goto error;
  3427. }
  3428. }
  3429. return rc;
  3430. error:
  3431. for (i = i - 1; i >= 0; i--) {
  3432. ctrl = &display->ctrl[i];
  3433. dsi_ctrl_put(ctrl->ctrl);
  3434. dsi_phy_put(ctrl->phy);
  3435. }
  3436. return -EPROBE_DEFER;
  3437. }
  3438. static int dsi_display_res_init(struct dsi_display *display)
  3439. {
  3440. int rc = 0;
  3441. int i;
  3442. display->panel = dsi_panel_get(&display->pdev->dev,
  3443. display->panel_node,
  3444. display->parser_node,
  3445. display->display_type,
  3446. display->cmdline_topology,
  3447. display->trusted_vm_env);
  3448. if (IS_ERR_OR_NULL(display->panel)) {
  3449. rc = PTR_ERR(display->panel);
  3450. DSI_ERR("failed to get panel, rc=%d\n", rc);
  3451. display->panel = NULL;
  3452. goto error;
  3453. }
  3454. display_for_each_ctrl(i, display) {
  3455. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  3456. phy->cfg.force_clk_lane_hs =
  3457. display->panel->host_config.force_hs_clk_lane;
  3458. phy->cfg.phy_type =
  3459. display->panel->host_config.phy_type;
  3460. /*
  3461. * Parse the dynamic clock trim codes for PLL, for video mode panels that have
  3462. * dynamic clock property set.
  3463. */
  3464. if ((display->panel->dyn_clk_caps.dyn_clk_support) &&
  3465. (display->panel->panel_mode == DSI_OP_VIDEO_MODE))
  3466. dsi_phy_pll_parse_dfps_data(phy);
  3467. }
  3468. rc = dsi_display_parse_lane_map(display);
  3469. if (rc) {
  3470. DSI_ERR("Lane map not found, rc=%d\n", rc);
  3471. goto error;
  3472. }
  3473. rc = dsi_display_clocks_init(display);
  3474. if (rc) {
  3475. DSI_ERR("Failed to parse clock data, rc=%d\n", rc);
  3476. goto error;
  3477. }
  3478. /**
  3479. * In trusted vm, the connectors will not be enabled
  3480. * until the HW resources are assigned and accepted.
  3481. */
  3482. if (display->trusted_vm_env)
  3483. display->is_active = false;
  3484. else
  3485. display->is_active = true;
  3486. error:
  3487. return rc;
  3488. }
  3489. static int dsi_display_res_deinit(struct dsi_display *display)
  3490. {
  3491. int rc = 0;
  3492. int i;
  3493. struct dsi_display_ctrl *ctrl;
  3494. display_for_each_ctrl(i, display) {
  3495. ctrl = &display->ctrl[i];
  3496. dsi_phy_put(ctrl->phy);
  3497. dsi_ctrl_put(ctrl->ctrl);
  3498. }
  3499. if (display->panel)
  3500. dsi_panel_put(display->panel);
  3501. return rc;
  3502. }
  3503. static int dsi_display_validate_mode_set(struct dsi_display *display,
  3504. struct dsi_display_mode *mode,
  3505. u32 flags)
  3506. {
  3507. int rc = 0;
  3508. int i;
  3509. struct dsi_display_ctrl *ctrl;
  3510. /*
  3511. * To set a mode:
  3512. * 1. Controllers should be turned off.
  3513. * 2. Link clocks should be off.
  3514. * 3. Phy should be disabled.
  3515. */
  3516. display_for_each_ctrl(i, display) {
  3517. ctrl = &display->ctrl[i];
  3518. if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
  3519. (ctrl->phy_enabled)) {
  3520. rc = -EINVAL;
  3521. goto error;
  3522. }
  3523. }
  3524. error:
  3525. return rc;
  3526. }
  3527. static bool dsi_display_is_seamless_dfps_possible(
  3528. const struct dsi_display *display,
  3529. const struct dsi_display_mode *tgt,
  3530. const enum dsi_dfps_type dfps_type)
  3531. {
  3532. struct dsi_display_mode *cur;
  3533. if (!display || !tgt || !display->panel) {
  3534. DSI_ERR("Invalid params\n");
  3535. return false;
  3536. }
  3537. cur = display->panel->cur_mode;
  3538. if (cur->timing.h_active != tgt->timing.h_active) {
  3539. DSI_DEBUG("timing.h_active differs %d %d\n",
  3540. cur->timing.h_active, tgt->timing.h_active);
  3541. return false;
  3542. }
  3543. if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
  3544. DSI_DEBUG("timing.h_back_porch differs %d %d\n",
  3545. cur->timing.h_back_porch,
  3546. tgt->timing.h_back_porch);
  3547. return false;
  3548. }
  3549. if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
  3550. DSI_DEBUG("timing.h_sync_width differs %d %d\n",
  3551. cur->timing.h_sync_width,
  3552. tgt->timing.h_sync_width);
  3553. return false;
  3554. }
  3555. if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
  3556. DSI_DEBUG("timing.h_front_porch differs %d %d\n",
  3557. cur->timing.h_front_porch,
  3558. tgt->timing.h_front_porch);
  3559. if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
  3560. return false;
  3561. }
  3562. if (cur->timing.h_skew != tgt->timing.h_skew) {
  3563. DSI_DEBUG("timing.h_skew differs %d %d\n",
  3564. cur->timing.h_skew,
  3565. tgt->timing.h_skew);
  3566. return false;
  3567. }
  3568. /* skip polarity comparison */
  3569. if (cur->timing.v_active != tgt->timing.v_active) {
  3570. DSI_DEBUG("timing.v_active differs %d %d\n",
  3571. cur->timing.v_active,
  3572. tgt->timing.v_active);
  3573. return false;
  3574. }
  3575. if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
  3576. DSI_DEBUG("timing.v_back_porch differs %d %d\n",
  3577. cur->timing.v_back_porch,
  3578. tgt->timing.v_back_porch);
  3579. return false;
  3580. }
  3581. if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
  3582. DSI_DEBUG("timing.v_sync_width differs %d %d\n",
  3583. cur->timing.v_sync_width,
  3584. tgt->timing.v_sync_width);
  3585. return false;
  3586. }
  3587. if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
  3588. DSI_DEBUG("timing.v_front_porch differs %d %d\n",
  3589. cur->timing.v_front_porch,
  3590. tgt->timing.v_front_porch);
  3591. if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
  3592. return false;
  3593. }
  3594. /* skip polarity comparison */
  3595. if (cur->timing.refresh_rate == tgt->timing.refresh_rate)
  3596. DSI_DEBUG("timing.refresh_rate identical %d %d\n",
  3597. cur->timing.refresh_rate,
  3598. tgt->timing.refresh_rate);
  3599. if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
  3600. DSI_DEBUG("pixel_clk_khz differs %d %d\n",
  3601. cur->pixel_clk_khz, tgt->pixel_clk_khz);
  3602. if (cur->dsi_mode_flags != tgt->dsi_mode_flags)
  3603. DSI_DEBUG("flags differs %d %d\n",
  3604. cur->dsi_mode_flags, tgt->dsi_mode_flags);
  3605. return true;
  3606. }
  3607. void dsi_display_update_byte_intf_div(struct dsi_display *display)
  3608. {
  3609. struct dsi_host_common_cfg *config;
  3610. struct dsi_display_ctrl *m_ctrl;
  3611. int phy_ver;
  3612. m_ctrl = &display->ctrl[display->cmd_master_idx];
  3613. config = &display->panel->host_config;
  3614. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3615. if (phy_ver <= DSI_PHY_VERSION_2_0)
  3616. config->byte_intf_clk_div = 1;
  3617. else
  3618. config->byte_intf_clk_div = 2;
  3619. }
  3620. static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
  3621. u32 bit_clk_rate)
  3622. {
  3623. int rc = 0;
  3624. int i;
  3625. DSI_DEBUG("%s:bit rate:%d\n", __func__, bit_clk_rate);
  3626. if (!display->panel) {
  3627. DSI_ERR("Invalid params\n");
  3628. return -EINVAL;
  3629. }
  3630. if (bit_clk_rate == 0) {
  3631. DSI_ERR("Invalid bit clock rate\n");
  3632. return -EINVAL;
  3633. }
  3634. display->config.bit_clk_rate_hz = bit_clk_rate;
  3635. display_for_each_ctrl(i, display) {
  3636. struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
  3637. struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;
  3638. u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
  3639. u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
  3640. byte_intf_clk_rate;
  3641. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  3642. struct dsi_host_common_cfg *host_cfg;
  3643. mutex_lock(&ctrl->ctrl_lock);
  3644. host_cfg = &display->panel->host_config;
  3645. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  3646. num_of_lanes++;
  3647. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  3648. num_of_lanes++;
  3649. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  3650. num_of_lanes++;
  3651. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  3652. num_of_lanes++;
  3653. if (num_of_lanes == 0) {
  3654. DSI_ERR("Invalid lane count\n");
  3655. rc = -EINVAL;
  3656. goto error;
  3657. }
  3658. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  3659. bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;
  3660. bit_rate_per_lane = bit_rate;
  3661. do_div(bit_rate_per_lane, num_of_lanes);
  3662. pclk_rate = bit_rate;
  3663. do_div(pclk_rate, bpp);
  3664. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  3665. bit_rate_per_lane = bit_rate;
  3666. do_div(bit_rate_per_lane, num_of_lanes);
  3667. byte_clk_rate = bit_rate_per_lane;
  3668. do_div(byte_clk_rate, 8);
  3669. byte_intf_clk_rate = byte_clk_rate;
  3670. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  3671. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  3672. } else {
  3673. bit_rate_per_lane = bit_clk_rate;
  3674. pclk_rate *= bits_per_symbol;
  3675. do_div(pclk_rate, num_of_symbols);
  3676. byte_clk_rate = bit_clk_rate;
  3677. do_div(byte_clk_rate, num_of_symbols);
  3678. /* For CPHY, byte_intf_clk is same as byte_clk */
  3679. byte_intf_clk_rate = byte_clk_rate;
  3680. }
  3681. DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  3682. bit_rate, bit_rate_per_lane);
  3683. DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
  3684. byte_clk_rate, byte_intf_clk_rate);
  3685. DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
  3686. SDE_EVT32(i, bit_rate, byte_clk_rate, pclk_rate);
  3687. ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  3688. ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  3689. ctrl->clk_freq.pix_clk_rate = pclk_rate;
  3690. rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
  3691. ctrl->clk_freq, ctrl->cell_index);
  3692. if (rc) {
  3693. DSI_ERR("Failed to update link frequencies\n");
  3694. goto error;
  3695. }
  3696. ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
  3697. error:
  3698. mutex_unlock(&ctrl->ctrl_lock);
  3699. /* TODO: recover ctrl->clk_freq in case of failure */
  3700. if (rc)
  3701. return rc;
  3702. }
  3703. return 0;
  3704. }
  3705. static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
  3706. struct dsi_dyn_clk_delay *delay,
  3707. struct dsi_display_mode *mode)
  3708. {
  3709. u32 esc_clk_rate_hz;
  3710. u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
  3711. u32 hsync_period = 0;
  3712. struct dsi_display_ctrl *m_ctrl;
  3713. struct dsi_ctrl *dsi_ctrl;
  3714. struct dsi_phy_cfg *cfg;
  3715. int phy_ver;
  3716. m_ctrl = &display->ctrl[display->clk_master_idx];
  3717. dsi_ctrl = m_ctrl->ctrl;
  3718. cfg = &(m_ctrl->phy->cfg);
  3719. esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
  3720. pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
  3721. esc_clk_rate_hz);
  3722. byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
  3723. esc_clk_rate_hz);
  3724. hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
  3725. esc_clk_rate_hz);
  3726. hsync_period = dsi_h_total_dce(&mode->timing);
  3727. delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
  3728. if (!display->panel->video_config.eof_bllp_lp11_en)
  3729. delay->pipe_delay += (17 / pclk_to_esc_ratio) +
  3730. ((21 + (display->config.common_config.t_clk_pre + 1) +
  3731. (display->config.common_config.t_clk_post + 1)) /
  3732. byte_to_esc_ratio) +
  3733. ((((cfg->timing.lane_v3[8] >> 1) + 1) +
  3734. ((cfg->timing.lane_v3[6] >> 1) + 1) +
  3735. ((cfg->timing.lane_v3[3] * 4) +
  3736. (cfg->timing.lane_v3[5] >> 1) + 1) +
  3737. ((cfg->timing.lane_v3[7] >> 1) + 1) +
  3738. ((cfg->timing.lane_v3[1] >> 1) + 1) +
  3739. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3740. hr_bit_to_esc_ratio);
  3741. delay->pipe_delay2 = 0;
  3742. if (display->panel->host_config.force_hs_clk_lane)
  3743. delay->pipe_delay2 = (6 / byte_to_esc_ratio) +
  3744. ((((cfg->timing.lane_v3[1] >> 1) + 1) +
  3745. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3746. hr_bit_to_esc_ratio);
  3747. /*
  3748. * 100us pll delay recommended for phy ver 2.0 and 3.0
  3749. * 25us pll delay recommended for phy ver 4.0
  3750. */
  3751. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3752. if (phy_ver <= DSI_PHY_VERSION_3_0)
  3753. delay->pll_delay = 100;
  3754. else
  3755. delay->pll_delay = 25;
  3756. delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000);
  3757. }
  3758. /*
  3759. * dsi_display_is_type_cphy - check if panel type is cphy
  3760. * @display: Pointer to private display structure
  3761. * Returns: True if panel type is cphy
  3762. */
  3763. static inline bool dsi_display_is_type_cphy(struct dsi_display *display)
  3764. {
  3765. return (display->panel->host_config.phy_type ==
  3766. DSI_PHY_TYPE_CPHY) ? true : false;
  3767. }
  3768. static int _dsi_display_dyn_update_clks(struct dsi_display *display,
  3769. struct link_clk_freq *bkp_freq)
  3770. {
  3771. int rc = 0, i;
  3772. u8 ctrl_version;
  3773. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3774. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3775. struct dsi_clk_link_set *enable_clk;
  3776. m_ctrl = &display->ctrl[display->clk_master_idx];
  3777. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3778. ctrl_version = m_ctrl->ctrl->version;
  3779. enable_clk = &display->clock_info.pll_clks;
  3780. dsi_clk_prepare_enable(enable_clk);
  3781. dsi_display_phy_configure(display, false);
  3782. display_for_each_ctrl(i, display) {
  3783. ctrl = &display->ctrl[i];
  3784. if (!ctrl->ctrl)
  3785. continue;
  3786. rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3787. ctrl->ctrl->clk_freq.byte_clk_rate,
  3788. ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);
  3789. if (rc) {
  3790. DSI_ERR("failed to set byte rate for index:%d\n", i);
  3791. goto recover_byte_clk;
  3792. }
  3793. rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3794. ctrl->ctrl->clk_freq.pix_clk_rate, i);
  3795. if (rc) {
  3796. DSI_ERR("failed to set pix rate for index:%d\n", i);
  3797. goto recover_pix_clk;
  3798. }
  3799. }
  3800. display_for_each_ctrl(i, display) {
  3801. ctrl = &display->ctrl[i];
  3802. if (ctrl == m_ctrl)
  3803. continue;
  3804. dsi_phy_dynamic_refresh_trigger(ctrl->phy, false);
  3805. }
  3806. dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true);
  3807. /*
  3808. * Don't wait for dynamic refresh done for dsi ctrl greater than 2.5
  3809. * and with constant fps, as dynamic refresh will applied with
  3810. * next mdp intf ctrl flush.
  3811. */
  3812. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  3813. (dyn_clk_caps->maintain_const_fps))
  3814. return 0;
  3815. /* wait for dynamic refresh done */
  3816. display_for_each_ctrl(i, display) {
  3817. ctrl = &display->ctrl[i];
  3818. rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl);
  3819. if (rc) {
  3820. DSI_ERR("wait4dynamic refresh failed for dsi:%d\n", i);
  3821. goto recover_pix_clk;
  3822. } else {
  3823. DSI_INFO("dynamic refresh done on dsi: %s\n",
  3824. i ? "slave" : "master");
  3825. }
  3826. }
  3827. display_for_each_ctrl(i, display) {
  3828. ctrl = &display->ctrl[i];
  3829. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  3830. }
  3831. if (rc)
  3832. DSI_ERR("could not switch back to src clks %d\n", rc);
  3833. dsi_clk_disable_unprepare(enable_clk);
  3834. return rc;
  3835. recover_pix_clk:
  3836. display_for_each_ctrl(i, display) {
  3837. ctrl = &display->ctrl[i];
  3838. if (!ctrl->ctrl)
  3839. continue;
  3840. dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3841. bkp_freq->pix_clk_rate, i);
  3842. }
  3843. recover_byte_clk:
  3844. display_for_each_ctrl(i, display) {
  3845. ctrl = &display->ctrl[i];
  3846. if (!ctrl->ctrl)
  3847. continue;
  3848. dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3849. bkp_freq->byte_clk_rate,
  3850. bkp_freq->byte_intf_clk_rate, i);
  3851. }
  3852. return rc;
  3853. }
  3854. static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,
  3855. struct dsi_display_mode *mode)
  3856. {
  3857. int rc = 0, mask, i;
  3858. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3859. struct dsi_dyn_clk_delay delay;
  3860. struct link_clk_freq bkp_freq;
  3861. dsi_panel_acquire_panel_lock(display->panel);
  3862. m_ctrl = &display->ctrl[display->clk_master_idx];
  3863. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  3864. /* mask PLL unlock, FIFO overflow and underflow errors */
  3865. mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) |
  3866. BIT(DSI_FIFO_OVERFLOW);
  3867. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  3868. /* update the phy timings based on new mode */
  3869. display_for_each_ctrl(i, display) {
  3870. ctrl = &display->ctrl[i];
  3871. dsi_phy_update_phy_timings(ctrl->phy, &display->config);
  3872. }
  3873. /* back up existing rates to handle failure case */
  3874. bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;
  3875. bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;
  3876. bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;
  3877. bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
  3878. rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz);
  3879. if (rc) {
  3880. DSI_ERR("failed set link frequencies %d\n", rc);
  3881. goto exit;
  3882. }
  3883. /* calculate pipe delays */
  3884. _dsi_display_calc_pipe_delay(display, &delay, mode);
  3885. /* configure dynamic refresh ctrl registers */
  3886. display_for_each_ctrl(i, display) {
  3887. ctrl = &display->ctrl[i];
  3888. if (!ctrl->phy)
  3889. continue;
  3890. if (ctrl == m_ctrl)
  3891. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);
  3892. else
  3893. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,
  3894. false);
  3895. }
  3896. rc = _dsi_display_dyn_update_clks(display, &bkp_freq);
  3897. exit:
  3898. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  3899. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS,
  3900. DSI_CLK_OFF);
  3901. /* store newly calculated phy timings in mode private info */
  3902. dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy,
  3903. mode->priv_info->phy_timing_val,
  3904. mode->priv_info->phy_timing_len);
  3905. dsi_panel_release_panel_lock(display->panel);
  3906. return rc;
  3907. }
  3908. static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
  3909. int clk_rate)
  3910. {
  3911. int rc = 0;
  3912. if (clk_rate <= 0) {
  3913. DSI_ERR("%s: bitrate should be greater than 0\n", __func__);
  3914. return -EINVAL;
  3915. }
  3916. if (clk_rate == display->cached_clk_rate) {
  3917. DSI_INFO("%s: ignore duplicated DSI clk setting\n", __func__);
  3918. return rc;
  3919. }
  3920. display->cached_clk_rate = clk_rate;
  3921. rc = dsi_display_update_dsi_bitrate(display, clk_rate);
  3922. if (!rc) {
  3923. DSI_DEBUG("%s: bit clk is ready to be configured to '%d'\n",
  3924. __func__, clk_rate);
  3925. atomic_set(&display->clkrate_change_pending, 1);
  3926. } else {
  3927. DSI_ERR("%s: Failed to prepare to configure '%d'. rc = %d\n",
  3928. __func__, clk_rate, rc);
  3929. /* Caching clock failed, so don't go on doing so. */
  3930. atomic_set(&display->clkrate_change_pending, 0);
  3931. display->cached_clk_rate = 0;
  3932. }
  3933. return rc;
  3934. }
  3935. static int dsi_display_dfps_update(struct dsi_display *display,
  3936. struct dsi_display_mode *dsi_mode)
  3937. {
  3938. struct dsi_mode_info *timing;
  3939. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3940. struct dsi_display_mode *panel_mode;
  3941. struct dsi_dfps_capabilities dfps_caps;
  3942. int rc = 0;
  3943. int i = 0;
  3944. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3945. if (!display || !dsi_mode || !display->panel) {
  3946. DSI_ERR("Invalid params\n");
  3947. return -EINVAL;
  3948. }
  3949. timing = &dsi_mode->timing;
  3950. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  3951. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3952. if (!dfps_caps.dfps_support && !dyn_clk_caps->maintain_const_fps) {
  3953. DSI_ERR("dfps or constant fps not supported\n");
  3954. return -ENOTSUPP;
  3955. }
  3956. if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
  3957. DSI_ERR("dfps clock method not supported\n");
  3958. return -ENOTSUPP;
  3959. }
  3960. /* For split DSI, update the clock master first */
  3961. DSI_DEBUG("configuring seamless dynamic fps\n\n");
  3962. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  3963. m_ctrl = &display->ctrl[display->clk_master_idx];
  3964. rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
  3965. if (rc) {
  3966. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3967. display->name, i, rc);
  3968. goto error;
  3969. }
  3970. /* Update the rest of the controllers */
  3971. display_for_each_ctrl(i, display) {
  3972. ctrl = &display->ctrl[i];
  3973. if (!ctrl->ctrl || (ctrl == m_ctrl))
  3974. continue;
  3975. rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
  3976. if (rc) {
  3977. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3978. display->name, i, rc);
  3979. goto error;
  3980. }
  3981. }
  3982. panel_mode = display->panel->cur_mode;
  3983. memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
  3984. /*
  3985. * dsi_mode_flags flags are used to communicate with other drm driver
  3986. * components, and are transient. They aren't inherently part of the
  3987. * display panel's mode and shouldn't be saved into the cached currently
  3988. * active mode.
  3989. */
  3990. panel_mode->dsi_mode_flags = 0;
  3991. error:
  3992. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  3993. return rc;
  3994. }
  3995. static int dsi_display_dfps_calc_front_porch(
  3996. u32 old_fps,
  3997. u32 new_fps,
  3998. u32 a_total,
  3999. u32 b_total,
  4000. u32 b_fp,
  4001. u32 *b_fp_out)
  4002. {
  4003. s32 b_fp_new;
  4004. int add_porches, diff;
  4005. if (!b_fp_out) {
  4006. DSI_ERR("Invalid params\n");
  4007. return -EINVAL;
  4008. }
  4009. if (!a_total || !new_fps) {
  4010. DSI_ERR("Invalid pixel total or new fps in mode request\n");
  4011. return -EINVAL;
  4012. }
  4013. /*
  4014. * Keep clock, other porches constant, use new fps, calc front porch
  4015. * new_vtotal = old_vtotal * (old_fps / new_fps )
  4016. * new_vfp - old_vfp = new_vtotal - old_vtotal
  4017. * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps)
  4018. */
  4019. diff = abs(old_fps - new_fps);
  4020. add_porches = mult_frac(b_total, diff, new_fps);
  4021. if (old_fps > new_fps)
  4022. b_fp_new = b_fp + add_porches;
  4023. else
  4024. b_fp_new = b_fp - add_porches;
  4025. DSI_DEBUG("fps %u a %u b %u b_fp %u new_fp %d\n",
  4026. new_fps, a_total, b_total, b_fp, b_fp_new);
  4027. if (b_fp_new < 0) {
  4028. DSI_ERR("Invalid new_hfp calcluated%d\n", b_fp_new);
  4029. return -EINVAL;
  4030. }
  4031. /**
  4032. * TODO: To differentiate from clock method when communicating to the
  4033. * other components, perhaps we should set clk here to original value
  4034. */
  4035. *b_fp_out = b_fp_new;
  4036. return 0;
  4037. }
  4038. /**
  4039. * dsi_display_get_dfps_timing() - Get the new dfps values.
  4040. * @display: DSI display handle.
  4041. * @adj_mode: Mode value structure to be changed.
  4042. * It contains old timing values and latest fps value.
  4043. * New timing values are updated based on new fps.
  4044. * @curr_refresh_rate: Current fps rate.
  4045. * If zero , current fps rate is taken from
  4046. * display->panel->cur_mode.
  4047. * Return: error code.
  4048. */
  4049. static int dsi_display_get_dfps_timing(struct dsi_display *display,
  4050. struct dsi_display_mode *adj_mode,
  4051. u32 curr_refresh_rate)
  4052. {
  4053. struct dsi_dfps_capabilities dfps_caps;
  4054. struct dsi_display_mode per_ctrl_mode;
  4055. struct dsi_mode_info *timing;
  4056. struct dsi_ctrl *m_ctrl;
  4057. int rc = 0;
  4058. if (!display || !adj_mode) {
  4059. DSI_ERR("Invalid params\n");
  4060. return -EINVAL;
  4061. }
  4062. m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
  4063. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4064. if (!dfps_caps.dfps_support) {
  4065. DSI_ERR("dfps not supported by panel\n");
  4066. return -EINVAL;
  4067. }
  4068. per_ctrl_mode = *adj_mode;
  4069. adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
  4070. if (!curr_refresh_rate) {
  4071. if (!dsi_display_is_seamless_dfps_possible(display,
  4072. &per_ctrl_mode, dfps_caps.type)) {
  4073. DSI_ERR("seamless dynamic fps not supported for mode\n");
  4074. return -EINVAL;
  4075. }
  4076. if (display->panel->cur_mode) {
  4077. curr_refresh_rate =
  4078. display->panel->cur_mode->timing.refresh_rate;
  4079. } else {
  4080. DSI_ERR("cur_mode is not initialized\n");
  4081. return -EINVAL;
  4082. }
  4083. }
  4084. /* TODO: Remove this direct reference to the dsi_ctrl */
  4085. timing = &per_ctrl_mode.timing;
  4086. switch (dfps_caps.type) {
  4087. case DSI_DFPS_IMMEDIATE_VFP:
  4088. rc = dsi_display_dfps_calc_front_porch(
  4089. curr_refresh_rate,
  4090. timing->refresh_rate,
  4091. dsi_h_total_dce(timing),
  4092. DSI_V_TOTAL(timing),
  4093. timing->v_front_porch,
  4094. &adj_mode->timing.v_front_porch);
  4095. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, DSI_DFPS_IMMEDIATE_VFP,
  4096. curr_refresh_rate, timing->refresh_rate,
  4097. timing->v_front_porch, adj_mode->timing.v_front_porch);
  4098. break;
  4099. case DSI_DFPS_IMMEDIATE_HFP:
  4100. rc = dsi_display_dfps_calc_front_porch(
  4101. curr_refresh_rate,
  4102. timing->refresh_rate,
  4103. DSI_V_TOTAL(timing),
  4104. dsi_h_total_dce(timing),
  4105. timing->h_front_porch,
  4106. &adj_mode->timing.h_front_porch);
  4107. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, DSI_DFPS_IMMEDIATE_HFP,
  4108. curr_refresh_rate, timing->refresh_rate,
  4109. timing->h_front_porch, adj_mode->timing.h_front_porch);
  4110. if (!rc)
  4111. adj_mode->timing.h_front_porch *= display->ctrl_count;
  4112. break;
  4113. default:
  4114. DSI_ERR("Unsupported DFPS mode %d\n", dfps_caps.type);
  4115. rc = -ENOTSUPP;
  4116. }
  4117. return rc;
  4118. }
  4119. static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
  4120. struct dsi_display_mode *adj_mode)
  4121. {
  4122. int rc = 0;
  4123. if (!display || !adj_mode) {
  4124. DSI_ERR("Invalid params\n");
  4125. return false;
  4126. }
  4127. /* Currently the only seamless transition is dynamic fps */
  4128. rc = dsi_display_get_dfps_timing(display, adj_mode, 0);
  4129. if (rc) {
  4130. DSI_DEBUG("Dynamic FPS not supported for seamless\n");
  4131. } else {
  4132. DSI_DEBUG("Mode switch is seamless Dynamic FPS\n");
  4133. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS |
  4134. DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  4135. }
  4136. return rc;
  4137. }
  4138. static void dsi_display_validate_dms_fps(struct dsi_display_mode *cur_mode,
  4139. struct dsi_display_mode *to_mode)
  4140. {
  4141. u32 cur_fps, to_fps;
  4142. u32 cur_h_active, to_h_active;
  4143. u32 cur_v_active, to_v_active;
  4144. cur_fps = cur_mode->timing.refresh_rate;
  4145. to_fps = to_mode->timing.refresh_rate;
  4146. cur_h_active = cur_mode->timing.h_active;
  4147. cur_v_active = cur_mode->timing.v_active;
  4148. to_h_active = to_mode->timing.h_active;
  4149. to_v_active = to_mode->timing.v_active;
  4150. if ((cur_h_active == to_h_active) && (cur_v_active == to_v_active) &&
  4151. (cur_fps != to_fps)) {
  4152. to_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS_FPS;
  4153. DSI_DEBUG("DMS Modeset with FPS change\n");
  4154. } else {
  4155. to_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS_FPS;
  4156. }
  4157. }
  4158. static int dsi_display_set_mode_sub(struct dsi_display *display,
  4159. struct dsi_display_mode *mode,
  4160. u32 flags)
  4161. {
  4162. int rc = 0, clk_rate = 0;
  4163. int i;
  4164. struct dsi_display_ctrl *ctrl;
  4165. struct dsi_display_ctrl *mctrl;
  4166. struct dsi_display_mode_priv_info *priv_info;
  4167. bool commit_phy_timing = false;
  4168. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4169. priv_info = mode->priv_info;
  4170. if (!priv_info) {
  4171. DSI_ERR("[%s] failed to get private info of the display mode\n",
  4172. display->name);
  4173. return -EINVAL;
  4174. }
  4175. SDE_EVT32(mode->dsi_mode_flags, display->panel->panel_mode);
  4176. if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)
  4177. display->panel->panel_mode = DSI_OP_VIDEO_MODE;
  4178. else if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)
  4179. display->panel->panel_mode = DSI_OP_CMD_MODE;
  4180. rc = dsi_panel_get_host_cfg_for_mode(display->panel,
  4181. mode,
  4182. &display->config);
  4183. if (rc) {
  4184. DSI_ERR("[%s] failed to get host config for mode, rc=%d\n",
  4185. display->name, rc);
  4186. goto error;
  4187. }
  4188. memcpy(&display->config.lane_map, &display->lane_map,
  4189. sizeof(display->lane_map));
  4190. mctrl = &display->ctrl[display->clk_master_idx];
  4191. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4192. if (mode->dsi_mode_flags &
  4193. (DSI_MODE_FLAG_DFPS | DSI_MODE_FLAG_VRR)) {
  4194. display_for_each_ctrl(i, display) {
  4195. ctrl = &display->ctrl[i];
  4196. if (!ctrl->ctrl || (ctrl != mctrl))
  4197. continue;
  4198. ctrl->ctrl->hw.ops.set_timing_db(&ctrl->ctrl->hw,
  4199. true);
  4200. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  4201. if ((ctrl->ctrl->version >= DSI_CTRL_VERSION_2_5) &&
  4202. (dyn_clk_caps->maintain_const_fps)) {
  4203. dsi_phy_dynamic_refresh_trigger_sel(ctrl->phy,
  4204. true);
  4205. }
  4206. }
  4207. rc = dsi_display_dfps_update(display, mode);
  4208. if (rc) {
  4209. DSI_ERR("[%s]DSI dfps update failed, rc=%d\n",
  4210. display->name, rc);
  4211. goto error;
  4212. }
  4213. display_for_each_ctrl(i, display) {
  4214. ctrl = &display->ctrl[i];
  4215. rc = dsi_ctrl_update_host_config(ctrl->ctrl,
  4216. &display->config, mode, mode->dsi_mode_flags,
  4217. display->dsi_clk_handle);
  4218. if (rc) {
  4219. DSI_ERR("failed to update ctrl config\n");
  4220. goto error;
  4221. }
  4222. }
  4223. if (priv_info->phy_timing_len) {
  4224. display_for_each_ctrl(i, display) {
  4225. ctrl = &display->ctrl[i];
  4226. rc = dsi_phy_set_timing_params(ctrl->phy,
  4227. priv_info->phy_timing_val,
  4228. priv_info->phy_timing_len,
  4229. commit_phy_timing);
  4230. if (rc)
  4231. DSI_ERR("Fail to add timing params\n");
  4232. }
  4233. }
  4234. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))
  4235. return rc;
  4236. }
  4237. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) {
  4238. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  4239. rc = dsi_display_dynamic_clk_switch_vid(display, mode);
  4240. if (rc)
  4241. DSI_ERR("dynamic clk change failed %d\n", rc);
  4242. /*
  4243. * skip rest of the opearations since
  4244. * dsi_display_dynamic_clk_switch_vid() already takes
  4245. * care of them.
  4246. */
  4247. return rc;
  4248. } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4249. clk_rate = mode->timing.clk_rate_hz;
  4250. rc = dsi_display_dynamic_clk_configure_cmd(display,
  4251. clk_rate);
  4252. if (rc) {
  4253. DSI_ERR("Failed to configure dynamic clk\n");
  4254. return rc;
  4255. }
  4256. }
  4257. }
  4258. display_for_each_ctrl(i, display) {
  4259. ctrl = &display->ctrl[i];
  4260. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
  4261. mode, mode->dsi_mode_flags,
  4262. display->dsi_clk_handle);
  4263. if (rc) {
  4264. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n",
  4265. display->name, rc);
  4266. goto error;
  4267. }
  4268. }
  4269. if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  4270. (display->panel->panel_mode == DSI_OP_CMD_MODE)) {
  4271. u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
  4272. u64 to_bitclk = mode->timing.clk_rate_hz;
  4273. commit_phy_timing = true;
  4274. /* No need to set clkrate pending flag if clocks are same */
  4275. if ((!cur_bitclk && !to_bitclk) || (cur_bitclk != to_bitclk))
  4276. atomic_set(&display->clkrate_change_pending, 1);
  4277. dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
  4278. }
  4279. if (priv_info->phy_timing_len) {
  4280. display_for_each_ctrl(i, display) {
  4281. ctrl = &display->ctrl[i];
  4282. rc = dsi_phy_set_timing_params(ctrl->phy,
  4283. priv_info->phy_timing_val,
  4284. priv_info->phy_timing_len,
  4285. commit_phy_timing);
  4286. if (rc)
  4287. DSI_ERR("failed to add DSI PHY timing params\n");
  4288. }
  4289. }
  4290. error:
  4291. return rc;
  4292. }
  4293. /**
  4294. * _dsi_display_dev_init - initializes the display device
  4295. * Initialization will acquire references to the resources required for the
  4296. * display hardware to function.
  4297. * @display: Handle to the display
  4298. * Returns: Zero on success
  4299. */
  4300. static int _dsi_display_dev_init(struct dsi_display *display)
  4301. {
  4302. int rc = 0;
  4303. if (!display) {
  4304. DSI_ERR("invalid display\n");
  4305. return -EINVAL;
  4306. }
  4307. if (!display->panel_node && !display->fw)
  4308. return 0;
  4309. mutex_lock(&display->display_lock);
  4310. display->parser = dsi_parser_get(&display->pdev->dev);
  4311. if (display->fw && display->parser)
  4312. display->parser_node = dsi_parser_get_head_node(
  4313. display->parser, display->fw->data,
  4314. display->fw->size);
  4315. rc = dsi_display_res_init(display);
  4316. if (rc) {
  4317. DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
  4318. display->name, rc);
  4319. goto error;
  4320. }
  4321. error:
  4322. mutex_unlock(&display->display_lock);
  4323. return rc;
  4324. }
  4325. /**
  4326. * _dsi_display_dev_deinit - deinitializes the display device
  4327. * All the resources acquired during device init will be released.
  4328. * @display: Handle to the display
  4329. * Returns: Zero on success
  4330. */
  4331. static int _dsi_display_dev_deinit(struct dsi_display *display)
  4332. {
  4333. int rc = 0;
  4334. if (!display) {
  4335. DSI_ERR("invalid display\n");
  4336. return -EINVAL;
  4337. }
  4338. mutex_lock(&display->display_lock);
  4339. rc = dsi_display_res_deinit(display);
  4340. if (rc)
  4341. DSI_ERR("[%s] failed to deinitialize resource, rc=%d\n",
  4342. display->name, rc);
  4343. mutex_unlock(&display->display_lock);
  4344. return rc;
  4345. }
  4346. /**
  4347. * dsi_display_cont_splash_res_disable() - Disable resource votes added in probe
  4348. * @dsi_display: Pointer to dsi display
  4349. * Returns: Zero on success
  4350. */
  4351. int dsi_display_cont_splash_res_disable(void *dsi_display)
  4352. {
  4353. struct dsi_display *display = dsi_display;
  4354. int rc = 0;
  4355. /* Remove the panel vote that was added during dsi display probe */
  4356. rc = dsi_pwr_enable_regulator(&display->panel->power_info, false);
  4357. if (rc)
  4358. DSI_ERR("[%s] failed to disable vregs, rc=%d\n",
  4359. display->panel->name, rc);
  4360. return rc;
  4361. }
  4362. /**
  4363. * dsi_display_cont_splash_config() - Initialize resources for continuous splash
  4364. * @dsi_display: Pointer to dsi display
  4365. * Returns: Zero on success
  4366. */
  4367. int dsi_display_cont_splash_config(void *dsi_display)
  4368. {
  4369. struct dsi_display *display = dsi_display;
  4370. int rc = 0;
  4371. /* Vote for gdsc required to read register address space */
  4372. if (!display) {
  4373. DSI_ERR("invalid input display param\n");
  4374. return -EINVAL;
  4375. }
  4376. rc = pm_runtime_get_sync(display->drm_dev->dev);
  4377. if (rc < 0) {
  4378. DSI_ERR("failed to vote gdsc for continuous splash, rc=%d\n",
  4379. rc);
  4380. return rc;
  4381. }
  4382. mutex_lock(&display->display_lock);
  4383. display->is_cont_splash_enabled = true;
  4384. /* Update splash status for clock manager */
  4385. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4386. display->is_cont_splash_enabled);
  4387. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, display->is_cont_splash_enabled);
  4388. /* Set up ctrl isr before enabling core clk */
  4389. dsi_display_ctrl_isr_configure(display, true);
  4390. /* Vote for Core clk and link clk. Votes on ctrl and phy
  4391. * regulator are inplicit from pre clk on callback
  4392. */
  4393. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4394. DSI_ALL_CLKS, DSI_CLK_ON);
  4395. if (rc) {
  4396. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  4397. display->name, rc);
  4398. goto clk_manager_update;
  4399. }
  4400. mutex_unlock(&display->display_lock);
  4401. /* Set the current brightness level */
  4402. dsi_panel_bl_handoff(display->panel);
  4403. return rc;
  4404. clk_manager_update:
  4405. dsi_display_ctrl_isr_configure(display, false);
  4406. /* Update splash status for clock manager */
  4407. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4408. false);
  4409. pm_runtime_put_sync(display->drm_dev->dev);
  4410. display->is_cont_splash_enabled = false;
  4411. mutex_unlock(&display->display_lock);
  4412. return rc;
  4413. }
  4414. /**
  4415. * dsi_display_splash_res_cleanup() - cleanup for continuous splash
  4416. * @display: Pointer to dsi display
  4417. * Returns: Zero on success
  4418. */
  4419. int dsi_display_splash_res_cleanup(struct dsi_display *display)
  4420. {
  4421. int rc = 0;
  4422. if (!display->is_cont_splash_enabled)
  4423. return 0;
  4424. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4425. DSI_ALL_CLKS, DSI_CLK_OFF);
  4426. if (rc)
  4427. DSI_ERR("[%s] failed to disable DSI link clocks, rc=%d\n",
  4428. display->name, rc);
  4429. pm_runtime_put_sync(display->drm_dev->dev);
  4430. display->is_cont_splash_enabled = false;
  4431. /* Update splash status for clock manager */
  4432. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4433. display->is_cont_splash_enabled);
  4434. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, display->is_cont_splash_enabled);
  4435. return rc;
  4436. }
  4437. static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
  4438. {
  4439. int rc = 0;
  4440. rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
  4441. if (!rc) {
  4442. DSI_DEBUG("dsi bit clk has been configured to %d\n",
  4443. display->cached_clk_rate);
  4444. atomic_set(&display->clkrate_change_pending, 0);
  4445. } else {
  4446. DSI_ERR("Failed to configure dsi bit clock '%d'. rc = %d\n",
  4447. display->cached_clk_rate, rc);
  4448. }
  4449. return rc;
  4450. }
  4451. static int dsi_display_validate_split_link(struct dsi_display *display)
  4452. {
  4453. int i, rc = 0;
  4454. struct dsi_display_ctrl *ctrl;
  4455. struct dsi_host_common_cfg *host = &display->panel->host_config;
  4456. if (!host->split_link.split_link_enabled)
  4457. return 0;
  4458. if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4459. DSI_ERR("[%s] split link is not supported in command mode\n",
  4460. display->name);
  4461. rc = -ENOTSUPP;
  4462. goto error;
  4463. }
  4464. display_for_each_ctrl(i, display) {
  4465. ctrl = &display->ctrl[i];
  4466. if (!ctrl->ctrl->split_link_supported) {
  4467. DSI_ERR("[%s] split link is not supported by hw\n",
  4468. display->name);
  4469. rc = -ENOTSUPP;
  4470. goto error;
  4471. }
  4472. set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
  4473. }
  4474. DSI_DEBUG("Split link is enabled\n");
  4475. return 0;
  4476. error:
  4477. host->split_link.split_link_enabled = false;
  4478. return rc;
  4479. }
  4480. static int dsi_display_get_io_resources(struct msm_io_res *io_res, void *data)
  4481. {
  4482. int rc = 0;
  4483. struct dsi_display *display;
  4484. if (!data)
  4485. return -EINVAL;
  4486. rc = dsi_ctrl_get_io_resources(io_res);
  4487. if (rc)
  4488. goto end;
  4489. rc = dsi_phy_get_io_resources(io_res);
  4490. if (rc)
  4491. goto end;
  4492. display = (struct dsi_display *)data;
  4493. rc = dsi_panel_get_io_resources(display->panel, io_res);
  4494. end:
  4495. return rc;
  4496. }
  4497. static int dsi_display_pre_release(void *data)
  4498. {
  4499. if (!data)
  4500. return -EINVAL;
  4501. dsi_display_ctrl_irq_update((struct dsi_display *)data, false);
  4502. return 0;
  4503. }
  4504. static int dsi_display_pre_acquire(void *data)
  4505. {
  4506. if (!data)
  4507. return -EINVAL;
  4508. dsi_display_ctrl_irq_update((struct dsi_display *)data, true);
  4509. return 0;
  4510. }
  4511. /**
  4512. * dsi_display_bind - bind dsi device with controlling device
  4513. * @dev: Pointer to base of platform device
  4514. * @master: Pointer to container of drm device
  4515. * @data: Pointer to private data
  4516. * Returns: Zero on success
  4517. */
  4518. static int dsi_display_bind(struct device *dev,
  4519. struct device *master,
  4520. void *data)
  4521. {
  4522. struct dsi_display_ctrl *display_ctrl;
  4523. struct drm_device *drm;
  4524. struct dsi_display *display;
  4525. struct dsi_clk_info info;
  4526. struct clk_ctrl_cb clk_cb;
  4527. void *handle = NULL;
  4528. struct platform_device *pdev = to_platform_device(dev);
  4529. char *client1 = "dsi_clk_client";
  4530. char *client2 = "mdp_event_client";
  4531. struct msm_vm_ops vm_event_ops = {
  4532. .vm_get_io_resources = dsi_display_get_io_resources,
  4533. .vm_pre_hw_release = dsi_display_pre_release,
  4534. .vm_post_hw_acquire = dsi_display_pre_acquire,
  4535. };
  4536. int i, rc = 0;
  4537. if (!dev || !pdev || !master) {
  4538. DSI_ERR("invalid param(s), dev %pK, pdev %pK, master %pK\n",
  4539. dev, pdev, master);
  4540. return -EINVAL;
  4541. }
  4542. drm = dev_get_drvdata(master);
  4543. display = platform_get_drvdata(pdev);
  4544. if (!drm || !display) {
  4545. DSI_ERR("invalid param(s), drm %pK, display %pK\n",
  4546. drm, display);
  4547. return -EINVAL;
  4548. }
  4549. if (!display->panel_node && !display->fw)
  4550. return 0;
  4551. if (!display->fw)
  4552. display->name = display->panel_node->name;
  4553. /* defer bind if ext bridge driver is not loaded */
  4554. if (display->panel && display->panel->host_config.ext_bridge_mode) {
  4555. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4556. if (!of_drm_find_bridge(
  4557. display->ext_bridge[i].node_of)) {
  4558. DSI_DEBUG("defer for bridge[%d] %s\n", i,
  4559. display->ext_bridge[i].node_of->full_name);
  4560. return -EPROBE_DEFER;
  4561. }
  4562. }
  4563. }
  4564. mutex_lock(&display->display_lock);
  4565. rc = dsi_display_validate_split_link(display);
  4566. if (rc) {
  4567. DSI_ERR("[%s] split link validation failed, rc=%d\n",
  4568. display->name, rc);
  4569. goto error;
  4570. }
  4571. rc = dsi_display_debugfs_init(display);
  4572. if (rc) {
  4573. DSI_ERR("[%s] debugfs init failed, rc=%d\n", display->name, rc);
  4574. goto error;
  4575. }
  4576. atomic_set(&display->clkrate_change_pending, 0);
  4577. display->cached_clk_rate = 0;
  4578. memset(&info, 0x0, sizeof(info));
  4579. display_for_each_ctrl(i, display) {
  4580. display_ctrl = &display->ctrl[i];
  4581. rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
  4582. if (rc) {
  4583. DSI_ERR("[%s] failed to initialize ctrl[%d], rc=%d\n",
  4584. display->name, i, rc);
  4585. goto error_ctrl_deinit;
  4586. }
  4587. display_ctrl->ctrl->horiz_index = i;
  4588. rc = dsi_phy_drv_init(display_ctrl->phy);
  4589. if (rc) {
  4590. DSI_ERR("[%s] Failed to initialize phy[%d], rc=%d\n",
  4591. display->name, i, rc);
  4592. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4593. goto error_ctrl_deinit;
  4594. }
  4595. display_ctrl->ctrl->dma_cmd_workq = display->dma_cmd_workq;
  4596. memcpy(&info.c_clks[i],
  4597. (&display_ctrl->ctrl->clk_info.core_clks),
  4598. sizeof(struct dsi_core_clk_info));
  4599. memcpy(&info.l_hs_clks[i],
  4600. (&display_ctrl->ctrl->clk_info.hs_link_clks),
  4601. sizeof(struct dsi_link_hs_clk_info));
  4602. memcpy(&info.l_lp_clks[i],
  4603. (&display_ctrl->ctrl->clk_info.lp_link_clks),
  4604. sizeof(struct dsi_link_lp_clk_info));
  4605. info.c_clks[i].drm = drm;
  4606. info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
  4607. }
  4608. info.pre_clkoff_cb = dsi_pre_clkoff_cb;
  4609. info.pre_clkon_cb = dsi_pre_clkon_cb;
  4610. info.post_clkoff_cb = dsi_post_clkoff_cb;
  4611. info.post_clkon_cb = dsi_post_clkon_cb;
  4612. info.phy_config_cb = dsi_display_phy_configure;
  4613. info.phy_pll_toggle_cb = dsi_display_phy_pll_toggle;
  4614. info.priv_data = display;
  4615. info.master_ndx = display->clk_master_idx;
  4616. info.dsi_ctrl_count = display->ctrl_count;
  4617. snprintf(info.name, MAX_STRING_LEN,
  4618. "DSI_MNGR-%s", display->name);
  4619. display->clk_mngr = dsi_display_clk_mngr_register(&info);
  4620. if (IS_ERR_OR_NULL(display->clk_mngr)) {
  4621. rc = PTR_ERR(display->clk_mngr);
  4622. display->clk_mngr = NULL;
  4623. DSI_ERR("dsi clock registration failed, rc = %d\n", rc);
  4624. goto error_ctrl_deinit;
  4625. }
  4626. handle = dsi_register_clk_handle(display->clk_mngr, client1);
  4627. if (IS_ERR_OR_NULL(handle)) {
  4628. rc = PTR_ERR(handle);
  4629. DSI_ERR("failed to register %s client, rc = %d\n",
  4630. client1, rc);
  4631. goto error_clk_deinit;
  4632. } else {
  4633. display->dsi_clk_handle = handle;
  4634. }
  4635. handle = dsi_register_clk_handle(display->clk_mngr, client2);
  4636. if (IS_ERR_OR_NULL(handle)) {
  4637. rc = PTR_ERR(handle);
  4638. DSI_ERR("failed to register %s client, rc = %d\n",
  4639. client2, rc);
  4640. goto error_clk_client_deinit;
  4641. } else {
  4642. display->mdp_clk_handle = handle;
  4643. }
  4644. clk_cb.priv = display;
  4645. clk_cb.dsi_clk_cb = dsi_display_clk_ctrl_cb;
  4646. display_for_each_ctrl(i, display) {
  4647. display_ctrl = &display->ctrl[i];
  4648. rc = dsi_ctrl_clk_cb_register(display_ctrl->ctrl, &clk_cb);
  4649. if (rc) {
  4650. DSI_ERR("[%s] failed to register ctrl clk_cb[%d], rc=%d\n",
  4651. display->name, i, rc);
  4652. goto error_ctrl_deinit;
  4653. }
  4654. rc = dsi_phy_clk_cb_register(display_ctrl->phy, &clk_cb);
  4655. if (rc) {
  4656. DSI_ERR("[%s] failed to register phy clk_cb[%d], rc=%d\n",
  4657. display->name, i, rc);
  4658. goto error_ctrl_deinit;
  4659. }
  4660. }
  4661. dsi_display_update_byte_intf_div(display);
  4662. rc = dsi_display_mipi_host_init(display);
  4663. if (rc) {
  4664. DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",
  4665. display->name, rc);
  4666. goto error_ctrl_deinit;
  4667. }
  4668. rc = dsi_panel_drv_init(display->panel, &display->host);
  4669. if (rc) {
  4670. if (rc != -EPROBE_DEFER)
  4671. DSI_ERR("[%s] failed to initialize panel driver, rc=%d\n",
  4672. display->name, rc);
  4673. goto error_host_deinit;
  4674. }
  4675. DSI_INFO("Successfully bind display panel '%s'\n", display->name);
  4676. display->drm_dev = drm;
  4677. display_for_each_ctrl(i, display) {
  4678. display_ctrl = &display->ctrl[i];
  4679. if (!display_ctrl->phy || !display_ctrl->ctrl)
  4680. continue;
  4681. display_ctrl->ctrl->drm_dev = drm;
  4682. rc = dsi_phy_set_clk_freq(display_ctrl->phy,
  4683. &display_ctrl->ctrl->clk_freq);
  4684. if (rc) {
  4685. DSI_ERR("[%s] failed to set phy clk freq, rc=%d\n",
  4686. display->name, rc);
  4687. goto error;
  4688. }
  4689. }
  4690. /* register te irq handler */
  4691. dsi_display_register_te_irq(display);
  4692. msm_register_vm_event(master, dev, &vm_event_ops, (void *)display);
  4693. goto error;
  4694. error_host_deinit:
  4695. (void)dsi_display_mipi_host_deinit(display);
  4696. error_clk_client_deinit:
  4697. (void)dsi_deregister_clk_handle(display->dsi_clk_handle);
  4698. error_clk_deinit:
  4699. (void)dsi_display_clk_mngr_deregister(display->clk_mngr);
  4700. error_ctrl_deinit:
  4701. for (i = i - 1; i >= 0; i--) {
  4702. display_ctrl = &display->ctrl[i];
  4703. (void)dsi_phy_drv_deinit(display_ctrl->phy);
  4704. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4705. }
  4706. (void)dsi_display_debugfs_deinit(display);
  4707. error:
  4708. mutex_unlock(&display->display_lock);
  4709. return rc;
  4710. }
  4711. /**
  4712. * dsi_display_unbind - unbind dsi from controlling device
  4713. * @dev: Pointer to base of platform device
  4714. * @master: Pointer to container of drm device
  4715. * @data: Pointer to private data
  4716. */
  4717. static void dsi_display_unbind(struct device *dev,
  4718. struct device *master, void *data)
  4719. {
  4720. struct dsi_display_ctrl *display_ctrl;
  4721. struct dsi_display *display;
  4722. struct platform_device *pdev = to_platform_device(dev);
  4723. int i, rc = 0;
  4724. if (!dev || !pdev || !master) {
  4725. DSI_ERR("invalid param(s)\n");
  4726. return;
  4727. }
  4728. display = platform_get_drvdata(pdev);
  4729. if (!display || !display->panel_node) {
  4730. DSI_ERR("invalid display\n");
  4731. return;
  4732. }
  4733. mutex_lock(&display->display_lock);
  4734. rc = dsi_display_mipi_host_deinit(display);
  4735. if (rc)
  4736. DSI_ERR("[%s] failed to deinit mipi hosts, rc=%d\n",
  4737. display->name,
  4738. rc);
  4739. display_for_each_ctrl(i, display) {
  4740. display_ctrl = &display->ctrl[i];
  4741. rc = dsi_phy_drv_deinit(display_ctrl->phy);
  4742. if (rc)
  4743. DSI_ERR("[%s] failed to deinit phy%d driver, rc=%d\n",
  4744. display->name, i, rc);
  4745. display->ctrl->ctrl->dma_cmd_workq = NULL;
  4746. rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4747. if (rc)
  4748. DSI_ERR("[%s] failed to deinit ctrl%d driver, rc=%d\n",
  4749. display->name, i, rc);
  4750. }
  4751. atomic_set(&display->clkrate_change_pending, 0);
  4752. (void)dsi_display_debugfs_deinit(display);
  4753. mutex_unlock(&display->display_lock);
  4754. }
  4755. static const struct component_ops dsi_display_comp_ops = {
  4756. .bind = dsi_display_bind,
  4757. .unbind = dsi_display_unbind,
  4758. };
  4759. static struct platform_driver dsi_display_driver = {
  4760. .probe = dsi_display_dev_probe,
  4761. .remove = dsi_display_dev_remove,
  4762. .driver = {
  4763. .name = "msm-dsi-display",
  4764. .of_match_table = dsi_display_dt_match,
  4765. .suppress_bind_attrs = true,
  4766. },
  4767. };
  4768. static int dsi_display_init(struct dsi_display *display)
  4769. {
  4770. int rc = 0;
  4771. struct platform_device *pdev = display->pdev;
  4772. rc = _dsi_display_dev_init(display);
  4773. if (rc) {
  4774. DSI_ERR("device init failed, rc=%d\n", rc);
  4775. goto end;
  4776. }
  4777. /*
  4778. * Vote on panel regulator is added to make sure panel regulators
  4779. * are ON for cont-splash enabled usecase.
  4780. * This panel regulator vote will be removed only in:
  4781. * 1) device suspend when cont-splash is enabled.
  4782. * 2) cont_splash_res_disable() when cont-splash is disabled.
  4783. * For GKI, adding this vote will make sure that sync_state
  4784. * kernel driver doesn't disable the panel regulators after
  4785. * dsi probe is complete.
  4786. */
  4787. if (display->panel) {
  4788. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4789. true);
  4790. if (rc) {
  4791. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4792. display->panel->name, rc);
  4793. return rc;
  4794. }
  4795. }
  4796. rc = component_add(&pdev->dev, &dsi_display_comp_ops);
  4797. if (rc)
  4798. DSI_ERR("component add failed, rc=%d\n", rc);
  4799. DSI_DEBUG("component add success: %s\n", display->name);
  4800. end:
  4801. return rc;
  4802. }
  4803. static void dsi_display_firmware_display(const struct firmware *fw,
  4804. void *context)
  4805. {
  4806. struct dsi_display *display = context;
  4807. if (fw) {
  4808. DSI_INFO("reading data from firmware, size=%zd\n",
  4809. fw->size);
  4810. display->fw = fw;
  4811. if (!strcmp(display->display_type, "primary"))
  4812. display->name = "dsi_firmware_display";
  4813. else if (!strcmp(display->display_type, "secondary"))
  4814. display->name = "dsi_firmware_display_secondary";
  4815. } else {
  4816. DSI_INFO("no firmware available, fallback to device node\n");
  4817. }
  4818. if (dsi_display_init(display))
  4819. return;
  4820. DSI_DEBUG("success\n");
  4821. }
  4822. int dsi_display_dev_probe(struct platform_device *pdev)
  4823. {
  4824. struct dsi_display *display = NULL;
  4825. struct device_node *node = NULL, *panel_node = NULL, *mdp_node = NULL;
  4826. int rc = 0, index = DSI_PRIMARY;
  4827. bool firm_req = false;
  4828. struct dsi_display_boot_param *boot_disp;
  4829. if (!pdev || !pdev->dev.of_node) {
  4830. DSI_ERR("pdev not found\n");
  4831. rc = -ENODEV;
  4832. goto end;
  4833. }
  4834. display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
  4835. if (!display) {
  4836. rc = -ENOMEM;
  4837. goto end;
  4838. }
  4839. mutex_init(&display->display_lock);
  4840. display->dma_cmd_workq = create_singlethread_workqueue(
  4841. "dsi_dma_cmd_workq");
  4842. if (!display->dma_cmd_workq) {
  4843. DSI_ERR("failed to create work queue\n");
  4844. rc = -EINVAL;
  4845. goto end;
  4846. }
  4847. mdp_node = of_parse_phandle(pdev->dev.of_node, "qcom,mdp", 0);
  4848. if (!mdp_node) {
  4849. DSI_ERR("mdp_node not found\n");
  4850. rc = -ENODEV;
  4851. goto end;
  4852. }
  4853. display->trusted_vm_env = of_property_read_bool(mdp_node,
  4854. "qcom,sde-trusted-vm-env");
  4855. if (display->trusted_vm_env)
  4856. DSI_INFO("Display enabled with trusted vm path\n");
  4857. /* initialize panel id to UINT64_MAX */
  4858. display->panel_id = ~0x0;
  4859. display->display_type = of_get_property(pdev->dev.of_node,
  4860. "label", NULL);
  4861. if (!display->display_type)
  4862. display->display_type = "primary";
  4863. if (!strcmp(display->display_type, "secondary"))
  4864. index = DSI_SECONDARY;
  4865. boot_disp = &boot_displays[index];
  4866. node = pdev->dev.of_node;
  4867. if (boot_disp->boot_disp_en) {
  4868. /* The panel name should be same as UEFI name index */
  4869. panel_node = of_find_node_by_name(mdp_node, boot_disp->name);
  4870. if (!panel_node)
  4871. DSI_WARN("panel_node %s not found\n", boot_disp->name);
  4872. } else {
  4873. panel_node = of_parse_phandle(node,
  4874. "qcom,dsi-default-panel", 0);
  4875. if (!panel_node)
  4876. DSI_WARN("default panel not found\n");
  4877. }
  4878. boot_disp->node = pdev->dev.of_node;
  4879. boot_disp->disp = display;
  4880. display->panel_node = panel_node;
  4881. display->pdev = pdev;
  4882. display->boot_disp = boot_disp;
  4883. dsi_display_parse_cmdline_topology(display, index);
  4884. platform_set_drvdata(pdev, display);
  4885. rc = dsi_display_parse_dt(display);
  4886. if (rc) {
  4887. DSI_ERR("[%s] failed to parse dt, rc=%d\n", display->name, rc);
  4888. goto end;
  4889. }
  4890. rc = dsi_display_validate_resources(display);
  4891. if (rc) {
  4892. DSI_ERR("[%s] needed resources not probed yet, rc=%d\n",
  4893. display->name, rc);
  4894. goto end;
  4895. }
  4896. /* initialize display in firmware callback */
  4897. if (!boot_disp->boot_disp_en &&
  4898. IS_ENABLED(CONFIG_DSI_PARSER) &&
  4899. !display->trusted_vm_env) {
  4900. if (!strcmp(display->display_type, "primary"))
  4901. firm_req = !request_firmware_nowait(
  4902. THIS_MODULE, 1, "dsi_prop",
  4903. &pdev->dev, GFP_KERNEL, display,
  4904. dsi_display_firmware_display);
  4905. else if (!strcmp(display->display_type, "secondary"))
  4906. firm_req = !request_firmware_nowait(
  4907. THIS_MODULE, 1, "dsi_prop_sec",
  4908. &pdev->dev, GFP_KERNEL, display,
  4909. dsi_display_firmware_display);
  4910. }
  4911. if (!firm_req) {
  4912. rc = dsi_display_init(display);
  4913. if (rc)
  4914. goto end;
  4915. }
  4916. return 0;
  4917. end:
  4918. if (display) {
  4919. mutex_destroy(&display->display_lock);
  4920. devm_kfree(&pdev->dev, display);
  4921. }
  4922. return rc;
  4923. }
  4924. int dsi_display_dev_remove(struct platform_device *pdev)
  4925. {
  4926. int rc = 0, i = 0;
  4927. struct dsi_display *display;
  4928. struct dsi_display_ctrl *ctrl;
  4929. if (!pdev) {
  4930. DSI_ERR("Invalid device\n");
  4931. return -EINVAL;
  4932. }
  4933. display = platform_get_drvdata(pdev);
  4934. /* decrement ref count */
  4935. of_node_put(display->panel_node);
  4936. if (display->dma_cmd_workq) {
  4937. flush_workqueue(display->dma_cmd_workq);
  4938. destroy_workqueue(display->dma_cmd_workq);
  4939. display->dma_cmd_workq = NULL;
  4940. display_for_each_ctrl(i, display) {
  4941. ctrl = &display->ctrl[i];
  4942. if (!ctrl->ctrl)
  4943. continue;
  4944. ctrl->ctrl->dma_cmd_workq = NULL;
  4945. }
  4946. }
  4947. (void)_dsi_display_dev_deinit(display);
  4948. platform_set_drvdata(pdev, NULL);
  4949. devm_kfree(&pdev->dev, display);
  4950. return rc;
  4951. }
  4952. int dsi_display_get_num_of_displays(void)
  4953. {
  4954. int i, count = 0;
  4955. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  4956. struct dsi_display *display = boot_displays[i].disp;
  4957. if ((display && display->panel_node) ||
  4958. (display && display->fw))
  4959. count++;
  4960. }
  4961. return count;
  4962. }
  4963. int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
  4964. {
  4965. int index = 0, count = 0;
  4966. if (!display_array || !max_display_count) {
  4967. DSI_ERR("invalid params\n");
  4968. return 0;
  4969. }
  4970. for (index = 0; index < MAX_DSI_ACTIVE_DISPLAY; index++) {
  4971. struct dsi_display *display = boot_displays[index].disp;
  4972. if ((display && display->panel_node) ||
  4973. (display && display->fw))
  4974. display_array[count++] = display;
  4975. }
  4976. return count;
  4977. }
  4978. void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
  4979. {
  4980. if (!display)
  4981. return;
  4982. mutex_lock(&display->display_lock);
  4983. display->is_active = is_active;
  4984. mutex_unlock(&display->display_lock);
  4985. }
  4986. int dsi_display_drm_bridge_init(struct dsi_display *display,
  4987. struct drm_encoder *enc)
  4988. {
  4989. int rc = 0;
  4990. struct dsi_bridge *bridge;
  4991. struct msm_drm_private *priv = NULL;
  4992. if (!display || !display->drm_dev || !enc) {
  4993. DSI_ERR("invalid param(s)\n");
  4994. return -EINVAL;
  4995. }
  4996. mutex_lock(&display->display_lock);
  4997. priv = display->drm_dev->dev_private;
  4998. if (!priv) {
  4999. DSI_ERR("Private data is not present\n");
  5000. rc = -EINVAL;
  5001. goto error;
  5002. }
  5003. if (display->bridge) {
  5004. DSI_ERR("display is already initialize\n");
  5005. goto error;
  5006. }
  5007. bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
  5008. if (IS_ERR_OR_NULL(bridge)) {
  5009. rc = PTR_ERR(bridge);
  5010. DSI_ERR("[%s] brige init failed, %d\n", display->name, rc);
  5011. goto error;
  5012. }
  5013. display->bridge = bridge;
  5014. priv->bridges[priv->num_bridges++] = &bridge->base;
  5015. if (display->tx_cmd_buf == NULL) {
  5016. rc = dsi_host_alloc_cmd_tx_buffer(display);
  5017. if (rc)
  5018. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  5019. }
  5020. error:
  5021. mutex_unlock(&display->display_lock);
  5022. return rc;
  5023. }
  5024. int dsi_display_drm_bridge_deinit(struct dsi_display *display)
  5025. {
  5026. int rc = 0;
  5027. if (!display) {
  5028. DSI_ERR("Invalid params\n");
  5029. return -EINVAL;
  5030. }
  5031. mutex_lock(&display->display_lock);
  5032. dsi_drm_bridge_cleanup(display->bridge);
  5033. display->bridge = NULL;
  5034. mutex_unlock(&display->display_lock);
  5035. return rc;
  5036. }
  5037. /* Hook functions to call external connector, pointer validation is
  5038. * done in dsi_display_drm_ext_bridge_init.
  5039. */
  5040. static enum drm_connector_status dsi_display_drm_ext_detect(
  5041. struct drm_connector *connector,
  5042. bool force,
  5043. void *disp)
  5044. {
  5045. struct dsi_display *display = disp;
  5046. return display->ext_conn->funcs->detect(display->ext_conn, force);
  5047. }
  5048. static int dsi_display_drm_ext_get_modes(
  5049. struct drm_connector *connector, void *disp,
  5050. const struct msm_resource_caps_info *avail_res)
  5051. {
  5052. struct dsi_display *display = disp;
  5053. struct drm_display_mode *pmode, *pt;
  5054. int count;
  5055. /* if there are modes defined in panel, ignore external modes */
  5056. if (display->panel->num_timing_nodes)
  5057. return dsi_connector_get_modes(connector, disp, avail_res);
  5058. count = display->ext_conn->helper_private->get_modes(
  5059. display->ext_conn);
  5060. list_for_each_entry_safe(pmode, pt,
  5061. &display->ext_conn->probed_modes, head) {
  5062. list_move_tail(&pmode->head, &connector->probed_modes);
  5063. }
  5064. connector->display_info = display->ext_conn->display_info;
  5065. return count;
  5066. }
  5067. static enum drm_mode_status dsi_display_drm_ext_mode_valid(
  5068. struct drm_connector *connector,
  5069. struct drm_display_mode *mode,
  5070. void *disp, const struct msm_resource_caps_info *avail_res)
  5071. {
  5072. struct dsi_display *display = disp;
  5073. enum drm_mode_status status;
  5074. /* always do internal mode_valid check */
  5075. status = dsi_conn_mode_valid(connector, mode, disp, avail_res);
  5076. if (status != MODE_OK)
  5077. return status;
  5078. return display->ext_conn->helper_private->mode_valid(
  5079. display->ext_conn, mode);
  5080. }
  5081. static int dsi_display_drm_ext_atomic_check(struct drm_connector *connector,
  5082. void *disp,
  5083. struct drm_atomic_state *state)
  5084. {
  5085. struct dsi_display *display = disp;
  5086. struct drm_connector_state *c_state;
  5087. c_state = drm_atomic_get_new_connector_state(state, connector);
  5088. return display->ext_conn->helper_private->atomic_check(
  5089. display->ext_conn, state);
  5090. }
  5091. static int dsi_display_ext_get_info(struct drm_connector *connector,
  5092. struct msm_display_info *info, void *disp)
  5093. {
  5094. struct dsi_display *display;
  5095. int i;
  5096. if (!info || !disp) {
  5097. DSI_ERR("invalid params\n");
  5098. return -EINVAL;
  5099. }
  5100. display = disp;
  5101. if (!display->panel) {
  5102. DSI_ERR("invalid display panel\n");
  5103. return -EINVAL;
  5104. }
  5105. mutex_lock(&display->display_lock);
  5106. memset(info, 0, sizeof(struct msm_display_info));
  5107. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5108. info->num_of_h_tiles = display->ctrl_count;
  5109. for (i = 0; i < info->num_of_h_tiles; i++)
  5110. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5111. info->is_connected = connector->status != connector_status_disconnected;
  5112. if (!strcmp(display->display_type, "primary"))
  5113. info->display_type = SDE_CONNECTOR_PRIMARY;
  5114. else if (!strcmp(display->display_type, "secondary"))
  5115. info->display_type = SDE_CONNECTOR_SECONDARY;
  5116. info->capabilities |= (MSM_DISPLAY_CAP_VID_MODE |
  5117. MSM_DISPLAY_CAP_EDID | MSM_DISPLAY_CAP_HOT_PLUG);
  5118. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5119. mutex_unlock(&display->display_lock);
  5120. return 0;
  5121. }
  5122. static int dsi_display_ext_get_mode_info(struct drm_connector *connector,
  5123. const struct drm_display_mode *drm_mode,
  5124. struct msm_mode_info *mode_info,
  5125. void *display, const struct msm_resource_caps_info *avail_res)
  5126. {
  5127. struct msm_display_topology *topology;
  5128. if (!drm_mode || !mode_info ||
  5129. !avail_res || !avail_res->max_mixer_width)
  5130. return -EINVAL;
  5131. memset(mode_info, 0, sizeof(*mode_info));
  5132. mode_info->frame_rate = drm_mode_vrefresh(drm_mode);
  5133. mode_info->vtotal = drm_mode->vtotal;
  5134. topology = &mode_info->topology;
  5135. topology->num_lm = (avail_res->max_mixer_width
  5136. <= drm_mode->hdisplay) ? 2 : 1;
  5137. topology->num_enc = 0;
  5138. topology->num_intf = topology->num_lm;
  5139. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  5140. return 0;
  5141. }
  5142. static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
  5143. struct drm_bridge *bridge)
  5144. {
  5145. struct msm_drm_private *priv;
  5146. struct sde_kms *sde_kms;
  5147. struct drm_connector *conn;
  5148. struct drm_connector_list_iter conn_iter;
  5149. struct sde_connector *sde_conn;
  5150. struct dsi_display *display;
  5151. struct dsi_display_ext_bridge *dsi_bridge = NULL;
  5152. int i;
  5153. if (!bridge || !bridge->encoder) {
  5154. SDE_ERROR("invalid argument\n");
  5155. return NULL;
  5156. }
  5157. priv = bridge->dev->dev_private;
  5158. sde_kms = to_sde_kms(priv->kms);
  5159. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  5160. drm_for_each_connector_iter(conn, &conn_iter) {
  5161. sde_conn = to_sde_connector(conn);
  5162. if (sde_conn->encoder == bridge->encoder) {
  5163. display = sde_conn->display;
  5164. display_for_each_ctrl(i, display) {
  5165. if (display->ext_bridge[i].bridge == bridge) {
  5166. dsi_bridge = &display->ext_bridge[i];
  5167. break;
  5168. }
  5169. }
  5170. }
  5171. }
  5172. drm_connector_list_iter_end(&conn_iter);
  5173. return dsi_bridge;
  5174. }
  5175. static void dsi_display_drm_ext_adjust_timing(
  5176. const struct dsi_display *display,
  5177. struct drm_display_mode *mode)
  5178. {
  5179. mode->hdisplay /= display->ctrl_count;
  5180. mode->hsync_start /= display->ctrl_count;
  5181. mode->hsync_end /= display->ctrl_count;
  5182. mode->htotal /= display->ctrl_count;
  5183. mode->hskew /= display->ctrl_count;
  5184. mode->clock /= display->ctrl_count;
  5185. }
  5186. static enum drm_mode_status dsi_display_drm_ext_bridge_mode_valid(
  5187. struct drm_bridge *bridge,
  5188. const struct drm_display_info *info,
  5189. const struct drm_display_mode *mode)
  5190. {
  5191. struct dsi_display_ext_bridge *ext_bridge;
  5192. struct drm_display_mode tmp;
  5193. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5194. if (!ext_bridge)
  5195. return MODE_ERROR;
  5196. tmp = *mode;
  5197. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5198. return ext_bridge->orig_funcs->mode_valid(bridge, info, &tmp);
  5199. }
  5200. static bool dsi_display_drm_ext_bridge_mode_fixup(
  5201. struct drm_bridge *bridge,
  5202. const struct drm_display_mode *mode,
  5203. struct drm_display_mode *adjusted_mode)
  5204. {
  5205. struct dsi_display_ext_bridge *ext_bridge;
  5206. struct drm_display_mode tmp;
  5207. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5208. if (!ext_bridge)
  5209. return false;
  5210. tmp = *mode;
  5211. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5212. return ext_bridge->orig_funcs->mode_fixup(bridge, &tmp, &tmp);
  5213. }
  5214. static void dsi_display_drm_ext_bridge_mode_set(
  5215. struct drm_bridge *bridge,
  5216. const struct drm_display_mode *mode,
  5217. const struct drm_display_mode *adjusted_mode)
  5218. {
  5219. struct dsi_display_ext_bridge *ext_bridge;
  5220. struct drm_display_mode tmp;
  5221. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5222. if (!ext_bridge)
  5223. return;
  5224. tmp = *mode;
  5225. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5226. ext_bridge->orig_funcs->mode_set(bridge, &tmp, &tmp);
  5227. }
  5228. static int dsi_host_ext_attach(struct mipi_dsi_host *host,
  5229. struct mipi_dsi_device *dsi)
  5230. {
  5231. struct dsi_display *display = to_dsi_display(host);
  5232. struct dsi_panel *panel;
  5233. if (!host || !dsi || !display->panel) {
  5234. DSI_ERR("Invalid param\n");
  5235. return -EINVAL;
  5236. }
  5237. DSI_DEBUG("DSI[%s]: channel=%d, lanes=%d, format=%d, mode_flags=%lx\n",
  5238. dsi->name, dsi->channel, dsi->lanes,
  5239. dsi->format, dsi->mode_flags);
  5240. panel = display->panel;
  5241. panel->host_config.data_lanes = 0;
  5242. if (dsi->lanes > 0)
  5243. panel->host_config.data_lanes |= DSI_DATA_LANE_0;
  5244. if (dsi->lanes > 1)
  5245. panel->host_config.data_lanes |= DSI_DATA_LANE_1;
  5246. if (dsi->lanes > 2)
  5247. panel->host_config.data_lanes |= DSI_DATA_LANE_2;
  5248. if (dsi->lanes > 3)
  5249. panel->host_config.data_lanes |= DSI_DATA_LANE_3;
  5250. switch (dsi->format) {
  5251. case MIPI_DSI_FMT_RGB888:
  5252. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
  5253. break;
  5254. case MIPI_DSI_FMT_RGB666:
  5255. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666_LOOSE;
  5256. break;
  5257. case MIPI_DSI_FMT_RGB666_PACKED:
  5258. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666;
  5259. break;
  5260. case MIPI_DSI_FMT_RGB565:
  5261. default:
  5262. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB565;
  5263. break;
  5264. }
  5265. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  5266. panel->panel_mode = DSI_OP_VIDEO_MODE;
  5267. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  5268. panel->video_config.traffic_mode =
  5269. DSI_VIDEO_TRAFFIC_BURST_MODE;
  5270. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  5271. panel->video_config.traffic_mode =
  5272. DSI_VIDEO_TRAFFIC_SYNC_PULSES;
  5273. else
  5274. panel->video_config.traffic_mode =
  5275. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
  5276. panel->video_config.hsa_lp11_en =
  5277. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA;
  5278. panel->video_config.hbp_lp11_en =
  5279. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP;
  5280. panel->video_config.hfp_lp11_en =
  5281. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP;
  5282. panel->video_config.pulse_mode_hsa_he =
  5283. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE;
  5284. } else {
  5285. panel->panel_mode = DSI_OP_CMD_MODE;
  5286. DSI_ERR("command mode not supported by ext bridge\n");
  5287. return -ENOTSUPP;
  5288. }
  5289. panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
  5290. return 0;
  5291. }
  5292. static struct mipi_dsi_host_ops dsi_host_ext_ops = {
  5293. .attach = dsi_host_ext_attach,
  5294. .detach = dsi_host_detach,
  5295. .transfer = dsi_host_transfer,
  5296. };
  5297. struct drm_panel *dsi_display_get_drm_panel(struct dsi_display *display)
  5298. {
  5299. if (!display || !display->panel) {
  5300. pr_err("invalid param(s)\n");
  5301. return NULL;
  5302. }
  5303. return &display->panel->drm_panel;
  5304. }
  5305. int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
  5306. struct drm_encoder *encoder, struct drm_connector *connector)
  5307. {
  5308. struct drm_device *drm;
  5309. struct drm_bridge *bridge;
  5310. struct drm_bridge *ext_bridge;
  5311. struct drm_connector *ext_conn;
  5312. struct sde_connector *sde_conn;
  5313. struct drm_bridge *prev_bridge;
  5314. int rc = 0, i;
  5315. if (!display || !encoder || !connector)
  5316. return -EINVAL;
  5317. drm = encoder->dev;
  5318. bridge = drm_bridge_chain_get_first_bridge(encoder);
  5319. sde_conn = to_sde_connector(connector);
  5320. prev_bridge = bridge;
  5321. if (display->panel && !display->panel->host_config.ext_bridge_mode)
  5322. return 0;
  5323. if (!bridge)
  5324. return -EINVAL;
  5325. for (i = 0; i < display->ext_bridge_cnt; i++) {
  5326. struct dsi_display_ext_bridge *ext_bridge_info =
  5327. &display->ext_bridge[i];
  5328. struct drm_encoder *c_encoder;
  5329. /* return if ext bridge is already initialized */
  5330. if (ext_bridge_info->bridge)
  5331. return 0;
  5332. ext_bridge = of_drm_find_bridge(ext_bridge_info->node_of);
  5333. if (IS_ERR_OR_NULL(ext_bridge)) {
  5334. rc = PTR_ERR(ext_bridge);
  5335. DSI_ERR("failed to find ext bridge\n");
  5336. goto error;
  5337. }
  5338. /* override functions for mode adjustment */
  5339. if (display->ext_bridge_cnt > 1) {
  5340. ext_bridge_info->bridge_funcs = *ext_bridge->funcs;
  5341. if (ext_bridge->funcs->mode_fixup)
  5342. ext_bridge_info->bridge_funcs.mode_fixup =
  5343. dsi_display_drm_ext_bridge_mode_fixup;
  5344. if (ext_bridge->funcs->mode_valid)
  5345. ext_bridge_info->bridge_funcs.mode_valid =
  5346. dsi_display_drm_ext_bridge_mode_valid;
  5347. if (ext_bridge->funcs->mode_set)
  5348. ext_bridge_info->bridge_funcs.mode_set =
  5349. dsi_display_drm_ext_bridge_mode_set;
  5350. ext_bridge_info->orig_funcs = ext_bridge->funcs;
  5351. ext_bridge->funcs = &ext_bridge_info->bridge_funcs;
  5352. }
  5353. rc = drm_bridge_attach(encoder, ext_bridge, prev_bridge, 0);
  5354. if (rc) {
  5355. DSI_ERR("[%s] ext brige attach failed, %d\n",
  5356. display->name, rc);
  5357. goto error;
  5358. }
  5359. ext_bridge_info->display = display;
  5360. ext_bridge_info->bridge = ext_bridge;
  5361. prev_bridge = ext_bridge;
  5362. /* ext bridge will init its own connector during attach,
  5363. * we need to extract it out of the connector list
  5364. */
  5365. spin_lock_irq(&drm->mode_config.connector_list_lock);
  5366. ext_conn = list_last_entry(&drm->mode_config.connector_list,
  5367. struct drm_connector, head);
  5368. if (!ext_conn) {
  5369. DSI_ERR("failed to get external connector\n");
  5370. rc = PTR_ERR(ext_conn);
  5371. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5372. goto error;
  5373. }
  5374. drm_connector_for_each_possible_encoder(ext_conn, c_encoder)
  5375. break;
  5376. if (!c_encoder) {
  5377. DSI_ERR("failed to get encoder\n");
  5378. rc = PTR_ERR(c_encoder);
  5379. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5380. goto error;
  5381. }
  5382. if (ext_conn && ext_conn != connector &&
  5383. c_encoder->base.id == bridge->encoder->base.id) {
  5384. list_del_init(&ext_conn->head);
  5385. display->ext_conn = ext_conn;
  5386. }
  5387. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5388. /* if there is no valid external connector created, or in split
  5389. * mode, default setting is used from panel defined in DT file.
  5390. */
  5391. if (!display->ext_conn ||
  5392. !display->ext_conn->funcs ||
  5393. !display->ext_conn->helper_private ||
  5394. display->ext_bridge_cnt > 1) {
  5395. display->ext_conn = NULL;
  5396. continue;
  5397. }
  5398. /* otherwise, hook up the functions to use external connector */
  5399. if (display->ext_conn->funcs->detect)
  5400. sde_conn->ops.detect = dsi_display_drm_ext_detect;
  5401. if (display->ext_conn->helper_private->get_modes)
  5402. sde_conn->ops.get_modes =
  5403. dsi_display_drm_ext_get_modes;
  5404. if (display->ext_conn->helper_private->mode_valid)
  5405. sde_conn->ops.mode_valid =
  5406. dsi_display_drm_ext_mode_valid;
  5407. if (display->ext_conn->helper_private->atomic_check)
  5408. sde_conn->ops.atomic_check =
  5409. dsi_display_drm_ext_atomic_check;
  5410. sde_conn->ops.get_info =
  5411. dsi_display_ext_get_info;
  5412. sde_conn->ops.get_mode_info =
  5413. dsi_display_ext_get_mode_info;
  5414. /* add support to attach/detach */
  5415. display->host.ops = &dsi_host_ext_ops;
  5416. }
  5417. return 0;
  5418. error:
  5419. return rc;
  5420. }
  5421. int dsi_display_get_info(struct drm_connector *connector,
  5422. struct msm_display_info *info, void *disp)
  5423. {
  5424. struct dsi_display *display;
  5425. struct dsi_panel_phy_props phy_props;
  5426. struct dsi_host_common_cfg *host;
  5427. int i, rc;
  5428. if (!info || !disp) {
  5429. DSI_ERR("invalid params\n");
  5430. return -EINVAL;
  5431. }
  5432. display = disp;
  5433. if (!display->panel) {
  5434. DSI_ERR("invalid display panel\n");
  5435. return -EINVAL;
  5436. }
  5437. mutex_lock(&display->display_lock);
  5438. rc = dsi_panel_get_phy_props(display->panel, &phy_props);
  5439. if (rc) {
  5440. DSI_ERR("[%s] failed to get panel phy props, rc=%d\n",
  5441. display->name, rc);
  5442. goto error;
  5443. }
  5444. memset(info, 0, sizeof(struct msm_display_info));
  5445. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5446. info->num_of_h_tiles = display->ctrl_count;
  5447. for (i = 0; i < info->num_of_h_tiles; i++)
  5448. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5449. info->is_connected = display->is_active;
  5450. if (!strcmp(display->display_type, "primary"))
  5451. info->display_type = SDE_CONNECTOR_PRIMARY;
  5452. else if (!strcmp(display->display_type, "secondary"))
  5453. info->display_type = SDE_CONNECTOR_SECONDARY;
  5454. info->width_mm = phy_props.panel_width_mm;
  5455. info->height_mm = phy_props.panel_height_mm;
  5456. info->max_width = 1920;
  5457. info->max_height = 1080;
  5458. info->qsync_min_fps =
  5459. display->panel->qsync_caps.qsync_min_fps;
  5460. info->has_qsync_min_fps_list =
  5461. (display->panel->qsync_caps.qsync_min_fps_list_len > 0) ?
  5462. true : false;
  5463. info->poms_align_vsync = display->panel->poms_align_vsync;
  5464. switch (display->panel->panel_mode) {
  5465. case DSI_OP_VIDEO_MODE:
  5466. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5467. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5468. if (display->panel->panel_mode_switch_enabled)
  5469. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5470. break;
  5471. case DSI_OP_CMD_MODE:
  5472. info->curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  5473. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5474. if (display->panel->panel_mode_switch_enabled)
  5475. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5476. info->is_te_using_watchdog_timer =
  5477. display->panel->te_using_watchdog_timer |
  5478. display->sw_te_using_wd;
  5479. break;
  5480. default:
  5481. DSI_ERR("unknwown dsi panel mode %d\n",
  5482. display->panel->panel_mode);
  5483. break;
  5484. }
  5485. if (display->panel->esd_config.esd_enabled &&
  5486. !display->sw_te_using_wd)
  5487. info->capabilities |= MSM_DISPLAY_ESD_ENABLED;
  5488. info->te_source = display->te_source;
  5489. host = &display->panel->host_config;
  5490. if (host->split_link.split_link_enabled)
  5491. info->capabilities |= MSM_DISPLAY_SPLIT_LINK;
  5492. info->dsc_count = display->panel->dsc_count;
  5493. info->lm_count = display->panel->lm_count;
  5494. error:
  5495. mutex_unlock(&display->display_lock);
  5496. return rc;
  5497. }
  5498. int dsi_display_get_mode_count(struct dsi_display *display,
  5499. u32 *count)
  5500. {
  5501. if (!display || !display->panel) {
  5502. DSI_ERR("invalid display:%d panel:%d\n", display != NULL,
  5503. display ? display->panel != NULL : 0);
  5504. return -EINVAL;
  5505. }
  5506. mutex_lock(&display->display_lock);
  5507. *count = display->panel->num_display_modes;
  5508. mutex_unlock(&display->display_lock);
  5509. return 0;
  5510. }
  5511. void dsi_display_adjust_mode_timing(struct dsi_display *display,
  5512. struct dsi_display_mode *dsi_mode,
  5513. int lanes, int bpp)
  5514. {
  5515. u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
  5516. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5517. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  5518. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5519. /* Constant FPS is not supported on command mode */
  5520. if (!(dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE))
  5521. return;
  5522. if (!dyn_clk_caps->maintain_const_fps)
  5523. return;
  5524. /*
  5525. * When there is a dynamic clock switch, there is small change
  5526. * in FPS. To compensate for this difference in FPS, hfp or vfp
  5527. * is adjusted. It has been assumed that the refined porch values
  5528. * are supported by the panel. This logic can be enhanced further
  5529. * in future by taking min/max porches supported by the panel.
  5530. */
  5531. switch (dyn_clk_caps->type) {
  5532. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5533. vtotal = DSI_V_TOTAL(&dsi_mode->timing);
  5534. old_htotal = dsi_h_total_dce(&dsi_mode->timing);
  5535. do_div(old_htotal, display->ctrl_count);
  5536. new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
  5537. div = bpp * vtotal * dsi_mode->timing.refresh_rate;
  5538. if (dsi_display_is_type_cphy(display)) {
  5539. new_htotal = new_htotal * bits_per_symbol;
  5540. div = div * num_of_symbols;
  5541. }
  5542. do_div(new_htotal, div);
  5543. if (old_htotal > new_htotal)
  5544. dsi_mode->timing.h_front_porch -=
  5545. ((old_htotal - new_htotal) * display->ctrl_count);
  5546. else
  5547. dsi_mode->timing.h_front_porch +=
  5548. ((new_htotal - old_htotal) * display->ctrl_count);
  5549. break;
  5550. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5551. htotal = dsi_h_total_dce(&dsi_mode->timing);
  5552. do_div(htotal, display->ctrl_count);
  5553. new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
  5554. div = bpp * htotal * dsi_mode->timing.refresh_rate;
  5555. if (dsi_display_is_type_cphy(display)) {
  5556. new_vtotal = new_vtotal * bits_per_symbol;
  5557. div = div * num_of_symbols;
  5558. }
  5559. do_div(new_vtotal, div);
  5560. dsi_mode->timing.v_front_porch = new_vtotal -
  5561. dsi_mode->timing.v_back_porch -
  5562. dsi_mode->timing.v_sync_width -
  5563. dsi_mode->timing.v_active;
  5564. break;
  5565. default:
  5566. break;
  5567. }
  5568. }
  5569. static void _dsi_display_populate_bit_clks(struct dsi_display *display,
  5570. int start, int end, u32 *mode_idx)
  5571. {
  5572. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5573. struct dsi_display_mode *src, *dst;
  5574. struct dsi_host_common_cfg *cfg;
  5575. struct dsi_display_mode_priv_info *priv_info;
  5576. int i, j, total_modes, bpp, lanes = 0;
  5577. size_t size = 0;
  5578. if (!display || !mode_idx)
  5579. return;
  5580. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5581. if (!dyn_clk_caps->dyn_clk_support)
  5582. return;
  5583. cfg = &(display->panel->host_config);
  5584. bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
  5585. if (cfg->data_lanes & DSI_DATA_LANE_0)
  5586. lanes++;
  5587. if (cfg->data_lanes & DSI_DATA_LANE_1)
  5588. lanes++;
  5589. if (cfg->data_lanes & DSI_DATA_LANE_2)
  5590. lanes++;
  5591. if (cfg->data_lanes & DSI_DATA_LANE_3)
  5592. lanes++;
  5593. total_modes = display->panel->num_display_modes;
  5594. for (i = start; i < end; i++) {
  5595. src = &display->modes[i];
  5596. if (!src)
  5597. return;
  5598. if (!src->priv_info->bit_clk_list.count)
  5599. continue;
  5600. src->timing.clk_rate_hz = src->priv_info->bit_clk_list.rates[0];
  5601. dsi_display_adjust_mode_timing(display, src, lanes, bpp);
  5602. src->pixel_clk_khz =
  5603. div_u64(src->timing.clk_rate_hz * lanes, bpp);
  5604. src->pixel_clk_khz /= 1000;
  5605. src->pixel_clk_khz *= display->ctrl_count;
  5606. }
  5607. for (i = 1; i < dyn_clk_caps->bit_clk_list_len; i++) {
  5608. if (*mode_idx >= total_modes)
  5609. return;
  5610. for (j = start; j < end; j++) {
  5611. src = &display->modes[j];
  5612. dst = &display->modes[*mode_idx];
  5613. if (!src || !dst) {
  5614. DSI_ERR("invalid mode index\n");
  5615. return;
  5616. }
  5617. memcpy(dst, src, sizeof(struct dsi_display_mode));
  5618. size = sizeof(struct dsi_display_mode_priv_info);
  5619. priv_info = kzalloc(size, GFP_KERNEL);
  5620. dst->priv_info = priv_info;
  5621. if (dst->priv_info)
  5622. memcpy(dst->priv_info, src->priv_info, size);
  5623. dst->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[i];
  5624. dsi_display_adjust_mode_timing(display, dst, lanes,
  5625. bpp);
  5626. dst->panel_mode_caps = DSI_OP_VIDEO_MODE;
  5627. dst->pixel_clk_khz =
  5628. div_u64(dst->timing.clk_rate_hz * lanes, bpp);
  5629. dst->pixel_clk_khz /= 1000;
  5630. dst->pixel_clk_khz *= display->ctrl_count;
  5631. (*mode_idx)++;
  5632. }
  5633. }
  5634. }
  5635. int dsi_display_restore_bit_clk(struct dsi_display *display, struct dsi_display_mode *mode)
  5636. {
  5637. int i;
  5638. u32 clk_rate_hz = 0;
  5639. if (!display || !mode || !mode->priv_info) {
  5640. DSI_ERR("invalid arguments\n");
  5641. return -EINVAL;
  5642. }
  5643. clk_rate_hz = display->cached_clk_rate;
  5644. if (mode->priv_info->bit_clk_list.count) {
  5645. /* use first entry as the default bit clk rate */
  5646. clk_rate_hz = mode->priv_info->bit_clk_list.rates[0];
  5647. for (i = 0; i < mode->priv_info->bit_clk_list.count; i++) {
  5648. if (display->dyn_bit_clk == mode->priv_info->bit_clk_list.rates[i])
  5649. clk_rate_hz = display->dyn_bit_clk;
  5650. }
  5651. }
  5652. mode->timing.clk_rate_hz = clk_rate_hz;
  5653. mode->priv_info->clk_rate_hz = clk_rate_hz;
  5654. SDE_EVT32(clk_rate_hz, display->cached_clk_rate, display->dyn_bit_clk);
  5655. DSI_DEBUG("clk_rate_hz:%u, cached_clk_rate:%u, dyn_bit_clk:%u\n",
  5656. clk_rate_hz, display->cached_clk_rate, display->dyn_bit_clk);
  5657. return 0;
  5658. }
  5659. void dsi_display_put_mode(struct dsi_display *display,
  5660. struct dsi_display_mode *mode)
  5661. {
  5662. dsi_panel_put_mode(mode);
  5663. }
  5664. int dsi_display_get_modes(struct dsi_display *display,
  5665. struct dsi_display_mode **out_modes)
  5666. {
  5667. struct dsi_dfps_capabilities dfps_caps;
  5668. struct dsi_display_ctrl *ctrl;
  5669. struct dsi_host_common_cfg *host = &display->panel->host_config;
  5670. bool is_split_link, support_cmd_mode, support_video_mode;
  5671. u32 num_dfps_rates, timing_mode_count, display_mode_count;
  5672. u32 sublinks_count, mode_idx, array_idx = 0;
  5673. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5674. int i, start, end, rc = -EINVAL;
  5675. if (!display || !out_modes) {
  5676. DSI_ERR("Invalid params\n");
  5677. return -EINVAL;
  5678. }
  5679. *out_modes = NULL;
  5680. ctrl = &display->ctrl[0];
  5681. mutex_lock(&display->display_lock);
  5682. if (display->modes)
  5683. goto exit;
  5684. display_mode_count = display->panel->num_display_modes;
  5685. display->modes = kcalloc(display_mode_count, sizeof(*display->modes),
  5686. GFP_KERNEL);
  5687. if (!display->modes) {
  5688. rc = -ENOMEM;
  5689. goto error;
  5690. }
  5691. rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5692. if (rc) {
  5693. DSI_ERR("[%s] failed to get dfps caps from panel\n",
  5694. display->name);
  5695. goto error;
  5696. }
  5697. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5698. timing_mode_count = display->panel->num_timing_nodes;
  5699. /* Validate command line timing */
  5700. if ((display->cmdline_timing != NO_OVERRIDE) &&
  5701. (display->cmdline_timing >= timing_mode_count))
  5702. display->cmdline_timing = NO_OVERRIDE;
  5703. for (mode_idx = 0; mode_idx < timing_mode_count; mode_idx++) {
  5704. struct dsi_display_mode display_mode;
  5705. int topology_override = NO_OVERRIDE;
  5706. bool is_preferred = false;
  5707. u32 frame_threshold_us = ctrl->ctrl->frame_threshold_time_us;
  5708. if (display->cmdline_timing == mode_idx) {
  5709. topology_override = display->cmdline_topology;
  5710. is_preferred = true;
  5711. }
  5712. memset(&display_mode, 0, sizeof(display_mode));
  5713. rc = dsi_panel_get_mode(display->panel, mode_idx,
  5714. &display_mode,
  5715. topology_override);
  5716. if (rc) {
  5717. DSI_ERR("[%s] failed to get mode idx %d from panel\n",
  5718. display->name, mode_idx);
  5719. goto error;
  5720. }
  5721. support_cmd_mode = display_mode.panel_mode_caps & DSI_OP_CMD_MODE;
  5722. support_video_mode = display_mode.panel_mode_caps & DSI_OP_VIDEO_MODE;
  5723. /* Setup widebus support */
  5724. display_mode.priv_info->widebus_support =
  5725. ctrl->ctrl->hw.widebus_support;
  5726. num_dfps_rates = ((!dfps_caps.dfps_support ||
  5727. !support_video_mode) ? 1 : dfps_caps.dfps_list_len);
  5728. /* Calculate dsi frame transfer time */
  5729. if (support_cmd_mode) {
  5730. dsi_panel_calc_dsi_transfer_time(
  5731. &display->panel->host_config,
  5732. &display_mode, frame_threshold_us);
  5733. display_mode.priv_info->dsi_transfer_time_us =
  5734. display_mode.timing.dsi_transfer_time_us;
  5735. display_mode.priv_info->min_dsi_clk_hz =
  5736. display_mode.timing.min_dsi_clk_hz;
  5737. display_mode.priv_info->mdp_transfer_time_us =
  5738. display_mode.timing.mdp_transfer_time_us;
  5739. }
  5740. is_split_link = host->split_link.split_link_enabled;
  5741. sublinks_count = host->split_link.num_sublinks;
  5742. if (is_split_link && sublinks_count > 1) {
  5743. display_mode.timing.h_active *= sublinks_count;
  5744. display_mode.timing.h_front_porch *= sublinks_count;
  5745. display_mode.timing.h_sync_width *= sublinks_count;
  5746. display_mode.timing.h_back_porch *= sublinks_count;
  5747. display_mode.timing.h_skew *= sublinks_count;
  5748. display_mode.pixel_clk_khz *= sublinks_count;
  5749. } else {
  5750. display_mode.timing.h_active *= display->ctrl_count;
  5751. display_mode.timing.h_front_porch *=
  5752. display->ctrl_count;
  5753. display_mode.timing.h_sync_width *=
  5754. display->ctrl_count;
  5755. display_mode.timing.h_back_porch *=
  5756. display->ctrl_count;
  5757. display_mode.timing.h_skew *= display->ctrl_count;
  5758. display_mode.pixel_clk_khz *= display->ctrl_count;
  5759. }
  5760. start = array_idx;
  5761. for (i = 0; i < num_dfps_rates; i++) {
  5762. struct dsi_display_mode *sub_mode =
  5763. &display->modes[array_idx];
  5764. u32 curr_refresh_rate;
  5765. if (!sub_mode) {
  5766. DSI_ERR("invalid mode data\n");
  5767. rc = -EFAULT;
  5768. goto error;
  5769. }
  5770. memcpy(sub_mode, &display_mode, sizeof(display_mode));
  5771. array_idx++;
  5772. if (!dfps_caps.dfps_support || !support_video_mode)
  5773. continue;
  5774. curr_refresh_rate = sub_mode->timing.refresh_rate;
  5775. sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i];
  5776. dsi_display_get_dfps_timing(display, sub_mode,
  5777. curr_refresh_rate);
  5778. sub_mode->panel_mode_caps = DSI_OP_VIDEO_MODE;
  5779. }
  5780. end = array_idx;
  5781. _dsi_display_populate_bit_clks(display, start, end, &array_idx);
  5782. if (is_preferred) {
  5783. /* Set first timing sub mode as preferred mode */
  5784. display->modes[start].is_preferred = true;
  5785. }
  5786. }
  5787. exit:
  5788. *out_modes = display->modes;
  5789. rc = 0;
  5790. error:
  5791. if (rc)
  5792. kfree(display->modes);
  5793. mutex_unlock(&display->display_lock);
  5794. return rc;
  5795. }
  5796. int dsi_display_get_panel_vfp(void *dsi_display,
  5797. int h_active, int v_active)
  5798. {
  5799. int i, rc = 0;
  5800. u32 count, refresh_rate = 0;
  5801. struct dsi_dfps_capabilities dfps_caps;
  5802. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5803. struct dsi_host_common_cfg *host;
  5804. if (!display || !display->panel)
  5805. return -EINVAL;
  5806. mutex_lock(&display->display_lock);
  5807. count = display->panel->num_display_modes;
  5808. if (display->panel->cur_mode)
  5809. refresh_rate = display->panel->cur_mode->timing.refresh_rate;
  5810. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5811. if (dfps_caps.dfps_support)
  5812. refresh_rate = dfps_caps.max_refresh_rate;
  5813. if (!refresh_rate) {
  5814. mutex_unlock(&display->display_lock);
  5815. DSI_ERR("Null Refresh Rate\n");
  5816. return -EINVAL;
  5817. }
  5818. host = &display->panel->host_config;
  5819. if (host->split_link.split_link_enabled)
  5820. h_active *= host->split_link.num_sublinks;
  5821. else
  5822. h_active *= display->ctrl_count;
  5823. for (i = 0; i < count; i++) {
  5824. struct dsi_display_mode *m = &display->modes[i];
  5825. if (m && v_active == m->timing.v_active &&
  5826. h_active == m->timing.h_active &&
  5827. refresh_rate == m->timing.refresh_rate) {
  5828. rc = m->timing.v_front_porch;
  5829. break;
  5830. }
  5831. }
  5832. mutex_unlock(&display->display_lock);
  5833. return rc;
  5834. }
  5835. int dsi_display_get_default_lms(void *dsi_display, u32 *num_lm)
  5836. {
  5837. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5838. u32 count, i;
  5839. int rc = 0;
  5840. *num_lm = 0;
  5841. mutex_lock(&display->display_lock);
  5842. count = display->panel->num_display_modes;
  5843. mutex_unlock(&display->display_lock);
  5844. if (!display->modes) {
  5845. struct dsi_display_mode *m;
  5846. rc = dsi_display_get_modes(display, &m);
  5847. if (rc)
  5848. return rc;
  5849. }
  5850. mutex_lock(&display->display_lock);
  5851. for (i = 0; i < count; i++) {
  5852. struct dsi_display_mode *m = &display->modes[i];
  5853. *num_lm = max(m->priv_info->topology.num_lm, *num_lm);
  5854. }
  5855. mutex_unlock(&display->display_lock);
  5856. return rc;
  5857. }
  5858. int dsi_display_get_qsync_min_fps(void *display_dsi, u32 mode_fps)
  5859. {
  5860. struct dsi_display *display = (struct dsi_display *)display_dsi;
  5861. struct dsi_panel *panel;
  5862. u32 i;
  5863. if (display == NULL || display->panel == NULL)
  5864. return -EINVAL;
  5865. panel = display->panel;
  5866. for (i = 0; i < panel->dfps_caps.dfps_list_len; i++) {
  5867. if (panel->dfps_caps.dfps_list[i] == mode_fps)
  5868. return panel->qsync_caps.qsync_min_fps_list[i];
  5869. }
  5870. SDE_EVT32(mode_fps);
  5871. DSI_DEBUG("Invalid mode_fps %d\n", mode_fps);
  5872. return -EINVAL;
  5873. }
  5874. int dsi_display_find_mode(struct dsi_display *display,
  5875. const struct dsi_display_mode *cmp,
  5876. struct dsi_display_mode **out_mode)
  5877. {
  5878. u32 count, i;
  5879. int rc;
  5880. if (!display || !out_mode)
  5881. return -EINVAL;
  5882. *out_mode = NULL;
  5883. mutex_lock(&display->display_lock);
  5884. count = display->panel->num_display_modes;
  5885. mutex_unlock(&display->display_lock);
  5886. if (!display->modes) {
  5887. struct dsi_display_mode *m;
  5888. rc = dsi_display_get_modes(display, &m);
  5889. if (rc)
  5890. return rc;
  5891. }
  5892. mutex_lock(&display->display_lock);
  5893. for (i = 0; i < count; i++) {
  5894. struct dsi_display_mode *m = &display->modes[i];
  5895. if (cmp->timing.v_active == m->timing.v_active &&
  5896. cmp->timing.h_active == m->timing.h_active &&
  5897. cmp->timing.refresh_rate == m->timing.refresh_rate) {
  5898. *out_mode = m;
  5899. rc = 0;
  5900. break;
  5901. }
  5902. }
  5903. mutex_unlock(&display->display_lock);
  5904. if (!*out_mode) {
  5905. DSI_ERR("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n",
  5906. display->name, cmp->timing.v_active,
  5907. cmp->timing.h_active, cmp->timing.refresh_rate,
  5908. cmp->pixel_clk_khz);
  5909. rc = -ENOENT;
  5910. }
  5911. return rc;
  5912. }
  5913. static inline bool dsi_display_mode_switch_dfps(struct dsi_display_mode *cur,
  5914. struct dsi_display_mode *adj)
  5915. {
  5916. /*
  5917. * If there is a change in the hfp or vfp of the current and adjoining
  5918. * mode,then either it is a dfps mode switch or dynamic clk change with
  5919. * constant fps.
  5920. */
  5921. if ((cur->timing.h_front_porch != adj->timing.h_front_porch) ||
  5922. (cur->timing.v_front_porch != adj->timing.v_front_porch))
  5923. return true;
  5924. else
  5925. return false;
  5926. }
  5927. /**
  5928. * dsi_display_validate_mode_change() - Validate mode change case.
  5929. * @display: DSI display handle.
  5930. * @cur_mode: Current mode.
  5931. * @adj_mode: Mode to be set.
  5932. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there
  5933. * is change in hfp or vfp but vactive and hactive are same.
  5934. * DSI_MODE_FLAG_DYN_CLK flag is set if there
  5935. * is change in clk but vactive and hactive are same.
  5936. * Return: error code.
  5937. */
  5938. int dsi_display_validate_mode_change(struct dsi_display *display,
  5939. struct dsi_display_mode *cur_mode,
  5940. struct dsi_display_mode *adj_mode)
  5941. {
  5942. int rc = 0;
  5943. struct dsi_dfps_capabilities dfps_caps;
  5944. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5945. struct sde_connector *sde_conn;
  5946. if (!display || !adj_mode || !display->drm_conn) {
  5947. DSI_ERR("Invalid params\n");
  5948. return -EINVAL;
  5949. }
  5950. if (!display->panel || !display->panel->cur_mode) {
  5951. DSI_DEBUG("Current panel mode not set\n");
  5952. return rc;
  5953. }
  5954. if ((cur_mode->timing.v_active != adj_mode->timing.v_active) ||
  5955. (cur_mode->timing.h_active != adj_mode->timing.h_active)) {
  5956. DSI_DEBUG("Avoid VRR and POMS when resolution is changed\n");
  5957. return rc;
  5958. }
  5959. sde_conn = to_sde_connector(display->drm_conn);
  5960. mutex_lock(&display->display_lock);
  5961. if (sde_conn->expected_panel_mode == MSM_DISPLAY_VIDEO_MODE &&
  5962. display->config.panel_mode == DSI_OP_CMD_MODE) {
  5963. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_VID;
  5964. DSI_DEBUG("Panel operating mode change to video detected\n");
  5965. } else if (sde_conn->expected_panel_mode == MSM_DISPLAY_CMD_MODE &&
  5966. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  5967. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_CMD;
  5968. DSI_DEBUG("Panel operating mode change to command detected\n");
  5969. } else {
  5970. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5971. /* dfps and dynamic clock with const fps use case */
  5972. if (dsi_display_mode_switch_dfps(cur_mode, adj_mode)) {
  5973. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5974. if (dfps_caps.dfps_support ||
  5975. dyn_clk_caps->maintain_const_fps) {
  5976. DSI_DEBUG("Mode switch is seamless variable refresh\n");
  5977. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  5978. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1,
  5979. cur_mode->timing.refresh_rate,
  5980. adj_mode->timing.refresh_rate,
  5981. cur_mode->timing.h_front_porch,
  5982. adj_mode->timing.h_front_porch,
  5983. cur_mode->timing.v_front_porch,
  5984. adj_mode->timing.v_front_porch);
  5985. }
  5986. }
  5987. /* dynamic clk change use case */
  5988. if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) {
  5989. if (dyn_clk_caps->dyn_clk_support) {
  5990. DSI_DEBUG("dynamic clk change detected\n");
  5991. if ((adj_mode->dsi_mode_flags &
  5992. DSI_MODE_FLAG_VRR) &&
  5993. (!dyn_clk_caps->maintain_const_fps)) {
  5994. DSI_ERR("dfps and dyn clk not supported in same commit\n");
  5995. rc = -ENOTSUPP;
  5996. goto error;
  5997. }
  5998. adj_mode->dsi_mode_flags |=
  5999. DSI_MODE_FLAG_DYN_CLK;
  6000. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
  6001. cur_mode->pixel_clk_khz,
  6002. adj_mode->pixel_clk_khz);
  6003. }
  6004. }
  6005. }
  6006. error:
  6007. mutex_unlock(&display->display_lock);
  6008. return rc;
  6009. }
  6010. int dsi_display_validate_mode(struct dsi_display *display,
  6011. struct dsi_display_mode *mode,
  6012. u32 flags)
  6013. {
  6014. int rc = 0;
  6015. int i;
  6016. struct dsi_display_ctrl *ctrl;
  6017. struct dsi_display_mode adj_mode;
  6018. if (!display || !mode) {
  6019. DSI_ERR("Invalid params\n");
  6020. return -EINVAL;
  6021. }
  6022. mutex_lock(&display->display_lock);
  6023. adj_mode = *mode;
  6024. adjust_timing_by_ctrl_count(display, &adj_mode);
  6025. rc = dsi_panel_validate_mode(display->panel, &adj_mode);
  6026. if (rc) {
  6027. DSI_ERR("[%s] panel mode validation failed, rc=%d\n",
  6028. display->name, rc);
  6029. goto error;
  6030. }
  6031. display_for_each_ctrl(i, display) {
  6032. ctrl = &display->ctrl[i];
  6033. rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
  6034. if (rc) {
  6035. DSI_ERR("[%s] ctrl mode validation failed, rc=%d\n",
  6036. display->name, rc);
  6037. goto error;
  6038. }
  6039. rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
  6040. if (rc) {
  6041. DSI_ERR("[%s] phy mode validation failed, rc=%d\n",
  6042. display->name, rc);
  6043. goto error;
  6044. }
  6045. }
  6046. if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
  6047. (mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)) {
  6048. rc = dsi_display_validate_mode_seamless(display, mode);
  6049. if (rc) {
  6050. DSI_ERR("[%s] seamless not possible rc=%d\n",
  6051. display->name, rc);
  6052. goto error;
  6053. }
  6054. }
  6055. error:
  6056. mutex_unlock(&display->display_lock);
  6057. return rc;
  6058. }
  6059. int dsi_display_set_mode(struct dsi_display *display,
  6060. struct dsi_display_mode *mode,
  6061. u32 flags)
  6062. {
  6063. int rc = 0;
  6064. struct dsi_display_mode adj_mode;
  6065. struct dsi_mode_info timing;
  6066. if (!display || !mode || !display->panel) {
  6067. DSI_ERR("Invalid params\n");
  6068. return -EINVAL;
  6069. }
  6070. mutex_lock(&display->display_lock);
  6071. adj_mode = *mode;
  6072. timing = adj_mode.timing;
  6073. adjust_timing_by_ctrl_count(display, &adj_mode);
  6074. if (!display->panel->cur_mode) {
  6075. display->panel->cur_mode =
  6076. kzalloc(sizeof(struct dsi_display_mode), GFP_KERNEL);
  6077. if (!display->panel->cur_mode) {
  6078. rc = -ENOMEM;
  6079. goto error;
  6080. }
  6081. }
  6082. rc = dsi_display_restore_bit_clk(display, &adj_mode);
  6083. if (rc) {
  6084. DSI_ERR("[%s] bit clk rate cannot be restored\n", display->name);
  6085. goto error;
  6086. }
  6087. rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
  6088. if (rc) {
  6089. DSI_ERR("[%s] mode cannot be set\n", display->name);
  6090. goto error;
  6091. }
  6092. rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
  6093. if (rc) {
  6094. DSI_ERR("[%s] failed to set mode\n", display->name);
  6095. goto error;
  6096. }
  6097. DSI_INFO("mdp_transfer_time=%d, hactive=%d, vactive=%d, fps=%d, clk_rate=%llu\n",
  6098. adj_mode.priv_info->mdp_transfer_time_us,
  6099. timing.h_active, timing.v_active, timing.refresh_rate,
  6100. adj_mode.priv_info->clk_rate_hz);
  6101. SDE_EVT32(adj_mode.priv_info->mdp_transfer_time_us,
  6102. timing.h_active, timing.v_active, timing.refresh_rate,
  6103. adj_mode.priv_info->clk_rate_hz);
  6104. memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
  6105. error:
  6106. mutex_unlock(&display->display_lock);
  6107. return rc;
  6108. }
  6109. int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
  6110. {
  6111. int rc = 0;
  6112. int i;
  6113. struct dsi_display_ctrl *ctrl;
  6114. if (!display) {
  6115. DSI_ERR("Invalid params\n");
  6116. return -EINVAL;
  6117. }
  6118. display_for_each_ctrl(i, display) {
  6119. ctrl = &display->ctrl[i];
  6120. rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
  6121. if (rc) {
  6122. DSI_ERR("[%s] failed to set tpg state for host_%d\n",
  6123. display->name, i);
  6124. goto error;
  6125. }
  6126. }
  6127. display->is_tpg_enabled = enable;
  6128. error:
  6129. return rc;
  6130. }
  6131. static int dsi_display_pre_switch(struct dsi_display *display)
  6132. {
  6133. int rc = 0;
  6134. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6135. DSI_CORE_CLK, DSI_CLK_ON);
  6136. if (rc) {
  6137. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6138. display->name, rc);
  6139. goto error;
  6140. }
  6141. rc = dsi_display_ctrl_update(display);
  6142. if (rc) {
  6143. DSI_ERR("[%s] failed to update DSI controller, rc=%d\n",
  6144. display->name, rc);
  6145. goto error_ctrl_clk_off;
  6146. }
  6147. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6148. DSI_LINK_CLK, DSI_CLK_ON);
  6149. if (rc) {
  6150. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6151. display->name, rc);
  6152. goto error_ctrl_deinit;
  6153. }
  6154. goto error;
  6155. error_ctrl_deinit:
  6156. (void)dsi_display_ctrl_deinit(display);
  6157. error_ctrl_clk_off:
  6158. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6159. DSI_CORE_CLK, DSI_CLK_OFF);
  6160. error:
  6161. return rc;
  6162. }
  6163. static bool _dsi_display_validate_host_state(struct dsi_display *display)
  6164. {
  6165. int i;
  6166. struct dsi_display_ctrl *ctrl;
  6167. display_for_each_ctrl(i, display) {
  6168. ctrl = &display->ctrl[i];
  6169. if (!ctrl->ctrl)
  6170. continue;
  6171. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  6172. return false;
  6173. }
  6174. return true;
  6175. }
  6176. static void dsi_display_handle_fifo_underflow(struct work_struct *work)
  6177. {
  6178. struct dsi_display *display = NULL;
  6179. display = container_of(work, struct dsi_display, fifo_underflow_work);
  6180. if (!display || !display->panel ||
  6181. atomic_read(&display->panel->esd_recovery_pending)) {
  6182. DSI_DEBUG("Invalid recovery use case\n");
  6183. return;
  6184. }
  6185. mutex_lock(&display->display_lock);
  6186. if (!_dsi_display_validate_host_state(display)) {
  6187. mutex_unlock(&display->display_lock);
  6188. return;
  6189. }
  6190. DSI_INFO("handle DSI FIFO underflow error\n");
  6191. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6192. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6193. DSI_ALL_CLKS, DSI_CLK_ON);
  6194. dsi_display_soft_reset(display);
  6195. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6196. DSI_ALL_CLKS, DSI_CLK_OFF);
  6197. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6198. mutex_unlock(&display->display_lock);
  6199. }
  6200. static void dsi_display_handle_fifo_overflow(struct work_struct *work)
  6201. {
  6202. struct dsi_display *display = NULL;
  6203. struct dsi_display_ctrl *ctrl;
  6204. int i, rc;
  6205. int mask = BIT(20); /* clock lane */
  6206. int (*cb_func)(void *event_usr_ptr,
  6207. uint32_t event_idx, uint32_t instance_idx,
  6208. uint32_t data0, uint32_t data1,
  6209. uint32_t data2, uint32_t data3);
  6210. void *data;
  6211. u32 version = 0;
  6212. display = container_of(work, struct dsi_display, fifo_overflow_work);
  6213. if (!display || !display->panel ||
  6214. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6215. atomic_read(&display->panel->esd_recovery_pending)) {
  6216. DSI_DEBUG("Invalid recovery use case\n");
  6217. return;
  6218. }
  6219. mutex_lock(&display->display_lock);
  6220. if (!_dsi_display_validate_host_state(display)) {
  6221. mutex_unlock(&display->display_lock);
  6222. return;
  6223. }
  6224. DSI_INFO("handle DSI FIFO overflow error\n");
  6225. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6226. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6227. DSI_ALL_CLKS, DSI_CLK_ON);
  6228. /*
  6229. * below recovery sequence is not applicable to
  6230. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6231. */
  6232. ctrl = &display->ctrl[display->clk_master_idx];
  6233. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6234. if (!version || (version < 0x20020001))
  6235. goto end;
  6236. /* reset ctrl and lanes */
  6237. display_for_each_ctrl(i, display) {
  6238. ctrl = &display->ctrl[i];
  6239. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6240. rc = dsi_phy_lane_reset(ctrl->phy);
  6241. }
  6242. /* wait for display line count to be in active area */
  6243. ctrl = &display->ctrl[display->clk_master_idx];
  6244. if (ctrl->ctrl->recovery_cb.event_cb) {
  6245. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6246. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6247. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6248. display->clk_master_idx, 0, 0, 0, 0);
  6249. if (rc < 0) {
  6250. DSI_DEBUG("sde callback failed\n");
  6251. goto end;
  6252. }
  6253. }
  6254. /* Enable Video mode for DSI controller */
  6255. display_for_each_ctrl(i, display) {
  6256. ctrl = &display->ctrl[i];
  6257. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6258. }
  6259. /*
  6260. * Add sufficient delay to make sure
  6261. * pixel transmission has started
  6262. */
  6263. udelay(200);
  6264. end:
  6265. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6266. DSI_ALL_CLKS, DSI_CLK_OFF);
  6267. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6268. mutex_unlock(&display->display_lock);
  6269. }
  6270. static void dsi_display_handle_lp_rx_timeout(struct work_struct *work)
  6271. {
  6272. struct dsi_display *display = NULL;
  6273. struct dsi_display_ctrl *ctrl;
  6274. int i, rc;
  6275. int mask = (BIT(20) | (0xF << 16)); /* clock lane and 4 data lane */
  6276. int (*cb_func)(void *event_usr_ptr,
  6277. uint32_t event_idx, uint32_t instance_idx,
  6278. uint32_t data0, uint32_t data1,
  6279. uint32_t data2, uint32_t data3);
  6280. void *data;
  6281. u32 version = 0;
  6282. display = container_of(work, struct dsi_display, lp_rx_timeout_work);
  6283. if (!display || !display->panel ||
  6284. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6285. atomic_read(&display->panel->esd_recovery_pending)) {
  6286. DSI_DEBUG("Invalid recovery use case\n");
  6287. return;
  6288. }
  6289. mutex_lock(&display->display_lock);
  6290. if (!_dsi_display_validate_host_state(display)) {
  6291. mutex_unlock(&display->display_lock);
  6292. return;
  6293. }
  6294. DSI_INFO("handle DSI LP RX Timeout error\n");
  6295. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6296. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6297. DSI_ALL_CLKS, DSI_CLK_ON);
  6298. /*
  6299. * below recovery sequence is not applicable to
  6300. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6301. */
  6302. ctrl = &display->ctrl[display->clk_master_idx];
  6303. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6304. if (!version || (version < 0x20020001))
  6305. goto end;
  6306. /* reset ctrl and lanes */
  6307. display_for_each_ctrl(i, display) {
  6308. ctrl = &display->ctrl[i];
  6309. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6310. rc = dsi_phy_lane_reset(ctrl->phy);
  6311. }
  6312. ctrl = &display->ctrl[display->clk_master_idx];
  6313. if (ctrl->ctrl->recovery_cb.event_cb) {
  6314. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6315. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6316. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6317. display->clk_master_idx, 0, 0, 0, 0);
  6318. if (rc < 0) {
  6319. DSI_DEBUG("Target is in suspend/shutdown\n");
  6320. goto end;
  6321. }
  6322. }
  6323. /* Enable Video mode for DSI controller */
  6324. display_for_each_ctrl(i, display) {
  6325. ctrl = &display->ctrl[i];
  6326. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6327. }
  6328. /*
  6329. * Add sufficient delay to make sure
  6330. * pixel transmission as started
  6331. */
  6332. udelay(200);
  6333. end:
  6334. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6335. DSI_ALL_CLKS, DSI_CLK_OFF);
  6336. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6337. mutex_unlock(&display->display_lock);
  6338. }
  6339. static int dsi_display_cb_error_handler(void *data,
  6340. uint32_t event_idx, uint32_t instance_idx,
  6341. uint32_t data0, uint32_t data1,
  6342. uint32_t data2, uint32_t data3)
  6343. {
  6344. struct dsi_display *display = data;
  6345. if (!display || !(display->err_workq))
  6346. return -EINVAL;
  6347. switch (event_idx) {
  6348. case DSI_FIFO_UNDERFLOW:
  6349. queue_work(display->err_workq, &display->fifo_underflow_work);
  6350. break;
  6351. case DSI_FIFO_OVERFLOW:
  6352. queue_work(display->err_workq, &display->fifo_overflow_work);
  6353. break;
  6354. case DSI_LP_Rx_TIMEOUT:
  6355. queue_work(display->err_workq, &display->lp_rx_timeout_work);
  6356. break;
  6357. default:
  6358. DSI_WARN("unhandled error interrupt: %d\n", event_idx);
  6359. break;
  6360. }
  6361. return 0;
  6362. }
  6363. static void dsi_display_register_error_handler(struct dsi_display *display)
  6364. {
  6365. int i = 0;
  6366. struct dsi_display_ctrl *ctrl;
  6367. struct dsi_event_cb_info event_info;
  6368. if (!display)
  6369. return;
  6370. display->err_workq = create_singlethread_workqueue("dsi_err_workq");
  6371. if (!display->err_workq) {
  6372. DSI_ERR("failed to create dsi workq!\n");
  6373. return;
  6374. }
  6375. INIT_WORK(&display->fifo_underflow_work,
  6376. dsi_display_handle_fifo_underflow);
  6377. INIT_WORK(&display->fifo_overflow_work,
  6378. dsi_display_handle_fifo_overflow);
  6379. INIT_WORK(&display->lp_rx_timeout_work,
  6380. dsi_display_handle_lp_rx_timeout);
  6381. memset(&event_info, 0, sizeof(event_info));
  6382. event_info.event_cb = dsi_display_cb_error_handler;
  6383. event_info.event_usr_ptr = display;
  6384. display_for_each_ctrl(i, display) {
  6385. ctrl = &display->ctrl[i];
  6386. ctrl->ctrl->irq_info.irq_err_cb = event_info;
  6387. }
  6388. }
  6389. static void dsi_display_unregister_error_handler(struct dsi_display *display)
  6390. {
  6391. int i = 0;
  6392. struct dsi_display_ctrl *ctrl;
  6393. if (!display)
  6394. return;
  6395. display_for_each_ctrl(i, display) {
  6396. ctrl = &display->ctrl[i];
  6397. memset(&ctrl->ctrl->irq_info.irq_err_cb,
  6398. 0, sizeof(struct dsi_event_cb_info));
  6399. }
  6400. if (display->err_workq) {
  6401. destroy_workqueue(display->err_workq);
  6402. display->err_workq = NULL;
  6403. }
  6404. }
  6405. int dsi_display_prepare(struct dsi_display *display)
  6406. {
  6407. int rc = 0;
  6408. struct dsi_display_mode *mode;
  6409. if (!display) {
  6410. DSI_ERR("Invalid params\n");
  6411. return -EINVAL;
  6412. }
  6413. if (!display->panel->cur_mode) {
  6414. DSI_ERR("no valid mode set for the display\n");
  6415. return -EINVAL;
  6416. }
  6417. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6418. mutex_lock(&display->display_lock);
  6419. mode = display->panel->cur_mode;
  6420. dsi_display_set_ctrl_esd_check_flag(display, false);
  6421. /* Set up ctrl isr before enabling core clk */
  6422. if (!display->trusted_vm_env)
  6423. dsi_display_ctrl_isr_configure(display, true);
  6424. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6425. if (display->is_cont_splash_enabled &&
  6426. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6427. DSI_ERR("DMS not supported on first frame\n");
  6428. rc = -EINVAL;
  6429. goto error;
  6430. }
  6431. if (!is_skip_op_required(display)) {
  6432. /* update dsi ctrl for new mode */
  6433. rc = dsi_display_pre_switch(display);
  6434. if (rc)
  6435. DSI_ERR("[%s] panel pre-switch failed, rc=%d\n",
  6436. display->name, rc);
  6437. goto error;
  6438. }
  6439. }
  6440. if (!display->poms_pending &&
  6441. (!is_skip_op_required(display))) {
  6442. /*
  6443. * For continuous splash/trusted vm, we skip panel
  6444. * pre prepare since the regulator vote is already
  6445. * taken care in splash resource init
  6446. */
  6447. rc = dsi_panel_pre_prepare(display->panel);
  6448. if (rc) {
  6449. DSI_ERR("[%s] panel pre-prepare failed, rc=%d\n",
  6450. display->name, rc);
  6451. goto error;
  6452. }
  6453. }
  6454. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6455. DSI_CORE_CLK, DSI_CLK_ON);
  6456. if (rc) {
  6457. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6458. display->name, rc);
  6459. goto error_panel_post_unprep;
  6460. }
  6461. /*
  6462. * If ULPS during suspend feature is enabled, then DSI PHY was
  6463. * left on during suspend. In this case, we do not need to reset/init
  6464. * PHY. This would have already been done when the CORE clocks are
  6465. * turned on. However, if cont splash is disabled, the first time DSI
  6466. * is powered on, phy init needs to be done unconditionally.
  6467. */
  6468. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  6469. rc = dsi_display_phy_sw_reset(display);
  6470. if (rc) {
  6471. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  6472. display->name, rc);
  6473. goto error_ctrl_clk_off;
  6474. }
  6475. rc = dsi_display_phy_enable(display);
  6476. if (rc) {
  6477. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  6478. display->name, rc);
  6479. goto error_ctrl_clk_off;
  6480. }
  6481. }
  6482. rc = dsi_display_ctrl_init(display);
  6483. if (rc) {
  6484. DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
  6485. display->name, rc);
  6486. goto error_phy_disable;
  6487. }
  6488. /* Set up DSI ERROR event callback */
  6489. dsi_display_register_error_handler(display);
  6490. rc = dsi_display_ctrl_host_enable(display);
  6491. if (rc) {
  6492. DSI_ERR("[%s] failed to enable DSI host, rc=%d\n",
  6493. display->name, rc);
  6494. goto error_ctrl_deinit;
  6495. }
  6496. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6497. DSI_LINK_CLK, DSI_CLK_ON);
  6498. if (rc) {
  6499. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6500. display->name, rc);
  6501. goto error_host_engine_off;
  6502. }
  6503. if (!is_skip_op_required(display)) {
  6504. /*
  6505. * For continuous splash/trusted vm, skip panel prepare and
  6506. * ctl reset since the pnael and ctrl is already in active
  6507. * state and panel on commands are not needed
  6508. */
  6509. rc = dsi_display_soft_reset(display);
  6510. if (rc) {
  6511. DSI_ERR("[%s] failed soft reset, rc=%d\n",
  6512. display->name, rc);
  6513. goto error_ctrl_link_off;
  6514. }
  6515. if (!display->poms_pending) {
  6516. rc = dsi_panel_prepare(display->panel);
  6517. if (rc) {
  6518. DSI_ERR("[%s] panel prepare failed, rc=%d\n",
  6519. display->name, rc);
  6520. goto error_ctrl_link_off;
  6521. }
  6522. }
  6523. }
  6524. goto error;
  6525. error_ctrl_link_off:
  6526. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6527. DSI_LINK_CLK, DSI_CLK_OFF);
  6528. error_host_engine_off:
  6529. (void)dsi_display_ctrl_host_disable(display);
  6530. error_ctrl_deinit:
  6531. (void)dsi_display_ctrl_deinit(display);
  6532. error_phy_disable:
  6533. (void)dsi_display_phy_disable(display);
  6534. error_ctrl_clk_off:
  6535. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6536. DSI_CORE_CLK, DSI_CLK_OFF);
  6537. error_panel_post_unprep:
  6538. (void)dsi_panel_post_unprepare(display->panel);
  6539. error:
  6540. mutex_unlock(&display->display_lock);
  6541. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6542. return rc;
  6543. }
  6544. static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
  6545. const struct dsi_display_ctrl *ctrl,
  6546. const struct msm_roi_list *req_rois,
  6547. struct dsi_rect *out_roi)
  6548. {
  6549. const struct dsi_rect *bounds = &ctrl->ctrl->mode_bounds;
  6550. struct dsi_display_mode *cur_mode;
  6551. struct msm_roi_caps *roi_caps;
  6552. struct dsi_rect req_roi = { 0 };
  6553. int rc = 0;
  6554. cur_mode = display->panel->cur_mode;
  6555. if (!cur_mode)
  6556. return 0;
  6557. roi_caps = &cur_mode->priv_info->roi_caps;
  6558. if (req_rois->num_rects > roi_caps->num_roi) {
  6559. DSI_ERR("request for %d rois greater than max %d\n",
  6560. req_rois->num_rects,
  6561. roi_caps->num_roi);
  6562. rc = -EINVAL;
  6563. goto exit;
  6564. }
  6565. /**
  6566. * if no rois, user wants to reset back to full resolution
  6567. * note: h_active is already divided by ctrl_count
  6568. */
  6569. if (!req_rois->num_rects) {
  6570. *out_roi = *bounds;
  6571. goto exit;
  6572. }
  6573. /* intersect with the bounds */
  6574. req_roi.x = req_rois->roi[0].x1;
  6575. req_roi.y = req_rois->roi[0].y1;
  6576. req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
  6577. req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
  6578. dsi_rect_intersect(&req_roi, bounds, out_roi);
  6579. exit:
  6580. /* adjust the ctrl origin to be top left within the ctrl */
  6581. out_roi->x = out_roi->x - bounds->x;
  6582. DSI_DEBUG("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out (%d,%d,%d,%d)\n",
  6583. ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
  6584. req_roi.x, req_roi.y, req_roi.w, req_roi.h,
  6585. bounds->x, bounds->y, bounds->w, bounds->h,
  6586. out_roi->x, out_roi->y, out_roi->w, out_roi->h);
  6587. return rc;
  6588. }
  6589. static int dsi_display_qsync(struct dsi_display *display, bool enable)
  6590. {
  6591. int i;
  6592. int rc = 0;
  6593. if (!display->panel->qsync_caps.qsync_min_fps) {
  6594. DSI_ERR("%s:ERROR: qsync set, but no fps\n", __func__);
  6595. return 0;
  6596. }
  6597. mutex_lock(&display->display_lock);
  6598. display_for_each_ctrl(i, display) {
  6599. if (enable) {
  6600. /* send the commands to enable qsync */
  6601. rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
  6602. if (rc) {
  6603. DSI_ERR("fail qsync ON cmds rc:%d\n", rc);
  6604. goto exit;
  6605. }
  6606. } else {
  6607. /* send the commands to enable qsync */
  6608. rc = dsi_panel_send_qsync_off_dcs(display->panel, i);
  6609. if (rc) {
  6610. DSI_ERR("fail qsync OFF cmds rc:%d\n", rc);
  6611. goto exit;
  6612. }
  6613. }
  6614. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  6615. }
  6616. exit:
  6617. SDE_EVT32(enable, display->panel->qsync_caps.qsync_min_fps, rc);
  6618. mutex_unlock(&display->display_lock);
  6619. return rc;
  6620. }
  6621. static int dsi_display_set_roi(struct dsi_display *display,
  6622. struct msm_roi_list *rois)
  6623. {
  6624. struct dsi_display_mode *cur_mode;
  6625. struct msm_roi_caps *roi_caps;
  6626. int rc = 0;
  6627. int i;
  6628. if (!display || !rois || !display->panel)
  6629. return -EINVAL;
  6630. cur_mode = display->panel->cur_mode;
  6631. if (!cur_mode)
  6632. return 0;
  6633. roi_caps = &cur_mode->priv_info->roi_caps;
  6634. if (!roi_caps->enabled)
  6635. return 0;
  6636. display_for_each_ctrl(i, display) {
  6637. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  6638. struct dsi_rect ctrl_roi;
  6639. bool changed = false;
  6640. rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, &ctrl_roi);
  6641. if (rc) {
  6642. DSI_ERR("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
  6643. return rc;
  6644. }
  6645. rc = dsi_ctrl_set_roi(ctrl->ctrl, &ctrl_roi, &changed);
  6646. if (rc) {
  6647. DSI_ERR("dsi_ctrl_set_roi failed rc %d\n", rc);
  6648. return rc;
  6649. }
  6650. if (!changed)
  6651. continue;
  6652. /* send the new roi to the panel via dcs commands */
  6653. rc = dsi_panel_send_roi_dcs(display->panel, i, &ctrl_roi);
  6654. if (rc) {
  6655. DSI_ERR("dsi_panel_set_roi failed rc %d\n", rc);
  6656. return rc;
  6657. }
  6658. /* re-program the ctrl with the timing based on the new roi */
  6659. rc = dsi_ctrl_timing_setup(ctrl->ctrl);
  6660. if (rc) {
  6661. DSI_ERR("dsi_ctrl_setup failed rc %d\n", rc);
  6662. return rc;
  6663. }
  6664. }
  6665. return rc;
  6666. }
  6667. int dsi_display_pre_kickoff(struct drm_connector *connector,
  6668. struct dsi_display *display,
  6669. struct msm_display_kickoff_params *params)
  6670. {
  6671. int rc = 0, ret = 0;
  6672. int i;
  6673. /* check and setup MISR */
  6674. if (display->misr_enable)
  6675. _dsi_display_setup_misr(display);
  6676. /* dynamic DSI clock setting */
  6677. if (atomic_read(&display->clkrate_change_pending)) {
  6678. mutex_lock(&display->display_lock);
  6679. /*
  6680. * acquire panel_lock to make sure no commands are in progress
  6681. */
  6682. dsi_panel_acquire_panel_lock(display->panel);
  6683. /*
  6684. * Wait for DSI command engine not to be busy sending data
  6685. * from display engine.
  6686. * If waiting fails, return "rc" instead of below "ret" so as
  6687. * not to impact DRM commit. The clock updating would be
  6688. * deferred to the next DRM commit.
  6689. */
  6690. display_for_each_ctrl(i, display) {
  6691. struct dsi_ctrl *ctrl = display->ctrl[i].ctrl;
  6692. ret = dsi_ctrl_wait_for_cmd_mode_mdp_idle(ctrl);
  6693. if (ret)
  6694. goto wait_failure;
  6695. }
  6696. /*
  6697. * Don't check the return value so as not to impact DRM commit
  6698. * when error occurs.
  6699. */
  6700. (void)dsi_display_force_update_dsi_clk(display);
  6701. wait_failure:
  6702. /* release panel_lock */
  6703. dsi_panel_release_panel_lock(display->panel);
  6704. mutex_unlock(&display->display_lock);
  6705. }
  6706. if (!ret)
  6707. rc = dsi_display_set_roi(display, params->rois);
  6708. return rc;
  6709. }
  6710. int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
  6711. {
  6712. int rc = 0;
  6713. if (!display || !display->panel) {
  6714. DSI_ERR("Invalid params\n");
  6715. return -EINVAL;
  6716. }
  6717. if (!display->panel->cur_mode) {
  6718. DSI_ERR("no valid mode set for the display\n");
  6719. return -EINVAL;
  6720. }
  6721. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6722. rc = dsi_display_vid_engine_enable(display);
  6723. if (rc) {
  6724. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6725. display->name, rc);
  6726. goto error_out;
  6727. }
  6728. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6729. rc = dsi_display_cmd_engine_enable(display);
  6730. if (rc) {
  6731. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6732. display->name, rc);
  6733. goto error_out;
  6734. }
  6735. } else {
  6736. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6737. rc = -EINVAL;
  6738. }
  6739. error_out:
  6740. return rc;
  6741. }
  6742. int dsi_display_pre_commit(void *display,
  6743. struct msm_display_conn_params *params)
  6744. {
  6745. bool enable = false;
  6746. int rc = 0;
  6747. if (!display || !params) {
  6748. pr_err("Invalid params\n");
  6749. return -EINVAL;
  6750. }
  6751. if (params->qsync_update) {
  6752. enable = (params->qsync_mode > 0) ? true : false;
  6753. rc = dsi_display_qsync(display, enable);
  6754. if (rc)
  6755. pr_err("%s failed to send qsync commands\n",
  6756. __func__);
  6757. SDE_EVT32(params->qsync_mode, rc);
  6758. }
  6759. return rc;
  6760. }
  6761. static void dsi_display_panel_id_notification(struct dsi_display *display)
  6762. {
  6763. if (display->panel_id != ~0x0 &&
  6764. display->ctrl[0].ctrl->panel_id_cb.event_cb) {
  6765. display->ctrl[0].ctrl->panel_id_cb.event_cb(
  6766. display->ctrl[0].ctrl->panel_id_cb.event_usr_ptr,
  6767. display->ctrl[0].ctrl->panel_id_cb.event_idx,
  6768. 0, ((display->panel_id & 0xffffffff00000000) >> 32),
  6769. (display->panel_id & 0xffffffff), 0, 0);
  6770. }
  6771. }
  6772. int dsi_display_enable(struct dsi_display *display)
  6773. {
  6774. int rc = 0;
  6775. struct dsi_display_mode *mode;
  6776. if (!display || !display->panel) {
  6777. DSI_ERR("Invalid params\n");
  6778. return -EINVAL;
  6779. }
  6780. if (!display->panel->cur_mode) {
  6781. DSI_ERR("no valid mode set for the display\n");
  6782. return -EINVAL;
  6783. }
  6784. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6785. /*
  6786. * Engine states and panel states are populated during splash
  6787. * resource/trusted vm and hence we return early
  6788. */
  6789. if (is_skip_op_required(display)) {
  6790. dsi_display_config_ctrl_for_cont_splash(display);
  6791. rc = dsi_display_splash_res_cleanup(display);
  6792. if (rc) {
  6793. DSI_ERR("Continuous splash res cleanup failed, rc=%d\n",
  6794. rc);
  6795. return -EINVAL;
  6796. }
  6797. display->panel->panel_initialized = true;
  6798. DSI_DEBUG("cont splash enabled, display enable not required\n");
  6799. dsi_display_panel_id_notification(display);
  6800. return 0;
  6801. }
  6802. mutex_lock(&display->display_lock);
  6803. mode = display->panel->cur_mode;
  6804. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6805. rc = dsi_panel_post_switch(display->panel);
  6806. if (rc) {
  6807. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6808. display->name, rc);
  6809. goto error;
  6810. }
  6811. } else if (!display->poms_pending) {
  6812. rc = dsi_panel_enable(display->panel);
  6813. if (rc) {
  6814. DSI_ERR("[%s] failed to enable DSI panel, rc=%d\n",
  6815. display->name, rc);
  6816. goto error;
  6817. }
  6818. }
  6819. dsi_display_panel_id_notification(display);
  6820. /* Block sending pps command if modeset is due to fps difference */
  6821. if ((mode->priv_info->dsc_enabled ||
  6822. mode->priv_info->vdc_enabled) &&
  6823. !(mode->dsi_mode_flags & DSI_MODE_FLAG_DMS_FPS)) {
  6824. rc = dsi_panel_update_pps(display->panel);
  6825. if (rc) {
  6826. DSI_ERR("[%s] panel pps cmd update failed, rc=%d\n",
  6827. display->name, rc);
  6828. goto error;
  6829. }
  6830. }
  6831. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6832. rc = dsi_panel_switch(display->panel);
  6833. if (rc)
  6834. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6835. display->name, rc);
  6836. goto error;
  6837. }
  6838. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6839. DSI_DEBUG("%s:enable video timing eng\n", __func__);
  6840. rc = dsi_display_vid_engine_enable(display);
  6841. if (rc) {
  6842. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6843. display->name, rc);
  6844. goto error_disable_panel;
  6845. }
  6846. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6847. DSI_DEBUG("%s:enable command timing eng\n", __func__);
  6848. rc = dsi_display_cmd_engine_enable(display);
  6849. if (rc) {
  6850. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6851. display->name, rc);
  6852. goto error_disable_panel;
  6853. }
  6854. } else {
  6855. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6856. rc = -EINVAL;
  6857. goto error_disable_panel;
  6858. }
  6859. goto error;
  6860. error_disable_panel:
  6861. (void)dsi_panel_disable(display->panel);
  6862. error:
  6863. mutex_unlock(&display->display_lock);
  6864. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6865. return rc;
  6866. }
  6867. int dsi_display_post_enable(struct dsi_display *display)
  6868. {
  6869. int rc = 0;
  6870. if (!display) {
  6871. DSI_ERR("Invalid params\n");
  6872. return -EINVAL;
  6873. }
  6874. mutex_lock(&display->display_lock);
  6875. if (display->panel->cur_mode->dsi_mode_flags &
  6876. DSI_MODE_FLAG_POMS_TO_CMD) {
  6877. dsi_panel_switch_cmd_mode_in(display->panel);
  6878. } else if (display->panel->cur_mode->dsi_mode_flags &
  6879. DSI_MODE_FLAG_POMS_TO_VID)
  6880. dsi_panel_switch_video_mode_in(display->panel);
  6881. else {
  6882. rc = dsi_panel_post_enable(display->panel);
  6883. if (rc)
  6884. DSI_ERR("[%s] panel post-enable failed, rc=%d\n",
  6885. display->name, rc);
  6886. }
  6887. /* remove the clk vote for CMD mode panels */
  6888. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6889. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6890. DSI_ALL_CLKS, DSI_CLK_OFF);
  6891. mutex_unlock(&display->display_lock);
  6892. return rc;
  6893. }
  6894. int dsi_display_pre_disable(struct dsi_display *display)
  6895. {
  6896. int rc = 0;
  6897. if (!display) {
  6898. DSI_ERR("Invalid params\n");
  6899. return -EINVAL;
  6900. }
  6901. mutex_lock(&display->display_lock);
  6902. /* enable the clk vote for CMD mode panels */
  6903. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6904. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6905. DSI_ALL_CLKS, DSI_CLK_ON);
  6906. if (display->poms_pending) {
  6907. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6908. dsi_panel_switch_cmd_mode_out(display->panel);
  6909. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6910. /*
  6911. * Add unbalanced vote for clock & cmd engine to enable
  6912. * async trigger of pre video to cmd mode switch.
  6913. */
  6914. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6915. DSI_ALL_CLKS, DSI_CLK_ON);
  6916. if (rc) {
  6917. DSI_ERR("[%s]failed to enable all clocks,rc=%d",
  6918. display->name, rc);
  6919. goto exit;
  6920. }
  6921. rc = dsi_display_cmd_engine_enable(display);
  6922. if (rc) {
  6923. DSI_ERR("[%s]failed to enable cmd engine,rc=%d",
  6924. display->name, rc);
  6925. goto error_disable_clks;
  6926. }
  6927. dsi_panel_switch_video_mode_out(display->panel);
  6928. }
  6929. } else {
  6930. rc = dsi_panel_pre_disable(display->panel);
  6931. if (rc)
  6932. DSI_ERR("[%s] panel pre-disable failed, rc=%d\n",
  6933. display->name, rc);
  6934. }
  6935. goto exit;
  6936. error_disable_clks:
  6937. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6938. DSI_ALL_CLKS, DSI_CLK_OFF);
  6939. if (rc)
  6940. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  6941. display->name, rc);
  6942. exit:
  6943. mutex_unlock(&display->display_lock);
  6944. return rc;
  6945. }
  6946. static void dsi_display_handle_poms_te(struct work_struct *work)
  6947. {
  6948. struct dsi_display *display = NULL;
  6949. struct delayed_work *dw = to_delayed_work(work);
  6950. struct mipi_dsi_device *dsi = NULL;
  6951. struct dsi_panel *panel = NULL;
  6952. int rc = 0;
  6953. display = container_of(dw, struct dsi_display, poms_te_work);
  6954. if (!display || !display->panel) {
  6955. DSI_ERR("Invalid params\n");
  6956. return;
  6957. }
  6958. panel = display->panel;
  6959. mutex_lock(&panel->panel_lock);
  6960. if (!dsi_panel_initialized(panel)) {
  6961. rc = -EINVAL;
  6962. goto error;
  6963. }
  6964. dsi = &panel->mipi_device;
  6965. rc = mipi_dsi_dcs_set_tear_off(dsi);
  6966. error:
  6967. mutex_unlock(&panel->panel_lock);
  6968. if (rc < 0)
  6969. DSI_ERR("failed to set tear off\n");
  6970. }
  6971. int dsi_display_disable(struct dsi_display *display)
  6972. {
  6973. int rc = 0;
  6974. if (!display) {
  6975. DSI_ERR("Invalid params\n");
  6976. return -EINVAL;
  6977. }
  6978. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6979. mutex_lock(&display->display_lock);
  6980. /* cancel delayed work */
  6981. if (display->poms_pending &&
  6982. display->panel->poms_align_vsync)
  6983. cancel_delayed_work_sync(&display->poms_te_work);
  6984. rc = dsi_display_wake_up(display);
  6985. if (rc)
  6986. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  6987. display->name, rc);
  6988. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6989. rc = dsi_display_vid_engine_disable(display);
  6990. if (rc)
  6991. DSI_ERR("[%s]failed to disable DSI vid engine, rc=%d\n",
  6992. display->name, rc);
  6993. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6994. /**
  6995. * On POMS request , disable panel TE through
  6996. * delayed work queue.
  6997. */
  6998. if (display->poms_pending &&
  6999. display->panel->poms_align_vsync) {
  7000. INIT_DELAYED_WORK(&display->poms_te_work,
  7001. dsi_display_handle_poms_te);
  7002. queue_delayed_work(system_wq,
  7003. &display->poms_te_work,
  7004. msecs_to_jiffies(100));
  7005. }
  7006. rc = dsi_display_cmd_engine_disable(display);
  7007. if (rc)
  7008. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  7009. display->name, rc);
  7010. } else {
  7011. DSI_ERR("[%s] Invalid configuration\n", display->name);
  7012. rc = -EINVAL;
  7013. }
  7014. if (!display->poms_pending && !is_skip_op_required(display)) {
  7015. rc = dsi_panel_disable(display->panel);
  7016. if (rc)
  7017. DSI_ERR("[%s] failed to disable DSI panel, rc=%d\n",
  7018. display->name, rc);
  7019. }
  7020. if (is_skip_op_required(display)) {
  7021. /* applicable only for trusted vm */
  7022. display->panel->panel_initialized = false;
  7023. display->panel->power_mode = SDE_MODE_DPMS_OFF;
  7024. }
  7025. mutex_unlock(&display->display_lock);
  7026. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7027. return rc;
  7028. }
  7029. int dsi_display_update_pps(char *pps_cmd, void *disp)
  7030. {
  7031. struct dsi_display *display;
  7032. if (pps_cmd == NULL || disp == NULL) {
  7033. DSI_ERR("Invalid parameter\n");
  7034. return -EINVAL;
  7035. }
  7036. display = disp;
  7037. mutex_lock(&display->display_lock);
  7038. memcpy(display->panel->dce_pps_cmd, pps_cmd, DSI_CMD_PPS_SIZE);
  7039. mutex_unlock(&display->display_lock);
  7040. return 0;
  7041. }
  7042. int dsi_display_update_dyn_bit_clk(struct dsi_display *display,
  7043. struct dsi_display_mode *mode)
  7044. {
  7045. struct dsi_dyn_clk_caps *dyn_clk_caps;
  7046. struct dsi_host_common_cfg *host_cfg;
  7047. int bpp, lanes = 0;
  7048. if (!display || !mode) {
  7049. DSI_ERR("invalid arguments\n");
  7050. return -EINVAL;
  7051. }
  7052. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  7053. if (!dyn_clk_caps->dyn_clk_support) {
  7054. DSI_DEBUG("dynamic bit clock support not enabled\n");
  7055. return 0;
  7056. } else if (!display->dyn_bit_clk_pending) {
  7057. DSI_DEBUG("dynamic bit clock rate not updated\n");
  7058. return 0;
  7059. } else if (!display->dyn_bit_clk) {
  7060. DSI_DEBUG("dynamic bit clock rate cleared\n");
  7061. return 0;
  7062. } else if (display->dyn_bit_clk < mode->priv_info->min_dsi_clk_hz) {
  7063. DSI_ERR("dynamic bit clock rate %llu smaller than minimum value:%llu\n",
  7064. display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz);
  7065. return -EINVAL;
  7066. }
  7067. /* update mode clk rate with user value */
  7068. mode->timing.clk_rate_hz = display->dyn_bit_clk;
  7069. mode->priv_info->clk_rate_hz = display->dyn_bit_clk;
  7070. host_cfg = &(display->panel->host_config);
  7071. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  7072. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  7073. lanes++;
  7074. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  7075. lanes++;
  7076. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  7077. lanes++;
  7078. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  7079. lanes++;
  7080. dsi_display_adjust_mode_timing(display, mode, lanes, bpp);
  7081. /* adjust pixel clock based on dynamic bit clock */
  7082. mode->pixel_clk_khz = div_u64(mode->timing.clk_rate_hz * lanes, bpp);
  7083. do_div(mode->pixel_clk_khz, 1000);
  7084. mode->pixel_clk_khz *= display->ctrl_count;
  7085. SDE_EVT32(display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz, mode->pixel_clk_khz);
  7086. DSI_DEBUG("dynamic bit clk:%u, min dsi clk:%llu, lanes:%d, bpp:%d, pck:%d Khz\n",
  7087. display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz, lanes, bpp,
  7088. mode->pixel_clk_khz);
  7089. display->dyn_bit_clk_pending = false;
  7090. return 0;
  7091. }
  7092. int dsi_display_dump_clks_state(struct dsi_display *display)
  7093. {
  7094. int rc = 0;
  7095. if (!display) {
  7096. DSI_ERR("invalid display argument\n");
  7097. return -EINVAL;
  7098. }
  7099. if (!display->clk_mngr) {
  7100. DSI_ERR("invalid clk manager\n");
  7101. return -EINVAL;
  7102. }
  7103. if (!display->dsi_clk_handle || !display->mdp_clk_handle) {
  7104. DSI_ERR("invalid clk handles\n");
  7105. return -EINVAL;
  7106. }
  7107. mutex_lock(&display->display_lock);
  7108. rc = dsi_display_dump_clk_handle_state(display->dsi_clk_handle);
  7109. if (rc) {
  7110. DSI_ERR("failed to dump dsi clock state\n");
  7111. goto end;
  7112. }
  7113. rc = dsi_display_dump_clk_handle_state(display->mdp_clk_handle);
  7114. if (rc) {
  7115. DSI_ERR("failed to dump mdp clock state\n");
  7116. goto end;
  7117. }
  7118. end:
  7119. mutex_unlock(&display->display_lock);
  7120. return rc;
  7121. }
  7122. int dsi_display_unprepare(struct dsi_display *display)
  7123. {
  7124. int rc = 0, i;
  7125. struct dsi_display_ctrl *ctrl;
  7126. if (!display) {
  7127. DSI_ERR("Invalid params\n");
  7128. return -EINVAL;
  7129. }
  7130. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7131. mutex_lock(&display->display_lock);
  7132. rc = dsi_display_wake_up(display);
  7133. if (rc)
  7134. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7135. display->name, rc);
  7136. if (!display->poms_pending && !is_skip_op_required(display)) {
  7137. rc = dsi_panel_unprepare(display->panel);
  7138. if (rc)
  7139. DSI_ERR("[%s] panel unprepare failed, rc=%d\n",
  7140. display->name, rc);
  7141. }
  7142. /* Remove additional vote added for pre_mode_switch_to_cmd */
  7143. if (display->poms_pending &&
  7144. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7145. display_for_each_ctrl(i, display) {
  7146. ctrl = &display->ctrl[i];
  7147. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  7148. continue;
  7149. flush_workqueue(display->dma_cmd_workq);
  7150. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  7151. ctrl->ctrl->dma_wait_queued = false;
  7152. }
  7153. dsi_display_cmd_engine_disable(display);
  7154. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7155. DSI_ALL_CLKS, DSI_CLK_OFF);
  7156. }
  7157. rc = dsi_display_ctrl_host_disable(display);
  7158. if (rc)
  7159. DSI_ERR("[%s] failed to disable DSI host, rc=%d\n",
  7160. display->name, rc);
  7161. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7162. DSI_LINK_CLK, DSI_CLK_OFF);
  7163. if (rc)
  7164. DSI_ERR("[%s] failed to disable Link clocks, rc=%d\n",
  7165. display->name, rc);
  7166. rc = dsi_display_ctrl_deinit(display);
  7167. if (rc)
  7168. DSI_ERR("[%s] failed to deinit controller, rc=%d\n",
  7169. display->name, rc);
  7170. if (!display->panel->ulps_suspend_enabled) {
  7171. rc = dsi_display_phy_disable(display);
  7172. if (rc)
  7173. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  7174. display->name, rc);
  7175. }
  7176. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7177. DSI_CORE_CLK, DSI_CLK_OFF);
  7178. if (rc)
  7179. DSI_ERR("[%s] failed to disable DSI clocks, rc=%d\n",
  7180. display->name, rc);
  7181. /* destrory dsi isr set up */
  7182. dsi_display_ctrl_isr_configure(display, false);
  7183. if (!display->poms_pending && !is_skip_op_required(display)) {
  7184. rc = dsi_panel_post_unprepare(display->panel);
  7185. if (rc)
  7186. DSI_ERR("[%s] panel post-unprepare failed, rc=%d\n",
  7187. display->name, rc);
  7188. }
  7189. mutex_unlock(&display->display_lock);
  7190. /* Free up DSI ERROR event callback */
  7191. dsi_display_unregister_error_handler(display);
  7192. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7193. return rc;
  7194. }
  7195. void __init dsi_display_register(void)
  7196. {
  7197. dsi_phy_drv_register();
  7198. dsi_ctrl_drv_register();
  7199. dsi_display_parse_boot_display_selection();
  7200. platform_driver_register(&dsi_display_driver);
  7201. }
  7202. void __exit dsi_display_unregister(void)
  7203. {
  7204. platform_driver_unregister(&dsi_display_driver);
  7205. dsi_ctrl_drv_unregister();
  7206. dsi_phy_drv_unregister();
  7207. }
  7208. module_param_string(dsi_display0, dsi_display_primary, MAX_CMDLINE_PARAM_LEN,
  7209. 0600);
  7210. MODULE_PARM_DESC(dsi_display0,
  7211. "msm_drm.dsi_display0=<display node>:<configX> where <display node> is 'primary dsi display node name' and <configX> where x represents index in the topology list");
  7212. module_param_string(dsi_display1, dsi_display_secondary, MAX_CMDLINE_PARAM_LEN,
  7213. 0600);
  7214. MODULE_PARM_DESC(dsi_display1,
  7215. "msm_drm.dsi_display1=<display node>:<configX> where <display node> is 'secondary dsi display node name' and <configX> where x represents index in the topology list");