wcd937x.c 99 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <linux/regmap.h>
  14. #include <linux/pm_runtime.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include <soc/soundwire.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <asoc/wcdcal-hwdep.h>
  21. #include <asoc/msm-cdc-pinctrl.h>
  22. #include <bindings/audio-codec-port-types.h>
  23. #include <asoc/msm-cdc-supply.h>
  24. #include "wcd937x-registers.h"
  25. #include "wcd937x.h"
  26. #include "internal.h"
  27. #include "asoc/bolero-slave-internal.h"
  28. #define WCD9370_VARIANT 0
  29. #define WCD9375_VARIANT 5
  30. #define WCD937X_VARIANT_ENTRY_SIZE 32
  31. #define NUM_SWRS_DT_PARAMS 5
  32. #define WCD937X_VERSION_1_0 1
  33. #define WCD937X_VERSION_ENTRY_SIZE 32
  34. #define EAR_RX_PATH_AUX 1
  35. #define NUM_ATTEMPTS 5
  36. #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  37. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  38. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  39. SNDRV_PCM_RATE_384000)
  40. /* Fractional Rates */
  41. #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  42. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  43. #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  44. SNDRV_PCM_FMTBIT_S24_LE |\
  45. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  46. enum {
  47. CODEC_TX = 0,
  48. CODEC_RX,
  49. };
  50. enum {
  51. ALLOW_BUCK_DISABLE,
  52. HPH_COMP_DELAY,
  53. HPH_PA_DELAY,
  54. AMIC2_BCS_ENABLE,
  55. };
  56. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  57. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  58. static int wcd937x_handle_post_irq(void *data);
  59. static int wcd937x_reset(struct device *dev);
  60. static int wcd937x_reset_low(struct device *dev);
  61. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  62. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  71. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  72. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  73. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  74. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  75. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  76. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  77. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  78. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  79. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  80. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  81. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  82. };
  83. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  84. .name = "wcd937x",
  85. .irqs = wcd937x_irqs,
  86. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  87. .num_regs = 3,
  88. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  89. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  90. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  91. .use_ack = 1,
  92. //#if IS_ENABLED(CONFIG_AUDIO_QGKI)
  93. .clear_ack = 1,
  94. //#endif
  95. .mask_writeonly = 1,
  96. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  97. .runtime_pm = false,
  98. .handle_post_irq = wcd937x_handle_post_irq,
  99. .irq_drv_data = NULL,
  100. };
  101. static struct snd_soc_dai_driver wcd937x_dai[] = {
  102. {
  103. .name = "wcd937x_cdc",
  104. .playback = {
  105. .stream_name = "WCD937X_AIF Playback",
  106. .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
  107. .formats = WCD937X_FORMATS,
  108. .rate_max = 384000,
  109. .rate_min = 8000,
  110. .channels_min = 1,
  111. .channels_max = 4,
  112. },
  113. .capture = {
  114. .stream_name = "WCD937X_AIF Capture",
  115. .rates = WCD937X_RATES,
  116. .formats = WCD937X_FORMATS,
  117. .rate_max = 192000,
  118. .rate_min = 8000,
  119. .channels_min = 1,
  120. .channels_max = 4,
  121. },
  122. },
  123. };
  124. static int wcd937x_handle_post_irq(void *data)
  125. {
  126. struct wcd937x_priv *wcd937x = data;
  127. u32 status1 = 0, status2 = 0, status3 = 0;
  128. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  129. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  130. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  131. wcd937x->tx_swr_dev->slave_irq_pending =
  132. ((status1 || status2 || status3) ? true : false);
  133. return IRQ_HANDLED;
  134. }
  135. static int wcd937x_init_reg(struct snd_soc_component *component)
  136. {
  137. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  138. 0x0E, 0x0E);
  139. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  140. 0x80, 0x80);
  141. usleep_range(1000, 1010);
  142. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  143. 0x40, 0x40);
  144. usleep_range(1000, 1010);
  145. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  146. 0x10, 0x00);
  147. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  148. 0xF0, 0x80);
  149. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  150. 0x80, 0x80);
  151. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  152. 0x40, 0x40);
  153. usleep_range(10000, 10010);
  154. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  155. 0x40, 0x00);
  156. snd_soc_component_update_bits(component,
  157. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  158. 0xFF, 0xD9);
  159. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  160. 0xFF, 0xFA);
  161. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  162. 0xFF, 0xFA);
  163. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  164. 0xFF, 0xFA);
  165. return 0;
  166. }
  167. static int wcd937x_set_port_params(struct snd_soc_component *component,
  168. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  169. u8 *ch_mask, u32 *ch_rate,
  170. u8 *port_type, u8 path)
  171. {
  172. int i, j;
  173. u8 num_ports = 0;
  174. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  175. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  176. switch (path) {
  177. case CODEC_RX:
  178. map = &wcd937x->rx_port_mapping;
  179. num_ports = wcd937x->num_rx_ports;
  180. break;
  181. case CODEC_TX:
  182. map = &wcd937x->tx_port_mapping;
  183. num_ports = wcd937x->num_tx_ports;
  184. break;
  185. default:
  186. dev_err(component->dev, "%s Invalid path selected %u\n",
  187. __func__, path);
  188. return -EINVAL;
  189. }
  190. for (i = 0; i <= num_ports; i++) {
  191. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  192. if ((*map)[i][j].slave_port_type == slv_prt_type)
  193. goto found;
  194. }
  195. }
  196. found:
  197. if (i > num_ports || j == MAX_CH_PER_PORT) {
  198. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  199. __func__, slv_prt_type);
  200. return -EINVAL;
  201. }
  202. *port_id = i;
  203. *num_ch = (*map)[i][j].num_ch;
  204. *ch_mask = (*map)[i][j].ch_mask;
  205. *ch_rate = (*map)[i][j].ch_rate;
  206. *port_type = (*map)[i][j].master_port_type;
  207. return 0;
  208. }
  209. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  210. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  211. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  212. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  213. static int wcd937x_parse_port_params(struct device *dev,
  214. char *prop, u8 path)
  215. {
  216. u32 *dt_array, map_size, max_uc;
  217. int ret = 0;
  218. u32 cnt = 0;
  219. u32 i, j;
  220. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  221. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  222. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  223. switch (path) {
  224. case CODEC_TX:
  225. map = &wcd937x->tx_port_params;
  226. map_uc = &wcd937x->swr_tx_port_params;
  227. break;
  228. default:
  229. ret = -EINVAL;
  230. goto err_port_map;
  231. }
  232. if (!of_find_property(dev->of_node, prop,
  233. &map_size)) {
  234. dev_err(dev, "missing port mapping prop %s\n", prop);
  235. ret = -EINVAL;
  236. goto err_port_map;
  237. }
  238. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  239. if (max_uc != SWR_UC_MAX) {
  240. dev_err(dev, "%s: port params not provided for all usecases\n",
  241. __func__);
  242. ret = -EINVAL;
  243. goto err_port_map;
  244. }
  245. dt_array = kzalloc(map_size, GFP_KERNEL);
  246. if (!dt_array) {
  247. ret = -ENOMEM;
  248. goto err_alloc;
  249. }
  250. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  251. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  252. if (ret) {
  253. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  254. __func__, prop);
  255. goto err_pdata_fail;
  256. }
  257. for (i = 0; i < max_uc; i++) {
  258. for (j = 0; j < SWR_NUM_PORTS; j++) {
  259. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  260. (*map)[i][j].offset1 = dt_array[cnt];
  261. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  262. }
  263. (*map_uc)[i].pp = &(*map)[i][0];
  264. }
  265. kfree(dt_array);
  266. return 0;
  267. err_pdata_fail:
  268. kfree(dt_array);
  269. err_alloc:
  270. err_port_map:
  271. return ret;
  272. }
  273. static int wcd937x_parse_port_mapping(struct device *dev,
  274. char *prop, u8 path)
  275. {
  276. u32 *dt_array, map_size, map_length;
  277. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  278. u32 slave_port_type, master_port_type;
  279. u32 i, ch_iter = 0;
  280. int ret = 0;
  281. u8 *num_ports = NULL;
  282. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  283. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  284. switch (path) {
  285. case CODEC_RX:
  286. map = &wcd937x->rx_port_mapping;
  287. num_ports = &wcd937x->num_rx_ports;
  288. break;
  289. case CODEC_TX:
  290. map = &wcd937x->tx_port_mapping;
  291. num_ports = &wcd937x->num_tx_ports;
  292. break;
  293. default:
  294. dev_err(dev, "%s Invalid path selected %u\n",
  295. __func__, path);
  296. return -EINVAL;
  297. }
  298. if (!of_find_property(dev->of_node, prop,
  299. &map_size)) {
  300. dev_err(dev, "missing port mapping prop %s\n", prop);
  301. ret = -EINVAL;
  302. goto err;
  303. }
  304. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  305. dt_array = kzalloc(map_size, GFP_KERNEL);
  306. if (!dt_array) {
  307. ret = -ENOMEM;
  308. goto err;
  309. }
  310. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  311. NUM_SWRS_DT_PARAMS * map_length);
  312. if (ret) {
  313. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  314. __func__, prop);
  315. ret = -EINVAL;
  316. goto err_pdata_fail;
  317. }
  318. for (i = 0; i < map_length; i++) {
  319. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  320. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  321. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  322. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  323. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  324. if (port_num != old_port_num)
  325. ch_iter = 0;
  326. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  327. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  328. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  329. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  330. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  331. old_port_num = port_num;
  332. }
  333. *num_ports = port_num;
  334. kfree(dt_array);
  335. return 0;
  336. err_pdata_fail:
  337. kfree(dt_array);
  338. err:
  339. return ret;
  340. }
  341. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  342. u8 slv_port_type, u8 enable)
  343. {
  344. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  345. u8 port_id;
  346. u8 num_ch;
  347. u8 ch_mask;
  348. u32 ch_rate;
  349. u8 ch_type = 0;
  350. int slave_ch_idx;
  351. u8 num_port = 1;
  352. int ret = 0;
  353. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  354. &num_ch, &ch_mask, &ch_rate,
  355. &ch_type, CODEC_TX);
  356. if (ret)
  357. return ret;
  358. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  359. if (slave_ch_idx != -EINVAL)
  360. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  361. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  362. __func__, slave_ch_idx, ch_type);
  363. if (enable)
  364. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  365. num_port, &ch_mask, &ch_rate,
  366. &num_ch, &ch_type);
  367. else
  368. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  369. num_port, &ch_mask, &ch_type);
  370. return ret;
  371. }
  372. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  373. u8 slv_port_type, u8 enable)
  374. {
  375. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  376. u8 port_id;
  377. u8 num_ch;
  378. u8 ch_mask;
  379. u32 ch_rate;
  380. u8 port_type;
  381. u8 num_port = 1;
  382. int ret = 0;
  383. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  384. &num_ch, &ch_mask, &ch_rate,
  385. &port_type, CODEC_RX);
  386. if (ret)
  387. return ret;
  388. if (enable)
  389. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  390. num_port, &ch_mask, &ch_rate,
  391. &num_ch, &port_type);
  392. else
  393. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  394. num_port, &ch_mask, &port_type);
  395. return ret;
  396. }
  397. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  398. {
  399. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  400. if (wcd937x->rx_clk_cnt == 0) {
  401. snd_soc_component_update_bits(component,
  402. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  403. snd_soc_component_update_bits(component,
  404. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  405. snd_soc_component_update_bits(component,
  406. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  407. snd_soc_component_update_bits(component,
  408. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  409. snd_soc_component_update_bits(component,
  410. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  411. snd_soc_component_update_bits(component,
  412. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  413. snd_soc_component_update_bits(component,
  414. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  415. }
  416. wcd937x->rx_clk_cnt++;
  417. return 0;
  418. }
  419. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  420. {
  421. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  422. if (wcd937x->rx_clk_cnt == 0) {
  423. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  424. return 0;
  425. }
  426. wcd937x->rx_clk_cnt--;
  427. if (wcd937x->rx_clk_cnt == 0) {
  428. snd_soc_component_update_bits(component,
  429. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  430. snd_soc_component_update_bits(component,
  431. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  432. 0x02, 0x00);
  433. snd_soc_component_update_bits(component,
  434. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  435. 0x01, 0x00);
  436. }
  437. return 0;
  438. }
  439. /*
  440. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  441. * @component: handle to snd_soc_component *
  442. *
  443. * return wcd937x_mbhc handle or error code in case of failure
  444. */
  445. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  446. {
  447. struct wcd937x_priv *wcd937x;
  448. if (!component) {
  449. pr_err("%s: Invalid params, NULL component\n", __func__);
  450. return NULL;
  451. }
  452. wcd937x = snd_soc_component_get_drvdata(component);
  453. if (!wcd937x) {
  454. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  455. return NULL;
  456. }
  457. return wcd937x->mbhc;
  458. }
  459. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  460. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  461. struct snd_kcontrol *kcontrol,
  462. int event)
  463. {
  464. struct snd_soc_component *component =
  465. snd_soc_dapm_to_component(w->dapm);
  466. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  467. int hph_mode = wcd937x->hph_mode;
  468. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  469. w->name, event);
  470. switch (event) {
  471. case SND_SOC_DAPM_PRE_PMU:
  472. wcd937x_rx_clk_enable(component);
  473. snd_soc_component_update_bits(component,
  474. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  475. 0x01, 0x01);
  476. snd_soc_component_update_bits(component,
  477. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  478. 0x04, 0x04);
  479. snd_soc_component_update_bits(component,
  480. WCD937X_HPH_RDAC_CLK_CTL1,
  481. 0x80, 0x00);
  482. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  483. break;
  484. case SND_SOC_DAPM_POST_PMU:
  485. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  486. snd_soc_component_update_bits(component,
  487. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  488. 0x0F, 0x02);
  489. else if (hph_mode == CLS_H_LOHIFI)
  490. snd_soc_component_update_bits(component,
  491. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  492. 0x0F, 0x06);
  493. if (wcd937x->comp1_enable) {
  494. snd_soc_component_update_bits(component,
  495. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  496. 0x02, 0x02);
  497. snd_soc_component_update_bits(component,
  498. WCD937X_HPH_L_EN, 0x20, 0x00);
  499. if (wcd937x->comp2_enable) {
  500. snd_soc_component_update_bits(component,
  501. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  502. 0x01, 0x01);
  503. snd_soc_component_update_bits(component,
  504. WCD937X_HPH_R_EN, 0x20, 0x00);
  505. }
  506. /*
  507. * 5ms sleep is required after COMP is enabled as per
  508. * HW requirement
  509. */
  510. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  511. usleep_range(5000, 5100);
  512. clear_bit(HPH_COMP_DELAY,
  513. &wcd937x->status_mask);
  514. }
  515. } else {
  516. snd_soc_component_update_bits(component,
  517. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  518. 0x02, 0x00);
  519. snd_soc_component_update_bits(component,
  520. WCD937X_HPH_L_EN, 0x20, 0x20);
  521. }
  522. snd_soc_component_update_bits(component,
  523. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  524. break;
  525. case SND_SOC_DAPM_POST_PMD:
  526. snd_soc_component_update_bits(component,
  527. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  528. 0x0F, 0x01);
  529. break;
  530. }
  531. return 0;
  532. }
  533. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  534. struct snd_kcontrol *kcontrol,
  535. int event)
  536. {
  537. struct snd_soc_component *component =
  538. snd_soc_dapm_to_component(w->dapm);
  539. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  540. int hph_mode = wcd937x->hph_mode;
  541. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  542. w->name, event);
  543. switch (event) {
  544. case SND_SOC_DAPM_PRE_PMU:
  545. wcd937x_rx_clk_enable(component);
  546. snd_soc_component_update_bits(component,
  547. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  548. snd_soc_component_update_bits(component,
  549. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  550. snd_soc_component_update_bits(component,
  551. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  552. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  553. break;
  554. case SND_SOC_DAPM_POST_PMU:
  555. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  556. snd_soc_component_update_bits(component,
  557. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  558. 0x0F, 0x02);
  559. else if (hph_mode == CLS_H_LOHIFI)
  560. snd_soc_component_update_bits(component,
  561. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  562. 0x0F, 0x06);
  563. if (wcd937x->comp2_enable) {
  564. snd_soc_component_update_bits(component,
  565. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  566. 0x01, 0x01);
  567. snd_soc_component_update_bits(component,
  568. WCD937X_HPH_R_EN, 0x20, 0x00);
  569. if (wcd937x->comp1_enable) {
  570. snd_soc_component_update_bits(component,
  571. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  572. 0x02, 0x02);
  573. snd_soc_component_update_bits(component,
  574. WCD937X_HPH_L_EN, 0x20, 0x00);
  575. }
  576. /*
  577. * 5ms sleep is required after COMP is enabled as per
  578. * HW requirement
  579. */
  580. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  581. usleep_range(5000, 5100);
  582. clear_bit(HPH_COMP_DELAY,
  583. &wcd937x->status_mask);
  584. }
  585. } else {
  586. snd_soc_component_update_bits(component,
  587. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  588. 0x01, 0x00);
  589. snd_soc_component_update_bits(component,
  590. WCD937X_HPH_R_EN, 0x20, 0x20);
  591. }
  592. snd_soc_component_update_bits(component,
  593. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  594. break;
  595. case SND_SOC_DAPM_POST_PMD:
  596. snd_soc_component_update_bits(component,
  597. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  598. 0x0F, 0x01);
  599. break;
  600. }
  601. return 0;
  602. }
  603. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  604. struct snd_kcontrol *kcontrol,
  605. int event)
  606. {
  607. struct snd_soc_component *component =
  608. snd_soc_dapm_to_component(w->dapm);
  609. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  610. int hph_mode = wcd937x->hph_mode;
  611. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  612. w->name, event);
  613. switch (event) {
  614. case SND_SOC_DAPM_PRE_PMU:
  615. wcd937x_rx_clk_enable(component);
  616. snd_soc_component_update_bits(component,
  617. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  618. 0x04, 0x04);
  619. snd_soc_component_update_bits(component,
  620. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  621. 0x01, 0x01);
  622. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  623. snd_soc_component_update_bits(component,
  624. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  625. 0x0F, 0x02);
  626. else if (hph_mode == CLS_H_LOHIFI)
  627. snd_soc_component_update_bits(component,
  628. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  629. 0x0F, 0x06);
  630. if (wcd937x->comp1_enable)
  631. snd_soc_component_update_bits(component,
  632. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  633. 0x02, 0x02);
  634. usleep_range(5000, 5010);
  635. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  636. 0x04, 0x00);
  637. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  638. WCD_CLSH_EVENT_PRE_DAC,
  639. WCD_CLSH_STATE_EAR,
  640. hph_mode);
  641. break;
  642. case SND_SOC_DAPM_POST_PMD:
  643. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  644. hph_mode == CLS_H_HIFI)
  645. snd_soc_component_update_bits(component,
  646. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  647. 0x0F, 0x01);
  648. if (wcd937x->comp1_enable)
  649. snd_soc_component_update_bits(component,
  650. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  651. 0x02, 0x00);
  652. break;
  653. };
  654. return 0;
  655. }
  656. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  657. struct snd_kcontrol *kcontrol,
  658. int event)
  659. {
  660. struct snd_soc_component *component =
  661. snd_soc_dapm_to_component(w->dapm);
  662. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  663. int hph_mode = wcd937x->hph_mode;
  664. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  665. w->name, event);
  666. switch (event) {
  667. case SND_SOC_DAPM_PRE_PMU:
  668. wcd937x_rx_clk_enable(component);
  669. snd_soc_component_update_bits(component,
  670. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  671. 0x04, 0x04);
  672. snd_soc_component_update_bits(component,
  673. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  674. 0x04, 0x04);
  675. snd_soc_component_update_bits(component,
  676. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  677. 0x01, 0x01);
  678. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  679. WCD_CLSH_EVENT_PRE_DAC,
  680. WCD_CLSH_STATE_AUX,
  681. hph_mode);
  682. break;
  683. case SND_SOC_DAPM_POST_PMD:
  684. snd_soc_component_update_bits(component,
  685. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  686. 0x04, 0x00);
  687. break;
  688. };
  689. return 0;
  690. }
  691. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  692. struct snd_kcontrol *kcontrol,
  693. int event)
  694. {
  695. struct snd_soc_component *component =
  696. snd_soc_dapm_to_component(w->dapm);
  697. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  698. int ret = 0;
  699. int hph_mode = wcd937x->hph_mode;
  700. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  701. w->name, event);
  702. switch (event) {
  703. case SND_SOC_DAPM_PRE_PMU:
  704. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  705. wcd937x->rx_swr_dev->dev_num,
  706. true);
  707. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  708. WCD_CLSH_EVENT_PRE_DAC,
  709. WCD_CLSH_STATE_HPHR,
  710. hph_mode);
  711. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  712. 0x10, 0x10);
  713. usleep_range(100, 110);
  714. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  715. snd_soc_component_update_bits(component,
  716. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  717. break;
  718. case SND_SOC_DAPM_POST_PMU:
  719. /*
  720. * 7ms sleep is required after PA is enabled as per
  721. * HW requirement. If compander is disabled, then
  722. * 20ms delay is required.
  723. */
  724. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  725. if (!wcd937x->comp2_enable)
  726. usleep_range(20000, 20100);
  727. else
  728. usleep_range(7000, 7100);
  729. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  730. }
  731. snd_soc_component_update_bits(component,
  732. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  733. 0x02, 0x02);
  734. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  735. snd_soc_component_update_bits(component,
  736. WCD937X_ANA_RX_SUPPLIES,
  737. 0x02, 0x02);
  738. if (wcd937x->update_wcd_event)
  739. wcd937x->update_wcd_event(wcd937x->handle,
  740. SLV_BOLERO_EVT_RX_MUTE,
  741. (WCD_RX2 << 0x10));
  742. wcd_enable_irq(&wcd937x->irq_info,
  743. WCD937X_IRQ_HPHR_PDM_WD_INT);
  744. break;
  745. case SND_SOC_DAPM_PRE_PMD:
  746. wcd_disable_irq(&wcd937x->irq_info,
  747. WCD937X_IRQ_HPHR_PDM_WD_INT);
  748. if (wcd937x->update_wcd_event)
  749. wcd937x->update_wcd_event(wcd937x->handle,
  750. SLV_BOLERO_EVT_RX_MUTE,
  751. (WCD_RX2 << 0x10 | 0x1));
  752. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  753. WCD_EVENT_PRE_HPHR_PA_OFF,
  754. &wcd937x->mbhc->wcd_mbhc);
  755. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  756. break;
  757. case SND_SOC_DAPM_POST_PMD:
  758. /*
  759. * 7ms sleep is required after PA is disabled as per
  760. * HW requirement. If compander is disabled, then
  761. * 20ms delay is required.
  762. */
  763. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  764. if (!wcd937x->comp2_enable)
  765. usleep_range(20000, 20100);
  766. else
  767. usleep_range(7000, 7100);
  768. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  769. }
  770. snd_soc_component_update_bits(component,
  771. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  772. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  773. WCD_EVENT_POST_HPHR_PA_OFF,
  774. &wcd937x->mbhc->wcd_mbhc);
  775. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  776. 0x10, 0x00);
  777. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  778. WCD_CLSH_EVENT_POST_PA,
  779. WCD_CLSH_STATE_HPHR,
  780. hph_mode);
  781. break;
  782. };
  783. return ret;
  784. }
  785. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  786. struct snd_kcontrol *kcontrol,
  787. int event)
  788. {
  789. struct snd_soc_component *component =
  790. snd_soc_dapm_to_component(w->dapm);
  791. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  792. int ret = 0;
  793. int hph_mode = wcd937x->hph_mode;
  794. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  795. w->name, event);
  796. switch (event) {
  797. case SND_SOC_DAPM_PRE_PMU:
  798. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  799. wcd937x->rx_swr_dev->dev_num,
  800. true);
  801. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  802. WCD_CLSH_EVENT_PRE_DAC,
  803. WCD_CLSH_STATE_HPHL,
  804. hph_mode);
  805. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  806. 0x20, 0x20);
  807. usleep_range(100, 110);
  808. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  809. snd_soc_component_update_bits(component,
  810. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  811. break;
  812. case SND_SOC_DAPM_POST_PMU:
  813. /*
  814. * 7ms sleep is required after PA is enabled as per
  815. * HW requirement. If compander is disabled, then
  816. * 20ms delay is required.
  817. */
  818. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  819. if (!wcd937x->comp1_enable)
  820. usleep_range(20000, 20100);
  821. else
  822. usleep_range(7000, 7100);
  823. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  824. }
  825. snd_soc_component_update_bits(component,
  826. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  827. 0x02, 0x02);
  828. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  829. snd_soc_component_update_bits(component,
  830. WCD937X_ANA_RX_SUPPLIES,
  831. 0x02, 0x02);
  832. if (wcd937x->update_wcd_event)
  833. wcd937x->update_wcd_event(wcd937x->handle,
  834. SLV_BOLERO_EVT_RX_MUTE,
  835. (WCD_RX1 << 0x10));
  836. wcd_enable_irq(&wcd937x->irq_info,
  837. WCD937X_IRQ_HPHL_PDM_WD_INT);
  838. break;
  839. case SND_SOC_DAPM_PRE_PMD:
  840. wcd_disable_irq(&wcd937x->irq_info,
  841. WCD937X_IRQ_HPHL_PDM_WD_INT);
  842. if (wcd937x->update_wcd_event)
  843. wcd937x->update_wcd_event(wcd937x->handle,
  844. SLV_BOLERO_EVT_RX_MUTE,
  845. (WCD_RX1 << 0x10 | 0x1));
  846. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  847. WCD_EVENT_PRE_HPHL_PA_OFF,
  848. &wcd937x->mbhc->wcd_mbhc);
  849. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  850. break;
  851. case SND_SOC_DAPM_POST_PMD:
  852. /*
  853. * 7ms sleep is required after PA is disabled as per
  854. * HW requirement. If compander is disabled, then
  855. * 20ms delay is required.
  856. */
  857. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  858. if (!wcd937x->comp1_enable)
  859. usleep_range(20000, 20100);
  860. else
  861. usleep_range(7000, 7100);
  862. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  863. }
  864. snd_soc_component_update_bits(component,
  865. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  866. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  867. WCD_EVENT_POST_HPHL_PA_OFF,
  868. &wcd937x->mbhc->wcd_mbhc);
  869. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  870. 0x20, 0x00);
  871. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  872. WCD_CLSH_EVENT_POST_PA,
  873. WCD_CLSH_STATE_HPHL,
  874. hph_mode);
  875. break;
  876. };
  877. return ret;
  878. }
  879. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  880. struct snd_kcontrol *kcontrol,
  881. int event)
  882. {
  883. struct snd_soc_component *component =
  884. snd_soc_dapm_to_component(w->dapm);
  885. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  886. int hph_mode = wcd937x->hph_mode;
  887. int ret = 0;
  888. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  889. w->name, event);
  890. switch (event) {
  891. case SND_SOC_DAPM_PRE_PMU:
  892. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  893. wcd937x->rx_swr_dev->dev_num,
  894. true);
  895. snd_soc_component_update_bits(component,
  896. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  897. break;
  898. case SND_SOC_DAPM_POST_PMU:
  899. usleep_range(1000, 1010);
  900. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  901. snd_soc_component_update_bits(component,
  902. WCD937X_ANA_RX_SUPPLIES,
  903. 0x02, 0x02);
  904. if (wcd937x->update_wcd_event)
  905. wcd937x->update_wcd_event(wcd937x->handle,
  906. SLV_BOLERO_EVT_RX_MUTE,
  907. (WCD_RX3 << 0x10));
  908. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  909. break;
  910. case SND_SOC_DAPM_PRE_PMD:
  911. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  912. if (wcd937x->update_wcd_event)
  913. wcd937x->update_wcd_event(wcd937x->handle,
  914. SLV_BOLERO_EVT_RX_MUTE,
  915. (WCD_RX3 << 0x10 | 0x1));
  916. break;
  917. case SND_SOC_DAPM_POST_PMD:
  918. /* Add delay as per hw requirement */
  919. usleep_range(2000, 2010);
  920. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  921. WCD_CLSH_EVENT_POST_PA,
  922. WCD_CLSH_STATE_AUX,
  923. hph_mode);
  924. snd_soc_component_update_bits(component,
  925. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  926. break;
  927. };
  928. return ret;
  929. }
  930. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  931. struct snd_kcontrol *kcontrol,
  932. int event)
  933. {
  934. struct snd_soc_component *component =
  935. snd_soc_dapm_to_component(w->dapm);
  936. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  937. int hph_mode = wcd937x->hph_mode;
  938. int ret = 0;
  939. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  940. w->name, event);
  941. switch (event) {
  942. case SND_SOC_DAPM_PRE_PMU:
  943. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  944. wcd937x->rx_swr_dev->dev_num,
  945. true);
  946. /*
  947. * Enable watchdog interrupt for HPHL or AUX
  948. * depending on mux value
  949. */
  950. wcd937x->ear_rx_path =
  951. snd_soc_component_read(
  952. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  953. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  954. snd_soc_component_update_bits(component,
  955. WCD937X_DIGITAL_PDM_WD_CTL2,
  956. 0x05, 0x05);
  957. else
  958. snd_soc_component_update_bits(component,
  959. WCD937X_DIGITAL_PDM_WD_CTL0,
  960. 0x17, 0x13);
  961. if (!wcd937x->comp1_enable)
  962. snd_soc_component_update_bits(component,
  963. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  964. break;
  965. case SND_SOC_DAPM_POST_PMU:
  966. usleep_range(6000, 6010);
  967. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  968. snd_soc_component_update_bits(component,
  969. WCD937X_ANA_RX_SUPPLIES,
  970. 0x02, 0x02);
  971. if (wcd937x->update_wcd_event)
  972. wcd937x->update_wcd_event(wcd937x->handle,
  973. SLV_BOLERO_EVT_RX_MUTE,
  974. (WCD_RX1 << 0x10));
  975. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  976. wcd_enable_irq(&wcd937x->irq_info,
  977. WCD937X_IRQ_AUX_PDM_WD_INT);
  978. else
  979. wcd_enable_irq(&wcd937x->irq_info,
  980. WCD937X_IRQ_HPHL_PDM_WD_INT);
  981. break;
  982. case SND_SOC_DAPM_PRE_PMD:
  983. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  984. wcd_disable_irq(&wcd937x->irq_info,
  985. WCD937X_IRQ_AUX_PDM_WD_INT);
  986. else
  987. wcd_disable_irq(&wcd937x->irq_info,
  988. WCD937X_IRQ_HPHL_PDM_WD_INT);
  989. if (wcd937x->update_wcd_event)
  990. wcd937x->update_wcd_event(wcd937x->handle,
  991. SLV_BOLERO_EVT_RX_MUTE,
  992. (WCD_RX1 << 0x10 | 0x1));
  993. break;
  994. case SND_SOC_DAPM_POST_PMD:
  995. if (!wcd937x->comp1_enable)
  996. snd_soc_component_update_bits(component,
  997. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  998. usleep_range(7000, 7010);
  999. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  1000. WCD_CLSH_EVENT_POST_PA,
  1001. WCD_CLSH_STATE_EAR,
  1002. hph_mode);
  1003. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  1004. 0x04, 0x04);
  1005. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1006. snd_soc_component_update_bits(component,
  1007. WCD937X_DIGITAL_PDM_WD_CTL2,
  1008. 0x05, 0x00);
  1009. else
  1010. snd_soc_component_update_bits(component,
  1011. WCD937X_DIGITAL_PDM_WD_CTL0,
  1012. 0x17, 0x00);
  1013. break;
  1014. };
  1015. return ret;
  1016. }
  1017. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  1018. struct snd_kcontrol *kcontrol,
  1019. int event)
  1020. {
  1021. struct snd_soc_component *component =
  1022. snd_soc_dapm_to_component(w->dapm);
  1023. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1024. int mode = wcd937x->hph_mode;
  1025. int ret = 0;
  1026. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1027. w->name, event);
  1028. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1029. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1030. wcd937x_rx_connect_port(component, CLSH,
  1031. SND_SOC_DAPM_EVENT_ON(event));
  1032. }
  1033. if (SND_SOC_DAPM_EVENT_OFF(event))
  1034. ret = swr_slvdev_datapath_control(
  1035. wcd937x->rx_swr_dev,
  1036. wcd937x->rx_swr_dev->dev_num,
  1037. false);
  1038. return ret;
  1039. }
  1040. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  1041. struct snd_kcontrol *kcontrol,
  1042. int event)
  1043. {
  1044. struct snd_soc_component *component =
  1045. snd_soc_dapm_to_component(w->dapm);
  1046. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1047. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1048. w->name, event);
  1049. switch (event) {
  1050. case SND_SOC_DAPM_PRE_PMU:
  1051. wcd937x_rx_connect_port(component, HPH_L, true);
  1052. if (wcd937x->comp1_enable)
  1053. wcd937x_rx_connect_port(component, COMP_L, true);
  1054. break;
  1055. case SND_SOC_DAPM_POST_PMD:
  1056. wcd937x_rx_connect_port(component, HPH_L, false);
  1057. if (wcd937x->comp1_enable)
  1058. wcd937x_rx_connect_port(component, COMP_L, false);
  1059. wcd937x_rx_clk_disable(component);
  1060. snd_soc_component_update_bits(component,
  1061. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1062. 0x01, 0x00);
  1063. break;
  1064. };
  1065. return 0;
  1066. }
  1067. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  1068. struct snd_kcontrol *kcontrol, int event)
  1069. {
  1070. struct snd_soc_component *component =
  1071. snd_soc_dapm_to_component(w->dapm);
  1072. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1073. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1074. w->name, event);
  1075. switch (event) {
  1076. case SND_SOC_DAPM_PRE_PMU:
  1077. wcd937x_rx_connect_port(component, HPH_R, true);
  1078. if (wcd937x->comp2_enable)
  1079. wcd937x_rx_connect_port(component, COMP_R, true);
  1080. break;
  1081. case SND_SOC_DAPM_POST_PMD:
  1082. wcd937x_rx_connect_port(component, HPH_R, false);
  1083. if (wcd937x->comp2_enable)
  1084. wcd937x_rx_connect_port(component, COMP_R, false);
  1085. wcd937x_rx_clk_disable(component);
  1086. snd_soc_component_update_bits(component,
  1087. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1088. 0x02, 0x00);
  1089. break;
  1090. };
  1091. return 0;
  1092. }
  1093. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  1094. struct snd_kcontrol *kcontrol,
  1095. int event)
  1096. {
  1097. struct snd_soc_component *component =
  1098. snd_soc_dapm_to_component(w->dapm);
  1099. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1100. w->name, event);
  1101. switch (event) {
  1102. case SND_SOC_DAPM_PRE_PMU:
  1103. wcd937x_rx_connect_port(component, LO, true);
  1104. break;
  1105. case SND_SOC_DAPM_POST_PMD:
  1106. wcd937x_rx_connect_port(component, LO, false);
  1107. usleep_range(6000, 6010);
  1108. wcd937x_rx_clk_disable(component);
  1109. snd_soc_component_update_bits(component,
  1110. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1111. break;
  1112. }
  1113. return 0;
  1114. }
  1115. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1116. struct snd_kcontrol *kcontrol,
  1117. int event)
  1118. {
  1119. struct snd_soc_component *component =
  1120. snd_soc_dapm_to_component(w->dapm);
  1121. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1122. u16 dmic_clk_reg;
  1123. s32 *dmic_clk_cnt;
  1124. unsigned int dmic;
  1125. char *wname;
  1126. int ret = 0;
  1127. wname = strpbrk(w->name, "012345");
  1128. if (!wname) {
  1129. dev_err(component->dev, "%s: widget not found\n", __func__);
  1130. return -EINVAL;
  1131. }
  1132. ret = kstrtouint(wname, 10, &dmic);
  1133. if (ret < 0) {
  1134. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1135. __func__);
  1136. return -EINVAL;
  1137. }
  1138. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1139. w->name, event);
  1140. switch (dmic) {
  1141. case 0:
  1142. case 1:
  1143. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1144. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1145. break;
  1146. case 2:
  1147. case 3:
  1148. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1149. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1150. break;
  1151. case 4:
  1152. case 5:
  1153. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1154. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1155. break;
  1156. default:
  1157. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1158. __func__);
  1159. return -EINVAL;
  1160. };
  1161. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1162. __func__, event, dmic, *dmic_clk_cnt);
  1163. switch (event) {
  1164. case SND_SOC_DAPM_PRE_PMU:
  1165. snd_soc_component_update_bits(component,
  1166. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1167. snd_soc_component_update_bits(component,
  1168. dmic_clk_reg, 0x07, 0x02);
  1169. snd_soc_component_update_bits(component,
  1170. dmic_clk_reg, 0x08, 0x08);
  1171. snd_soc_component_update_bits(component,
  1172. dmic_clk_reg, 0x70, 0x20);
  1173. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1174. wcd937x->tx_swr_dev->dev_num,
  1175. true);
  1176. break;
  1177. case SND_SOC_DAPM_POST_PMD:
  1178. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1179. break;
  1180. };
  1181. return 0;
  1182. }
  1183. /*
  1184. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1185. * @micb_mv: micbias in mv
  1186. *
  1187. * return register value converted
  1188. */
  1189. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1190. {
  1191. /* min micbias voltage is 1V and maximum is 2.85V */
  1192. if (micb_mv < 1000 || micb_mv > 2850) {
  1193. pr_err("%s: unsupported micbias voltage\n", __func__);
  1194. return -EINVAL;
  1195. }
  1196. return (micb_mv - 1000) / 50;
  1197. }
  1198. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1199. /*
  1200. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1201. * @component: handle to snd_soc_component *
  1202. * @req_volt: micbias voltage to be set
  1203. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1204. *
  1205. * return 0 if adjustment is success or error code in case of failure
  1206. */
  1207. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1208. int req_volt, int micb_num)
  1209. {
  1210. struct wcd937x_priv *wcd937x =
  1211. snd_soc_component_get_drvdata(component);
  1212. int cur_vout_ctl, req_vout_ctl;
  1213. int micb_reg, micb_val, micb_en;
  1214. int ret = 0;
  1215. switch (micb_num) {
  1216. case MIC_BIAS_1:
  1217. micb_reg = WCD937X_ANA_MICB1;
  1218. break;
  1219. case MIC_BIAS_2:
  1220. micb_reg = WCD937X_ANA_MICB2;
  1221. break;
  1222. case MIC_BIAS_3:
  1223. micb_reg = WCD937X_ANA_MICB3;
  1224. break;
  1225. default:
  1226. return -EINVAL;
  1227. }
  1228. mutex_lock(&wcd937x->micb_lock);
  1229. /*
  1230. * If requested micbias voltage is same as current micbias
  1231. * voltage, then just return. Otherwise, adjust voltage as
  1232. * per requested value. If micbias is already enabled, then
  1233. * to avoid slow micbias ramp-up or down enable pull-up
  1234. * momentarily, change the micbias value and then re-enable
  1235. * micbias.
  1236. */
  1237. micb_val = snd_soc_component_read(component, micb_reg);
  1238. micb_en = (micb_val & 0xC0) >> 6;
  1239. cur_vout_ctl = micb_val & 0x3F;
  1240. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1241. if (req_vout_ctl < 0) {
  1242. ret = -EINVAL;
  1243. goto exit;
  1244. }
  1245. if (cur_vout_ctl == req_vout_ctl) {
  1246. ret = 0;
  1247. goto exit;
  1248. }
  1249. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1250. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1251. req_volt, micb_en);
  1252. if (micb_en == 0x1)
  1253. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1254. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1255. if (micb_en == 0x1) {
  1256. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1257. /*
  1258. * Add 2ms delay as per HW requirement after enabling
  1259. * micbias
  1260. */
  1261. usleep_range(2000, 2100);
  1262. }
  1263. exit:
  1264. mutex_unlock(&wcd937x->micb_lock);
  1265. return ret;
  1266. }
  1267. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1268. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1269. struct snd_kcontrol *kcontrol,
  1270. int event)
  1271. {
  1272. struct snd_soc_component *component =
  1273. snd_soc_dapm_to_component(w->dapm);
  1274. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1275. int ret = 0;
  1276. switch (event) {
  1277. case SND_SOC_DAPM_PRE_PMU:
  1278. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1279. /* Enable BCS for Headset mic */
  1280. if (w->shift == 1 && !(snd_soc_component_read(component,
  1281. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1282. wcd937x_tx_connect_port(component, MBHC, true);
  1283. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1284. }
  1285. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1286. } else {
  1287. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1288. }
  1289. break;
  1290. case SND_SOC_DAPM_POST_PMD:
  1291. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1292. wcd937x->tx_swr_dev->dev_num,
  1293. false);
  1294. break;
  1295. };
  1296. return ret;
  1297. }
  1298. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1299. struct snd_kcontrol *kcontrol,
  1300. int event){
  1301. struct snd_soc_component *component =
  1302. snd_soc_dapm_to_component(w->dapm);
  1303. struct wcd937x_priv *wcd937x =
  1304. snd_soc_component_get_drvdata(component);
  1305. int ret = 0;
  1306. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1307. w->name, event);
  1308. switch (event) {
  1309. case SND_SOC_DAPM_PRE_PMU:
  1310. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1311. wcd937x->ana_clk_count++;
  1312. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1313. snd_soc_component_update_bits(component,
  1314. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1315. snd_soc_component_update_bits(component,
  1316. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1317. snd_soc_component_update_bits(component,
  1318. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1319. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1320. wcd937x->tx_swr_dev->dev_num,
  1321. true);
  1322. break;
  1323. case SND_SOC_DAPM_POST_PMD:
  1324. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1325. if (w->shift == 1 &&
  1326. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1327. wcd937x_tx_connect_port(component, MBHC, false);
  1328. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1329. }
  1330. snd_soc_component_update_bits(component,
  1331. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1332. break;
  1333. };
  1334. return ret;
  1335. }
  1336. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1337. struct snd_kcontrol *kcontrol, int event)
  1338. {
  1339. struct snd_soc_component *component =
  1340. snd_soc_dapm_to_component(w->dapm);
  1341. struct wcd937x_priv *wcd937x =
  1342. snd_soc_component_get_drvdata(component);
  1343. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1344. w->name, event);
  1345. switch (event) {
  1346. case SND_SOC_DAPM_PRE_PMU:
  1347. snd_soc_component_update_bits(component,
  1348. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1349. snd_soc_component_update_bits(component,
  1350. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1351. snd_soc_component_update_bits(component,
  1352. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1353. snd_soc_component_update_bits(component,
  1354. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1355. snd_soc_component_update_bits(component,
  1356. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1357. snd_soc_component_update_bits(component,
  1358. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1359. snd_soc_component_update_bits(component,
  1360. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1361. snd_soc_component_update_bits(component,
  1362. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1363. snd_soc_component_update_bits(component,
  1364. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1365. break;
  1366. case SND_SOC_DAPM_POST_PMD:
  1367. snd_soc_component_update_bits(component,
  1368. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1369. snd_soc_component_update_bits(component,
  1370. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1371. snd_soc_component_update_bits(component,
  1372. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1373. snd_soc_component_update_bits(component,
  1374. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1375. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1376. wcd937x->ana_clk_count--;
  1377. if (wcd937x->ana_clk_count <= 0) {
  1378. snd_soc_component_update_bits(component,
  1379. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1380. wcd937x->ana_clk_count = 0;
  1381. }
  1382. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1383. snd_soc_component_update_bits(component,
  1384. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1385. break;
  1386. };
  1387. return 0;
  1388. }
  1389. int wcd937x_micbias_control(struct snd_soc_component *component,
  1390. int micb_num, int req, bool is_dapm)
  1391. {
  1392. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1393. int micb_index = micb_num - 1;
  1394. u16 micb_reg;
  1395. int pre_off_event = 0, post_off_event = 0;
  1396. int post_on_event = 0, post_dapm_off = 0;
  1397. int post_dapm_on = 0;
  1398. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1399. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1400. __func__, micb_index);
  1401. return -EINVAL;
  1402. }
  1403. switch (micb_num) {
  1404. case MIC_BIAS_1:
  1405. micb_reg = WCD937X_ANA_MICB1;
  1406. break;
  1407. case MIC_BIAS_2:
  1408. micb_reg = WCD937X_ANA_MICB2;
  1409. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1410. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1411. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1412. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1413. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1414. break;
  1415. case MIC_BIAS_3:
  1416. micb_reg = WCD937X_ANA_MICB3;
  1417. break;
  1418. default:
  1419. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1420. __func__, micb_num);
  1421. return -EINVAL;
  1422. };
  1423. mutex_lock(&wcd937x->micb_lock);
  1424. switch (req) {
  1425. case MICB_PULLUP_ENABLE:
  1426. wcd937x->pullup_ref[micb_index]++;
  1427. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1428. (wcd937x->micb_ref[micb_index] == 0))
  1429. snd_soc_component_update_bits(component, micb_reg,
  1430. 0xC0, 0x80);
  1431. break;
  1432. case MICB_PULLUP_DISABLE:
  1433. if (wcd937x->pullup_ref[micb_index] > 0)
  1434. wcd937x->pullup_ref[micb_index]--;
  1435. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1436. (wcd937x->micb_ref[micb_index] == 0))
  1437. snd_soc_component_update_bits(component, micb_reg,
  1438. 0xC0, 0x00);
  1439. break;
  1440. case MICB_ENABLE:
  1441. wcd937x->micb_ref[micb_index]++;
  1442. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1443. wcd937x->ana_clk_count++;
  1444. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1445. if (wcd937x->micb_ref[micb_index] == 1) {
  1446. snd_soc_component_update_bits(component,
  1447. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1448. snd_soc_component_update_bits(component,
  1449. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1450. snd_soc_component_update_bits(component,
  1451. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1452. snd_soc_component_update_bits(component,
  1453. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1454. snd_soc_component_update_bits(component,
  1455. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1456. snd_soc_component_update_bits(component,
  1457. micb_reg, 0xC0, 0x40);
  1458. if (post_on_event)
  1459. blocking_notifier_call_chain(
  1460. &wcd937x->mbhc->notifier, post_on_event,
  1461. &wcd937x->mbhc->wcd_mbhc);
  1462. }
  1463. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1464. blocking_notifier_call_chain(
  1465. &wcd937x->mbhc->notifier, post_dapm_on,
  1466. &wcd937x->mbhc->wcd_mbhc);
  1467. break;
  1468. case MICB_DISABLE:
  1469. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1470. wcd937x->ana_clk_count--;
  1471. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1472. if (wcd937x->micb_ref[micb_index] > 0)
  1473. wcd937x->micb_ref[micb_index]--;
  1474. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1475. (wcd937x->pullup_ref[micb_index] > 0))
  1476. snd_soc_component_update_bits(component, micb_reg,
  1477. 0xC0, 0x80);
  1478. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1479. (wcd937x->pullup_ref[micb_index] == 0)) {
  1480. if (pre_off_event && wcd937x->mbhc)
  1481. blocking_notifier_call_chain(
  1482. &wcd937x->mbhc->notifier, pre_off_event,
  1483. &wcd937x->mbhc->wcd_mbhc);
  1484. snd_soc_component_update_bits(component, micb_reg,
  1485. 0xC0, 0x00);
  1486. if (post_off_event && wcd937x->mbhc)
  1487. blocking_notifier_call_chain(
  1488. &wcd937x->mbhc->notifier,
  1489. post_off_event,
  1490. &wcd937x->mbhc->wcd_mbhc);
  1491. }
  1492. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1493. if (wcd937x->ana_clk_count <= 0) {
  1494. snd_soc_component_update_bits(component,
  1495. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1496. 0x10, 0x00);
  1497. wcd937x->ana_clk_count = 0;
  1498. }
  1499. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1500. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1501. blocking_notifier_call_chain(
  1502. &wcd937x->mbhc->notifier, post_dapm_off,
  1503. &wcd937x->mbhc->wcd_mbhc);
  1504. break;
  1505. };
  1506. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1507. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1508. wcd937x->pullup_ref[micb_index]);
  1509. mutex_unlock(&wcd937x->micb_lock);
  1510. return 0;
  1511. }
  1512. EXPORT_SYMBOL(wcd937x_micbias_control);
  1513. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1514. bool bcs_disable)
  1515. {
  1516. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1517. if (wcd937x->update_wcd_event) {
  1518. if (bcs_disable)
  1519. wcd937x->update_wcd_event(wcd937x->handle,
  1520. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1521. else
  1522. wcd937x->update_wcd_event(wcd937x->handle,
  1523. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1524. }
  1525. }
  1526. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1527. {
  1528. int ret = 0;
  1529. uint8_t devnum = 0;
  1530. int num_retry = NUM_ATTEMPTS;
  1531. do {
  1532. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1533. if (ret) {
  1534. dev_err(&swr_dev->dev,
  1535. "%s get devnum %d for dev addr %lx failed\n",
  1536. __func__, devnum, swr_dev->addr);
  1537. /* retry after 1ms */
  1538. usleep_range(1000, 1010);
  1539. }
  1540. } while (ret && --num_retry);
  1541. swr_dev->dev_num = devnum;
  1542. return 0;
  1543. }
  1544. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1545. struct wcd_mbhc_config *mbhc_cfg)
  1546. {
  1547. if (mbhc_cfg->enable_usbc_analog) {
  1548. if (!(snd_soc_component_read(component, WCD937X_ANA_MBHC_MECH)
  1549. & 0x20))
  1550. return true;
  1551. }
  1552. return false;
  1553. }
  1554. static int wcd937x_event_notify(struct notifier_block *block,
  1555. unsigned long val,
  1556. void *data)
  1557. {
  1558. u16 event = (val & 0xffff);
  1559. u16 amic = (val >> 0x10);
  1560. u16 mask = 0x40, reg = 0x0;
  1561. int ret = 0;
  1562. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1563. struct snd_soc_component *component = wcd937x->component;
  1564. struct wcd_mbhc *mbhc;
  1565. switch (event) {
  1566. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1567. if (amic == 0x1 || amic == 0x2)
  1568. reg = WCD937X_ANA_TX_CH2;
  1569. else if (amic == 0x3)
  1570. reg = WCD937X_ANA_TX_CH3_HPF;
  1571. else
  1572. return 0;
  1573. if (amic == 0x2)
  1574. mask = 0x20;
  1575. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1576. break;
  1577. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1578. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1579. 0xC0, 0x00);
  1580. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1581. 0x80, 0x00);
  1582. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1583. 0x80, 0x00);
  1584. break;
  1585. case BOLERO_SLV_EVT_SSR_DOWN:
  1586. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1587. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1588. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1589. mbhc->mbhc_cfg);
  1590. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1591. wcd937x_reset_low(wcd937x->dev);
  1592. break;
  1593. case BOLERO_SLV_EVT_SSR_UP:
  1594. wcd937x_reset(wcd937x->dev);
  1595. /* allow reset to take effect */
  1596. usleep_range(10000, 10010);
  1597. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1598. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1599. wcd937x_init_reg(component);
  1600. regcache_mark_dirty(wcd937x->regmap);
  1601. regcache_sync(wcd937x->regmap);
  1602. /* Initialize MBHC module */
  1603. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1604. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1605. if (ret) {
  1606. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1607. __func__);
  1608. } else {
  1609. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1610. if (wcd937x->usbc_hs_status)
  1611. mdelay(500);
  1612. }
  1613. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1614. break;
  1615. default:
  1616. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1617. event);
  1618. break;
  1619. }
  1620. return 0;
  1621. }
  1622. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1623. int event)
  1624. {
  1625. struct snd_soc_component *component =
  1626. snd_soc_dapm_to_component(w->dapm);
  1627. int micb_num;
  1628. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1629. __func__, w->name, event);
  1630. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1631. micb_num = MIC_BIAS_1;
  1632. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1633. micb_num = MIC_BIAS_2;
  1634. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1635. micb_num = MIC_BIAS_3;
  1636. else
  1637. return -EINVAL;
  1638. switch (event) {
  1639. case SND_SOC_DAPM_PRE_PMU:
  1640. wcd937x_micbias_control(component, micb_num,
  1641. MICB_ENABLE, true);
  1642. break;
  1643. case SND_SOC_DAPM_POST_PMU:
  1644. usleep_range(1000, 1100);
  1645. break;
  1646. case SND_SOC_DAPM_POST_PMD:
  1647. wcd937x_micbias_control(component, micb_num,
  1648. MICB_DISABLE, true);
  1649. break;
  1650. };
  1651. return 0;
  1652. }
  1653. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1654. struct snd_kcontrol *kcontrol,
  1655. int event)
  1656. {
  1657. return __wcd937x_codec_enable_micbias(w, event);
  1658. }
  1659. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1660. int event)
  1661. {
  1662. struct snd_soc_component *component =
  1663. snd_soc_dapm_to_component(w->dapm);
  1664. int micb_num;
  1665. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1666. __func__, w->name, event);
  1667. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1668. micb_num = MIC_BIAS_1;
  1669. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1670. micb_num = MIC_BIAS_2;
  1671. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1672. micb_num = MIC_BIAS_3;
  1673. else
  1674. return -EINVAL;
  1675. switch (event) {
  1676. case SND_SOC_DAPM_PRE_PMU:
  1677. wcd937x_micbias_control(component, micb_num,
  1678. MICB_PULLUP_ENABLE, true);
  1679. break;
  1680. case SND_SOC_DAPM_POST_PMU:
  1681. /* 1 msec delay as per HW requirement */
  1682. usleep_range(1000, 1100);
  1683. break;
  1684. case SND_SOC_DAPM_POST_PMD:
  1685. wcd937x_micbias_control(component, micb_num,
  1686. MICB_PULLUP_DISABLE, true);
  1687. break;
  1688. };
  1689. return 0;
  1690. }
  1691. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1692. struct snd_kcontrol *kcontrol,
  1693. int event)
  1694. {
  1695. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1696. }
  1697. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1698. struct snd_ctl_elem_value *ucontrol)
  1699. {
  1700. struct snd_soc_component *component =
  1701. snd_soc_kcontrol_component(kcontrol);
  1702. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1703. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1704. return 0;
  1705. }
  1706. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1707. struct snd_ctl_elem_value *ucontrol)
  1708. {
  1709. struct snd_soc_component *component =
  1710. snd_soc_kcontrol_component(kcontrol);
  1711. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1712. u32 mode_val;
  1713. mode_val = ucontrol->value.enumerated.item[0];
  1714. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1715. if (mode_val == 0) {
  1716. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1717. __func__);
  1718. mode_val = 3; /* enum will be updated later */
  1719. }
  1720. wcd937x->hph_mode = mode_val;
  1721. return 0;
  1722. }
  1723. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1724. struct snd_ctl_elem_value *ucontrol)
  1725. {
  1726. struct snd_soc_component *component =
  1727. snd_soc_kcontrol_component(kcontrol);
  1728. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1729. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1730. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1731. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1732. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1733. return 0;
  1734. }
  1735. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1736. struct snd_ctl_elem_value *ucontrol)
  1737. {
  1738. struct snd_soc_component *component =
  1739. snd_soc_kcontrol_component(kcontrol);
  1740. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1741. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1742. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1743. __func__, pwr_level);
  1744. if (strnstr(kcontrol->id.name, "CH1",
  1745. sizeof(kcontrol->id.name))) {
  1746. snd_soc_component_update_bits(component,
  1747. WCD937X_ANA_TX_CH1, 0x60,
  1748. pwr_level << 0x5);
  1749. wcd937x->tx_ch_pwr[0] = pwr_level;
  1750. } else if (strnstr(kcontrol->id.name, "CH3",
  1751. sizeof(kcontrol->id.name))) {
  1752. snd_soc_component_update_bits(component,
  1753. WCD937X_ANA_TX_CH3, 0x60,
  1754. pwr_level << 0x5);
  1755. wcd937x->tx_ch_pwr[1] = pwr_level;
  1756. }
  1757. return 0;
  1758. }
  1759. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1760. struct snd_ctl_elem_value *ucontrol)
  1761. {
  1762. u8 ear_pa_gain = 0;
  1763. struct snd_soc_component *component =
  1764. snd_soc_kcontrol_component(kcontrol);
  1765. ear_pa_gain = snd_soc_component_read(component,
  1766. WCD937X_ANA_EAR_COMPANDER_CTL);
  1767. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1768. ucontrol->value.integer.value[0] = ear_pa_gain;
  1769. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1770. ear_pa_gain);
  1771. return 0;
  1772. }
  1773. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1774. struct snd_ctl_elem_value *ucontrol)
  1775. {
  1776. u8 ear_pa_gain = 0;
  1777. struct snd_soc_component *component =
  1778. snd_soc_kcontrol_component(kcontrol);
  1779. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1780. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1781. __func__, ucontrol->value.integer.value[0]);
  1782. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1783. if (!wcd937x->comp1_enable) {
  1784. snd_soc_component_update_bits(component,
  1785. WCD937X_ANA_EAR_COMPANDER_CTL,
  1786. 0x7C, ear_pa_gain);
  1787. }
  1788. return 0;
  1789. }
  1790. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1791. struct snd_ctl_elem_value *ucontrol)
  1792. {
  1793. struct snd_soc_component *component =
  1794. snd_soc_kcontrol_component(kcontrol);
  1795. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1796. bool hphr;
  1797. struct soc_multi_mixer_control *mc;
  1798. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1799. hphr = mc->shift;
  1800. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1801. wcd937x->comp1_enable;
  1802. return 0;
  1803. }
  1804. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1805. struct snd_ctl_elem_value *ucontrol)
  1806. {
  1807. struct snd_soc_component *component =
  1808. snd_soc_kcontrol_component(kcontrol);
  1809. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1810. int value = ucontrol->value.integer.value[0];
  1811. bool hphr;
  1812. struct soc_multi_mixer_control *mc;
  1813. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1814. hphr = mc->shift;
  1815. if (hphr)
  1816. wcd937x->comp2_enable = value;
  1817. else
  1818. wcd937x->comp1_enable = value;
  1819. return 0;
  1820. }
  1821. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1822. struct snd_kcontrol *kcontrol,
  1823. int event)
  1824. {
  1825. struct snd_soc_component *component =
  1826. snd_soc_dapm_to_component(w->dapm);
  1827. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1828. struct wcd937x_pdata *pdata = NULL;
  1829. int ret = 0;
  1830. pdata = dev_get_platdata(wcd937x->dev);
  1831. if (!pdata) {
  1832. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1833. return -EINVAL;
  1834. }
  1835. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1836. w->name, event);
  1837. switch (event) {
  1838. case SND_SOC_DAPM_PRE_PMU:
  1839. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1840. dev_dbg(component->dev,
  1841. "%s: buck already in enabled state\n",
  1842. __func__);
  1843. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1844. return 0;
  1845. }
  1846. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1847. wcd937x->supplies,
  1848. pdata->regulator,
  1849. pdata->num_supplies,
  1850. "cdc-vdd-buck");
  1851. if (ret == -EINVAL) {
  1852. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1853. __func__);
  1854. return ret;
  1855. }
  1856. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1857. /*
  1858. * 200us sleep is required after LDO15 is enabled as per
  1859. * HW requirement
  1860. */
  1861. usleep_range(200, 250);
  1862. break;
  1863. case SND_SOC_DAPM_POST_PMD:
  1864. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1865. break;
  1866. }
  1867. return 0;
  1868. }
  1869. static const char * const rx_hph_mode_mux_text[] = {
  1870. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1871. "CLS_H_ULP", "CLS_AB_HIFI",
  1872. };
  1873. const char * const tx_master_ch_text[] = {
  1874. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1875. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1876. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1877. "SWRM_PCM_IN",
  1878. };
  1879. const struct soc_enum tx_master_ch_enum =
  1880. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1881. tx_master_ch_text);
  1882. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1883. {
  1884. u8 ch_type = 0;
  1885. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1886. ch_type = ADC1;
  1887. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1888. ch_type = ADC2;
  1889. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1890. ch_type = ADC3;
  1891. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1892. ch_type = DMIC0;
  1893. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1894. ch_type = DMIC1;
  1895. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1896. ch_type = MBHC;
  1897. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1898. ch_type = DMIC2;
  1899. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1900. ch_type = DMIC3;
  1901. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1902. ch_type = DMIC4;
  1903. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1904. ch_type = DMIC5;
  1905. else
  1906. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1907. if (ch_type)
  1908. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1909. else
  1910. *ch_idx = -EINVAL;
  1911. }
  1912. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1913. struct snd_ctl_elem_value *ucontrol)
  1914. {
  1915. struct snd_soc_component *component =
  1916. snd_soc_kcontrol_component(kcontrol);
  1917. struct wcd937x_priv *wcd937x = NULL;
  1918. int slave_ch_idx = -EINVAL;
  1919. if (component == NULL)
  1920. return -EINVAL;
  1921. wcd937x = snd_soc_component_get_drvdata(component);
  1922. if (wcd937x == NULL)
  1923. return -EINVAL;
  1924. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1925. if (slave_ch_idx < 0 || slave_ch_idx >= WCD937X_MAX_SLAVE_CH_TYPES)
  1926. return -EINVAL;
  1927. ucontrol->value.integer.value[0] =
  1928. wcd937x_slave_get_master_ch_val(
  1929. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1930. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1931. __func__, ucontrol->value.integer.value[0]);
  1932. return 0;
  1933. }
  1934. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  1935. struct snd_ctl_elem_value *ucontrol)
  1936. {
  1937. struct snd_soc_component *component =
  1938. snd_soc_kcontrol_component(kcontrol);
  1939. struct wcd937x_priv *wcd937x;
  1940. int slave_ch_idx = -EINVAL, idx = 0;
  1941. if (component == NULL)
  1942. return -EINVAL;
  1943. wcd937x = snd_soc_component_get_drvdata(component);
  1944. if (wcd937x == NULL)
  1945. return -EINVAL;
  1946. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1947. if (slave_ch_idx < 0 || slave_ch_idx >= WCD937X_MAX_SLAVE_CH_TYPES)
  1948. return -EINVAL;
  1949. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  1950. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  1951. __func__, ucontrol->value.enumerated.item[0]);
  1952. idx = ucontrol->value.enumerated.item[0];
  1953. if (idx < 0 || idx >= ARRAY_SIZE(wcd937x_swr_master_ch_map))
  1954. return -EINVAL;
  1955. wcd937x->tx_master_ch_map[slave_ch_idx] =
  1956. wcd937x_slave_get_master_ch(idx);
  1957. return 0;
  1958. }
  1959. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  1960. "L0", "L1", "L2", "L3",
  1961. };
  1962. static const char * const wcd937x_ear_pa_gain_text[] = {
  1963. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1964. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1965. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1966. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1967. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1968. };
  1969. static const struct soc_enum rx_hph_mode_mux_enum =
  1970. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1971. rx_hph_mode_mux_text);
  1972. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1973. wcd937x_ear_pa_gain_text);
  1974. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  1975. wcd937x_tx_ch_pwr_level_text);
  1976. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1977. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1978. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1979. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1980. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1981. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1982. wcd937x_get_compander, wcd937x_set_compander),
  1983. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1984. wcd937x_get_compander, wcd937x_set_compander),
  1985. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1986. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1987. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1988. analog_gain),
  1989. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1990. analog_gain),
  1991. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1992. analog_gain),
  1993. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  1994. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1995. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  1996. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1997. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  1998. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1999. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2000. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2001. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2002. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2003. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2004. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2005. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2006. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2007. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2008. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2009. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2010. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2011. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2012. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2013. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  2014. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2015. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  2016. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2017. };
  2018. static const struct snd_kcontrol_new adc1_switch[] = {
  2019. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2020. };
  2021. static const struct snd_kcontrol_new adc2_switch[] = {
  2022. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2023. };
  2024. static const struct snd_kcontrol_new adc3_switch[] = {
  2025. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2026. };
  2027. static const struct snd_kcontrol_new dmic1_switch[] = {
  2028. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2029. };
  2030. static const struct snd_kcontrol_new dmic2_switch[] = {
  2031. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2032. };
  2033. static const struct snd_kcontrol_new dmic3_switch[] = {
  2034. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2035. };
  2036. static const struct snd_kcontrol_new dmic4_switch[] = {
  2037. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2038. };
  2039. static const struct snd_kcontrol_new dmic5_switch[] = {
  2040. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2041. };
  2042. static const struct snd_kcontrol_new dmic6_switch[] = {
  2043. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2044. };
  2045. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2046. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2047. };
  2048. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2049. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2050. };
  2051. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2052. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2053. };
  2054. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2055. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2056. };
  2057. static const char * const adc2_mux_text[] = {
  2058. "INP2", "INP3"
  2059. };
  2060. static const char * const rdac3_mux_text[] = {
  2061. "RX1", "RX3"
  2062. };
  2063. static const struct soc_enum adc2_enum =
  2064. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  2065. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2066. static const struct soc_enum rdac3_enum =
  2067. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2068. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2069. static const struct snd_kcontrol_new tx_adc2_mux =
  2070. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2071. static const struct snd_kcontrol_new rx_rdac3_mux =
  2072. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2073. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  2074. /*input widgets*/
  2075. SND_SOC_DAPM_INPUT("AMIC1"),
  2076. SND_SOC_DAPM_INPUT("AMIC2"),
  2077. SND_SOC_DAPM_INPUT("AMIC3"),
  2078. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2079. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2080. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2081. /*
  2082. * These dummy widgets are null connected to WCD937x dapm input and
  2083. * output widgets which are not actual path endpoints. This ensures
  2084. * dapm doesnt set these dapm input and output widgets as endpoints.
  2085. */
  2086. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2087. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2088. /*tx widgets*/
  2089. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2090. wcd937x_codec_enable_adc,
  2091. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2092. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2093. wcd937x_codec_enable_adc,
  2094. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2095. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2096. NULL, 0, wcd937x_enable_req,
  2097. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2098. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  2099. NULL, 0, wcd937x_enable_req,
  2100. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2101. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2102. &tx_adc2_mux),
  2103. /*tx mixers*/
  2104. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2105. adc1_switch, ARRAY_SIZE(adc1_switch),
  2106. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2107. SND_SOC_DAPM_POST_PMD),
  2108. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
  2109. adc2_switch, ARRAY_SIZE(adc2_switch),
  2110. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2111. SND_SOC_DAPM_POST_PMD),
  2112. /* micbias widgets*/
  2113. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2114. wcd937x_codec_enable_micbias,
  2115. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2116. SND_SOC_DAPM_POST_PMD),
  2117. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2118. wcd937x_codec_enable_micbias,
  2119. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2120. SND_SOC_DAPM_POST_PMD),
  2121. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2122. wcd937x_codec_enable_micbias,
  2123. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2124. SND_SOC_DAPM_POST_PMD),
  2125. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2126. wcd937x_codec_enable_vdd_buck,
  2127. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2128. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2129. wcd937x_enable_clsh,
  2130. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2131. /*rx widgets*/
  2132. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2133. wcd937x_codec_enable_ear_pa,
  2134. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2135. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2136. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2137. wcd937x_codec_enable_aux_pa,
  2138. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2139. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2140. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2141. wcd937x_codec_enable_hphl_pa,
  2142. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2143. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2144. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2145. wcd937x_codec_enable_hphr_pa,
  2146. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2147. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2148. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2149. wcd937x_codec_hphl_dac_event,
  2150. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2151. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2152. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2153. wcd937x_codec_hphr_dac_event,
  2154. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2155. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2156. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2157. wcd937x_codec_ear_dac_event,
  2158. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2159. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2160. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2161. wcd937x_codec_aux_dac_event,
  2162. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2163. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2164. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2165. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2166. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2167. SND_SOC_DAPM_POST_PMD),
  2168. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2169. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2170. SND_SOC_DAPM_POST_PMD),
  2171. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2172. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2173. SND_SOC_DAPM_POST_PMD),
  2174. /* rx mixer widgets*/
  2175. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2176. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2177. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2178. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2179. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2180. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2181. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2182. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2183. /*output widgets tx*/
  2184. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2185. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2186. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2187. /*output widgets rx*/
  2188. SND_SOC_DAPM_OUTPUT("EAR"),
  2189. SND_SOC_DAPM_OUTPUT("AUX"),
  2190. SND_SOC_DAPM_OUTPUT("HPHL"),
  2191. SND_SOC_DAPM_OUTPUT("HPHR"),
  2192. /* micbias pull up widgets*/
  2193. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2194. wcd937x_codec_enable_micbias_pullup,
  2195. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2196. SND_SOC_DAPM_POST_PMD),
  2197. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2198. wcd937x_codec_enable_micbias_pullup,
  2199. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2200. SND_SOC_DAPM_POST_PMD),
  2201. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2202. wcd937x_codec_enable_micbias_pullup,
  2203. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2204. SND_SOC_DAPM_POST_PMD),
  2205. };
  2206. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2207. /*input widgets*/
  2208. SND_SOC_DAPM_INPUT("AMIC4"),
  2209. /*tx widgets*/
  2210. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2211. wcd937x_codec_enable_adc,
  2212. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2213. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2214. NULL, 0, wcd937x_enable_req,
  2215. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2216. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2217. wcd937x_codec_enable_dmic,
  2218. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2219. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2220. wcd937x_codec_enable_dmic,
  2221. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2222. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2223. wcd937x_codec_enable_dmic,
  2224. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2225. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2226. wcd937x_codec_enable_dmic,
  2227. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2228. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2229. wcd937x_codec_enable_dmic,
  2230. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2231. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2232. wcd937x_codec_enable_dmic,
  2233. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2234. /*tx mixer widgets*/
  2235. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2236. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2237. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2238. SND_SOC_DAPM_POST_PMD),
  2239. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
  2240. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2241. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2242. SND_SOC_DAPM_POST_PMD),
  2243. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
  2244. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2245. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2246. SND_SOC_DAPM_POST_PMD),
  2247. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
  2248. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2249. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2250. SND_SOC_DAPM_POST_PMD),
  2251. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
  2252. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2253. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2254. SND_SOC_DAPM_POST_PMD),
  2255. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
  2256. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2257. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2258. SND_SOC_DAPM_POST_PMD),
  2259. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
  2260. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2261. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2262. /*output widgets*/
  2263. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2264. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2265. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2266. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2267. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2268. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2269. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2270. };
  2271. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2272. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2273. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2274. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2275. {"ADC1 REQ", NULL, "ADC1"},
  2276. {"ADC1", NULL, "AMIC1"},
  2277. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2278. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2279. {"ADC2 REQ", NULL, "ADC2"},
  2280. {"ADC2", NULL, "ADC2 MUX"},
  2281. {"ADC2 MUX", "INP3", "AMIC3"},
  2282. {"ADC2 MUX", "INP2", "AMIC2"},
  2283. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  2284. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2285. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2286. {"RX1", NULL, "IN1_HPHL"},
  2287. {"RDAC1", NULL, "RX1"},
  2288. {"HPHL_RDAC", "Switch", "RDAC1"},
  2289. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2290. {"HPHL", NULL, "HPHL PGA"},
  2291. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  2292. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2293. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2294. {"RX2", NULL, "IN2_HPHR"},
  2295. {"RDAC2", NULL, "RX2"},
  2296. {"HPHR_RDAC", "Switch", "RDAC2"},
  2297. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2298. {"HPHR", NULL, "HPHR PGA"},
  2299. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  2300. {"IN3_AUX", NULL, "VDD_BUCK"},
  2301. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2302. {"RX3", NULL, "IN3_AUX"},
  2303. {"RDAC4", NULL, "RX3"},
  2304. {"AUX_RDAC", "Switch", "RDAC4"},
  2305. {"AUX PGA", NULL, "AUX_RDAC"},
  2306. {"AUX", NULL, "AUX PGA"},
  2307. {"RDAC3_MUX", "RX3", "RX3"},
  2308. {"RDAC3_MUX", "RX1", "RX1"},
  2309. {"RDAC3", NULL, "RDAC3_MUX"},
  2310. {"EAR_RDAC", "Switch", "RDAC3"},
  2311. {"EAR PGA", NULL, "EAR_RDAC"},
  2312. {"EAR", NULL, "EAR PGA"},
  2313. };
  2314. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2315. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2316. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2317. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2318. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2319. {"ADC3 REQ", NULL, "ADC3"},
  2320. {"ADC3", NULL, "AMIC4"},
  2321. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2322. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2323. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2324. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2325. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2326. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2327. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2328. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2329. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2330. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2331. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2332. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2333. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2334. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2335. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2336. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2337. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2338. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2339. };
  2340. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2341. void *file_private_data,
  2342. struct file *file,
  2343. char __user *buf, size_t count,
  2344. loff_t pos)
  2345. {
  2346. struct wcd937x_priv *priv;
  2347. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2348. int len = 0;
  2349. priv = (struct wcd937x_priv *) entry->private_data;
  2350. if (!priv) {
  2351. pr_err("%s: wcd937x priv is null\n", __func__);
  2352. return -EINVAL;
  2353. }
  2354. switch (priv->version) {
  2355. case WCD937X_VERSION_1_0:
  2356. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2357. break;
  2358. default:
  2359. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2360. }
  2361. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2362. }
  2363. static struct snd_info_entry_ops wcd937x_info_ops = {
  2364. .read = wcd937x_version_read,
  2365. };
  2366. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2367. void *file_private_data,
  2368. struct file *file,
  2369. char __user *buf, size_t count,
  2370. loff_t pos)
  2371. {
  2372. struct wcd937x_priv *priv;
  2373. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2374. int len = 0;
  2375. priv = (struct wcd937x_priv *) entry->private_data;
  2376. if (!priv) {
  2377. pr_err("%s: wcd937x priv is null\n", __func__);
  2378. return -EINVAL;
  2379. }
  2380. switch (priv->variant) {
  2381. case WCD9370_VARIANT:
  2382. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2383. break;
  2384. case WCD9375_VARIANT:
  2385. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2386. break;
  2387. default:
  2388. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2389. }
  2390. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2391. }
  2392. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2393. .read = wcd937x_variant_read,
  2394. };
  2395. /*
  2396. * wcd937x_info_create_codec_entry - creates wcd937x module
  2397. * @codec_root: The parent directory
  2398. * @component: component instance
  2399. *
  2400. * Creates wcd937x module, variant and version entry under the given
  2401. * parent directory.
  2402. *
  2403. * Return: 0 on success or negative error code on failure.
  2404. */
  2405. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2406. struct snd_soc_component *component)
  2407. {
  2408. struct snd_info_entry *version_entry;
  2409. struct snd_info_entry *variant_entry;
  2410. struct wcd937x_priv *priv;
  2411. struct snd_soc_card *card;
  2412. if (!codec_root || !component)
  2413. return -EINVAL;
  2414. priv = snd_soc_component_get_drvdata(component);
  2415. if (priv->entry) {
  2416. dev_dbg(priv->dev,
  2417. "%s:wcd937x module already created\n", __func__);
  2418. return 0;
  2419. }
  2420. card = component->card;
  2421. priv->entry = snd_info_create_module_entry(codec_root->module,
  2422. "wcd937x", codec_root);
  2423. if (!priv->entry) {
  2424. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2425. __func__);
  2426. return -ENOMEM;
  2427. }
  2428. priv->entry->mode = S_IFDIR | 0555;
  2429. if (snd_info_register(priv->entry) < 0) {
  2430. snd_info_free_entry(priv->entry);
  2431. return -ENOMEM;
  2432. }
  2433. version_entry = snd_info_create_card_entry(card->snd_card,
  2434. "version",
  2435. priv->entry);
  2436. if (!version_entry) {
  2437. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2438. __func__);
  2439. snd_info_free_entry(priv->entry);
  2440. return -ENOMEM;
  2441. }
  2442. version_entry->private_data = priv;
  2443. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2444. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2445. version_entry->c.ops = &wcd937x_info_ops;
  2446. if (snd_info_register(version_entry) < 0) {
  2447. snd_info_free_entry(version_entry);
  2448. snd_info_free_entry(priv->entry);
  2449. return -ENOMEM;
  2450. }
  2451. priv->version_entry = version_entry;
  2452. variant_entry = snd_info_create_card_entry(card->snd_card,
  2453. "variant",
  2454. priv->entry);
  2455. if (!variant_entry) {
  2456. dev_dbg(component->dev,
  2457. "%s: failed to create wcd937x variant entry\n",
  2458. __func__);
  2459. snd_info_free_entry(version_entry);
  2460. snd_info_free_entry(priv->entry);
  2461. return -ENOMEM;
  2462. }
  2463. variant_entry->private_data = priv;
  2464. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2465. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2466. variant_entry->c.ops = &wcd937x_variant_ops;
  2467. if (snd_info_register(variant_entry) < 0) {
  2468. snd_info_free_entry(variant_entry);
  2469. snd_info_free_entry(version_entry);
  2470. snd_info_free_entry(priv->entry);
  2471. return -ENOMEM;
  2472. }
  2473. priv->variant_entry = variant_entry;
  2474. return 0;
  2475. }
  2476. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2477. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2478. struct wcd937x_pdata *pdata)
  2479. {
  2480. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2481. int rc = 0;
  2482. if (!pdata) {
  2483. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2484. return -ENODEV;
  2485. }
  2486. /* set micbias voltage */
  2487. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2488. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2489. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2490. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2491. rc = -EINVAL;
  2492. goto done;
  2493. }
  2494. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2495. vout_ctl_1);
  2496. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2497. vout_ctl_2);
  2498. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2499. vout_ctl_3);
  2500. done:
  2501. return rc;
  2502. }
  2503. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2504. {
  2505. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2506. struct snd_soc_dapm_context *dapm =
  2507. snd_soc_component_get_dapm(component);
  2508. int variant;
  2509. int ret = -EINVAL;
  2510. dev_info(component->dev, "%s()\n", __func__);
  2511. wcd937x = snd_soc_component_get_drvdata(component);
  2512. if (!wcd937x)
  2513. return -EINVAL;
  2514. wcd937x->component = component;
  2515. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2516. variant = (snd_soc_component_read(
  2517. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2518. wcd937x->variant = variant;
  2519. wcd937x->fw_data = devm_kzalloc(component->dev,
  2520. sizeof(*(wcd937x->fw_data)),
  2521. GFP_KERNEL);
  2522. if (!wcd937x->fw_data) {
  2523. dev_err(component->dev, "Failed to allocate fw_data\n");
  2524. ret = -ENOMEM;
  2525. goto err;
  2526. }
  2527. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2528. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2529. WCD9XXX_CODEC_HWDEP_NODE, component);
  2530. if (ret < 0) {
  2531. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2532. goto err_hwdep;
  2533. }
  2534. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2535. if (ret) {
  2536. pr_err("%s: mbhc initialization failed\n", __func__);
  2537. goto err_hwdep;
  2538. }
  2539. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2540. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2541. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2542. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2543. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2544. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2545. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2546. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2547. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2548. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2549. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2550. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2551. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2552. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  2553. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  2554. snd_soc_dapm_sync(dapm);
  2555. wcd_cls_h_init(&wcd937x->clsh_info);
  2556. wcd937x_init_reg(component);
  2557. if (wcd937x->variant == WCD9375_VARIANT) {
  2558. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2559. ARRAY_SIZE(wcd9375_dapm_widgets));
  2560. if (ret < 0) {
  2561. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2562. __func__);
  2563. goto err_hwdep;
  2564. }
  2565. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2566. ARRAY_SIZE(wcd9375_audio_map));
  2567. if (ret < 0) {
  2568. dev_err(component->dev, "%s: Failed to add routes\n",
  2569. __func__);
  2570. goto err_hwdep;
  2571. }
  2572. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2573. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2574. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2575. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2576. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2577. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2578. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2579. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2580. snd_soc_dapm_sync(dapm);
  2581. }
  2582. wcd937x->version = WCD937X_VERSION_1_0;
  2583. /* Register event notifier */
  2584. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2585. if (wcd937x->register_notifier) {
  2586. ret = wcd937x->register_notifier(wcd937x->handle,
  2587. &wcd937x->nblock,
  2588. true);
  2589. if (ret) {
  2590. dev_err(component->dev,
  2591. "%s: Failed to register notifier %d\n",
  2592. __func__, ret);
  2593. return ret;
  2594. }
  2595. }
  2596. return ret;
  2597. err_hwdep:
  2598. wcd937x->fw_data = NULL;
  2599. err:
  2600. return ret;
  2601. }
  2602. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2603. {
  2604. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2605. if (!wcd937x)
  2606. return;
  2607. if (wcd937x->register_notifier)
  2608. wcd937x->register_notifier(wcd937x->handle,
  2609. &wcd937x->nblock,
  2610. false);
  2611. return;
  2612. }
  2613. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2614. .name = WCD937X_DRV_NAME,
  2615. .probe = wcd937x_soc_codec_probe,
  2616. .remove = wcd937x_soc_codec_remove,
  2617. .controls = wcd937x_snd_controls,
  2618. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2619. .dapm_widgets = wcd937x_dapm_widgets,
  2620. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2621. .dapm_routes = wcd937x_audio_map,
  2622. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2623. };
  2624. #ifdef CONFIG_PM_SLEEP
  2625. static int wcd937x_suspend(struct device *dev)
  2626. {
  2627. struct wcd937x_priv *wcd937x = NULL;
  2628. int ret = 0;
  2629. struct wcd937x_pdata *pdata = NULL;
  2630. if (!dev)
  2631. return -ENODEV;
  2632. wcd937x = dev_get_drvdata(dev);
  2633. if (!wcd937x)
  2634. return -EINVAL;
  2635. pdata = dev_get_platdata(wcd937x->dev);
  2636. if (!pdata) {
  2637. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2638. return -EINVAL;
  2639. }
  2640. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2641. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2642. wcd937x->supplies,
  2643. pdata->regulator,
  2644. pdata->num_supplies,
  2645. "cdc-vdd-buck");
  2646. if (ret == -EINVAL) {
  2647. dev_err(dev, "%s: vdd buck is not disabled\n",
  2648. __func__);
  2649. return 0;
  2650. }
  2651. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2652. }
  2653. return 0;
  2654. }
  2655. static int wcd937x_resume(struct device *dev)
  2656. {
  2657. return 0;
  2658. }
  2659. #endif
  2660. static int wcd937x_reset(struct device *dev)
  2661. {
  2662. struct wcd937x_priv *wcd937x = NULL;
  2663. int rc = 0;
  2664. int value = 0;
  2665. if (!dev)
  2666. return -ENODEV;
  2667. wcd937x = dev_get_drvdata(dev);
  2668. if (!wcd937x)
  2669. return -EINVAL;
  2670. if (!wcd937x->rst_np) {
  2671. dev_err(dev, "%s: reset gpio device node not specified\n",
  2672. __func__);
  2673. return -EINVAL;
  2674. }
  2675. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2676. if (value > 0)
  2677. return 0;
  2678. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2679. if (rc) {
  2680. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2681. __func__);
  2682. return rc;
  2683. }
  2684. /* 20ms sleep required after pulling the reset gpio to LOW */
  2685. usleep_range(20, 30);
  2686. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2687. if (rc) {
  2688. dev_err(dev, "%s: wcd active state request fail!\n",
  2689. __func__);
  2690. return rc;
  2691. }
  2692. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2693. usleep_range(20, 30);
  2694. return rc;
  2695. }
  2696. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2697. u32 *val)
  2698. {
  2699. int rc = 0;
  2700. rc = of_property_read_u32(dev->of_node, name, val);
  2701. if (rc)
  2702. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2703. __func__, name, dev->of_node->full_name);
  2704. return rc;
  2705. }
  2706. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2707. struct wcd937x_micbias_setting *mb)
  2708. {
  2709. u32 prop_val = 0;
  2710. int rc = 0;
  2711. /* MB1 */
  2712. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2713. NULL)) {
  2714. rc = wcd937x_read_of_property_u32(dev,
  2715. "qcom,cdc-micbias1-mv",
  2716. &prop_val);
  2717. if (!rc)
  2718. mb->micb1_mv = prop_val;
  2719. } else {
  2720. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2721. __func__);
  2722. }
  2723. /* MB2 */
  2724. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2725. NULL)) {
  2726. rc = wcd937x_read_of_property_u32(dev,
  2727. "qcom,cdc-micbias2-mv",
  2728. &prop_val);
  2729. if (!rc)
  2730. mb->micb2_mv = prop_val;
  2731. } else {
  2732. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2733. __func__);
  2734. }
  2735. /* MB3 */
  2736. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2737. NULL)) {
  2738. rc = wcd937x_read_of_property_u32(dev,
  2739. "qcom,cdc-micbias3-mv",
  2740. &prop_val);
  2741. if (!rc)
  2742. mb->micb3_mv = prop_val;
  2743. } else {
  2744. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2745. __func__);
  2746. }
  2747. }
  2748. static int wcd937x_reset_low(struct device *dev)
  2749. {
  2750. struct wcd937x_priv *wcd937x = NULL;
  2751. int rc = 0;
  2752. if (!dev)
  2753. return -ENODEV;
  2754. wcd937x = dev_get_drvdata(dev);
  2755. if (!wcd937x)
  2756. return -EINVAL;
  2757. if (!wcd937x->rst_np) {
  2758. dev_err(dev, "%s: reset gpio device node not specified\n",
  2759. __func__);
  2760. return -EINVAL;
  2761. }
  2762. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2763. if (rc) {
  2764. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2765. __func__);
  2766. return rc;
  2767. }
  2768. /* 20ms sleep required after pulling the reset gpio to LOW */
  2769. usleep_range(20, 30);
  2770. return rc;
  2771. }
  2772. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2773. {
  2774. struct wcd937x_pdata *pdata = NULL;
  2775. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2776. GFP_KERNEL);
  2777. if (!pdata)
  2778. return NULL;
  2779. pdata->rst_np = of_parse_phandle(dev->of_node,
  2780. "qcom,wcd-rst-gpio-node", 0);
  2781. if (!pdata->rst_np) {
  2782. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2783. __func__, "qcom,wcd-rst-gpio-node",
  2784. dev->of_node->full_name);
  2785. return NULL;
  2786. }
  2787. /* Parse power supplies */
  2788. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2789. &pdata->num_supplies);
  2790. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2791. dev_err(dev, "%s: no power supplies defined for codec\n",
  2792. __func__);
  2793. return NULL;
  2794. }
  2795. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2796. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2797. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2798. return pdata;
  2799. }
  2800. static int wcd937x_wakeup(void *handle, bool enable)
  2801. {
  2802. struct wcd937x_priv *priv;
  2803. if (!handle) {
  2804. pr_err("%s: NULL handle\n", __func__);
  2805. return -EINVAL;
  2806. }
  2807. priv = (struct wcd937x_priv *)handle;
  2808. if (!priv->tx_swr_dev) {
  2809. pr_err("%s: tx swr dev is NULL\n", __func__);
  2810. return -EINVAL;
  2811. }
  2812. if (enable)
  2813. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2814. else
  2815. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2816. }
  2817. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2818. {
  2819. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2820. __func__, irq);
  2821. return IRQ_HANDLED;
  2822. }
  2823. static int wcd937x_bind(struct device *dev)
  2824. {
  2825. int ret = 0, i = 0;
  2826. struct wcd937x_priv *wcd937x = NULL;
  2827. struct wcd937x_pdata *pdata = NULL;
  2828. struct wcd_ctrl_platform_data *plat_data = NULL;
  2829. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2830. if (!wcd937x)
  2831. return -ENOMEM;
  2832. dev_set_drvdata(dev, wcd937x);
  2833. pdata = wcd937x_populate_dt_data(dev);
  2834. if (!pdata) {
  2835. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2836. return -EINVAL;
  2837. }
  2838. wcd937x->dev = dev;
  2839. wcd937x->dev->platform_data = pdata;
  2840. wcd937x->rst_np = pdata->rst_np;
  2841. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2842. pdata->regulator, pdata->num_supplies);
  2843. if (!wcd937x->supplies) {
  2844. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2845. __func__);
  2846. goto err_bind_all;
  2847. }
  2848. plat_data = dev_get_platdata(dev->parent);
  2849. if (!plat_data) {
  2850. dev_err(dev, "%s: platform data from parent is NULL\n",
  2851. __func__);
  2852. ret = -EINVAL;
  2853. goto err_bind_all;
  2854. }
  2855. wcd937x->handle = (void *)plat_data->handle;
  2856. if (!wcd937x->handle) {
  2857. dev_err(dev, "%s: handle is NULL\n", __func__);
  2858. ret = -EINVAL;
  2859. goto err_bind_all;
  2860. }
  2861. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2862. if (!wcd937x->update_wcd_event) {
  2863. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2864. __func__);
  2865. ret = -EINVAL;
  2866. goto err_bind_all;
  2867. }
  2868. wcd937x->register_notifier = plat_data->register_notifier;
  2869. if (!wcd937x->register_notifier) {
  2870. dev_err(dev, "%s: register_notifier api is null!\n",
  2871. __func__);
  2872. ret = -EINVAL;
  2873. goto err_bind_all;
  2874. }
  2875. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2876. pdata->regulator,
  2877. pdata->num_supplies);
  2878. if (ret) {
  2879. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2880. __func__);
  2881. goto err_bind_all;
  2882. }
  2883. wcd937x_reset(dev);
  2884. /*
  2885. * Add 5msec delay to provide sufficient time for
  2886. * soundwire auto enumeration of slave devices as
  2887. * as per HW requirement.
  2888. */
  2889. usleep_range(5000, 5010);
  2890. wcd937x->wakeup = wcd937x_wakeup;
  2891. ret = component_bind_all(dev, wcd937x);
  2892. if (ret) {
  2893. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2894. __func__, ret);
  2895. goto err_bind_all;
  2896. }
  2897. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2898. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2899. if (ret) {
  2900. dev_err(dev, "Failed to read port mapping\n");
  2901. goto err;
  2902. }
  2903. ret = wcd937x_parse_port_params(dev, "qcom,swr-tx-port-params",
  2904. CODEC_TX);
  2905. if (ret) {
  2906. dev_err(dev, "Failed to read port params\n");
  2907. goto err;
  2908. }
  2909. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2910. if (!wcd937x->rx_swr_dev) {
  2911. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2912. __func__);
  2913. ret = -ENODEV;
  2914. goto err;
  2915. }
  2916. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2917. if (!wcd937x->tx_swr_dev) {
  2918. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2919. __func__);
  2920. ret = -ENODEV;
  2921. goto err;
  2922. }
  2923. swr_init_port_params(wcd937x->tx_swr_dev, SWR_NUM_PORTS,
  2924. wcd937x->swr_tx_port_params);
  2925. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2926. &wcd937x_regmap_config);
  2927. if (!wcd937x->regmap) {
  2928. dev_err(dev, "%s: Regmap init failed\n",
  2929. __func__);
  2930. goto err;
  2931. }
  2932. /* Set all interupts as edge triggered */
  2933. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2934. regmap_write(wcd937x->regmap,
  2935. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2936. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2937. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2938. wcd937x->irq_info.codec_name = "WCD937X";
  2939. wcd937x->irq_info.regmap = wcd937x->regmap;
  2940. wcd937x->irq_info.dev = dev;
  2941. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2942. if (ret) {
  2943. dev_err(dev, "%s: IRQ init failed: %d\n",
  2944. __func__, ret);
  2945. goto err;
  2946. }
  2947. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2948. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2949. if (ret < 0) {
  2950. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2951. goto err_irq;
  2952. }
  2953. /* default L1 power setting */
  2954. wcd937x->tx_ch_pwr[0] = 1;
  2955. wcd937x->tx_ch_pwr[1] = 1;
  2956. mutex_init(&wcd937x->micb_lock);
  2957. mutex_init(&wcd937x->ana_tx_clk_lock);
  2958. /* Request for watchdog interrupt */
  2959. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2960. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2961. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2962. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2963. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2964. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2965. /* Disable watchdog interrupt for HPH and AUX */
  2966. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2967. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2968. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2969. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2970. wcd937x_dai, ARRAY_SIZE(wcd937x_dai));
  2971. if (ret) {
  2972. dev_err(dev, "%s: Codec registration failed\n",
  2973. __func__);
  2974. goto err_irq;
  2975. }
  2976. return ret;
  2977. err_irq:
  2978. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2979. err:
  2980. component_unbind_all(dev, wcd937x);
  2981. err_bind_all:
  2982. dev_set_drvdata(dev, NULL);
  2983. kfree(pdata);
  2984. kfree(wcd937x);
  2985. return ret;
  2986. }
  2987. static void wcd937x_unbind(struct device *dev)
  2988. {
  2989. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2990. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2991. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2992. snd_soc_unregister_component(dev);
  2993. component_unbind_all(dev, wcd937x);
  2994. mutex_destroy(&wcd937x->micb_lock);
  2995. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2996. dev_set_drvdata(dev, NULL);
  2997. kfree(pdata);
  2998. kfree(wcd937x);
  2999. }
  3000. static const struct of_device_id wcd937x_dt_match[] = {
  3001. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  3002. {}
  3003. };
  3004. static const struct component_master_ops wcd937x_comp_ops = {
  3005. .bind = wcd937x_bind,
  3006. .unbind = wcd937x_unbind,
  3007. };
  3008. static int wcd937x_compare_of(struct device *dev, void *data)
  3009. {
  3010. return dev->of_node == data;
  3011. }
  3012. static void wcd937x_release_of(struct device *dev, void *data)
  3013. {
  3014. of_node_put(data);
  3015. }
  3016. static int wcd937x_add_slave_components(struct device *dev,
  3017. struct component_match **matchptr)
  3018. {
  3019. struct device_node *np, *rx_node, *tx_node;
  3020. np = dev->of_node;
  3021. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3022. if (!rx_node) {
  3023. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3024. return -ENODEV;
  3025. }
  3026. of_node_get(rx_node);
  3027. component_match_add_release(dev, matchptr,
  3028. wcd937x_release_of,
  3029. wcd937x_compare_of,
  3030. rx_node);
  3031. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3032. if (!tx_node) {
  3033. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3034. return -ENODEV;
  3035. }
  3036. of_node_get(tx_node);
  3037. component_match_add_release(dev, matchptr,
  3038. wcd937x_release_of,
  3039. wcd937x_compare_of,
  3040. tx_node);
  3041. return 0;
  3042. }
  3043. static int wcd937x_probe(struct platform_device *pdev)
  3044. {
  3045. struct component_match *match = NULL;
  3046. int ret;
  3047. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  3048. if (ret)
  3049. return ret;
  3050. return component_master_add_with_match(&pdev->dev,
  3051. &wcd937x_comp_ops, match);
  3052. }
  3053. static int wcd937x_remove(struct platform_device *pdev)
  3054. {
  3055. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  3056. dev_set_drvdata(&pdev->dev, NULL);
  3057. return 0;
  3058. }
  3059. #ifdef CONFIG_PM_SLEEP
  3060. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  3061. SET_SYSTEM_SLEEP_PM_OPS(
  3062. wcd937x_suspend,
  3063. wcd937x_resume
  3064. )
  3065. };
  3066. #endif
  3067. static struct platform_driver wcd937x_codec_driver = {
  3068. .probe = wcd937x_probe,
  3069. .remove = wcd937x_remove,
  3070. .driver = {
  3071. .name = "wcd937x_codec",
  3072. .owner = THIS_MODULE,
  3073. .of_match_table = of_match_ptr(wcd937x_dt_match),
  3074. #ifdef CONFIG_PM_SLEEP
  3075. .pm = &wcd937x_dev_pm_ops,
  3076. #endif
  3077. .suppress_bind_attrs = true,
  3078. },
  3079. };
  3080. module_platform_driver(wcd937x_codec_driver);
  3081. MODULE_DESCRIPTION("WCD937X Codec driver");
  3082. MODULE_LICENSE("GPL v2");