dsi_catalog.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DSI_CATALOG_H_
  6. #define _DSI_CATALOG_H_
  7. #include "dsi_ctrl_hw.h"
  8. #include "dsi_phy_hw.h"
  9. /**
  10. * dsi_catalog_ctrl_setup() - return catalog info for dsi controller
  11. * @ctrl: Pointer to DSI controller hw object.
  12. * @version: DSI controller version.
  13. * @index: DSI controller instance ID.
  14. * @phy_isolation_enabled: DSI controller works isolated from phy.
  15. * @null_insertion_enabled: DSI controller inserts null packet.
  16. *
  17. * This function setups the catalog information in the dsi_ctrl_hw object.
  18. *
  19. * return: error code for failure and 0 for success.
  20. */
  21. int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl,
  22. enum dsi_ctrl_version version, u32 index,
  23. bool phy_isolation_enabled, bool null_insertion_enabled);
  24. /**
  25. * dsi_catalog_phy_setup() - return catalog info for dsi phy hardware
  26. * @phy: Pointer to DSI PHY hw object.
  27. * @version: DSI PHY version.
  28. * @index: DSI PHY instance ID.
  29. *
  30. * This function setups the catalog information in the dsi_phy_hw object.
  31. *
  32. * return: error code for failure and 0 for success.
  33. */
  34. int dsi_catalog_phy_setup(struct dsi_phy_hw *phy,
  35. enum dsi_phy_version version,
  36. u32 index);
  37. /**
  38. * dsi_phy_timing_calc_init() - initialize info for DSI PHY timing calculations
  39. * @phy: Pointer to DSI PHY hw object.
  40. * @version: DSI PHY version.
  41. *
  42. * This function setups the catalog information in the dsi_phy_hw object.
  43. *
  44. * return: error code for failure and 0 for success.
  45. */
  46. int dsi_phy_timing_calc_init(struct dsi_phy_hw *phy,
  47. enum dsi_phy_version version);
  48. /**
  49. * dsi_phy_hw_calculate_timing_params() - DSI PHY timing parameter calculations
  50. * @phy: Pointer to DSI PHY hw object.
  51. * @mode: DSI mode information.
  52. * @host: DSI host configuration.
  53. * @timing: DSI phy lane configurations.
  54. * @use_mode_bit_clk: Boolean to indicate whether to recalculate bit clk.
  55. *
  56. * This function setups the catalog information in the dsi_phy_hw object.
  57. *
  58. * return: error code for failure and 0 for success.
  59. */
  60. int dsi_phy_hw_calculate_timing_params(struct dsi_phy_hw *phy,
  61. struct dsi_mode_info *mode,
  62. struct dsi_host_common_cfg *host,
  63. struct dsi_phy_per_lane_cfgs *timing,
  64. bool use_mode_bit_clk);
  65. /* Definitions for 14nm PHY hardware driver */
  66. void dsi_phy_hw_v2_0_regulator_enable(struct dsi_phy_hw *phy,
  67. struct dsi_phy_per_lane_cfgs *cfg);
  68. void dsi_phy_hw_v2_0_regulator_disable(struct dsi_phy_hw *phy);
  69. void dsi_phy_hw_v2_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  70. void dsi_phy_hw_v2_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  71. void dsi_phy_hw_v2_0_idle_on(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  72. void dsi_phy_hw_v2_0_idle_off(struct dsi_phy_hw *phy);
  73. int dsi_phy_hw_timing_val_v2_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
  74. u32 *timing_val, u32 size);
  75. void dsi_phy_hw_v2_0_clamp_ctrl(struct dsi_phy_hw *phy, bool enable);
  76. /* Definitions for 10nm PHY hardware driver */
  77. void dsi_phy_hw_v3_0_regulator_enable(struct dsi_phy_hw *phy,
  78. struct dsi_phy_per_lane_cfgs *cfg);
  79. void dsi_phy_hw_v3_0_regulator_disable(struct dsi_phy_hw *phy);
  80. void dsi_phy_hw_v3_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  81. void dsi_phy_hw_v3_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  82. int dsi_phy_hw_v3_0_wait_for_lane_idle(struct dsi_phy_hw *phy, u32 lanes);
  83. void dsi_phy_hw_v3_0_ulps_request(struct dsi_phy_hw *phy,
  84. struct dsi_phy_cfg *cfg, u32 lanes);
  85. void dsi_phy_hw_v3_0_ulps_exit(struct dsi_phy_hw *phy,
  86. struct dsi_phy_cfg *cfg, u32 lanes);
  87. u32 dsi_phy_hw_v3_0_get_lanes_in_ulps(struct dsi_phy_hw *phy);
  88. bool dsi_phy_hw_v3_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes);
  89. int dsi_phy_hw_timing_val_v3_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
  90. u32 *timing_val, u32 size);
  91. void dsi_phy_hw_v3_0_clamp_ctrl(struct dsi_phy_hw *phy, bool enable);
  92. int dsi_phy_hw_v3_0_lane_reset(struct dsi_phy_hw *phy);
  93. void dsi_phy_hw_v3_0_toggle_resync_fifo(struct dsi_phy_hw *phy);
  94. /* Definitions for 7nm PHY hardware driver */
  95. void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  96. void dsi_phy_hw_v4_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
  97. int dsi_phy_hw_v4_0_wait_for_lane_idle(struct dsi_phy_hw *phy, u32 lanes);
  98. void dsi_phy_hw_v4_0_ulps_request(struct dsi_phy_hw *phy,
  99. struct dsi_phy_cfg *cfg, u32 lanes);
  100. void dsi_phy_hw_v4_0_ulps_exit(struct dsi_phy_hw *phy,
  101. struct dsi_phy_cfg *cfg, u32 lanes);
  102. u32 dsi_phy_hw_v4_0_get_lanes_in_ulps(struct dsi_phy_hw *phy);
  103. bool dsi_phy_hw_v4_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes);
  104. int dsi_phy_hw_timing_val_v4_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
  105. u32 *timing_val, u32 size);
  106. int dsi_phy_hw_v4_0_lane_reset(struct dsi_phy_hw *phy);
  107. void dsi_phy_hw_v4_0_toggle_resync_fifo(struct dsi_phy_hw *phy);
  108. void dsi_phy_hw_v4_0_reset_clk_en_sel(struct dsi_phy_hw *phy);
  109. void dsi_phy_hw_v4_0_set_continuous_clk(struct dsi_phy_hw *phy, bool enable);
  110. /* DSI controller common ops */
  111. u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);
  112. void dsi_ctrl_hw_cmn_debug_bus(struct dsi_ctrl_hw *ctrl, u32 *entries,
  113. u32 size);
  114. void dsi_ctrl_hw_cmn_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints);
  115. void dsi_ctrl_hw_cmn_enable_status_interrupts(struct dsi_ctrl_hw *ctrl,
  116. u32 ints);
  117. u64 dsi_ctrl_hw_cmn_get_error_status(struct dsi_ctrl_hw *ctrl);
  118. void dsi_ctrl_hw_cmn_clear_error_status(struct dsi_ctrl_hw *ctrl, u64 errors);
  119. void dsi_ctrl_hw_cmn_enable_error_interrupts(struct dsi_ctrl_hw *ctrl,
  120. u64 errors);
  121. void dsi_ctrl_hw_cmn_video_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
  122. enum dsi_test_pattern type,
  123. u32 init_val);
  124. void dsi_ctrl_hw_cmn_cmd_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
  125. enum dsi_test_pattern type,
  126. u32 init_val,
  127. u32 stream_id);
  128. void dsi_ctrl_hw_cmn_test_pattern_enable(struct dsi_ctrl_hw *ctrl, bool enable);
  129. void dsi_ctrl_hw_cmn_trigger_cmd_test_pattern(struct dsi_ctrl_hw *ctrl,
  130. u32 stream_id);
  131. void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,
  132. struct dsi_host_common_cfg *config);
  133. void dsi_ctrl_hw_cmn_video_engine_en(struct dsi_ctrl_hw *ctrl, bool on);
  134. void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl,
  135. struct dsi_host_common_cfg *common_cfg,
  136. struct dsi_video_engine_cfg *cfg);
  137. void dsi_ctrl_hw_cmn_setup_avr(struct dsi_ctrl_hw *ctrl, bool enable);
  138. void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl,
  139. struct dsi_mode_info *mode);
  140. void dsi_ctrl_hw_cmn_set_timing_db(struct dsi_ctrl_hw *ctrl,
  141. bool enable);
  142. void dsi_ctrl_hw_cmn_cmd_engine_setup(struct dsi_ctrl_hw *ctrl,
  143. struct dsi_host_common_cfg *common_cfg,
  144. struct dsi_cmd_engine_cfg *cfg);
  145. void dsi_ctrl_hw_cmn_ctrl_en(struct dsi_ctrl_hw *ctrl, bool on);
  146. void dsi_ctrl_hw_cmn_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on);
  147. void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,
  148. struct dsi_mode_info *mode,
  149. u32 h_stride,
  150. u32 vc_id,
  151. struct dsi_rect *roi);
  152. void dsi_ctrl_hw_cmn_phy_sw_reset(struct dsi_ctrl_hw *ctrl);
  153. void dsi_ctrl_hw_cmn_soft_reset(struct dsi_ctrl_hw *ctrl);
  154. void dsi_ctrl_hw_cmn_setup_misr(struct dsi_ctrl_hw *ctrl,
  155. enum dsi_op_mode panel_mode,
  156. bool enable, u32 frame_count);
  157. u32 dsi_ctrl_hw_cmn_collect_misr(struct dsi_ctrl_hw *ctrl,
  158. enum dsi_op_mode panel_mode);
  159. void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl,
  160. struct dsi_ctrl_cmd_dma_info *cmd,
  161. u32 flags);
  162. void dsi_ctrl_hw_cmn_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl,
  163. struct dsi_ctrl_cmd_dma_fifo_info *cmd,
  164. u32 flags);
  165. void dsi_ctrl_hw_cmn_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl);
  166. void dsi_ctrl_hw_cmn_trigger_command_dma(struct dsi_ctrl_hw *ctrl);
  167. void dsi_ctrl_hw_dln0_phy_err(struct dsi_ctrl_hw *ctrl);
  168. void dsi_ctrl_hw_cmn_phy_reset_config(struct dsi_ctrl_hw *ctrl,
  169. bool enable);
  170. void dsi_ctrl_hw_22_phy_reset_config(struct dsi_ctrl_hw *ctrl,
  171. bool enable);
  172. u32 dsi_ctrl_hw_cmn_get_cmd_read_data(struct dsi_ctrl_hw *ctrl,
  173. u8 *rd_buf,
  174. u32 read_offset,
  175. u32 rx_byte,
  176. u32 pkt_size, u32 *hw_read_cnt);
  177. void dsi_ctrl_hw_cmn_clear_rdbk_reg(struct dsi_ctrl_hw *ctrl);
  178. void dsi_ctrl_hw_22_schedule_dma_cmd(struct dsi_ctrl_hw *ctrl, int line_on);
  179. int dsi_ctrl_hw_cmn_ctrl_reset(struct dsi_ctrl_hw *ctrl,
  180. int mask);
  181. void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx,
  182. bool en);
  183. void dsi_ctrl_hw_cmn_error_intr_ctrl(struct dsi_ctrl_hw *ctrl, bool en);
  184. u32 dsi_ctrl_hw_cmn_get_error_mask(struct dsi_ctrl_hw *ctrl);
  185. u32 dsi_ctrl_hw_cmn_get_hw_version(struct dsi_ctrl_hw *ctrl);
  186. int dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl_hw *ctrl);
  187. /* Definitions specific to 1.4 DSI controller hardware */
  188. int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);
  189. void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl,
  190. struct dsi_lane_map *lane_map);
  191. void dsi_ctrl_hw_cmn_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes);
  192. void dsi_ctrl_hw_cmn_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes);
  193. u32 dsi_ctrl_hw_cmn_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl);
  194. void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl,
  195. u32 lanes,
  196. bool enable_ulps);
  197. void dsi_ctrl_hw_14_clamp_disable(struct dsi_ctrl_hw *ctrl,
  198. u32 lanes,
  199. bool disable_ulps);
  200. ssize_t dsi_ctrl_hw_14_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
  201. char *buf,
  202. u32 size);
  203. /* Definitions specific to 2.0 DSI controller hardware */
  204. void dsi_ctrl_hw_20_setup_lane_map(struct dsi_ctrl_hw *ctrl,
  205. struct dsi_lane_map *lane_map);
  206. int dsi_ctrl_hw_20_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);
  207. ssize_t dsi_ctrl_hw_20_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
  208. char *buf,
  209. u32 size);
  210. void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl,
  211. struct dsi_ctrl_cmd_dma_info *cmd,
  212. u32 flags);
  213. /* Definitions specific to 2.2 DSI controller hardware */
  214. void dsi_ctrl_hw_22_config_clk_gating(struct dsi_ctrl_hw *ctrl, bool enable,
  215. enum dsi_clk_gate_type clk_selection);
  216. void dsi_ctrl_hw_cmn_set_continuous_clk(struct dsi_ctrl_hw *ctrl, bool enable);
  217. void dsi_ctrl_hw_cmn_hs_req_sel(struct dsi_ctrl_hw *ctrl, bool sel_phy);
  218. /* dynamic refresh specific functions */
  219. void dsi_phy_hw_v3_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset);
  220. void dsi_phy_hw_v3_0_dyn_refresh_config(struct dsi_phy_hw *phy,
  221. struct dsi_phy_cfg *cfg, bool is_master);
  222. void dsi_phy_hw_v3_0_dyn_refresh_pipe_delay(struct dsi_phy_hw *phy,
  223. struct dsi_dyn_clk_delay *delay);
  224. int dsi_ctrl_hw_cmn_wait4dynamic_refresh_done(struct dsi_ctrl_hw *ctrl);
  225. int dsi_phy_hw_v3_0_cache_phy_timings(struct dsi_phy_per_lane_cfgs *timings,
  226. u32 *dst, u32 size);
  227. void dsi_phy_hw_v4_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset);
  228. void dsi_phy_hw_v4_0_dyn_refresh_config(struct dsi_phy_hw *phy,
  229. struct dsi_phy_cfg *cfg, bool is_master);
  230. void dsi_phy_hw_v4_0_dyn_refresh_pipe_delay(struct dsi_phy_hw *phy,
  231. struct dsi_dyn_clk_delay *delay);
  232. int dsi_phy_hw_v4_0_cache_phy_timings(struct dsi_phy_per_lane_cfgs *timings,
  233. u32 *dst, u32 size);
  234. #endif /* _DSI_CATALOG_H_ */