hfi.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/delay.h>
  7. #include <linux/slab.h>
  8. #include <linux/random.h>
  9. #include <asm/errno.h>
  10. #include <linux/timer.h>
  11. #include <media/cam_icp.h>
  12. #include <linux/iopoll.h>
  13. #include "cam_io_util.h"
  14. #include "hfi_reg.h"
  15. #include "hfi_sys_defs.h"
  16. #include "hfi_session_defs.h"
  17. #include "hfi_intf.h"
  18. #include "cam_icp_hw_mgr_intf.h"
  19. #include "cam_debug_util.h"
  20. #include "cam_compat.h"
  21. #define HFI_VERSION_INFO_MAJOR_VAL 1
  22. #define HFI_VERSION_INFO_MINOR_VAL 1
  23. #define HFI_VERSION_INFO_STEP_VAL 0
  24. #define HFI_VERSION_INFO_STEP_VAL 0
  25. #define HFI_VERSION_INFO_MAJOR_BMSK 0xFF000000
  26. #define HFI_VERSION_INFO_MAJOR_SHFT 24
  27. #define HFI_VERSION_INFO_MINOR_BMSK 0xFFFF00
  28. #define HFI_VERSION_INFO_MINOR_SHFT 8
  29. #define HFI_VERSION_INFO_STEP_BMSK 0xFF
  30. #define HFI_VERSION_INFO_STEP_SHFT 0
  31. /* TO DO Lower timeout value */
  32. #define HFI_POLL_DELAY_US 10
  33. #define HFI_POLL_TIMEOUT_US 1500000
  34. static struct hfi_info *g_hfi;
  35. unsigned int g_icp_mmu_hdl;
  36. static DEFINE_MUTEX(hfi_cmd_q_mutex);
  37. static DEFINE_MUTEX(hfi_msg_q_mutex);
  38. static void hfi_irq_raise(struct hfi_info *hfi)
  39. {
  40. if (hfi->ops.irq_raise)
  41. hfi->ops.irq_raise(hfi->priv);
  42. }
  43. static void hfi_irq_enable(struct hfi_info *hfi)
  44. {
  45. if (hfi->ops.irq_enable)
  46. hfi->ops.irq_enable(hfi->priv);
  47. }
  48. static void __iomem *hfi_iface_addr(struct hfi_info *hfi)
  49. {
  50. void __iomem *ret = NULL;
  51. if (hfi->ops.iface_addr)
  52. ret = hfi->ops.iface_addr(hfi->priv);
  53. return IS_ERR_OR_NULL(ret) ? NULL : ret;
  54. }
  55. static void hfi_queue_dump(uint32_t *dwords, int count)
  56. {
  57. int i;
  58. int rows;
  59. int remaining;
  60. rows = count / 4;
  61. remaining = count % 4;
  62. for (i = 0; i < rows; i++, dwords += 4)
  63. CAM_DBG(CAM_HFI,
  64. "word[%04d]: 0x%08x 0x%08x 0x%08x 0x%08x",
  65. i * 4, dwords[0], dwords[1], dwords[2], dwords[3]);
  66. if (remaining == 1)
  67. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x", rows * 4, dwords[0]);
  68. else if (remaining == 2)
  69. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x 0x%08x",
  70. rows * 4, dwords[0], dwords[1]);
  71. else if (remaining == 3)
  72. CAM_DBG(CAM_HFI, "word[%04d]: 0x%08x 0x%08x 0x%08x",
  73. rows * 4, dwords[0], dwords[1], dwords[2]);
  74. }
  75. void cam_hfi_queue_dump(void)
  76. {
  77. struct hfi_mem_info *hfi_mem = &g_hfi->map;
  78. struct hfi_qtbl *qtbl;
  79. struct hfi_q_hdr *q_hdr;
  80. uint32_t *dwords;
  81. int num_dwords;
  82. if (!hfi_mem) {
  83. CAM_ERR(CAM_HFI, "hfi mem info NULL... unable to dump queues");
  84. return;
  85. }
  86. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  87. CAM_DBG(CAM_HFI,
  88. "qtbl header: version=0x%08x tbl_size=%u numq=%u qhdr_size=%u",
  89. qtbl->q_tbl_hdr.qtbl_version,
  90. qtbl->q_tbl_hdr.qtbl_size,
  91. qtbl->q_tbl_hdr.qtbl_num_q,
  92. qtbl->q_tbl_hdr.qtbl_qhdr_size);
  93. q_hdr = &qtbl->q_hdr[Q_CMD];
  94. CAM_DBG(CAM_HFI,
  95. "cmd_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
  96. hfi_mem->cmd_q.iova,
  97. q_hdr->qhdr_q_size,
  98. q_hdr->qhdr_read_idx,
  99. q_hdr->qhdr_write_idx);
  100. dwords = (uint32_t *)hfi_mem->cmd_q.kva;
  101. num_dwords = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  102. hfi_queue_dump(dwords, num_dwords);
  103. q_hdr = &qtbl->q_hdr[Q_MSG];
  104. CAM_DBG(CAM_HFI,
  105. "msg_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
  106. hfi_mem->msg_q.iova,
  107. q_hdr->qhdr_q_size,
  108. q_hdr->qhdr_read_idx,
  109. q_hdr->qhdr_write_idx);
  110. dwords = (uint32_t *)hfi_mem->msg_q.kva;
  111. num_dwords = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  112. hfi_queue_dump(dwords, num_dwords);
  113. }
  114. int hfi_write_cmd(void *cmd_ptr)
  115. {
  116. uint32_t size_in_words, empty_space, new_write_idx, read_idx, temp;
  117. uint32_t *write_q, *write_ptr;
  118. struct hfi_qtbl *q_tbl;
  119. struct hfi_q_hdr *q;
  120. int rc = 0;
  121. if (!cmd_ptr) {
  122. CAM_ERR(CAM_HFI, "command is null");
  123. return -EINVAL;
  124. }
  125. mutex_lock(&hfi_cmd_q_mutex);
  126. if (!g_hfi) {
  127. CAM_ERR(CAM_HFI, "HFI interface not setup");
  128. rc = -ENODEV;
  129. goto err;
  130. }
  131. if (g_hfi->hfi_state != HFI_READY ||
  132. !g_hfi->cmd_q_state) {
  133. CAM_ERR(CAM_HFI, "HFI state: %u, cmd q state: %u",
  134. g_hfi->hfi_state, g_hfi->cmd_q_state);
  135. rc = -ENODEV;
  136. goto err;
  137. }
  138. q_tbl = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  139. q = &q_tbl->q_hdr[Q_CMD];
  140. write_q = (uint32_t *)g_hfi->map.cmd_q.kva;
  141. size_in_words = (*(uint32_t *)cmd_ptr) >> BYTE_WORD_SHIFT;
  142. if (!size_in_words) {
  143. CAM_DBG(CAM_HFI, "failed");
  144. rc = -EINVAL;
  145. goto err;
  146. }
  147. read_idx = q->qhdr_read_idx;
  148. empty_space = (q->qhdr_write_idx >= read_idx) ?
  149. (q->qhdr_q_size - (q->qhdr_write_idx - read_idx)) :
  150. (read_idx - q->qhdr_write_idx);
  151. if (empty_space <= size_in_words) {
  152. CAM_ERR(CAM_HFI, "failed: empty space %u, size_in_words %u",
  153. empty_space, size_in_words);
  154. rc = -EIO;
  155. goto err;
  156. }
  157. new_write_idx = q->qhdr_write_idx + size_in_words;
  158. write_ptr = (uint32_t *)(write_q + q->qhdr_write_idx);
  159. if (new_write_idx < q->qhdr_q_size) {
  160. memcpy(write_ptr, (uint8_t *)cmd_ptr,
  161. size_in_words << BYTE_WORD_SHIFT);
  162. } else {
  163. new_write_idx -= q->qhdr_q_size;
  164. temp = (size_in_words - new_write_idx) << BYTE_WORD_SHIFT;
  165. memcpy(write_ptr, (uint8_t *)cmd_ptr, temp);
  166. memcpy(write_q, (uint8_t *)cmd_ptr + temp,
  167. new_write_idx << BYTE_WORD_SHIFT);
  168. }
  169. /*
  170. * To make sure command data in a command queue before
  171. * updating write index
  172. */
  173. wmb();
  174. q->qhdr_write_idx = new_write_idx;
  175. /*
  176. * Before raising interrupt make sure command data is ready for
  177. * firmware to process
  178. */
  179. wmb();
  180. hfi_irq_raise(g_hfi);
  181. /* Ensure HOST2ICP trigger is received by FW */
  182. wmb();
  183. err:
  184. mutex_unlock(&hfi_cmd_q_mutex);
  185. return rc;
  186. }
  187. int hfi_read_message(uint32_t *pmsg, uint8_t q_id,
  188. uint32_t *words_read)
  189. {
  190. struct hfi_qtbl *q_tbl_ptr;
  191. struct hfi_q_hdr *q;
  192. uint32_t new_read_idx, size_in_words, word_diff, temp;
  193. uint32_t *read_q, *read_ptr, *write_ptr;
  194. uint32_t size_upper_bound = 0;
  195. int rc = 0;
  196. if (!pmsg) {
  197. CAM_ERR(CAM_HFI, "Invalid msg");
  198. return -EINVAL;
  199. }
  200. if (q_id > Q_DBG) {
  201. CAM_ERR(CAM_HFI, "Invalid q :%u", q_id);
  202. return -EINVAL;
  203. }
  204. mutex_lock(&hfi_msg_q_mutex);
  205. if (!g_hfi) {
  206. CAM_ERR(CAM_HFI, "hfi not set up yet");
  207. rc = -ENODEV;
  208. goto err;
  209. }
  210. if ((g_hfi->hfi_state != HFI_READY) ||
  211. !g_hfi->msg_q_state) {
  212. CAM_ERR(CAM_HFI, "hfi state: %u, msg q state: %u",
  213. g_hfi->hfi_state, g_hfi->msg_q_state);
  214. rc = -ENODEV;
  215. goto err;
  216. }
  217. q_tbl_ptr = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  218. q = &q_tbl_ptr->q_hdr[q_id];
  219. if (q->qhdr_read_idx == q->qhdr_write_idx) {
  220. CAM_DBG(CAM_HFI, "Q not ready, state:%u, r idx:%u, w idx:%u",
  221. g_hfi->hfi_state, q->qhdr_read_idx, q->qhdr_write_idx);
  222. rc = -EIO;
  223. goto err;
  224. }
  225. if (q_id == Q_MSG) {
  226. read_q = (uint32_t *)g_hfi->map.msg_q.kva;
  227. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS;
  228. } else {
  229. read_q = (uint32_t *)g_hfi->map.dbg_q.kva;
  230. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_IN_WORDS;
  231. }
  232. read_ptr = (uint32_t *)(read_q + q->qhdr_read_idx);
  233. write_ptr = (uint32_t *)(read_q + q->qhdr_write_idx);
  234. if (write_ptr > read_ptr)
  235. size_in_words = write_ptr - read_ptr;
  236. else {
  237. word_diff = read_ptr - write_ptr;
  238. if (q_id == Q_MSG)
  239. size_in_words = (ICP_MSG_Q_SIZE_IN_BYTES >>
  240. BYTE_WORD_SHIFT) - word_diff;
  241. else
  242. size_in_words = (ICP_DBG_Q_SIZE_IN_BYTES >>
  243. BYTE_WORD_SHIFT) - word_diff;
  244. }
  245. if ((size_in_words == 0) ||
  246. (size_in_words > size_upper_bound)) {
  247. CAM_ERR(CAM_HFI, "invalid HFI message packet size - 0x%08x",
  248. size_in_words << BYTE_WORD_SHIFT);
  249. q->qhdr_read_idx = q->qhdr_write_idx;
  250. rc = -EIO;
  251. goto err;
  252. }
  253. new_read_idx = q->qhdr_read_idx + size_in_words;
  254. if (new_read_idx < q->qhdr_q_size) {
  255. memcpy(pmsg, read_ptr, size_in_words << BYTE_WORD_SHIFT);
  256. } else {
  257. new_read_idx -= q->qhdr_q_size;
  258. temp = (size_in_words - new_read_idx) << BYTE_WORD_SHIFT;
  259. memcpy(pmsg, read_ptr, temp);
  260. memcpy((uint8_t *)pmsg + temp, read_q,
  261. new_read_idx << BYTE_WORD_SHIFT);
  262. }
  263. q->qhdr_read_idx = new_read_idx;
  264. *words_read = size_in_words;
  265. /* Memory Barrier to make sure message
  266. * queue parameters are updated after read
  267. */
  268. wmb();
  269. err:
  270. mutex_unlock(&hfi_msg_q_mutex);
  271. return rc;
  272. }
  273. int hfi_cmd_ubwc_config(uint32_t *ubwc_cfg)
  274. {
  275. uint8_t *prop;
  276. struct hfi_cmd_prop *dbg_prop;
  277. uint32_t size = 0;
  278. size = sizeof(struct hfi_cmd_prop) +
  279. sizeof(struct hfi_cmd_ubwc_cfg);
  280. CAM_DBG(CAM_HFI,
  281. "size of ubwc %u, ubwc_cfg [rd-0x%x,wr-0x%x]",
  282. size, ubwc_cfg[0], ubwc_cfg[1]);
  283. prop = kzalloc(size, GFP_KERNEL);
  284. if (!prop)
  285. return -ENOMEM;
  286. dbg_prop = (struct hfi_cmd_prop *)prop;
  287. dbg_prop->size = size;
  288. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  289. dbg_prop->num_prop = 1;
  290. dbg_prop->prop_data[0] = HFI_PROP_SYS_UBWC_CFG;
  291. dbg_prop->prop_data[1] = ubwc_cfg[0];
  292. dbg_prop->prop_data[2] = ubwc_cfg[1];
  293. hfi_write_cmd(prop);
  294. kfree(prop);
  295. return 0;
  296. }
  297. int hfi_cmd_ubwc_config_ext(uint32_t *ubwc_ipe_cfg,
  298. uint32_t *ubwc_bps_cfg)
  299. {
  300. uint8_t *prop;
  301. struct hfi_cmd_prop *dbg_prop;
  302. uint32_t size = 0;
  303. size = sizeof(struct hfi_cmd_prop) +
  304. sizeof(struct hfi_cmd_ubwc_cfg_ext);
  305. CAM_DBG(CAM_HFI,
  306. "size of ubwc %u, ubwc_ipe_cfg[rd-0x%x,wr-0x%x] ubwc_bps_cfg[rd-0x%x,wr-0x%x]",
  307. size, ubwc_ipe_cfg[0], ubwc_ipe_cfg[1],
  308. ubwc_bps_cfg[0], ubwc_bps_cfg[1]);
  309. prop = kzalloc(size, GFP_KERNEL);
  310. if (!prop)
  311. return -ENOMEM;
  312. dbg_prop = (struct hfi_cmd_prop *)prop;
  313. dbg_prop->size = size;
  314. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  315. dbg_prop->num_prop = 1;
  316. dbg_prop->prop_data[0] = HFI_PROPERTY_SYS_UBWC_CONFIG_EX;
  317. dbg_prop->prop_data[1] = ubwc_bps_cfg[0];
  318. dbg_prop->prop_data[2] = ubwc_bps_cfg[1];
  319. dbg_prop->prop_data[3] = ubwc_ipe_cfg[0];
  320. dbg_prop->prop_data[4] = ubwc_ipe_cfg[1];
  321. hfi_write_cmd(prop);
  322. kfree(prop);
  323. return 0;
  324. }
  325. int hfi_enable_ipe_bps_pc(bool enable, uint32_t core_info)
  326. {
  327. uint8_t *prop;
  328. struct hfi_cmd_prop *dbg_prop;
  329. uint32_t size = 0;
  330. size = sizeof(struct hfi_cmd_prop) +
  331. sizeof(struct hfi_ipe_bps_pc);
  332. prop = kzalloc(size, GFP_KERNEL);
  333. if (!prop)
  334. return -ENOMEM;
  335. dbg_prop = (struct hfi_cmd_prop *)prop;
  336. dbg_prop->size = size;
  337. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  338. dbg_prop->num_prop = 1;
  339. dbg_prop->prop_data[0] = HFI_PROP_SYS_IPEBPS_PC;
  340. dbg_prop->prop_data[1] = enable;
  341. dbg_prop->prop_data[2] = core_info;
  342. hfi_write_cmd(prop);
  343. kfree(prop);
  344. return 0;
  345. }
  346. int hfi_set_debug_level(u64 icp_dbg_type, uint32_t lvl)
  347. {
  348. uint8_t *prop;
  349. struct hfi_cmd_prop *dbg_prop;
  350. uint32_t size = 0, val;
  351. val = HFI_DEBUG_MSG_LOW |
  352. HFI_DEBUG_MSG_MEDIUM |
  353. HFI_DEBUG_MSG_HIGH |
  354. HFI_DEBUG_MSG_ERROR |
  355. HFI_DEBUG_MSG_FATAL |
  356. HFI_DEBUG_MSG_PERF |
  357. HFI_DEBUG_CFG_WFI |
  358. HFI_DEBUG_CFG_ARM9WD;
  359. if (lvl > val)
  360. return -EINVAL;
  361. size = sizeof(struct hfi_cmd_prop) +
  362. sizeof(struct hfi_debug);
  363. prop = kzalloc(size, GFP_KERNEL);
  364. if (!prop)
  365. return -ENOMEM;
  366. dbg_prop = (struct hfi_cmd_prop *)prop;
  367. dbg_prop->size = size;
  368. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  369. dbg_prop->num_prop = 1;
  370. dbg_prop->prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  371. dbg_prop->prop_data[1] = lvl;
  372. dbg_prop->prop_data[2] = icp_dbg_type;
  373. hfi_write_cmd(prop);
  374. kfree(prop);
  375. return 0;
  376. }
  377. int hfi_set_fw_dump_level(uint32_t lvl)
  378. {
  379. uint8_t *prop = NULL;
  380. struct hfi_cmd_prop *fw_dump_level_switch_prop = NULL;
  381. uint32_t size = 0;
  382. CAM_DBG(CAM_HFI, "fw dump ENTER");
  383. size = sizeof(struct hfi_cmd_prop) + sizeof(lvl);
  384. prop = kzalloc(size, GFP_KERNEL);
  385. if (!prop)
  386. return -ENOMEM;
  387. fw_dump_level_switch_prop = (struct hfi_cmd_prop *)prop;
  388. fw_dump_level_switch_prop->size = size;
  389. fw_dump_level_switch_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  390. fw_dump_level_switch_prop->num_prop = 1;
  391. fw_dump_level_switch_prop->prop_data[0] = HFI_PROP_SYS_FW_DUMP_CFG;
  392. fw_dump_level_switch_prop->prop_data[1] = lvl;
  393. CAM_DBG(CAM_HFI, "prop->size = %d\n"
  394. "prop->pkt_type = %d\n"
  395. "prop->num_prop = %d\n"
  396. "prop->prop_data[0] = %d\n"
  397. "prop->prop_data[1] = %d\n",
  398. fw_dump_level_switch_prop->size,
  399. fw_dump_level_switch_prop->pkt_type,
  400. fw_dump_level_switch_prop->num_prop,
  401. fw_dump_level_switch_prop->prop_data[0],
  402. fw_dump_level_switch_prop->prop_data[1]);
  403. hfi_write_cmd(prop);
  404. kfree(prop);
  405. return 0;
  406. }
  407. void hfi_send_system_cmd(uint32_t type, uint64_t data, uint32_t size)
  408. {
  409. switch (type) {
  410. case HFI_CMD_SYS_INIT: {
  411. struct hfi_cmd_sys_init init;
  412. memset(&init, 0, sizeof(init));
  413. init.size = sizeof(struct hfi_cmd_sys_init);
  414. init.pkt_type = type;
  415. hfi_write_cmd(&init);
  416. }
  417. break;
  418. case HFI_CMD_SYS_PC_PREP: {
  419. struct hfi_cmd_pc_prep prep;
  420. prep.size = sizeof(struct hfi_cmd_pc_prep);
  421. prep.pkt_type = type;
  422. hfi_write_cmd(&prep);
  423. }
  424. break;
  425. case HFI_CMD_SYS_SET_PROPERTY: {
  426. struct hfi_cmd_prop prop;
  427. if ((uint32_t)data == (uint32_t)HFI_PROP_SYS_DEBUG_CFG) {
  428. prop.size = sizeof(struct hfi_cmd_prop);
  429. prop.pkt_type = type;
  430. prop.num_prop = 1;
  431. prop.prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  432. hfi_write_cmd(&prop);
  433. }
  434. }
  435. break;
  436. case HFI_CMD_SYS_GET_PROPERTY:
  437. break;
  438. case HFI_CMD_SYS_PING: {
  439. struct hfi_cmd_ping_pkt ping;
  440. ping.size = sizeof(struct hfi_cmd_ping_pkt);
  441. ping.pkt_type = type;
  442. ping.user_data = (uint64_t)data;
  443. hfi_write_cmd(&ping);
  444. }
  445. break;
  446. case HFI_CMD_SYS_RESET: {
  447. struct hfi_cmd_sys_reset_pkt reset;
  448. reset.size = sizeof(struct hfi_cmd_sys_reset_pkt);
  449. reset.pkt_type = type;
  450. reset.user_data = (uint64_t)data;
  451. hfi_write_cmd(&reset);
  452. }
  453. break;
  454. case HFI_CMD_IPEBPS_CREATE_HANDLE: {
  455. struct hfi_cmd_create_handle handle;
  456. handle.size = sizeof(struct hfi_cmd_create_handle);
  457. handle.pkt_type = type;
  458. handle.handle_type = (uint32_t)data;
  459. handle.user_data1 = 0;
  460. hfi_write_cmd(&handle);
  461. }
  462. break;
  463. case HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT:
  464. break;
  465. default:
  466. CAM_ERR(CAM_HFI, "command not supported :%d", type);
  467. break;
  468. }
  469. }
  470. int hfi_get_hw_caps(void *query_buf)
  471. {
  472. int i = 0;
  473. struct cam_icp_query_cap_cmd *query_cmd = NULL;
  474. if (!query_buf) {
  475. CAM_ERR(CAM_HFI, "query buf is NULL");
  476. return -EINVAL;
  477. }
  478. query_cmd = (struct cam_icp_query_cap_cmd *)query_buf;
  479. query_cmd->fw_version.major = 0x12;
  480. query_cmd->fw_version.minor = 0x12;
  481. query_cmd->fw_version.revision = 0x12;
  482. query_cmd->api_version.major = 0x13;
  483. query_cmd->api_version.minor = 0x13;
  484. query_cmd->api_version.revision = 0x13;
  485. query_cmd->num_ipe = 2;
  486. query_cmd->num_bps = 1;
  487. for (i = 0; i < CAM_ICP_DEV_TYPE_MAX; i++) {
  488. query_cmd->dev_ver[i].dev_type = i;
  489. query_cmd->dev_ver[i].hw_ver.major = 0x34 + i;
  490. query_cmd->dev_ver[i].hw_ver.minor = 0x34 + i;
  491. query_cmd->dev_ver[i].hw_ver.incr = 0x34 + i;
  492. }
  493. return 0;
  494. }
  495. int cam_hfi_resume(struct hfi_mem_info *hfi_mem)
  496. {
  497. int rc = 0;
  498. uint32_t fw_version, status = 0;
  499. void __iomem *icp_base = hfi_iface_addr(g_hfi);
  500. if (!icp_base) {
  501. CAM_ERR(CAM_HFI, "invalid HFI interface address");
  502. return -EINVAL;
  503. }
  504. if (cam_common_read_poll_timeout(icp_base +
  505. HFI_REG_ICP_HOST_INIT_RESPONSE,
  506. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
  507. 0x1, ICP_INIT_RESP_SUCCESS, &status)) {
  508. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  509. status);
  510. return -ETIMEDOUT;
  511. }
  512. hfi_irq_enable(g_hfi);
  513. fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION);
  514. CAM_DBG(CAM_HFI, "fw version : [%x]", fw_version);
  515. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova, icp_base + HFI_REG_QTBL_PTR);
  516. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  517. icp_base + HFI_REG_SFR_PTR);
  518. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  519. icp_base + HFI_REG_SHARED_MEM_PTR);
  520. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  521. icp_base + HFI_REG_SHARED_MEM_SIZE);
  522. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  523. icp_base + HFI_REG_SECONDARY_HEAP_PTR);
  524. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  525. icp_base + HFI_REG_SECONDARY_HEAP_SIZE);
  526. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  527. icp_base + HFI_REG_QDSS_IOVA);
  528. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  529. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  530. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  531. icp_base + HFI_REG_IO_REGION_IOVA);
  532. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  533. icp_base + HFI_REG_IO_REGION_SIZE);
  534. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  535. icp_base + HFI_REG_IO2_REGION_IOVA);
  536. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  537. icp_base + HFI_REG_IO2_REGION_SIZE);
  538. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.iova,
  539. icp_base + HFI_REG_FWUNCACHED_REGION_IOVA);
  540. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.len,
  541. icp_base + HFI_REG_FWUNCACHED_REGION_SIZE);
  542. CAM_DBG(CAM_HFI, "IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  543. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  544. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  545. CAM_DBG(CAM_HFI, "FwUncached : [0x%x 0x%x] Shared [0x%x 0x%x]",
  546. hfi_mem->fw_uncached.iova, hfi_mem->fw_uncached.len,
  547. hfi_mem->shmem.iova, hfi_mem->shmem.len);
  548. CAM_DBG(CAM_HFI, "SecHeap : [0x%x 0x%x] QDSS [0x%x 0x%x]",
  549. hfi_mem->sec_heap.iova, hfi_mem->sec_heap.len,
  550. hfi_mem->qdss.iova, hfi_mem->qdss.len);
  551. CAM_DBG(CAM_HFI, "QTbl : [0x%x 0x%x] Sfr [0x%x 0x%x]",
  552. hfi_mem->qtbl.iova, hfi_mem->qtbl.len,
  553. hfi_mem->sfr_buf.iova, hfi_mem->sfr_buf.len);
  554. return rc;
  555. }
  556. int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
  557. void *priv, uint8_t event_driven_mode)
  558. {
  559. int rc = 0;
  560. uint32_t status = 0;
  561. struct hfi_qtbl *qtbl;
  562. struct hfi_qtbl_hdr *qtbl_hdr;
  563. struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr, *dbg_q_hdr;
  564. struct sfr_buf *sfr_buffer;
  565. void __iomem *icp_base;
  566. if (!hfi_mem || !hfi_ops || !priv) {
  567. CAM_ERR(CAM_HFI,
  568. "invalid arg: hfi_mem=%pK hfi_ops=%pK priv=%pK",
  569. hfi_mem, hfi_ops, priv);
  570. return -EINVAL;
  571. }
  572. mutex_lock(&hfi_cmd_q_mutex);
  573. mutex_lock(&hfi_msg_q_mutex);
  574. if (!g_hfi) {
  575. g_hfi = kzalloc(sizeof(struct hfi_info), GFP_KERNEL);
  576. if (!g_hfi) {
  577. rc = -ENOMEM;
  578. goto alloc_fail;
  579. }
  580. }
  581. if (g_hfi->hfi_state != HFI_DEINIT) {
  582. CAM_ERR(CAM_HFI, "hfi_init: invalid state");
  583. rc = -EINVAL;
  584. goto regions_fail;
  585. }
  586. memcpy(&g_hfi->map, hfi_mem, sizeof(g_hfi->map));
  587. g_hfi->hfi_state = HFI_DEINIT;
  588. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  589. qtbl_hdr = &qtbl->q_tbl_hdr;
  590. qtbl_hdr->qtbl_version = 0xFFFFFFFF;
  591. qtbl_hdr->qtbl_size = sizeof(struct hfi_qtbl);
  592. qtbl_hdr->qtbl_qhdr0_offset = sizeof(struct hfi_qtbl_hdr);
  593. qtbl_hdr->qtbl_qhdr_size = sizeof(struct hfi_q_hdr);
  594. qtbl_hdr->qtbl_num_q = ICP_HFI_NUMBER_OF_QS;
  595. qtbl_hdr->qtbl_num_active_q = ICP_HFI_NUMBER_OF_QS;
  596. /* setup host-to-firmware command queue */
  597. cmd_q_hdr = &qtbl->q_hdr[Q_CMD];
  598. cmd_q_hdr->qhdr_status = QHDR_ACTIVE;
  599. cmd_q_hdr->qhdr_start_addr = hfi_mem->cmd_q.iova;
  600. cmd_q_hdr->qhdr_q_size = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  601. cmd_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  602. cmd_q_hdr->qhdr_pkt_drop_cnt = RESET;
  603. cmd_q_hdr->qhdr_read_idx = RESET;
  604. cmd_q_hdr->qhdr_write_idx = RESET;
  605. /* setup firmware-to-Host message queue */
  606. msg_q_hdr = &qtbl->q_hdr[Q_MSG];
  607. msg_q_hdr->qhdr_status = QHDR_ACTIVE;
  608. msg_q_hdr->qhdr_start_addr = hfi_mem->msg_q.iova;
  609. msg_q_hdr->qhdr_q_size = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  610. msg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  611. msg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  612. msg_q_hdr->qhdr_read_idx = RESET;
  613. msg_q_hdr->qhdr_write_idx = RESET;
  614. /* setup firmware-to-Host message queue */
  615. dbg_q_hdr = &qtbl->q_hdr[Q_DBG];
  616. dbg_q_hdr->qhdr_status = QHDR_ACTIVE;
  617. dbg_q_hdr->qhdr_start_addr = hfi_mem->dbg_q.iova;
  618. dbg_q_hdr->qhdr_q_size = ICP_DBG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  619. dbg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  620. dbg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  621. dbg_q_hdr->qhdr_read_idx = RESET;
  622. dbg_q_hdr->qhdr_write_idx = RESET;
  623. sfr_buffer = (struct sfr_buf *)hfi_mem->sfr_buf.kva;
  624. sfr_buffer->size = ICP_MSG_SFR_SIZE_IN_BYTES;
  625. switch (event_driven_mode) {
  626. case INTR_MODE:
  627. cmd_q_hdr->qhdr_type = Q_CMD;
  628. cmd_q_hdr->qhdr_rx_wm = SET;
  629. cmd_q_hdr->qhdr_tx_wm = SET;
  630. cmd_q_hdr->qhdr_rx_req = SET;
  631. cmd_q_hdr->qhdr_tx_req = RESET;
  632. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  633. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  634. msg_q_hdr->qhdr_type = Q_MSG;
  635. msg_q_hdr->qhdr_rx_wm = SET;
  636. msg_q_hdr->qhdr_tx_wm = SET;
  637. msg_q_hdr->qhdr_rx_req = SET;
  638. msg_q_hdr->qhdr_tx_req = RESET;
  639. msg_q_hdr->qhdr_rx_irq_status = RESET;
  640. msg_q_hdr->qhdr_tx_irq_status = RESET;
  641. dbg_q_hdr->qhdr_type = Q_DBG;
  642. dbg_q_hdr->qhdr_rx_wm = SET;
  643. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  644. dbg_q_hdr->qhdr_rx_req = RESET;
  645. dbg_q_hdr->qhdr_tx_req = RESET;
  646. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  647. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  648. break;
  649. case POLL_MODE:
  650. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_POLL_MODE_2 |
  651. RX_EVENT_POLL_MODE_2;
  652. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_POLL_MODE_2 |
  653. RX_EVENT_POLL_MODE_2;
  654. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_POLL_MODE_2 |
  655. RX_EVENT_POLL_MODE_2;
  656. break;
  657. case WM_MODE:
  658. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_DRIVEN_MODE_2 |
  659. RX_EVENT_DRIVEN_MODE_2;
  660. cmd_q_hdr->qhdr_rx_wm = SET;
  661. cmd_q_hdr->qhdr_tx_wm = SET;
  662. cmd_q_hdr->qhdr_rx_req = RESET;
  663. cmd_q_hdr->qhdr_tx_req = SET;
  664. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  665. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  666. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_DRIVEN_MODE_2 |
  667. RX_EVENT_DRIVEN_MODE_2;
  668. msg_q_hdr->qhdr_rx_wm = SET;
  669. msg_q_hdr->qhdr_tx_wm = SET;
  670. msg_q_hdr->qhdr_rx_req = SET;
  671. msg_q_hdr->qhdr_tx_req = RESET;
  672. msg_q_hdr->qhdr_rx_irq_status = RESET;
  673. msg_q_hdr->qhdr_tx_irq_status = RESET;
  674. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_DRIVEN_MODE_2 |
  675. RX_EVENT_DRIVEN_MODE_2;
  676. dbg_q_hdr->qhdr_rx_wm = SET;
  677. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  678. dbg_q_hdr->qhdr_rx_req = RESET;
  679. dbg_q_hdr->qhdr_tx_req = RESET;
  680. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  681. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  682. break;
  683. default:
  684. CAM_ERR(CAM_HFI, "Invalid event driven mode :%u",
  685. event_driven_mode);
  686. break;
  687. }
  688. g_hfi->ops = *hfi_ops;
  689. g_hfi->priv = priv;
  690. icp_base = hfi_iface_addr(g_hfi);
  691. if (!icp_base) {
  692. CAM_ERR(CAM_HFI, "invalid HFI interface address");
  693. rc = -EINVAL;
  694. goto regions_fail;
  695. }
  696. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova,
  697. icp_base + HFI_REG_QTBL_PTR);
  698. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  699. icp_base + HFI_REG_SFR_PTR);
  700. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  701. icp_base + HFI_REG_SHARED_MEM_PTR);
  702. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  703. icp_base + HFI_REG_SHARED_MEM_SIZE);
  704. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  705. icp_base + HFI_REG_SECONDARY_HEAP_PTR);
  706. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  707. icp_base + HFI_REG_SECONDARY_HEAP_SIZE);
  708. cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET,
  709. icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
  710. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  711. icp_base + HFI_REG_QDSS_IOVA);
  712. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  713. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  714. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  715. icp_base + HFI_REG_IO_REGION_IOVA);
  716. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  717. icp_base + HFI_REG_IO_REGION_SIZE);
  718. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  719. icp_base + HFI_REG_IO2_REGION_IOVA);
  720. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  721. icp_base + HFI_REG_IO2_REGION_SIZE);
  722. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.iova,
  723. icp_base + HFI_REG_FWUNCACHED_REGION_IOVA);
  724. cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.len,
  725. icp_base + HFI_REG_FWUNCACHED_REGION_SIZE);
  726. CAM_DBG(CAM_HFI, "IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  727. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  728. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  729. CAM_DBG(CAM_HFI, "FwUncached : [0x%x 0x%x] Shared [0x%x 0x%x]",
  730. hfi_mem->fw_uncached.iova, hfi_mem->fw_uncached.len,
  731. hfi_mem->shmem.iova, hfi_mem->shmem.len);
  732. CAM_DBG(CAM_HFI, "SecHeap : [0x%x 0x%x] QDSS [0x%x 0x%x]",
  733. hfi_mem->sec_heap.iova, hfi_mem->sec_heap.len,
  734. hfi_mem->qdss.iova, hfi_mem->qdss.len);
  735. CAM_DBG(CAM_HFI, "QTbl : [0x%x 0x%x] Sfr [0x%x 0x%x]",
  736. hfi_mem->qtbl.iova, hfi_mem->qtbl.len,
  737. hfi_mem->sfr_buf.iova, hfi_mem->sfr_buf.len);
  738. if (cam_common_read_poll_timeout(icp_base +
  739. HFI_REG_ICP_HOST_INIT_RESPONSE,
  740. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
  741. 0x1, ICP_INIT_RESP_SUCCESS, &status)) {
  742. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  743. status);
  744. rc = -ETIMEDOUT;
  745. goto regions_fail;
  746. }
  747. CAM_DBG(CAM_HFI, "ICP fw version: 0x%x",
  748. cam_io_r(icp_base + HFI_REG_FW_VERSION));
  749. g_hfi->hfi_state = HFI_READY;
  750. g_hfi->cmd_q_state = true;
  751. g_hfi->msg_q_state = true;
  752. hfi_irq_enable(g_hfi);
  753. mutex_unlock(&hfi_cmd_q_mutex);
  754. mutex_unlock(&hfi_msg_q_mutex);
  755. return rc;
  756. regions_fail:
  757. kfree(g_hfi);
  758. g_hfi = NULL;
  759. alloc_fail:
  760. mutex_unlock(&hfi_cmd_q_mutex);
  761. mutex_unlock(&hfi_msg_q_mutex);
  762. return rc;
  763. }
  764. void cam_hfi_deinit(void)
  765. {
  766. mutex_lock(&hfi_cmd_q_mutex);
  767. mutex_lock(&hfi_msg_q_mutex);
  768. if (!g_hfi) {
  769. CAM_ERR(CAM_HFI, "hfi path not established yet");
  770. goto err;
  771. }
  772. g_hfi->cmd_q_state = false;
  773. g_hfi->msg_q_state = false;
  774. cam_free_clear((void *)g_hfi);
  775. g_hfi = NULL;
  776. err:
  777. mutex_unlock(&hfi_cmd_q_mutex);
  778. mutex_unlock(&hfi_msg_q_mutex);
  779. }