hif.h 65 KB

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  1. /*
  2. * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HIF_H_
  20. #define _HIF_H_
  21. #ifdef __cplusplus
  22. extern "C" {
  23. #endif /* __cplusplus */
  24. /* Header files */
  25. #include <qdf_status.h>
  26. #include "qdf_nbuf.h"
  27. #include "qdf_lro.h"
  28. #include "ol_if_athvar.h"
  29. #include <linux/platform_device.h>
  30. #ifdef HIF_PCI
  31. #include <linux/pci.h>
  32. #endif /* HIF_PCI */
  33. #ifdef HIF_USB
  34. #include <linux/usb.h>
  35. #endif /* HIF_USB */
  36. #ifdef IPA_OFFLOAD
  37. #include <linux/ipa.h>
  38. #endif
  39. #include "cfg_ucfg_api.h"
  40. #include "qdf_dev.h"
  41. #include <wlan_init_cfg.h>
  42. #define ENABLE_MBOX_DUMMY_SPACE_FEATURE 1
  43. typedef void __iomem *A_target_id_t;
  44. typedef void *hif_handle_t;
  45. #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE)
  46. #define HIF_WORK_DRAIN_WAIT_CNT 50
  47. #define HIF_EP_WAKE_RESET_WAIT_CNT 10
  48. #endif
  49. #define HIF_TYPE_AR6002 2
  50. #define HIF_TYPE_AR6003 3
  51. #define HIF_TYPE_AR6004 5
  52. #define HIF_TYPE_AR9888 6
  53. #define HIF_TYPE_AR6320 7
  54. #define HIF_TYPE_AR6320V2 8
  55. /* For attaching Peregrine 2.0 board host_reg_tbl only */
  56. #define HIF_TYPE_AR9888V2 9
  57. #define HIF_TYPE_ADRASTEA 10
  58. #define HIF_TYPE_AR900B 11
  59. #define HIF_TYPE_QCA9984 12
  60. #define HIF_TYPE_IPQ4019 13
  61. #define HIF_TYPE_QCA9888 14
  62. #define HIF_TYPE_QCA8074 15
  63. #define HIF_TYPE_QCA6290 16
  64. #define HIF_TYPE_QCN7605 17
  65. #define HIF_TYPE_QCA6390 18
  66. #define HIF_TYPE_QCA8074V2 19
  67. #define HIF_TYPE_QCA6018 20
  68. #define HIF_TYPE_QCN9000 21
  69. #define HIF_TYPE_QCA6490 22
  70. #define HIF_TYPE_QCA6750 23
  71. #define HIF_TYPE_QCA5018 24
  72. #define HIF_TYPE_QCN6122 25
  73. #define HIF_TYPE_KIWI 26
  74. #define HIF_TYPE_QCN9224 27
  75. #define HIF_TYPE_QCA9574 28
  76. #define DMA_COHERENT_MASK_DEFAULT 37
  77. #ifdef IPA_OFFLOAD
  78. #define DMA_COHERENT_MASK_BELOW_IPA_VER_3 32
  79. #endif
  80. /* enum hif_ic_irq - enum defining integrated chip irq numbers
  81. * defining irq nubers that can be used by external modules like datapath
  82. */
  83. enum hif_ic_irq {
  84. host2wbm_desc_feed = 16,
  85. host2reo_re_injection,
  86. host2reo_command,
  87. host2rxdma_monitor_ring3,
  88. host2rxdma_monitor_ring2,
  89. host2rxdma_monitor_ring1,
  90. reo2host_exception,
  91. wbm2host_rx_release,
  92. reo2host_status,
  93. reo2host_destination_ring4,
  94. reo2host_destination_ring3,
  95. reo2host_destination_ring2,
  96. reo2host_destination_ring1,
  97. rxdma2host_monitor_destination_mac3,
  98. rxdma2host_monitor_destination_mac2,
  99. rxdma2host_monitor_destination_mac1,
  100. ppdu_end_interrupts_mac3,
  101. ppdu_end_interrupts_mac2,
  102. ppdu_end_interrupts_mac1,
  103. rxdma2host_monitor_status_ring_mac3,
  104. rxdma2host_monitor_status_ring_mac2,
  105. rxdma2host_monitor_status_ring_mac1,
  106. host2rxdma_host_buf_ring_mac3,
  107. host2rxdma_host_buf_ring_mac2,
  108. host2rxdma_host_buf_ring_mac1,
  109. rxdma2host_destination_ring_mac3,
  110. rxdma2host_destination_ring_mac2,
  111. rxdma2host_destination_ring_mac1,
  112. host2tcl_input_ring4,
  113. host2tcl_input_ring3,
  114. host2tcl_input_ring2,
  115. host2tcl_input_ring1,
  116. wbm2host_tx_completions_ring4,
  117. wbm2host_tx_completions_ring3,
  118. wbm2host_tx_completions_ring2,
  119. wbm2host_tx_completions_ring1,
  120. tcl2host_status_ring,
  121. };
  122. struct CE_state;
  123. #ifdef QCA_WIFI_QCN9224
  124. #define CE_COUNT_MAX 16
  125. #else
  126. #define CE_COUNT_MAX 12
  127. #endif
  128. #ifndef HIF_MAX_GROUP
  129. #define HIF_MAX_GROUP WLAN_CFG_INT_NUM_CONTEXTS
  130. #endif
  131. #ifdef CONFIG_BERYLLIUM
  132. #define HIF_MAX_GRP_IRQ 25
  133. #else
  134. #define HIF_MAX_GRP_IRQ 16
  135. #endif
  136. #ifndef NAPI_YIELD_BUDGET_BASED
  137. #ifndef QCA_NAPI_DEF_SCALE_BIN_SHIFT
  138. #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 4
  139. #endif
  140. #else /* NAPI_YIELD_BUDGET_BASED */
  141. #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 2
  142. #endif /* NAPI_YIELD_BUDGET_BASED */
  143. #define QCA_NAPI_BUDGET 64
  144. #define QCA_NAPI_DEF_SCALE \
  145. (1 << QCA_NAPI_DEF_SCALE_BIN_SHIFT)
  146. #define HIF_NAPI_MAX_RECEIVES (QCA_NAPI_BUDGET * QCA_NAPI_DEF_SCALE)
  147. /* NOTE: "napi->scale" can be changed,
  148. * but this does not change the number of buckets
  149. */
  150. #define QCA_NAPI_NUM_BUCKETS 4
  151. /**
  152. * qca_napi_stat - stats structure for execution contexts
  153. * @napi_schedules - number of times the schedule function is called
  154. * @napi_polls - number of times the execution context runs
  155. * @napi_completes - number of times that the generating interrupt is reenabled
  156. * @napi_workdone - cumulative of all work done reported by handler
  157. * @cpu_corrected - incremented when execution context runs on a different core
  158. * than the one that its irq is affined to.
  159. * @napi_budget_uses - histogram of work done per execution run
  160. * @time_limit_reache - count of yields due to time limit threshholds
  161. * @rxpkt_thresh_reached - count of yields due to a work limit
  162. * @poll_time_buckets - histogram of poll times for the napi
  163. *
  164. */
  165. struct qca_napi_stat {
  166. uint32_t napi_schedules;
  167. uint32_t napi_polls;
  168. uint32_t napi_completes;
  169. uint32_t napi_workdone;
  170. uint32_t cpu_corrected;
  171. uint32_t napi_budget_uses[QCA_NAPI_NUM_BUCKETS];
  172. uint32_t time_limit_reached;
  173. uint32_t rxpkt_thresh_reached;
  174. unsigned long long napi_max_poll_time;
  175. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  176. uint32_t poll_time_buckets[QCA_NAPI_NUM_BUCKETS];
  177. #endif
  178. };
  179. /**
  180. * per NAPI instance data structure
  181. * This data structure holds stuff per NAPI instance.
  182. * Note that, in the current implementation, though scale is
  183. * an instance variable, it is set to the same value for all
  184. * instances.
  185. */
  186. struct qca_napi_info {
  187. struct net_device netdev; /* dummy net_dev */
  188. void *hif_ctx;
  189. struct napi_struct napi;
  190. uint8_t scale; /* currently same on all instances */
  191. uint8_t id;
  192. uint8_t cpu;
  193. int irq;
  194. cpumask_t cpumask;
  195. struct qca_napi_stat stats[NR_CPUS];
  196. #ifdef RECEIVE_OFFLOAD
  197. /* will only be present for data rx CE's */
  198. void (*offld_flush_cb)(void *);
  199. struct napi_struct rx_thread_napi;
  200. struct net_device rx_thread_netdev;
  201. #endif /* RECEIVE_OFFLOAD */
  202. qdf_lro_ctx_t lro_ctx;
  203. };
  204. enum qca_napi_tput_state {
  205. QCA_NAPI_TPUT_UNINITIALIZED,
  206. QCA_NAPI_TPUT_LO,
  207. QCA_NAPI_TPUT_HI
  208. };
  209. enum qca_napi_cpu_state {
  210. QCA_NAPI_CPU_UNINITIALIZED,
  211. QCA_NAPI_CPU_DOWN,
  212. QCA_NAPI_CPU_UP };
  213. /**
  214. * struct qca_napi_cpu - an entry of the napi cpu table
  215. * @core_id: physical core id of the core
  216. * @cluster_id: cluster this core belongs to
  217. * @core_mask: mask to match all core of this cluster
  218. * @thread_mask: mask for this core within the cluster
  219. * @max_freq: maximum clock this core can be clocked at
  220. * same for all cpus of the same core.
  221. * @napis: bitmap of napi instances on this core
  222. * @execs: bitmap of execution contexts on this core
  223. * cluster_nxt: chain to link cores within the same cluster
  224. *
  225. * This structure represents a single entry in the napi cpu
  226. * table. The table is part of struct qca_napi_data.
  227. * This table is initialized by the init function, called while
  228. * the first napi instance is being created, updated by hotplug
  229. * notifier and when cpu affinity decisions are made (by throughput
  230. * detection), and deleted when the last napi instance is removed.
  231. */
  232. struct qca_napi_cpu {
  233. enum qca_napi_cpu_state state;
  234. int core_id;
  235. int cluster_id;
  236. cpumask_t core_mask;
  237. cpumask_t thread_mask;
  238. unsigned int max_freq;
  239. uint32_t napis;
  240. uint32_t execs;
  241. int cluster_nxt; /* index, not pointer */
  242. };
  243. /**
  244. * struct qca_napi_data - collection of napi data for a single hif context
  245. * @hif_softc: pointer to the hif context
  246. * @lock: spinlock used in the event state machine
  247. * @state: state variable used in the napi stat machine
  248. * @ce_map: bit map indicating which ce's have napis running
  249. * @exec_map: bit map of instanciated exec contexts
  250. * @user_cpu_affin_map: CPU affinity map from INI config.
  251. * @napi_cpu: cpu info for irq affinty
  252. * @lilcl_head:
  253. * @bigcl_head:
  254. * @napi_mode: irq affinity & clock voting mode
  255. * @cpuhp_handler: CPU hotplug event registration handle
  256. */
  257. struct qca_napi_data {
  258. struct hif_softc *hif_softc;
  259. qdf_spinlock_t lock;
  260. uint32_t state;
  261. /* bitmap of created/registered NAPI instances, indexed by pipe_id,
  262. * not used by clients (clients use an id returned by create)
  263. */
  264. uint32_t ce_map;
  265. uint32_t exec_map;
  266. uint32_t user_cpu_affin_mask;
  267. struct qca_napi_info *napis[CE_COUNT_MAX];
  268. struct qca_napi_cpu napi_cpu[NR_CPUS];
  269. int lilcl_head, bigcl_head;
  270. enum qca_napi_tput_state napi_mode;
  271. struct qdf_cpuhp_handler *cpuhp_handler;
  272. uint8_t flags;
  273. };
  274. /**
  275. * struct hif_config_info - Place Holder for HIF configuration
  276. * @enable_self_recovery: Self Recovery
  277. * @enable_runtime_pm: Enable Runtime PM
  278. * @runtime_pm_delay: Runtime PM Delay
  279. * @rx_softirq_max_yield_duration_ns: Max Yield time duration for RX Softirq
  280. *
  281. * Structure for holding HIF ini parameters.
  282. */
  283. struct hif_config_info {
  284. bool enable_self_recovery;
  285. #ifdef FEATURE_RUNTIME_PM
  286. uint8_t enable_runtime_pm;
  287. u_int32_t runtime_pm_delay;
  288. #endif
  289. uint64_t rx_softirq_max_yield_duration_ns;
  290. };
  291. /**
  292. * struct hif_target_info - Target Information
  293. * @target_version: Target Version
  294. * @target_type: Target Type
  295. * @target_revision: Target Revision
  296. * @soc_version: SOC Version
  297. * @hw_name: pointer to hardware name
  298. *
  299. * Structure to hold target information.
  300. */
  301. struct hif_target_info {
  302. uint32_t target_version;
  303. uint32_t target_type;
  304. uint32_t target_revision;
  305. uint32_t soc_version;
  306. char *hw_name;
  307. };
  308. struct hif_opaque_softc {
  309. };
  310. /**
  311. * enum hif_event_type - Type of DP events to be recorded
  312. * @HIF_EVENT_IRQ_TRIGGER: IRQ trigger event
  313. * @HIF_EVENT_TIMER_ENTRY: Monitor Timer entry event
  314. * @HIF_EVENT_TIMER_EXIT: Monitor Timer exit event
  315. * @HIF_EVENT_BH_SCHED: NAPI POLL scheduled event
  316. * @HIF_EVENT_SRNG_ACCESS_START: hal ring access start event
  317. * @HIF_EVENT_SRNG_ACCESS_END: hal ring access end event
  318. * @HIF_EVENT_BH_COMPLETE: NAPI POLL completion event
  319. * @HIF_EVENT_BH_FORCE_BREAK: NAPI POLL force break event
  320. */
  321. enum hif_event_type {
  322. HIF_EVENT_IRQ_TRIGGER,
  323. HIF_EVENT_TIMER_ENTRY,
  324. HIF_EVENT_TIMER_EXIT,
  325. HIF_EVENT_BH_SCHED,
  326. HIF_EVENT_SRNG_ACCESS_START,
  327. HIF_EVENT_SRNG_ACCESS_END,
  328. HIF_EVENT_BH_COMPLETE,
  329. HIF_EVENT_BH_FORCE_BREAK,
  330. /* Do check hif_hist_skip_event_record when adding new events */
  331. };
  332. /**
  333. * enum hif_system_pm_state - System PM state
  334. * HIF_SYSTEM_PM_STATE_ON: System in active state
  335. * HIF_SYSTEM_PM_STATE_BUS_RESUMING: bus resume in progress as part of
  336. * system resume
  337. * HIF_SYSTEM_PM_STATE_BUS_SUSPENDING: bus suspend in progress as part of
  338. * system suspend
  339. * HIF_SYSTEM_PM_STATE_BUS_SUSPENDED: bus suspended as part of system suspend
  340. */
  341. enum hif_system_pm_state {
  342. HIF_SYSTEM_PM_STATE_ON,
  343. HIF_SYSTEM_PM_STATE_BUS_RESUMING,
  344. HIF_SYSTEM_PM_STATE_BUS_SUSPENDING,
  345. HIF_SYSTEM_PM_STATE_BUS_SUSPENDED,
  346. };
  347. #ifdef WLAN_FEATURE_DP_EVENT_HISTORY
  348. #define HIF_NUM_INT_CONTEXTS HIF_MAX_GROUP
  349. #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)
  350. /* HIF_EVENT_HIST_MAX should always be power of 2 */
  351. #define HIF_EVENT_HIST_MAX 512
  352. #define HIF_EVENT_HIST_ENABLE_MASK 0xFF
  353. static inline uint64_t hif_get_log_timestamp(void)
  354. {
  355. return qdf_get_log_timestamp();
  356. }
  357. #else
  358. #define HIF_EVENT_HIST_MAX 32
  359. /* Enable IRQ TRIGGER, NAPI SCHEDULE, SRNG ACCESS START */
  360. #define HIF_EVENT_HIST_ENABLE_MASK 0x19
  361. static inline uint64_t hif_get_log_timestamp(void)
  362. {
  363. return qdf_sched_clock();
  364. }
  365. #endif
  366. /**
  367. * struct hif_event_record - an entry of the DP event history
  368. * @hal_ring_id: ring id for which event is recorded
  369. * @hp: head pointer of the ring (may not be applicable for all events)
  370. * @tp: tail pointer of the ring (may not be applicable for all events)
  371. * @cpu_id: cpu id on which the event occurred
  372. * @timestamp: timestamp when event occurred
  373. * @type: type of the event
  374. *
  375. * This structure represents the information stored for every datapath
  376. * event which is logged in the history.
  377. */
  378. struct hif_event_record {
  379. uint8_t hal_ring_id;
  380. uint32_t hp;
  381. uint32_t tp;
  382. int cpu_id;
  383. uint64_t timestamp;
  384. enum hif_event_type type;
  385. };
  386. /**
  387. * struct hif_event_misc - history related misc info
  388. * @last_irq_index: last irq event index in history
  389. * @last_irq_ts: last irq timestamp
  390. */
  391. struct hif_event_misc {
  392. int32_t last_irq_index;
  393. uint64_t last_irq_ts;
  394. };
  395. /**
  396. * struct hif_event_history - history for one interrupt group
  397. * @index: index to store new event
  398. * @event: event entry
  399. *
  400. * This structure represents the datapath history for one
  401. * interrupt group.
  402. */
  403. struct hif_event_history {
  404. qdf_atomic_t index;
  405. struct hif_event_misc misc;
  406. struct hif_event_record event[HIF_EVENT_HIST_MAX];
  407. };
  408. /**
  409. * hif_hist_record_event() - Record one datapath event in history
  410. * @hif_ctx: HIF opaque context
  411. * @event: DP event entry
  412. * @intr_grp_id: interrupt group ID registered with hif
  413. *
  414. * Return: None
  415. */
  416. void hif_hist_record_event(struct hif_opaque_softc *hif_ctx,
  417. struct hif_event_record *event,
  418. uint8_t intr_grp_id);
  419. /**
  420. * hif_event_history_init() - Initialize SRNG event history buffers
  421. * @hif_ctx: HIF opaque context
  422. * @id: context group ID for which history is recorded
  423. *
  424. * Returns: None
  425. */
  426. void hif_event_history_init(struct hif_opaque_softc *hif_ctx, uint8_t id);
  427. /**
  428. * hif_event_history_deinit() - De-initialize SRNG event history buffers
  429. * @hif_ctx: HIF opaque context
  430. * @id: context group ID for which history is recorded
  431. *
  432. * Returns: None
  433. */
  434. void hif_event_history_deinit(struct hif_opaque_softc *hif_ctx, uint8_t id);
  435. /**
  436. * hif_record_event() - Wrapper function to form and record DP event
  437. * @hif_ctx: HIF opaque context
  438. * @intr_grp_id: interrupt group ID registered with hif
  439. * @hal_ring_id: ring id for which event is recorded
  440. * @hp: head pointer index of the srng
  441. * @tp: tail pointer index of the srng
  442. * @type: type of the event to be logged in history
  443. *
  444. * Return: None
  445. */
  446. static inline void hif_record_event(struct hif_opaque_softc *hif_ctx,
  447. uint8_t intr_grp_id,
  448. uint8_t hal_ring_id,
  449. uint32_t hp,
  450. uint32_t tp,
  451. enum hif_event_type type)
  452. {
  453. struct hif_event_record event;
  454. event.hal_ring_id = hal_ring_id;
  455. event.hp = hp;
  456. event.tp = tp;
  457. event.type = type;
  458. hif_hist_record_event(hif_ctx, &event, intr_grp_id);
  459. return;
  460. }
  461. #else
  462. static inline void hif_record_event(struct hif_opaque_softc *hif_ctx,
  463. uint8_t intr_grp_id,
  464. uint8_t hal_ring_id,
  465. uint32_t hp,
  466. uint32_t tp,
  467. enum hif_event_type type)
  468. {
  469. }
  470. static inline void hif_event_history_init(struct hif_opaque_softc *hif_ctx,
  471. uint8_t id)
  472. {
  473. }
  474. static inline void hif_event_history_deinit(struct hif_opaque_softc *hif_ctx,
  475. uint8_t id)
  476. {
  477. }
  478. #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */
  479. /**
  480. * enum HIF_DEVICE_POWER_CHANGE_TYPE: Device Power change type
  481. *
  482. * @HIF_DEVICE_POWER_UP: HIF layer should power up interface and/or module
  483. * @HIF_DEVICE_POWER_DOWN: HIF layer should initiate bus-specific measures to
  484. * minimize power
  485. * @HIF_DEVICE_POWER_CUT: HIF layer should initiate bus-specific AND/OR
  486. * platform-specific measures to completely power-off
  487. * the module and associated hardware (i.e. cut power
  488. * supplies)
  489. */
  490. enum HIF_DEVICE_POWER_CHANGE_TYPE {
  491. HIF_DEVICE_POWER_UP,
  492. HIF_DEVICE_POWER_DOWN,
  493. HIF_DEVICE_POWER_CUT
  494. };
  495. /**
  496. * enum hif_enable_type: what triggered the enabling of hif
  497. *
  498. * @HIF_ENABLE_TYPE_PROBE: probe triggered enable
  499. * @HIF_ENABLE_TYPE_REINIT: reinit triggered enable
  500. */
  501. enum hif_enable_type {
  502. HIF_ENABLE_TYPE_PROBE,
  503. HIF_ENABLE_TYPE_REINIT,
  504. HIF_ENABLE_TYPE_MAX
  505. };
  506. /**
  507. * enum hif_disable_type: what triggered the disabling of hif
  508. *
  509. * @HIF_DISABLE_TYPE_PROBE_ERROR: probe error triggered disable
  510. * @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered disable
  511. * @HIF_DISABLE_TYPE_REMOVE: remove triggered disable
  512. * @HIF_DISABLE_TYPE_SHUTDOWN: shutdown triggered disable
  513. */
  514. enum hif_disable_type {
  515. HIF_DISABLE_TYPE_PROBE_ERROR,
  516. HIF_DISABLE_TYPE_REINIT_ERROR,
  517. HIF_DISABLE_TYPE_REMOVE,
  518. HIF_DISABLE_TYPE_SHUTDOWN,
  519. HIF_DISABLE_TYPE_MAX
  520. };
  521. /**
  522. * enum hif_device_config_opcode: configure mode
  523. *
  524. * @HIF_DEVICE_POWER_STATE: device power state
  525. * @HIF_DEVICE_GET_BLOCK_SIZE: get block size
  526. * @HIF_DEVICE_GET_ADDR: get block address
  527. * @HIF_DEVICE_GET_PENDING_EVENTS_FUNC: get pending events functions
  528. * @HIF_DEVICE_GET_IRQ_PROC_MODE: get irq proc mode
  529. * @HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC: receive event function
  530. * @HIF_DEVICE_POWER_STATE_CHANGE: change power state
  531. * @HIF_DEVICE_GET_IRQ_YIELD_PARAMS: get yield params
  532. * @HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT: configure scatter request
  533. * @HIF_DEVICE_GET_OS_DEVICE: get OS device
  534. * @HIF_DEVICE_DEBUG_BUS_STATE: debug bus state
  535. * @HIF_BMI_DONE: bmi done
  536. * @HIF_DEVICE_SET_TARGET_TYPE: set target type
  537. * @HIF_DEVICE_SET_HTC_CONTEXT: set htc context
  538. * @HIF_DEVICE_GET_HTC_CONTEXT: get htc context
  539. */
  540. enum hif_device_config_opcode {
  541. HIF_DEVICE_POWER_STATE = 0,
  542. HIF_DEVICE_GET_BLOCK_SIZE,
  543. HIF_DEVICE_GET_FIFO_ADDR,
  544. HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
  545. HIF_DEVICE_GET_IRQ_PROC_MODE,
  546. HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
  547. HIF_DEVICE_POWER_STATE_CHANGE,
  548. HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
  549. HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
  550. HIF_DEVICE_GET_OS_DEVICE,
  551. HIF_DEVICE_DEBUG_BUS_STATE,
  552. HIF_BMI_DONE,
  553. HIF_DEVICE_SET_TARGET_TYPE,
  554. HIF_DEVICE_SET_HTC_CONTEXT,
  555. HIF_DEVICE_GET_HTC_CONTEXT,
  556. };
  557. #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
  558. struct HID_ACCESS_LOG {
  559. uint32_t seqnum;
  560. bool is_write;
  561. void *addr;
  562. uint32_t value;
  563. };
  564. #endif
  565. void hif_reg_write(struct hif_opaque_softc *hif_ctx, uint32_t offset,
  566. uint32_t value);
  567. uint32_t hif_reg_read(struct hif_opaque_softc *hif_ctx, uint32_t offset);
  568. #define HIF_MAX_DEVICES 1
  569. /**
  570. * struct htc_callbacks - Structure for HTC Callbacks methods
  571. * @context: context to pass to the dsrhandler
  572. * note : rwCompletionHandler is provided the context
  573. * passed to hif_read_write
  574. * @rwCompletionHandler: Read / write completion handler
  575. * @dsrHandler: DSR Handler
  576. */
  577. struct htc_callbacks {
  578. void *context;
  579. QDF_STATUS(*rw_compl_handler)(void *rw_ctx, QDF_STATUS status);
  580. QDF_STATUS(*dsr_handler)(void *context);
  581. };
  582. /**
  583. * struct hif_driver_state_callbacks - Callbacks for HIF to query Driver state
  584. * @context: Private data context
  585. * @set_recovery_in_progress: To Set Driver state for recovery in progress
  586. * @is_recovery_in_progress: Query if driver state is recovery in progress
  587. * @is_load_unload_in_progress: Query if driver state Load/Unload in Progress
  588. * @is_driver_unloading: Query if driver is unloading.
  589. * @get_bandwidth_level: Query current bandwidth level for the driver
  590. * @prealloc_get_consistent_mem_unligned: get prealloc unaligned consistent mem
  591. * @prealloc_put_consistent_mem_unligned: put unaligned consistent mem to pool
  592. * This Structure provides callback pointer for HIF to query hdd for driver
  593. * states.
  594. */
  595. struct hif_driver_state_callbacks {
  596. void *context;
  597. void (*set_recovery_in_progress)(void *context, uint8_t val);
  598. bool (*is_recovery_in_progress)(void *context);
  599. bool (*is_load_unload_in_progress)(void *context);
  600. bool (*is_driver_unloading)(void *context);
  601. bool (*is_target_ready)(void *context);
  602. int (*get_bandwidth_level)(void *context);
  603. void *(*prealloc_get_consistent_mem_unaligned)(qdf_size_t size,
  604. qdf_dma_addr_t *paddr,
  605. uint32_t ring_type);
  606. void (*prealloc_put_consistent_mem_unaligned)(void *vaddr);
  607. };
  608. /* This API detaches the HTC layer from the HIF device */
  609. void hif_detach_htc(struct hif_opaque_softc *hif_ctx);
  610. /****************************************************************/
  611. /* BMI and Diag window abstraction */
  612. /****************************************************************/
  613. #define HIF_BMI_EXCHANGE_NO_TIMEOUT ((uint32_t)(0))
  614. #define DIAG_TRANSFER_LIMIT 2048U /* maximum number of bytes that can be
  615. * handled atomically by
  616. * DiagRead/DiagWrite
  617. */
  618. #ifdef WLAN_FEATURE_BMI
  619. /*
  620. * API to handle HIF-specific BMI message exchanges, this API is synchronous
  621. * and only allowed to be called from a context that can block (sleep)
  622. */
  623. QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *hif_ctx,
  624. qdf_dma_addr_t cmd, qdf_dma_addr_t rsp,
  625. uint8_t *pSendMessage, uint32_t Length,
  626. uint8_t *pResponseMessage,
  627. uint32_t *pResponseLength, uint32_t TimeoutMS);
  628. void hif_register_bmi_callbacks(struct hif_opaque_softc *hif_ctx);
  629. bool hif_needs_bmi(struct hif_opaque_softc *hif_ctx);
  630. #else /* WLAN_FEATURE_BMI */
  631. static inline void
  632. hif_register_bmi_callbacks(struct hif_opaque_softc *hif_ctx)
  633. {
  634. }
  635. static inline bool
  636. hif_needs_bmi(struct hif_opaque_softc *hif_ctx)
  637. {
  638. return false;
  639. }
  640. #endif /* WLAN_FEATURE_BMI */
  641. #ifdef HIF_CPU_CLEAR_AFFINITY
  642. /**
  643. * hif_config_irq_clear_cpu_affinity() - Remove cpu affinity of IRQ
  644. * @scn: HIF handle
  645. * @intr_ctxt_id: interrupt group index
  646. * @cpu: CPU core to clear
  647. *
  648. * Return: None
  649. */
  650. void hif_config_irq_clear_cpu_affinity(struct hif_opaque_softc *scn,
  651. int intr_ctxt_id, int cpu);
  652. #else
  653. static inline
  654. void hif_config_irq_clear_cpu_affinity(struct hif_opaque_softc *scn,
  655. int intr_ctxt_id, int cpu)
  656. {
  657. }
  658. #endif
  659. /*
  660. * APIs to handle HIF specific diagnostic read accesses. These APIs are
  661. * synchronous and only allowed to be called from a context that
  662. * can block (sleep). They are not high performance APIs.
  663. *
  664. * hif_diag_read_access reads a 4 Byte aligned/length value from a
  665. * Target register or memory word.
  666. *
  667. * hif_diag_read_mem reads an arbitrary length of arbitrarily aligned memory.
  668. */
  669. QDF_STATUS hif_diag_read_access(struct hif_opaque_softc *hif_ctx,
  670. uint32_t address, uint32_t *data);
  671. QDF_STATUS hif_diag_read_mem(struct hif_opaque_softc *hif_ctx, uint32_t address,
  672. uint8_t *data, int nbytes);
  673. void hif_dump_target_memory(struct hif_opaque_softc *hif_ctx,
  674. void *ramdump_base, uint32_t address, uint32_t size);
  675. /*
  676. * APIs to handle HIF specific diagnostic write accesses. These APIs are
  677. * synchronous and only allowed to be called from a context that
  678. * can block (sleep).
  679. * They are not high performance APIs.
  680. *
  681. * hif_diag_write_access writes a 4 Byte aligned/length value to a
  682. * Target register or memory word.
  683. *
  684. * hif_diag_write_mem writes an arbitrary length of arbitrarily aligned memory.
  685. */
  686. QDF_STATUS hif_diag_write_access(struct hif_opaque_softc *hif_ctx,
  687. uint32_t address, uint32_t data);
  688. QDF_STATUS hif_diag_write_mem(struct hif_opaque_softc *hif_ctx,
  689. uint32_t address, uint8_t *data, int nbytes);
  690. typedef void (*fastpath_msg_handler)(void *, qdf_nbuf_t *, uint32_t);
  691. void hif_enable_polled_mode(struct hif_opaque_softc *hif_ctx);
  692. bool hif_is_polled_mode_enabled(struct hif_opaque_softc *hif_ctx);
  693. /*
  694. * Set the FASTPATH_mode_on flag in sc, for use by data path
  695. */
  696. #ifdef WLAN_FEATURE_FASTPATH
  697. void hif_enable_fastpath(struct hif_opaque_softc *hif_ctx);
  698. bool hif_is_fastpath_mode_enabled(struct hif_opaque_softc *hif_ctx);
  699. void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret);
  700. /**
  701. * hif_ce_fastpath_cb_register() - Register callback for fastpath msg handler
  702. * @handler: Callback funtcion
  703. * @context: handle for callback function
  704. *
  705. * Return: QDF_STATUS_SUCCESS on success or QDF_STATUS_E_FAILURE
  706. */
  707. QDF_STATUS hif_ce_fastpath_cb_register(
  708. struct hif_opaque_softc *hif_ctx,
  709. fastpath_msg_handler handler, void *context);
  710. #else
  711. static inline QDF_STATUS hif_ce_fastpath_cb_register(
  712. struct hif_opaque_softc *hif_ctx,
  713. fastpath_msg_handler handler, void *context)
  714. {
  715. return QDF_STATUS_E_FAILURE;
  716. }
  717. static inline void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret)
  718. {
  719. return NULL;
  720. }
  721. #endif
  722. /*
  723. * Enable/disable CDC max performance workaround
  724. * For max-performace set this to 0
  725. * To allow SoC to enter sleep set this to 1
  726. */
  727. #define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0
  728. void hif_ipa_get_ce_resource(struct hif_opaque_softc *hif_ctx,
  729. qdf_shared_mem_t **ce_sr,
  730. uint32_t *ce_sr_ring_size,
  731. qdf_dma_addr_t *ce_reg_paddr);
  732. /**
  733. * @brief List of callbacks - filled in by HTC.
  734. */
  735. struct hif_msg_callbacks {
  736. void *Context;
  737. /**< context meaningful to HTC */
  738. QDF_STATUS (*txCompletionHandler)(void *Context, qdf_nbuf_t wbuf,
  739. uint32_t transferID,
  740. uint32_t toeplitz_hash_result);
  741. QDF_STATUS (*rxCompletionHandler)(void *Context, qdf_nbuf_t wbuf,
  742. uint8_t pipeID);
  743. void (*txResourceAvailHandler)(void *context, uint8_t pipe);
  744. void (*fwEventHandler)(void *context, QDF_STATUS status);
  745. void (*update_bundle_stats)(void *context, uint8_t no_of_pkt_in_bundle);
  746. };
  747. enum hif_target_status {
  748. TARGET_STATUS_CONNECTED = 0, /* target connected */
  749. TARGET_STATUS_RESET, /* target got reset */
  750. TARGET_STATUS_EJECT, /* target got ejected */
  751. TARGET_STATUS_SUSPEND /*target got suspend */
  752. };
  753. /**
  754. * enum hif_attribute_flags: configure hif
  755. *
  756. * @HIF_LOWDESC_CE_CFG: Configure HIF with Low descriptor CE
  757. * @HIF_LOWDESC_CE_NO_PKTLOG_CFG: Configure HIF with Low descriptor
  758. * + No pktlog CE
  759. */
  760. enum hif_attribute_flags {
  761. HIF_LOWDESC_CE_CFG = 1,
  762. HIF_LOWDESC_CE_NO_PKTLOG_CFG
  763. };
  764. #define HIF_DATA_ATTR_SET_TX_CLASSIFY(attr, v) \
  765. (attr |= (v & 0x01) << 5)
  766. #define HIF_DATA_ATTR_SET_ENCAPSULATION_TYPE(attr, v) \
  767. (attr |= (v & 0x03) << 6)
  768. #define HIF_DATA_ATTR_SET_ADDR_X_SEARCH_DISABLE(attr, v) \
  769. (attr |= (v & 0x01) << 13)
  770. #define HIF_DATA_ATTR_SET_ADDR_Y_SEARCH_DISABLE(attr, v) \
  771. (attr |= (v & 0x01) << 14)
  772. #define HIF_DATA_ATTR_SET_TOEPLITZ_HASH_ENABLE(attr, v) \
  773. (attr |= (v & 0x01) << 15)
  774. #define HIF_DATA_ATTR_SET_PACKET_OR_RESULT_OFFSET(attr, v) \
  775. (attr |= (v & 0x0FFF) << 16)
  776. #define HIF_DATA_ATTR_SET_ENABLE_11H(attr, v) \
  777. (attr |= (v & 0x01) << 30)
  778. struct hif_ul_pipe_info {
  779. unsigned int nentries;
  780. unsigned int nentries_mask;
  781. unsigned int sw_index;
  782. unsigned int write_index; /* cached copy */
  783. unsigned int hw_index; /* cached copy */
  784. void *base_addr_owner_space; /* Host address space */
  785. qdf_dma_addr_t base_addr_CE_space; /* CE address space */
  786. };
  787. struct hif_dl_pipe_info {
  788. unsigned int nentries;
  789. unsigned int nentries_mask;
  790. unsigned int sw_index;
  791. unsigned int write_index; /* cached copy */
  792. unsigned int hw_index; /* cached copy */
  793. void *base_addr_owner_space; /* Host address space */
  794. qdf_dma_addr_t base_addr_CE_space; /* CE address space */
  795. };
  796. struct hif_pipe_addl_info {
  797. uint32_t pci_mem;
  798. uint32_t ctrl_addr;
  799. struct hif_ul_pipe_info ul_pipe;
  800. struct hif_dl_pipe_info dl_pipe;
  801. };
  802. #ifdef CONFIG_SLUB_DEBUG_ON
  803. #define MSG_FLUSH_NUM 16
  804. #else /* PERF build */
  805. #define MSG_FLUSH_NUM 32
  806. #endif /* SLUB_DEBUG_ON */
  807. struct hif_bus_id;
  808. void hif_claim_device(struct hif_opaque_softc *hif_ctx);
  809. QDF_STATUS hif_get_config_item(struct hif_opaque_softc *hif_ctx,
  810. int opcode, void *config, uint32_t config_len);
  811. void hif_set_mailbox_swap(struct hif_opaque_softc *hif_ctx);
  812. void hif_mask_interrupt_call(struct hif_opaque_softc *hif_ctx);
  813. void hif_post_init(struct hif_opaque_softc *hif_ctx, void *hHTC,
  814. struct hif_msg_callbacks *callbacks);
  815. QDF_STATUS hif_start(struct hif_opaque_softc *hif_ctx);
  816. void hif_stop(struct hif_opaque_softc *hif_ctx);
  817. void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx);
  818. void hif_dump(struct hif_opaque_softc *hif_ctx, uint8_t CmdId, bool start);
  819. void hif_trigger_dump(struct hif_opaque_softc *hif_ctx,
  820. uint8_t cmd_id, bool start);
  821. QDF_STATUS hif_send_head(struct hif_opaque_softc *hif_ctx, uint8_t PipeID,
  822. uint32_t transferID, uint32_t nbytes,
  823. qdf_nbuf_t wbuf, uint32_t data_attr);
  824. void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t PipeID,
  825. int force);
  826. void hif_shut_down_device(struct hif_opaque_softc *hif_ctx);
  827. void hif_get_default_pipe(struct hif_opaque_softc *hif_ctx, uint8_t *ULPipe,
  828. uint8_t *DLPipe);
  829. int hif_map_service_to_pipe(struct hif_opaque_softc *hif_ctx, uint16_t svc_id,
  830. uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled,
  831. int *dl_is_polled);
  832. uint16_t
  833. hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx, uint8_t PipeID);
  834. void *hif_get_targetdef(struct hif_opaque_softc *hif_ctx);
  835. uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset);
  836. void hif_set_target_sleep(struct hif_opaque_softc *hif_ctx, bool sleep_ok,
  837. bool wait_for_it);
  838. int hif_check_fw_reg(struct hif_opaque_softc *hif_ctx);
  839. #ifndef HIF_PCI
  840. static inline int hif_check_soc_status(struct hif_opaque_softc *hif_ctx)
  841. {
  842. return 0;
  843. }
  844. #else
  845. int hif_check_soc_status(struct hif_opaque_softc *hif_ctx);
  846. #endif
  847. void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version,
  848. u32 *revision, const char **target_name);
  849. #ifdef RECEIVE_OFFLOAD
  850. /**
  851. * hif_offld_flush_cb_register() - Register the offld flush callback
  852. * @scn: HIF opaque context
  853. * @offld_flush_handler: Flush callback is either ol_flush, incase of rx_thread
  854. * Or GRO/LRO flush when RxThread is not enabled. Called
  855. * with corresponding context for flush.
  856. * Return: None
  857. */
  858. void hif_offld_flush_cb_register(struct hif_opaque_softc *scn,
  859. void (offld_flush_handler)(void *ol_ctx));
  860. /**
  861. * hif_offld_flush_cb_deregister() - deRegister the offld flush callback
  862. * @scn: HIF opaque context
  863. *
  864. * Return: None
  865. */
  866. void hif_offld_flush_cb_deregister(struct hif_opaque_softc *scn);
  867. #endif
  868. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  869. /**
  870. * hif_exec_should_yield() - Check if hif napi context should yield
  871. * @hif_ctx - HIF opaque context
  872. * @grp_id - grp_id of the napi for which check needs to be done
  873. *
  874. * The function uses grp_id to look for NAPI and checks if NAPI needs to
  875. * yield. HIF_EXT_GROUP_MAX_YIELD_DURATION_NS is the duration used for
  876. * yield decision.
  877. *
  878. * Return: true if NAPI needs to yield, else false
  879. */
  880. bool hif_exec_should_yield(struct hif_opaque_softc *hif_ctx, uint grp_id);
  881. #else
  882. static inline bool hif_exec_should_yield(struct hif_opaque_softc *hif_ctx,
  883. uint grp_id)
  884. {
  885. return false;
  886. }
  887. #endif
  888. void hif_disable_isr(struct hif_opaque_softc *hif_ctx);
  889. void hif_reset_soc(struct hif_opaque_softc *hif_ctx);
  890. void hif_save_htc_htt_config_endpoint(struct hif_opaque_softc *hif_ctx,
  891. int htc_htt_tx_endpoint);
  892. /**
  893. * hif_open() - Create hif handle
  894. * @qdf_ctx: qdf context
  895. * @mode: Driver Mode
  896. * @bus_type: Bus Type
  897. * @cbk: CDS Callbacks
  898. * @psoc: psoc object manager
  899. *
  900. * API to open HIF Context
  901. *
  902. * Return: HIF Opaque Pointer
  903. */
  904. struct hif_opaque_softc *hif_open(qdf_device_t qdf_ctx,
  905. uint32_t mode,
  906. enum qdf_bus_type bus_type,
  907. struct hif_driver_state_callbacks *cbk,
  908. struct wlan_objmgr_psoc *psoc);
  909. /**
  910. * hif_init_dma_mask() - Set dma mask for the dev
  911. * @dev: dev for which DMA mask is to be set
  912. * @bus_type: bus type for the target
  913. *
  914. * This API sets the DMA mask for the device. before the datapath
  915. * memory pre-allocation is done. If the DMA mask is not set before
  916. * requesting the DMA memory, kernel defaults to a 32-bit DMA mask,
  917. * and does not utilize the full device capability.
  918. *
  919. * Return: 0 - success, non-zero on failure.
  920. */
  921. int hif_init_dma_mask(struct device *dev, enum qdf_bus_type bus_type);
  922. void hif_close(struct hif_opaque_softc *hif_ctx);
  923. QDF_STATUS hif_enable(struct hif_opaque_softc *hif_ctx, struct device *dev,
  924. void *bdev, const struct hif_bus_id *bid,
  925. enum qdf_bus_type bus_type,
  926. enum hif_enable_type type);
  927. void hif_disable(struct hif_opaque_softc *hif_ctx, enum hif_disable_type type);
  928. #ifdef CE_TASKLET_DEBUG_ENABLE
  929. void hif_enable_ce_latency_stats(struct hif_opaque_softc *hif_ctx,
  930. uint8_t value);
  931. #endif
  932. void hif_display_stats(struct hif_opaque_softc *hif_ctx);
  933. void hif_clear_stats(struct hif_opaque_softc *hif_ctx);
  934. /**
  935. * enum hif_pm_wake_irq_type - Wake interrupt type for Power Management
  936. * HIF_PM_INVALID_WAKE: Wake irq is invalid or not configured
  937. * HIF_PM_MSI_WAKE: Wake irq is MSI interrupt
  938. * HIF_PM_CE_WAKE: Wake irq is CE interrupt
  939. */
  940. typedef enum {
  941. HIF_PM_INVALID_WAKE,
  942. HIF_PM_MSI_WAKE,
  943. HIF_PM_CE_WAKE,
  944. } hif_pm_wake_irq_type;
  945. /**
  946. * hif_pm_get_wake_irq_type - Get wake irq type for Power Management
  947. * @hif_ctx: HIF context
  948. *
  949. * Return: enum hif_pm_wake_irq_type
  950. */
  951. hif_pm_wake_irq_type hif_pm_get_wake_irq_type(struct hif_opaque_softc *hif_ctx);
  952. /**
  953. * enum wlan_rtpm_dbgid - runtime pm put/get debug id
  954. * @RTPM_ID_RESVERD: Reserved
  955. * @RTPM_ID_WMI: WMI sending msg, expect put happen at
  956. * tx completion from CE level directly.
  957. * @RTPM_ID_HTC: pkt sending by HTT_DATA_MSG_SVC, expect
  958. * put from fw response or just in
  959. * htc_issue_packets
  960. * @RTPM_ID_QOS_NOTIFY: pm qos notifer
  961. * @RTPM_ID_DP_TX_DESC_ALLOC_FREE: tx desc alloc/free
  962. * @RTPM_ID_CE_SEND_FAST: operation in ce_send_fast, not include
  963. * the pkt put happens outside this function
  964. * @RTPM_ID_SUSPEND_RESUME: suspend/resume in hdd
  965. * @RTPM_ID_DW_TX_HW_ENQUEUE: operation in functin dp_tx_hw_enqueue
  966. * @RTPM_ID_HAL_REO_CMD: HAL_REO_CMD operation
  967. * @RTPM_ID_DP_PRINT_RING_STATS: operation in dp_print_ring_stats
  968. * @RTPM_ID_PM_STOP: operation in hif_pm_runtime_stop
  969. * @RTPM_ID_CONN_DISCONNECT:operation when issue disconnect
  970. * @RTPM_ID_SOC_REMOVE: operation in soc remove
  971. * @RTPM_ID_DRIVER_UNLOAD: operation in driver unload
  972. * @RTPM_ID_CE_INTR_HANDLER: operation from ce interrupt handler
  973. * @RTPM_ID_WAKE_INTR_HANDLER: operation from wake interrupt handler
  974. * @RTPM_ID_SOC_IDLE_SHUTDOWN: operation in soc idle shutdown
  975. */
  976. /* New value added to the enum must also be reflected in function
  977. * rtpm_string_from_dbgid()
  978. */
  979. typedef enum {
  980. RTPM_ID_RESVERD = 0,
  981. RTPM_ID_WMI,
  982. RTPM_ID_HTC,
  983. RTPM_ID_QOS_NOTIFY,
  984. RTPM_ID_DP_TX_DESC_ALLOC_FREE,
  985. RTPM_ID_CE_SEND_FAST,
  986. RTPM_ID_SUSPEND_RESUME,
  987. RTPM_ID_DW_TX_HW_ENQUEUE,
  988. RTPM_ID_HAL_REO_CMD,
  989. RTPM_ID_DP_PRINT_RING_STATS,
  990. RTPM_ID_PM_STOP,
  991. RTPM_ID_CONN_DISCONNECT,
  992. RTPM_ID_SOC_REMOVE,
  993. RTPM_ID_DRIVER_UNLOAD,
  994. RTPM_ID_CE_INTR_HANDLER,
  995. RTPM_ID_WAKE_INTR_HANDLER,
  996. RTPM_ID_SOC_IDLE_SHUTDOWN,
  997. RTPM_ID_MAX,
  998. } wlan_rtpm_dbgid;
  999. /**
  1000. * rtpm_string_from_dbgid() - Convert dbgid to respective string
  1001. * @id - debug id
  1002. *
  1003. * Debug support function to convert dbgid to string.
  1004. * Please note to add new string in the array at index equal to
  1005. * its enum value in wlan_rtpm_dbgid.
  1006. */
  1007. static inline char *rtpm_string_from_dbgid(wlan_rtpm_dbgid id)
  1008. {
  1009. static const char *strings[] = { "RTPM_ID_RESVERD",
  1010. "RTPM_ID_WMI",
  1011. "RTPM_ID_HTC",
  1012. "RTPM_ID_QOS_NOTIFY",
  1013. "RTPM_ID_DP_TX_DESC_ALLOC_FREE",
  1014. "RTPM_ID_CE_SEND_FAST",
  1015. "RTPM_ID_SUSPEND_RESUME",
  1016. "RTPM_ID_DW_TX_HW_ENQUEUE",
  1017. "RTPM_ID_HAL_REO_CMD",
  1018. "RTPM_ID_DP_PRINT_RING_STATS",
  1019. "RTPM_ID_PM_STOP",
  1020. "RTPM_ID_CONN_DISCONNECT",
  1021. "RTPM_ID_SOC_REMOVE",
  1022. "RTPM_ID_DRIVER_UNLOAD",
  1023. "RTPM_ID_CE_INTR_HANDLER",
  1024. "RTPM_ID_WAKE_INTR_HANDLER",
  1025. "RTPM_ID_SOC_IDLE_SHUTDOWN",
  1026. "RTPM_ID_MAX"};
  1027. return (char *)strings[id];
  1028. }
  1029. /**
  1030. * enum hif_ep_vote_type - hif ep vote type
  1031. * HIF_EP_VOTE_DP_ACCESS: vote type is specific DP
  1032. * HIF_EP_VOTE_NONDP_ACCESS: ep vote for over all access
  1033. */
  1034. enum hif_ep_vote_type {
  1035. HIF_EP_VOTE_DP_ACCESS,
  1036. HIF_EP_VOTE_NONDP_ACCESS
  1037. };
  1038. /**
  1039. * enum hif_ep_vote_access - hif ep vote access
  1040. * HIF_EP_VOTE_ACCESS_ENABLE: Enable ep voting
  1041. * HIF_EP_VOTE_INTERMEDIATE_ACCESS: allow during transistion
  1042. * HIF_EP_VOTE_ACCESS_DISABLE: disable ep voting
  1043. */
  1044. enum hif_ep_vote_access {
  1045. HIF_EP_VOTE_ACCESS_ENABLE,
  1046. HIF_EP_VOTE_INTERMEDIATE_ACCESS,
  1047. HIF_EP_VOTE_ACCESS_DISABLE
  1048. };
  1049. /**
  1050. * enum hif_pm_link_state - hif link state
  1051. * HIF_PM_LINK_STATE_DOWN: hif link state is down
  1052. * HIF_PM_LINK_STATE_UP: hif link state is up
  1053. */
  1054. enum hif_pm_link_state {
  1055. HIF_PM_LINK_STATE_DOWN,
  1056. HIF_PM_LINK_STATE_UP
  1057. };
  1058. /**
  1059. * enum hif_pm_htc_stats - hif runtime PM stats for HTC layer
  1060. * HIF_PM_HTC_STATS_GET_HTT_RESPONSE: PM stats for RTPM GET for HTT packets
  1061. with response
  1062. * HIF_PM_HTC_STATS_GET_HTT_NO_RESPONSE: PM stats for RTPM GET for HTT packets
  1063. with no response
  1064. * HIF_PM_HTC_STATS_PUT_HTT_RESPONSE: PM stats for RTPM PUT for HTT packets
  1065. with response
  1066. * HIF_PM_HTC_STATS_PUT_HTT_NO_RESPONSE: PM stats for RTPM PUT for HTT packets
  1067. with no response
  1068. * HIF_PM_HTC_STATS_PUT_HTT_ERROR: PM stats for RTPM PUT for failed HTT packets
  1069. * HIF_PM_HTC_STATS_PUT_HTC_CLEANUP: PM stats for RTPM PUT during HTC cleanup
  1070. * HIF_PM_HTC_STATS_GET_HTC_KICK_QUEUES: PM stats for RTPM GET done during
  1071. * htc_kick_queues()
  1072. * HIF_PM_HTC_STATS_PUT_HTC_KICK_QUEUES: PM stats for RTPM PUT done during
  1073. * htc_kick_queues()
  1074. * HIF_PM_HTC_STATS_GET_HTT_FETCH_PKTS: PM stats for RTPM GET while fetching
  1075. * HTT packets from endpoint TX queue
  1076. * HIF_PM_HTC_STATS_PUT_HTT_FETCH_PKTS: PM stats for RTPM PUT while fetching
  1077. * HTT packets from endpoint TX queue
  1078. */
  1079. enum hif_pm_htc_stats {
  1080. HIF_PM_HTC_STATS_GET_HTT_RESPONSE,
  1081. HIF_PM_HTC_STATS_GET_HTT_NO_RESPONSE,
  1082. HIF_PM_HTC_STATS_PUT_HTT_RESPONSE,
  1083. HIF_PM_HTC_STATS_PUT_HTT_NO_RESPONSE,
  1084. HIF_PM_HTC_STATS_PUT_HTT_ERROR,
  1085. HIF_PM_HTC_STATS_PUT_HTC_CLEANUP,
  1086. HIF_PM_HTC_STATS_GET_HTC_KICK_QUEUES,
  1087. HIF_PM_HTC_STATS_PUT_HTC_KICK_QUEUES,
  1088. HIF_PM_HTC_STATS_GET_HTT_FETCH_PKTS,
  1089. HIF_PM_HTC_STATS_PUT_HTT_FETCH_PKTS,
  1090. };
  1091. #ifdef FEATURE_RUNTIME_PM
  1092. struct hif_pm_runtime_lock;
  1093. void hif_fastpath_resume(struct hif_opaque_softc *hif_ctx);
  1094. int hif_pm_runtime_get_sync(struct hif_opaque_softc *hif_ctx,
  1095. wlan_rtpm_dbgid rtpm_dbgid);
  1096. int hif_pm_runtime_put_sync_suspend(struct hif_opaque_softc *hif_ctx,
  1097. wlan_rtpm_dbgid rtpm_dbgid);
  1098. int hif_pm_runtime_request_resume(struct hif_opaque_softc *hif_ctx,
  1099. wlan_rtpm_dbgid rtpm_dbgid);
  1100. int hif_pm_runtime_get(struct hif_opaque_softc *hif_ctx,
  1101. wlan_rtpm_dbgid rtpm_dbgid,
  1102. bool is_critical_ctx);
  1103. void hif_pm_runtime_get_noresume(struct hif_opaque_softc *hif_ctx,
  1104. wlan_rtpm_dbgid rtpm_dbgid);
  1105. int hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx,
  1106. wlan_rtpm_dbgid rtpm_dbgid);
  1107. int hif_pm_runtime_put_noidle(struct hif_opaque_softc *hif_ctx,
  1108. wlan_rtpm_dbgid rtpm_dbgid);
  1109. void hif_pm_runtime_mark_last_busy(struct hif_opaque_softc *hif_ctx);
  1110. int hif_runtime_lock_init(qdf_runtime_lock_t *lock, const char *name);
  1111. void hif_runtime_lock_deinit(struct hif_opaque_softc *hif_ctx,
  1112. struct hif_pm_runtime_lock *lock);
  1113. int hif_pm_runtime_prevent_suspend(struct hif_opaque_softc *ol_sc,
  1114. struct hif_pm_runtime_lock *lock);
  1115. int hif_pm_runtime_allow_suspend(struct hif_opaque_softc *ol_sc,
  1116. struct hif_pm_runtime_lock *lock);
  1117. bool hif_pm_runtime_is_suspended(struct hif_opaque_softc *hif_ctx);
  1118. void hif_pm_runtime_suspend_lock(struct hif_opaque_softc *hif_ctx);
  1119. void hif_pm_runtime_suspend_unlock(struct hif_opaque_softc *hif_ctx);
  1120. int hif_pm_runtime_get_monitor_wake_intr(struct hif_opaque_softc *hif_ctx);
  1121. void hif_pm_runtime_set_monitor_wake_intr(struct hif_opaque_softc *hif_ctx,
  1122. int val);
  1123. void hif_pm_runtime_check_and_request_resume(struct hif_opaque_softc *hif_ctx);
  1124. void hif_pm_runtime_mark_dp_rx_busy(struct hif_opaque_softc *hif_ctx);
  1125. int hif_pm_runtime_is_dp_rx_busy(struct hif_opaque_softc *hif_ctx);
  1126. qdf_time_t hif_pm_runtime_get_dp_rx_busy_mark(struct hif_opaque_softc *hif_ctx);
  1127. int hif_pm_runtime_sync_resume(struct hif_opaque_softc *hif_ctx,
  1128. wlan_rtpm_dbgid rtpm_dbgid);
  1129. void hif_pm_runtime_update_stats(struct hif_opaque_softc *hif_ctx,
  1130. wlan_rtpm_dbgid rtpm_dbgid,
  1131. enum hif_pm_htc_stats stats);
  1132. /**
  1133. * hif_pm_set_link_state() - set link state during RTPM
  1134. * @hif_sc: HIF Context
  1135. *
  1136. * Return: None
  1137. */
  1138. void hif_pm_set_link_state(struct hif_opaque_softc *hif_handle, uint8_t val);
  1139. /**
  1140. * hif_is_link_state_up() - Is link state up
  1141. * @hif_sc: HIF Context
  1142. *
  1143. * Return: 1 link is up, 0 link is down
  1144. */
  1145. uint8_t hif_pm_get_link_state(struct hif_opaque_softc *hif_handle);
  1146. #else
  1147. struct hif_pm_runtime_lock {
  1148. const char *name;
  1149. };
  1150. static inline void hif_fastpath_resume(struct hif_opaque_softc *hif_ctx) {}
  1151. static inline int
  1152. hif_pm_runtime_get_sync(struct hif_opaque_softc *hif_ctx,
  1153. wlan_rtpm_dbgid rtpm_dbgid)
  1154. { return 0; }
  1155. static inline int
  1156. hif_pm_runtime_put_sync_suspend(struct hif_opaque_softc *hif_ctx,
  1157. wlan_rtpm_dbgid rtpm_dbgid)
  1158. { return 0; }
  1159. static inline int
  1160. hif_pm_runtime_request_resume(struct hif_opaque_softc *hif_ctx,
  1161. wlan_rtpm_dbgid rtpm_dbgid)
  1162. { return 0; }
  1163. static inline void
  1164. hif_pm_runtime_get_noresume(struct hif_opaque_softc *hif_ctx,
  1165. wlan_rtpm_dbgid rtpm_dbgid)
  1166. {}
  1167. static inline int
  1168. hif_pm_runtime_get(struct hif_opaque_softc *hif_ctx, wlan_rtpm_dbgid rtpm_dbgid,
  1169. bool is_critical_ctx)
  1170. { return 0; }
  1171. static inline int
  1172. hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx, wlan_rtpm_dbgid rtpm_dbgid)
  1173. { return 0; }
  1174. static inline int
  1175. hif_pm_runtime_put_noidle(struct hif_opaque_softc *hif_ctx,
  1176. wlan_rtpm_dbgid rtpm_dbgid)
  1177. { return 0; }
  1178. static inline void
  1179. hif_pm_runtime_mark_last_busy(struct hif_opaque_softc *hif_ctx) {};
  1180. static inline int hif_runtime_lock_init(qdf_runtime_lock_t *lock,
  1181. const char *name)
  1182. { return 0; }
  1183. static inline void
  1184. hif_runtime_lock_deinit(struct hif_opaque_softc *hif_ctx,
  1185. struct hif_pm_runtime_lock *lock) {}
  1186. static inline int hif_pm_runtime_prevent_suspend(struct hif_opaque_softc *ol_sc,
  1187. struct hif_pm_runtime_lock *lock)
  1188. { return 0; }
  1189. static inline int hif_pm_runtime_allow_suspend(struct hif_opaque_softc *ol_sc,
  1190. struct hif_pm_runtime_lock *lock)
  1191. { return 0; }
  1192. static inline bool hif_pm_runtime_is_suspended(struct hif_opaque_softc *hif_ctx)
  1193. { return false; }
  1194. static inline void
  1195. hif_pm_runtime_suspend_lock(struct hif_opaque_softc *hif_ctx)
  1196. { return; }
  1197. static inline void
  1198. hif_pm_runtime_suspend_unlock(struct hif_opaque_softc *hif_ctx)
  1199. { return; }
  1200. static inline int
  1201. hif_pm_runtime_get_monitor_wake_intr(struct hif_opaque_softc *hif_ctx)
  1202. { return 0; }
  1203. static inline void
  1204. hif_pm_runtime_set_monitor_wake_intr(struct hif_opaque_softc *hif_ctx, int val)
  1205. { return; }
  1206. static inline void
  1207. hif_pm_runtime_check_and_request_resume(struct hif_opaque_softc *hif_ctx)
  1208. { return; }
  1209. static inline void
  1210. hif_pm_runtime_mark_dp_rx_busy(struct hif_opaque_softc *hif_ctx) {};
  1211. static inline int
  1212. hif_pm_runtime_is_dp_rx_busy(struct hif_opaque_softc *hif_ctx)
  1213. { return 0; }
  1214. static inline qdf_time_t
  1215. hif_pm_runtime_get_dp_rx_busy_mark(struct hif_opaque_softc *hif_ctx)
  1216. { return 0; }
  1217. static inline int hif_pm_runtime_sync_resume(struct hif_opaque_softc *hif_ctx,
  1218. wlan_rtpm_dbgid rtpm_dbgid)
  1219. { return 0; }
  1220. static inline
  1221. void hif_pm_set_link_state(struct hif_opaque_softc *hif_handle, uint8_t val)
  1222. {}
  1223. static inline
  1224. void hif_pm_runtime_update_stats(struct hif_opaque_softc *hif_ctx,
  1225. wlan_rtpm_dbgid rtpm_dbgid,
  1226. enum hif_pm_htc_stats stats)
  1227. {}
  1228. #endif
  1229. void hif_enable_power_management(struct hif_opaque_softc *hif_ctx,
  1230. bool is_packet_log_enabled);
  1231. void hif_disable_power_management(struct hif_opaque_softc *hif_ctx);
  1232. void hif_vote_link_down(struct hif_opaque_softc *hif_ctx);
  1233. void hif_vote_link_up(struct hif_opaque_softc *hif_ctx);
  1234. bool hif_can_suspend_link(struct hif_opaque_softc *hif_ctx);
  1235. #ifdef IPA_OFFLOAD
  1236. /**
  1237. * hif_get_ipa_hw_type() - get IPA hw type
  1238. *
  1239. * This API return the IPA hw type.
  1240. *
  1241. * Return: IPA hw type
  1242. */
  1243. static inline
  1244. enum ipa_hw_type hif_get_ipa_hw_type(void)
  1245. {
  1246. return ipa_get_hw_type();
  1247. }
  1248. /**
  1249. * hif_get_ipa_present() - get IPA hw status
  1250. *
  1251. * This API return the IPA hw status.
  1252. *
  1253. * Return: true if IPA is present or false otherwise
  1254. */
  1255. static inline
  1256. bool hif_get_ipa_present(void)
  1257. {
  1258. if (ipa_uc_reg_rdyCB(NULL) != -EPERM)
  1259. return true;
  1260. else
  1261. return false;
  1262. }
  1263. #endif
  1264. int hif_bus_resume(struct hif_opaque_softc *hif_ctx);
  1265. /**
  1266. * hif_bus_ealry_suspend() - stop non wmi tx traffic
  1267. * @context: hif context
  1268. */
  1269. int hif_bus_early_suspend(struct hif_opaque_softc *hif_ctx);
  1270. /**
  1271. * hif_bus_late_resume() - resume non wmi traffic
  1272. * @context: hif context
  1273. */
  1274. int hif_bus_late_resume(struct hif_opaque_softc *hif_ctx);
  1275. int hif_bus_suspend(struct hif_opaque_softc *hif_ctx);
  1276. int hif_bus_resume_noirq(struct hif_opaque_softc *hif_ctx);
  1277. int hif_bus_suspend_noirq(struct hif_opaque_softc *hif_ctx);
  1278. /**
  1279. * hif_apps_irqs_enable() - Enables all irqs from the APPS side
  1280. * @hif_ctx: an opaque HIF handle to use
  1281. *
  1282. * As opposed to the standard hif_irq_enable, this function always applies to
  1283. * the APPS side kernel interrupt handling.
  1284. *
  1285. * Return: errno
  1286. */
  1287. int hif_apps_irqs_enable(struct hif_opaque_softc *hif_ctx);
  1288. /**
  1289. * hif_apps_irqs_disable() - Disables all irqs from the APPS side
  1290. * @hif_ctx: an opaque HIF handle to use
  1291. *
  1292. * As opposed to the standard hif_irq_disable, this function always applies to
  1293. * the APPS side kernel interrupt handling.
  1294. *
  1295. * Return: errno
  1296. */
  1297. int hif_apps_irqs_disable(struct hif_opaque_softc *hif_ctx);
  1298. /**
  1299. * hif_apps_wake_irq_enable() - Enables the wake irq from the APPS side
  1300. * @hif_ctx: an opaque HIF handle to use
  1301. *
  1302. * As opposed to the standard hif_irq_enable, this function always applies to
  1303. * the APPS side kernel interrupt handling.
  1304. *
  1305. * Return: errno
  1306. */
  1307. int hif_apps_wake_irq_enable(struct hif_opaque_softc *hif_ctx);
  1308. /**
  1309. * hif_apps_wake_irq_disable() - Disables the wake irq from the APPS side
  1310. * @hif_ctx: an opaque HIF handle to use
  1311. *
  1312. * As opposed to the standard hif_irq_disable, this function always applies to
  1313. * the APPS side kernel interrupt handling.
  1314. *
  1315. * Return: errno
  1316. */
  1317. int hif_apps_wake_irq_disable(struct hif_opaque_softc *hif_ctx);
  1318. /**
  1319. * hif_apps_enable_irq_wake() - Enables the irq wake from the APPS side
  1320. * @hif_ctx: an opaque HIF handle to use
  1321. *
  1322. * This function always applies to the APPS side kernel interrupt handling
  1323. * to wake the system from suspend.
  1324. *
  1325. * Return: errno
  1326. */
  1327. int hif_apps_enable_irq_wake(struct hif_opaque_softc *hif_ctx);
  1328. /**
  1329. * hif_apps_disable_irq_wake() - Disables the wake irq from the APPS side
  1330. * @hif_ctx: an opaque HIF handle to use
  1331. *
  1332. * This function always applies to the APPS side kernel interrupt handling
  1333. * to disable the wake irq.
  1334. *
  1335. * Return: errno
  1336. */
  1337. int hif_apps_disable_irq_wake(struct hif_opaque_softc *hif_ctx);
  1338. /**
  1339. * hif_apps_enable_irqs_except_wake_irq() - Enables all irqs except wake_irq
  1340. * @hif_ctx: an opaque HIF handle to use
  1341. *
  1342. * As opposed to the standard hif_irq_enable, this function always applies to
  1343. * the APPS side kernel interrupt handling.
  1344. *
  1345. * Return: errno
  1346. */
  1347. int hif_apps_enable_irqs_except_wake_irq(struct hif_opaque_softc *hif_ctx);
  1348. /**
  1349. * hif_apps_disable_irqs_except_wake_irq() - Disables all irqs except wake_irq
  1350. * @hif_ctx: an opaque HIF handle to use
  1351. *
  1352. * As opposed to the standard hif_irq_disable, this function always applies to
  1353. * the APPS side kernel interrupt handling.
  1354. *
  1355. * Return: errno
  1356. */
  1357. int hif_apps_disable_irqs_except_wake_irq(struct hif_opaque_softc *hif_ctx);
  1358. #ifdef FEATURE_RUNTIME_PM
  1359. void hif_print_runtime_pm_prevent_list(struct hif_opaque_softc *hif_ctx);
  1360. int hif_pre_runtime_suspend(struct hif_opaque_softc *hif_ctx);
  1361. void hif_pre_runtime_resume(struct hif_opaque_softc *hif_ctx);
  1362. int hif_runtime_suspend(struct hif_opaque_softc *hif_ctx);
  1363. int hif_runtime_resume(struct hif_opaque_softc *hif_ctx);
  1364. void hif_process_runtime_suspend_success(struct hif_opaque_softc *hif_ctx);
  1365. void hif_process_runtime_suspend_failure(struct hif_opaque_softc *hif_ctx);
  1366. void hif_process_runtime_resume_success(struct hif_opaque_softc *hif_ctx);
  1367. #else
  1368. static inline void
  1369. hif_print_runtime_pm_prevent_list(struct hif_opaque_softc *hif_ctx)
  1370. {}
  1371. #endif
  1372. int hif_get_irq_num(struct hif_opaque_softc *scn, int *irq, uint32_t size);
  1373. int hif_dump_registers(struct hif_opaque_softc *scn);
  1374. int ol_copy_ramdump(struct hif_opaque_softc *scn);
  1375. void hif_crash_shutdown(struct hif_opaque_softc *hif_ctx);
  1376. void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version,
  1377. u32 *revision, const char **target_name);
  1378. enum qdf_bus_type hif_get_bus_type(struct hif_opaque_softc *hif_hdl);
  1379. struct hif_target_info *hif_get_target_info_handle(struct hif_opaque_softc *
  1380. scn);
  1381. struct hif_config_info *hif_get_ini_handle(struct hif_opaque_softc *hif_ctx);
  1382. struct ramdump_info *hif_get_ramdump_ctx(struct hif_opaque_softc *hif_ctx);
  1383. enum hif_target_status hif_get_target_status(struct hif_opaque_softc *hif_ctx);
  1384. void hif_set_target_status(struct hif_opaque_softc *hif_ctx, enum
  1385. hif_target_status);
  1386. void hif_init_ini_config(struct hif_opaque_softc *hif_ctx,
  1387. struct hif_config_info *cfg);
  1388. void hif_update_tx_ring(struct hif_opaque_softc *osc, u_int32_t num_htt_cmpls);
  1389. qdf_nbuf_t hif_batch_send(struct hif_opaque_softc *osc, qdf_nbuf_t msdu,
  1390. uint32_t transfer_id, u_int32_t len, uint32_t sendhead);
  1391. QDF_STATUS hif_send_single(struct hif_opaque_softc *osc, qdf_nbuf_t msdu,
  1392. uint32_t transfer_id, u_int32_t len);
  1393. int hif_send_fast(struct hif_opaque_softc *osc, qdf_nbuf_t nbuf,
  1394. uint32_t transfer_id, uint32_t download_len);
  1395. void hif_pkt_dl_len_set(void *hif_sc, unsigned int pkt_download_len);
  1396. void hif_ce_war_disable(void);
  1397. void hif_ce_war_enable(void);
  1398. void hif_disable_interrupt(struct hif_opaque_softc *osc, uint32_t pipe_num);
  1399. #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT
  1400. struct hif_pipe_addl_info *hif_get_addl_pipe_info(struct hif_opaque_softc *osc,
  1401. struct hif_pipe_addl_info *hif_info, uint32_t pipe_number);
  1402. uint32_t hif_set_nss_wifiol_mode(struct hif_opaque_softc *osc,
  1403. uint32_t pipe_num);
  1404. int32_t hif_get_nss_wifiol_bypass_nw_process(struct hif_opaque_softc *osc);
  1405. #endif /* QCA_NSS_WIFI_OFFLOAD_SUPPORT */
  1406. void hif_set_bundle_mode(struct hif_opaque_softc *hif_ctx, bool enabled,
  1407. int rx_bundle_cnt);
  1408. int hif_bus_reset_resume(struct hif_opaque_softc *hif_ctx);
  1409. void hif_set_attribute(struct hif_opaque_softc *osc, uint8_t hif_attrib);
  1410. void *hif_get_lro_info(int ctx_id, struct hif_opaque_softc *hif_hdl);
  1411. enum hif_exec_type {
  1412. HIF_EXEC_NAPI_TYPE,
  1413. HIF_EXEC_TASKLET_TYPE,
  1414. };
  1415. typedef uint32_t (*ext_intr_handler)(void *, uint32_t);
  1416. /**
  1417. * hif_get_int_ctx_irq_num() - retrieve an irq num for an interrupt context id
  1418. * @softc: hif opaque context owning the exec context
  1419. * @id: the id of the interrupt context
  1420. *
  1421. * Return: IRQ number of the first (zero'th) IRQ within the interrupt context ID
  1422. * 'id' registered with the OS
  1423. */
  1424. int32_t hif_get_int_ctx_irq_num(struct hif_opaque_softc *softc,
  1425. uint8_t id);
  1426. /**
  1427. * hif_configure_ext_group_interrupts() - Congigure ext group intrrupts
  1428. * @hif_ctx: hif opaque context
  1429. *
  1430. * Return: QDF_STATUS
  1431. */
  1432. QDF_STATUS hif_configure_ext_group_interrupts(struct hif_opaque_softc *hif_ctx);
  1433. /**
  1434. * hif_deconfigure_ext_group_interrupts() - Deconfigure ext group intrrupts
  1435. * @hif_ctx: hif opaque context
  1436. *
  1437. * Return: None
  1438. */
  1439. void hif_deconfigure_ext_group_interrupts(struct hif_opaque_softc *hif_ctx);
  1440. /**
  1441. * hif_register_ext_group() - API to register external group
  1442. * interrupt handler.
  1443. * @hif_ctx : HIF Context
  1444. * @numirq: number of irq's in the group
  1445. * @irq: array of irq values
  1446. * @handler: callback interrupt handler function
  1447. * @cb_ctx: context to passed in callback
  1448. * @type: napi vs tasklet
  1449. *
  1450. * Return: QDF_STATUS
  1451. */
  1452. QDF_STATUS hif_register_ext_group(struct hif_opaque_softc *hif_ctx,
  1453. uint32_t numirq, uint32_t irq[],
  1454. ext_intr_handler handler,
  1455. void *cb_ctx, const char *context_name,
  1456. enum hif_exec_type type, uint32_t scale);
  1457. void hif_deregister_exec_group(struct hif_opaque_softc *hif_ctx,
  1458. const char *context_name);
  1459. void hif_update_pipe_callback(struct hif_opaque_softc *osc,
  1460. u_int8_t pipeid,
  1461. struct hif_msg_callbacks *callbacks);
  1462. /**
  1463. * hif_print_napi_stats() - Display HIF NAPI stats
  1464. * @hif_ctx - HIF opaque context
  1465. *
  1466. * Return: None
  1467. */
  1468. void hif_print_napi_stats(struct hif_opaque_softc *hif_ctx);
  1469. /* hif_clear_napi_stats() - function clears the stats of the
  1470. * latency when called.
  1471. * @hif_ctx - the HIF context to assign the callback to
  1472. *
  1473. * Return: None
  1474. */
  1475. void hif_clear_napi_stats(struct hif_opaque_softc *hif_ctx);
  1476. #ifdef __cplusplus
  1477. }
  1478. #endif
  1479. #ifdef FORCE_WAKE
  1480. /**
  1481. * hif_force_wake_request() - Function to wake from power collapse
  1482. * @handle: HIF opaque handle
  1483. *
  1484. * Description: API to check if the device is awake or not before
  1485. * read/write to BAR + 4K registers. If device is awake return
  1486. * success otherwise write '1' to
  1487. * PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG which will interrupt
  1488. * the device and does wakeup the PCI and MHI within 50ms
  1489. * and then the device writes a value to
  1490. * PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG to complete the
  1491. * handshake process to let the host know the device is awake.
  1492. *
  1493. * Return: zero - success/non-zero - failure
  1494. */
  1495. int hif_force_wake_request(struct hif_opaque_softc *handle);
  1496. /**
  1497. * hif_force_wake_release() - API to release/reset the SOC wake register
  1498. * from interrupting the device.
  1499. * @handle: HIF opaque handle
  1500. *
  1501. * Description: API to set the
  1502. * PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG to '0'
  1503. * to release the interrupt line.
  1504. *
  1505. * Return: zero - success/non-zero - failure
  1506. */
  1507. int hif_force_wake_release(struct hif_opaque_softc *handle);
  1508. #else
  1509. static inline
  1510. int hif_force_wake_request(struct hif_opaque_softc *handle)
  1511. {
  1512. return 0;
  1513. }
  1514. static inline
  1515. int hif_force_wake_release(struct hif_opaque_softc *handle)
  1516. {
  1517. return 0;
  1518. }
  1519. #endif /* FORCE_WAKE */
  1520. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  1521. /**
  1522. * hif_prevent_link_low_power_states() - Prevent from going to low power states
  1523. * @hif - HIF opaque context
  1524. *
  1525. * Return: 0 on success. Error code on failure.
  1526. */
  1527. int hif_prevent_link_low_power_states(struct hif_opaque_softc *hif);
  1528. /**
  1529. * hif_allow_link_low_power_states() - Allow link to go to low power states
  1530. * @hif - HIF opaque context
  1531. *
  1532. * Return: None
  1533. */
  1534. void hif_allow_link_low_power_states(struct hif_opaque_softc *hif);
  1535. #else
  1536. static inline
  1537. int hif_prevent_link_low_power_states(struct hif_opaque_softc *hif)
  1538. {
  1539. return 0;
  1540. }
  1541. static inline
  1542. void hif_allow_link_low_power_states(struct hif_opaque_softc *hif)
  1543. {
  1544. }
  1545. #endif
  1546. void *hif_get_dev_ba(struct hif_opaque_softc *hif_handle);
  1547. void *hif_get_dev_ba_ce(struct hif_opaque_softc *hif_handle);
  1548. /**
  1549. * hif_set_initial_wakeup_cb() - set the initial wakeup event handler function
  1550. * @hif_ctx - the HIF context to assign the callback to
  1551. * @callback - the callback to assign
  1552. * @priv - the private data to pass to the callback when invoked
  1553. *
  1554. * Return: None
  1555. */
  1556. void hif_set_initial_wakeup_cb(struct hif_opaque_softc *hif_ctx,
  1557. void (*callback)(void *),
  1558. void *priv);
  1559. /*
  1560. * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked
  1561. * for defined here
  1562. */
  1563. #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)
  1564. ssize_t hif_dump_desc_trace_buf(struct device *dev,
  1565. struct device_attribute *attr, char *buf);
  1566. ssize_t hif_input_desc_trace_buf_index(struct hif_softc *scn,
  1567. const char *buf, size_t size);
  1568. ssize_t hif_ce_en_desc_hist(struct hif_softc *scn,
  1569. const char *buf, size_t size);
  1570. ssize_t hif_disp_ce_enable_desc_data_hist(struct hif_softc *scn, char *buf);
  1571. ssize_t hif_dump_desc_event(struct hif_softc *scn, char *buf);
  1572. /**
  1573. * hif_ce_debug_history_prealloc_init() - alloc ce debug history memory
  1574. *
  1575. * alloc ce debug history memory with driver init, so such memory can
  1576. * be existed even after stop module.
  1577. * on ini value.
  1578. *
  1579. * Return: QDF_STATUS_SUCCESS for success, other for fail.
  1580. */
  1581. QDF_STATUS hif_ce_debug_history_prealloc_init(void);
  1582. /**
  1583. * hif_ce_debug_history_prealloc_deinit() - free ce debug history memory
  1584. *
  1585. * free ce debug history memory when driver deinit.
  1586. *
  1587. * Return: QDF_STATUS_SUCCESS for success, other for fail.
  1588. */
  1589. QDF_STATUS hif_ce_debug_history_prealloc_deinit(void);
  1590. #else
  1591. static inline
  1592. QDF_STATUS hif_ce_debug_history_prealloc_init(void)
  1593. {
  1594. return QDF_STATUS_SUCCESS;
  1595. }
  1596. static inline
  1597. QDF_STATUS hif_ce_debug_history_prealloc_deinit(void)
  1598. {
  1599. return QDF_STATUS_SUCCESS;
  1600. }
  1601. #endif/*#if defined(HIF_CONFIG_SLUB_DEBUG_ON)||defined(HIF_CE_DEBUG_DATA_BUF)*/
  1602. /**
  1603. * hif_set_ce_service_max_yield_time() - sets CE service max yield time
  1604. * @hif: hif context
  1605. * @ce_service_max_yield_time: CE service max yield time to set
  1606. *
  1607. * This API storess CE service max yield time in hif context based
  1608. * on ini value.
  1609. *
  1610. * Return: void
  1611. */
  1612. void hif_set_ce_service_max_yield_time(struct hif_opaque_softc *hif,
  1613. uint32_t ce_service_max_yield_time);
  1614. /**
  1615. * hif_get_ce_service_max_yield_time() - get CE service max yield time
  1616. * @hif: hif context
  1617. *
  1618. * This API returns CE service max yield time.
  1619. *
  1620. * Return: CE service max yield time
  1621. */
  1622. unsigned long long
  1623. hif_get_ce_service_max_yield_time(struct hif_opaque_softc *hif);
  1624. /**
  1625. * hif_set_ce_service_max_rx_ind_flush() - sets CE service max rx ind flush
  1626. * @hif: hif context
  1627. * @ce_service_max_rx_ind_flush: CE service max rx ind flush to set
  1628. *
  1629. * This API stores CE service max rx ind flush in hif context based
  1630. * on ini value.
  1631. *
  1632. * Return: void
  1633. */
  1634. void hif_set_ce_service_max_rx_ind_flush(struct hif_opaque_softc *hif,
  1635. uint8_t ce_service_max_rx_ind_flush);
  1636. #ifdef OL_ATH_SMART_LOGGING
  1637. /*
  1638. * hif_log_ce_dump() - Copy all the CE DEST ring to buf
  1639. * @scn : HIF handler
  1640. * @buf_cur: Current pointer in ring buffer
  1641. * @buf_init:Start of the ring buffer
  1642. * @buf_sz: Size of the ring buffer
  1643. * @ce: Copy Engine id
  1644. * @skb_sz: Max size of the SKB buffer to be copied
  1645. *
  1646. * Calls the respective function to dump all the CE SRC/DEST ring descriptors
  1647. * and buffers pointed by them in to the given buf
  1648. *
  1649. * Return: Current pointer in ring buffer
  1650. */
  1651. uint8_t *hif_log_dump_ce(struct hif_softc *scn, uint8_t *buf_cur,
  1652. uint8_t *buf_init, uint32_t buf_sz,
  1653. uint32_t ce, uint32_t skb_sz);
  1654. #endif /* OL_ATH_SMART_LOGGING */
  1655. /*
  1656. * hif_softc_to_hif_opaque_softc - API to convert hif_softc handle
  1657. * to hif_opaque_softc handle
  1658. * @hif_handle - hif_softc type
  1659. *
  1660. * Return: hif_opaque_softc type
  1661. */
  1662. static inline struct hif_opaque_softc *
  1663. hif_softc_to_hif_opaque_softc(struct hif_softc *hif_handle)
  1664. {
  1665. return (struct hif_opaque_softc *)hif_handle;
  1666. }
  1667. #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE)
  1668. QDF_STATUS hif_try_prevent_ep_vote_access(struct hif_opaque_softc *hif_ctx);
  1669. void hif_set_ep_intermediate_vote_access(struct hif_opaque_softc *hif_ctx);
  1670. void hif_allow_ep_vote_access(struct hif_opaque_softc *hif_ctx);
  1671. void hif_set_ep_vote_access(struct hif_opaque_softc *hif_ctx,
  1672. uint8_t type, uint8_t access);
  1673. uint8_t hif_get_ep_vote_access(struct hif_opaque_softc *hif_ctx,
  1674. uint8_t type);
  1675. #else
  1676. static inline QDF_STATUS
  1677. hif_try_prevent_ep_vote_access(struct hif_opaque_softc *hif_ctx)
  1678. {
  1679. return QDF_STATUS_SUCCESS;
  1680. }
  1681. static inline void
  1682. hif_set_ep_intermediate_vote_access(struct hif_opaque_softc *hif_ctx)
  1683. {
  1684. }
  1685. static inline void
  1686. hif_allow_ep_vote_access(struct hif_opaque_softc *hif_ctx)
  1687. {
  1688. }
  1689. static inline void
  1690. hif_set_ep_vote_access(struct hif_opaque_softc *hif_ctx,
  1691. uint8_t type, uint8_t access)
  1692. {
  1693. }
  1694. static inline uint8_t
  1695. hif_get_ep_vote_access(struct hif_opaque_softc *hif_ctx,
  1696. uint8_t type)
  1697. {
  1698. return HIF_EP_VOTE_ACCESS_ENABLE;
  1699. }
  1700. #endif
  1701. #ifdef FORCE_WAKE
  1702. /**
  1703. * hif_srng_init_phase(): Indicate srng initialization phase
  1704. * to avoid force wake as UMAC power collapse is not yet
  1705. * enabled
  1706. * @hif_ctx: hif opaque handle
  1707. * @init_phase: initialization phase
  1708. *
  1709. * Return: None
  1710. */
  1711. void hif_srng_init_phase(struct hif_opaque_softc *hif_ctx,
  1712. bool init_phase);
  1713. #else
  1714. static inline
  1715. void hif_srng_init_phase(struct hif_opaque_softc *hif_ctx,
  1716. bool init_phase)
  1717. {
  1718. }
  1719. #endif /* FORCE_WAKE */
  1720. #ifdef HIF_IPCI
  1721. /**
  1722. * hif_shutdown_notifier_cb - Call back for shutdown notifier
  1723. * @ctx: hif handle
  1724. *
  1725. * Return: None
  1726. */
  1727. void hif_shutdown_notifier_cb(void *ctx);
  1728. #else
  1729. static inline
  1730. void hif_shutdown_notifier_cb(void *ctx)
  1731. {
  1732. }
  1733. #endif /* HIF_IPCI */
  1734. #ifdef HIF_CE_LOG_INFO
  1735. /**
  1736. * hif_log_ce_info() - API to log ce info
  1737. * @scn: hif handle
  1738. * @data: hang event data buffer
  1739. * @offset: offset at which data needs to be written
  1740. *
  1741. * Return: None
  1742. */
  1743. void hif_log_ce_info(struct hif_softc *scn, uint8_t *data,
  1744. unsigned int *offset);
  1745. #else
  1746. static inline
  1747. void hif_log_ce_info(struct hif_softc *scn, uint8_t *data,
  1748. unsigned int *offset)
  1749. {
  1750. }
  1751. #endif
  1752. #ifdef HIF_CPU_PERF_AFFINE_MASK
  1753. /**
  1754. * hif_config_irq_set_perf_affinity_hint() - API to set affinity
  1755. * @hif_ctx: hif opaque handle
  1756. *
  1757. * This function is used to move the WLAN IRQs to perf cores in
  1758. * case of defconfig builds.
  1759. *
  1760. * Return: None
  1761. */
  1762. void hif_config_irq_set_perf_affinity_hint(
  1763. struct hif_opaque_softc *hif_ctx);
  1764. #else
  1765. static inline void hif_config_irq_set_perf_affinity_hint(
  1766. struct hif_opaque_softc *hif_ctx)
  1767. {
  1768. }
  1769. #endif
  1770. /**
  1771. * hif_apps_grp_irqs_enable() - enable ext grp irqs
  1772. * @hif - HIF opaque context
  1773. *
  1774. * Return: 0 on success. Error code on failure.
  1775. */
  1776. int hif_apps_grp_irqs_enable(struct hif_opaque_softc *hif_ctx);
  1777. /**
  1778. * hif_apps_grp_irqs_disable() - disable ext grp irqs
  1779. * @hif - HIF opaque context
  1780. *
  1781. * Return: 0 on success. Error code on failure.
  1782. */
  1783. int hif_apps_grp_irqs_disable(struct hif_opaque_softc *hif_ctx);
  1784. /**
  1785. * hif_disable_grp_irqs() - disable ext grp irqs
  1786. * @hif - HIF opaque context
  1787. *
  1788. * Return: 0 on success. Error code on failure.
  1789. */
  1790. int hif_disable_grp_irqs(struct hif_opaque_softc *scn);
  1791. /**
  1792. * hif_enable_grp_irqs() - enable ext grp irqs
  1793. * @hif - HIF opaque context
  1794. *
  1795. * Return: 0 on success. Error code on failure.
  1796. */
  1797. int hif_enable_grp_irqs(struct hif_opaque_softc *scn);
  1798. enum hif_credit_exchange_type {
  1799. HIF_REQUEST_CREDIT,
  1800. HIF_PROCESS_CREDIT_REPORT,
  1801. };
  1802. enum hif_detect_latency_type {
  1803. HIF_DETECT_TASKLET,
  1804. HIF_DETECT_CREDIT,
  1805. HIF_DETECT_UNKNOWN
  1806. };
  1807. #ifdef HIF_DETECTION_LATENCY_ENABLE
  1808. void hif_latency_detect_credit_record_time(
  1809. enum hif_credit_exchange_type type,
  1810. struct hif_opaque_softc *hif_ctx);
  1811. void hif_latency_detect_timer_start(struct hif_opaque_softc *hif_ctx);
  1812. void hif_latency_detect_timer_stop(struct hif_opaque_softc *hif_ctx);
  1813. void hif_tasklet_latency(struct hif_softc *scn, bool from_timer);
  1814. void hif_credit_latency(struct hif_softc *scn, bool from_timer);
  1815. void hif_check_detection_latency(struct hif_softc *scn,
  1816. bool from_timer,
  1817. uint32_t bitmap_type);
  1818. void hif_set_enable_detection(struct hif_opaque_softc *hif_ctx, bool value);
  1819. #else
  1820. static inline
  1821. void hif_latency_detect_timer_start(struct hif_opaque_softc *hif_ctx)
  1822. {}
  1823. static inline
  1824. void hif_latency_detect_timer_stop(struct hif_opaque_softc *hif_ctx)
  1825. {}
  1826. static inline
  1827. void hif_latency_detect_credit_record_time(
  1828. enum hif_credit_exchange_type type,
  1829. struct hif_opaque_softc *hif_ctx)
  1830. {}
  1831. static inline
  1832. void hif_check_detection_latency(struct hif_softc *scn,
  1833. bool from_timer,
  1834. uint32_t bitmap_type)
  1835. {}
  1836. static inline
  1837. void hif_set_enable_detection(struct hif_opaque_softc *hif_ctx, bool value)
  1838. {}
  1839. #endif
  1840. #ifdef SYSTEM_PM_CHECK
  1841. /**
  1842. * __hif_system_pm_set_state() - Set system pm state
  1843. * @hif: hif opaque handle
  1844. * @state: system state
  1845. *
  1846. * Return: None
  1847. */
  1848. void __hif_system_pm_set_state(struct hif_opaque_softc *hif,
  1849. enum hif_system_pm_state state);
  1850. /**
  1851. * hif_system_pm_set_state_on() - Set system pm state to ON
  1852. * @hif: hif opaque handle
  1853. *
  1854. * Return: None
  1855. */
  1856. static inline
  1857. void hif_system_pm_set_state_on(struct hif_opaque_softc *hif)
  1858. {
  1859. __hif_system_pm_set_state(hif, HIF_SYSTEM_PM_STATE_ON);
  1860. }
  1861. /**
  1862. * hif_system_pm_set_state_resuming() - Set system pm state to resuming
  1863. * @hif: hif opaque handle
  1864. *
  1865. * Return: None
  1866. */
  1867. static inline
  1868. void hif_system_pm_set_state_resuming(struct hif_opaque_softc *hif)
  1869. {
  1870. __hif_system_pm_set_state(hif, HIF_SYSTEM_PM_STATE_BUS_RESUMING);
  1871. }
  1872. /**
  1873. * hif_system_pm_set_state_suspending() - Set system pm state to suspending
  1874. * @hif: hif opaque handle
  1875. *
  1876. * Return: None
  1877. */
  1878. static inline
  1879. void hif_system_pm_set_state_suspending(struct hif_opaque_softc *hif)
  1880. {
  1881. __hif_system_pm_set_state(hif, HIF_SYSTEM_PM_STATE_BUS_SUSPENDING);
  1882. }
  1883. /**
  1884. * hif_system_pm_set_state_suspended() - Set system pm state to suspended
  1885. * @hif: hif opaque handle
  1886. *
  1887. * Return: None
  1888. */
  1889. static inline
  1890. void hif_system_pm_set_state_suspended(struct hif_opaque_softc *hif)
  1891. {
  1892. __hif_system_pm_set_state(hif, HIF_SYSTEM_PM_STATE_BUS_SUSPENDED);
  1893. }
  1894. /**
  1895. * hif_system_pm_get_state() - Get system pm state
  1896. * @hif: hif opaque handle
  1897. *
  1898. * Return: system state
  1899. */
  1900. int32_t hif_system_pm_get_state(struct hif_opaque_softc *hif);
  1901. /**
  1902. * hif_system_pm_state_check() - Check system state and trigger resume
  1903. * if required
  1904. * @hif: hif opaque handle
  1905. *
  1906. * Return: 0 if system is in on state else error code
  1907. */
  1908. int hif_system_pm_state_check(struct hif_opaque_softc *hif);
  1909. #else
  1910. static inline
  1911. void __hif_system_pm_set_state(struct hif_opaque_softc *hif,
  1912. enum hif_system_pm_state state)
  1913. {
  1914. }
  1915. static inline
  1916. void hif_system_pm_set_state_on(struct hif_opaque_softc *hif)
  1917. {
  1918. }
  1919. static inline
  1920. void hif_system_pm_set_state_resuming(struct hif_opaque_softc *hif)
  1921. {
  1922. }
  1923. static inline
  1924. void hif_system_pm_set_state_suspending(struct hif_opaque_softc *hif)
  1925. {
  1926. }
  1927. static inline
  1928. void hif_system_pm_set_state_suspended(struct hif_opaque_softc *hif)
  1929. {
  1930. }
  1931. static inline
  1932. int32_t hif_system_pm_get_state(struct hif_opaque_softc *hif)
  1933. {
  1934. return 0;
  1935. }
  1936. static inline int hif_system_pm_state_check(struct hif_opaque_softc *hif)
  1937. {
  1938. return 0;
  1939. }
  1940. #endif
  1941. #ifdef FEATURE_IRQ_AFFINITY
  1942. /**
  1943. * hif_set_grp_intr_affinity() - API to set affinity for grp
  1944. * intrs set in the bitmap
  1945. * @scn: hif handle
  1946. * @grp_intr_bitmask: grp intrs for which perf affinity should be
  1947. * applied
  1948. * @perf: affine to perf or non-perf cluster
  1949. *
  1950. * Return: None
  1951. */
  1952. void hif_set_grp_intr_affinity(struct hif_opaque_softc *scn,
  1953. uint32_t grp_intr_bitmask, bool perf);
  1954. #else
  1955. static inline
  1956. void hif_set_grp_intr_affinity(struct hif_opaque_softc *scn,
  1957. uint32_t grp_intr_bitmask, bool perf)
  1958. {
  1959. }
  1960. #endif
  1961. /**
  1962. * hif_get_max_wmi_ep() - Get max WMI EPs configured in target svc map
  1963. * @hif_ctx: hif opaque handle
  1964. *
  1965. * Description:
  1966. * Gets number of WMI EPs configured in target svc map. Since EP map
  1967. * include IN and OUT direction pipes, count only OUT pipes to get EPs
  1968. * configured for WMI service.
  1969. *
  1970. * Return:
  1971. * uint8_t: count for WMI eps in target svc map
  1972. */
  1973. uint8_t hif_get_max_wmi_ep(struct hif_opaque_softc *scn);
  1974. #endif /* _HIF_H_ */