qcedev.c 74 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * QTI CE device driver.
  4. *
  5. * Copyright (c) 2010-2021, The Linux Foundation. All rights reserved.
  6. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  7. */
  8. #include <linux/mman.h>
  9. #include <linux/module.h>
  10. #include <linux/device.h>
  11. #include <linux/types.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/kernel.h>
  15. #include <linux/dmapool.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/init.h>
  19. #include <linux/module.h>
  20. #include <linux/fs.h>
  21. #include <linux/uaccess.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/scatterlist.h>
  24. #include <linux/crypto.h>
  25. #include "linux/qcedev.h"
  26. #include <linux/interconnect.h>
  27. #include <linux/delay.h>
  28. #include "linux/compat_qcedev.h"
  29. #include <crypto/hash.h>
  30. #include "qcedevi.h"
  31. #include "qce.h"
  32. #include "qcedev_smmu.h"
  33. #include "qcom_crypto_device.h"
  34. #include <linux/compat.h>
  35. #define CACHE_LINE_SIZE 64
  36. #define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
  37. #define MAX_CEHW_REQ_TRANSFER_SIZE (128*32*1024)
  38. /*
  39. * Max wait time once a crypto request is submitted.
  40. */
  41. #define MAX_CRYPTO_WAIT_TIME 1500
  42. /*
  43. * Max wait time once a offload crypto request is submitted.
  44. * This is low due to expected timeout and key pause errors.
  45. * This is temporary, and we can use the 1500 value once the
  46. * core irqs are enabled.
  47. */
  48. #define MAX_OFFLOAD_CRYPTO_WAIT_TIME 25
  49. #define MAX_REQUEST_TIME 5000
  50. enum qcedev_req_status {
  51. QCEDEV_REQ_CURRENT = 0,
  52. QCEDEV_REQ_WAITING = 1,
  53. QCEDEV_REQ_SUBMITTED = 2,
  54. QCEDEV_REQ_DONE = 3,
  55. };
  56. static uint8_t _std_init_vector_sha1_uint8[] = {
  57. 0x67, 0x45, 0x23, 0x01, 0xEF, 0xCD, 0xAB, 0x89,
  58. 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76,
  59. 0xC3, 0xD2, 0xE1, 0xF0
  60. };
  61. /* standard initialization vector for SHA-256, source: FIPS 180-2 */
  62. static uint8_t _std_init_vector_sha256_uint8[] = {
  63. 0x6A, 0x09, 0xE6, 0x67, 0xBB, 0x67, 0xAE, 0x85,
  64. 0x3C, 0x6E, 0xF3, 0x72, 0xA5, 0x4F, 0xF5, 0x3A,
  65. 0x51, 0x0E, 0x52, 0x7F, 0x9B, 0x05, 0x68, 0x8C,
  66. 0x1F, 0x83, 0xD9, 0xAB, 0x5B, 0xE0, 0xCD, 0x19
  67. };
  68. #define QCEDEV_CTX_KEY_MASK 0x000000ff
  69. #define QCEDEV_CTX_USE_HW_KEY 0x00000001
  70. #define QCEDEV_CTX_USE_PIPE_KEY 0x00000002
  71. static DEFINE_MUTEX(send_cmd_lock);
  72. static DEFINE_MUTEX(qcedev_sent_bw_req);
  73. static DEFINE_MUTEX(hash_access_lock);
  74. static dev_t qcedev_device_no;
  75. static struct class *driver_class;
  76. static struct device *class_dev;
  77. static const struct of_device_id qcedev_match[] = {
  78. { .compatible = "qcom,qcedev"},
  79. { .compatible = "qcom,qcedev,context-bank"},
  80. {}
  81. };
  82. MODULE_DEVICE_TABLE(of, qcedev_match);
  83. static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
  84. {
  85. unsigned int control_flag;
  86. int ret = 0;
  87. if (podev->ce_support.req_bw_before_clk) {
  88. if (enable)
  89. control_flag = QCE_BW_REQUEST_FIRST;
  90. else
  91. control_flag = QCE_CLK_DISABLE_FIRST;
  92. } else {
  93. if (enable)
  94. control_flag = QCE_CLK_ENABLE_FIRST;
  95. else
  96. control_flag = QCE_BW_REQUEST_RESET_FIRST;
  97. }
  98. switch (control_flag) {
  99. case QCE_CLK_ENABLE_FIRST:
  100. ret = qce_enable_clk(podev->qce);
  101. if (ret) {
  102. pr_err("%s Unable enable clk\n", __func__);
  103. return ret;
  104. }
  105. ret = icc_set_bw(podev->icc_path,
  106. podev->icc_avg_bw, podev->icc_peak_bw);
  107. if (ret) {
  108. pr_err("%s Unable to set high bw\n", __func__);
  109. ret = qce_disable_clk(podev->qce);
  110. if (ret)
  111. pr_err("%s Unable disable clk\n", __func__);
  112. return ret;
  113. }
  114. break;
  115. case QCE_BW_REQUEST_FIRST:
  116. ret = icc_set_bw(podev->icc_path,
  117. podev->icc_avg_bw, podev->icc_peak_bw);
  118. if (ret) {
  119. pr_err("%s Unable to set high bw\n", __func__);
  120. return ret;
  121. }
  122. ret = qce_enable_clk(podev->qce);
  123. if (ret) {
  124. pr_err("%s Unable enable clk\n", __func__);
  125. ret = icc_set_bw(podev->icc_path, 0, 0);
  126. if (ret)
  127. pr_err("%s Unable to set low bw\n", __func__);
  128. return ret;
  129. }
  130. break;
  131. case QCE_CLK_DISABLE_FIRST:
  132. ret = qce_disable_clk(podev->qce);
  133. if (ret) {
  134. pr_err("%s Unable to disable clk\n", __func__);
  135. return ret;
  136. }
  137. ret = icc_set_bw(podev->icc_path, 0, 0);
  138. if (ret) {
  139. pr_err("%s Unable to set low bw\n", __func__);
  140. ret = qce_enable_clk(podev->qce);
  141. if (ret)
  142. pr_err("%s Unable enable clk\n", __func__);
  143. return ret;
  144. }
  145. break;
  146. case QCE_BW_REQUEST_RESET_FIRST:
  147. ret = icc_set_bw(podev->icc_path, 0, 0);
  148. if (ret) {
  149. pr_err("%s Unable to set low bw\n", __func__);
  150. return ret;
  151. }
  152. ret = qce_disable_clk(podev->qce);
  153. if (ret) {
  154. pr_err("%s Unable to disable clk\n", __func__);
  155. ret = icc_set_bw(podev->icc_path,
  156. podev->icc_avg_bw, podev->icc_peak_bw);
  157. if (ret)
  158. pr_err("%s Unable to set high bw\n", __func__);
  159. return ret;
  160. }
  161. break;
  162. default:
  163. return -ENOENT;
  164. }
  165. return 0;
  166. }
  167. static void qcedev_ce_high_bw_req(struct qcedev_control *podev,
  168. bool high_bw_req)
  169. {
  170. int ret = 0;
  171. if(podev == NULL) return;
  172. mutex_lock(&qcedev_sent_bw_req);
  173. if (high_bw_req) {
  174. if (podev->high_bw_req_count == 0) {
  175. ret = qcedev_control_clocks(podev, true);
  176. if (ret)
  177. goto exit_unlock_mutex;
  178. ret = qce_set_irqs(podev->qce, true);
  179. if (ret) {
  180. pr_err("%s: could not enable bam irqs, ret = %d",
  181. __func__, ret);
  182. qcedev_control_clocks(podev, false);
  183. goto exit_unlock_mutex;
  184. }
  185. }
  186. podev->high_bw_req_count++;
  187. } else {
  188. if (podev->high_bw_req_count == 1) {
  189. ret = qce_set_irqs(podev->qce, false);
  190. if (ret) {
  191. pr_err("%s: could not disable bam irqs, ret = %d",
  192. __func__, ret);
  193. goto exit_unlock_mutex;
  194. }
  195. ret = qcedev_control_clocks(podev, false);
  196. if (ret)
  197. goto exit_unlock_mutex;
  198. }
  199. podev->high_bw_req_count--;
  200. }
  201. exit_unlock_mutex:
  202. mutex_unlock(&qcedev_sent_bw_req);
  203. }
  204. #define QCEDEV_MAGIC 0x56434544 /* "qced" */
  205. static int qcedev_open(struct inode *inode, struct file *file);
  206. static int qcedev_release(struct inode *inode, struct file *file);
  207. static int start_cipher_req(struct qcedev_control *podev,
  208. int *current_req_info);
  209. static int start_offload_cipher_req(struct qcedev_control *podev,
  210. int *current_req_info);
  211. static int start_sha_req(struct qcedev_control *podev,
  212. int *current_req_info);
  213. static const struct file_operations qcedev_fops = {
  214. .owner = THIS_MODULE,
  215. .unlocked_ioctl = qcedev_ioctl,
  216. #ifdef CONFIG_COMPAT
  217. .compat_ioctl = compat_qcedev_ioctl,
  218. #endif
  219. .open = qcedev_open,
  220. .release = qcedev_release,
  221. };
  222. static struct qcedev_control qce_dev[] = {
  223. {
  224. .magic = QCEDEV_MAGIC,
  225. },
  226. };
  227. #define MAX_QCE_DEVICE ARRAY_SIZE(qce_dev)
  228. #define DEBUG_MAX_FNAME 16
  229. #define DEBUG_MAX_RW_BUF 1024
  230. struct qcedev_stat {
  231. u32 qcedev_dec_success;
  232. u32 qcedev_dec_fail;
  233. u32 qcedev_enc_success;
  234. u32 qcedev_enc_fail;
  235. u32 qcedev_sha_success;
  236. u32 qcedev_sha_fail;
  237. };
  238. static struct qcedev_stat _qcedev_stat;
  239. static struct dentry *_debug_dent;
  240. static char _debug_read_buf[DEBUG_MAX_RW_BUF];
  241. static int _debug_qcedev;
  242. static struct qcedev_control *qcedev_minor_to_control(unsigned int n)
  243. {
  244. int i;
  245. for (i = 0; i < MAX_QCE_DEVICE; i++) {
  246. if (qce_dev[i].minor == n)
  247. return &qce_dev[n];
  248. }
  249. return NULL;
  250. }
  251. static int qcedev_open(struct inode *inode, struct file *file)
  252. {
  253. struct qcedev_handle *handle;
  254. struct qcedev_control *podev;
  255. podev = qcedev_minor_to_control(MINOR(inode->i_rdev));
  256. if (podev == NULL) {
  257. pr_err("%s: no such device %d\n", __func__,
  258. MINOR(inode->i_rdev));
  259. return -ENOENT;
  260. }
  261. handle = kzalloc(sizeof(struct qcedev_handle), GFP_KERNEL);
  262. if (handle == NULL)
  263. return -ENOMEM;
  264. handle->cntl = podev;
  265. file->private_data = handle;
  266. qcedev_ce_high_bw_req(podev, true);
  267. mutex_init(&handle->registeredbufs.lock);
  268. INIT_LIST_HEAD(&handle->registeredbufs.list);
  269. return 0;
  270. }
  271. static int qcedev_release(struct inode *inode, struct file *file)
  272. {
  273. struct qcedev_control *podev;
  274. struct qcedev_handle *handle;
  275. handle = file->private_data;
  276. podev = handle->cntl;
  277. if (podev != NULL && podev->magic != QCEDEV_MAGIC) {
  278. pr_err("%s: invalid handle %pK\n",
  279. __func__, podev);
  280. }
  281. if (podev)
  282. qcedev_ce_high_bw_req(podev, false);
  283. if (qcedev_unmap_all_buffers(handle))
  284. pr_err("%s: failed to unmap all ion buffers\n", __func__);
  285. kfree_sensitive(handle);
  286. file->private_data = NULL;
  287. return 0;
  288. }
  289. static void req_done(unsigned long data)
  290. {
  291. struct qcedev_control *podev = (struct qcedev_control *)data;
  292. struct qcedev_async_req *areq;
  293. unsigned long flags = 0;
  294. struct qcedev_async_req *new_req = NULL;
  295. spin_lock_irqsave(&podev->lock, flags);
  296. areq = podev->active_command;
  297. podev->active_command = NULL;
  298. if (areq) {
  299. if (!areq->timed_out)
  300. complete(&areq->complete);
  301. areq->state = QCEDEV_REQ_DONE;
  302. }
  303. /* Look through queued requests and wake up the corresponding thread */
  304. if (!list_empty(&podev->ready_commands)) {
  305. new_req = container_of(podev->ready_commands.next,
  306. struct qcedev_async_req, list);
  307. list_del(&new_req->list);
  308. new_req->state = QCEDEV_REQ_CURRENT;
  309. wake_up_interruptible(&new_req->wait_q);
  310. }
  311. spin_unlock_irqrestore(&podev->lock, flags);
  312. }
  313. void qcedev_sha_req_cb(void *cookie, unsigned char *digest,
  314. unsigned char *authdata, int ret)
  315. {
  316. struct qcedev_sha_req *areq;
  317. struct qcedev_control *pdev;
  318. struct qcedev_handle *handle;
  319. uint32_t *auth32 = (uint32_t *)authdata;
  320. areq = (struct qcedev_sha_req *) cookie;
  321. if (!areq || !areq->cookie)
  322. return;
  323. handle = (struct qcedev_handle *) areq->cookie;
  324. pdev = handle->cntl;
  325. if (!pdev)
  326. return;
  327. if (digest)
  328. memcpy(&handle->sha_ctxt.digest[0], digest, 32);
  329. if (authdata) {
  330. handle->sha_ctxt.auth_data[0] = auth32[0];
  331. handle->sha_ctxt.auth_data[1] = auth32[1];
  332. }
  333. tasklet_schedule(&pdev->done_tasklet);
  334. };
  335. void qcedev_cipher_req_cb(void *cookie, unsigned char *icv,
  336. unsigned char *iv, int ret)
  337. {
  338. struct qcedev_cipher_req *areq;
  339. struct qcedev_handle *handle;
  340. struct qcedev_control *podev;
  341. struct qcedev_async_req *qcedev_areq;
  342. areq = (struct qcedev_cipher_req *) cookie;
  343. if (!areq || !areq->cookie)
  344. return;
  345. handle = (struct qcedev_handle *) areq->cookie;
  346. podev = handle->cntl;
  347. if (!podev)
  348. return;
  349. qcedev_areq = podev->active_command;
  350. if (iv)
  351. memcpy(&qcedev_areq->cipher_op_req.iv[0], iv,
  352. qcedev_areq->cipher_op_req.ivlen);
  353. tasklet_schedule(&podev->done_tasklet);
  354. };
  355. static int start_cipher_req(struct qcedev_control *podev,
  356. int *current_req_info)
  357. {
  358. struct qcedev_async_req *qcedev_areq;
  359. struct qce_req creq;
  360. int ret = 0;
  361. memset(&creq, 0, sizeof(creq));
  362. /* start the command on the podev->active_command */
  363. qcedev_areq = podev->active_command;
  364. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  365. if (qcedev_areq->cipher_op_req.use_pmem == QCEDEV_USE_PMEM) {
  366. pr_err("%s: Use of PMEM is not supported\n", __func__);
  367. goto unsupported;
  368. }
  369. creq.pmem = NULL;
  370. switch (qcedev_areq->cipher_op_req.alg) {
  371. case QCEDEV_ALG_DES:
  372. creq.alg = CIPHER_ALG_DES;
  373. break;
  374. case QCEDEV_ALG_3DES:
  375. creq.alg = CIPHER_ALG_3DES;
  376. break;
  377. case QCEDEV_ALG_AES:
  378. creq.alg = CIPHER_ALG_AES;
  379. break;
  380. default:
  381. return -EINVAL;
  382. }
  383. switch (qcedev_areq->cipher_op_req.mode) {
  384. case QCEDEV_AES_MODE_CBC:
  385. case QCEDEV_DES_MODE_CBC:
  386. creq.mode = QCE_MODE_CBC;
  387. break;
  388. case QCEDEV_AES_MODE_ECB:
  389. case QCEDEV_DES_MODE_ECB:
  390. creq.mode = QCE_MODE_ECB;
  391. break;
  392. case QCEDEV_AES_MODE_CTR:
  393. creq.mode = QCE_MODE_CTR;
  394. break;
  395. case QCEDEV_AES_MODE_XTS:
  396. creq.mode = QCE_MODE_XTS;
  397. break;
  398. default:
  399. return -EINVAL;
  400. }
  401. if ((creq.alg == CIPHER_ALG_AES) &&
  402. (creq.mode == QCE_MODE_CTR)) {
  403. creq.dir = QCE_ENCRYPT;
  404. } else {
  405. if (qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC)
  406. creq.dir = QCE_ENCRYPT;
  407. else
  408. creq.dir = QCE_DECRYPT;
  409. }
  410. creq.iv = &qcedev_areq->cipher_op_req.iv[0];
  411. creq.ivsize = qcedev_areq->cipher_op_req.ivlen;
  412. creq.iv_ctr_size = 0;
  413. creq.enckey = &qcedev_areq->cipher_op_req.enckey[0];
  414. creq.encklen = qcedev_areq->cipher_op_req.encklen;
  415. creq.cryptlen = qcedev_areq->cipher_op_req.data_len;
  416. if (qcedev_areq->cipher_op_req.encklen == 0) {
  417. if ((qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC_NO_KEY)
  418. || (qcedev_areq->cipher_op_req.op ==
  419. QCEDEV_OPER_DEC_NO_KEY))
  420. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  421. else {
  422. int i;
  423. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  424. if (qcedev_areq->cipher_op_req.enckey[i] != 0)
  425. break;
  426. }
  427. if ((podev->platform_support.hw_key_support == 1) &&
  428. (i == QCEDEV_MAX_KEY_SIZE))
  429. creq.op = QCE_REQ_ABLK_CIPHER;
  430. else {
  431. ret = -EINVAL;
  432. goto unsupported;
  433. }
  434. }
  435. } else {
  436. creq.op = QCE_REQ_ABLK_CIPHER;
  437. }
  438. creq.qce_cb = qcedev_cipher_req_cb;
  439. creq.areq = (void *)&qcedev_areq->cipher_req;
  440. creq.flags = 0;
  441. creq.offload_op = QCE_OFFLOAD_NONE;
  442. ret = qce_ablk_cipher_req(podev->qce, &creq);
  443. *current_req_info = creq.current_req_info;
  444. unsupported:
  445. qcedev_areq->err = ret ? -ENXIO : 0;
  446. return ret;
  447. };
  448. void qcedev_offload_cipher_req_cb(void *cookie, unsigned char *icv,
  449. unsigned char *iv, int ret)
  450. {
  451. struct qcedev_cipher_req *areq;
  452. struct qcedev_handle *handle;
  453. struct qcedev_control *podev;
  454. struct qcedev_async_req *qcedev_areq;
  455. areq = (struct qcedev_cipher_req *) cookie;
  456. if (!areq || !areq->cookie)
  457. return;
  458. handle = (struct qcedev_handle *) areq->cookie;
  459. podev = handle->cntl;
  460. if (!podev)
  461. return;
  462. qcedev_areq = podev->active_command;
  463. if (iv)
  464. memcpy(&qcedev_areq->offload_cipher_op_req.iv[0], iv,
  465. qcedev_areq->offload_cipher_op_req.ivlen);
  466. tasklet_schedule(&podev->done_tasklet);
  467. }
  468. static int start_offload_cipher_req(struct qcedev_control *podev,
  469. int *current_req_info)
  470. {
  471. struct qcedev_async_req *qcedev_areq;
  472. struct qce_req creq;
  473. u8 patt_sz = 0, proc_data_sz = 0;
  474. int ret = 0;
  475. memset(&creq, 0, sizeof(creq));
  476. /* Start the command on the podev->active_command */
  477. qcedev_areq = podev->active_command;
  478. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  479. switch (qcedev_areq->offload_cipher_op_req.alg) {
  480. case QCEDEV_ALG_AES:
  481. creq.alg = CIPHER_ALG_AES;
  482. break;
  483. default:
  484. return -EINVAL;
  485. }
  486. switch (qcedev_areq->offload_cipher_op_req.mode) {
  487. case QCEDEV_AES_MODE_CBC:
  488. creq.mode = QCE_MODE_CBC;
  489. break;
  490. case QCEDEV_AES_MODE_CTR:
  491. creq.mode = QCE_MODE_CTR;
  492. break;
  493. default:
  494. return -EINVAL;
  495. }
  496. if (qcedev_areq->offload_cipher_op_req.is_copy_op) {
  497. creq.dir = QCE_ENCRYPT;
  498. } else {
  499. switch(qcedev_areq->offload_cipher_op_req.op) {
  500. case QCEDEV_OFFLOAD_HLOS_HLOS:
  501. case QCEDEV_OFFLOAD_HLOS_CPB:
  502. creq.dir = QCE_DECRYPT;
  503. break;
  504. case QCEDEV_OFFLOAD_CPB_HLOS:
  505. creq.dir = QCE_ENCRYPT;
  506. break;
  507. default:
  508. return -EINVAL;
  509. }
  510. }
  511. creq.iv = &qcedev_areq->offload_cipher_op_req.iv[0];
  512. creq.ivsize = qcedev_areq->offload_cipher_op_req.ivlen;
  513. creq.iv_ctr_size = qcedev_areq->offload_cipher_op_req.iv_ctr_size;
  514. creq.encklen = qcedev_areq->offload_cipher_op_req.encklen;
  515. /* OFFLOAD use cases use PIPE keys so no need to set keys */
  516. creq.flags = QCEDEV_CTX_USE_PIPE_KEY;
  517. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  518. creq.offload_op = (int)qcedev_areq->offload_cipher_op_req.op;
  519. if (qcedev_areq->offload_cipher_op_req.is_copy_op)
  520. creq.is_copy_op = true;
  521. creq.cryptlen = qcedev_areq->offload_cipher_op_req.data_len;
  522. creq.qce_cb = qcedev_offload_cipher_req_cb;
  523. creq.areq = (void *)&qcedev_areq->cipher_req;
  524. patt_sz = qcedev_areq->offload_cipher_op_req.pattern_info.patt_sz;
  525. proc_data_sz =
  526. qcedev_areq->offload_cipher_op_req.pattern_info.proc_data_sz;
  527. creq.is_pattern_valid =
  528. qcedev_areq->offload_cipher_op_req.is_pattern_valid;
  529. if (creq.is_pattern_valid) {
  530. creq.pattern_info = 0x1;
  531. if (patt_sz)
  532. creq.pattern_info |= (patt_sz - 1) << 4;
  533. if (proc_data_sz)
  534. creq.pattern_info |= (proc_data_sz - 1) << 8;
  535. creq.pattern_info |=
  536. qcedev_areq->offload_cipher_op_req.pattern_info.patt_offset << 12;
  537. }
  538. creq.block_offset = qcedev_areq->offload_cipher_op_req.block_offset;
  539. ret = qce_ablk_cipher_req(podev->qce, &creq);
  540. *current_req_info = creq.current_req_info;
  541. qcedev_areq->err = ret ? -ENXIO : 0;
  542. return ret;
  543. }
  544. static int start_sha_req(struct qcedev_control *podev,
  545. int *current_req_info)
  546. {
  547. struct qcedev_async_req *qcedev_areq;
  548. struct qce_sha_req sreq;
  549. int ret = 0;
  550. struct qcedev_handle *handle;
  551. /* start the command on the podev->active_command */
  552. qcedev_areq = podev->active_command;
  553. handle = qcedev_areq->handle;
  554. switch (qcedev_areq->sha_op_req.alg) {
  555. case QCEDEV_ALG_SHA1:
  556. sreq.alg = QCE_HASH_SHA1;
  557. break;
  558. case QCEDEV_ALG_SHA256:
  559. sreq.alg = QCE_HASH_SHA256;
  560. break;
  561. case QCEDEV_ALG_SHA1_HMAC:
  562. if (podev->ce_support.sha_hmac) {
  563. sreq.alg = QCE_HASH_SHA1_HMAC;
  564. sreq.authkey = &handle->sha_ctxt.authkey[0];
  565. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  566. } else {
  567. sreq.alg = QCE_HASH_SHA1;
  568. sreq.authkey = NULL;
  569. }
  570. break;
  571. case QCEDEV_ALG_SHA256_HMAC:
  572. if (podev->ce_support.sha_hmac) {
  573. sreq.alg = QCE_HASH_SHA256_HMAC;
  574. sreq.authkey = &handle->sha_ctxt.authkey[0];
  575. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  576. } else {
  577. sreq.alg = QCE_HASH_SHA256;
  578. sreq.authkey = NULL;
  579. }
  580. break;
  581. case QCEDEV_ALG_AES_CMAC:
  582. sreq.alg = QCE_HASH_AES_CMAC;
  583. sreq.authkey = &handle->sha_ctxt.authkey[0];
  584. sreq.authklen = qcedev_areq->sha_op_req.authklen;
  585. break;
  586. default:
  587. pr_err("Algorithm %d not supported, exiting\n",
  588. qcedev_areq->sha_op_req.alg);
  589. return -EINVAL;
  590. }
  591. qcedev_areq->sha_req.cookie = handle;
  592. sreq.qce_cb = qcedev_sha_req_cb;
  593. if (qcedev_areq->sha_op_req.alg != QCEDEV_ALG_AES_CMAC) {
  594. sreq.auth_data[0] = handle->sha_ctxt.auth_data[0];
  595. sreq.auth_data[1] = handle->sha_ctxt.auth_data[1];
  596. sreq.auth_data[2] = handle->sha_ctxt.auth_data[2];
  597. sreq.auth_data[3] = handle->sha_ctxt.auth_data[3];
  598. sreq.digest = &handle->sha_ctxt.digest[0];
  599. sreq.first_blk = handle->sha_ctxt.first_blk;
  600. sreq.last_blk = handle->sha_ctxt.last_blk;
  601. }
  602. sreq.size = qcedev_areq->sha_req.sreq.nbytes;
  603. sreq.src = qcedev_areq->sha_req.sreq.src;
  604. sreq.areq = (void *)&qcedev_areq->sha_req;
  605. sreq.flags = 0;
  606. ret = qce_process_sha_req(podev->qce, &sreq);
  607. *current_req_info = sreq.current_req_info;
  608. qcedev_areq->err = ret ? -ENXIO : 0;
  609. return ret;
  610. };
  611. static void qcedev_check_crypto_status(
  612. struct qcedev_async_req *qcedev_areq, void *handle)
  613. {
  614. struct qce_error error = {0};
  615. qcedev_areq->offload_cipher_op_req.err = QCEDEV_OFFLOAD_NO_ERROR;
  616. qce_get_crypto_status(handle, &error);
  617. if (error.timer_error) {
  618. qcedev_areq->offload_cipher_op_req.err =
  619. QCEDEV_OFFLOAD_KEY_TIMER_EXPIRED_ERROR;
  620. } else if (error.key_paused) {
  621. qcedev_areq->offload_cipher_op_req.err =
  622. QCEDEV_OFFLOAD_KEY_PAUSE_ERROR;
  623. } else if (error.generic_error) {
  624. qcedev_areq->offload_cipher_op_req.err =
  625. QCEDEV_OFFLOAD_GENERIC_ERROR;
  626. }
  627. return;
  628. }
  629. #define MAX_RETRIES 333
  630. static int submit_req(struct qcedev_async_req *qcedev_areq,
  631. struct qcedev_handle *handle)
  632. {
  633. struct qcedev_control *podev;
  634. unsigned long flags = 0;
  635. int ret = 0;
  636. struct qcedev_stat *pstat;
  637. int current_req_info = 0;
  638. int wait = MAX_CRYPTO_WAIT_TIME;
  639. struct qcedev_async_req *new_req = NULL;
  640. int retries = 0;
  641. int req_wait = MAX_REQUEST_TIME;
  642. unsigned int crypto_wait = 0;
  643. qcedev_areq->err = 0;
  644. podev = handle->cntl;
  645. init_waitqueue_head(&qcedev_areq->wait_q);
  646. spin_lock_irqsave(&podev->lock, flags);
  647. /*
  648. * Service only one crypto request at a time.
  649. * Any other new requests are queued in ready_commands and woken up
  650. * only when the active command has finished successfully or when the
  651. * request times out or when the command failed when setting up.
  652. */
  653. do {
  654. if (podev->active_command == NULL) {
  655. podev->active_command = qcedev_areq;
  656. qcedev_areq->state = QCEDEV_REQ_SUBMITTED;
  657. switch (qcedev_areq->op_type) {
  658. case QCEDEV_CRYPTO_OPER_CIPHER:
  659. ret = start_cipher_req(podev,
  660. &current_req_info);
  661. crypto_wait = MAX_CRYPTO_WAIT_TIME;
  662. break;
  663. case QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER:
  664. ret = start_offload_cipher_req(podev,
  665. &current_req_info);
  666. crypto_wait = MAX_OFFLOAD_CRYPTO_WAIT_TIME;
  667. break;
  668. default:
  669. crypto_wait = MAX_CRYPTO_WAIT_TIME;
  670. ret = start_sha_req(podev,
  671. &current_req_info);
  672. break;
  673. }
  674. } else {
  675. list_add_tail(&qcedev_areq->list,
  676. &podev->ready_commands);
  677. qcedev_areq->state = QCEDEV_REQ_WAITING;
  678. req_wait = wait_event_interruptible_lock_irq_timeout(
  679. qcedev_areq->wait_q,
  680. (qcedev_areq->state == QCEDEV_REQ_CURRENT),
  681. podev->lock,
  682. msecs_to_jiffies(MAX_REQUEST_TIME));
  683. if ((req_wait == 0) || (req_wait == -ERESTARTSYS)) {
  684. pr_err("%s: request timed out, req_wait = %d\n",
  685. __func__, req_wait);
  686. list_del(&qcedev_areq->list);
  687. podev->active_command = NULL;
  688. spin_unlock_irqrestore(&podev->lock, flags);
  689. return qcedev_areq->err;
  690. }
  691. }
  692. } while (qcedev_areq->state != QCEDEV_REQ_SUBMITTED);
  693. if (ret != 0) {
  694. podev->active_command = NULL;
  695. /*
  696. * Look through queued requests and wake up the corresponding
  697. * thread.
  698. */
  699. if (!list_empty(&podev->ready_commands)) {
  700. new_req = container_of(podev->ready_commands.next,
  701. struct qcedev_async_req, list);
  702. list_del(&new_req->list);
  703. new_req->state = QCEDEV_REQ_CURRENT;
  704. wake_up_interruptible(&new_req->wait_q);
  705. }
  706. }
  707. spin_unlock_irqrestore(&podev->lock, flags);
  708. qcedev_areq->timed_out = false;
  709. if (ret == 0)
  710. wait = wait_for_completion_timeout(&qcedev_areq->complete,
  711. msecs_to_jiffies(crypto_wait));
  712. if (!wait) {
  713. /*
  714. * This means wait timed out, and the callback routine was not
  715. * exercised. The callback sequence does some housekeeping which
  716. * would be missed here, hence having a call to qce here to do
  717. * that.
  718. */
  719. pr_err("%s: wait timed out, req info = %d\n", __func__,
  720. current_req_info);
  721. spin_lock_irqsave(&podev->lock, flags);
  722. qcedev_areq->timed_out = true;
  723. spin_unlock_irqrestore(&podev->lock, flags);
  724. qcedev_check_crypto_status(qcedev_areq, podev->qce);
  725. if (qcedev_areq->offload_cipher_op_req.err ==
  726. QCEDEV_OFFLOAD_NO_ERROR) {
  727. pr_err("%s: no error, wait for request to be done", __func__);
  728. while (qcedev_areq->state != QCEDEV_REQ_DONE &&
  729. retries < MAX_RETRIES) {
  730. usleep_range(3000, 5000);
  731. retries++;
  732. pr_err("%s: waiting for req state to be done, retries = %d",
  733. __func__, retries);
  734. }
  735. return 0;
  736. }
  737. spin_lock_irqsave(&podev->lock, flags);
  738. ret = qce_manage_timeout(podev->qce, current_req_info);
  739. if (ret)
  740. pr_err("%s: error during manage timeout", __func__);
  741. spin_unlock_irqrestore(&podev->lock, flags);
  742. req_done((unsigned long) podev);
  743. if (qcedev_areq->offload_cipher_op_req.err !=
  744. QCEDEV_OFFLOAD_NO_ERROR)
  745. return 0;
  746. }
  747. if (ret)
  748. qcedev_areq->err = -EIO;
  749. pstat = &_qcedev_stat;
  750. if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER) {
  751. switch (qcedev_areq->cipher_op_req.op) {
  752. case QCEDEV_OPER_DEC:
  753. if (qcedev_areq->err)
  754. pstat->qcedev_dec_fail++;
  755. else
  756. pstat->qcedev_dec_success++;
  757. break;
  758. case QCEDEV_OPER_ENC:
  759. if (qcedev_areq->err)
  760. pstat->qcedev_enc_fail++;
  761. else
  762. pstat->qcedev_enc_success++;
  763. break;
  764. default:
  765. break;
  766. }
  767. } else if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER) {
  768. //Do nothing
  769. } else {
  770. if (qcedev_areq->err)
  771. pstat->qcedev_sha_fail++;
  772. else
  773. pstat->qcedev_sha_success++;
  774. }
  775. return qcedev_areq->err;
  776. }
  777. static int qcedev_sha_init(struct qcedev_async_req *areq,
  778. struct qcedev_handle *handle)
  779. {
  780. struct qcedev_sha_ctxt *sha_ctxt = &handle->sha_ctxt;
  781. memset(sha_ctxt, 0, sizeof(struct qcedev_sha_ctxt));
  782. sha_ctxt->first_blk = 1;
  783. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  784. (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)) {
  785. memcpy(&sha_ctxt->digest[0],
  786. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  787. sha_ctxt->diglen = SHA1_DIGEST_SIZE;
  788. } else {
  789. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA256) ||
  790. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)) {
  791. memcpy(&sha_ctxt->digest[0],
  792. &_std_init_vector_sha256_uint8[0],
  793. SHA256_DIGEST_SIZE);
  794. sha_ctxt->diglen = SHA256_DIGEST_SIZE;
  795. }
  796. }
  797. sha_ctxt->init_done = true;
  798. return 0;
  799. }
  800. static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq,
  801. struct qcedev_handle *handle,
  802. struct scatterlist *sg_src)
  803. {
  804. int err = 0;
  805. int i = 0;
  806. uint32_t total;
  807. uint8_t *user_src = NULL;
  808. uint8_t *k_src = NULL;
  809. uint8_t *k_buf_src = NULL;
  810. uint32_t buf_size = 0;
  811. uint8_t *k_align_src = NULL;
  812. uint32_t sha_pad_len = 0;
  813. uint32_t trailing_buf_len = 0;
  814. uint32_t t_buf = handle->sha_ctxt.trailing_buf_len;
  815. uint32_t sha_block_size;
  816. total = qcedev_areq->sha_op_req.data_len + t_buf;
  817. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1)
  818. sha_block_size = SHA1_BLOCK_SIZE;
  819. else
  820. sha_block_size = SHA256_BLOCK_SIZE;
  821. if (total <= sha_block_size) {
  822. uint32_t len = qcedev_areq->sha_op_req.data_len;
  823. i = 0;
  824. k_src = &handle->sha_ctxt.trailing_buf[t_buf];
  825. /* Copy data from user src(s) */
  826. while (len > 0) {
  827. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  828. if (user_src && copy_from_user(k_src,
  829. (void __user *)user_src,
  830. qcedev_areq->sha_op_req.data[i].len))
  831. return -EFAULT;
  832. len -= qcedev_areq->sha_op_req.data[i].len;
  833. k_src += qcedev_areq->sha_op_req.data[i].len;
  834. i++;
  835. }
  836. handle->sha_ctxt.trailing_buf_len = total;
  837. return 0;
  838. }
  839. buf_size = total + CACHE_LINE_SIZE * 2;
  840. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  841. if (k_buf_src == NULL)
  842. return -ENOMEM;
  843. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  844. CACHE_LINE_SIZE);
  845. k_src = k_align_src;
  846. /* check for trailing buffer from previous updates and append it */
  847. if (t_buf > 0) {
  848. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  849. t_buf);
  850. k_src += t_buf;
  851. }
  852. /* Copy data from user src(s) */
  853. user_src = qcedev_areq->sha_op_req.data[0].vaddr;
  854. if (user_src && copy_from_user(k_src,
  855. (void __user *)user_src,
  856. qcedev_areq->sha_op_req.data[0].len)) {
  857. memset(k_buf_src, 0, buf_size);
  858. kfree(k_buf_src);
  859. return -EFAULT;
  860. }
  861. k_src += qcedev_areq->sha_op_req.data[0].len;
  862. for (i = 1; i < qcedev_areq->sha_op_req.entries; i++) {
  863. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  864. if (user_src && copy_from_user(k_src,
  865. (void __user *)user_src,
  866. qcedev_areq->sha_op_req.data[i].len)) {
  867. memset(k_buf_src, 0, buf_size);
  868. kfree(k_buf_src);
  869. return -EFAULT;
  870. }
  871. k_src += qcedev_areq->sha_op_req.data[i].len;
  872. }
  873. /* get new trailing buffer */
  874. sha_pad_len = ALIGN(total, CE_SHA_BLOCK_SIZE) - total;
  875. trailing_buf_len = CE_SHA_BLOCK_SIZE - sha_pad_len;
  876. qcedev_areq->sha_req.sreq.src = sg_src;
  877. sg_init_one(qcedev_areq->sha_req.sreq.src, k_align_src,
  878. total-trailing_buf_len);
  879. qcedev_areq->sha_req.sreq.nbytes = total - trailing_buf_len;
  880. /* update sha_ctxt trailing buf content to new trailing buf */
  881. if (trailing_buf_len > 0) {
  882. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  883. memcpy(&handle->sha_ctxt.trailing_buf[0],
  884. (k_src - trailing_buf_len),
  885. trailing_buf_len);
  886. }
  887. handle->sha_ctxt.trailing_buf_len = trailing_buf_len;
  888. err = submit_req(qcedev_areq, handle);
  889. handle->sha_ctxt.last_blk = 0;
  890. handle->sha_ctxt.first_blk = 0;
  891. memset(k_buf_src, 0, buf_size);
  892. kfree(k_buf_src);
  893. return err;
  894. }
  895. static int qcedev_sha_update(struct qcedev_async_req *qcedev_areq,
  896. struct qcedev_handle *handle,
  897. struct scatterlist *sg_src)
  898. {
  899. int err = 0;
  900. int i = 0;
  901. int j = 0;
  902. int k = 0;
  903. int num_entries = 0;
  904. uint32_t total = 0;
  905. if (!handle->sha_ctxt.init_done) {
  906. pr_err("%s Init was not called\n", __func__);
  907. return -EINVAL;
  908. }
  909. if (qcedev_areq->sha_op_req.data_len > QCE_MAX_OPER_DATA) {
  910. struct qcedev_sha_op_req *saved_req;
  911. struct qcedev_sha_op_req req;
  912. struct qcedev_sha_op_req *sreq = &qcedev_areq->sha_op_req;
  913. uint32_t req_size = 0;
  914. req_size = sizeof(struct qcedev_sha_op_req);
  915. /* save the original req structure */
  916. saved_req =
  917. kmalloc(req_size, GFP_KERNEL);
  918. if (saved_req == NULL) {
  919. pr_err("%s:Can't Allocate mem:saved_req 0x%lx\n",
  920. __func__, (uintptr_t)saved_req);
  921. return -ENOMEM;
  922. }
  923. memcpy(&req, sreq, sizeof(*sreq));
  924. memcpy(saved_req, sreq, sizeof(*sreq));
  925. i = 0;
  926. /* Address 32 KB at a time */
  927. while ((i < req.entries) && (err == 0)) {
  928. if (sreq->data[i].len > QCE_MAX_OPER_DATA) {
  929. sreq->data[0].len = QCE_MAX_OPER_DATA;
  930. if (i > 0) {
  931. sreq->data[0].vaddr =
  932. sreq->data[i].vaddr;
  933. }
  934. sreq->data_len = QCE_MAX_OPER_DATA;
  935. sreq->entries = 1;
  936. err = qcedev_sha_update_max_xfer(qcedev_areq,
  937. handle, sg_src);
  938. sreq->data[i].len = req.data[i].len -
  939. QCE_MAX_OPER_DATA;
  940. sreq->data[i].vaddr = req.data[i].vaddr +
  941. QCE_MAX_OPER_DATA;
  942. req.data[i].vaddr = sreq->data[i].vaddr;
  943. req.data[i].len = sreq->data[i].len;
  944. } else {
  945. total = 0;
  946. for (j = i; j < req.entries; j++) {
  947. num_entries++;
  948. if ((total + sreq->data[j].len) >=
  949. QCE_MAX_OPER_DATA) {
  950. sreq->data[j].len =
  951. (QCE_MAX_OPER_DATA - total);
  952. total = QCE_MAX_OPER_DATA;
  953. break;
  954. }
  955. total += sreq->data[j].len;
  956. }
  957. sreq->data_len = total;
  958. if (i > 0)
  959. for (k = 0; k < num_entries; k++) {
  960. sreq->data[k].len =
  961. sreq->data[i+k].len;
  962. sreq->data[k].vaddr =
  963. sreq->data[i+k].vaddr;
  964. }
  965. sreq->entries = num_entries;
  966. i = j;
  967. err = qcedev_sha_update_max_xfer(qcedev_areq,
  968. handle, sg_src);
  969. num_entries = 0;
  970. sreq->data[i].vaddr = req.data[i].vaddr +
  971. sreq->data[i].len;
  972. sreq->data[i].len = req.data[i].len -
  973. sreq->data[i].len;
  974. req.data[i].vaddr = sreq->data[i].vaddr;
  975. req.data[i].len = sreq->data[i].len;
  976. if (sreq->data[i].len == 0)
  977. i++;
  978. }
  979. } /* end of while ((i < req.entries) && (err == 0)) */
  980. /* Restore the original req structure */
  981. for (i = 0; i < saved_req->entries; i++) {
  982. sreq->data[i].len = saved_req->data[i].len;
  983. sreq->data[i].vaddr = saved_req->data[i].vaddr;
  984. }
  985. sreq->entries = saved_req->entries;
  986. sreq->data_len = saved_req->data_len;
  987. memset(saved_req, 0, req_size);
  988. kfree(saved_req);
  989. } else
  990. err = qcedev_sha_update_max_xfer(qcedev_areq, handle, sg_src);
  991. return err;
  992. }
  993. static int qcedev_sha_final(struct qcedev_async_req *qcedev_areq,
  994. struct qcedev_handle *handle)
  995. {
  996. int err = 0;
  997. struct scatterlist sg_src;
  998. uint32_t total;
  999. uint8_t *k_buf_src = NULL;
  1000. uint32_t buf_size = 0;
  1001. uint8_t *k_align_src = NULL;
  1002. if (!handle->sha_ctxt.init_done) {
  1003. pr_err("%s Init was not called\n", __func__);
  1004. return -EINVAL;
  1005. }
  1006. handle->sha_ctxt.last_blk = 1;
  1007. total = handle->sha_ctxt.trailing_buf_len;
  1008. buf_size = total + CACHE_LINE_SIZE * 2;
  1009. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1010. if (k_buf_src == NULL)
  1011. return -ENOMEM;
  1012. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  1013. CACHE_LINE_SIZE);
  1014. memcpy(k_align_src, &handle->sha_ctxt.trailing_buf[0], total);
  1015. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  1016. sg_init_one(qcedev_areq->sha_req.sreq.src, k_align_src, total);
  1017. qcedev_areq->sha_req.sreq.nbytes = total;
  1018. err = submit_req(qcedev_areq, handle);
  1019. handle->sha_ctxt.first_blk = 0;
  1020. handle->sha_ctxt.last_blk = 0;
  1021. handle->sha_ctxt.auth_data[0] = 0;
  1022. handle->sha_ctxt.auth_data[1] = 0;
  1023. handle->sha_ctxt.trailing_buf_len = 0;
  1024. handle->sha_ctxt.init_done = false;
  1025. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  1026. memset(k_buf_src, 0, buf_size);
  1027. kfree(k_buf_src);
  1028. qcedev_areq->sha_req.sreq.src = NULL;
  1029. return err;
  1030. }
  1031. static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq,
  1032. struct qcedev_handle *handle,
  1033. struct scatterlist *sg_src)
  1034. {
  1035. int err = 0;
  1036. int i = 0;
  1037. uint32_t total;
  1038. uint8_t *user_src = NULL;
  1039. uint8_t *k_src = NULL;
  1040. uint8_t *k_buf_src = NULL;
  1041. uint32_t buf_size = 0;
  1042. total = qcedev_areq->sha_op_req.data_len;
  1043. if ((qcedev_areq->sha_op_req.authklen != QCEDEV_AES_KEY_128) &&
  1044. (qcedev_areq->sha_op_req.authklen != QCEDEV_AES_KEY_256)) {
  1045. pr_err("%s: unsupported key length\n", __func__);
  1046. return -EINVAL;
  1047. }
  1048. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  1049. (void __user *)qcedev_areq->sha_op_req.authkey,
  1050. qcedev_areq->sha_op_req.authklen))
  1051. return -EFAULT;
  1052. if (total > U32_MAX - CACHE_LINE_SIZE * 2)
  1053. return -EINVAL;
  1054. buf_size = total + CACHE_LINE_SIZE * 2;
  1055. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1056. if (k_buf_src == NULL)
  1057. return -ENOMEM;
  1058. k_src = k_buf_src;
  1059. /* Copy data from user src(s) */
  1060. user_src = qcedev_areq->sha_op_req.data[0].vaddr;
  1061. for (i = 0; i < qcedev_areq->sha_op_req.entries; i++) {
  1062. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  1063. if (user_src && copy_from_user(k_src, (void __user *)user_src,
  1064. qcedev_areq->sha_op_req.data[i].len)) {
  1065. memset(k_buf_src, 0, buf_size);
  1066. kfree(k_buf_src);
  1067. return -EFAULT;
  1068. }
  1069. k_src += qcedev_areq->sha_op_req.data[i].len;
  1070. }
  1071. qcedev_areq->sha_req.sreq.src = sg_src;
  1072. sg_init_one(qcedev_areq->sha_req.sreq.src, k_buf_src, total);
  1073. qcedev_areq->sha_req.sreq.nbytes = total;
  1074. handle->sha_ctxt.diglen = qcedev_areq->sha_op_req.diglen;
  1075. err = submit_req(qcedev_areq, handle);
  1076. memset(k_buf_src, 0, buf_size);
  1077. kfree(k_buf_src);
  1078. return err;
  1079. }
  1080. static int qcedev_set_hmac_auth_key(struct qcedev_async_req *areq,
  1081. struct qcedev_handle *handle,
  1082. struct scatterlist *sg_src)
  1083. {
  1084. int err = 0;
  1085. if (areq->sha_op_req.authklen <= QCEDEV_MAX_KEY_SIZE) {
  1086. qcedev_sha_init(areq, handle);
  1087. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  1088. (void __user *)areq->sha_op_req.authkey,
  1089. areq->sha_op_req.authklen))
  1090. return -EFAULT;
  1091. } else {
  1092. struct qcedev_async_req authkey_areq;
  1093. uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
  1094. init_completion(&authkey_areq.complete);
  1095. authkey_areq.sha_op_req.entries = 1;
  1096. authkey_areq.sha_op_req.data[0].vaddr =
  1097. areq->sha_op_req.authkey;
  1098. authkey_areq.sha_op_req.data[0].len = areq->sha_op_req.authklen;
  1099. authkey_areq.sha_op_req.data_len = areq->sha_op_req.authklen;
  1100. authkey_areq.sha_op_req.diglen = 0;
  1101. authkey_areq.handle = handle;
  1102. memset(&authkey_areq.sha_op_req.digest[0], 0,
  1103. QCEDEV_MAX_SHA_DIGEST);
  1104. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  1105. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA1;
  1106. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)
  1107. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA256;
  1108. authkey_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
  1109. qcedev_sha_init(&authkey_areq, handle);
  1110. err = qcedev_sha_update(&authkey_areq, handle, sg_src);
  1111. if (!err)
  1112. err = qcedev_sha_final(&authkey_areq, handle);
  1113. else
  1114. return err;
  1115. memcpy(&authkey[0], &handle->sha_ctxt.digest[0],
  1116. handle->sha_ctxt.diglen);
  1117. qcedev_sha_init(areq, handle);
  1118. memcpy(&handle->sha_ctxt.authkey[0], &authkey[0],
  1119. handle->sha_ctxt.diglen);
  1120. }
  1121. return err;
  1122. }
  1123. static int qcedev_hmac_get_ohash(struct qcedev_async_req *qcedev_areq,
  1124. struct qcedev_handle *handle)
  1125. {
  1126. int err = 0;
  1127. struct scatterlist sg_src;
  1128. uint8_t *k_src = NULL;
  1129. uint32_t sha_block_size = 0;
  1130. uint32_t sha_digest_size = 0;
  1131. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  1132. sha_digest_size = SHA1_DIGEST_SIZE;
  1133. sha_block_size = SHA1_BLOCK_SIZE;
  1134. } else {
  1135. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  1136. sha_digest_size = SHA256_DIGEST_SIZE;
  1137. sha_block_size = SHA256_BLOCK_SIZE;
  1138. }
  1139. }
  1140. k_src = kmalloc(sha_block_size, GFP_KERNEL);
  1141. if (k_src == NULL)
  1142. return -ENOMEM;
  1143. /* check for trailing buffer from previous updates and append it */
  1144. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  1145. handle->sha_ctxt.trailing_buf_len);
  1146. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  1147. sg_init_one(qcedev_areq->sha_req.sreq.src, k_src, sha_block_size);
  1148. qcedev_areq->sha_req.sreq.nbytes = sha_block_size;
  1149. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  1150. memcpy(&handle->sha_ctxt.trailing_buf[0], &handle->sha_ctxt.digest[0],
  1151. sha_digest_size);
  1152. handle->sha_ctxt.trailing_buf_len = sha_digest_size;
  1153. handle->sha_ctxt.first_blk = 1;
  1154. handle->sha_ctxt.last_blk = 0;
  1155. handle->sha_ctxt.auth_data[0] = 0;
  1156. handle->sha_ctxt.auth_data[1] = 0;
  1157. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  1158. memcpy(&handle->sha_ctxt.digest[0],
  1159. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  1160. handle->sha_ctxt.diglen = SHA1_DIGEST_SIZE;
  1161. }
  1162. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  1163. memcpy(&handle->sha_ctxt.digest[0],
  1164. &_std_init_vector_sha256_uint8[0], SHA256_DIGEST_SIZE);
  1165. handle->sha_ctxt.diglen = SHA256_DIGEST_SIZE;
  1166. }
  1167. err = submit_req(qcedev_areq, handle);
  1168. handle->sha_ctxt.last_blk = 0;
  1169. handle->sha_ctxt.first_blk = 0;
  1170. memset(k_src, 0, sha_block_size);
  1171. kfree(k_src);
  1172. qcedev_areq->sha_req.sreq.src = NULL;
  1173. return err;
  1174. }
  1175. static int qcedev_hmac_update_iokey(struct qcedev_async_req *areq,
  1176. struct qcedev_handle *handle, bool ikey)
  1177. {
  1178. int i;
  1179. uint32_t constant;
  1180. uint32_t sha_block_size;
  1181. if (ikey)
  1182. constant = 0x36;
  1183. else
  1184. constant = 0x5c;
  1185. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  1186. sha_block_size = SHA1_BLOCK_SIZE;
  1187. else
  1188. sha_block_size = SHA256_BLOCK_SIZE;
  1189. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  1190. for (i = 0; i < sha_block_size; i++)
  1191. handle->sha_ctxt.trailing_buf[i] =
  1192. (handle->sha_ctxt.authkey[i] ^ constant);
  1193. handle->sha_ctxt.trailing_buf_len = sha_block_size;
  1194. return 0;
  1195. }
  1196. static int qcedev_hmac_init(struct qcedev_async_req *areq,
  1197. struct qcedev_handle *handle,
  1198. struct scatterlist *sg_src)
  1199. {
  1200. int err;
  1201. struct qcedev_control *podev = handle->cntl;
  1202. err = qcedev_set_hmac_auth_key(areq, handle, sg_src);
  1203. if (err)
  1204. return err;
  1205. if (!podev->ce_support.sha_hmac)
  1206. qcedev_hmac_update_iokey(areq, handle, true);
  1207. return 0;
  1208. }
  1209. static int qcedev_hmac_final(struct qcedev_async_req *areq,
  1210. struct qcedev_handle *handle)
  1211. {
  1212. int err;
  1213. struct qcedev_control *podev = handle->cntl;
  1214. err = qcedev_sha_final(areq, handle);
  1215. if (podev->ce_support.sha_hmac)
  1216. return err;
  1217. qcedev_hmac_update_iokey(areq, handle, false);
  1218. err = qcedev_hmac_get_ohash(areq, handle);
  1219. if (err)
  1220. return err;
  1221. err = qcedev_sha_final(areq, handle);
  1222. return err;
  1223. }
  1224. static int qcedev_hash_init(struct qcedev_async_req *areq,
  1225. struct qcedev_handle *handle,
  1226. struct scatterlist *sg_src)
  1227. {
  1228. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1229. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1230. return qcedev_sha_init(areq, handle);
  1231. else
  1232. return qcedev_hmac_init(areq, handle, sg_src);
  1233. }
  1234. static int qcedev_hash_update(struct qcedev_async_req *qcedev_areq,
  1235. struct qcedev_handle *handle,
  1236. struct scatterlist *sg_src)
  1237. {
  1238. return qcedev_sha_update(qcedev_areq, handle, sg_src);
  1239. }
  1240. static int qcedev_hash_final(struct qcedev_async_req *areq,
  1241. struct qcedev_handle *handle)
  1242. {
  1243. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1244. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1245. return qcedev_sha_final(areq, handle);
  1246. else
  1247. return qcedev_hmac_final(areq, handle);
  1248. }
  1249. static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
  1250. int *di, struct qcedev_handle *handle,
  1251. uint8_t *k_align_src)
  1252. {
  1253. int err = 0;
  1254. int i = 0;
  1255. int dst_i = *di;
  1256. struct scatterlist sg_src;
  1257. uint32_t byteoffset = 0;
  1258. uint8_t *user_src = NULL;
  1259. uint8_t *k_align_dst = k_align_src;
  1260. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1261. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1262. byteoffset = areq->cipher_op_req.byteoffset;
  1263. user_src = areq->cipher_op_req.vbuf.src[0].vaddr;
  1264. if (user_src && copy_from_user((k_align_src + byteoffset),
  1265. (void __user *)user_src,
  1266. areq->cipher_op_req.vbuf.src[0].len))
  1267. return -EFAULT;
  1268. k_align_src += byteoffset + areq->cipher_op_req.vbuf.src[0].len;
  1269. for (i = 1; i < areq->cipher_op_req.entries; i++) {
  1270. user_src = areq->cipher_op_req.vbuf.src[i].vaddr;
  1271. if (user_src && copy_from_user(k_align_src,
  1272. (void __user *)user_src,
  1273. areq->cipher_op_req.vbuf.src[i].len)) {
  1274. return -EFAULT;
  1275. }
  1276. k_align_src += areq->cipher_op_req.vbuf.src[i].len;
  1277. }
  1278. /* restore src beginning */
  1279. k_align_src = k_align_dst;
  1280. areq->cipher_op_req.data_len += byteoffset;
  1281. areq->cipher_req.creq.src = (struct scatterlist *) &sg_src;
  1282. areq->cipher_req.creq.dst = (struct scatterlist *) &sg_src;
  1283. /* In place encryption/decryption */
  1284. sg_init_one(areq->cipher_req.creq.src,
  1285. k_align_dst,
  1286. areq->cipher_op_req.data_len);
  1287. areq->cipher_req.creq.cryptlen = areq->cipher_op_req.data_len;
  1288. areq->cipher_req.creq.iv = areq->cipher_op_req.iv;
  1289. areq->cipher_op_req.entries = 1;
  1290. err = submit_req(areq, handle);
  1291. /* copy data to destination buffer*/
  1292. creq->data_len -= byteoffset;
  1293. while (creq->data_len > 0) {
  1294. if (creq->vbuf.dst[dst_i].len <= creq->data_len) {
  1295. if (err == 0 && copy_to_user(
  1296. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1297. (k_align_dst + byteoffset),
  1298. creq->vbuf.dst[dst_i].len)) {
  1299. err = -EFAULT;
  1300. goto exit;
  1301. }
  1302. k_align_dst += creq->vbuf.dst[dst_i].len;
  1303. creq->data_len -= creq->vbuf.dst[dst_i].len;
  1304. dst_i++;
  1305. } else {
  1306. if (err == 0 && copy_to_user(
  1307. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1308. (k_align_dst + byteoffset),
  1309. creq->data_len)) {
  1310. err = -EFAULT;
  1311. goto exit;
  1312. }
  1313. k_align_dst += creq->data_len;
  1314. creq->vbuf.dst[dst_i].len -= creq->data_len;
  1315. creq->vbuf.dst[dst_i].vaddr += creq->data_len;
  1316. creq->data_len = 0;
  1317. }
  1318. }
  1319. *di = dst_i;
  1320. exit:
  1321. areq->cipher_req.creq.src = NULL;
  1322. areq->cipher_req.creq.dst = NULL;
  1323. return err;
  1324. };
  1325. static int qcedev_vbuf_ablk_cipher(struct qcedev_async_req *areq,
  1326. struct qcedev_handle *handle)
  1327. {
  1328. int err = 0;
  1329. int di = 0;
  1330. int i = 0;
  1331. int j = 0;
  1332. int k = 0;
  1333. uint32_t byteoffset = 0;
  1334. int num_entries = 0;
  1335. uint32_t total = 0;
  1336. uint32_t len;
  1337. uint8_t *k_buf_src = NULL;
  1338. uint32_t buf_size = 0;
  1339. uint8_t *k_align_src = NULL;
  1340. uint32_t max_data_xfer;
  1341. struct qcedev_cipher_op_req *saved_req;
  1342. uint32_t req_size = 0;
  1343. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1344. total = 0;
  1345. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1346. byteoffset = areq->cipher_op_req.byteoffset;
  1347. buf_size = QCE_MAX_OPER_DATA + CACHE_LINE_SIZE * 2;
  1348. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1349. if (k_buf_src == NULL)
  1350. return -ENOMEM;
  1351. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  1352. CACHE_LINE_SIZE);
  1353. max_data_xfer = QCE_MAX_OPER_DATA - byteoffset;
  1354. req_size = sizeof(struct qcedev_cipher_op_req);
  1355. saved_req = kmemdup(creq, req_size, GFP_KERNEL);
  1356. if (saved_req == NULL) {
  1357. memset(k_buf_src, 0, buf_size);
  1358. kfree(k_buf_src);
  1359. return -ENOMEM;
  1360. }
  1361. if (areq->cipher_op_req.data_len > max_data_xfer) {
  1362. struct qcedev_cipher_op_req req;
  1363. /* save the original req structure */
  1364. memcpy(&req, creq, sizeof(struct qcedev_cipher_op_req));
  1365. i = 0;
  1366. /* Address 32 KB at a time */
  1367. while ((i < req.entries) && (err == 0)) {
  1368. if (creq->vbuf.src[i].len > max_data_xfer) {
  1369. creq->vbuf.src[0].len = max_data_xfer;
  1370. if (i > 0) {
  1371. creq->vbuf.src[0].vaddr =
  1372. creq->vbuf.src[i].vaddr;
  1373. }
  1374. creq->data_len = max_data_xfer;
  1375. creq->entries = 1;
  1376. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1377. &di, handle, k_align_src);
  1378. if (err < 0) {
  1379. memset(saved_req, 0, req_size);
  1380. memset(k_buf_src, 0, buf_size);
  1381. kfree(k_buf_src);
  1382. kfree(saved_req);
  1383. return err;
  1384. }
  1385. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1386. max_data_xfer;
  1387. creq->vbuf.src[i].vaddr =
  1388. req.vbuf.src[i].vaddr +
  1389. max_data_xfer;
  1390. req.vbuf.src[i].vaddr =
  1391. creq->vbuf.src[i].vaddr;
  1392. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1393. } else {
  1394. total = areq->cipher_op_req.byteoffset;
  1395. for (j = i; j < req.entries; j++) {
  1396. num_entries++;
  1397. if ((total + creq->vbuf.src[j].len)
  1398. >= max_data_xfer) {
  1399. creq->vbuf.src[j].len =
  1400. max_data_xfer - total;
  1401. total = max_data_xfer;
  1402. break;
  1403. }
  1404. total += creq->vbuf.src[j].len;
  1405. }
  1406. creq->data_len = total;
  1407. if (i > 0)
  1408. for (k = 0; k < num_entries; k++) {
  1409. creq->vbuf.src[k].len =
  1410. creq->vbuf.src[i+k].len;
  1411. creq->vbuf.src[k].vaddr =
  1412. creq->vbuf.src[i+k].vaddr;
  1413. }
  1414. creq->entries = num_entries;
  1415. i = j;
  1416. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1417. &di, handle, k_align_src);
  1418. if (err < 0) {
  1419. memset(saved_req, 0, req_size);
  1420. memset(k_buf_src, 0, buf_size);
  1421. kfree(k_buf_src);
  1422. kfree(saved_req);
  1423. return err;
  1424. }
  1425. num_entries = 0;
  1426. areq->cipher_op_req.byteoffset = 0;
  1427. creq->vbuf.src[i].vaddr = req.vbuf.src[i].vaddr
  1428. + creq->vbuf.src[i].len;
  1429. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1430. creq->vbuf.src[i].len;
  1431. req.vbuf.src[i].vaddr =
  1432. creq->vbuf.src[i].vaddr;
  1433. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1434. if (creq->vbuf.src[i].len == 0)
  1435. i++;
  1436. }
  1437. areq->cipher_op_req.byteoffset = 0;
  1438. max_data_xfer = QCE_MAX_OPER_DATA;
  1439. byteoffset = 0;
  1440. } /* end of while ((i < req.entries) && (err == 0)) */
  1441. } else
  1442. err = qcedev_vbuf_ablk_cipher_max_xfer(areq, &di, handle,
  1443. k_align_src);
  1444. /* Restore the original req structure */
  1445. for (i = 0; i < saved_req->entries; i++) {
  1446. creq->vbuf.src[i].len = saved_req->vbuf.src[i].len;
  1447. creq->vbuf.src[i].vaddr = saved_req->vbuf.src[i].vaddr;
  1448. }
  1449. for (len = 0, i = 0; len < saved_req->data_len; i++) {
  1450. creq->vbuf.dst[i].len = saved_req->vbuf.dst[i].len;
  1451. creq->vbuf.dst[i].vaddr = saved_req->vbuf.dst[i].vaddr;
  1452. len += saved_req->vbuf.dst[i].len;
  1453. }
  1454. creq->entries = saved_req->entries;
  1455. creq->data_len = saved_req->data_len;
  1456. creq->byteoffset = saved_req->byteoffset;
  1457. memset(saved_req, 0, req_size);
  1458. memset(k_buf_src, 0, buf_size);
  1459. kfree(saved_req);
  1460. kfree(k_buf_src);
  1461. return err;
  1462. }
  1463. static int qcedev_smmu_ablk_offload_cipher(struct qcedev_async_req *areq,
  1464. struct qcedev_handle *handle)
  1465. {
  1466. int i = 0;
  1467. int err = 0;
  1468. size_t byteoffset = 0;
  1469. size_t transfer_data_len = 0;
  1470. size_t pending_data_len = 0;
  1471. size_t max_data_xfer = MAX_CEHW_REQ_TRANSFER_SIZE - byteoffset;
  1472. uint8_t *user_src = NULL;
  1473. uint8_t *user_dst = NULL;
  1474. struct scatterlist sg_src;
  1475. struct scatterlist sg_dst;
  1476. if (areq->offload_cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1477. byteoffset = areq->offload_cipher_op_req.byteoffset;
  1478. /*
  1479. * areq has two components:
  1480. * a) Request that comes from userspace i.e. offload_cipher_op_req
  1481. * b) Request that QCE understands - skcipher i.e. cipher_req.creq
  1482. * skcipher has sglist pointers src and dest that would carry
  1483. * data to/from CE.
  1484. */
  1485. areq->cipher_req.creq.src = &sg_src;
  1486. areq->cipher_req.creq.dst = &sg_dst;
  1487. sg_init_table(&sg_src, 1);
  1488. sg_init_table(&sg_dst, 1);
  1489. for (i = 0; i < areq->offload_cipher_op_req.entries; i++) {
  1490. transfer_data_len = 0;
  1491. pending_data_len = areq->offload_cipher_op_req.vbuf.src[i].len;
  1492. user_src = areq->offload_cipher_op_req.vbuf.src[i].vaddr;
  1493. user_src += byteoffset;
  1494. user_dst = areq->offload_cipher_op_req.vbuf.dst[i].vaddr;
  1495. user_dst += byteoffset;
  1496. areq->cipher_req.creq.iv = areq->offload_cipher_op_req.iv;
  1497. while (pending_data_len) {
  1498. transfer_data_len = min(max_data_xfer,
  1499. pending_data_len);
  1500. sg_src.dma_address = (dma_addr_t)user_src;
  1501. sg_dst.dma_address = (dma_addr_t)user_dst;
  1502. areq->cipher_req.creq.cryptlen = transfer_data_len;
  1503. sg_src.length = transfer_data_len;
  1504. sg_dst.length = transfer_data_len;
  1505. err = submit_req(areq, handle);
  1506. if (err) {
  1507. pr_err("%s: Error processing req, err = %d\n",
  1508. __func__, err);
  1509. goto exit;
  1510. }
  1511. /* update data len to be processed */
  1512. pending_data_len -= transfer_data_len;
  1513. user_src += transfer_data_len;
  1514. user_dst += transfer_data_len;
  1515. }
  1516. }
  1517. exit:
  1518. areq->cipher_req.creq.src = NULL;
  1519. areq->cipher_req.creq.dst = NULL;
  1520. return err;
  1521. }
  1522. static int qcedev_check_cipher_key(struct qcedev_cipher_op_req *req,
  1523. struct qcedev_control *podev)
  1524. {
  1525. /* if intending to use HW key make sure key fields are set
  1526. * correctly and HW key is indeed supported in target
  1527. */
  1528. if (req->encklen == 0) {
  1529. int i;
  1530. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  1531. if (req->enckey[i]) {
  1532. pr_err("%s: Invalid key: non-zero key input\n",
  1533. __func__);
  1534. goto error;
  1535. }
  1536. }
  1537. if ((req->op != QCEDEV_OPER_ENC_NO_KEY) &&
  1538. (req->op != QCEDEV_OPER_DEC_NO_KEY))
  1539. if (!podev->platform_support.hw_key_support) {
  1540. pr_err("%s: Invalid op %d\n", __func__,
  1541. (uint32_t)req->op);
  1542. goto error;
  1543. }
  1544. } else {
  1545. if (req->encklen == QCEDEV_AES_KEY_192) {
  1546. if (!podev->ce_support.aes_key_192) {
  1547. pr_err("%s: AES-192 not supported\n", __func__);
  1548. goto error;
  1549. }
  1550. } else {
  1551. /* if not using HW key make sure key
  1552. * length is valid
  1553. */
  1554. if (req->mode == QCEDEV_AES_MODE_XTS) {
  1555. if ((req->encklen != QCEDEV_AES_KEY_128*2) &&
  1556. (req->encklen != QCEDEV_AES_KEY_256*2)) {
  1557. pr_err("%s: unsupported key size: %d\n",
  1558. __func__, req->encklen);
  1559. goto error;
  1560. }
  1561. } else {
  1562. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1563. (req->encklen != QCEDEV_AES_KEY_256)) {
  1564. pr_err("%s: unsupported key size %d\n",
  1565. __func__, req->encklen);
  1566. goto error;
  1567. }
  1568. }
  1569. }
  1570. }
  1571. return 0;
  1572. error:
  1573. return -EINVAL;
  1574. }
  1575. static int qcedev_check_cipher_params(struct qcedev_cipher_op_req *req,
  1576. struct qcedev_control *podev)
  1577. {
  1578. uint32_t total = 0;
  1579. uint32_t i;
  1580. if (req->use_pmem) {
  1581. pr_err("%s: Use of PMEM is not supported\n", __func__);
  1582. goto error;
  1583. }
  1584. if ((req->entries == 0) || (req->data_len == 0) ||
  1585. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1586. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1587. goto error;
  1588. }
  1589. if ((req->alg >= QCEDEV_ALG_LAST) ||
  1590. (req->mode >= QCEDEV_AES_DES_MODE_LAST)) {
  1591. pr_err("%s: Invalid algorithm %d\n", __func__,
  1592. (uint32_t)req->alg);
  1593. goto error;
  1594. }
  1595. if ((req->mode == QCEDEV_AES_MODE_XTS) &&
  1596. (!podev->ce_support.aes_xts)) {
  1597. pr_err("%s: XTS algorithm is not supported\n", __func__);
  1598. goto error;
  1599. }
  1600. if (req->alg == QCEDEV_ALG_AES) {
  1601. if (qcedev_check_cipher_key(req, podev))
  1602. goto error;
  1603. }
  1604. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1605. if (req->byteoffset) {
  1606. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1607. pr_err("%s: Operation on byte offset not supported\n",
  1608. __func__);
  1609. goto error;
  1610. }
  1611. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1612. pr_err("%s: Invalid byte offset\n", __func__);
  1613. goto error;
  1614. }
  1615. total = req->byteoffset;
  1616. for (i = 0; i < req->entries; i++) {
  1617. if (total > U32_MAX - req->vbuf.src[i].len) {
  1618. pr_err("%s:Integer overflow on total src len\n",
  1619. __func__);
  1620. goto error;
  1621. }
  1622. total += req->vbuf.src[i].len;
  1623. }
  1624. }
  1625. if (req->data_len < req->byteoffset) {
  1626. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1627. __func__, req->data_len, req->byteoffset);
  1628. goto error;
  1629. }
  1630. /* Ensure IV size */
  1631. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1632. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1633. goto error;
  1634. }
  1635. /* Ensure Key size */
  1636. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1637. pr_err("%s: Klen is not correct: %u\n", __func__, req->encklen);
  1638. goto error;
  1639. }
  1640. /* Ensure zer ivlen for ECB mode */
  1641. if (req->ivlen > 0) {
  1642. if ((req->mode == QCEDEV_AES_MODE_ECB) ||
  1643. (req->mode == QCEDEV_DES_MODE_ECB)) {
  1644. pr_err("%s: Expecting a zero length IV\n", __func__);
  1645. goto error;
  1646. }
  1647. } else {
  1648. if ((req->mode != QCEDEV_AES_MODE_ECB) &&
  1649. (req->mode != QCEDEV_DES_MODE_ECB)) {
  1650. pr_err("%s: Expecting a non-zero ength IV\n", __func__);
  1651. goto error;
  1652. }
  1653. }
  1654. /* Check for sum of all dst length is equal to data_len */
  1655. for (i = 0, total = 0; i < req->entries; i++) {
  1656. if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
  1657. pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
  1658. __func__, i, req->vbuf.dst[i].len);
  1659. goto error;
  1660. }
  1661. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1662. pr_err("%s: Integer overflow on total req dst vbuf length\n",
  1663. __func__);
  1664. goto error;
  1665. }
  1666. total += req->vbuf.dst[i].len;
  1667. }
  1668. if (total != req->data_len) {
  1669. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1670. __func__, i, total, req->data_len);
  1671. goto error;
  1672. }
  1673. /* Check for sum of all src length is equal to data_len */
  1674. for (i = 0, total = 0; i < req->entries; i++) {
  1675. if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
  1676. pr_err("%s: NULL req src vbuf[%d] with length %d\n",
  1677. __func__, i, req->vbuf.src[i].len);
  1678. goto error;
  1679. }
  1680. if (req->vbuf.src[i].len > U32_MAX - total) {
  1681. pr_err("%s: Integer overflow on total req src vbuf length\n",
  1682. __func__);
  1683. goto error;
  1684. }
  1685. total += req->vbuf.src[i].len;
  1686. }
  1687. if (total != req->data_len) {
  1688. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1689. __func__, total, req->data_len);
  1690. goto error;
  1691. }
  1692. return 0;
  1693. error:
  1694. return -EINVAL;
  1695. }
  1696. static int qcedev_check_sha_params(struct qcedev_sha_op_req *req,
  1697. struct qcedev_control *podev)
  1698. {
  1699. uint32_t total = 0;
  1700. uint32_t i;
  1701. if ((req->alg == QCEDEV_ALG_AES_CMAC) &&
  1702. (!podev->ce_support.cmac)) {
  1703. pr_err("%s: CMAC not supported\n", __func__);
  1704. goto sha_error;
  1705. }
  1706. if ((!req->entries) || (req->entries > QCEDEV_MAX_BUFFERS)) {
  1707. pr_err("%s: Invalid num entries (%d)\n",
  1708. __func__, req->entries);
  1709. goto sha_error;
  1710. }
  1711. if (req->alg >= QCEDEV_ALG_SHA_ALG_LAST) {
  1712. pr_err("%s: Invalid algorithm (%d)\n", __func__, req->alg);
  1713. goto sha_error;
  1714. }
  1715. if ((req->alg == QCEDEV_ALG_SHA1_HMAC) ||
  1716. (req->alg == QCEDEV_ALG_SHA256_HMAC)) {
  1717. if (req->authkey == NULL) {
  1718. pr_err("%s: Invalid authkey pointer\n", __func__);
  1719. goto sha_error;
  1720. }
  1721. if (req->authklen <= 0) {
  1722. pr_err("%s: Invalid authkey length (%d)\n",
  1723. __func__, req->authklen);
  1724. goto sha_error;
  1725. }
  1726. }
  1727. if (req->alg == QCEDEV_ALG_AES_CMAC) {
  1728. if ((req->authklen != QCEDEV_AES_KEY_128) &&
  1729. (req->authklen != QCEDEV_AES_KEY_256)) {
  1730. pr_err("%s: unsupported key length\n", __func__);
  1731. goto sha_error;
  1732. }
  1733. }
  1734. /* Check for sum of all src length is equal to data_len */
  1735. for (i = 0, total = 0; i < req->entries; i++) {
  1736. if (req->data[i].len > U32_MAX - total) {
  1737. pr_err("%s: Integer overflow on total req buf length\n",
  1738. __func__);
  1739. goto sha_error;
  1740. }
  1741. total += req->data[i].len;
  1742. }
  1743. if (total != req->data_len) {
  1744. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1745. __func__, total, req->data_len);
  1746. goto sha_error;
  1747. }
  1748. return 0;
  1749. sha_error:
  1750. return -EINVAL;
  1751. }
  1752. static int qcedev_check_offload_cipher_key(struct qcedev_offload_cipher_op_req *req,
  1753. struct qcedev_control *podev)
  1754. {
  1755. if (req->encklen == 0)
  1756. return -EINVAL;
  1757. /* AES-192 is not a valid option for OFFLOAD use case */
  1758. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1759. (req->encklen != QCEDEV_AES_KEY_256)) {
  1760. pr_err("%s: unsupported key size %d\n",
  1761. __func__, req->encklen);
  1762. goto error;
  1763. }
  1764. return 0;
  1765. error:
  1766. return -EINVAL;
  1767. }
  1768. static int qcedev_check_offload_cipher_params(struct qcedev_offload_cipher_op_req *req,
  1769. struct qcedev_control *podev)
  1770. {
  1771. uint32_t total = 0;
  1772. int i = 0;
  1773. if ((req->entries == 0) || (req->data_len == 0) ||
  1774. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1775. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1776. goto error;
  1777. }
  1778. if ((req->alg != QCEDEV_ALG_AES) ||
  1779. (req->mode > QCEDEV_AES_MODE_CTR)) {
  1780. pr_err("%s: Invalid algorithm %d\n", __func__,
  1781. (uint32_t)req->alg);
  1782. goto error;
  1783. }
  1784. if (qcedev_check_offload_cipher_key(req, podev))
  1785. goto error;
  1786. if (req->block_offset >= AES_CE_BLOCK_SIZE)
  1787. goto error;
  1788. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1789. if (req->byteoffset) {
  1790. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1791. pr_err("%s: Operation on byte offset not supported\n",
  1792. __func__);
  1793. goto error;
  1794. }
  1795. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1796. pr_err("%s: Invalid byte offset\n", __func__);
  1797. goto error;
  1798. }
  1799. total = req->byteoffset;
  1800. for (i = 0; i < req->entries; i++) {
  1801. if (total > U32_MAX - req->vbuf.src[i].len) {
  1802. pr_err("%s:Int overflow on total src len\n",
  1803. __func__);
  1804. goto error;
  1805. }
  1806. total += req->vbuf.src[i].len;
  1807. }
  1808. }
  1809. if (req->data_len < req->byteoffset) {
  1810. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1811. __func__, req->data_len, req->byteoffset);
  1812. goto error;
  1813. }
  1814. /* Ensure IV size */
  1815. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1816. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1817. goto error;
  1818. }
  1819. /* Ensure Key size */
  1820. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1821. pr_err("%s: Klen is not correct: %u\n", __func__,
  1822. req->encklen);
  1823. goto error;
  1824. }
  1825. /* Check for sum of all dst length is equal to data_len */
  1826. for (i = 0, total = 0; i < req->entries; i++) {
  1827. if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
  1828. pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
  1829. __func__, i, req->vbuf.dst[i].len);
  1830. goto error;
  1831. }
  1832. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1833. pr_err("%s: Int overflow on total req dst vbuf len\n",
  1834. __func__);
  1835. goto error;
  1836. }
  1837. total += req->vbuf.dst[i].len;
  1838. }
  1839. if (total != req->data_len) {
  1840. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1841. __func__, i, total, req->data_len);
  1842. goto error;
  1843. }
  1844. /* Check for sum of all src length is equal to data_len */
  1845. for (i = 0, total = 0; i < req->entries; i++) {
  1846. if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
  1847. pr_err("%s: NULL req src vbuf[%d] with length %d\n",
  1848. __func__, i, req->vbuf.src[i].len);
  1849. goto error;
  1850. }
  1851. if (req->vbuf.src[i].len > U32_MAX - total) {
  1852. pr_err("%s: Int overflow on total req src vbuf len\n",
  1853. __func__);
  1854. goto error;
  1855. }
  1856. total += req->vbuf.src[i].len;
  1857. }
  1858. if (total != req->data_len) {
  1859. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1860. __func__, total, req->data_len);
  1861. goto error;
  1862. }
  1863. return 0;
  1864. error:
  1865. return -EINVAL;
  1866. }
  1867. long qcedev_ioctl(struct file *file,
  1868. unsigned int cmd, unsigned long arg)
  1869. {
  1870. int err = 0;
  1871. struct qcedev_handle *handle;
  1872. struct qcedev_control *podev;
  1873. struct qcedev_async_req *qcedev_areq;
  1874. struct qcedev_stat *pstat;
  1875. qcedev_areq = kzalloc(sizeof(struct qcedev_async_req), GFP_KERNEL);
  1876. if (!qcedev_areq)
  1877. return -ENOMEM;
  1878. handle = file->private_data;
  1879. podev = handle->cntl;
  1880. qcedev_areq->handle = handle;
  1881. if (podev == NULL || podev->magic != QCEDEV_MAGIC) {
  1882. pr_err("%s: invalid handle %pK\n",
  1883. __func__, podev);
  1884. err = -ENOENT;
  1885. goto exit_free_qcedev_areq;
  1886. }
  1887. /* Verify user arguments. */
  1888. if (_IOC_TYPE(cmd) != QCEDEV_IOC_MAGIC) {
  1889. err = -ENOTTY;
  1890. goto exit_free_qcedev_areq;
  1891. }
  1892. init_completion(&qcedev_areq->complete);
  1893. pstat = &_qcedev_stat;
  1894. switch (cmd) {
  1895. case QCEDEV_IOCTL_ENC_REQ:
  1896. case QCEDEV_IOCTL_DEC_REQ:
  1897. if (copy_from_user(&qcedev_areq->cipher_op_req,
  1898. (void __user *)arg,
  1899. sizeof(struct qcedev_cipher_op_req))) {
  1900. err = -EFAULT;
  1901. goto exit_free_qcedev_areq;
  1902. }
  1903. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_CIPHER;
  1904. if (qcedev_check_cipher_params(&qcedev_areq->cipher_op_req,
  1905. podev)) {
  1906. err = -EINVAL;
  1907. goto exit_free_qcedev_areq;
  1908. }
  1909. err = qcedev_vbuf_ablk_cipher(qcedev_areq, handle);
  1910. if (err)
  1911. goto exit_free_qcedev_areq;
  1912. if (copy_to_user((void __user *)arg,
  1913. &qcedev_areq->cipher_op_req,
  1914. sizeof(struct qcedev_cipher_op_req))) {
  1915. err = -EFAULT;
  1916. goto exit_free_qcedev_areq;
  1917. }
  1918. break;
  1919. case QCEDEV_IOCTL_OFFLOAD_OP_REQ:
  1920. if (copy_from_user(&qcedev_areq->offload_cipher_op_req,
  1921. (void __user *)arg,
  1922. sizeof(struct qcedev_offload_cipher_op_req))) {
  1923. err = -EFAULT;
  1924. goto exit_free_qcedev_areq;
  1925. }
  1926. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER;
  1927. if (qcedev_check_offload_cipher_params(
  1928. &qcedev_areq->offload_cipher_op_req, podev)) {
  1929. err = -EINVAL;
  1930. goto exit_free_qcedev_areq;
  1931. }
  1932. qcedev_areq->offload_cipher_op_req.err = QCEDEV_OFFLOAD_NO_ERROR;
  1933. err = qcedev_smmu_ablk_offload_cipher(qcedev_areq, handle);
  1934. if (err)
  1935. goto exit_free_qcedev_areq;
  1936. if (copy_to_user((void __user *)arg,
  1937. &qcedev_areq->offload_cipher_op_req,
  1938. sizeof(struct qcedev_offload_cipher_op_req))) {
  1939. err = -EFAULT;
  1940. goto exit_free_qcedev_areq;
  1941. }
  1942. break;
  1943. case QCEDEV_IOCTL_SHA_INIT_REQ:
  1944. {
  1945. struct scatterlist sg_src;
  1946. if (copy_from_user(&qcedev_areq->sha_op_req,
  1947. (void __user *)arg,
  1948. sizeof(struct qcedev_sha_op_req))) {
  1949. err = -EFAULT;
  1950. goto exit_free_qcedev_areq;
  1951. }
  1952. mutex_lock(&hash_access_lock);
  1953. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  1954. mutex_unlock(&hash_access_lock);
  1955. err = -EINVAL;
  1956. goto exit_free_qcedev_areq;
  1957. }
  1958. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  1959. err = qcedev_hash_init(qcedev_areq, handle, &sg_src);
  1960. if (err) {
  1961. mutex_unlock(&hash_access_lock);
  1962. goto exit_free_qcedev_areq;
  1963. }
  1964. mutex_unlock(&hash_access_lock);
  1965. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  1966. sizeof(struct qcedev_sha_op_req))) {
  1967. err = -EFAULT;
  1968. goto exit_free_qcedev_areq;
  1969. }
  1970. handle->sha_ctxt.init_done = true;
  1971. }
  1972. break;
  1973. case QCEDEV_IOCTL_GET_CMAC_REQ:
  1974. if (!podev->ce_support.cmac) {
  1975. err = -ENOTTY;
  1976. goto exit_free_qcedev_areq;
  1977. }
  1978. fallthrough;
  1979. case QCEDEV_IOCTL_SHA_UPDATE_REQ:
  1980. {
  1981. struct scatterlist sg_src;
  1982. if (copy_from_user(&qcedev_areq->sha_op_req,
  1983. (void __user *)arg,
  1984. sizeof(struct qcedev_sha_op_req))) {
  1985. err = -EFAULT;
  1986. goto exit_free_qcedev_areq;
  1987. }
  1988. mutex_lock(&hash_access_lock);
  1989. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  1990. mutex_unlock(&hash_access_lock);
  1991. err = -EINVAL;
  1992. goto exit_free_qcedev_areq;
  1993. }
  1994. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  1995. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_AES_CMAC) {
  1996. err = qcedev_hash_cmac(qcedev_areq, handle, &sg_src);
  1997. if (err) {
  1998. mutex_unlock(&hash_access_lock);
  1999. goto exit_free_qcedev_areq;
  2000. }
  2001. } else {
  2002. if (!handle->sha_ctxt.init_done) {
  2003. pr_err("%s Init was not called\n", __func__);
  2004. mutex_unlock(&hash_access_lock);
  2005. err = -EINVAL;
  2006. goto exit_free_qcedev_areq;
  2007. }
  2008. err = qcedev_hash_update(qcedev_areq, handle, &sg_src);
  2009. if (err) {
  2010. mutex_unlock(&hash_access_lock);
  2011. goto exit_free_qcedev_areq;
  2012. }
  2013. }
  2014. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2015. pr_err("Invalid sha_ctxt.diglen %d\n",
  2016. handle->sha_ctxt.diglen);
  2017. mutex_unlock(&hash_access_lock);
  2018. err = -EINVAL;
  2019. goto exit_free_qcedev_areq;
  2020. }
  2021. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2022. &handle->sha_ctxt.digest[0],
  2023. handle->sha_ctxt.diglen);
  2024. mutex_unlock(&hash_access_lock);
  2025. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2026. sizeof(struct qcedev_sha_op_req))) {
  2027. err = -EFAULT;
  2028. goto exit_free_qcedev_areq;
  2029. }
  2030. }
  2031. break;
  2032. case QCEDEV_IOCTL_SHA_FINAL_REQ:
  2033. if (!handle->sha_ctxt.init_done) {
  2034. pr_err("%s Init was not called\n", __func__);
  2035. err = -EINVAL;
  2036. goto exit_free_qcedev_areq;
  2037. }
  2038. if (copy_from_user(&qcedev_areq->sha_op_req,
  2039. (void __user *)arg,
  2040. sizeof(struct qcedev_sha_op_req))) {
  2041. err = -EFAULT;
  2042. goto exit_free_qcedev_areq;
  2043. }
  2044. mutex_lock(&hash_access_lock);
  2045. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  2046. mutex_unlock(&hash_access_lock);
  2047. err = -EINVAL;
  2048. goto exit_free_qcedev_areq;
  2049. }
  2050. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  2051. err = qcedev_hash_final(qcedev_areq, handle);
  2052. if (err) {
  2053. mutex_unlock(&hash_access_lock);
  2054. goto exit_free_qcedev_areq;
  2055. }
  2056. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2057. pr_err("Invalid sha_ctxt.diglen %d\n",
  2058. handle->sha_ctxt.diglen);
  2059. mutex_unlock(&hash_access_lock);
  2060. err = -EINVAL;
  2061. goto exit_free_qcedev_areq;
  2062. }
  2063. qcedev_areq->sha_op_req.diglen = handle->sha_ctxt.diglen;
  2064. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2065. &handle->sha_ctxt.digest[0],
  2066. handle->sha_ctxt.diglen);
  2067. mutex_unlock(&hash_access_lock);
  2068. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2069. sizeof(struct qcedev_sha_op_req))) {
  2070. err = -EFAULT;
  2071. goto exit_free_qcedev_areq;
  2072. }
  2073. handle->sha_ctxt.init_done = false;
  2074. break;
  2075. case QCEDEV_IOCTL_GET_SHA_REQ:
  2076. {
  2077. struct scatterlist sg_src;
  2078. if (copy_from_user(&qcedev_areq->sha_op_req,
  2079. (void __user *)arg,
  2080. sizeof(struct qcedev_sha_op_req))) {
  2081. err = -EFAULT;
  2082. goto exit_free_qcedev_areq;
  2083. }
  2084. mutex_lock(&hash_access_lock);
  2085. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  2086. mutex_unlock(&hash_access_lock);
  2087. err = -EINVAL;
  2088. goto exit_free_qcedev_areq;
  2089. }
  2090. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  2091. qcedev_hash_init(qcedev_areq, handle, &sg_src);
  2092. err = qcedev_hash_update(qcedev_areq, handle, &sg_src);
  2093. if (err) {
  2094. mutex_unlock(&hash_access_lock);
  2095. goto exit_free_qcedev_areq;
  2096. }
  2097. err = qcedev_hash_final(qcedev_areq, handle);
  2098. if (err) {
  2099. mutex_unlock(&hash_access_lock);
  2100. goto exit_free_qcedev_areq;
  2101. }
  2102. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2103. pr_err("Invalid sha_ctxt.diglen %d\n",
  2104. handle->sha_ctxt.diglen);
  2105. mutex_unlock(&hash_access_lock);
  2106. err = -EINVAL;
  2107. goto exit_free_qcedev_areq;
  2108. }
  2109. qcedev_areq->sha_op_req.diglen = handle->sha_ctxt.diglen;
  2110. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2111. &handle->sha_ctxt.digest[0],
  2112. handle->sha_ctxt.diglen);
  2113. mutex_unlock(&hash_access_lock);
  2114. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2115. sizeof(struct qcedev_sha_op_req))) {
  2116. err = -EFAULT;
  2117. goto exit_free_qcedev_areq;
  2118. }
  2119. }
  2120. break;
  2121. case QCEDEV_IOCTL_MAP_BUF_REQ:
  2122. {
  2123. unsigned long long vaddr = 0;
  2124. struct qcedev_map_buf_req map_buf = { {0} };
  2125. int i = 0;
  2126. if (copy_from_user(&map_buf,
  2127. (void __user *)arg, sizeof(map_buf))) {
  2128. err = -EFAULT;
  2129. goto exit_free_qcedev_areq;
  2130. }
  2131. if (map_buf.num_fds > ARRAY_SIZE(map_buf.fd)) {
  2132. pr_err("%s: err: num_fds = %d exceeds max value\n",
  2133. __func__, map_buf.num_fds);
  2134. err = -EINVAL;
  2135. goto exit_free_qcedev_areq;
  2136. }
  2137. for (i = 0; i < map_buf.num_fds; i++) {
  2138. err = qcedev_check_and_map_buffer(handle,
  2139. map_buf.fd[i],
  2140. map_buf.fd_offset[i],
  2141. map_buf.fd_size[i],
  2142. &vaddr);
  2143. if (err) {
  2144. pr_err(
  2145. "%s: err: failed to map fd(%d) - %d\n",
  2146. __func__, map_buf.fd[i], err);
  2147. goto exit_free_qcedev_areq;
  2148. }
  2149. map_buf.buf_vaddr[i] = vaddr;
  2150. pr_info("%s: info: vaddr = %llx\n, fd = %d",
  2151. __func__, vaddr, map_buf.fd[i]);
  2152. }
  2153. if (copy_to_user((void __user *)arg, &map_buf,
  2154. sizeof(map_buf))) {
  2155. err = -EFAULT;
  2156. goto exit_free_qcedev_areq;
  2157. }
  2158. break;
  2159. }
  2160. case QCEDEV_IOCTL_UNMAP_BUF_REQ:
  2161. {
  2162. struct qcedev_unmap_buf_req unmap_buf = { { 0 } };
  2163. int i = 0;
  2164. if (copy_from_user(&unmap_buf,
  2165. (void __user *)arg, sizeof(unmap_buf))) {
  2166. err = -EFAULT;
  2167. goto exit_free_qcedev_areq;
  2168. }
  2169. if (unmap_buf.num_fds > ARRAY_SIZE(unmap_buf.fd)) {
  2170. pr_err("%s: err: num_fds = %d exceeds max value\n",
  2171. __func__, unmap_buf.num_fds);
  2172. err = -EINVAL;
  2173. goto exit_free_qcedev_areq;
  2174. }
  2175. for (i = 0; i < unmap_buf.num_fds; i++) {
  2176. err = qcedev_check_and_unmap_buffer(handle,
  2177. unmap_buf.fd[i]);
  2178. if (err) {
  2179. pr_err(
  2180. "%s: err: failed to unmap fd(%d) - %d\n",
  2181. __func__,
  2182. unmap_buf.fd[i], err);
  2183. goto exit_free_qcedev_areq;
  2184. }
  2185. }
  2186. break;
  2187. }
  2188. default:
  2189. err = -ENOTTY;
  2190. goto exit_free_qcedev_areq;
  2191. }
  2192. exit_free_qcedev_areq:
  2193. kfree(qcedev_areq);
  2194. return err;
  2195. }
  2196. static int qcedev_probe_device(struct platform_device *pdev)
  2197. {
  2198. void *handle = NULL;
  2199. int rc = 0;
  2200. struct qcedev_control *podev;
  2201. struct msm_ce_hw_support *platform_support;
  2202. podev = &qce_dev[0];
  2203. rc = alloc_chrdev_region(&qcedev_device_no, 0, 1, QCEDEV_DEV);
  2204. if (rc < 0) {
  2205. pr_err("alloc_chrdev_region failed %d\n", rc);
  2206. return rc;
  2207. }
  2208. driver_class = class_create(THIS_MODULE, QCEDEV_DEV);
  2209. if (IS_ERR(driver_class)) {
  2210. rc = -ENOMEM;
  2211. pr_err("class_create failed %d\n", rc);
  2212. goto exit_unreg_chrdev_region;
  2213. }
  2214. class_dev = device_create(driver_class, NULL, qcedev_device_no, NULL,
  2215. QCEDEV_DEV);
  2216. if (IS_ERR(class_dev)) {
  2217. pr_err("class_device_create failed %d\n", rc);
  2218. rc = -ENOMEM;
  2219. goto exit_destroy_class;
  2220. }
  2221. cdev_init(&podev->cdev, &qcedev_fops);
  2222. podev->cdev.owner = THIS_MODULE;
  2223. rc = cdev_add(&podev->cdev, MKDEV(MAJOR(qcedev_device_no), 0), 1);
  2224. if (rc < 0) {
  2225. pr_err("cdev_add failed %d\n", rc);
  2226. goto exit_destroy_device;
  2227. }
  2228. podev->minor = 0;
  2229. podev->high_bw_req_count = 0;
  2230. INIT_LIST_HEAD(&podev->ready_commands);
  2231. podev->active_command = NULL;
  2232. INIT_LIST_HEAD(&podev->context_banks);
  2233. spin_lock_init(&podev->lock);
  2234. tasklet_init(&podev->done_tasklet, req_done, (unsigned long)podev);
  2235. podev->icc_path = of_icc_get(&pdev->dev, "data_path");
  2236. if (IS_ERR(podev->icc_path)) {
  2237. rc = PTR_ERR(podev->icc_path);
  2238. pr_err("%s Failed to get icc path with error %d\n",
  2239. __func__, rc);
  2240. goto exit_del_cdev;
  2241. }
  2242. /*
  2243. * HLOS crypto vote values from DTSI. If no values specified, use
  2244. * nominal values.
  2245. */
  2246. if (of_property_read_u32((&pdev->dev)->of_node,
  2247. "qcom,icc_avg_bw",
  2248. &podev->icc_avg_bw)) {
  2249. pr_warn("%s: No icc avg BW set, using default\n", __func__);
  2250. podev->icc_avg_bw = CRYPTO_AVG_BW;
  2251. }
  2252. if (of_property_read_u32((&pdev->dev)->of_node,
  2253. "qcom,icc_peak_bw",
  2254. &podev->icc_peak_bw)) {
  2255. pr_warn("%s: No icc peak BW set, using default\n", __func__);
  2256. podev->icc_peak_bw = CRYPTO_PEAK_BW;
  2257. }
  2258. rc = icc_set_bw(podev->icc_path, podev->icc_avg_bw,
  2259. podev->icc_peak_bw);
  2260. if (rc) {
  2261. pr_err("%s Unable to set high bandwidth\n", __func__);
  2262. goto exit_unregister_bus_scale;
  2263. }
  2264. handle = qce_open(pdev, &rc);
  2265. if (handle == NULL) {
  2266. rc = -ENODEV;
  2267. goto exit_scale_busbandwidth;
  2268. }
  2269. podev->qce = handle;
  2270. rc = qce_set_irqs(podev->qce, false);
  2271. if (rc) {
  2272. pr_err("%s: could not disable bam irqs, ret = %d",
  2273. __func__, rc);
  2274. goto exit_scale_busbandwidth;
  2275. }
  2276. rc = icc_set_bw(podev->icc_path, 0, 0);
  2277. if (rc) {
  2278. pr_err("%s Unable to set to low bandwidth\n", __func__);
  2279. goto exit_qce_close;
  2280. }
  2281. podev->pdev = pdev;
  2282. platform_set_drvdata(pdev, podev);
  2283. qce_hw_support(podev->qce, &podev->ce_support);
  2284. if (podev->ce_support.bam) {
  2285. podev->platform_support.ce_shared = 0;
  2286. podev->platform_support.shared_ce_resource = 0;
  2287. podev->platform_support.hw_key_support =
  2288. podev->ce_support.hw_key;
  2289. podev->platform_support.sha_hmac = 1;
  2290. } else {
  2291. platform_support =
  2292. (struct msm_ce_hw_support *)pdev->dev.platform_data;
  2293. podev->platform_support.ce_shared = platform_support->ce_shared;
  2294. podev->platform_support.shared_ce_resource =
  2295. platform_support->shared_ce_resource;
  2296. podev->platform_support.hw_key_support =
  2297. platform_support->hw_key_support;
  2298. podev->platform_support.sha_hmac = platform_support->sha_hmac;
  2299. }
  2300. podev->mem_client = qcedev_mem_new_client(MEM_ION);
  2301. if (!podev->mem_client) {
  2302. pr_err("%s: err: qcedev_mem_new_client failed\n", __func__);
  2303. goto exit_qce_close;
  2304. }
  2305. rc = of_platform_populate(pdev->dev.of_node, qcedev_match,
  2306. NULL, &pdev->dev);
  2307. if (rc) {
  2308. pr_err("%s: err: of_platform_populate failed: %d\n",
  2309. __func__, rc);
  2310. goto exit_mem_new_client;
  2311. }
  2312. return 0;
  2313. exit_mem_new_client:
  2314. if (podev->mem_client)
  2315. qcedev_mem_delete_client(podev->mem_client);
  2316. podev->mem_client = NULL;
  2317. exit_qce_close:
  2318. if (handle)
  2319. qce_close(handle);
  2320. exit_scale_busbandwidth:
  2321. icc_set_bw(podev->icc_path, 0, 0);
  2322. exit_unregister_bus_scale:
  2323. if (podev->icc_path)
  2324. icc_put(podev->icc_path);
  2325. exit_del_cdev:
  2326. cdev_del(&podev->cdev);
  2327. exit_destroy_device:
  2328. device_destroy(driver_class, qcedev_device_no);
  2329. exit_destroy_class:
  2330. class_destroy(driver_class);
  2331. exit_unreg_chrdev_region:
  2332. unregister_chrdev_region(qcedev_device_no, 1);
  2333. podev->icc_path = NULL;
  2334. platform_set_drvdata(pdev, NULL);
  2335. podev->pdev = NULL;
  2336. podev->qce = NULL;
  2337. return rc;
  2338. }
  2339. static int qcedev_probe(struct platform_device *pdev)
  2340. {
  2341. if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcedev"))
  2342. return qcedev_probe_device(pdev);
  2343. else if (of_device_is_compatible(pdev->dev.of_node,
  2344. "qcom,qcedev,context-bank"))
  2345. return qcedev_parse_context_bank(pdev);
  2346. return -EINVAL;
  2347. };
  2348. static int qcedev_remove(struct platform_device *pdev)
  2349. {
  2350. struct qcedev_control *podev;
  2351. podev = platform_get_drvdata(pdev);
  2352. if (!podev)
  2353. return 0;
  2354. qcedev_ce_high_bw_req(podev, true);
  2355. if (podev->qce)
  2356. qce_close(podev->qce);
  2357. qcedev_ce_high_bw_req(podev, false);
  2358. if (podev->icc_path)
  2359. icc_put(podev->icc_path);
  2360. tasklet_kill(&podev->done_tasklet);
  2361. cdev_del(&podev->cdev);
  2362. device_destroy(driver_class, qcedev_device_no);
  2363. class_destroy(driver_class);
  2364. unregister_chrdev_region(qcedev_device_no, 1);
  2365. return 0;
  2366. };
  2367. static int qcedev_suspend(struct platform_device *pdev, pm_message_t state)
  2368. {
  2369. struct qcedev_control *podev;
  2370. int ret;
  2371. podev = platform_get_drvdata(pdev);
  2372. if (!podev)
  2373. return 0;
  2374. mutex_lock(&qcedev_sent_bw_req);
  2375. if (podev->high_bw_req_count) {
  2376. ret = qce_set_irqs(podev->qce, false);
  2377. if (ret) {
  2378. pr_err("%s: could not disable bam irqs, ret = %d",
  2379. __func__, ret);
  2380. goto suspend_exit;
  2381. }
  2382. ret = qcedev_control_clocks(podev, false);
  2383. if (ret)
  2384. goto suspend_exit;
  2385. }
  2386. suspend_exit:
  2387. mutex_unlock(&qcedev_sent_bw_req);
  2388. return 0;
  2389. }
  2390. static int qcedev_resume(struct platform_device *pdev)
  2391. {
  2392. struct qcedev_control *podev;
  2393. int ret;
  2394. podev = platform_get_drvdata(pdev);
  2395. if (!podev)
  2396. return 0;
  2397. mutex_lock(&qcedev_sent_bw_req);
  2398. if (podev->high_bw_req_count) {
  2399. ret = qcedev_control_clocks(podev, true);
  2400. if (ret)
  2401. goto resume_exit;
  2402. ret = qce_set_irqs(podev->qce, true);
  2403. if (ret) {
  2404. pr_err("%s: could not enable bam irqs, ret = %d",
  2405. __func__, ret);
  2406. qcedev_control_clocks(podev, false);
  2407. }
  2408. }
  2409. resume_exit:
  2410. mutex_unlock(&qcedev_sent_bw_req);
  2411. return 0;
  2412. }
  2413. static struct platform_driver qcedev_plat_driver = {
  2414. .probe = qcedev_probe,
  2415. .remove = qcedev_remove,
  2416. .suspend = qcedev_suspend,
  2417. .resume = qcedev_resume,
  2418. .driver = {
  2419. .name = "qce",
  2420. .of_match_table = qcedev_match,
  2421. },
  2422. };
  2423. static int _disp_stats(int id)
  2424. {
  2425. struct qcedev_stat *pstat;
  2426. int len = 0;
  2427. pstat = &_qcedev_stat;
  2428. len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1,
  2429. "\nQTI QCE dev driver %d Statistics:\n",
  2430. id + 1);
  2431. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2432. " Encryption operation success : %d\n",
  2433. pstat->qcedev_enc_success);
  2434. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2435. " Encryption operation fail : %d\n",
  2436. pstat->qcedev_enc_fail);
  2437. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2438. " Decryption operation success : %d\n",
  2439. pstat->qcedev_dec_success);
  2440. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2441. " Encryption operation fail : %d\n",
  2442. pstat->qcedev_dec_fail);
  2443. return len;
  2444. }
  2445. static ssize_t _debug_stats_read(struct file *file, char __user *buf,
  2446. size_t count, loff_t *ppos)
  2447. {
  2448. ssize_t rc = -EINVAL;
  2449. int qcedev = *((int *) file->private_data);
  2450. int len;
  2451. len = _disp_stats(qcedev);
  2452. if (len <= count)
  2453. rc = simple_read_from_buffer((void __user *) buf, len,
  2454. ppos, (void *) _debug_read_buf, len);
  2455. return rc;
  2456. }
  2457. static ssize_t _debug_stats_write(struct file *file, const char __user *buf,
  2458. size_t count, loff_t *ppos)
  2459. {
  2460. memset((char *)&_qcedev_stat, 0, sizeof(struct qcedev_stat));
  2461. return count;
  2462. };
  2463. static const struct file_operations _debug_stats_ops = {
  2464. .open = simple_open,
  2465. .read = _debug_stats_read,
  2466. .write = _debug_stats_write,
  2467. };
  2468. static int _qcedev_debug_init(void)
  2469. {
  2470. int rc;
  2471. char name[DEBUG_MAX_FNAME];
  2472. struct dentry *dent;
  2473. _debug_dent = debugfs_create_dir("qcedev", NULL);
  2474. if (IS_ERR(_debug_dent)) {
  2475. pr_debug("qcedev debugfs_create_dir fail, error %ld\n",
  2476. PTR_ERR(_debug_dent));
  2477. return PTR_ERR(_debug_dent);
  2478. }
  2479. snprintf(name, DEBUG_MAX_FNAME-1, "stats-%d", 1);
  2480. _debug_qcedev = 0;
  2481. dent = debugfs_create_file(name, 0644, _debug_dent,
  2482. &_debug_qcedev, &_debug_stats_ops);
  2483. if (dent == NULL) {
  2484. pr_debug("qcedev debugfs_create_file fail, error %ld\n",
  2485. PTR_ERR(dent));
  2486. rc = PTR_ERR(dent);
  2487. goto err;
  2488. }
  2489. return 0;
  2490. err:
  2491. debugfs_remove_recursive(_debug_dent);
  2492. return rc;
  2493. }
  2494. static int qcedev_init(void)
  2495. {
  2496. _qcedev_debug_init();
  2497. return platform_driver_register(&qcedev_plat_driver);
  2498. }
  2499. static void qcedev_exit(void)
  2500. {
  2501. debugfs_remove_recursive(_debug_dent);
  2502. platform_driver_unregister(&qcedev_plat_driver);
  2503. }
  2504. MODULE_LICENSE("GPL v2");
  2505. MODULE_DESCRIPTION("QTI DEV Crypto driver");
  2506. MODULE_IMPORT_NS(DMA_BUF);
  2507. module_init(qcedev_init);
  2508. module_exit(qcedev_exit);