dp_tx.c 140 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  71. /**
  72. * dp_update_tx_desc_stats - Update the increase or decrease in
  73. * outstanding tx desc count
  74. * values on pdev and soc
  75. * @vdev: DP pdev handle
  76. *
  77. * Return: void
  78. */
  79. static inline void
  80. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  81. {
  82. int32_t tx_descs_cnt =
  83. qdf_atomic_read(&pdev->num_tx_outstanding);
  84. if (pdev->tx_descs_max < tx_descs_cnt)
  85. pdev->tx_descs_max = tx_descs_cnt;
  86. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  87. pdev->tx_descs_max);
  88. }
  89. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  90. static inline void
  91. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  92. {
  93. }
  94. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  95. #ifdef QCA_TX_LIMIT_CHECK
  96. /**
  97. * dp_tx_limit_check - Check if allocated tx descriptors reached
  98. * soc max limit and pdev max limit
  99. * @vdev: DP vdev handle
  100. *
  101. * Return: true if allocated tx descriptors reached max configured value, else
  102. * false
  103. */
  104. static inline bool
  105. dp_tx_limit_check(struct dp_vdev *vdev)
  106. {
  107. struct dp_pdev *pdev = vdev->pdev;
  108. struct dp_soc *soc = pdev->soc;
  109. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  110. soc->num_tx_allowed) {
  111. dp_tx_info("queued packets are more than max tx, drop the frame");
  112. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  113. return true;
  114. }
  115. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  116. pdev->num_tx_allowed) {
  117. dp_tx_info("queued packets are more than max tx, drop the frame");
  118. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  119. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  120. return true;
  121. }
  122. return false;
  123. }
  124. /**
  125. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  126. * reached soc max limit
  127. * @vdev: DP vdev handle
  128. *
  129. * Return: true if allocated tx descriptors reached max configured value, else
  130. * false
  131. */
  132. static inline bool
  133. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  134. {
  135. struct dp_pdev *pdev = vdev->pdev;
  136. struct dp_soc *soc = pdev->soc;
  137. if (qdf_atomic_read(&soc->num_tx_exception) >=
  138. soc->num_msdu_exception_desc) {
  139. dp_info("exc packets are more than max drop the exc pkt");
  140. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  141. return true;
  142. }
  143. return false;
  144. }
  145. /**
  146. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  147. * @vdev: DP pdev handle
  148. *
  149. * Return: void
  150. */
  151. static inline void
  152. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  153. {
  154. struct dp_soc *soc = pdev->soc;
  155. qdf_atomic_inc(&pdev->num_tx_outstanding);
  156. qdf_atomic_inc(&soc->num_tx_outstanding);
  157. dp_update_tx_desc_stats(pdev);
  158. }
  159. /**
  160. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  161. * @vdev: DP pdev handle
  162. *
  163. * Return: void
  164. */
  165. static inline void
  166. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  167. {
  168. struct dp_soc *soc = pdev->soc;
  169. qdf_atomic_dec(&pdev->num_tx_outstanding);
  170. qdf_atomic_dec(&soc->num_tx_outstanding);
  171. dp_update_tx_desc_stats(pdev);
  172. }
  173. #else //QCA_TX_LIMIT_CHECK
  174. static inline bool
  175. dp_tx_limit_check(struct dp_vdev *vdev)
  176. {
  177. return false;
  178. }
  179. static inline bool
  180. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  181. {
  182. return false;
  183. }
  184. static inline void
  185. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  186. {
  187. qdf_atomic_inc(&pdev->num_tx_outstanding);
  188. dp_update_tx_desc_stats(pdev);
  189. }
  190. static inline void
  191. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  192. {
  193. qdf_atomic_dec(&pdev->num_tx_outstanding);
  194. dp_update_tx_desc_stats(pdev);
  195. }
  196. #endif //QCA_TX_LIMIT_CHECK
  197. #if defined(FEATURE_TSO)
  198. /**
  199. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  200. *
  201. * @soc - core txrx main context
  202. * @seg_desc - tso segment descriptor
  203. * @num_seg_desc - tso number segment descriptor
  204. */
  205. static void dp_tx_tso_unmap_segment(
  206. struct dp_soc *soc,
  207. struct qdf_tso_seg_elem_t *seg_desc,
  208. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  209. {
  210. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  211. if (qdf_unlikely(!seg_desc)) {
  212. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  213. __func__, __LINE__);
  214. qdf_assert(0);
  215. } else if (qdf_unlikely(!num_seg_desc)) {
  216. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  217. __func__, __LINE__);
  218. qdf_assert(0);
  219. } else {
  220. bool is_last_seg;
  221. /* no tso segment left to do dma unmap */
  222. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  223. return;
  224. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  225. true : false;
  226. qdf_nbuf_unmap_tso_segment(soc->osdev,
  227. seg_desc, is_last_seg);
  228. num_seg_desc->num_seg.tso_cmn_num_seg--;
  229. }
  230. }
  231. /**
  232. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  233. * back to the freelist
  234. *
  235. * @soc - soc device handle
  236. * @tx_desc - Tx software descriptor
  237. */
  238. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  239. struct dp_tx_desc_s *tx_desc)
  240. {
  241. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  242. if (qdf_unlikely(!tx_desc->tso_desc)) {
  243. dp_tx_err("SO desc is NULL!");
  244. qdf_assert(0);
  245. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  246. dp_tx_err("TSO num desc is NULL!");
  247. qdf_assert(0);
  248. } else {
  249. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  250. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  251. /* Add the tso num segment into the free list */
  252. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  253. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  254. tx_desc->tso_num_desc);
  255. tx_desc->tso_num_desc = NULL;
  256. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  257. }
  258. /* Add the tso segment into the free list*/
  259. dp_tx_tso_desc_free(soc,
  260. tx_desc->pool_id, tx_desc->tso_desc);
  261. tx_desc->tso_desc = NULL;
  262. }
  263. }
  264. #else
  265. static void dp_tx_tso_unmap_segment(
  266. struct dp_soc *soc,
  267. struct qdf_tso_seg_elem_t *seg_desc,
  268. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  269. {
  270. }
  271. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  272. struct dp_tx_desc_s *tx_desc)
  273. {
  274. }
  275. #endif
  276. /**
  277. * dp_tx_desc_release() - Release Tx Descriptor
  278. * @tx_desc : Tx Descriptor
  279. * @desc_pool_id: Descriptor Pool ID
  280. *
  281. * Deallocate all resources attached to Tx descriptor and free the Tx
  282. * descriptor.
  283. *
  284. * Return:
  285. */
  286. static void
  287. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  288. {
  289. struct dp_pdev *pdev = tx_desc->pdev;
  290. struct dp_soc *soc;
  291. uint8_t comp_status = 0;
  292. qdf_assert(pdev);
  293. soc = pdev->soc;
  294. dp_tx_outstanding_dec(pdev);
  295. if (tx_desc->frm_type == dp_tx_frm_tso)
  296. dp_tx_tso_desc_release(soc, tx_desc);
  297. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  298. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  299. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  300. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  301. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  302. qdf_atomic_dec(&soc->num_tx_exception);
  303. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  304. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  305. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  306. soc->hal_soc);
  307. else
  308. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  309. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  310. tx_desc->id, comp_status,
  311. qdf_atomic_read(&pdev->num_tx_outstanding));
  312. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  313. return;
  314. }
  315. /**
  316. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  317. * @vdev: DP vdev Handle
  318. * @nbuf: skb
  319. * @msdu_info: msdu_info required to create HTT metadata
  320. *
  321. * Prepares and fills HTT metadata in the frame pre-header for special frames
  322. * that should be transmitted using varying transmit parameters.
  323. * There are 2 VDEV modes that currently needs this special metadata -
  324. * 1) Mesh Mode
  325. * 2) DSRC Mode
  326. *
  327. * Return: HTT metadata size
  328. *
  329. */
  330. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  331. struct dp_tx_msdu_info_s *msdu_info)
  332. {
  333. uint32_t *meta_data = msdu_info->meta_data;
  334. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  335. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  336. uint8_t htt_desc_size;
  337. /* Size rounded of multiple of 8 bytes */
  338. uint8_t htt_desc_size_aligned;
  339. uint8_t *hdr = NULL;
  340. /*
  341. * Metadata - HTT MSDU Extension header
  342. */
  343. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  344. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  345. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  346. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  347. meta_data[0])) {
  348. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  349. htt_desc_size_aligned)) {
  350. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  351. htt_desc_size_aligned);
  352. if (!nbuf) {
  353. /*
  354. * qdf_nbuf_realloc_headroom won't do skb_clone
  355. * as skb_realloc_headroom does. so, no free is
  356. * needed here.
  357. */
  358. DP_STATS_INC(vdev,
  359. tx_i.dropped.headroom_insufficient,
  360. 1);
  361. qdf_print(" %s[%d] skb_realloc_headroom failed",
  362. __func__, __LINE__);
  363. return 0;
  364. }
  365. }
  366. /* Fill and add HTT metaheader */
  367. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  368. if (!hdr) {
  369. dp_tx_err("Error in filling HTT metadata");
  370. return 0;
  371. }
  372. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  373. } else if (vdev->opmode == wlan_op_mode_ocb) {
  374. /* Todo - Add support for DSRC */
  375. }
  376. return htt_desc_size_aligned;
  377. }
  378. /**
  379. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  380. * @tso_seg: TSO segment to process
  381. * @ext_desc: Pointer to MSDU extension descriptor
  382. *
  383. * Return: void
  384. */
  385. #if defined(FEATURE_TSO)
  386. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  387. void *ext_desc)
  388. {
  389. uint8_t num_frag;
  390. uint32_t tso_flags;
  391. /*
  392. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  393. * tcp_flag_mask
  394. *
  395. * Checksum enable flags are set in TCL descriptor and not in Extension
  396. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  397. */
  398. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  399. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  400. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  401. tso_seg->tso_flags.ip_len);
  402. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  403. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  404. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  405. uint32_t lo = 0;
  406. uint32_t hi = 0;
  407. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  408. (tso_seg->tso_frags[num_frag].length));
  409. qdf_dmaaddr_to_32s(
  410. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  411. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  412. tso_seg->tso_frags[num_frag].length);
  413. }
  414. return;
  415. }
  416. #else
  417. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  418. void *ext_desc)
  419. {
  420. return;
  421. }
  422. #endif
  423. #if defined(FEATURE_TSO)
  424. /**
  425. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  426. * allocated and free them
  427. *
  428. * @soc: soc handle
  429. * @free_seg: list of tso segments
  430. * @msdu_info: msdu descriptor
  431. *
  432. * Return - void
  433. */
  434. static void dp_tx_free_tso_seg_list(
  435. struct dp_soc *soc,
  436. struct qdf_tso_seg_elem_t *free_seg,
  437. struct dp_tx_msdu_info_s *msdu_info)
  438. {
  439. struct qdf_tso_seg_elem_t *next_seg;
  440. while (free_seg) {
  441. next_seg = free_seg->next;
  442. dp_tx_tso_desc_free(soc,
  443. msdu_info->tx_queue.desc_pool_id,
  444. free_seg);
  445. free_seg = next_seg;
  446. }
  447. }
  448. /**
  449. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  450. * allocated and free them
  451. *
  452. * @soc: soc handle
  453. * @free_num_seg: list of tso number segments
  454. * @msdu_info: msdu descriptor
  455. * Return - void
  456. */
  457. static void dp_tx_free_tso_num_seg_list(
  458. struct dp_soc *soc,
  459. struct qdf_tso_num_seg_elem_t *free_num_seg,
  460. struct dp_tx_msdu_info_s *msdu_info)
  461. {
  462. struct qdf_tso_num_seg_elem_t *next_num_seg;
  463. while (free_num_seg) {
  464. next_num_seg = free_num_seg->next;
  465. dp_tso_num_seg_free(soc,
  466. msdu_info->tx_queue.desc_pool_id,
  467. free_num_seg);
  468. free_num_seg = next_num_seg;
  469. }
  470. }
  471. /**
  472. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  473. * do dma unmap for each segment
  474. *
  475. * @soc: soc handle
  476. * @free_seg: list of tso segments
  477. * @num_seg_desc: tso number segment descriptor
  478. *
  479. * Return - void
  480. */
  481. static void dp_tx_unmap_tso_seg_list(
  482. struct dp_soc *soc,
  483. struct qdf_tso_seg_elem_t *free_seg,
  484. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  485. {
  486. struct qdf_tso_seg_elem_t *next_seg;
  487. if (qdf_unlikely(!num_seg_desc)) {
  488. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  489. return;
  490. }
  491. while (free_seg) {
  492. next_seg = free_seg->next;
  493. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  494. free_seg = next_seg;
  495. }
  496. }
  497. #ifdef FEATURE_TSO_STATS
  498. /**
  499. * dp_tso_get_stats_idx: Retrieve the tso packet id
  500. * @pdev - pdev handle
  501. *
  502. * Return: id
  503. */
  504. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  505. {
  506. uint32_t stats_idx;
  507. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  508. % CDP_MAX_TSO_PACKETS);
  509. return stats_idx;
  510. }
  511. #else
  512. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  513. {
  514. return 0;
  515. }
  516. #endif /* FEATURE_TSO_STATS */
  517. /**
  518. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  519. * free the tso segments descriptor and
  520. * tso num segments descriptor
  521. *
  522. * @soc: soc handle
  523. * @msdu_info: msdu descriptor
  524. * @tso_seg_unmap: flag to show if dma unmap is necessary
  525. *
  526. * Return - void
  527. */
  528. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  529. struct dp_tx_msdu_info_s *msdu_info,
  530. bool tso_seg_unmap)
  531. {
  532. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  533. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  534. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  535. tso_info->tso_num_seg_list;
  536. /* do dma unmap for each segment */
  537. if (tso_seg_unmap)
  538. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  539. /* free all tso number segment descriptor though looks only have 1 */
  540. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  541. /* free all tso segment descriptor */
  542. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  543. }
  544. /**
  545. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  546. * @vdev: virtual device handle
  547. * @msdu: network buffer
  548. * @msdu_info: meta data associated with the msdu
  549. *
  550. * Return: QDF_STATUS_SUCCESS success
  551. */
  552. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  553. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  554. {
  555. struct qdf_tso_seg_elem_t *tso_seg;
  556. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  557. struct dp_soc *soc = vdev->pdev->soc;
  558. struct dp_pdev *pdev = vdev->pdev;
  559. struct qdf_tso_info_t *tso_info;
  560. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  561. tso_info = &msdu_info->u.tso_info;
  562. tso_info->curr_seg = NULL;
  563. tso_info->tso_seg_list = NULL;
  564. tso_info->num_segs = num_seg;
  565. msdu_info->frm_type = dp_tx_frm_tso;
  566. tso_info->tso_num_seg_list = NULL;
  567. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  568. while (num_seg) {
  569. tso_seg = dp_tx_tso_desc_alloc(
  570. soc, msdu_info->tx_queue.desc_pool_id);
  571. if (tso_seg) {
  572. tso_seg->next = tso_info->tso_seg_list;
  573. tso_info->tso_seg_list = tso_seg;
  574. num_seg--;
  575. } else {
  576. dp_err_rl("Failed to alloc tso seg desc");
  577. DP_STATS_INC_PKT(vdev->pdev,
  578. tso_stats.tso_no_mem_dropped, 1,
  579. qdf_nbuf_len(msdu));
  580. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  581. return QDF_STATUS_E_NOMEM;
  582. }
  583. }
  584. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  585. tso_num_seg = dp_tso_num_seg_alloc(soc,
  586. msdu_info->tx_queue.desc_pool_id);
  587. if (tso_num_seg) {
  588. tso_num_seg->next = tso_info->tso_num_seg_list;
  589. tso_info->tso_num_seg_list = tso_num_seg;
  590. } else {
  591. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  592. __func__);
  593. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  594. return QDF_STATUS_E_NOMEM;
  595. }
  596. msdu_info->num_seg =
  597. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  598. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  599. msdu_info->num_seg);
  600. if (!(msdu_info->num_seg)) {
  601. /*
  602. * Free allocated TSO seg desc and number seg desc,
  603. * do unmap for segments if dma map has done.
  604. */
  605. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  606. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  607. return QDF_STATUS_E_INVAL;
  608. }
  609. tso_info->curr_seg = tso_info->tso_seg_list;
  610. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  611. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  612. msdu, msdu_info->num_seg);
  613. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  614. tso_info->msdu_stats_idx);
  615. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  616. return QDF_STATUS_SUCCESS;
  617. }
  618. #else
  619. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  620. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  621. {
  622. return QDF_STATUS_E_NOMEM;
  623. }
  624. #endif
  625. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  626. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  627. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  628. /**
  629. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  630. * @vdev: DP Vdev handle
  631. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  632. * @desc_pool_id: Descriptor Pool ID
  633. *
  634. * Return:
  635. */
  636. static
  637. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  638. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  639. {
  640. uint8_t i;
  641. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  642. struct dp_tx_seg_info_s *seg_info;
  643. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  644. struct dp_soc *soc = vdev->pdev->soc;
  645. /* Allocate an extension descriptor */
  646. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  647. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  648. if (!msdu_ext_desc) {
  649. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  650. return NULL;
  651. }
  652. if (msdu_info->exception_fw &&
  653. qdf_unlikely(vdev->mesh_vdev)) {
  654. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  655. &msdu_info->meta_data[0],
  656. sizeof(struct htt_tx_msdu_desc_ext2_t));
  657. qdf_atomic_inc(&soc->num_tx_exception);
  658. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  659. }
  660. switch (msdu_info->frm_type) {
  661. case dp_tx_frm_sg:
  662. case dp_tx_frm_me:
  663. case dp_tx_frm_raw:
  664. seg_info = msdu_info->u.sg_info.curr_seg;
  665. /* Update the buffer pointers in MSDU Extension Descriptor */
  666. for (i = 0; i < seg_info->frag_cnt; i++) {
  667. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  668. seg_info->frags[i].paddr_lo,
  669. seg_info->frags[i].paddr_hi,
  670. seg_info->frags[i].len);
  671. }
  672. break;
  673. case dp_tx_frm_tso:
  674. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  675. &cached_ext_desc[0]);
  676. break;
  677. default:
  678. break;
  679. }
  680. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  681. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  682. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  683. msdu_ext_desc->vaddr);
  684. return msdu_ext_desc;
  685. }
  686. /**
  687. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  688. *
  689. * @skb: skb to be traced
  690. * @msdu_id: msdu_id of the packet
  691. * @vdev_id: vdev_id of the packet
  692. *
  693. * Return: None
  694. */
  695. #ifdef DP_DISABLE_TX_PKT_TRACE
  696. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  697. uint8_t vdev_id)
  698. {
  699. }
  700. #else
  701. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  702. uint8_t vdev_id)
  703. {
  704. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  705. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  706. DPTRACE(qdf_dp_trace_ptr(skb,
  707. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  708. QDF_TRACE_DEFAULT_PDEV_ID,
  709. qdf_nbuf_data_addr(skb),
  710. sizeof(qdf_nbuf_data(skb)),
  711. msdu_id, vdev_id, 0));
  712. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  713. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  714. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  715. msdu_id, QDF_TX));
  716. }
  717. #endif
  718. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  719. /**
  720. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  721. * exception by the upper layer (OS_IF)
  722. * @soc: DP soc handle
  723. * @nbuf: packet to be transmitted
  724. *
  725. * Returns: 1 if the packet is marked as exception,
  726. * 0, if the packet is not marked as exception.
  727. */
  728. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  729. qdf_nbuf_t nbuf)
  730. {
  731. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  732. }
  733. #else
  734. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  735. qdf_nbuf_t nbuf)
  736. {
  737. return 0;
  738. }
  739. #endif
  740. /**
  741. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  742. * @vdev: DP vdev handle
  743. * @nbuf: skb
  744. * @desc_pool_id: Descriptor pool ID
  745. * @meta_data: Metadata to the fw
  746. * @tx_exc_metadata: Handle that holds exception path metadata
  747. * Allocate and prepare Tx descriptor with msdu information.
  748. *
  749. * Return: Pointer to Tx Descriptor on success,
  750. * NULL on failure
  751. */
  752. static
  753. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  754. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  755. struct dp_tx_msdu_info_s *msdu_info,
  756. struct cdp_tx_exception_metadata *tx_exc_metadata)
  757. {
  758. uint8_t align_pad;
  759. uint8_t is_exception = 0;
  760. uint8_t htt_hdr_size;
  761. struct dp_tx_desc_s *tx_desc;
  762. struct dp_pdev *pdev = vdev->pdev;
  763. struct dp_soc *soc = pdev->soc;
  764. if (dp_tx_limit_check(vdev))
  765. return NULL;
  766. /* Allocate software Tx descriptor */
  767. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  768. if (qdf_unlikely(!tx_desc)) {
  769. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  770. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  771. return NULL;
  772. }
  773. dp_tx_outstanding_inc(pdev);
  774. /* Initialize the SW tx descriptor */
  775. tx_desc->nbuf = nbuf;
  776. tx_desc->frm_type = dp_tx_frm_std;
  777. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  778. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  779. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  780. tx_desc->vdev_id = vdev->vdev_id;
  781. tx_desc->pdev = pdev;
  782. tx_desc->msdu_ext_desc = NULL;
  783. tx_desc->pkt_offset = 0;
  784. tx_desc->length = qdf_nbuf_headlen(nbuf);
  785. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  786. if (qdf_unlikely(vdev->multipass_en)) {
  787. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  788. goto failure;
  789. }
  790. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  791. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  792. is_exception = 1;
  793. /*
  794. * For special modes (vdev_type == ocb or mesh), data frames should be
  795. * transmitted using varying transmit parameters (tx spec) which include
  796. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  797. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  798. * These frames are sent as exception packets to firmware.
  799. *
  800. * HW requirement is that metadata should always point to a
  801. * 8-byte aligned address. So we add alignment pad to start of buffer.
  802. * HTT Metadata should be ensured to be multiple of 8-bytes,
  803. * to get 8-byte aligned start address along with align_pad added
  804. *
  805. * |-----------------------------|
  806. * | |
  807. * |-----------------------------| <-----Buffer Pointer Address given
  808. * | | ^ in HW descriptor (aligned)
  809. * | HTT Metadata | |
  810. * | | |
  811. * | | | Packet Offset given in descriptor
  812. * | | |
  813. * |-----------------------------| |
  814. * | Alignment Pad | v
  815. * |-----------------------------| <----- Actual buffer start address
  816. * | SKB Data | (Unaligned)
  817. * | |
  818. * | |
  819. * | |
  820. * | |
  821. * | |
  822. * |-----------------------------|
  823. */
  824. if (qdf_unlikely((msdu_info->exception_fw)) ||
  825. (vdev->opmode == wlan_op_mode_ocb) ||
  826. (tx_exc_metadata &&
  827. tx_exc_metadata->is_tx_sniffer)) {
  828. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  829. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  830. DP_STATS_INC(vdev,
  831. tx_i.dropped.headroom_insufficient, 1);
  832. goto failure;
  833. }
  834. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  835. dp_tx_err("qdf_nbuf_push_head failed");
  836. goto failure;
  837. }
  838. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  839. msdu_info);
  840. if (htt_hdr_size == 0)
  841. goto failure;
  842. tx_desc->length = qdf_nbuf_headlen(nbuf);
  843. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  844. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  845. is_exception = 1;
  846. tx_desc->length -= tx_desc->pkt_offset;
  847. }
  848. #if !TQM_BYPASS_WAR
  849. if (is_exception || tx_exc_metadata)
  850. #endif
  851. {
  852. /* Temporary WAR due to TQM VP issues */
  853. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  854. qdf_atomic_inc(&soc->num_tx_exception);
  855. }
  856. return tx_desc;
  857. failure:
  858. dp_tx_desc_release(tx_desc, desc_pool_id);
  859. return NULL;
  860. }
  861. /**
  862. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  863. * @vdev: DP vdev handle
  864. * @nbuf: skb
  865. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  866. * @desc_pool_id : Descriptor Pool ID
  867. *
  868. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  869. * information. For frames wth fragments, allocate and prepare
  870. * an MSDU extension descriptor
  871. *
  872. * Return: Pointer to Tx Descriptor on success,
  873. * NULL on failure
  874. */
  875. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  876. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  877. uint8_t desc_pool_id)
  878. {
  879. struct dp_tx_desc_s *tx_desc;
  880. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  881. struct dp_pdev *pdev = vdev->pdev;
  882. struct dp_soc *soc = pdev->soc;
  883. if (dp_tx_limit_check(vdev))
  884. return NULL;
  885. /* Allocate software Tx descriptor */
  886. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  887. if (!tx_desc) {
  888. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  889. return NULL;
  890. }
  891. dp_tx_outstanding_inc(pdev);
  892. /* Initialize the SW tx descriptor */
  893. tx_desc->nbuf = nbuf;
  894. tx_desc->frm_type = msdu_info->frm_type;
  895. tx_desc->tx_encap_type = vdev->tx_encap_type;
  896. tx_desc->vdev_id = vdev->vdev_id;
  897. tx_desc->pdev = pdev;
  898. tx_desc->pkt_offset = 0;
  899. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  900. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  901. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  902. /* Handle scattered frames - TSO/SG/ME */
  903. /* Allocate and prepare an extension descriptor for scattered frames */
  904. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  905. if (!msdu_ext_desc) {
  906. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  907. goto failure;
  908. }
  909. #if TQM_BYPASS_WAR
  910. /* Temporary WAR due to TQM VP issues */
  911. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  912. qdf_atomic_inc(&soc->num_tx_exception);
  913. #endif
  914. if (qdf_unlikely(msdu_info->exception_fw))
  915. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  916. tx_desc->msdu_ext_desc = msdu_ext_desc;
  917. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  918. tx_desc->dma_addr = msdu_ext_desc->paddr;
  919. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  920. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  921. else
  922. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  923. return tx_desc;
  924. failure:
  925. dp_tx_desc_release(tx_desc, desc_pool_id);
  926. return NULL;
  927. }
  928. /**
  929. * dp_tx_prepare_raw() - Prepare RAW packet TX
  930. * @vdev: DP vdev handle
  931. * @nbuf: buffer pointer
  932. * @seg_info: Pointer to Segment info Descriptor to be prepared
  933. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  934. * descriptor
  935. *
  936. * Return:
  937. */
  938. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  939. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  940. {
  941. qdf_nbuf_t curr_nbuf = NULL;
  942. uint16_t total_len = 0;
  943. qdf_dma_addr_t paddr;
  944. int32_t i;
  945. int32_t mapped_buf_num = 0;
  946. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  947. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  948. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  949. /* Continue only if frames are of DATA type */
  950. if (!DP_FRAME_IS_DATA(qos_wh)) {
  951. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  952. dp_tx_debug("Pkt. recd is of not data type");
  953. goto error;
  954. }
  955. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  956. if (vdev->raw_mode_war &&
  957. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  958. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  959. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  960. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  961. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  962. /*
  963. * Number of nbuf's must not exceed the size of the frags
  964. * array in seg_info.
  965. */
  966. if (i >= DP_TX_MAX_NUM_FRAGS) {
  967. dp_err_rl("nbuf cnt exceeds the max number of segs");
  968. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  969. goto error;
  970. }
  971. if (QDF_STATUS_SUCCESS !=
  972. qdf_nbuf_map_nbytes_single(vdev->osdev,
  973. curr_nbuf,
  974. QDF_DMA_TO_DEVICE,
  975. curr_nbuf->len)) {
  976. dp_tx_err("%s dma map error ", __func__);
  977. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  978. goto error;
  979. }
  980. /* Update the count of mapped nbuf's */
  981. mapped_buf_num++;
  982. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  983. seg_info->frags[i].paddr_lo = paddr;
  984. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  985. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  986. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  987. total_len += qdf_nbuf_len(curr_nbuf);
  988. }
  989. seg_info->frag_cnt = i;
  990. seg_info->total_len = total_len;
  991. seg_info->next = NULL;
  992. sg_info->curr_seg = seg_info;
  993. msdu_info->frm_type = dp_tx_frm_raw;
  994. msdu_info->num_seg = 1;
  995. return nbuf;
  996. error:
  997. i = 0;
  998. while (nbuf) {
  999. curr_nbuf = nbuf;
  1000. if (i < mapped_buf_num) {
  1001. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1002. QDF_DMA_TO_DEVICE,
  1003. curr_nbuf->len);
  1004. i++;
  1005. }
  1006. nbuf = qdf_nbuf_next(nbuf);
  1007. qdf_nbuf_free(curr_nbuf);
  1008. }
  1009. return NULL;
  1010. }
  1011. /**
  1012. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1013. * @soc: DP soc handle
  1014. * @nbuf: Buffer pointer
  1015. *
  1016. * unmap the chain of nbufs that belong to this RAW frame.
  1017. *
  1018. * Return: None
  1019. */
  1020. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1021. qdf_nbuf_t nbuf)
  1022. {
  1023. qdf_nbuf_t cur_nbuf = nbuf;
  1024. do {
  1025. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1026. QDF_DMA_TO_DEVICE,
  1027. cur_nbuf->len);
  1028. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1029. } while (cur_nbuf);
  1030. }
  1031. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1032. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  1033. { \
  1034. qdf_nbuf_t nbuf_local; \
  1035. struct dp_vdev *vdev_local = vdev_hdl; \
  1036. do { \
  1037. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  1038. break; \
  1039. nbuf_local = nbuf; \
  1040. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  1041. htt_cmn_pkt_type_raw)) \
  1042. break; \
  1043. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  1044. break; \
  1045. else if (qdf_nbuf_is_tso((nbuf_local))) \
  1046. break; \
  1047. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  1048. (nbuf_local), \
  1049. NULL, 1, 0); \
  1050. } while (0); \
  1051. }
  1052. #else
  1053. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  1054. #endif
  1055. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1056. /**
  1057. * dp_tx_update_stats() - Update soc level tx stats
  1058. * @soc: DP soc handle
  1059. * @nbuf: packet being transmitted
  1060. *
  1061. * Returns: none
  1062. */
  1063. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1064. qdf_nbuf_t nbuf)
  1065. {
  1066. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1067. }
  1068. /**
  1069. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1070. * @soc: Datapath soc handle
  1071. * @tx_desc: tx packet descriptor
  1072. * @tid: TID for pkt transmission
  1073. *
  1074. * Returns: 1, if coalescing is to be done
  1075. * 0, if coalescing is not to be done
  1076. */
  1077. static inline int
  1078. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1079. struct dp_tx_desc_s *tx_desc,
  1080. uint8_t tid)
  1081. {
  1082. struct dp_swlm *swlm = &soc->swlm;
  1083. union swlm_data swlm_query_data;
  1084. struct dp_swlm_tcl_data tcl_data;
  1085. QDF_STATUS status;
  1086. int ret;
  1087. if (qdf_unlikely(!swlm->is_enabled))
  1088. return 0;
  1089. tcl_data.nbuf = tx_desc->nbuf;
  1090. tcl_data.tid = tid;
  1091. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1092. swlm_query_data.tcl_data = &tcl_data;
  1093. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1094. if (QDF_IS_STATUS_ERROR(status)) {
  1095. dp_swlm_tcl_reset_session_data(soc);
  1096. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1097. return 0;
  1098. }
  1099. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1100. if (ret) {
  1101. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1102. } else {
  1103. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1104. }
  1105. return ret;
  1106. }
  1107. /**
  1108. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1109. * @soc: Datapath soc handle
  1110. * @hal_ring_hdl: HAL ring handle
  1111. * @coalesce: Coalesce the current write or not
  1112. *
  1113. * Returns: none
  1114. */
  1115. static inline void
  1116. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1117. int coalesce)
  1118. {
  1119. if (coalesce)
  1120. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1121. else
  1122. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1123. }
  1124. #else
  1125. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1126. qdf_nbuf_t nbuf)
  1127. {
  1128. }
  1129. static inline int
  1130. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1131. struct dp_tx_desc_s *tx_desc,
  1132. uint8_t tid)
  1133. {
  1134. return 0;
  1135. }
  1136. static inline void
  1137. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1138. int coalesce)
  1139. {
  1140. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1141. }
  1142. #endif
  1143. #ifdef FEATURE_RUNTIME_PM
  1144. /**
  1145. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1146. * @soc: Datapath soc handle
  1147. * @hal_ring_hdl: HAL ring handle
  1148. * @coalesce: Coalesce the current write or not
  1149. *
  1150. * Wrapper for HAL ring access end for data transmission for
  1151. * FEATURE_RUNTIME_PM
  1152. *
  1153. * Returns: none
  1154. */
  1155. static inline void
  1156. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1157. hal_ring_handle_t hal_ring_hdl,
  1158. int coalesce)
  1159. {
  1160. int ret;
  1161. ret = hif_pm_runtime_get(soc->hif_handle,
  1162. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1163. switch (ret) {
  1164. case 0:
  1165. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1166. hif_pm_runtime_put(soc->hif_handle,
  1167. RTPM_ID_DW_TX_HW_ENQUEUE);
  1168. break;
  1169. /*
  1170. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1171. * take the dp runtime refcount using dp_runtime_get,
  1172. * check link state,if up, write TX ring HP, else just set flush event.
  1173. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1174. * zero or time out, then flush pending tx.
  1175. */
  1176. case -EBUSY:
  1177. case -EINPROGRESS:
  1178. dp_runtime_get(soc);
  1179. if (hif_pm_get_link_state(soc->hif_handle) ==
  1180. HIF_PM_LINK_STATE_UP) {
  1181. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1182. } else {
  1183. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1184. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1185. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1186. }
  1187. dp_runtime_put(soc);
  1188. break;
  1189. default:
  1190. dp_runtime_get(soc);
  1191. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1192. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1193. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1194. dp_runtime_put(soc);
  1195. }
  1196. }
  1197. #else
  1198. static inline void
  1199. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1200. hal_ring_handle_t hal_ring_hdl,
  1201. int coalesce)
  1202. {
  1203. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1204. }
  1205. #endif
  1206. /**
  1207. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1208. * @soc: DP Soc Handle
  1209. * @vdev: DP vdev handle
  1210. * @tx_desc: Tx Descriptor Handle
  1211. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1212. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1213. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1214. * @tx_exc_metadata: Handle that holds exception path meta data
  1215. *
  1216. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1217. * from software Tx descriptor
  1218. *
  1219. * Return: QDF_STATUS_SUCCESS: success
  1220. * QDF_STATUS_E_RESOURCES: Error return
  1221. */
  1222. static QDF_STATUS
  1223. dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1224. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1225. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1226. struct dp_tx_msdu_info_s *msdu_info)
  1227. {
  1228. void *hal_tx_desc;
  1229. uint32_t *hal_tx_desc_cached;
  1230. int coalesce = 0;
  1231. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1232. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  1233. uint8_t tid = msdu_info->tid;
  1234. /*
  1235. * Setting it initialization statically here to avoid
  1236. * a memset call jump with qdf_mem_set call
  1237. */
  1238. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1239. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1240. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1241. tx_exc_metadata->sec_type : vdev->sec_type);
  1242. /* Return Buffer Manager ID */
  1243. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1244. hal_ring_handle_t hal_ring_hdl = NULL;
  1245. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1246. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1247. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1248. return QDF_STATUS_E_RESOURCES;
  1249. }
  1250. hal_tx_desc_cached = (void *) cached_desc;
  1251. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1252. tx_desc->dma_addr, bm_id, tx_desc->id,
  1253. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1254. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1255. vdev->lmac_id);
  1256. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1257. vdev->search_type);
  1258. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1259. vdev->bss_ast_idx);
  1260. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1261. vdev->dscp_tid_map_id);
  1262. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1263. sec_type_map[sec_type]);
  1264. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1265. (vdev->bss_ast_hash & 0xF));
  1266. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1267. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1268. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1269. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1270. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1271. vdev->hal_desc_addr_search_flags);
  1272. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1273. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1274. /* verify checksum offload configuration*/
  1275. if (vdev->csum_enabled &&
  1276. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1277. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1278. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1279. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1280. }
  1281. if (tid != HTT_TX_EXT_TID_INVALID)
  1282. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1283. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1284. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1285. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1286. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1287. soc->wlan_cfg_ctx)))
  1288. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1289. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1290. tx_desc->length,
  1291. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
  1292. (uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
  1293. tx_desc->id);
  1294. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1295. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1296. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1297. "%s %d : HAL RING Access Failed -- %pK",
  1298. __func__, __LINE__, hal_ring_hdl);
  1299. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1300. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1301. return status;
  1302. }
  1303. /* Sync cached descriptor with HW */
  1304. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1305. if (qdf_unlikely(!hal_tx_desc)) {
  1306. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1307. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1308. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1309. goto ring_access_fail;
  1310. }
  1311. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1312. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1313. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1314. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1315. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1316. dp_tx_update_stats(soc, tx_desc->nbuf);
  1317. status = QDF_STATUS_SUCCESS;
  1318. ring_access_fail:
  1319. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  1320. return status;
  1321. }
  1322. /**
  1323. * dp_cce_classify() - Classify the frame based on CCE rules
  1324. * @vdev: DP vdev handle
  1325. * @nbuf: skb
  1326. *
  1327. * Classify frames based on CCE rules
  1328. * Return: bool( true if classified,
  1329. * else false)
  1330. */
  1331. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1332. {
  1333. qdf_ether_header_t *eh = NULL;
  1334. uint16_t ether_type;
  1335. qdf_llc_t *llcHdr;
  1336. qdf_nbuf_t nbuf_clone = NULL;
  1337. qdf_dot3_qosframe_t *qos_wh = NULL;
  1338. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1339. /*
  1340. * In case of mesh packets or hlos tid override enabled,
  1341. * don't do any classification
  1342. */
  1343. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1344. & DP_TX_SKIP_CCE_CLASSIFY))
  1345. return false;
  1346. }
  1347. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1348. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1349. ether_type = eh->ether_type;
  1350. llcHdr = (qdf_llc_t *)(nbuf->data +
  1351. sizeof(qdf_ether_header_t));
  1352. } else {
  1353. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1354. /* For encrypted packets don't do any classification */
  1355. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1356. return false;
  1357. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1358. if (qdf_unlikely(
  1359. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1360. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1361. ether_type = *(uint16_t *)(nbuf->data
  1362. + QDF_IEEE80211_4ADDR_HDR_LEN
  1363. + sizeof(qdf_llc_t)
  1364. - sizeof(ether_type));
  1365. llcHdr = (qdf_llc_t *)(nbuf->data +
  1366. QDF_IEEE80211_4ADDR_HDR_LEN);
  1367. } else {
  1368. ether_type = *(uint16_t *)(nbuf->data
  1369. + QDF_IEEE80211_3ADDR_HDR_LEN
  1370. + sizeof(qdf_llc_t)
  1371. - sizeof(ether_type));
  1372. llcHdr = (qdf_llc_t *)(nbuf->data +
  1373. QDF_IEEE80211_3ADDR_HDR_LEN);
  1374. }
  1375. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1376. && (ether_type ==
  1377. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1378. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1379. return true;
  1380. }
  1381. }
  1382. return false;
  1383. }
  1384. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1385. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1386. sizeof(*llcHdr));
  1387. nbuf_clone = qdf_nbuf_clone(nbuf);
  1388. if (qdf_unlikely(nbuf_clone)) {
  1389. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1390. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1391. qdf_nbuf_pull_head(nbuf_clone,
  1392. sizeof(qdf_net_vlanhdr_t));
  1393. }
  1394. }
  1395. } else {
  1396. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1397. nbuf_clone = qdf_nbuf_clone(nbuf);
  1398. if (qdf_unlikely(nbuf_clone)) {
  1399. qdf_nbuf_pull_head(nbuf_clone,
  1400. sizeof(qdf_net_vlanhdr_t));
  1401. }
  1402. }
  1403. }
  1404. if (qdf_unlikely(nbuf_clone))
  1405. nbuf = nbuf_clone;
  1406. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1407. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1408. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1409. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1410. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1411. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1412. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1413. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1414. if (qdf_unlikely(nbuf_clone))
  1415. qdf_nbuf_free(nbuf_clone);
  1416. return true;
  1417. }
  1418. if (qdf_unlikely(nbuf_clone))
  1419. qdf_nbuf_free(nbuf_clone);
  1420. return false;
  1421. }
  1422. /**
  1423. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1424. * @vdev: DP vdev handle
  1425. * @nbuf: skb
  1426. *
  1427. * Extract the DSCP or PCP information from frame and map into TID value.
  1428. *
  1429. * Return: void
  1430. */
  1431. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1432. struct dp_tx_msdu_info_s *msdu_info)
  1433. {
  1434. uint8_t tos = 0, dscp_tid_override = 0;
  1435. uint8_t *hdr_ptr, *L3datap;
  1436. uint8_t is_mcast = 0;
  1437. qdf_ether_header_t *eh = NULL;
  1438. qdf_ethervlan_header_t *evh = NULL;
  1439. uint16_t ether_type;
  1440. qdf_llc_t *llcHdr;
  1441. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1442. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1443. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1444. eh = (qdf_ether_header_t *)nbuf->data;
  1445. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1446. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1447. } else {
  1448. qdf_dot3_qosframe_t *qos_wh =
  1449. (qdf_dot3_qosframe_t *) nbuf->data;
  1450. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1451. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1452. return;
  1453. }
  1454. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1455. ether_type = eh->ether_type;
  1456. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1457. /*
  1458. * Check if packet is dot3 or eth2 type.
  1459. */
  1460. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1461. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1462. sizeof(*llcHdr));
  1463. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1464. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1465. sizeof(*llcHdr);
  1466. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1467. + sizeof(*llcHdr) +
  1468. sizeof(qdf_net_vlanhdr_t));
  1469. } else {
  1470. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1471. sizeof(*llcHdr);
  1472. }
  1473. } else {
  1474. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1475. evh = (qdf_ethervlan_header_t *) eh;
  1476. ether_type = evh->ether_type;
  1477. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1478. }
  1479. }
  1480. /*
  1481. * Find priority from IP TOS DSCP field
  1482. */
  1483. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1484. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1485. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1486. /* Only for unicast frames */
  1487. if (!is_mcast) {
  1488. /* send it on VO queue */
  1489. msdu_info->tid = DP_VO_TID;
  1490. }
  1491. } else {
  1492. /*
  1493. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1494. * from TOS byte.
  1495. */
  1496. tos = ip->ip_tos;
  1497. dscp_tid_override = 1;
  1498. }
  1499. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1500. /* TODO
  1501. * use flowlabel
  1502. *igmpmld cases to be handled in phase 2
  1503. */
  1504. unsigned long ver_pri_flowlabel;
  1505. unsigned long pri;
  1506. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1507. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1508. DP_IPV6_PRIORITY_SHIFT;
  1509. tos = pri;
  1510. dscp_tid_override = 1;
  1511. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1512. msdu_info->tid = DP_VO_TID;
  1513. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1514. /* Only for unicast frames */
  1515. if (!is_mcast) {
  1516. /* send ucast arp on VO queue */
  1517. msdu_info->tid = DP_VO_TID;
  1518. }
  1519. }
  1520. /*
  1521. * Assign all MCAST packets to BE
  1522. */
  1523. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1524. if (is_mcast) {
  1525. tos = 0;
  1526. dscp_tid_override = 1;
  1527. }
  1528. }
  1529. if (dscp_tid_override == 1) {
  1530. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1531. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1532. }
  1533. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1534. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1535. return;
  1536. }
  1537. /**
  1538. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1539. * @vdev: DP vdev handle
  1540. * @nbuf: skb
  1541. *
  1542. * Software based TID classification is required when more than 2 DSCP-TID
  1543. * mapping tables are needed.
  1544. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1545. *
  1546. * Return: void
  1547. */
  1548. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1549. struct dp_tx_msdu_info_s *msdu_info)
  1550. {
  1551. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1552. /*
  1553. * skip_sw_tid_classification flag will set in below cases-
  1554. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1555. * 2. hlos_tid_override enabled for vdev
  1556. * 3. mesh mode enabled for vdev
  1557. */
  1558. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1559. /* Update tid in msdu_info from skb priority */
  1560. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1561. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1562. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1563. return;
  1564. }
  1565. return;
  1566. }
  1567. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1568. }
  1569. #ifdef FEATURE_WLAN_TDLS
  1570. /**
  1571. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1572. * @soc: datapath SOC
  1573. * @vdev: datapath vdev
  1574. * @tx_desc: TX descriptor
  1575. *
  1576. * Return: None
  1577. */
  1578. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1579. struct dp_vdev *vdev,
  1580. struct dp_tx_desc_s *tx_desc)
  1581. {
  1582. if (vdev) {
  1583. if (vdev->is_tdls_frame) {
  1584. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1585. vdev->is_tdls_frame = false;
  1586. }
  1587. }
  1588. }
  1589. /**
  1590. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1591. * @soc: dp_soc handle
  1592. * @tx_desc: TX descriptor
  1593. * @vdev: datapath vdev handle
  1594. *
  1595. * Return: None
  1596. */
  1597. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1598. struct dp_tx_desc_s *tx_desc)
  1599. {
  1600. struct hal_tx_completion_status ts = {0};
  1601. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1602. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1603. DP_MOD_ID_TDLS);
  1604. if (qdf_unlikely(!vdev)) {
  1605. dp_err_rl("vdev is null!");
  1606. goto error;
  1607. }
  1608. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1609. if (vdev->tx_non_std_data_callback.func) {
  1610. qdf_nbuf_set_next(nbuf, NULL);
  1611. vdev->tx_non_std_data_callback.func(
  1612. vdev->tx_non_std_data_callback.ctxt,
  1613. nbuf, ts.status);
  1614. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1615. return;
  1616. } else {
  1617. dp_err_rl("callback func is null");
  1618. }
  1619. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1620. error:
  1621. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1622. qdf_nbuf_free(nbuf);
  1623. }
  1624. /**
  1625. * dp_tx_msdu_single_map() - do nbuf map
  1626. * @vdev: DP vdev handle
  1627. * @tx_desc: DP TX descriptor pointer
  1628. * @nbuf: skb pointer
  1629. *
  1630. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1631. * operation done in other component.
  1632. *
  1633. * Return: QDF_STATUS
  1634. */
  1635. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1636. struct dp_tx_desc_s *tx_desc,
  1637. qdf_nbuf_t nbuf)
  1638. {
  1639. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1640. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1641. nbuf,
  1642. QDF_DMA_TO_DEVICE,
  1643. nbuf->len);
  1644. else
  1645. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1646. QDF_DMA_TO_DEVICE);
  1647. }
  1648. #else
  1649. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1650. struct dp_vdev *vdev,
  1651. struct dp_tx_desc_s *tx_desc)
  1652. {
  1653. }
  1654. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1655. struct dp_tx_desc_s *tx_desc)
  1656. {
  1657. }
  1658. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1659. struct dp_tx_desc_s *tx_desc,
  1660. qdf_nbuf_t nbuf)
  1661. {
  1662. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1663. nbuf,
  1664. QDF_DMA_TO_DEVICE,
  1665. nbuf->len);
  1666. }
  1667. #endif
  1668. #ifdef MESH_MODE_SUPPORT
  1669. /**
  1670. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1671. * @soc: datapath SOC
  1672. * @vdev: datapath vdev
  1673. * @tx_desc: TX descriptor
  1674. *
  1675. * Return: None
  1676. */
  1677. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1678. struct dp_vdev *vdev,
  1679. struct dp_tx_desc_s *tx_desc)
  1680. {
  1681. if (qdf_unlikely(vdev->mesh_vdev))
  1682. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1683. }
  1684. /**
  1685. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1686. * @soc: dp_soc handle
  1687. * @tx_desc: TX descriptor
  1688. * @vdev: datapath vdev handle
  1689. *
  1690. * Return: None
  1691. */
  1692. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1693. struct dp_tx_desc_s *tx_desc)
  1694. {
  1695. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1696. struct dp_vdev *vdev = NULL;
  1697. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1698. qdf_nbuf_free(nbuf);
  1699. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1700. } else {
  1701. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1702. DP_MOD_ID_MESH);
  1703. if (vdev && vdev->osif_tx_free_ext)
  1704. vdev->osif_tx_free_ext((nbuf));
  1705. else
  1706. qdf_nbuf_free(nbuf);
  1707. if (vdev)
  1708. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1709. }
  1710. }
  1711. #else
  1712. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1713. struct dp_vdev *vdev,
  1714. struct dp_tx_desc_s *tx_desc)
  1715. {
  1716. }
  1717. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1718. struct dp_tx_desc_s *tx_desc)
  1719. {
  1720. }
  1721. #endif
  1722. /**
  1723. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1724. * @vdev: DP vdev handle
  1725. * @nbuf: skb
  1726. *
  1727. * Return: 1 if frame needs to be dropped else 0
  1728. */
  1729. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1730. {
  1731. struct dp_pdev *pdev = NULL;
  1732. struct dp_ast_entry *src_ast_entry = NULL;
  1733. struct dp_ast_entry *dst_ast_entry = NULL;
  1734. struct dp_soc *soc = NULL;
  1735. qdf_assert(vdev);
  1736. pdev = vdev->pdev;
  1737. qdf_assert(pdev);
  1738. soc = pdev->soc;
  1739. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1740. (soc, dstmac, vdev->pdev->pdev_id);
  1741. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1742. (soc, srcmac, vdev->pdev->pdev_id);
  1743. if (dst_ast_entry && src_ast_entry) {
  1744. if (dst_ast_entry->peer_id ==
  1745. src_ast_entry->peer_id)
  1746. return 1;
  1747. }
  1748. return 0;
  1749. }
  1750. /**
  1751. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1752. * @vdev: DP vdev handle
  1753. * @nbuf: skb
  1754. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1755. * @meta_data: Metadata to the fw
  1756. * @tx_q: Tx queue to be used for this Tx frame
  1757. * @peer_id: peer_id of the peer in case of NAWDS frames
  1758. * @tx_exc_metadata: Handle that holds exception path metadata
  1759. *
  1760. * Return: NULL on success,
  1761. * nbuf when it fails to send
  1762. */
  1763. qdf_nbuf_t
  1764. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1765. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1766. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1767. {
  1768. struct dp_pdev *pdev = vdev->pdev;
  1769. struct dp_soc *soc = pdev->soc;
  1770. struct dp_tx_desc_s *tx_desc;
  1771. QDF_STATUS status;
  1772. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1773. uint16_t htt_tcl_metadata = 0;
  1774. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1775. uint8_t tid = msdu_info->tid;
  1776. struct cdp_tid_tx_stats *tid_stats = NULL;
  1777. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1778. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1779. msdu_info, tx_exc_metadata);
  1780. if (!tx_desc) {
  1781. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1782. vdev, tx_q->desc_pool_id);
  1783. drop_code = TX_DESC_ERR;
  1784. goto fail_return;
  1785. }
  1786. if (qdf_unlikely(soc->cce_disable)) {
  1787. if (dp_cce_classify(vdev, nbuf) == true) {
  1788. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1789. tid = DP_VO_TID;
  1790. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1791. }
  1792. }
  1793. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1794. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1795. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1796. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1797. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1798. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1799. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1800. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1801. peer_id);
  1802. } else
  1803. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1804. if (msdu_info->exception_fw)
  1805. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1806. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1807. !pdev->enhanced_stats_en);
  1808. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1809. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1810. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1811. /* Handle failure */
  1812. dp_err("qdf_nbuf_map failed");
  1813. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1814. drop_code = TX_DMA_MAP_ERR;
  1815. goto release_desc;
  1816. }
  1817. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1818. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1819. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1820. tx_exc_metadata, msdu_info);
  1821. if (status != QDF_STATUS_SUCCESS) {
  1822. dp_tx_err("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1823. tx_desc, tx_q->ring_id);
  1824. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1825. QDF_DMA_TO_DEVICE,
  1826. nbuf->len);
  1827. drop_code = TX_HW_ENQUEUE;
  1828. goto release_desc;
  1829. }
  1830. return NULL;
  1831. release_desc:
  1832. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1833. fail_return:
  1834. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1835. tid_stats = &pdev->stats.tid_stats.
  1836. tid_tx_stats[tx_q->ring_id][tid];
  1837. tid_stats->swdrop_cnt[drop_code]++;
  1838. return nbuf;
  1839. }
  1840. /**
  1841. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1842. * @soc: Soc handle
  1843. * @desc: software Tx descriptor to be processed
  1844. *
  1845. * Return: none
  1846. */
  1847. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1848. struct dp_tx_desc_s *desc)
  1849. {
  1850. qdf_nbuf_t nbuf = desc->nbuf;
  1851. /* nbuf already freed in vdev detach path */
  1852. if (!nbuf)
  1853. return;
  1854. /* If it is TDLS mgmt, don't unmap or free the frame */
  1855. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1856. return dp_non_std_tx_comp_free_buff(soc, desc);
  1857. /* 0 : MSDU buffer, 1 : MLE */
  1858. if (desc->msdu_ext_desc) {
  1859. /* TSO free */
  1860. if (hal_tx_ext_desc_get_tso_enable(
  1861. desc->msdu_ext_desc->vaddr)) {
  1862. /* unmap eash TSO seg before free the nbuf */
  1863. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1864. desc->tso_num_desc);
  1865. qdf_nbuf_free(nbuf);
  1866. return;
  1867. }
  1868. }
  1869. /* If it's ME frame, dont unmap the cloned nbuf's */
  1870. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1871. goto nbuf_free;
  1872. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  1873. QDF_DMA_TO_DEVICE, nbuf->len);
  1874. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1875. return dp_mesh_tx_comp_free_buff(soc, desc);
  1876. nbuf_free:
  1877. qdf_nbuf_free(nbuf);
  1878. }
  1879. /**
  1880. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1881. * @vdev: DP vdev handle
  1882. * @nbuf: skb
  1883. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1884. *
  1885. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1886. *
  1887. * Return: NULL on success,
  1888. * nbuf when it fails to send
  1889. */
  1890. #if QDF_LOCK_STATS
  1891. noinline
  1892. #else
  1893. #endif
  1894. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1895. struct dp_tx_msdu_info_s *msdu_info)
  1896. {
  1897. uint32_t i;
  1898. struct dp_pdev *pdev = vdev->pdev;
  1899. struct dp_soc *soc = pdev->soc;
  1900. struct dp_tx_desc_s *tx_desc;
  1901. bool is_cce_classified = false;
  1902. QDF_STATUS status;
  1903. uint16_t htt_tcl_metadata = 0;
  1904. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1905. struct cdp_tid_tx_stats *tid_stats = NULL;
  1906. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1907. if (qdf_unlikely(soc->cce_disable)) {
  1908. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1909. if (is_cce_classified) {
  1910. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1911. msdu_info->tid = DP_VO_TID;
  1912. }
  1913. }
  1914. if (msdu_info->frm_type == dp_tx_frm_me)
  1915. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1916. i = 0;
  1917. /* Print statement to track i and num_seg */
  1918. /*
  1919. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1920. * descriptors using information in msdu_info
  1921. */
  1922. while (i < msdu_info->num_seg) {
  1923. /*
  1924. * Setup Tx descriptor for an MSDU, and MSDU extension
  1925. * descriptor
  1926. */
  1927. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1928. tx_q->desc_pool_id);
  1929. if (!tx_desc) {
  1930. if (msdu_info->frm_type == dp_tx_frm_me) {
  1931. prep_desc_fail++;
  1932. dp_tx_me_free_buf(pdev,
  1933. (void *)(msdu_info->u.sg_info
  1934. .curr_seg->frags[0].vaddr));
  1935. if (prep_desc_fail == msdu_info->num_seg) {
  1936. /*
  1937. * Unmap is needed only if descriptor
  1938. * preparation failed for all segments.
  1939. */
  1940. qdf_nbuf_unmap(soc->osdev,
  1941. msdu_info->u.sg_info.
  1942. curr_seg->nbuf,
  1943. QDF_DMA_TO_DEVICE);
  1944. }
  1945. /*
  1946. * Free the nbuf for the current segment
  1947. * and make it point to the next in the list.
  1948. * For me, there are as many segments as there
  1949. * are no of clients.
  1950. */
  1951. qdf_nbuf_free(msdu_info->u.sg_info
  1952. .curr_seg->nbuf);
  1953. if (msdu_info->u.sg_info.curr_seg->next) {
  1954. msdu_info->u.sg_info.curr_seg =
  1955. msdu_info->u.sg_info
  1956. .curr_seg->next;
  1957. nbuf = msdu_info->u.sg_info
  1958. .curr_seg->nbuf;
  1959. }
  1960. i++;
  1961. continue;
  1962. }
  1963. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1964. dp_tx_tso_unmap_segment(soc,
  1965. msdu_info->u.tso_info.
  1966. curr_seg,
  1967. msdu_info->u.tso_info.
  1968. tso_num_seg_list);
  1969. if (msdu_info->u.tso_info.curr_seg->next) {
  1970. msdu_info->u.tso_info.curr_seg =
  1971. msdu_info->u.tso_info.curr_seg->next;
  1972. i++;
  1973. continue;
  1974. }
  1975. }
  1976. goto done;
  1977. }
  1978. if (msdu_info->frm_type == dp_tx_frm_me) {
  1979. tx_desc->me_buffer =
  1980. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1981. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1982. }
  1983. if (is_cce_classified)
  1984. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1985. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1986. if (msdu_info->exception_fw) {
  1987. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1988. }
  1989. /*
  1990. * For frames with multiple segments (TSO, ME), jump to next
  1991. * segment.
  1992. */
  1993. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1994. if (msdu_info->u.tso_info.curr_seg->next) {
  1995. msdu_info->u.tso_info.curr_seg =
  1996. msdu_info->u.tso_info.curr_seg->next;
  1997. /*
  1998. * If this is a jumbo nbuf, then increment the
  1999. * number of nbuf users for each additional
  2000. * segment of the msdu. This will ensure that
  2001. * the skb is freed only after receiving tx
  2002. * completion for all segments of an nbuf
  2003. */
  2004. qdf_nbuf_inc_users(nbuf);
  2005. /* Check with MCL if this is needed */
  2006. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2007. */
  2008. }
  2009. }
  2010. /*
  2011. * Enqueue the Tx MSDU descriptor to HW for transmit
  2012. */
  2013. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  2014. NULL, msdu_info);
  2015. if (status != QDF_STATUS_SUCCESS) {
  2016. dp_info("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2017. tx_desc, tx_q->ring_id);
  2018. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2019. tid_stats = &pdev->stats.tid_stats.
  2020. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2021. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2022. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2023. if (msdu_info->frm_type == dp_tx_frm_me) {
  2024. hw_enq_fail++;
  2025. if (hw_enq_fail == msdu_info->num_seg) {
  2026. /*
  2027. * Unmap is needed only if enqueue
  2028. * failed for all segments.
  2029. */
  2030. qdf_nbuf_unmap(soc->osdev,
  2031. msdu_info->u.sg_info.
  2032. curr_seg->nbuf,
  2033. QDF_DMA_TO_DEVICE);
  2034. }
  2035. /*
  2036. * Free the nbuf for the current segment
  2037. * and make it point to the next in the list.
  2038. * For me, there are as many segments as there
  2039. * are no of clients.
  2040. */
  2041. qdf_nbuf_free(msdu_info->u.sg_info
  2042. .curr_seg->nbuf);
  2043. if (msdu_info->u.sg_info.curr_seg->next) {
  2044. msdu_info->u.sg_info.curr_seg =
  2045. msdu_info->u.sg_info
  2046. .curr_seg->next;
  2047. nbuf = msdu_info->u.sg_info
  2048. .curr_seg->nbuf;
  2049. } else
  2050. break;
  2051. i++;
  2052. continue;
  2053. }
  2054. /*
  2055. * For TSO frames, the nbuf users increment done for
  2056. * the current segment has to be reverted, since the
  2057. * hw enqueue for this segment failed
  2058. */
  2059. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2060. msdu_info->u.tso_info.curr_seg) {
  2061. /*
  2062. * unmap and free current,
  2063. * retransmit remaining segments
  2064. */
  2065. dp_tx_comp_free_buf(soc, tx_desc);
  2066. i++;
  2067. continue;
  2068. }
  2069. goto done;
  2070. }
  2071. /*
  2072. * TODO
  2073. * if tso_info structure can be modified to have curr_seg
  2074. * as first element, following 2 blocks of code (for TSO and SG)
  2075. * can be combined into 1
  2076. */
  2077. /*
  2078. * For Multicast-Unicast converted packets,
  2079. * each converted frame (for a client) is represented as
  2080. * 1 segment
  2081. */
  2082. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2083. (msdu_info->frm_type == dp_tx_frm_me)) {
  2084. if (msdu_info->u.sg_info.curr_seg->next) {
  2085. msdu_info->u.sg_info.curr_seg =
  2086. msdu_info->u.sg_info.curr_seg->next;
  2087. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2088. } else
  2089. break;
  2090. }
  2091. i++;
  2092. }
  2093. nbuf = NULL;
  2094. done:
  2095. return nbuf;
  2096. }
  2097. /**
  2098. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2099. * for SG frames
  2100. * @vdev: DP vdev handle
  2101. * @nbuf: skb
  2102. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2103. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2104. *
  2105. * Return: NULL on success,
  2106. * nbuf when it fails to send
  2107. */
  2108. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2109. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2110. {
  2111. uint32_t cur_frag, nr_frags, i;
  2112. qdf_dma_addr_t paddr;
  2113. struct dp_tx_sg_info_s *sg_info;
  2114. sg_info = &msdu_info->u.sg_info;
  2115. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2116. if (QDF_STATUS_SUCCESS !=
  2117. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2118. QDF_DMA_TO_DEVICE,
  2119. qdf_nbuf_headlen(nbuf))) {
  2120. dp_tx_err("dma map error");
  2121. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2122. qdf_nbuf_free(nbuf);
  2123. return NULL;
  2124. }
  2125. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2126. seg_info->frags[0].paddr_lo = paddr;
  2127. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2128. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2129. seg_info->frags[0].vaddr = (void *) nbuf;
  2130. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2131. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2132. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2133. dp_tx_err("frag dma map error");
  2134. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2135. goto map_err;
  2136. }
  2137. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2138. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2139. seg_info->frags[cur_frag + 1].paddr_hi =
  2140. ((uint64_t) paddr) >> 32;
  2141. seg_info->frags[cur_frag + 1].len =
  2142. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2143. }
  2144. seg_info->frag_cnt = (cur_frag + 1);
  2145. seg_info->total_len = qdf_nbuf_len(nbuf);
  2146. seg_info->next = NULL;
  2147. sg_info->curr_seg = seg_info;
  2148. msdu_info->frm_type = dp_tx_frm_sg;
  2149. msdu_info->num_seg = 1;
  2150. return nbuf;
  2151. map_err:
  2152. /* restore paddr into nbuf before calling unmap */
  2153. qdf_nbuf_mapped_paddr_set(nbuf,
  2154. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2155. ((uint64_t)
  2156. seg_info->frags[0].paddr_hi) << 32));
  2157. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2158. QDF_DMA_TO_DEVICE,
  2159. seg_info->frags[0].len);
  2160. for (i = 1; i <= cur_frag; i++) {
  2161. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2162. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2163. seg_info->frags[i].paddr_hi) << 32),
  2164. seg_info->frags[i].len,
  2165. QDF_DMA_TO_DEVICE);
  2166. }
  2167. qdf_nbuf_free(nbuf);
  2168. return NULL;
  2169. }
  2170. /**
  2171. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2172. * @vdev: DP vdev handle
  2173. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2174. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2175. *
  2176. * Return: NULL on failure,
  2177. * nbuf when extracted successfully
  2178. */
  2179. static
  2180. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2181. struct dp_tx_msdu_info_s *msdu_info,
  2182. uint16_t ppdu_cookie)
  2183. {
  2184. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2185. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2186. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2187. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2188. (msdu_info->meta_data[5], 1);
  2189. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2190. (msdu_info->meta_data[5], 1);
  2191. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2192. (msdu_info->meta_data[6], ppdu_cookie);
  2193. msdu_info->exception_fw = 1;
  2194. msdu_info->is_tx_sniffer = 1;
  2195. }
  2196. #ifdef MESH_MODE_SUPPORT
  2197. /**
  2198. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2199. and prepare msdu_info for mesh frames.
  2200. * @vdev: DP vdev handle
  2201. * @nbuf: skb
  2202. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2203. *
  2204. * Return: NULL on failure,
  2205. * nbuf when extracted successfully
  2206. */
  2207. static
  2208. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2209. struct dp_tx_msdu_info_s *msdu_info)
  2210. {
  2211. struct meta_hdr_s *mhdr;
  2212. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2213. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2214. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2215. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2216. msdu_info->exception_fw = 0;
  2217. goto remove_meta_hdr;
  2218. }
  2219. msdu_info->exception_fw = 1;
  2220. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2221. meta_data->host_tx_desc_pool = 1;
  2222. meta_data->update_peer_cache = 1;
  2223. meta_data->learning_frame = 1;
  2224. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2225. meta_data->power = mhdr->power;
  2226. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2227. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2228. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2229. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2230. meta_data->dyn_bw = 1;
  2231. meta_data->valid_pwr = 1;
  2232. meta_data->valid_mcs_mask = 1;
  2233. meta_data->valid_nss_mask = 1;
  2234. meta_data->valid_preamble_type = 1;
  2235. meta_data->valid_retries = 1;
  2236. meta_data->valid_bw_info = 1;
  2237. }
  2238. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2239. meta_data->encrypt_type = 0;
  2240. meta_data->valid_encrypt_type = 1;
  2241. meta_data->learning_frame = 0;
  2242. }
  2243. meta_data->valid_key_flags = 1;
  2244. meta_data->key_flags = (mhdr->keyix & 0x3);
  2245. remove_meta_hdr:
  2246. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2247. dp_tx_err("qdf_nbuf_pull_head failed");
  2248. qdf_nbuf_free(nbuf);
  2249. return NULL;
  2250. }
  2251. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2252. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2253. " tid %d to_fw %d",
  2254. msdu_info->meta_data[0],
  2255. msdu_info->meta_data[1],
  2256. msdu_info->meta_data[2],
  2257. msdu_info->meta_data[3],
  2258. msdu_info->meta_data[4],
  2259. msdu_info->meta_data[5],
  2260. msdu_info->tid, msdu_info->exception_fw);
  2261. return nbuf;
  2262. }
  2263. #else
  2264. static
  2265. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2266. struct dp_tx_msdu_info_s *msdu_info)
  2267. {
  2268. return nbuf;
  2269. }
  2270. #endif
  2271. /**
  2272. * dp_check_exc_metadata() - Checks if parameters are valid
  2273. * @tx_exc - holds all exception path parameters
  2274. *
  2275. * Returns true when all the parameters are valid else false
  2276. *
  2277. */
  2278. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2279. {
  2280. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2281. HTT_INVALID_TID);
  2282. bool invalid_encap_type =
  2283. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2284. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2285. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2286. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2287. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2288. tx_exc->ppdu_cookie == 0);
  2289. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2290. invalid_cookie) {
  2291. return false;
  2292. }
  2293. return true;
  2294. }
  2295. #ifdef ATH_SUPPORT_IQUE
  2296. /**
  2297. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2298. * @vdev: vdev handle
  2299. * @nbuf: skb
  2300. *
  2301. * Return: true on success,
  2302. * false on failure
  2303. */
  2304. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2305. {
  2306. qdf_ether_header_t *eh;
  2307. /* Mcast to Ucast Conversion*/
  2308. if (qdf_likely(!vdev->mcast_enhancement_en))
  2309. return true;
  2310. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2311. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2312. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2313. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2314. qdf_nbuf_set_next(nbuf, NULL);
  2315. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2316. qdf_nbuf_len(nbuf));
  2317. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2318. QDF_STATUS_SUCCESS) {
  2319. return false;
  2320. }
  2321. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2322. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2323. QDF_STATUS_SUCCESS) {
  2324. return false;
  2325. }
  2326. }
  2327. }
  2328. return true;
  2329. }
  2330. #else
  2331. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2332. {
  2333. return true;
  2334. }
  2335. #endif
  2336. /**
  2337. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2338. * @nbuf: qdf_nbuf_t
  2339. * @vdev: struct dp_vdev *
  2340. *
  2341. * Allow packet for processing only if it is for peer client which is
  2342. * connected with same vap. Drop packet if client is connected to
  2343. * different vap.
  2344. *
  2345. * Return: QDF_STATUS
  2346. */
  2347. static inline QDF_STATUS
  2348. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2349. {
  2350. struct dp_ast_entry *dst_ast_entry = NULL;
  2351. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2352. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2353. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2354. return QDF_STATUS_SUCCESS;
  2355. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2356. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2357. eh->ether_dhost,
  2358. vdev->vdev_id);
  2359. /* If there is no ast entry, return failure */
  2360. if (qdf_unlikely(!dst_ast_entry)) {
  2361. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2362. return QDF_STATUS_E_FAILURE;
  2363. }
  2364. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2365. return QDF_STATUS_SUCCESS;
  2366. }
  2367. /**
  2368. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2369. * @soc: DP soc handle
  2370. * @vdev_id: id of DP vdev handle
  2371. * @nbuf: skb
  2372. * @tx_exc_metadata: Handle that holds exception path meta data
  2373. *
  2374. * Entry point for Core Tx layer (DP_TX) invoked from
  2375. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2376. *
  2377. * Return: NULL on success,
  2378. * nbuf when it fails to send
  2379. */
  2380. qdf_nbuf_t
  2381. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2382. qdf_nbuf_t nbuf,
  2383. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2384. {
  2385. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2386. qdf_ether_header_t *eh = NULL;
  2387. struct dp_tx_msdu_info_s msdu_info;
  2388. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2389. DP_MOD_ID_TX_EXCEPTION);
  2390. if (qdf_unlikely(!vdev))
  2391. goto fail;
  2392. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2393. if (!tx_exc_metadata)
  2394. goto fail;
  2395. msdu_info.tid = tx_exc_metadata->tid;
  2396. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2397. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2398. QDF_MAC_ADDR_REF(nbuf->data));
  2399. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2400. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2401. dp_tx_err("Invalid parameters in exception path");
  2402. goto fail;
  2403. }
  2404. /* Basic sanity checks for unsupported packets */
  2405. /* MESH mode */
  2406. if (qdf_unlikely(vdev->mesh_vdev)) {
  2407. dp_tx_err("Mesh mode is not supported in exception path");
  2408. goto fail;
  2409. }
  2410. /*
  2411. * Classify the frame and call corresponding
  2412. * "prepare" function which extracts the segment (TSO)
  2413. * and fragmentation information (for TSO , SG, ME, or Raw)
  2414. * into MSDU_INFO structure which is later used to fill
  2415. * SW and HW descriptors.
  2416. */
  2417. if (qdf_nbuf_is_tso(nbuf)) {
  2418. dp_verbose_debug("TSO frame %pK", vdev);
  2419. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2420. qdf_nbuf_len(nbuf));
  2421. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2422. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2423. qdf_nbuf_len(nbuf));
  2424. goto fail;
  2425. }
  2426. goto send_multiple;
  2427. }
  2428. /* SG */
  2429. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2430. struct dp_tx_seg_info_s seg_info = {0};
  2431. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2432. if (!nbuf)
  2433. goto fail;
  2434. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2435. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2436. qdf_nbuf_len(nbuf));
  2437. goto send_multiple;
  2438. }
  2439. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2440. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2441. qdf_nbuf_len(nbuf));
  2442. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2443. tx_exc_metadata->ppdu_cookie);
  2444. }
  2445. /*
  2446. * Get HW Queue to use for this frame.
  2447. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2448. * dedicated for data and 1 for command.
  2449. * "queue_id" maps to one hardware ring.
  2450. * With each ring, we also associate a unique Tx descriptor pool
  2451. * to minimize lock contention for these resources.
  2452. */
  2453. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2454. /*
  2455. * Check exception descriptors
  2456. */
  2457. if (dp_tx_exception_limit_check(vdev))
  2458. goto fail;
  2459. /* Single linear frame */
  2460. /*
  2461. * If nbuf is a simple linear frame, use send_single function to
  2462. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2463. * SRNG. There is no need to setup a MSDU extension descriptor.
  2464. */
  2465. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2466. tx_exc_metadata->peer_id, tx_exc_metadata);
  2467. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2468. return nbuf;
  2469. send_multiple:
  2470. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2471. fail:
  2472. if (vdev)
  2473. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2474. dp_verbose_debug("pkt send failed");
  2475. return nbuf;
  2476. }
  2477. /**
  2478. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2479. * in exception path in special case to avoid regular exception path chk.
  2480. * @soc: DP soc handle
  2481. * @vdev_id: id of DP vdev handle
  2482. * @nbuf: skb
  2483. * @tx_exc_metadata: Handle that holds exception path meta data
  2484. *
  2485. * Entry point for Core Tx layer (DP_TX) invoked from
  2486. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2487. *
  2488. * Return: NULL on success,
  2489. * nbuf when it fails to send
  2490. */
  2491. qdf_nbuf_t
  2492. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2493. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2494. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2495. {
  2496. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2497. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2498. DP_MOD_ID_TX_EXCEPTION);
  2499. if (qdf_unlikely(!vdev))
  2500. goto fail;
  2501. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2502. == QDF_STATUS_E_FAILURE)) {
  2503. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2504. goto fail;
  2505. }
  2506. /* Unref count as it will agin be taken inside dp_tx_exception */
  2507. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2508. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2509. fail:
  2510. if (vdev)
  2511. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2512. dp_verbose_debug("pkt send failed");
  2513. return nbuf;
  2514. }
  2515. /**
  2516. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2517. * @soc: DP soc handle
  2518. * @vdev_id: DP vdev handle
  2519. * @nbuf: skb
  2520. *
  2521. * Entry point for Core Tx layer (DP_TX) invoked from
  2522. * hard_start_xmit in OSIF/HDD
  2523. *
  2524. * Return: NULL on success,
  2525. * nbuf when it fails to send
  2526. */
  2527. #ifdef MESH_MODE_SUPPORT
  2528. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2529. qdf_nbuf_t nbuf)
  2530. {
  2531. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2532. struct meta_hdr_s *mhdr;
  2533. qdf_nbuf_t nbuf_mesh = NULL;
  2534. qdf_nbuf_t nbuf_clone = NULL;
  2535. struct dp_vdev *vdev;
  2536. uint8_t no_enc_frame = 0;
  2537. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2538. if (!nbuf_mesh) {
  2539. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2540. "qdf_nbuf_unshare failed");
  2541. return nbuf;
  2542. }
  2543. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2544. if (!vdev) {
  2545. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2546. "vdev is NULL for vdev_id %d", vdev_id);
  2547. return nbuf;
  2548. }
  2549. nbuf = nbuf_mesh;
  2550. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2551. if ((vdev->sec_type != cdp_sec_type_none) &&
  2552. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2553. no_enc_frame = 1;
  2554. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2555. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2556. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2557. !no_enc_frame) {
  2558. nbuf_clone = qdf_nbuf_clone(nbuf);
  2559. if (!nbuf_clone) {
  2560. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2561. "qdf_nbuf_clone failed");
  2562. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2563. return nbuf;
  2564. }
  2565. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2566. }
  2567. if (nbuf_clone) {
  2568. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2569. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2570. } else {
  2571. qdf_nbuf_free(nbuf_clone);
  2572. }
  2573. }
  2574. if (no_enc_frame)
  2575. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2576. else
  2577. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2578. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2579. if ((!nbuf) && no_enc_frame) {
  2580. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2581. }
  2582. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2583. return nbuf;
  2584. }
  2585. #else
  2586. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2587. qdf_nbuf_t nbuf)
  2588. {
  2589. return dp_tx_send(soc, vdev_id, nbuf);
  2590. }
  2591. #endif
  2592. /**
  2593. * dp_tx_nawds_handler() - NAWDS handler
  2594. *
  2595. * @soc: DP soc handle
  2596. * @vdev_id: id of DP vdev handle
  2597. * @msdu_info: msdu_info required to create HTT metadata
  2598. * @nbuf: skb
  2599. *
  2600. * This API transfers the multicast frames with the peer id
  2601. * on NAWDS enabled peer.
  2602. * Return: none
  2603. */
  2604. static inline
  2605. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2606. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2607. {
  2608. struct dp_peer *peer = NULL;
  2609. qdf_nbuf_t nbuf_clone = NULL;
  2610. uint16_t peer_id = DP_INVALID_PEER;
  2611. uint16_t sa_peer_id = DP_INVALID_PEER;
  2612. struct dp_ast_entry *ast_entry = NULL;
  2613. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2614. qdf_spin_lock_bh(&soc->ast_lock);
  2615. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2616. (soc,
  2617. (uint8_t *)(eh->ether_shost),
  2618. vdev->pdev->pdev_id);
  2619. if (ast_entry)
  2620. sa_peer_id = ast_entry->peer_id;
  2621. qdf_spin_unlock_bh(&soc->ast_lock);
  2622. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2623. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2624. if (!peer->bss_peer && peer->nawds_enabled) {
  2625. peer_id = peer->peer_id;
  2626. /* Multicast packets needs to be
  2627. * dropped in case of intra bss forwarding
  2628. */
  2629. if (sa_peer_id == peer->peer_id) {
  2630. dp_tx_debug("multicast packet");
  2631. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2632. continue;
  2633. }
  2634. nbuf_clone = qdf_nbuf_clone(nbuf);
  2635. if (!nbuf_clone) {
  2636. QDF_TRACE(QDF_MODULE_ID_DP,
  2637. QDF_TRACE_LEVEL_ERROR,
  2638. FL("nbuf clone failed"));
  2639. break;
  2640. }
  2641. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2642. msdu_info, peer_id,
  2643. NULL);
  2644. if (nbuf_clone) {
  2645. dp_tx_debug("pkt send failed");
  2646. qdf_nbuf_free(nbuf_clone);
  2647. } else {
  2648. if (peer_id != DP_INVALID_PEER)
  2649. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2650. 1, qdf_nbuf_len(nbuf));
  2651. }
  2652. }
  2653. }
  2654. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2655. }
  2656. /**
  2657. * dp_tx_send() - Transmit a frame on a given VAP
  2658. * @soc: DP soc handle
  2659. * @vdev_id: id of DP vdev handle
  2660. * @nbuf: skb
  2661. *
  2662. * Entry point for Core Tx layer (DP_TX) invoked from
  2663. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2664. * cases
  2665. *
  2666. * Return: NULL on success,
  2667. * nbuf when it fails to send
  2668. */
  2669. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2670. qdf_nbuf_t nbuf)
  2671. {
  2672. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2673. uint16_t peer_id = HTT_INVALID_PEER;
  2674. /*
  2675. * doing a memzero is causing additional function call overhead
  2676. * so doing static stack clearing
  2677. */
  2678. struct dp_tx_msdu_info_s msdu_info = {0};
  2679. struct dp_vdev *vdev = NULL;
  2680. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2681. return nbuf;
  2682. /*
  2683. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2684. * this in per packet path.
  2685. *
  2686. * As in this path vdev memory is already protected with netdev
  2687. * tx lock
  2688. */
  2689. vdev = soc->vdev_id_map[vdev_id];
  2690. if (qdf_unlikely(!vdev))
  2691. return nbuf;
  2692. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2693. QDF_MAC_ADDR_REF(nbuf->data));
  2694. /*
  2695. * Set Default Host TID value to invalid TID
  2696. * (TID override disabled)
  2697. */
  2698. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2699. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2700. if (qdf_unlikely(vdev->mesh_vdev)) {
  2701. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2702. &msdu_info);
  2703. if (!nbuf_mesh) {
  2704. dp_verbose_debug("Extracting mesh metadata failed");
  2705. return nbuf;
  2706. }
  2707. nbuf = nbuf_mesh;
  2708. }
  2709. /*
  2710. * Get HW Queue to use for this frame.
  2711. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2712. * dedicated for data and 1 for command.
  2713. * "queue_id" maps to one hardware ring.
  2714. * With each ring, we also associate a unique Tx descriptor pool
  2715. * to minimize lock contention for these resources.
  2716. */
  2717. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2718. /*
  2719. * TCL H/W supports 2 DSCP-TID mapping tables.
  2720. * Table 1 - Default DSCP-TID mapping table
  2721. * Table 2 - 1 DSCP-TID override table
  2722. *
  2723. * If we need a different DSCP-TID mapping for this vap,
  2724. * call tid_classify to extract DSCP/ToS from frame and
  2725. * map to a TID and store in msdu_info. This is later used
  2726. * to fill in TCL Input descriptor (per-packet TID override).
  2727. */
  2728. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2729. /*
  2730. * Classify the frame and call corresponding
  2731. * "prepare" function which extracts the segment (TSO)
  2732. * and fragmentation information (for TSO , SG, ME, or Raw)
  2733. * into MSDU_INFO structure which is later used to fill
  2734. * SW and HW descriptors.
  2735. */
  2736. if (qdf_nbuf_is_tso(nbuf)) {
  2737. dp_verbose_debug("TSO frame %pK", vdev);
  2738. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2739. qdf_nbuf_len(nbuf));
  2740. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2741. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2742. qdf_nbuf_len(nbuf));
  2743. return nbuf;
  2744. }
  2745. goto send_multiple;
  2746. }
  2747. /* SG */
  2748. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2749. struct dp_tx_seg_info_s seg_info = {0};
  2750. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2751. if (!nbuf)
  2752. return NULL;
  2753. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2754. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2755. qdf_nbuf_len(nbuf));
  2756. goto send_multiple;
  2757. }
  2758. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2759. return NULL;
  2760. /* RAW */
  2761. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2762. struct dp_tx_seg_info_s seg_info = {0};
  2763. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2764. if (!nbuf)
  2765. return NULL;
  2766. dp_verbose_debug("Raw frame %pK", vdev);
  2767. goto send_multiple;
  2768. }
  2769. if (qdf_unlikely(vdev->nawds_enabled)) {
  2770. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2771. qdf_nbuf_data(nbuf);
  2772. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2773. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2774. peer_id = DP_INVALID_PEER;
  2775. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2776. 1, qdf_nbuf_len(nbuf));
  2777. }
  2778. /* Single linear frame */
  2779. /*
  2780. * If nbuf is a simple linear frame, use send_single function to
  2781. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2782. * SRNG. There is no need to setup a MSDU extension descriptor.
  2783. */
  2784. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2785. return nbuf;
  2786. send_multiple:
  2787. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2788. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2789. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2790. return nbuf;
  2791. }
  2792. /**
  2793. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2794. * case to vaoid check in perpkt path.
  2795. * @soc: DP soc handle
  2796. * @vdev_id: id of DP vdev handle
  2797. * @nbuf: skb
  2798. *
  2799. * Entry point for Core Tx layer (DP_TX) invoked from
  2800. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2801. * with special condition to avoid per pkt check in dp_tx_send
  2802. *
  2803. * Return: NULL on success,
  2804. * nbuf when it fails to send
  2805. */
  2806. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2807. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2808. {
  2809. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2810. struct dp_vdev *vdev = NULL;
  2811. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2812. return nbuf;
  2813. /*
  2814. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2815. * this in per packet path.
  2816. *
  2817. * As in this path vdev memory is already protected with netdev
  2818. * tx lock
  2819. */
  2820. vdev = soc->vdev_id_map[vdev_id];
  2821. if (qdf_unlikely(!vdev))
  2822. return nbuf;
  2823. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2824. == QDF_STATUS_E_FAILURE)) {
  2825. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2826. return nbuf;
  2827. }
  2828. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2829. }
  2830. /**
  2831. * dp_tx_reinject_handler() - Tx Reinject Handler
  2832. * @soc: datapath soc handle
  2833. * @vdev: datapath vdev handle
  2834. * @tx_desc: software descriptor head pointer
  2835. * @status : Tx completion status from HTT descriptor
  2836. *
  2837. * This function reinjects frames back to Target.
  2838. * Todo - Host queue needs to be added
  2839. *
  2840. * Return: none
  2841. */
  2842. static
  2843. void dp_tx_reinject_handler(struct dp_soc *soc,
  2844. struct dp_vdev *vdev,
  2845. struct dp_tx_desc_s *tx_desc,
  2846. uint8_t *status)
  2847. {
  2848. struct dp_peer *peer = NULL;
  2849. uint32_t peer_id = HTT_INVALID_PEER;
  2850. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2851. qdf_nbuf_t nbuf_copy = NULL;
  2852. struct dp_tx_msdu_info_s msdu_info;
  2853. #ifdef WDS_VENDOR_EXTENSION
  2854. int is_mcast = 0, is_ucast = 0;
  2855. int num_peers_3addr = 0;
  2856. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2857. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2858. #endif
  2859. qdf_assert(vdev);
  2860. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2861. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2862. dp_tx_debug("Tx reinject path");
  2863. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2864. qdf_nbuf_len(tx_desc->nbuf));
  2865. #ifdef WDS_VENDOR_EXTENSION
  2866. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2867. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2868. } else {
  2869. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2870. }
  2871. is_ucast = !is_mcast;
  2872. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2873. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2874. if (peer->bss_peer)
  2875. continue;
  2876. /* Detect wds peers that use 3-addr framing for mcast.
  2877. * if there are any, the bss_peer is used to send the
  2878. * the mcast frame using 3-addr format. all wds enabled
  2879. * peers that use 4-addr framing for mcast frames will
  2880. * be duplicated and sent as 4-addr frames below.
  2881. */
  2882. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2883. num_peers_3addr = 1;
  2884. break;
  2885. }
  2886. }
  2887. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2888. #endif
  2889. if (qdf_unlikely(vdev->mesh_vdev)) {
  2890. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2891. } else {
  2892. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2893. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2894. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2895. #ifdef WDS_VENDOR_EXTENSION
  2896. /*
  2897. * . if 3-addr STA, then send on BSS Peer
  2898. * . if Peer WDS enabled and accept 4-addr mcast,
  2899. * send mcast on that peer only
  2900. * . if Peer WDS enabled and accept 4-addr ucast,
  2901. * send ucast on that peer only
  2902. */
  2903. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2904. (peer->wds_enabled &&
  2905. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2906. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2907. #else
  2908. ((peer->bss_peer &&
  2909. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2910. #endif
  2911. peer_id = DP_INVALID_PEER;
  2912. nbuf_copy = qdf_nbuf_copy(nbuf);
  2913. if (!nbuf_copy) {
  2914. dp_tx_debug("nbuf copy failed");
  2915. break;
  2916. }
  2917. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2918. nbuf_copy,
  2919. &msdu_info,
  2920. peer_id,
  2921. NULL);
  2922. if (nbuf_copy) {
  2923. dp_tx_debug("pkt send failed");
  2924. qdf_nbuf_free(nbuf_copy);
  2925. }
  2926. }
  2927. }
  2928. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2929. }
  2930. qdf_nbuf_free(nbuf);
  2931. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2932. }
  2933. /**
  2934. * dp_tx_inspect_handler() - Tx Inspect Handler
  2935. * @soc: datapath soc handle
  2936. * @vdev: datapath vdev handle
  2937. * @tx_desc: software descriptor head pointer
  2938. * @status : Tx completion status from HTT descriptor
  2939. *
  2940. * Handles Tx frames sent back to Host for inspection
  2941. * (ProxyARP)
  2942. *
  2943. * Return: none
  2944. */
  2945. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2946. struct dp_vdev *vdev,
  2947. struct dp_tx_desc_s *tx_desc,
  2948. uint8_t *status)
  2949. {
  2950. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2951. "%s Tx inspect path",
  2952. __func__);
  2953. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2954. qdf_nbuf_len(tx_desc->nbuf));
  2955. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2956. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2957. }
  2958. #ifdef MESH_MODE_SUPPORT
  2959. /**
  2960. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2961. * in mesh meta header
  2962. * @tx_desc: software descriptor head pointer
  2963. * @ts: pointer to tx completion stats
  2964. * Return: none
  2965. */
  2966. static
  2967. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2968. struct hal_tx_completion_status *ts)
  2969. {
  2970. struct meta_hdr_s *mhdr;
  2971. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2972. if (!tx_desc->msdu_ext_desc) {
  2973. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2974. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2975. "netbuf %pK offset %d",
  2976. netbuf, tx_desc->pkt_offset);
  2977. return;
  2978. }
  2979. }
  2980. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2981. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2982. "netbuf %pK offset %zu", netbuf,
  2983. sizeof(struct meta_hdr_s));
  2984. return;
  2985. }
  2986. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2987. mhdr->rssi = ts->ack_frame_rssi;
  2988. mhdr->band = tx_desc->pdev->operating_channel.band;
  2989. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2990. }
  2991. #else
  2992. static
  2993. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2994. struct hal_tx_completion_status *ts)
  2995. {
  2996. }
  2997. #endif
  2998. #ifdef QCA_PEER_EXT_STATS
  2999. /*
  3000. * dp_tx_compute_tid_delay() - Compute per TID delay
  3001. * @stats: Per TID delay stats
  3002. * @tx_desc: Software Tx descriptor
  3003. *
  3004. * Compute the software enqueue and hw enqueue delays and
  3005. * update the respective histograms
  3006. *
  3007. * Return: void
  3008. */
  3009. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3010. struct dp_tx_desc_s *tx_desc)
  3011. {
  3012. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3013. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3014. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3015. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3016. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3017. timestamp_hw_enqueue = tx_desc->timestamp;
  3018. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3019. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3020. timestamp_hw_enqueue);
  3021. /*
  3022. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3023. */
  3024. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3025. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3026. }
  3027. /*
  3028. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3029. * @peer: DP peer context
  3030. * @tx_desc: Tx software descriptor
  3031. * @tid: Transmission ID
  3032. * @ring_id: Rx CPU context ID/CPU_ID
  3033. *
  3034. * Update the peer extended stats. These are enhanced other
  3035. * delay stats per msdu level.
  3036. *
  3037. * Return: void
  3038. */
  3039. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3040. struct dp_tx_desc_s *tx_desc,
  3041. uint8_t tid, uint8_t ring_id)
  3042. {
  3043. struct dp_pdev *pdev = peer->vdev->pdev;
  3044. struct dp_soc *soc = NULL;
  3045. struct cdp_peer_ext_stats *pext_stats = NULL;
  3046. soc = pdev->soc;
  3047. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3048. return;
  3049. pext_stats = peer->pext_stats;
  3050. qdf_assert(pext_stats);
  3051. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3052. /*
  3053. * For non-TID packets use the TID 9
  3054. */
  3055. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3056. tid = CDP_MAX_DATA_TIDS - 1;
  3057. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3058. tx_desc);
  3059. }
  3060. #else
  3061. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3062. struct dp_tx_desc_s *tx_desc,
  3063. uint8_t tid, uint8_t ring_id)
  3064. {
  3065. }
  3066. #endif
  3067. /**
  3068. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3069. * to pass in correct fields
  3070. *
  3071. * @vdev: pdev handle
  3072. * @tx_desc: tx descriptor
  3073. * @tid: tid value
  3074. * @ring_id: TCL or WBM ring number for transmit path
  3075. * Return: none
  3076. */
  3077. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3078. struct dp_tx_desc_s *tx_desc,
  3079. uint8_t tid, uint8_t ring_id)
  3080. {
  3081. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3082. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3083. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3084. return;
  3085. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3086. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3087. timestamp_hw_enqueue = tx_desc->timestamp;
  3088. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3089. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3090. timestamp_hw_enqueue);
  3091. interframe_delay = (uint32_t)(timestamp_ingress -
  3092. vdev->prev_tx_enq_tstamp);
  3093. /*
  3094. * Delay in software enqueue
  3095. */
  3096. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3097. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3098. /*
  3099. * Delay between packet enqueued to HW and Tx completion
  3100. */
  3101. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3102. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3103. /*
  3104. * Update interframe delay stats calculated at hardstart receive point.
  3105. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3106. * interframe delay will not be calculate correctly for 1st frame.
  3107. * On the other side, this will help in avoiding extra per packet check
  3108. * of !vdev->prev_tx_enq_tstamp.
  3109. */
  3110. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3111. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3112. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3113. }
  3114. #ifdef DISABLE_DP_STATS
  3115. static
  3116. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3117. {
  3118. }
  3119. #else
  3120. static
  3121. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3122. {
  3123. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3124. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3125. if (subtype != QDF_PROTO_INVALID)
  3126. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3127. }
  3128. #endif
  3129. /**
  3130. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3131. * per wbm ring
  3132. *
  3133. * @tx_desc: software descriptor head pointer
  3134. * @ts: Tx completion status
  3135. * @peer: peer handle
  3136. * @ring_id: ring number
  3137. *
  3138. * Return: None
  3139. */
  3140. static inline void
  3141. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3142. struct hal_tx_completion_status *ts,
  3143. struct dp_peer *peer, uint8_t ring_id)
  3144. {
  3145. struct dp_pdev *pdev = peer->vdev->pdev;
  3146. struct dp_soc *soc = NULL;
  3147. uint8_t mcs, pkt_type;
  3148. uint8_t tid = ts->tid;
  3149. uint32_t length;
  3150. struct cdp_tid_tx_stats *tid_stats;
  3151. if (!pdev)
  3152. return;
  3153. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3154. tid = CDP_MAX_DATA_TIDS - 1;
  3155. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3156. soc = pdev->soc;
  3157. mcs = ts->mcs;
  3158. pkt_type = ts->pkt_type;
  3159. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3160. dp_err("Release source is not from TQM");
  3161. return;
  3162. }
  3163. length = qdf_nbuf_len(tx_desc->nbuf);
  3164. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3165. if (qdf_unlikely(pdev->delay_stats_flag))
  3166. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3167. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3168. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3169. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3170. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3171. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3172. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3173. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3174. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3175. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3176. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3177. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3178. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3179. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3180. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3181. /*
  3182. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3183. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3184. * are no completions for failed cases. Hence updating tx_failed from
  3185. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3186. * then this has to be removed
  3187. */
  3188. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3189. peer->stats.tx.dropped.fw_rem_notx +
  3190. peer->stats.tx.dropped.fw_rem_tx +
  3191. peer->stats.tx.dropped.age_out +
  3192. peer->stats.tx.dropped.fw_reason1 +
  3193. peer->stats.tx.dropped.fw_reason2 +
  3194. peer->stats.tx.dropped.fw_reason3;
  3195. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3196. tid_stats->tqm_status_cnt[ts->status]++;
  3197. }
  3198. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3199. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3200. return;
  3201. }
  3202. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3203. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3204. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3205. /*
  3206. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3207. * Return from here if HTT PPDU events are enabled.
  3208. */
  3209. if (!(soc->process_tx_status))
  3210. return;
  3211. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3212. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3213. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3214. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3215. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3216. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3217. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3218. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3219. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3220. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3221. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3222. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3223. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3224. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3225. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3226. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3227. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3228. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3229. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3230. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3231. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3232. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3233. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3234. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3235. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3236. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3237. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3238. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3239. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3240. &peer->stats, ts->peer_id,
  3241. UPDATE_PEER_STATS, pdev->pdev_id);
  3242. #endif
  3243. }
  3244. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3245. /**
  3246. * dp_tx_flow_pool_lock() - take flow pool lock
  3247. * @soc: core txrx main context
  3248. * @tx_desc: tx desc
  3249. *
  3250. * Return: None
  3251. */
  3252. static inline
  3253. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3254. struct dp_tx_desc_s *tx_desc)
  3255. {
  3256. struct dp_tx_desc_pool_s *pool;
  3257. uint8_t desc_pool_id;
  3258. desc_pool_id = tx_desc->pool_id;
  3259. pool = &soc->tx_desc[desc_pool_id];
  3260. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3261. }
  3262. /**
  3263. * dp_tx_flow_pool_unlock() - release flow pool lock
  3264. * @soc: core txrx main context
  3265. * @tx_desc: tx desc
  3266. *
  3267. * Return: None
  3268. */
  3269. static inline
  3270. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3271. struct dp_tx_desc_s *tx_desc)
  3272. {
  3273. struct dp_tx_desc_pool_s *pool;
  3274. uint8_t desc_pool_id;
  3275. desc_pool_id = tx_desc->pool_id;
  3276. pool = &soc->tx_desc[desc_pool_id];
  3277. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3278. }
  3279. #else
  3280. static inline
  3281. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3282. {
  3283. }
  3284. static inline
  3285. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3286. {
  3287. }
  3288. #endif
  3289. /**
  3290. * dp_tx_notify_completion() - Notify tx completion for this desc
  3291. * @soc: core txrx main context
  3292. * @vdev: datapath vdev handle
  3293. * @tx_desc: tx desc
  3294. * @netbuf: buffer
  3295. * @status: tx status
  3296. *
  3297. * Return: none
  3298. */
  3299. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3300. struct dp_vdev *vdev,
  3301. struct dp_tx_desc_s *tx_desc,
  3302. qdf_nbuf_t netbuf,
  3303. uint8_t status)
  3304. {
  3305. void *osif_dev;
  3306. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3307. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3308. qdf_assert(tx_desc);
  3309. dp_tx_flow_pool_lock(soc, tx_desc);
  3310. if (!vdev ||
  3311. !vdev->osif_vdev) {
  3312. dp_tx_flow_pool_unlock(soc, tx_desc);
  3313. return;
  3314. }
  3315. osif_dev = vdev->osif_vdev;
  3316. tx_compl_cbk = vdev->tx_comp;
  3317. dp_tx_flow_pool_unlock(soc, tx_desc);
  3318. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3319. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3320. if (tx_compl_cbk)
  3321. tx_compl_cbk(netbuf, osif_dev, flag);
  3322. }
  3323. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3324. * @pdev: pdev handle
  3325. * @tid: tid value
  3326. * @txdesc_ts: timestamp from txdesc
  3327. * @ppdu_id: ppdu id
  3328. *
  3329. * Return: none
  3330. */
  3331. #ifdef FEATURE_PERPKT_INFO
  3332. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3333. struct dp_peer *peer,
  3334. uint8_t tid,
  3335. uint64_t txdesc_ts,
  3336. uint32_t ppdu_id)
  3337. {
  3338. uint64_t delta_ms;
  3339. struct cdp_tx_sojourn_stats *sojourn_stats;
  3340. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3341. return;
  3342. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3343. tid >= CDP_DATA_TID_MAX))
  3344. return;
  3345. if (qdf_unlikely(!pdev->sojourn_buf))
  3346. return;
  3347. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3348. qdf_nbuf_data(pdev->sojourn_buf);
  3349. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3350. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3351. txdesc_ts;
  3352. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3353. delta_ms);
  3354. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3355. sojourn_stats->num_msdus[tid] = 1;
  3356. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3357. peer->avg_sojourn_msdu[tid].internal;
  3358. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3359. pdev->sojourn_buf, HTT_INVALID_PEER,
  3360. WDI_NO_VAL, pdev->pdev_id);
  3361. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3362. sojourn_stats->num_msdus[tid] = 0;
  3363. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3364. }
  3365. #else
  3366. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3367. struct dp_peer *peer,
  3368. uint8_t tid,
  3369. uint64_t txdesc_ts,
  3370. uint32_t ppdu_id)
  3371. {
  3372. }
  3373. #endif
  3374. #ifdef WLAN_FEATURE_PKT_CAPTURE_LITHIUM
  3375. /**
  3376. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3377. * @soc: dp_soc handle
  3378. * @desc: Tx Descriptor
  3379. * @ts: HAL Tx completion descriptor contents
  3380. *
  3381. * This function is used to send tx completion to packet capture
  3382. */
  3383. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3384. struct dp_tx_desc_s *desc,
  3385. struct hal_tx_completion_status *ts)
  3386. {
  3387. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3388. desc, ts->peer_id,
  3389. WDI_NO_VAL, desc->pdev->pdev_id);
  3390. }
  3391. #endif
  3392. /**
  3393. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3394. * @soc: DP Soc handle
  3395. * @tx_desc: software Tx descriptor
  3396. * @ts : Tx completion status from HAL/HTT descriptor
  3397. *
  3398. * Return: none
  3399. */
  3400. static inline void
  3401. dp_tx_comp_process_desc(struct dp_soc *soc,
  3402. struct dp_tx_desc_s *desc,
  3403. struct hal_tx_completion_status *ts,
  3404. struct dp_peer *peer)
  3405. {
  3406. uint64_t time_latency = 0;
  3407. /*
  3408. * m_copy/tx_capture modes are not supported for
  3409. * scatter gather packets
  3410. */
  3411. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3412. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3413. desc->timestamp);
  3414. }
  3415. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3416. if (!(desc->msdu_ext_desc)) {
  3417. if (QDF_STATUS_SUCCESS ==
  3418. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3419. return;
  3420. }
  3421. if (QDF_STATUS_SUCCESS ==
  3422. dp_get_completion_indication_for_stack(soc,
  3423. desc->pdev,
  3424. peer, ts,
  3425. desc->nbuf,
  3426. time_latency)) {
  3427. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3428. QDF_DMA_TO_DEVICE,
  3429. desc->nbuf->len);
  3430. dp_send_completion_to_stack(soc,
  3431. desc->pdev,
  3432. ts->peer_id,
  3433. ts->ppdu_id,
  3434. desc->nbuf);
  3435. return;
  3436. }
  3437. }
  3438. dp_tx_comp_free_buf(soc, desc);
  3439. }
  3440. #ifdef DISABLE_DP_STATS
  3441. /**
  3442. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3443. * @soc: core txrx main context
  3444. * @tx_desc: tx desc
  3445. * @status: tx status
  3446. *
  3447. * Return: none
  3448. */
  3449. static inline
  3450. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3451. struct dp_vdev *vdev,
  3452. struct dp_tx_desc_s *tx_desc,
  3453. uint8_t status)
  3454. {
  3455. }
  3456. #else
  3457. static inline
  3458. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3459. struct dp_vdev *vdev,
  3460. struct dp_tx_desc_s *tx_desc,
  3461. uint8_t status)
  3462. {
  3463. void *osif_dev;
  3464. ol_txrx_stats_rx_fp stats_cbk;
  3465. uint8_t pkt_type;
  3466. qdf_assert(tx_desc);
  3467. if (!vdev ||
  3468. !vdev->osif_vdev ||
  3469. !vdev->stats_cb)
  3470. return;
  3471. osif_dev = vdev->osif_vdev;
  3472. stats_cbk = vdev->stats_cb;
  3473. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3474. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3475. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3476. &pkt_type);
  3477. }
  3478. #endif
  3479. /**
  3480. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3481. * @soc: DP soc handle
  3482. * @tx_desc: software descriptor head pointer
  3483. * @ts: Tx completion status
  3484. * @peer: peer handle
  3485. * @ring_id: ring number
  3486. *
  3487. * Return: none
  3488. */
  3489. static inline
  3490. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3491. struct dp_tx_desc_s *tx_desc,
  3492. struct hal_tx_completion_status *ts,
  3493. struct dp_peer *peer, uint8_t ring_id)
  3494. {
  3495. uint32_t length;
  3496. qdf_ether_header_t *eh;
  3497. struct dp_vdev *vdev = NULL;
  3498. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3499. enum qdf_dp_tx_rx_status dp_status;
  3500. if (!nbuf) {
  3501. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3502. goto out;
  3503. }
  3504. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3505. length = qdf_nbuf_len(nbuf);
  3506. dp_status = dp_tx_hw_to_qdf(ts->status);
  3507. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3508. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3509. QDF_TRACE_DEFAULT_PDEV_ID,
  3510. qdf_nbuf_data_addr(nbuf),
  3511. sizeof(qdf_nbuf_data(nbuf)),
  3512. tx_desc->id, ts->status, dp_status));
  3513. dp_tx_comp_debug("-------------------- \n"
  3514. "Tx Completion Stats: \n"
  3515. "-------------------- \n"
  3516. "ack_frame_rssi = %d \n"
  3517. "first_msdu = %d \n"
  3518. "last_msdu = %d \n"
  3519. "msdu_part_of_amsdu = %d \n"
  3520. "rate_stats valid = %d \n"
  3521. "bw = %d \n"
  3522. "pkt_type = %d \n"
  3523. "stbc = %d \n"
  3524. "ldpc = %d \n"
  3525. "sgi = %d \n"
  3526. "mcs = %d \n"
  3527. "ofdma = %d \n"
  3528. "tones_in_ru = %d \n"
  3529. "tsf = %d \n"
  3530. "ppdu_id = %d \n"
  3531. "transmit_cnt = %d \n"
  3532. "tid = %d \n"
  3533. "peer_id = %d\n",
  3534. ts->ack_frame_rssi, ts->first_msdu,
  3535. ts->last_msdu, ts->msdu_part_of_amsdu,
  3536. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3537. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3538. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3539. ts->transmit_cnt, ts->tid, ts->peer_id);
  3540. /* Update SoC level stats */
  3541. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3542. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3543. if (!peer) {
  3544. dp_info_rl("peer is null or deletion in progress");
  3545. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3546. goto out;
  3547. }
  3548. vdev = peer->vdev;
  3549. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3550. /* Update per-packet stats for mesh mode */
  3551. if (qdf_unlikely(vdev->mesh_vdev) &&
  3552. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3553. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3554. /* Update peer level stats */
  3555. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3556. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3557. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3558. if ((peer->vdev->tx_encap_type ==
  3559. htt_cmn_pkt_type_ethernet) &&
  3560. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3561. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3562. }
  3563. }
  3564. } else {
  3565. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3566. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3567. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3568. if (qdf_unlikely(peer->in_twt)) {
  3569. DP_STATS_INC_PKT(peer,
  3570. tx.tx_success_twt,
  3571. 1, length);
  3572. }
  3573. }
  3574. }
  3575. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3576. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3577. #ifdef QCA_SUPPORT_RDK_STATS
  3578. if (soc->rdkstats_enabled)
  3579. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3580. tx_desc->timestamp,
  3581. ts->ppdu_id);
  3582. #endif
  3583. out:
  3584. return;
  3585. }
  3586. /**
  3587. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3588. * @soc: core txrx main context
  3589. * @comp_head: software descriptor head pointer
  3590. * @ring_id: ring number
  3591. *
  3592. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3593. * and release the software descriptors after processing is complete
  3594. *
  3595. * Return: none
  3596. */
  3597. static void
  3598. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3599. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3600. {
  3601. struct dp_tx_desc_s *desc;
  3602. struct dp_tx_desc_s *next;
  3603. struct hal_tx_completion_status ts;
  3604. struct dp_peer *peer = NULL;
  3605. uint16_t peer_id = DP_INVALID_PEER;
  3606. qdf_nbuf_t netbuf;
  3607. desc = comp_head;
  3608. while (desc) {
  3609. if (peer_id != desc->peer_id) {
  3610. if (peer)
  3611. dp_peer_unref_delete(peer,
  3612. DP_MOD_ID_TX_COMP);
  3613. peer_id = desc->peer_id;
  3614. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3615. DP_MOD_ID_TX_COMP);
  3616. }
  3617. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3618. struct dp_pdev *pdev = desc->pdev;
  3619. if (qdf_likely(peer)) {
  3620. /*
  3621. * Increment peer statistics
  3622. * Minimal statistics update done here
  3623. */
  3624. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3625. desc->length);
  3626. if (desc->tx_status !=
  3627. HAL_TX_TQM_RR_FRAME_ACKED)
  3628. DP_STATS_INC(peer, tx.tx_failed, 1);
  3629. }
  3630. qdf_assert(pdev);
  3631. dp_tx_outstanding_dec(pdev);
  3632. /*
  3633. * Calling a QDF WRAPPER here is creating signifcant
  3634. * performance impact so avoided the wrapper call here
  3635. */
  3636. next = desc->next;
  3637. qdf_mem_unmap_nbytes_single(soc->osdev,
  3638. desc->dma_addr,
  3639. QDF_DMA_TO_DEVICE,
  3640. desc->length);
  3641. qdf_nbuf_free(desc->nbuf);
  3642. dp_tx_desc_free(soc, desc, desc->pool_id);
  3643. desc = next;
  3644. continue;
  3645. }
  3646. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3647. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3648. netbuf = desc->nbuf;
  3649. /* check tx complete notification */
  3650. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3651. dp_tx_notify_completion(soc, peer->vdev, desc,
  3652. netbuf, ts.status);
  3653. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3654. next = desc->next;
  3655. dp_tx_desc_release(desc, desc->pool_id);
  3656. desc = next;
  3657. }
  3658. if (peer)
  3659. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3660. }
  3661. /**
  3662. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3663. * @soc: Handle to DP soc structure
  3664. * @tx_desc: software descriptor head pointer
  3665. * @status : Tx completion status from HTT descriptor
  3666. * @ring_id: ring number
  3667. *
  3668. * This function will process HTT Tx indication messages from Target
  3669. *
  3670. * Return: none
  3671. */
  3672. static
  3673. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3674. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3675. uint8_t ring_id)
  3676. {
  3677. uint8_t tx_status;
  3678. struct dp_pdev *pdev;
  3679. struct dp_vdev *vdev;
  3680. struct hal_tx_completion_status ts = {0};
  3681. uint32_t *htt_desc = (uint32_t *)status;
  3682. struct dp_peer *peer;
  3683. struct cdp_tid_tx_stats *tid_stats = NULL;
  3684. struct htt_soc *htt_handle;
  3685. uint8_t vdev_id;
  3686. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3687. htt_handle = (struct htt_soc *)soc->htt_handle;
  3688. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3689. /*
  3690. * There can be scenario where WBM consuming descriptor enqueued
  3691. * from TQM2WBM first and TQM completion can happen before MEC
  3692. * notification comes from FW2WBM. Avoid access any field of tx
  3693. * descriptor in case of MEC notify.
  3694. */
  3695. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3696. /*
  3697. * Get vdev id from HTT status word in case of MEC
  3698. * notification
  3699. */
  3700. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3701. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3702. return;
  3703. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3704. DP_MOD_ID_HTT_COMP);
  3705. if (!vdev)
  3706. return;
  3707. dp_tx_mec_handler(vdev, status);
  3708. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3709. return;
  3710. }
  3711. /*
  3712. * If the descriptor is already freed in vdev_detach,
  3713. * continue to next descriptor
  3714. */
  3715. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3716. QDF_TRACE(QDF_MODULE_ID_DP,
  3717. QDF_TRACE_LEVEL_INFO,
  3718. "Descriptor freed in vdev_detach %d",
  3719. tx_desc->id);
  3720. return;
  3721. }
  3722. pdev = tx_desc->pdev;
  3723. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3724. QDF_TRACE(QDF_MODULE_ID_DP,
  3725. QDF_TRACE_LEVEL_INFO,
  3726. "pdev in down state %d",
  3727. tx_desc->id);
  3728. dp_tx_comp_free_buf(soc, tx_desc);
  3729. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3730. return;
  3731. }
  3732. qdf_assert(tx_desc->pdev);
  3733. vdev_id = tx_desc->vdev_id;
  3734. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3735. DP_MOD_ID_HTT_COMP);
  3736. if (!vdev)
  3737. return;
  3738. switch (tx_status) {
  3739. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3740. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3741. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3742. {
  3743. uint8_t tid;
  3744. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3745. ts.peer_id =
  3746. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3747. htt_desc[2]);
  3748. ts.tid =
  3749. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3750. htt_desc[2]);
  3751. } else {
  3752. ts.peer_id = HTT_INVALID_PEER;
  3753. ts.tid = HTT_INVALID_TID;
  3754. }
  3755. ts.ppdu_id =
  3756. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3757. htt_desc[1]);
  3758. ts.ack_frame_rssi =
  3759. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3760. htt_desc[1]);
  3761. ts.tsf = htt_desc[3];
  3762. ts.first_msdu = 1;
  3763. ts.last_msdu = 1;
  3764. tid = ts.tid;
  3765. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3766. tid = CDP_MAX_DATA_TIDS - 1;
  3767. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3768. if (qdf_unlikely(pdev->delay_stats_flag))
  3769. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3770. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3771. tid_stats->htt_status_cnt[tx_status]++;
  3772. }
  3773. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3774. DP_MOD_ID_HTT_COMP);
  3775. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3776. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3777. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3778. if (qdf_likely(peer))
  3779. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3780. break;
  3781. }
  3782. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3783. {
  3784. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3785. break;
  3786. }
  3787. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3788. {
  3789. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3790. break;
  3791. }
  3792. default:
  3793. dp_tx_comp_debug("Invalid HTT tx_status %d\n",
  3794. tx_status);
  3795. break;
  3796. }
  3797. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3798. }
  3799. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3800. static inline
  3801. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3802. {
  3803. bool limit_hit = false;
  3804. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3805. limit_hit =
  3806. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3807. if (limit_hit)
  3808. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3809. return limit_hit;
  3810. }
  3811. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3812. {
  3813. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3814. }
  3815. #else
  3816. static inline
  3817. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3818. {
  3819. return false;
  3820. }
  3821. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3822. {
  3823. return false;
  3824. }
  3825. #endif
  3826. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3827. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3828. uint32_t quota)
  3829. {
  3830. void *tx_comp_hal_desc;
  3831. uint8_t buffer_src;
  3832. uint8_t pool_id;
  3833. uint32_t tx_desc_id;
  3834. struct dp_tx_desc_s *tx_desc = NULL;
  3835. struct dp_tx_desc_s *head_desc = NULL;
  3836. struct dp_tx_desc_s *tail_desc = NULL;
  3837. uint32_t num_processed = 0;
  3838. uint32_t count;
  3839. uint32_t num_avail_for_reap = 0;
  3840. bool force_break = false;
  3841. DP_HIST_INIT();
  3842. more_data:
  3843. /* Re-initialize local variables to be re-used */
  3844. head_desc = NULL;
  3845. tail_desc = NULL;
  3846. count = 0;
  3847. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3848. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3849. return 0;
  3850. }
  3851. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3852. if (num_avail_for_reap >= quota)
  3853. num_avail_for_reap = quota;
  3854. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3855. /* Find head descriptor from completion ring */
  3856. while (qdf_likely(num_avail_for_reap)) {
  3857. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3858. if (qdf_unlikely(!tx_comp_hal_desc))
  3859. break;
  3860. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3861. /* If this buffer was not released by TQM or FW, then it is not
  3862. * Tx completion indication, assert */
  3863. if (qdf_unlikely(buffer_src !=
  3864. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3865. (qdf_unlikely(buffer_src !=
  3866. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3867. uint8_t wbm_internal_error;
  3868. dp_err_rl(
  3869. "Tx comp release_src != TQM | FW but from %d",
  3870. buffer_src);
  3871. hal_dump_comp_desc(tx_comp_hal_desc);
  3872. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3873. /* When WBM sees NULL buffer_addr_info in any of
  3874. * ingress rings it sends an error indication,
  3875. * with wbm_internal_error=1, to a specific ring.
  3876. * The WBM2SW ring used to indicate these errors is
  3877. * fixed in HW, and that ring is being used as Tx
  3878. * completion ring. These errors are not related to
  3879. * Tx completions, and should just be ignored
  3880. */
  3881. wbm_internal_error = hal_get_wbm_internal_error(
  3882. soc->hal_soc,
  3883. tx_comp_hal_desc);
  3884. if (wbm_internal_error) {
  3885. dp_err_rl("Tx comp wbm_internal_error!!");
  3886. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3887. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3888. buffer_src)
  3889. dp_handle_wbm_internal_error(
  3890. soc,
  3891. tx_comp_hal_desc,
  3892. hal_tx_comp_get_buffer_type(
  3893. tx_comp_hal_desc));
  3894. } else {
  3895. dp_err_rl("Tx comp wbm_internal_error false");
  3896. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3897. }
  3898. continue;
  3899. }
  3900. /* Get descriptor id */
  3901. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3902. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3903. DP_TX_DESC_ID_POOL_OS;
  3904. /* Find Tx descriptor */
  3905. tx_desc = dp_tx_desc_find(soc, pool_id,
  3906. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3907. DP_TX_DESC_ID_PAGE_OS,
  3908. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3909. DP_TX_DESC_ID_OFFSET_OS);
  3910. /*
  3911. * If the release source is FW, process the HTT status
  3912. */
  3913. if (qdf_unlikely(buffer_src ==
  3914. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3915. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3916. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3917. htt_tx_status);
  3918. dp_tx_process_htt_completion(soc, tx_desc,
  3919. htt_tx_status, ring_id);
  3920. } else {
  3921. tx_desc->peer_id =
  3922. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3923. tx_desc->tx_status =
  3924. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3925. /*
  3926. * If the fast completion mode is enabled extended
  3927. * metadata from descriptor is not copied
  3928. */
  3929. if (qdf_likely(tx_desc->flags &
  3930. DP_TX_DESC_FLAG_SIMPLE))
  3931. goto add_to_pool;
  3932. /*
  3933. * If the descriptor is already freed in vdev_detach,
  3934. * continue to next descriptor
  3935. */
  3936. if (qdf_unlikely
  3937. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  3938. !tx_desc->flags)) {
  3939. dp_tx_comp_info("Descriptor freed in vdev_detach %d",
  3940. tx_desc_id);
  3941. continue;
  3942. }
  3943. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3944. dp_tx_comp_info("pdev in down state %d",
  3945. tx_desc_id);
  3946. dp_tx_comp_free_buf(soc, tx_desc);
  3947. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3948. goto next_desc;
  3949. }
  3950. /* Pool id is not matching. Error */
  3951. if (tx_desc->pool_id != pool_id) {
  3952. dp_tx_comp_alert("Tx Comp pool id %d not matched %d",
  3953. pool_id, tx_desc->pool_id);
  3954. qdf_assert_always(0);
  3955. }
  3956. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3957. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3958. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  3959. tx_desc->flags, tx_desc_id);
  3960. qdf_assert_always(0);
  3961. }
  3962. /* Collect hw completion contents */
  3963. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3964. &tx_desc->comp, 1);
  3965. add_to_pool:
  3966. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3967. /* First ring descriptor on the cycle */
  3968. if (!head_desc) {
  3969. head_desc = tx_desc;
  3970. tail_desc = tx_desc;
  3971. }
  3972. tail_desc->next = tx_desc;
  3973. tx_desc->next = NULL;
  3974. tail_desc = tx_desc;
  3975. }
  3976. next_desc:
  3977. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3978. /*
  3979. * Processed packet count is more than given quota
  3980. * stop to processing
  3981. */
  3982. count++;
  3983. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3984. break;
  3985. }
  3986. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3987. /* Process the reaped descriptors */
  3988. if (head_desc)
  3989. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3990. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3991. if (num_processed >= quota)
  3992. force_break = true;
  3993. if (!force_break &&
  3994. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3995. hal_ring_hdl)) {
  3996. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3997. if (!hif_exec_should_yield(soc->hif_handle,
  3998. int_ctx->dp_intr_id))
  3999. goto more_data;
  4000. }
  4001. }
  4002. DP_TX_HIST_STATS_PER_PDEV();
  4003. return num_processed;
  4004. }
  4005. #ifdef FEATURE_WLAN_TDLS
  4006. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4007. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4008. {
  4009. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4010. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4011. DP_MOD_ID_TDLS);
  4012. if (!vdev) {
  4013. dp_err("vdev handle for id %d is NULL", vdev_id);
  4014. return NULL;
  4015. }
  4016. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4017. vdev->is_tdls_frame = true;
  4018. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4019. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4020. }
  4021. #endif
  4022. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4023. {
  4024. struct wlan_cfg_dp_soc_ctxt *cfg;
  4025. struct dp_soc *soc;
  4026. soc = vdev->pdev->soc;
  4027. if (!soc)
  4028. return;
  4029. cfg = soc->wlan_cfg_ctx;
  4030. if (!cfg)
  4031. return;
  4032. if (vdev->opmode == wlan_op_mode_ndi)
  4033. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4034. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4035. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4036. (vdev->subtype == wlan_op_subtype_p2p_go))
  4037. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4038. else
  4039. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4040. }
  4041. /**
  4042. * dp_tx_vdev_attach() - attach vdev to dp tx
  4043. * @vdev: virtual device instance
  4044. *
  4045. * Return: QDF_STATUS_SUCCESS: success
  4046. * QDF_STATUS_E_RESOURCES: Error return
  4047. */
  4048. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4049. {
  4050. int pdev_id;
  4051. /*
  4052. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4053. */
  4054. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4055. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4056. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4057. vdev->vdev_id);
  4058. pdev_id =
  4059. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4060. vdev->pdev->pdev_id);
  4061. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4062. /*
  4063. * Set HTT Extension Valid bit to 0 by default
  4064. */
  4065. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4066. dp_tx_vdev_update_search_flags(vdev);
  4067. dp_tx_vdev_update_feature_flags(vdev);
  4068. return QDF_STATUS_SUCCESS;
  4069. }
  4070. #ifndef FEATURE_WDS
  4071. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4072. {
  4073. return false;
  4074. }
  4075. #endif
  4076. /**
  4077. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4078. * @vdev: virtual device instance
  4079. *
  4080. * Return: void
  4081. *
  4082. */
  4083. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4084. {
  4085. struct dp_soc *soc = vdev->pdev->soc;
  4086. /*
  4087. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4088. * for TDLS link
  4089. *
  4090. * Enable AddrY (SA based search) only for non-WDS STA and
  4091. * ProxySTA VAP (in HKv1) modes.
  4092. *
  4093. * In all other VAP modes, only DA based search should be
  4094. * enabled
  4095. */
  4096. if (vdev->opmode == wlan_op_mode_sta &&
  4097. vdev->tdls_link_connected)
  4098. vdev->hal_desc_addr_search_flags =
  4099. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4100. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4101. !dp_tx_da_search_override(vdev))
  4102. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4103. else
  4104. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4105. /* Set search type only when peer map v2 messaging is enabled
  4106. * as we will have the search index (AST hash) only when v2 is
  4107. * enabled
  4108. */
  4109. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4110. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4111. else
  4112. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4113. }
  4114. static inline bool
  4115. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4116. struct dp_vdev *vdev,
  4117. struct dp_tx_desc_s *tx_desc)
  4118. {
  4119. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4120. return false;
  4121. /*
  4122. * if vdev is given, then only check whether desc
  4123. * vdev match. if vdev is NULL, then check whether
  4124. * desc pdev match.
  4125. */
  4126. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4127. (tx_desc->pdev == pdev);
  4128. }
  4129. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4130. /**
  4131. * dp_tx_desc_flush() - release resources associated
  4132. * to TX Desc
  4133. *
  4134. * @dp_pdev: Handle to DP pdev structure
  4135. * @vdev: virtual device instance
  4136. * NULL: no specific Vdev is required and check all allcated TX desc
  4137. * on this pdev.
  4138. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4139. *
  4140. * @force_free:
  4141. * true: flush the TX desc.
  4142. * false: only reset the Vdev in each allocated TX desc
  4143. * that associated to current Vdev.
  4144. *
  4145. * This function will go through the TX desc pool to flush
  4146. * the outstanding TX data or reset Vdev to NULL in associated TX
  4147. * Desc.
  4148. */
  4149. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4150. bool force_free)
  4151. {
  4152. uint8_t i;
  4153. uint32_t j;
  4154. uint32_t num_desc, page_id, offset;
  4155. uint16_t num_desc_per_page;
  4156. struct dp_soc *soc = pdev->soc;
  4157. struct dp_tx_desc_s *tx_desc = NULL;
  4158. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4159. if (!vdev && !force_free) {
  4160. dp_err("Reset TX desc vdev, Vdev param is required!");
  4161. return;
  4162. }
  4163. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4164. tx_desc_pool = &soc->tx_desc[i];
  4165. if (!(tx_desc_pool->pool_size) ||
  4166. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4167. !(tx_desc_pool->desc_pages.cacheable_pages))
  4168. continue;
  4169. /*
  4170. * Add flow pool lock protection in case pool is freed
  4171. * due to all tx_desc is recycled when handle TX completion.
  4172. * this is not necessary when do force flush as:
  4173. * a. double lock will happen if dp_tx_desc_release is
  4174. * also trying to acquire it.
  4175. * b. dp interrupt has been disabled before do force TX desc
  4176. * flush in dp_pdev_deinit().
  4177. */
  4178. if (!force_free)
  4179. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4180. num_desc = tx_desc_pool->pool_size;
  4181. num_desc_per_page =
  4182. tx_desc_pool->desc_pages.num_element_per_page;
  4183. for (j = 0; j < num_desc; j++) {
  4184. page_id = j / num_desc_per_page;
  4185. offset = j % num_desc_per_page;
  4186. if (qdf_unlikely(!(tx_desc_pool->
  4187. desc_pages.cacheable_pages)))
  4188. break;
  4189. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4190. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4191. /*
  4192. * Free TX desc if force free is
  4193. * required, otherwise only reset vdev
  4194. * in this TX desc.
  4195. */
  4196. if (force_free) {
  4197. dp_tx_comp_free_buf(soc, tx_desc);
  4198. dp_tx_desc_release(tx_desc, i);
  4199. } else {
  4200. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4201. }
  4202. }
  4203. }
  4204. if (!force_free)
  4205. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4206. }
  4207. }
  4208. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4209. /**
  4210. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4211. *
  4212. * @soc: Handle to DP soc structure
  4213. * @tx_desc: pointer of one TX desc
  4214. * @desc_pool_id: TX Desc pool id
  4215. */
  4216. static inline void
  4217. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4218. uint8_t desc_pool_id)
  4219. {
  4220. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4221. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4222. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4223. }
  4224. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4225. bool force_free)
  4226. {
  4227. uint8_t i, num_pool;
  4228. uint32_t j;
  4229. uint32_t num_desc, page_id, offset;
  4230. uint16_t num_desc_per_page;
  4231. struct dp_soc *soc = pdev->soc;
  4232. struct dp_tx_desc_s *tx_desc = NULL;
  4233. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4234. if (!vdev && !force_free) {
  4235. dp_err("Reset TX desc vdev, Vdev param is required!");
  4236. return;
  4237. }
  4238. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4239. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4240. for (i = 0; i < num_pool; i++) {
  4241. tx_desc_pool = &soc->tx_desc[i];
  4242. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4243. continue;
  4244. num_desc_per_page =
  4245. tx_desc_pool->desc_pages.num_element_per_page;
  4246. for (j = 0; j < num_desc; j++) {
  4247. page_id = j / num_desc_per_page;
  4248. offset = j % num_desc_per_page;
  4249. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4250. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4251. if (force_free) {
  4252. dp_tx_comp_free_buf(soc, tx_desc);
  4253. dp_tx_desc_release(tx_desc, i);
  4254. } else {
  4255. dp_tx_desc_reset_vdev(soc, tx_desc,
  4256. i);
  4257. }
  4258. }
  4259. }
  4260. }
  4261. }
  4262. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4263. /**
  4264. * dp_tx_vdev_detach() - detach vdev from dp tx
  4265. * @vdev: virtual device instance
  4266. *
  4267. * Return: QDF_STATUS_SUCCESS: success
  4268. * QDF_STATUS_E_RESOURCES: Error return
  4269. */
  4270. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4271. {
  4272. struct dp_pdev *pdev = vdev->pdev;
  4273. /* Reset TX desc associated to this Vdev as NULL */
  4274. dp_tx_desc_flush(pdev, vdev, false);
  4275. return QDF_STATUS_SUCCESS;
  4276. }
  4277. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4278. /* Pools will be allocated dynamically */
  4279. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4280. int num_desc)
  4281. {
  4282. uint8_t i;
  4283. for (i = 0; i < num_pool; i++) {
  4284. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4285. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4286. }
  4287. return QDF_STATUS_SUCCESS;
  4288. }
  4289. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4290. int num_desc)
  4291. {
  4292. return QDF_STATUS_SUCCESS;
  4293. }
  4294. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4295. {
  4296. }
  4297. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4298. {
  4299. uint8_t i;
  4300. for (i = 0; i < num_pool; i++)
  4301. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4302. }
  4303. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4304. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4305. int num_desc)
  4306. {
  4307. uint8_t i, count;
  4308. /* Allocate software Tx descriptor pools */
  4309. for (i = 0; i < num_pool; i++) {
  4310. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4311. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4312. FL("Tx Desc Pool alloc %d failed %pK"),
  4313. i, soc);
  4314. goto fail;
  4315. }
  4316. }
  4317. return QDF_STATUS_SUCCESS;
  4318. fail:
  4319. for (count = 0; count < i; count++)
  4320. dp_tx_desc_pool_free(soc, count);
  4321. return QDF_STATUS_E_NOMEM;
  4322. }
  4323. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4324. int num_desc)
  4325. {
  4326. uint8_t i;
  4327. for (i = 0; i < num_pool; i++) {
  4328. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4329. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4330. FL("Tx Desc Pool init %d failed %pK"),
  4331. i, soc);
  4332. return QDF_STATUS_E_NOMEM;
  4333. }
  4334. }
  4335. return QDF_STATUS_SUCCESS;
  4336. }
  4337. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4338. {
  4339. uint8_t i;
  4340. for (i = 0; i < num_pool; i++)
  4341. dp_tx_desc_pool_deinit(soc, i);
  4342. }
  4343. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4344. {
  4345. uint8_t i;
  4346. for (i = 0; i < num_pool; i++)
  4347. dp_tx_desc_pool_free(soc, i);
  4348. }
  4349. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4350. /**
  4351. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4352. * @soc: core txrx main context
  4353. * @num_pool: number of pools
  4354. *
  4355. */
  4356. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4357. {
  4358. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4359. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4360. }
  4361. /**
  4362. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4363. * @soc: core txrx main context
  4364. * @num_pool: number of pools
  4365. *
  4366. */
  4367. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4368. {
  4369. dp_tx_tso_desc_pool_free(soc, num_pool);
  4370. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4371. }
  4372. /**
  4373. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4374. * @soc: core txrx main context
  4375. *
  4376. * This function frees all tx related descriptors as below
  4377. * 1. Regular TX descriptors (static pools)
  4378. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4379. * 3. TSO descriptors
  4380. *
  4381. */
  4382. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4383. {
  4384. uint8_t num_pool;
  4385. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4386. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4387. dp_tx_ext_desc_pool_free(soc, num_pool);
  4388. dp_tx_delete_static_pools(soc, num_pool);
  4389. }
  4390. /**
  4391. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4392. * @soc: core txrx main context
  4393. *
  4394. * This function de-initializes all tx related descriptors as below
  4395. * 1. Regular TX descriptors (static pools)
  4396. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4397. * 3. TSO descriptors
  4398. *
  4399. */
  4400. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4401. {
  4402. uint8_t num_pool;
  4403. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4404. dp_tx_flow_control_deinit(soc);
  4405. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4406. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4407. dp_tx_deinit_static_pools(soc, num_pool);
  4408. }
  4409. /**
  4410. * dp_tso_attach() - TSO attach handler
  4411. * @txrx_soc: Opaque Dp handle
  4412. *
  4413. * Reserve TSO descriptor buffers
  4414. *
  4415. * Return: QDF_STATUS_E_FAILURE on failure or
  4416. * QDF_STATUS_SUCCESS on success
  4417. */
  4418. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4419. uint8_t num_pool,
  4420. uint16_t num_desc)
  4421. {
  4422. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4423. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4424. return QDF_STATUS_E_FAILURE;
  4425. }
  4426. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4427. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4428. num_pool, soc);
  4429. return QDF_STATUS_E_FAILURE;
  4430. }
  4431. return QDF_STATUS_SUCCESS;
  4432. }
  4433. /**
  4434. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4435. * @soc: DP soc handle
  4436. * @num_pool: Number of pools
  4437. * @num_desc: Number of descriptors
  4438. *
  4439. * Initialize TSO descriptor pools
  4440. *
  4441. * Return: QDF_STATUS_E_FAILURE on failure or
  4442. * QDF_STATUS_SUCCESS on success
  4443. */
  4444. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4445. uint8_t num_pool,
  4446. uint16_t num_desc)
  4447. {
  4448. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4449. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4450. return QDF_STATUS_E_FAILURE;
  4451. }
  4452. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4453. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4454. num_pool, soc);
  4455. return QDF_STATUS_E_FAILURE;
  4456. }
  4457. return QDF_STATUS_SUCCESS;
  4458. }
  4459. /**
  4460. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4461. * @soc: core txrx main context
  4462. *
  4463. * This function allocates memory for following descriptor pools
  4464. * 1. regular sw tx descriptor pools (static pools)
  4465. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4466. * 3. TSO descriptor pools
  4467. *
  4468. * Return: QDF_STATUS_SUCCESS: success
  4469. * QDF_STATUS_E_RESOURCES: Error return
  4470. */
  4471. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4472. {
  4473. uint8_t num_pool;
  4474. uint32_t num_desc;
  4475. uint32_t num_ext_desc;
  4476. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4477. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4478. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4479. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4480. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4481. __func__, num_pool, num_desc);
  4482. if ((num_pool > MAX_TXDESC_POOLS) ||
  4483. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4484. goto fail1;
  4485. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4486. goto fail1;
  4487. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4488. goto fail2;
  4489. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4490. return QDF_STATUS_SUCCESS;
  4491. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4492. goto fail3;
  4493. return QDF_STATUS_SUCCESS;
  4494. fail3:
  4495. dp_tx_ext_desc_pool_free(soc, num_pool);
  4496. fail2:
  4497. dp_tx_delete_static_pools(soc, num_pool);
  4498. fail1:
  4499. return QDF_STATUS_E_RESOURCES;
  4500. }
  4501. /**
  4502. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4503. * @soc: core txrx main context
  4504. *
  4505. * This function initializes the following TX descriptor pools
  4506. * 1. regular sw tx descriptor pools (static pools)
  4507. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4508. * 3. TSO descriptor pools
  4509. *
  4510. * Return: QDF_STATUS_SUCCESS: success
  4511. * QDF_STATUS_E_RESOURCES: Error return
  4512. */
  4513. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4514. {
  4515. uint8_t num_pool;
  4516. uint32_t num_desc;
  4517. uint32_t num_ext_desc;
  4518. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4519. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4520. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4521. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4522. goto fail1;
  4523. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4524. goto fail2;
  4525. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4526. return QDF_STATUS_SUCCESS;
  4527. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4528. goto fail3;
  4529. dp_tx_flow_control_init(soc);
  4530. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4531. return QDF_STATUS_SUCCESS;
  4532. fail3:
  4533. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4534. fail2:
  4535. dp_tx_deinit_static_pools(soc, num_pool);
  4536. fail1:
  4537. return QDF_STATUS_E_RESOURCES;
  4538. }
  4539. /**
  4540. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4541. * @txrx_soc: dp soc handle
  4542. *
  4543. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4544. * QDF_STATUS_E_FAILURE
  4545. */
  4546. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4547. {
  4548. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4549. uint8_t num_pool;
  4550. uint32_t num_desc;
  4551. uint32_t num_ext_desc;
  4552. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4553. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4554. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4555. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4556. return QDF_STATUS_E_FAILURE;
  4557. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4558. return QDF_STATUS_E_FAILURE;
  4559. return QDF_STATUS_SUCCESS;
  4560. }
  4561. /**
  4562. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4563. * @txrx_soc: dp soc handle
  4564. *
  4565. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4566. */
  4567. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4568. {
  4569. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4570. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4571. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4572. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4573. return QDF_STATUS_SUCCESS;
  4574. }