sde_hw_dspp.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <drm/msm_drm_pp.h>
  6. #include "sde_hw_mdss.h"
  7. #include "sde_hwio.h"
  8. #include "sde_hw_catalog.h"
  9. #include "sde_hw_dspp.h"
  10. #include "sde_hw_color_processing.h"
  11. #include "sde_dbg.h"
  12. #include "sde_ad4.h"
  13. #include "sde_hw_rc.h"
  14. #include "sde_kms.h"
  15. static struct sde_dspp_cfg *_dspp_offset(enum sde_dspp dspp,
  16. struct sde_mdss_cfg *m,
  17. void __iomem *addr,
  18. struct sde_hw_blk_reg_map *b)
  19. {
  20. int i;
  21. if (!m || !addr || !b)
  22. return ERR_PTR(-EINVAL);
  23. for (i = 0; i < m->dspp_count; i++) {
  24. if (dspp == m->dspp[i].id) {
  25. b->base_off = addr;
  26. b->blk_off = m->dspp[i].base;
  27. b->length = m->dspp[i].len;
  28. b->hwversion = m->hwversion;
  29. b->log_mask = SDE_DBG_MASK_DSPP;
  30. return &m->dspp[i];
  31. }
  32. }
  33. return ERR_PTR(-EINVAL);
  34. }
  35. static void dspp_igc(struct sde_hw_dspp *c)
  36. {
  37. int ret = 0;
  38. if (c->cap->sblk->igc.version == SDE_COLOR_PROCESS_VER(0x3, 0x1)) {
  39. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_IGC, c->idx);
  40. if (!ret)
  41. c->ops.setup_igc = reg_dmav1_setup_dspp_igcv31;
  42. else
  43. c->ops.setup_igc = sde_setup_dspp_igcv3;
  44. } else if (c->cap->sblk->igc.version ==
  45. SDE_COLOR_PROCESS_VER(0x3, 0x2)) {
  46. c->ops.setup_igc = NULL;
  47. ret = reg_dmav2_init_dspp_op_v4(SDE_DSPP_IGC, c->idx);
  48. if (!ret)
  49. c->ops.setup_igc = reg_dmav2_setup_dspp_igcv32;
  50. }
  51. }
  52. static void dspp_pcc(struct sde_hw_dspp *c)
  53. {
  54. int ret = 0;
  55. if (c->cap->sblk->pcc.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7)))
  56. c->ops.setup_pcc = sde_setup_dspp_pcc_v1_7;
  57. else if (c->cap->sblk->pcc.version ==
  58. (SDE_COLOR_PROCESS_VER(0x4, 0x0))) {
  59. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_PCC, c->idx);
  60. if (!ret)
  61. c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv4;
  62. else
  63. c->ops.setup_pcc = sde_setup_dspp_pccv4;
  64. }
  65. }
  66. static void dspp_gc(struct sde_hw_dspp *c)
  67. {
  68. int ret = 0;
  69. if (c->cap->sblk->gc.version == SDE_COLOR_PROCESS_VER(0x1, 8)) {
  70. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GC, c->idx);
  71. if (!ret)
  72. c->ops.setup_gc = reg_dmav1_setup_dspp_gcv18;
  73. /**
  74. * programming for v18 through ahb is same as v17,
  75. * hence assign v17 function
  76. */
  77. else
  78. c->ops.setup_gc = sde_setup_dspp_gc_v1_7;
  79. }
  80. }
  81. static void dspp_hsic(struct sde_hw_dspp *c)
  82. {
  83. int ret = 0;
  84. if (c->cap->sblk->hsic.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
  85. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_HSIC, c->idx);
  86. if (!ret)
  87. c->ops.setup_pa_hsic = reg_dmav1_setup_dspp_pa_hsicv17;
  88. else
  89. c->ops.setup_pa_hsic = sde_setup_dspp_pa_hsic_v17;
  90. }
  91. }
  92. static void dspp_memcolor(struct sde_hw_dspp *c)
  93. {
  94. int ret = 0;
  95. if (c->cap->sblk->memcolor.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
  96. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_MEMCOLOR, c->idx);
  97. if (!ret) {
  98. c->ops.setup_pa_memcol_skin =
  99. reg_dmav1_setup_dspp_memcol_skinv17;
  100. c->ops.setup_pa_memcol_sky =
  101. reg_dmav1_setup_dspp_memcol_skyv17;
  102. c->ops.setup_pa_memcol_foliage =
  103. reg_dmav1_setup_dspp_memcol_folv17;
  104. c->ops.setup_pa_memcol_prot =
  105. reg_dmav1_setup_dspp_memcol_protv17;
  106. } else {
  107. c->ops.setup_pa_memcol_skin =
  108. sde_setup_dspp_memcol_skin_v17;
  109. c->ops.setup_pa_memcol_sky =
  110. sde_setup_dspp_memcol_sky_v17;
  111. c->ops.setup_pa_memcol_foliage =
  112. sde_setup_dspp_memcol_foliage_v17;
  113. c->ops.setup_pa_memcol_prot =
  114. sde_setup_dspp_memcol_prot_v17;
  115. }
  116. }
  117. }
  118. static void dspp_sixzone(struct sde_hw_dspp *c)
  119. {
  120. int ret = 0;
  121. if (c->cap->sblk->sixzone.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
  122. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_SIXZONE, c->idx);
  123. if (!ret)
  124. c->ops.setup_sixzone = reg_dmav1_setup_dspp_sixzonev17;
  125. else
  126. c->ops.setup_sixzone = sde_setup_dspp_sixzone_v17;
  127. }
  128. }
  129. static void dspp_gamut(struct sde_hw_dspp *c)
  130. {
  131. int ret = 0;
  132. if (c->cap->sblk->gamut.version == SDE_COLOR_PROCESS_VER(0x4, 0)) {
  133. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  134. if (!ret)
  135. c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv4;
  136. else
  137. c->ops.setup_gamut = sde_setup_dspp_3d_gamutv4;
  138. } else if (c->cap->sblk->gamut.version ==
  139. SDE_COLOR_PROCESS_VER(0x4, 1)) {
  140. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  141. if (!ret)
  142. c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv41;
  143. else
  144. c->ops.setup_gamut = sde_setup_dspp_3d_gamutv41;
  145. } else if (c->cap->sblk->gamut.version ==
  146. SDE_COLOR_PROCESS_VER(0x4, 2)) {
  147. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  148. c->ops.setup_gamut = NULL;
  149. if (!ret)
  150. c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv42;
  151. } else if (c->cap->sblk->gamut.version ==
  152. SDE_COLOR_PROCESS_VER(0x4, 3)) {
  153. c->ops.setup_gamut = NULL;
  154. ret = reg_dmav2_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  155. if (!ret)
  156. c->ops.setup_gamut = reg_dmav2_setup_dspp_3d_gamutv43;
  157. }
  158. }
  159. static void dspp_dither(struct sde_hw_dspp *c)
  160. {
  161. if (c->cap->sblk->dither.version == SDE_COLOR_PROCESS_VER(0x1, 0x7))
  162. c->ops.setup_pa_dither = sde_setup_dspp_dither_v1_7;
  163. }
  164. static void dspp_hist(struct sde_hw_dspp *c)
  165. {
  166. if (c->cap->sblk->hist.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
  167. c->ops.setup_histogram = sde_setup_dspp_hist_v1_7;
  168. c->ops.read_histogram = sde_read_dspp_hist_v1_7;
  169. c->ops.lock_histogram = sde_lock_dspp_hist_v1_7;
  170. }
  171. }
  172. static void dspp_vlut(struct sde_hw_dspp *c)
  173. {
  174. int ret = 0;
  175. if (c->cap->sblk->vlut.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
  176. c->ops.setup_vlut = sde_setup_dspp_pa_vlut_v1_7;
  177. } else if (c->cap->sblk->vlut.version ==
  178. (SDE_COLOR_PROCESS_VER(0x1, 0x8))) {
  179. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_VLUT, c->idx);
  180. if (!ret)
  181. c->ops.setup_vlut = reg_dmav1_setup_dspp_vlutv18;
  182. else
  183. c->ops.setup_vlut = sde_setup_dspp_pa_vlut_v1_8;
  184. }
  185. }
  186. static void dspp_ad(struct sde_hw_dspp *c)
  187. {
  188. if (c->cap->sblk->ad.version == SDE_COLOR_PROCESS_VER(4, 0)) {
  189. c->ops.setup_ad = sde_setup_dspp_ad4;
  190. c->ops.ad_read_intr_resp = sde_read_intr_resp_ad4;
  191. c->ops.validate_ad = sde_validate_dspp_ad4;
  192. }
  193. }
  194. static void dspp_ltm(struct sde_hw_dspp *c)
  195. {
  196. int ret = 0;
  197. if (c->cap->sblk->ltm.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {
  198. ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_INIT, c->idx);
  199. if (!ret)
  200. ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_ROI, c->idx);
  201. if (!ret)
  202. ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_VLUT, c->idx);
  203. if (!ret) {
  204. c->ops.setup_ltm_init = reg_dmav1_setup_ltm_initv1;
  205. c->ops.setup_ltm_roi = reg_dmav1_setup_ltm_roiv1;
  206. c->ops.setup_ltm_vlut = reg_dmav1_setup_ltm_vlutv1;
  207. } else {
  208. c->ops.setup_ltm_init = NULL;
  209. c->ops.setup_ltm_roi = NULL;
  210. c->ops.setup_ltm_vlut = NULL;
  211. }
  212. c->ops.setup_ltm_thresh = sde_setup_dspp_ltm_threshv1;
  213. c->ops.setup_ltm_hist_ctrl = sde_setup_dspp_ltm_hist_ctrlv1;
  214. c->ops.setup_ltm_hist_buffer = sde_setup_dspp_ltm_hist_bufferv1;
  215. c->ops.ltm_read_intr_status = sde_ltm_read_intr_status;
  216. }
  217. }
  218. static void dspp_rc(struct sde_hw_dspp *c)
  219. {
  220. int ret = 0;
  221. if (!c) {
  222. SDE_ERROR("invalid arguments\n");
  223. return;
  224. }
  225. if (c->cap->sblk->rc.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {
  226. ret = sde_hw_rc_init(c);
  227. if (ret) {
  228. SDE_ERROR("rc init failed, ret %d\n", ret);
  229. return;
  230. }
  231. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_RC, c->idx);
  232. if (!ret)
  233. c->ops.setup_rc_data =
  234. sde_hw_rc_setup_data_dma;
  235. else
  236. c->ops.setup_rc_data =
  237. sde_hw_rc_setup_data_ahb;
  238. c->ops.validate_rc_mask = sde_hw_rc_check_mask;
  239. c->ops.setup_rc_mask = sde_hw_rc_setup_mask;
  240. c->ops.validate_rc_pu_roi = sde_hw_rc_check_pu_roi;
  241. c->ops.setup_rc_pu_roi = sde_hw_rc_setup_pu_roi;
  242. }
  243. }
  244. static void dspp_spr(struct sde_hw_dspp *c)
  245. {
  246. int ret = 0;
  247. if (!c) {
  248. SDE_ERROR("invalid arguments\n");
  249. return;
  250. }
  251. c->ops.setup_spr_init_config = NULL;
  252. c->ops.setup_spr_pu_config = NULL;
  253. if (c->cap->sblk->spr.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {
  254. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_SPR, c->idx);
  255. if (ret) {
  256. SDE_ERROR("regdma init failed for spr, ret %d\n", ret);
  257. return;
  258. }
  259. c->ops.setup_spr_init_config = reg_dmav1_setup_spr_init_cfgv1;
  260. c->ops.setup_spr_pu_config = reg_dmav1_setup_spr_pu_cfgv1;
  261. }
  262. }
  263. static void dspp_demura(struct sde_hw_dspp *c)
  264. {
  265. int ret;
  266. if (c->cap->sblk->demura.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {
  267. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_DEMURA, c->idx);
  268. c->ops.setup_demura_cfg = NULL;
  269. c->ops.setup_demura_backlight_cfg = NULL;
  270. if (!ret) {
  271. c->ops.setup_demura_cfg = reg_dmav1_setup_demurav1;
  272. c->ops.setup_demura_backlight_cfg =
  273. sde_demura_backlight_cfg;
  274. }
  275. }
  276. }
  277. static void (*dspp_blocks[SDE_DSPP_MAX])(struct sde_hw_dspp *c);
  278. static void _init_dspp_ops(void)
  279. {
  280. dspp_blocks[SDE_DSPP_IGC] = dspp_igc;
  281. dspp_blocks[SDE_DSPP_PCC] = dspp_pcc;
  282. dspp_blocks[SDE_DSPP_GC] = dspp_gc;
  283. dspp_blocks[SDE_DSPP_HSIC] = dspp_hsic;
  284. dspp_blocks[SDE_DSPP_MEMCOLOR] = dspp_memcolor;
  285. dspp_blocks[SDE_DSPP_SIXZONE] = dspp_sixzone;
  286. dspp_blocks[SDE_DSPP_GAMUT] = dspp_gamut;
  287. dspp_blocks[SDE_DSPP_DITHER] = dspp_dither;
  288. dspp_blocks[SDE_DSPP_HIST] = dspp_hist;
  289. dspp_blocks[SDE_DSPP_VLUT] = dspp_vlut;
  290. dspp_blocks[SDE_DSPP_AD] = dspp_ad;
  291. dspp_blocks[SDE_DSPP_LTM] = dspp_ltm;
  292. dspp_blocks[SDE_DSPP_RC] = dspp_rc;
  293. dspp_blocks[SDE_DSPP_SPR] = dspp_spr;
  294. dspp_blocks[SDE_DSPP_DEMURA] = dspp_demura;
  295. }
  296. static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features)
  297. {
  298. int i = 0;
  299. if (!c->cap->sblk)
  300. return;
  301. for (i = 0; i < SDE_DSPP_MAX; i++) {
  302. if (!test_bit(i, &features))
  303. continue;
  304. if (dspp_blocks[i])
  305. dspp_blocks[i](c);
  306. }
  307. }
  308. static struct sde_hw_blk_ops sde_hw_ops = {
  309. .start = NULL,
  310. .stop = NULL,
  311. };
  312. struct sde_hw_dspp *sde_hw_dspp_init(enum sde_dspp idx,
  313. void __iomem *addr,
  314. struct sde_mdss_cfg *m)
  315. {
  316. struct sde_hw_dspp *c;
  317. struct sde_dspp_cfg *cfg;
  318. int rc;
  319. char buf[256];
  320. if (!addr || !m)
  321. return ERR_PTR(-EINVAL);
  322. c = kzalloc(sizeof(*c), GFP_KERNEL);
  323. if (!c)
  324. return ERR_PTR(-ENOMEM);
  325. cfg = _dspp_offset(idx, m, addr, &c->hw);
  326. if (IS_ERR_OR_NULL(cfg)) {
  327. kfree(c);
  328. return ERR_PTR(-EINVAL);
  329. }
  330. /* Populate DSPP Top HW block */
  331. c->hw_top.base_off = addr;
  332. c->hw_top.blk_off = m->dspp_top.base;
  333. c->hw_top.length = m->dspp_top.len;
  334. c->hw_top.hwversion = m->hwversion;
  335. c->hw_top.log_mask = SDE_DBG_MASK_DSPP;
  336. /* Assign ops */
  337. c->idx = idx;
  338. c->cap = cfg;
  339. _init_dspp_ops();
  340. _setup_dspp_ops(c, c->cap->features);
  341. rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_DSPP, idx, &sde_hw_ops);
  342. if (rc) {
  343. SDE_ERROR("failed to init hw blk %d\n", rc);
  344. goto blk_init_error;
  345. }
  346. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
  347. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  348. if ((cfg->sblk->ltm.id == SDE_DSPP_LTM) && cfg->sblk->ltm.base) {
  349. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "LTM",
  350. c->hw.blk_off + cfg->sblk->ltm.base,
  351. c->hw.blk_off + cfg->sblk->ltm.base + 0xC4,
  352. c->hw.xin_id);
  353. }
  354. if ((cfg->sblk->rc.id == SDE_DSPP_RC) && cfg->sblk->rc.base) {
  355. snprintf(buf, ARRAY_SIZE(buf), "%s_%d", "rc", c->idx - DSPP_0);
  356. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, buf,
  357. c->hw.blk_off + cfg->sblk->rc.base,
  358. c->hw.blk_off + cfg->sblk->rc.base +
  359. cfg->sblk->rc.len, c->hw.xin_id);
  360. }
  361. if ((cfg->sblk->spr.id == SDE_DSPP_SPR) && cfg->sblk->spr.base) {
  362. snprintf(buf, ARRAY_SIZE(buf), "%s_%d", "spr", c->idx - DSPP_0);
  363. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, buf,
  364. c->hw.blk_off + cfg->sblk->spr.base,
  365. c->hw.blk_off + cfg->sblk->spr.base +
  366. cfg->sblk->spr.len, c->hw.xin_id);
  367. }
  368. if ((cfg->sblk->demura.id == SDE_DSPP_DEMURA) &&
  369. cfg->sblk->demura.base) {
  370. snprintf(buf, ARRAY_SIZE(buf), "%s_%d", "demura",
  371. c->idx - DSPP_0);
  372. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, buf,
  373. c->hw.blk_off + cfg->sblk->demura.base,
  374. c->hw.blk_off + cfg->sblk->demura.base +
  375. cfg->sblk->demura.len, c->hw.xin_id);
  376. }
  377. return c;
  378. blk_init_error:
  379. kzfree(c);
  380. return ERR_PTR(rc);
  381. }
  382. void sde_hw_dspp_destroy(struct sde_hw_dspp *dspp)
  383. {
  384. if (dspp) {
  385. reg_dmav1_deinit_dspp_ops(dspp->idx);
  386. reg_dmav1_deinit_ltm_ops(dspp->idx);
  387. sde_hw_blk_destroy(&dspp->base);
  388. }
  389. kfree(dspp);
  390. }