main.c 100 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/version.h>
  20. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  21. #include <linux/panic_notifier.h>
  22. #endif
  23. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  24. #include <soc/qcom/minidump.h>
  25. #endif
  26. #include "cnss_plat_ipc_qmi.h"
  27. #include "main.h"
  28. #include "bus.h"
  29. #include "debug.h"
  30. #include "genl.h"
  31. #define CNSS_DUMP_FORMAT_VER 0x11
  32. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  33. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  34. #define CNSS_DUMP_NAME "CNSS_WLAN"
  35. #define CNSS_DUMP_DESC_SIZE 0x1000
  36. #define CNSS_DUMP_SEG_VER 0x1
  37. #define FILE_SYSTEM_READY 1
  38. #define FW_READY_TIMEOUT 20000
  39. #define FW_ASSERT_TIMEOUT 5000
  40. #define CNSS_EVENT_PENDING 2989
  41. #define POWER_RESET_MIN_DELAY_MS 100
  42. #define CNSS_QUIRKS_DEFAULT 0
  43. #ifdef CONFIG_CNSS_EMULATION
  44. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  45. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  46. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  47. #else
  48. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  49. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  50. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  51. #endif
  52. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  53. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  54. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  55. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  56. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  57. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  58. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  59. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  60. enum cnss_cal_db_op {
  61. CNSS_CAL_DB_UPLOAD,
  62. CNSS_CAL_DB_DOWNLOAD,
  63. CNSS_CAL_DB_INVALID_OP,
  64. };
  65. static struct cnss_plat_data *plat_env;
  66. static DECLARE_RWSEM(cnss_pm_sem);
  67. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  68. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  69. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  70. };
  71. static struct cnss_fw_files FW_FILES_DEFAULT = {
  72. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  73. "utfbd.bin", "epping.bin", "evicted.bin"
  74. };
  75. struct cnss_driver_event {
  76. struct list_head list;
  77. enum cnss_driver_event_type type;
  78. bool sync;
  79. struct completion complete;
  80. int ret;
  81. void *data;
  82. };
  83. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  84. struct cnss_plat_data *plat_priv)
  85. {
  86. plat_env = plat_priv;
  87. }
  88. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  89. {
  90. return plat_env;
  91. }
  92. /**
  93. * cnss_get_mem_seg_count - Get segment count of memory
  94. * @type: memory type
  95. * @seg: segment count
  96. *
  97. * Return: 0 on success, negative value on failure
  98. */
  99. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  100. {
  101. struct cnss_plat_data *plat_priv;
  102. plat_priv = cnss_get_plat_priv(NULL);
  103. if (!plat_priv)
  104. return -ENODEV;
  105. switch (type) {
  106. case CNSS_REMOTE_MEM_TYPE_FW:
  107. *seg = plat_priv->fw_mem_seg_len;
  108. break;
  109. case CNSS_REMOTE_MEM_TYPE_QDSS:
  110. *seg = plat_priv->qdss_mem_seg_len;
  111. break;
  112. default:
  113. return -EINVAL;
  114. }
  115. return 0;
  116. }
  117. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  118. /**
  119. * cnss_get_mem_segment_info - Get memory info of different type
  120. * @type: memory type
  121. * @segment: array to save the segment info
  122. * @seg: segment count
  123. *
  124. * Return: 0 on success, negative value on failure
  125. */
  126. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  127. struct cnss_mem_segment segment[],
  128. u32 segment_count)
  129. {
  130. struct cnss_plat_data *plat_priv;
  131. u32 i;
  132. plat_priv = cnss_get_plat_priv(NULL);
  133. if (!plat_priv)
  134. return -ENODEV;
  135. switch (type) {
  136. case CNSS_REMOTE_MEM_TYPE_FW:
  137. if (segment_count > plat_priv->fw_mem_seg_len)
  138. segment_count = plat_priv->fw_mem_seg_len;
  139. for (i = 0; i < segment_count; i++) {
  140. segment[i].size = plat_priv->fw_mem[i].size;
  141. segment[i].va = plat_priv->fw_mem[i].va;
  142. segment[i].pa = plat_priv->fw_mem[i].pa;
  143. }
  144. break;
  145. case CNSS_REMOTE_MEM_TYPE_QDSS:
  146. if (segment_count > plat_priv->qdss_mem_seg_len)
  147. segment_count = plat_priv->qdss_mem_seg_len;
  148. for (i = 0; i < segment_count; i++) {
  149. segment[i].size = plat_priv->qdss_mem[i].size;
  150. segment[i].va = plat_priv->qdss_mem[i].va;
  151. segment[i].pa = plat_priv->qdss_mem[i].pa;
  152. }
  153. break;
  154. default:
  155. return -EINVAL;
  156. }
  157. return 0;
  158. }
  159. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  160. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  161. enum cnss_feature_v01 feature)
  162. {
  163. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  164. return -EINVAL;
  165. plat_priv->feature_list |= 1 << feature;
  166. return 0;
  167. }
  168. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  169. u64 *feature_list)
  170. {
  171. if (unlikely(!plat_priv))
  172. return -EINVAL;
  173. *feature_list = plat_priv->feature_list;
  174. return 0;
  175. }
  176. static int cnss_pm_notify(struct notifier_block *b,
  177. unsigned long event, void *p)
  178. {
  179. switch (event) {
  180. case PM_SUSPEND_PREPARE:
  181. down_write(&cnss_pm_sem);
  182. break;
  183. case PM_POST_SUSPEND:
  184. up_write(&cnss_pm_sem);
  185. break;
  186. }
  187. return NOTIFY_DONE;
  188. }
  189. static struct notifier_block cnss_pm_notifier = {
  190. .notifier_call = cnss_pm_notify,
  191. };
  192. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  193. {
  194. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  195. return;
  196. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  197. plat_priv->driver_state,
  198. atomic_read(&plat_priv->pm_count));
  199. pm_stay_awake(&plat_priv->plat_dev->dev);
  200. }
  201. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  202. {
  203. int r = atomic_dec_return(&plat_priv->pm_count);
  204. WARN_ON(r < 0);
  205. if (r != 0)
  206. return;
  207. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  208. plat_priv->driver_state,
  209. atomic_read(&plat_priv->pm_count));
  210. pm_relax(&plat_priv->plat_dev->dev);
  211. }
  212. void cnss_lock_pm_sem(struct device *dev)
  213. {
  214. down_read(&cnss_pm_sem);
  215. }
  216. EXPORT_SYMBOL(cnss_lock_pm_sem);
  217. void cnss_release_pm_sem(struct device *dev)
  218. {
  219. up_read(&cnss_pm_sem);
  220. }
  221. EXPORT_SYMBOL(cnss_release_pm_sem);
  222. int cnss_get_fw_files_for_target(struct device *dev,
  223. struct cnss_fw_files *pfw_files,
  224. u32 target_type, u32 target_version)
  225. {
  226. if (!pfw_files)
  227. return -ENODEV;
  228. switch (target_version) {
  229. case QCA6174_REV3_VERSION:
  230. case QCA6174_REV3_2_VERSION:
  231. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  232. break;
  233. default:
  234. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  235. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  236. target_type, target_version);
  237. break;
  238. }
  239. return 0;
  240. }
  241. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  242. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  243. {
  244. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  245. if (!plat_priv)
  246. return -ENODEV;
  247. if (!cap)
  248. return -EINVAL;
  249. *cap = plat_priv->cap;
  250. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  251. return 0;
  252. }
  253. EXPORT_SYMBOL(cnss_get_platform_cap);
  254. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  255. {
  256. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  257. if (!plat_priv)
  258. return;
  259. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  260. }
  261. EXPORT_SYMBOL(cnss_request_pm_qos);
  262. void cnss_remove_pm_qos(struct device *dev)
  263. {
  264. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  265. if (!plat_priv)
  266. return;
  267. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  268. }
  269. EXPORT_SYMBOL(cnss_remove_pm_qos);
  270. int cnss_wlan_enable(struct device *dev,
  271. struct cnss_wlan_enable_cfg *config,
  272. enum cnss_driver_mode mode,
  273. const char *host_version)
  274. {
  275. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  276. int ret = 0;
  277. if (!plat_priv)
  278. return -ENODEV;
  279. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  280. return 0;
  281. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  282. return 0;
  283. if (!config || !host_version) {
  284. cnss_pr_err("Invalid config or host_version pointer\n");
  285. return -EINVAL;
  286. }
  287. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  288. mode, config, host_version);
  289. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  290. goto skip_cfg;
  291. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  292. if (ret)
  293. goto out;
  294. skip_cfg:
  295. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  296. out:
  297. return ret;
  298. }
  299. EXPORT_SYMBOL(cnss_wlan_enable);
  300. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  301. {
  302. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  303. int ret = 0;
  304. if (!plat_priv)
  305. return -ENODEV;
  306. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  307. return 0;
  308. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  309. return 0;
  310. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  311. cnss_bus_free_qdss_mem(plat_priv);
  312. return ret;
  313. }
  314. EXPORT_SYMBOL(cnss_wlan_disable);
  315. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  316. u32 data_len, u8 *output)
  317. {
  318. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  319. int ret = 0;
  320. if (!plat_priv) {
  321. cnss_pr_err("plat_priv is NULL!\n");
  322. return -EINVAL;
  323. }
  324. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  325. return 0;
  326. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  327. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  328. plat_priv->driver_state);
  329. ret = -EINVAL;
  330. goto out;
  331. }
  332. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  333. data_len, output);
  334. out:
  335. return ret;
  336. }
  337. EXPORT_SYMBOL(cnss_athdiag_read);
  338. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  339. u32 data_len, u8 *input)
  340. {
  341. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  342. int ret = 0;
  343. if (!plat_priv) {
  344. cnss_pr_err("plat_priv is NULL!\n");
  345. return -EINVAL;
  346. }
  347. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  348. return 0;
  349. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  350. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  351. plat_priv->driver_state);
  352. ret = -EINVAL;
  353. goto out;
  354. }
  355. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  356. data_len, input);
  357. out:
  358. return ret;
  359. }
  360. EXPORT_SYMBOL(cnss_athdiag_write);
  361. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  362. {
  363. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  364. if (!plat_priv)
  365. return -ENODEV;
  366. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  367. return 0;
  368. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  369. }
  370. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  371. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  372. {
  373. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  374. if (!plat_priv)
  375. return -EINVAL;
  376. if (plat_priv->device_id != QCA6490_DEVICE_ID ||
  377. !plat_priv->fw_pcie_gen_switch)
  378. return -EOPNOTSUPP;
  379. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  380. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  381. return -EINVAL;
  382. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  383. plat_priv->pcie_gen_speed = pcie_gen_speed;
  384. return 0;
  385. }
  386. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  387. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  388. {
  389. int ret = 0;
  390. if (!plat_priv)
  391. return -ENODEV;
  392. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  393. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  394. if (ret)
  395. goto out;
  396. if (plat_priv->hds_enabled)
  397. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  398. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  399. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  400. plat_priv->ctrl_params.bdf_type);
  401. if (ret)
  402. goto out;
  403. ret = cnss_bus_load_m3(plat_priv);
  404. if (ret)
  405. goto out;
  406. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  407. if (ret)
  408. goto out;
  409. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  410. return 0;
  411. out:
  412. return ret;
  413. }
  414. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  415. {
  416. int ret = 0;
  417. if (!plat_priv->antenna) {
  418. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  419. if (ret)
  420. goto out;
  421. }
  422. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  423. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  424. if (ret)
  425. goto out;
  426. }
  427. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  428. if (ret)
  429. goto out;
  430. return 0;
  431. out:
  432. return ret;
  433. }
  434. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  435. {
  436. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  437. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  438. }
  439. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  440. {
  441. u32 i;
  442. int ret = 0;
  443. struct cnss_plat_ipc_daemon_config *cfg;
  444. ret = cnss_qmi_get_dms_mac(plat_priv);
  445. if (ret == 0 && plat_priv->dms.mac_valid)
  446. goto qmi_send;
  447. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  448. * Thus assert on failure to get MAC from DMS even after retries
  449. */
  450. if (plat_priv->use_nv_mac) {
  451. /* Check if Daemon says platform support DMS MAC provisioning */
  452. cfg = cnss_plat_ipc_qmi_daemon_config();
  453. if (cfg) {
  454. if (!cfg->dms_mac_addr_supported) {
  455. cnss_pr_err("DMS MAC address not supported\n");
  456. CNSS_ASSERT(0);
  457. return -EINVAL;
  458. }
  459. }
  460. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  461. if (plat_priv->dms.mac_valid)
  462. break;
  463. ret = cnss_qmi_get_dms_mac(plat_priv);
  464. if (ret == 0)
  465. break;
  466. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  467. }
  468. if (!plat_priv->dms.mac_valid) {
  469. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  470. CNSS_ASSERT(0);
  471. return -EINVAL;
  472. }
  473. }
  474. qmi_send:
  475. if (plat_priv->dms.mac_valid)
  476. ret =
  477. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  478. ARRAY_SIZE(plat_priv->dms.mac));
  479. return ret;
  480. }
  481. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  482. enum cnss_cal_db_op op, u32 *size)
  483. {
  484. int ret = 0;
  485. u32 timeout = cnss_get_timeout(plat_priv,
  486. CNSS_TIMEOUT_DAEMON_CONNECTION);
  487. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  488. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  489. if (op >= CNSS_CAL_DB_INVALID_OP)
  490. return -EINVAL;
  491. if (!plat_priv->cbc_file_download) {
  492. cnss_pr_info("CAL DB file not required as per BDF\n");
  493. return 0;
  494. }
  495. if (*size == 0) {
  496. cnss_pr_err("Invalid cal file size\n");
  497. return -EINVAL;
  498. }
  499. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  500. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  501. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  502. msecs_to_jiffies(timeout));
  503. if (!ret) {
  504. cnss_pr_err("Daemon not yet connected\n");
  505. CNSS_ASSERT(0);
  506. return ret;
  507. }
  508. }
  509. if (!plat_priv->cal_mem->va) {
  510. cnss_pr_err("CAL DB Memory not setup for FW\n");
  511. return -EINVAL;
  512. }
  513. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  514. if (op == CNSS_CAL_DB_DOWNLOAD) {
  515. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  516. ret = cnss_plat_ipc_qmi_file_download(client_id,
  517. CNSS_CAL_DB_FILE_NAME,
  518. plat_priv->cal_mem->va,
  519. size);
  520. } else {
  521. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  522. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  523. CNSS_CAL_DB_FILE_NAME,
  524. plat_priv->cal_mem->va,
  525. *size);
  526. }
  527. if (ret)
  528. cnss_pr_err("Cal DB file %s %s failure\n",
  529. CNSS_CAL_DB_FILE_NAME,
  530. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  531. else
  532. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  533. CNSS_CAL_DB_FILE_NAME,
  534. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  535. *size);
  536. return ret;
  537. }
  538. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  539. {
  540. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  541. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  542. return -EINVAL;
  543. }
  544. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  545. &plat_priv->cal_file_size);
  546. }
  547. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  548. u32 *cal_file_size)
  549. {
  550. /* To download pass the total size of cal DB mem allocated.
  551. * After cal file is download to mem, its size is updated in
  552. * return pointer
  553. */
  554. *cal_file_size = plat_priv->cal_mem->size;
  555. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  556. cal_file_size);
  557. }
  558. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  559. {
  560. int ret = 0;
  561. u32 cal_file_size = 0;
  562. if (!plat_priv)
  563. return -ENODEV;
  564. cnss_pr_dbg("Processing FW Init Done..\n");
  565. del_timer(&plat_priv->fw_boot_timer);
  566. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  567. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  568. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  569. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  570. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  571. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  572. }
  573. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  574. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  575. CNSS_WALTEST);
  576. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  577. cnss_request_antenna_sharing(plat_priv);
  578. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  579. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  580. plat_priv->cal_time = jiffies;
  581. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  582. CNSS_CALIBRATION);
  583. } else {
  584. ret = cnss_setup_dms_mac(plat_priv);
  585. ret = cnss_bus_call_driver_probe(plat_priv);
  586. }
  587. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  588. goto out;
  589. else if (ret)
  590. goto shutdown;
  591. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  592. return 0;
  593. shutdown:
  594. cnss_bus_dev_shutdown(plat_priv);
  595. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  596. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  597. out:
  598. return ret;
  599. }
  600. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  601. {
  602. switch (type) {
  603. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  604. return "SERVER_ARRIVE";
  605. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  606. return "SERVER_EXIT";
  607. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  608. return "REQUEST_MEM";
  609. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  610. return "FW_MEM_READY";
  611. case CNSS_DRIVER_EVENT_FW_READY:
  612. return "FW_READY";
  613. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  614. return "COLD_BOOT_CAL_START";
  615. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  616. return "COLD_BOOT_CAL_DONE";
  617. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  618. return "REGISTER_DRIVER";
  619. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  620. return "UNREGISTER_DRIVER";
  621. case CNSS_DRIVER_EVENT_RECOVERY:
  622. return "RECOVERY";
  623. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  624. return "FORCE_FW_ASSERT";
  625. case CNSS_DRIVER_EVENT_POWER_UP:
  626. return "POWER_UP";
  627. case CNSS_DRIVER_EVENT_POWER_DOWN:
  628. return "POWER_DOWN";
  629. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  630. return "IDLE_RESTART";
  631. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  632. return "IDLE_SHUTDOWN";
  633. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  634. return "IMS_WFC_CALL_IND";
  635. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  636. return "WLFW_TWC_CFG_IND";
  637. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  638. return "QDSS_TRACE_REQ_MEM";
  639. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  640. return "FW_MEM_FILE_SAVE";
  641. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  642. return "QDSS_TRACE_FREE";
  643. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  644. return "QDSS_TRACE_REQ_DATA";
  645. case CNSS_DRIVER_EVENT_MAX:
  646. return "EVENT_MAX";
  647. }
  648. return "UNKNOWN";
  649. };
  650. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  651. enum cnss_driver_event_type type,
  652. u32 flags, void *data)
  653. {
  654. struct cnss_driver_event *event;
  655. unsigned long irq_flags;
  656. int gfp = GFP_KERNEL;
  657. int ret = 0;
  658. if (!plat_priv)
  659. return -ENODEV;
  660. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  661. cnss_driver_event_to_str(type), type,
  662. flags ? "-sync" : "", plat_priv->driver_state, flags);
  663. if (type >= CNSS_DRIVER_EVENT_MAX) {
  664. cnss_pr_err("Invalid Event type: %d, can't post", type);
  665. return -EINVAL;
  666. }
  667. if (in_interrupt() || irqs_disabled())
  668. gfp = GFP_ATOMIC;
  669. event = kzalloc(sizeof(*event), gfp);
  670. if (!event)
  671. return -ENOMEM;
  672. cnss_pm_stay_awake(plat_priv);
  673. event->type = type;
  674. event->data = data;
  675. init_completion(&event->complete);
  676. event->ret = CNSS_EVENT_PENDING;
  677. event->sync = !!(flags & CNSS_EVENT_SYNC);
  678. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  679. list_add_tail(&event->list, &plat_priv->event_list);
  680. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  681. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  682. if (!(flags & CNSS_EVENT_SYNC))
  683. goto out;
  684. if (flags & CNSS_EVENT_UNKILLABLE)
  685. wait_for_completion(&event->complete);
  686. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  687. ret = wait_for_completion_killable(&event->complete);
  688. else
  689. ret = wait_for_completion_interruptible(&event->complete);
  690. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  691. cnss_driver_event_to_str(type), type,
  692. plat_priv->driver_state, ret, event->ret);
  693. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  694. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  695. event->sync = false;
  696. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  697. ret = -EINTR;
  698. goto out;
  699. }
  700. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  701. ret = event->ret;
  702. kfree(event);
  703. out:
  704. cnss_pm_relax(plat_priv);
  705. return ret;
  706. }
  707. /**
  708. * cnss_get_timeout - Get timeout for corresponding type.
  709. * @plat_priv: Pointer to platform driver context.
  710. * @cnss_timeout_type: Timeout type.
  711. *
  712. * Return: Timeout in milliseconds.
  713. */
  714. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  715. enum cnss_timeout_type timeout_type)
  716. {
  717. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  718. switch (timeout_type) {
  719. case CNSS_TIMEOUT_QMI:
  720. return qmi_timeout;
  721. case CNSS_TIMEOUT_POWER_UP:
  722. return (qmi_timeout << 2);
  723. case CNSS_TIMEOUT_IDLE_RESTART:
  724. /* In idle restart power up sequence, we have fw_boot_timer to
  725. * handle FW initialization failure.
  726. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  727. * account for FW dump collection and FW re-initialization on
  728. * retry.
  729. */
  730. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  731. case CNSS_TIMEOUT_CALIBRATION:
  732. /* Similar to mission mode, in CBC if FW init fails
  733. * fw recovery is tried. Thus return 2x the CBC timeout.
  734. */
  735. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  736. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  737. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  738. case CNSS_TIMEOUT_RDDM:
  739. return CNSS_RDDM_TIMEOUT_MS;
  740. case CNSS_TIMEOUT_RECOVERY:
  741. return RECOVERY_TIMEOUT;
  742. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  743. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  744. default:
  745. return qmi_timeout;
  746. }
  747. }
  748. unsigned int cnss_get_boot_timeout(struct device *dev)
  749. {
  750. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  751. if (!plat_priv) {
  752. cnss_pr_err("plat_priv is NULL\n");
  753. return 0;
  754. }
  755. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  756. }
  757. EXPORT_SYMBOL(cnss_get_boot_timeout);
  758. int cnss_power_up(struct device *dev)
  759. {
  760. int ret = 0;
  761. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  762. unsigned int timeout;
  763. if (!plat_priv) {
  764. cnss_pr_err("plat_priv is NULL\n");
  765. return -ENODEV;
  766. }
  767. cnss_pr_dbg("Powering up device\n");
  768. ret = cnss_driver_event_post(plat_priv,
  769. CNSS_DRIVER_EVENT_POWER_UP,
  770. CNSS_EVENT_SYNC, NULL);
  771. if (ret)
  772. goto out;
  773. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  774. goto out;
  775. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  776. reinit_completion(&plat_priv->power_up_complete);
  777. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  778. msecs_to_jiffies(timeout));
  779. if (!ret) {
  780. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  781. timeout);
  782. ret = -EAGAIN;
  783. goto out;
  784. }
  785. return 0;
  786. out:
  787. return ret;
  788. }
  789. EXPORT_SYMBOL(cnss_power_up);
  790. int cnss_power_down(struct device *dev)
  791. {
  792. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  793. if (!plat_priv) {
  794. cnss_pr_err("plat_priv is NULL\n");
  795. return -ENODEV;
  796. }
  797. cnss_pr_dbg("Powering down device\n");
  798. return cnss_driver_event_post(plat_priv,
  799. CNSS_DRIVER_EVENT_POWER_DOWN,
  800. CNSS_EVENT_SYNC, NULL);
  801. }
  802. EXPORT_SYMBOL(cnss_power_down);
  803. int cnss_idle_restart(struct device *dev)
  804. {
  805. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  806. unsigned int timeout;
  807. int ret = 0;
  808. if (!plat_priv) {
  809. cnss_pr_err("plat_priv is NULL\n");
  810. return -ENODEV;
  811. }
  812. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  813. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  814. return -EBUSY;
  815. }
  816. cnss_pr_dbg("Doing idle restart\n");
  817. reinit_completion(&plat_priv->power_up_complete);
  818. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  819. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  820. ret = -EINVAL;
  821. goto out;
  822. }
  823. ret = cnss_driver_event_post(plat_priv,
  824. CNSS_DRIVER_EVENT_IDLE_RESTART,
  825. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  826. if (ret)
  827. goto out;
  828. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  829. ret = cnss_bus_call_driver_probe(plat_priv);
  830. goto out;
  831. }
  832. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  833. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  834. msecs_to_jiffies(timeout));
  835. if (plat_priv->power_up_error) {
  836. ret = plat_priv->power_up_error;
  837. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  838. cnss_pr_dbg("Power up error:%d, exiting\n",
  839. plat_priv->power_up_error);
  840. goto out;
  841. }
  842. if (!ret) {
  843. /* This exception occurs after attempting retry of FW recovery.
  844. * Thus we can safely power off the device.
  845. */
  846. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  847. timeout);
  848. ret = -ETIMEDOUT;
  849. cnss_power_down(dev);
  850. CNSS_ASSERT(0);
  851. goto out;
  852. }
  853. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  854. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  855. del_timer(&plat_priv->fw_boot_timer);
  856. ret = -EINVAL;
  857. goto out;
  858. }
  859. mutex_unlock(&plat_priv->driver_ops_lock);
  860. return 0;
  861. out:
  862. mutex_unlock(&plat_priv->driver_ops_lock);
  863. return ret;
  864. }
  865. EXPORT_SYMBOL(cnss_idle_restart);
  866. int cnss_idle_shutdown(struct device *dev)
  867. {
  868. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  869. unsigned int timeout;
  870. int ret;
  871. if (!plat_priv) {
  872. cnss_pr_err("plat_priv is NULL\n");
  873. return -ENODEV;
  874. }
  875. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  876. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  877. return -EAGAIN;
  878. }
  879. cnss_pr_dbg("Doing idle shutdown\n");
  880. if (!test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) &&
  881. !test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  882. goto skip_wait;
  883. reinit_completion(&plat_priv->recovery_complete);
  884. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY);
  885. ret = wait_for_completion_timeout(&plat_priv->recovery_complete,
  886. msecs_to_jiffies(timeout));
  887. if (!ret) {
  888. cnss_pr_err("Timeout (%ums) waiting for recovery to complete\n",
  889. timeout);
  890. CNSS_ASSERT(0);
  891. }
  892. skip_wait:
  893. return cnss_driver_event_post(plat_priv,
  894. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  895. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  896. }
  897. EXPORT_SYMBOL(cnss_idle_shutdown);
  898. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  899. {
  900. int ret = 0;
  901. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  902. if (ret) {
  903. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  904. goto out;
  905. }
  906. ret = cnss_get_clk(plat_priv);
  907. if (ret) {
  908. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  909. goto put_vreg;
  910. }
  911. ret = cnss_get_pinctrl(plat_priv);
  912. if (ret) {
  913. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  914. goto put_clk;
  915. }
  916. return 0;
  917. put_clk:
  918. cnss_put_clk(plat_priv);
  919. put_vreg:
  920. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  921. out:
  922. return ret;
  923. }
  924. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  925. {
  926. cnss_put_clk(plat_priv);
  927. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  928. }
  929. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  930. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  931. unsigned long code,
  932. void *ss_handle)
  933. {
  934. struct cnss_plat_data *plat_priv =
  935. container_of(nb, struct cnss_plat_data, modem_nb);
  936. struct cnss_esoc_info *esoc_info;
  937. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  938. if (!plat_priv)
  939. return NOTIFY_DONE;
  940. esoc_info = &plat_priv->esoc_info;
  941. if (code == SUBSYS_AFTER_POWERUP)
  942. esoc_info->modem_current_status = 1;
  943. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  944. esoc_info->modem_current_status = 0;
  945. else
  946. return NOTIFY_DONE;
  947. if (!cnss_bus_call_driver_modem_status(plat_priv,
  948. esoc_info->modem_current_status))
  949. return NOTIFY_DONE;
  950. return NOTIFY_OK;
  951. }
  952. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  953. {
  954. int ret = 0;
  955. struct device *dev;
  956. struct cnss_esoc_info *esoc_info;
  957. struct esoc_desc *esoc_desc;
  958. const char *client_desc;
  959. dev = &plat_priv->plat_dev->dev;
  960. esoc_info = &plat_priv->esoc_info;
  961. esoc_info->notify_modem_status =
  962. of_property_read_bool(dev->of_node,
  963. "qcom,notify-modem-status");
  964. if (!esoc_info->notify_modem_status)
  965. goto out;
  966. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  967. &client_desc);
  968. if (ret) {
  969. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  970. } else {
  971. esoc_desc = devm_register_esoc_client(dev, client_desc);
  972. if (IS_ERR_OR_NULL(esoc_desc)) {
  973. ret = PTR_RET(esoc_desc);
  974. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  975. ret);
  976. goto out;
  977. }
  978. esoc_info->esoc_desc = esoc_desc;
  979. }
  980. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  981. esoc_info->modem_current_status = 0;
  982. esoc_info->modem_notify_handler =
  983. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  984. esoc_info->esoc_desc->name :
  985. "modem", &plat_priv->modem_nb);
  986. if (IS_ERR(esoc_info->modem_notify_handler)) {
  987. ret = PTR_ERR(esoc_info->modem_notify_handler);
  988. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  989. ret);
  990. goto unreg_esoc;
  991. }
  992. return 0;
  993. unreg_esoc:
  994. if (esoc_info->esoc_desc)
  995. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  996. out:
  997. return ret;
  998. }
  999. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1000. {
  1001. struct device *dev;
  1002. struct cnss_esoc_info *esoc_info;
  1003. dev = &plat_priv->plat_dev->dev;
  1004. esoc_info = &plat_priv->esoc_info;
  1005. if (esoc_info->notify_modem_status)
  1006. subsys_notif_unregister_notifier
  1007. (esoc_info->modem_notify_handler,
  1008. &plat_priv->modem_nb);
  1009. if (esoc_info->esoc_desc)
  1010. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1011. }
  1012. #else
  1013. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1014. {
  1015. return 0;
  1016. }
  1017. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1018. #endif
  1019. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1020. {
  1021. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1022. int ret = 0;
  1023. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1024. return 0;
  1025. enable_irq(sol_gpio->dev_sol_irq);
  1026. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1027. if (ret)
  1028. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1029. ret);
  1030. return ret;
  1031. }
  1032. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1033. {
  1034. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1035. int ret = 0;
  1036. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1037. return 0;
  1038. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1039. if (ret)
  1040. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1041. ret);
  1042. disable_irq(sol_gpio->dev_sol_irq);
  1043. return ret;
  1044. }
  1045. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1046. {
  1047. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1048. if (sol_gpio->dev_sol_gpio < 0)
  1049. return -EINVAL;
  1050. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1051. }
  1052. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1053. {
  1054. struct cnss_plat_data *plat_priv = data;
  1055. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1056. sol_gpio->dev_sol_counter++;
  1057. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u\n",
  1058. irq, sol_gpio->dev_sol_counter);
  1059. /* Make sure abort current suspend */
  1060. cnss_pm_stay_awake(plat_priv);
  1061. cnss_pm_relax(plat_priv);
  1062. pm_system_wakeup();
  1063. cnss_bus_handle_dev_sol_irq(plat_priv);
  1064. return IRQ_HANDLED;
  1065. }
  1066. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1067. {
  1068. struct device *dev = &plat_priv->plat_dev->dev;
  1069. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1070. int ret = 0;
  1071. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1072. "wlan-dev-sol-gpio", 0);
  1073. if (sol_gpio->dev_sol_gpio < 0)
  1074. goto out;
  1075. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1076. sol_gpio->dev_sol_gpio);
  1077. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1078. if (ret) {
  1079. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1080. ret);
  1081. goto out;
  1082. }
  1083. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1084. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1085. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1086. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1087. if (ret) {
  1088. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1089. goto free_gpio;
  1090. }
  1091. return 0;
  1092. free_gpio:
  1093. gpio_free(sol_gpio->dev_sol_gpio);
  1094. out:
  1095. return ret;
  1096. }
  1097. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1098. {
  1099. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1100. if (sol_gpio->dev_sol_gpio < 0)
  1101. return;
  1102. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1103. gpio_free(sol_gpio->dev_sol_gpio);
  1104. }
  1105. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1106. {
  1107. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1108. if (sol_gpio->host_sol_gpio < 0)
  1109. return -EINVAL;
  1110. if (value)
  1111. cnss_pr_dbg("Assert host SOL GPIO\n");
  1112. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1113. return 0;
  1114. }
  1115. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1116. {
  1117. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1118. if (sol_gpio->host_sol_gpio < 0)
  1119. return -EINVAL;
  1120. return gpio_get_value(sol_gpio->host_sol_gpio);
  1121. }
  1122. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1123. {
  1124. struct device *dev = &plat_priv->plat_dev->dev;
  1125. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1126. int ret = 0;
  1127. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1128. "wlan-host-sol-gpio", 0);
  1129. if (sol_gpio->host_sol_gpio < 0)
  1130. goto out;
  1131. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1132. sol_gpio->host_sol_gpio);
  1133. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1134. if (ret) {
  1135. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1136. ret);
  1137. goto out;
  1138. }
  1139. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1140. return 0;
  1141. out:
  1142. return ret;
  1143. }
  1144. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1145. {
  1146. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1147. if (sol_gpio->host_sol_gpio < 0)
  1148. return;
  1149. gpio_free(sol_gpio->host_sol_gpio);
  1150. }
  1151. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1152. {
  1153. int ret;
  1154. ret = cnss_init_dev_sol_gpio(plat_priv);
  1155. if (ret)
  1156. goto out;
  1157. ret = cnss_init_host_sol_gpio(plat_priv);
  1158. if (ret)
  1159. goto deinit_dev_sol;
  1160. return 0;
  1161. deinit_dev_sol:
  1162. cnss_deinit_dev_sol_gpio(plat_priv);
  1163. out:
  1164. return ret;
  1165. }
  1166. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1167. {
  1168. cnss_deinit_host_sol_gpio(plat_priv);
  1169. cnss_deinit_dev_sol_gpio(plat_priv);
  1170. }
  1171. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1172. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1173. {
  1174. struct cnss_plat_data *plat_priv;
  1175. int ret = 0;
  1176. if (!subsys_desc->dev) {
  1177. cnss_pr_err("dev from subsys_desc is NULL\n");
  1178. return -ENODEV;
  1179. }
  1180. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1181. if (!plat_priv) {
  1182. cnss_pr_err("plat_priv is NULL\n");
  1183. return -ENODEV;
  1184. }
  1185. if (!plat_priv->driver_state) {
  1186. cnss_pr_dbg("Powerup is ignored\n");
  1187. return 0;
  1188. }
  1189. ret = cnss_bus_dev_powerup(plat_priv);
  1190. if (ret)
  1191. __pm_relax(plat_priv->recovery_ws);
  1192. return ret;
  1193. }
  1194. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1195. bool force_stop)
  1196. {
  1197. struct cnss_plat_data *plat_priv;
  1198. if (!subsys_desc->dev) {
  1199. cnss_pr_err("dev from subsys_desc is NULL\n");
  1200. return -ENODEV;
  1201. }
  1202. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1203. if (!plat_priv) {
  1204. cnss_pr_err("plat_priv is NULL\n");
  1205. return -ENODEV;
  1206. }
  1207. if (!plat_priv->driver_state) {
  1208. cnss_pr_dbg("shutdown is ignored\n");
  1209. return 0;
  1210. }
  1211. return cnss_bus_dev_shutdown(plat_priv);
  1212. }
  1213. void cnss_device_crashed(struct device *dev)
  1214. {
  1215. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1216. struct cnss_subsys_info *subsys_info;
  1217. if (!plat_priv)
  1218. return;
  1219. subsys_info = &plat_priv->subsys_info;
  1220. if (subsys_info->subsys_device) {
  1221. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1222. subsys_set_crash_status(subsys_info->subsys_device, true);
  1223. subsystem_restart_dev(subsys_info->subsys_device);
  1224. }
  1225. }
  1226. EXPORT_SYMBOL(cnss_device_crashed);
  1227. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1228. {
  1229. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1230. if (!plat_priv) {
  1231. cnss_pr_err("plat_priv is NULL\n");
  1232. return;
  1233. }
  1234. cnss_bus_dev_crash_shutdown(plat_priv);
  1235. }
  1236. static int cnss_subsys_ramdump(int enable,
  1237. const struct subsys_desc *subsys_desc)
  1238. {
  1239. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1240. if (!plat_priv) {
  1241. cnss_pr_err("plat_priv is NULL\n");
  1242. return -ENODEV;
  1243. }
  1244. if (!enable)
  1245. return 0;
  1246. return cnss_bus_dev_ramdump(plat_priv);
  1247. }
  1248. static void cnss_recovery_work_handler(struct work_struct *work)
  1249. {
  1250. }
  1251. #else
  1252. static void cnss_recovery_work_handler(struct work_struct *work)
  1253. {
  1254. int ret;
  1255. struct cnss_plat_data *plat_priv =
  1256. container_of(work, struct cnss_plat_data, recovery_work);
  1257. if (!plat_priv->recovery_enabled)
  1258. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1259. cnss_bus_dev_shutdown(plat_priv);
  1260. cnss_bus_dev_ramdump(plat_priv);
  1261. msleep(POWER_RESET_MIN_DELAY_MS);
  1262. ret = cnss_bus_dev_powerup(plat_priv);
  1263. if (ret)
  1264. __pm_relax(plat_priv->recovery_ws);
  1265. return;
  1266. }
  1267. void cnss_device_crashed(struct device *dev)
  1268. {
  1269. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1270. if (!plat_priv)
  1271. return;
  1272. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1273. schedule_work(&plat_priv->recovery_work);
  1274. }
  1275. EXPORT_SYMBOL(cnss_device_crashed);
  1276. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1277. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1278. {
  1279. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1280. struct cnss_ramdump_info *ramdump_info;
  1281. if (!plat_priv)
  1282. return NULL;
  1283. ramdump_info = &plat_priv->ramdump_info;
  1284. *size = ramdump_info->ramdump_size;
  1285. return ramdump_info->ramdump_va;
  1286. }
  1287. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1288. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1289. {
  1290. switch (reason) {
  1291. case CNSS_REASON_DEFAULT:
  1292. return "DEFAULT";
  1293. case CNSS_REASON_LINK_DOWN:
  1294. return "LINK_DOWN";
  1295. case CNSS_REASON_RDDM:
  1296. return "RDDM";
  1297. case CNSS_REASON_TIMEOUT:
  1298. return "TIMEOUT";
  1299. }
  1300. return "UNKNOWN";
  1301. };
  1302. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1303. enum cnss_recovery_reason reason)
  1304. {
  1305. plat_priv->recovery_count++;
  1306. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1307. goto self_recovery;
  1308. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1309. cnss_pr_dbg("Skip device recovery\n");
  1310. return 0;
  1311. }
  1312. /* FW recovery sequence has multiple steps and firmware load requires
  1313. * linux PM in awake state. Thus hold the cnss wake source until
  1314. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1315. * time taken in this process.
  1316. */
  1317. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1318. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1319. true);
  1320. switch (reason) {
  1321. case CNSS_REASON_LINK_DOWN:
  1322. if (!cnss_bus_check_link_status(plat_priv)) {
  1323. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1324. return 0;
  1325. }
  1326. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1327. &plat_priv->ctrl_params.quirks))
  1328. goto self_recovery;
  1329. if (!cnss_bus_recover_link_down(plat_priv)) {
  1330. /* clear recovery bit here to avoid skipping
  1331. * the recovery work for RDDM later
  1332. */
  1333. clear_bit(CNSS_DRIVER_RECOVERY,
  1334. &plat_priv->driver_state);
  1335. return 0;
  1336. }
  1337. break;
  1338. case CNSS_REASON_RDDM:
  1339. cnss_bus_collect_dump_info(plat_priv, false);
  1340. break;
  1341. case CNSS_REASON_DEFAULT:
  1342. case CNSS_REASON_TIMEOUT:
  1343. break;
  1344. default:
  1345. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1346. cnss_recovery_reason_to_str(reason), reason);
  1347. break;
  1348. }
  1349. cnss_bus_device_crashed(plat_priv);
  1350. return 0;
  1351. self_recovery:
  1352. cnss_pr_dbg("Going for self recovery\n");
  1353. cnss_bus_dev_shutdown(plat_priv);
  1354. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1355. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1356. &plat_priv->ctrl_params.quirks);
  1357. cnss_bus_dev_powerup(plat_priv);
  1358. return 0;
  1359. }
  1360. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1361. void *data)
  1362. {
  1363. struct cnss_recovery_data *recovery_data = data;
  1364. int ret = 0;
  1365. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1366. cnss_recovery_reason_to_str(recovery_data->reason),
  1367. recovery_data->reason);
  1368. if (!plat_priv->driver_state) {
  1369. cnss_pr_err("Improper driver state, ignore recovery\n");
  1370. ret = -EINVAL;
  1371. goto out;
  1372. }
  1373. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1374. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1375. ret = -EINVAL;
  1376. goto out;
  1377. }
  1378. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1379. cnss_pr_err("Recovery is already in progress\n");
  1380. CNSS_ASSERT(0);
  1381. ret = -EINVAL;
  1382. goto out;
  1383. }
  1384. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1385. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1386. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1387. ret = -EINVAL;
  1388. goto out;
  1389. }
  1390. switch (plat_priv->device_id) {
  1391. case QCA6174_DEVICE_ID:
  1392. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1393. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1394. &plat_priv->driver_state)) {
  1395. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1396. ret = -EINVAL;
  1397. goto out;
  1398. }
  1399. break;
  1400. default:
  1401. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1402. set_bit(CNSS_FW_BOOT_RECOVERY,
  1403. &plat_priv->driver_state);
  1404. }
  1405. break;
  1406. }
  1407. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1408. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1409. out:
  1410. kfree(data);
  1411. return ret;
  1412. }
  1413. int cnss_self_recovery(struct device *dev,
  1414. enum cnss_recovery_reason reason)
  1415. {
  1416. cnss_schedule_recovery(dev, reason);
  1417. return 0;
  1418. }
  1419. EXPORT_SYMBOL(cnss_self_recovery);
  1420. void cnss_schedule_recovery(struct device *dev,
  1421. enum cnss_recovery_reason reason)
  1422. {
  1423. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1424. struct cnss_recovery_data *data;
  1425. int gfp = GFP_KERNEL;
  1426. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1427. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1428. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1429. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1430. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1431. return;
  1432. }
  1433. if (in_interrupt() || irqs_disabled())
  1434. gfp = GFP_ATOMIC;
  1435. data = kzalloc(sizeof(*data), gfp);
  1436. if (!data)
  1437. return;
  1438. data->reason = reason;
  1439. cnss_driver_event_post(plat_priv,
  1440. CNSS_DRIVER_EVENT_RECOVERY,
  1441. 0, data);
  1442. }
  1443. EXPORT_SYMBOL(cnss_schedule_recovery);
  1444. int cnss_force_fw_assert(struct device *dev)
  1445. {
  1446. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1447. if (!plat_priv) {
  1448. cnss_pr_err("plat_priv is NULL\n");
  1449. return -ENODEV;
  1450. }
  1451. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1452. cnss_pr_info("Forced FW assert is not supported\n");
  1453. return -EOPNOTSUPP;
  1454. }
  1455. if (cnss_bus_is_device_down(plat_priv)) {
  1456. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1457. return 0;
  1458. }
  1459. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1460. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1461. return 0;
  1462. }
  1463. if (in_interrupt() || irqs_disabled())
  1464. cnss_driver_event_post(plat_priv,
  1465. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1466. 0, NULL);
  1467. else
  1468. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1469. return 0;
  1470. }
  1471. EXPORT_SYMBOL(cnss_force_fw_assert);
  1472. int cnss_force_collect_rddm(struct device *dev)
  1473. {
  1474. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1475. unsigned int timeout;
  1476. int ret = 0;
  1477. if (!plat_priv) {
  1478. cnss_pr_err("plat_priv is NULL\n");
  1479. return -ENODEV;
  1480. }
  1481. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1482. cnss_pr_info("Force collect rddm is not supported\n");
  1483. return -EOPNOTSUPP;
  1484. }
  1485. if (cnss_bus_is_device_down(plat_priv)) {
  1486. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1487. goto wait_rddm;
  1488. }
  1489. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1490. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1491. goto wait_rddm;
  1492. }
  1493. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1494. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1495. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1496. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1497. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1498. return 0;
  1499. }
  1500. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1501. if (ret)
  1502. return ret;
  1503. wait_rddm:
  1504. reinit_completion(&plat_priv->rddm_complete);
  1505. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  1506. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  1507. msecs_to_jiffies(timeout));
  1508. if (!ret) {
  1509. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  1510. timeout);
  1511. ret = -ETIMEDOUT;
  1512. } else if (ret > 0) {
  1513. ret = 0;
  1514. }
  1515. return ret;
  1516. }
  1517. EXPORT_SYMBOL(cnss_force_collect_rddm);
  1518. int cnss_qmi_send_get(struct device *dev)
  1519. {
  1520. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1521. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1522. return 0;
  1523. return cnss_bus_qmi_send_get(plat_priv);
  1524. }
  1525. EXPORT_SYMBOL(cnss_qmi_send_get);
  1526. int cnss_qmi_send_put(struct device *dev)
  1527. {
  1528. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1529. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1530. return 0;
  1531. return cnss_bus_qmi_send_put(plat_priv);
  1532. }
  1533. EXPORT_SYMBOL(cnss_qmi_send_put);
  1534. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  1535. int cmd_len, void *cb_ctx,
  1536. int (*cb)(void *ctx, void *event, int event_len))
  1537. {
  1538. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1539. int ret;
  1540. if (!plat_priv)
  1541. return -ENODEV;
  1542. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1543. return -EINVAL;
  1544. plat_priv->get_info_cb = cb;
  1545. plat_priv->get_info_cb_ctx = cb_ctx;
  1546. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  1547. if (ret) {
  1548. plat_priv->get_info_cb = NULL;
  1549. plat_priv->get_info_cb_ctx = NULL;
  1550. }
  1551. return ret;
  1552. }
  1553. EXPORT_SYMBOL(cnss_qmi_send);
  1554. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  1555. {
  1556. int ret = 0;
  1557. u32 retry = 0, timeout;
  1558. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  1559. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  1560. goto out;
  1561. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1562. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  1563. goto out;
  1564. }
  1565. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1566. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  1567. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1568. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  1569. CNSS_ASSERT(0);
  1570. return -EINVAL;
  1571. }
  1572. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1573. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  1574. break;
  1575. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  1576. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1577. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  1578. CNSS_ASSERT(0);
  1579. ret = -EINVAL;
  1580. goto mark_cal_fail;
  1581. }
  1582. }
  1583. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1584. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  1585. timeout = cnss_get_timeout(plat_priv,
  1586. CNSS_TIMEOUT_CALIBRATION);
  1587. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  1588. timeout / 1000);
  1589. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1590. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1591. msecs_to_jiffies(timeout));
  1592. }
  1593. reinit_completion(&plat_priv->cal_complete);
  1594. ret = cnss_bus_dev_powerup(plat_priv);
  1595. mark_cal_fail:
  1596. if (ret) {
  1597. complete(&plat_priv->cal_complete);
  1598. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1599. /* Set CBC done in driver state to mark attempt and note error
  1600. * since calibration cannot be retried at boot.
  1601. */
  1602. plat_priv->cal_done = CNSS_CAL_FAILURE;
  1603. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1604. }
  1605. out:
  1606. return ret;
  1607. }
  1608. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  1609. void *data)
  1610. {
  1611. struct cnss_cal_info *cal_info = data;
  1612. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  1613. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  1614. goto out;
  1615. switch (cal_info->cal_status) {
  1616. case CNSS_CAL_DONE:
  1617. cnss_pr_dbg("Calibration completed successfully\n");
  1618. plat_priv->cal_done = true;
  1619. break;
  1620. case CNSS_CAL_TIMEOUT:
  1621. case CNSS_CAL_FAILURE:
  1622. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  1623. cal_info->cal_status);
  1624. break;
  1625. default:
  1626. cnss_pr_err("Unknown calibration status: %u\n",
  1627. cal_info->cal_status);
  1628. break;
  1629. }
  1630. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  1631. cnss_bus_free_qdss_mem(plat_priv);
  1632. cnss_release_antenna_sharing(plat_priv);
  1633. cnss_bus_dev_shutdown(plat_priv);
  1634. msleep(POWER_RESET_MIN_DELAY_MS);
  1635. complete(&plat_priv->cal_complete);
  1636. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1637. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1638. if (cal_info->cal_status == CNSS_CAL_DONE) {
  1639. cnss_cal_mem_upload_to_file(plat_priv);
  1640. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  1641. goto out;
  1642. cnss_pr_dbg("Schedule WLAN driver load\n");
  1643. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1644. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1645. 0);
  1646. }
  1647. out:
  1648. kfree(data);
  1649. return 0;
  1650. }
  1651. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  1652. {
  1653. int ret;
  1654. ret = cnss_bus_dev_powerup(plat_priv);
  1655. if (ret)
  1656. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1657. return ret;
  1658. }
  1659. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  1660. {
  1661. cnss_bus_dev_shutdown(plat_priv);
  1662. return 0;
  1663. }
  1664. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  1665. {
  1666. int ret = 0;
  1667. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  1668. if (ret < 0)
  1669. return ret;
  1670. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  1671. }
  1672. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  1673. u32 mem_seg_len, u64 pa, u32 size)
  1674. {
  1675. int i = 0;
  1676. u64 offset = 0;
  1677. void *va = NULL;
  1678. u64 local_pa;
  1679. u32 local_size;
  1680. for (i = 0; i < mem_seg_len; i++) {
  1681. local_pa = (u64)fw_mem[i].pa;
  1682. local_size = (u32)fw_mem[i].size;
  1683. if (pa == local_pa && size <= local_size) {
  1684. va = fw_mem[i].va;
  1685. break;
  1686. }
  1687. if (pa > local_pa &&
  1688. pa < local_pa + local_size &&
  1689. pa + size <= local_pa + local_size) {
  1690. offset = pa - local_pa;
  1691. va = fw_mem[i].va + offset;
  1692. break;
  1693. }
  1694. }
  1695. return va;
  1696. }
  1697. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  1698. void *data)
  1699. {
  1700. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1701. struct cnss_fw_mem *fw_mem_seg;
  1702. int ret = 0L;
  1703. void *va = NULL;
  1704. u32 i, fw_mem_seg_len;
  1705. switch (event_data->mem_type) {
  1706. case QMI_WLFW_MEM_TYPE_DDR_V01:
  1707. if (!plat_priv->fw_mem_seg_len)
  1708. goto invalid_mem_save;
  1709. fw_mem_seg = plat_priv->fw_mem;
  1710. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  1711. break;
  1712. case QMI_WLFW_MEM_QDSS_V01:
  1713. if (!plat_priv->qdss_mem_seg_len)
  1714. goto invalid_mem_save;
  1715. fw_mem_seg = plat_priv->qdss_mem;
  1716. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  1717. break;
  1718. default:
  1719. goto invalid_mem_save;
  1720. }
  1721. for (i = 0; i < event_data->mem_seg_len; i++) {
  1722. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  1723. event_data->mem_seg[i].addr,
  1724. event_data->mem_seg[i].size);
  1725. if (!va) {
  1726. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  1727. &event_data->mem_seg[i].addr,
  1728. event_data->mem_type);
  1729. ret = -EINVAL;
  1730. break;
  1731. }
  1732. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  1733. event_data->file_name,
  1734. event_data->mem_seg[i].size);
  1735. if (ret < 0) {
  1736. cnss_pr_err("Fail to save fw mem data: %d\n",
  1737. ret);
  1738. break;
  1739. }
  1740. }
  1741. kfree(data);
  1742. return ret;
  1743. invalid_mem_save:
  1744. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  1745. event_data->mem_type);
  1746. kfree(data);
  1747. return -EINVAL;
  1748. }
  1749. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  1750. {
  1751. cnss_bus_free_qdss_mem(plat_priv);
  1752. return 0;
  1753. }
  1754. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  1755. void *data)
  1756. {
  1757. int ret = 0;
  1758. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1759. if (!plat_priv)
  1760. return -ENODEV;
  1761. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  1762. event_data->total_size);
  1763. kfree(data);
  1764. return ret;
  1765. }
  1766. static void cnss_driver_event_work(struct work_struct *work)
  1767. {
  1768. struct cnss_plat_data *plat_priv =
  1769. container_of(work, struct cnss_plat_data, event_work);
  1770. struct cnss_driver_event *event;
  1771. unsigned long flags;
  1772. int ret = 0;
  1773. if (!plat_priv) {
  1774. cnss_pr_err("plat_priv is NULL!\n");
  1775. return;
  1776. }
  1777. cnss_pm_stay_awake(plat_priv);
  1778. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1779. while (!list_empty(&plat_priv->event_list)) {
  1780. event = list_first_entry(&plat_priv->event_list,
  1781. struct cnss_driver_event, list);
  1782. list_del(&event->list);
  1783. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1784. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  1785. cnss_driver_event_to_str(event->type),
  1786. event->sync ? "-sync" : "", event->type,
  1787. plat_priv->driver_state);
  1788. switch (event->type) {
  1789. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1790. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  1791. break;
  1792. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1793. ret = cnss_wlfw_server_exit(plat_priv);
  1794. break;
  1795. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1796. ret = cnss_bus_alloc_fw_mem(plat_priv);
  1797. if (ret)
  1798. break;
  1799. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  1800. break;
  1801. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1802. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  1803. break;
  1804. case CNSS_DRIVER_EVENT_FW_READY:
  1805. ret = cnss_fw_ready_hdlr(plat_priv);
  1806. break;
  1807. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1808. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  1809. break;
  1810. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1811. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  1812. event->data);
  1813. break;
  1814. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1815. ret = cnss_bus_register_driver_hdlr(plat_priv,
  1816. event->data);
  1817. break;
  1818. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1819. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  1820. break;
  1821. case CNSS_DRIVER_EVENT_RECOVERY:
  1822. ret = cnss_driver_recovery_hdlr(plat_priv,
  1823. event->data);
  1824. break;
  1825. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1826. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1827. break;
  1828. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1829. set_bit(CNSS_DRIVER_IDLE_RESTART,
  1830. &plat_priv->driver_state);
  1831. /* fall through */
  1832. case CNSS_DRIVER_EVENT_POWER_UP:
  1833. ret = cnss_power_up_hdlr(plat_priv);
  1834. break;
  1835. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1836. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  1837. &plat_priv->driver_state);
  1838. /* fall through */
  1839. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1840. ret = cnss_power_down_hdlr(plat_priv);
  1841. break;
  1842. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1843. ret = cnss_process_wfc_call_ind_event(plat_priv,
  1844. event->data);
  1845. break;
  1846. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1847. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  1848. event->data);
  1849. break;
  1850. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1851. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  1852. break;
  1853. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1854. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  1855. event->data);
  1856. break;
  1857. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1858. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  1859. break;
  1860. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1861. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  1862. event->data);
  1863. break;
  1864. default:
  1865. cnss_pr_err("Invalid driver event type: %d",
  1866. event->type);
  1867. kfree(event);
  1868. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1869. continue;
  1870. }
  1871. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1872. if (event->sync) {
  1873. event->ret = ret;
  1874. complete(&event->complete);
  1875. continue;
  1876. }
  1877. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1878. kfree(event);
  1879. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1880. }
  1881. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1882. cnss_pm_relax(plat_priv);
  1883. }
  1884. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1885. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  1886. {
  1887. int ret = 0;
  1888. struct cnss_subsys_info *subsys_info;
  1889. subsys_info = &plat_priv->subsys_info;
  1890. subsys_info->subsys_desc.name = "wlan";
  1891. subsys_info->subsys_desc.owner = THIS_MODULE;
  1892. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  1893. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  1894. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  1895. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  1896. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  1897. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  1898. if (IS_ERR(subsys_info->subsys_device)) {
  1899. ret = PTR_ERR(subsys_info->subsys_device);
  1900. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  1901. goto out;
  1902. }
  1903. subsys_info->subsys_handle =
  1904. subsystem_get(subsys_info->subsys_desc.name);
  1905. if (!subsys_info->subsys_handle) {
  1906. cnss_pr_err("Failed to get subsys_handle!\n");
  1907. ret = -EINVAL;
  1908. goto unregister_subsys;
  1909. } else if (IS_ERR(subsys_info->subsys_handle)) {
  1910. ret = PTR_ERR(subsys_info->subsys_handle);
  1911. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  1912. goto unregister_subsys;
  1913. }
  1914. return 0;
  1915. unregister_subsys:
  1916. subsys_unregister(subsys_info->subsys_device);
  1917. out:
  1918. return ret;
  1919. }
  1920. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  1921. {
  1922. struct cnss_subsys_info *subsys_info;
  1923. subsys_info = &plat_priv->subsys_info;
  1924. subsystem_put(subsys_info->subsys_handle);
  1925. subsys_unregister(subsys_info->subsys_device);
  1926. }
  1927. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  1928. {
  1929. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  1930. return create_ramdump_device(subsys_info->subsys_desc.name,
  1931. subsys_info->subsys_desc.dev);
  1932. }
  1933. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  1934. void *ramdump_dev)
  1935. {
  1936. destroy_ramdump_device(ramdump_dev);
  1937. }
  1938. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  1939. {
  1940. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  1941. struct ramdump_segment segment;
  1942. memset(&segment, 0, sizeof(segment));
  1943. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  1944. segment.size = ramdump_info->ramdump_size;
  1945. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  1946. }
  1947. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  1948. {
  1949. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  1950. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  1951. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  1952. struct ramdump_segment *ramdump_segs, *s;
  1953. struct cnss_dump_meta_info meta_info = {0};
  1954. int i, ret = 0;
  1955. ramdump_segs = kcalloc(dump_data->nentries + 1,
  1956. sizeof(*ramdump_segs),
  1957. GFP_KERNEL);
  1958. if (!ramdump_segs)
  1959. return -ENOMEM;
  1960. s = ramdump_segs + 1;
  1961. for (i = 0; i < dump_data->nentries; i++) {
  1962. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  1963. cnss_pr_err("Unsupported dump type: %d",
  1964. dump_seg->type);
  1965. continue;
  1966. }
  1967. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  1968. meta_info.entry[dump_seg->type].type = dump_seg->type;
  1969. meta_info.entry[dump_seg->type].entry_start = i + 1;
  1970. }
  1971. meta_info.entry[dump_seg->type].entry_num++;
  1972. s->address = dump_seg->address;
  1973. s->v_address = (void __iomem *)dump_seg->v_address;
  1974. s->size = dump_seg->size;
  1975. s++;
  1976. dump_seg++;
  1977. }
  1978. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  1979. meta_info.version = CNSS_RAMDUMP_VERSION;
  1980. meta_info.chipset = plat_priv->device_id;
  1981. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  1982. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  1983. ramdump_segs->size = sizeof(meta_info);
  1984. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  1985. dump_data->nentries + 1);
  1986. kfree(ramdump_segs);
  1987. return ret;
  1988. }
  1989. #else
  1990. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  1991. void *data)
  1992. {
  1993. struct cnss_plat_data *plat_priv =
  1994. container_of(nb, struct cnss_plat_data, panic_nb);
  1995. cnss_bus_dev_crash_shutdown(plat_priv);
  1996. return NOTIFY_DONE;
  1997. }
  1998. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  1999. {
  2000. int ret;
  2001. if (!plat_priv)
  2002. return -ENODEV;
  2003. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2004. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2005. &plat_priv->panic_nb);
  2006. if (ret) {
  2007. cnss_pr_err("Failed to register panic handler\n");
  2008. return -EINVAL;
  2009. }
  2010. return 0;
  2011. }
  2012. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2013. {
  2014. int ret;
  2015. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2016. &plat_priv->panic_nb);
  2017. if (ret)
  2018. cnss_pr_err("Failed to unregister panic handler\n");
  2019. }
  2020. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2021. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2022. {
  2023. return &plat_priv->plat_dev->dev;
  2024. }
  2025. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2026. void *ramdump_dev)
  2027. {
  2028. }
  2029. #endif
  2030. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2031. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2032. {
  2033. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2034. struct qcom_dump_segment segment;
  2035. struct list_head head;
  2036. INIT_LIST_HEAD(&head);
  2037. memset(&segment, 0, sizeof(segment));
  2038. segment.va = ramdump_info->ramdump_va;
  2039. segment.size = ramdump_info->ramdump_size;
  2040. list_add(&segment.node, &head);
  2041. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2042. }
  2043. #else
  2044. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2045. {
  2046. return 0;
  2047. }
  2048. /* Using completion event inside dynamically allocated ramdump_desc
  2049. * may result a race between freeing the event after setting it to
  2050. * complete inside dev coredump free callback and the thread that is
  2051. * waiting for completion.
  2052. */
  2053. DECLARE_COMPLETION(dump_done);
  2054. #define TIMEOUT_SAVE_DUMP_MS 30000
  2055. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2056. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2057. { \
  2058. if (class == ELFCLASS32) \
  2059. return sizeof(struct elf32_##__xhdr); \
  2060. else \
  2061. return sizeof(struct elf64_##__xhdr); \
  2062. }
  2063. SIZEOF_ELF_STRUCT(phdr)
  2064. SIZEOF_ELF_STRUCT(hdr)
  2065. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2066. do { \
  2067. if (class == ELFCLASS32) \
  2068. ((struct elf32_##__xhdr *)arg)->member = value; \
  2069. else \
  2070. ((struct elf64_##__xhdr *)arg)->member = value; \
  2071. } while (0)
  2072. #define set_ehdr_property(arg, class, member, value) \
  2073. set_xhdr_property(hdr, arg, class, member, value)
  2074. #define set_phdr_property(arg, class, member, value) \
  2075. set_xhdr_property(phdr, arg, class, member, value)
  2076. /* These replace qcom_ramdump driver APIs called from common API
  2077. * cnss_do_elf_dump() by the ones defined here.
  2078. */
  2079. #define qcom_dump_segment cnss_qcom_dump_segment
  2080. #define qcom_elf_dump cnss_qcom_elf_dump
  2081. #define dump_enabled cnss_dump_enabled
  2082. struct cnss_qcom_dump_segment {
  2083. struct list_head node;
  2084. dma_addr_t da;
  2085. void *va;
  2086. size_t size;
  2087. };
  2088. struct cnss_qcom_ramdump_desc {
  2089. void *data;
  2090. struct completion dump_done;
  2091. };
  2092. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2093. void *data, size_t datalen)
  2094. {
  2095. struct cnss_qcom_ramdump_desc *desc = data;
  2096. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2097. datalen);
  2098. }
  2099. static void cnss_qcom_devcd_freev(void *data)
  2100. {
  2101. struct cnss_qcom_ramdump_desc *desc = data;
  2102. cnss_pr_dbg("Free dump data for dev coredump\n");
  2103. complete(&dump_done);
  2104. vfree(desc->data);
  2105. kfree(desc);
  2106. }
  2107. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2108. gfp_t gfp)
  2109. {
  2110. struct cnss_qcom_ramdump_desc *desc;
  2111. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2112. int ret;
  2113. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2114. if (!desc)
  2115. return -ENOMEM;
  2116. desc->data = data;
  2117. reinit_completion(&dump_done);
  2118. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2119. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2120. ret = wait_for_completion_timeout(&dump_done,
  2121. msecs_to_jiffies(timeout));
  2122. if (!ret)
  2123. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2124. timeout);
  2125. return ret ? 0 : -ETIMEDOUT;
  2126. }
  2127. /* Since the elf32 and elf64 identification is identical apart from
  2128. * the class, use elf32 by default.
  2129. */
  2130. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2131. {
  2132. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2133. ehdr->e_ident[EI_CLASS] = class;
  2134. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2135. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2136. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2137. }
  2138. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2139. unsigned char class)
  2140. {
  2141. struct cnss_qcom_dump_segment *segment;
  2142. void *phdr, *ehdr;
  2143. size_t data_size, offset;
  2144. int phnum = 0;
  2145. void *data;
  2146. void __iomem *ptr;
  2147. if (!segs || list_empty(segs))
  2148. return -EINVAL;
  2149. data_size = sizeof_elf_hdr(class);
  2150. list_for_each_entry(segment, segs, node) {
  2151. data_size += sizeof_elf_phdr(class) + segment->size;
  2152. phnum++;
  2153. }
  2154. data = vmalloc(data_size);
  2155. if (!data)
  2156. return -ENOMEM;
  2157. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2158. ehdr = data;
  2159. memset(ehdr, 0, sizeof_elf_hdr(class));
  2160. init_elf_identification(ehdr, class);
  2161. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2162. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2163. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2164. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2165. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2166. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2167. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2168. phdr = data + sizeof_elf_hdr(class);
  2169. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2170. list_for_each_entry(segment, segs, node) {
  2171. memset(phdr, 0, sizeof_elf_phdr(class));
  2172. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2173. set_phdr_property(phdr, class, p_offset, offset);
  2174. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2175. set_phdr_property(phdr, class, p_paddr, segment->da);
  2176. set_phdr_property(phdr, class, p_filesz, segment->size);
  2177. set_phdr_property(phdr, class, p_memsz, segment->size);
  2178. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2179. set_phdr_property(phdr, class, p_align, 0);
  2180. if (segment->va) {
  2181. memcpy(data + offset, segment->va, segment->size);
  2182. } else {
  2183. ptr = devm_ioremap(dev, segment->da, segment->size);
  2184. if (!ptr) {
  2185. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2186. &segment->da, segment->size);
  2187. memset(data + offset, 0xff, segment->size);
  2188. } else {
  2189. memcpy_fromio(data + offset, ptr,
  2190. segment->size);
  2191. }
  2192. }
  2193. offset += segment->size;
  2194. phdr += sizeof_elf_phdr(class);
  2195. }
  2196. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2197. }
  2198. /* Saving dump to file system is always needed in this case. */
  2199. static bool cnss_dump_enabled(void)
  2200. {
  2201. return true;
  2202. }
  2203. #endif /* CONFIG_QCOM_RAMDUMP */
  2204. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2205. {
  2206. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2207. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2208. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2209. struct qcom_dump_segment *seg;
  2210. struct cnss_dump_meta_info meta_info = {0};
  2211. struct list_head head;
  2212. int i, ret = 0;
  2213. if (!dump_enabled()) {
  2214. cnss_pr_info("Dump collection is not enabled\n");
  2215. return ret;
  2216. }
  2217. INIT_LIST_HEAD(&head);
  2218. for (i = 0; i < dump_data->nentries; i++) {
  2219. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2220. cnss_pr_err("Unsupported dump type: %d",
  2221. dump_seg->type);
  2222. continue;
  2223. }
  2224. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2225. if (!seg)
  2226. continue;
  2227. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2228. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2229. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2230. }
  2231. meta_info.entry[dump_seg->type].entry_num++;
  2232. seg->da = dump_seg->address;
  2233. seg->va = dump_seg->v_address;
  2234. seg->size = dump_seg->size;
  2235. list_add_tail(&seg->node, &head);
  2236. dump_seg++;
  2237. }
  2238. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2239. if (!seg)
  2240. goto do_elf_dump;
  2241. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2242. meta_info.version = CNSS_RAMDUMP_VERSION;
  2243. meta_info.chipset = plat_priv->device_id;
  2244. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2245. seg->va = &meta_info;
  2246. seg->size = sizeof(meta_info);
  2247. list_add(&seg->node, &head);
  2248. do_elf_dump:
  2249. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2250. while (!list_empty(&head)) {
  2251. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2252. list_del(&seg->node);
  2253. kfree(seg);
  2254. }
  2255. return ret;
  2256. }
  2257. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  2258. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2259. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  2260. {
  2261. struct cnss_ramdump_info *ramdump_info;
  2262. struct msm_dump_entry dump_entry;
  2263. ramdump_info = &plat_priv->ramdump_info;
  2264. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  2265. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  2266. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  2267. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  2268. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  2269. sizeof(ramdump_info->dump_data.name));
  2270. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2271. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  2272. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2273. &dump_entry);
  2274. }
  2275. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  2276. {
  2277. int ret = 0;
  2278. struct device *dev;
  2279. struct cnss_ramdump_info *ramdump_info;
  2280. u32 ramdump_size = 0;
  2281. dev = &plat_priv->plat_dev->dev;
  2282. ramdump_info = &plat_priv->ramdump_info;
  2283. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2284. &ramdump_size) == 0) {
  2285. ramdump_info->ramdump_va =
  2286. dma_alloc_coherent(dev, ramdump_size,
  2287. &ramdump_info->ramdump_pa,
  2288. GFP_KERNEL);
  2289. if (ramdump_info->ramdump_va)
  2290. ramdump_info->ramdump_size = ramdump_size;
  2291. }
  2292. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  2293. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  2294. if (ramdump_info->ramdump_size == 0) {
  2295. cnss_pr_info("Ramdump will not be collected");
  2296. goto out;
  2297. }
  2298. ret = cnss_init_dump_entry(plat_priv);
  2299. if (ret) {
  2300. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  2301. goto free_ramdump;
  2302. }
  2303. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2304. if (!ramdump_info->ramdump_dev) {
  2305. cnss_pr_err("Failed to create ramdump device!");
  2306. ret = -ENOMEM;
  2307. goto free_ramdump;
  2308. }
  2309. return 0;
  2310. free_ramdump:
  2311. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2312. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  2313. out:
  2314. return ret;
  2315. }
  2316. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  2317. {
  2318. struct device *dev;
  2319. struct cnss_ramdump_info *ramdump_info;
  2320. dev = &plat_priv->plat_dev->dev;
  2321. ramdump_info = &plat_priv->ramdump_info;
  2322. if (ramdump_info->ramdump_dev)
  2323. cnss_destroy_ramdump_device(plat_priv,
  2324. ramdump_info->ramdump_dev);
  2325. if (ramdump_info->ramdump_va)
  2326. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2327. ramdump_info->ramdump_va,
  2328. ramdump_info->ramdump_pa);
  2329. }
  2330. /**
  2331. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  2332. * @ret: Error returned by msm_dump_data_register_nominidump
  2333. *
  2334. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  2335. * ignore failure.
  2336. *
  2337. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  2338. */
  2339. static int cnss_ignore_dump_data_reg_fail(int ret)
  2340. {
  2341. return ret;
  2342. }
  2343. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  2344. {
  2345. int ret = 0;
  2346. struct cnss_ramdump_info_v2 *info_v2;
  2347. struct cnss_dump_data *dump_data;
  2348. struct msm_dump_entry dump_entry;
  2349. struct device *dev = &plat_priv->plat_dev->dev;
  2350. u32 ramdump_size = 0;
  2351. info_v2 = &plat_priv->ramdump_info_v2;
  2352. dump_data = &info_v2->dump_data;
  2353. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2354. &ramdump_size) == 0)
  2355. info_v2->ramdump_size = ramdump_size;
  2356. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2357. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2358. if (!info_v2->dump_data_vaddr)
  2359. return -ENOMEM;
  2360. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2361. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2362. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2363. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2364. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2365. sizeof(dump_data->name));
  2366. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2367. dump_entry.addr = virt_to_phys(dump_data);
  2368. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2369. &dump_entry);
  2370. if (ret) {
  2371. ret = cnss_ignore_dump_data_reg_fail(ret);
  2372. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  2373. ret ? "Error" : "Ignoring", ret);
  2374. goto free_ramdump;
  2375. }
  2376. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2377. if (!info_v2->ramdump_dev) {
  2378. cnss_pr_err("Failed to create ramdump device!\n");
  2379. ret = -ENOMEM;
  2380. goto free_ramdump;
  2381. }
  2382. return 0;
  2383. free_ramdump:
  2384. kfree(info_v2->dump_data_vaddr);
  2385. info_v2->dump_data_vaddr = NULL;
  2386. return ret;
  2387. }
  2388. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  2389. {
  2390. struct cnss_ramdump_info_v2 *info_v2;
  2391. info_v2 = &plat_priv->ramdump_info_v2;
  2392. if (info_v2->ramdump_dev)
  2393. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  2394. kfree(info_v2->dump_data_vaddr);
  2395. info_v2->dump_data_vaddr = NULL;
  2396. info_v2->dump_data_valid = false;
  2397. }
  2398. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2399. {
  2400. int ret = 0;
  2401. switch (plat_priv->device_id) {
  2402. case QCA6174_DEVICE_ID:
  2403. ret = cnss_register_ramdump_v1(plat_priv);
  2404. break;
  2405. case QCA6290_DEVICE_ID:
  2406. case QCA6390_DEVICE_ID:
  2407. case QCA6490_DEVICE_ID:
  2408. case KIWI_DEVICE_ID:
  2409. ret = cnss_register_ramdump_v2(plat_priv);
  2410. break;
  2411. default:
  2412. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2413. ret = -ENODEV;
  2414. break;
  2415. }
  2416. return ret;
  2417. }
  2418. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2419. {
  2420. switch (plat_priv->device_id) {
  2421. case QCA6174_DEVICE_ID:
  2422. cnss_unregister_ramdump_v1(plat_priv);
  2423. break;
  2424. case QCA6290_DEVICE_ID:
  2425. case QCA6390_DEVICE_ID:
  2426. case QCA6490_DEVICE_ID:
  2427. case KIWI_DEVICE_ID:
  2428. cnss_unregister_ramdump_v2(plat_priv);
  2429. break;
  2430. default:
  2431. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2432. break;
  2433. }
  2434. }
  2435. #else
  2436. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2437. {
  2438. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2439. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  2440. struct device *dev = &plat_priv->plat_dev->dev;
  2441. u32 ramdump_size = 0;
  2442. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2443. &ramdump_size) == 0)
  2444. info_v2->ramdump_size = ramdump_size;
  2445. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2446. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2447. if (!info_v2->dump_data_vaddr)
  2448. return -ENOMEM;
  2449. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2450. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2451. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2452. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2453. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2454. sizeof(dump_data->name));
  2455. info_v2->ramdump_dev = dev;
  2456. return 0;
  2457. }
  2458. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2459. {
  2460. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2461. info_v2->ramdump_dev = NULL;
  2462. kfree(info_v2->dump_data_vaddr);
  2463. info_v2->dump_data_vaddr = NULL;
  2464. info_v2->dump_data_valid = false;
  2465. }
  2466. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  2467. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  2468. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2469. phys_addr_t *pa, unsigned long attrs)
  2470. {
  2471. struct sg_table sgt;
  2472. int ret;
  2473. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  2474. if (ret) {
  2475. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  2476. va, &dma, size, attrs);
  2477. return -EINVAL;
  2478. }
  2479. *pa = page_to_phys(sg_page(sgt.sgl));
  2480. sg_free_table(&sgt);
  2481. return 0;
  2482. }
  2483. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2484. enum cnss_fw_dump_type type, int seg_no,
  2485. void *va, phys_addr_t pa, size_t size)
  2486. {
  2487. struct md_region md_entry;
  2488. int ret;
  2489. switch (type) {
  2490. case CNSS_FW_IMAGE:
  2491. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2492. seg_no);
  2493. break;
  2494. case CNSS_FW_RDDM:
  2495. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2496. seg_no);
  2497. break;
  2498. case CNSS_FW_REMOTE_HEAP:
  2499. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2500. seg_no);
  2501. break;
  2502. default:
  2503. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2504. return -EINVAL;
  2505. }
  2506. md_entry.phys_addr = pa;
  2507. md_entry.virt_addr = (uintptr_t)va;
  2508. md_entry.size = size;
  2509. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2510. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2511. md_entry.name, va, &pa, size);
  2512. ret = msm_minidump_add_region(&md_entry);
  2513. if (ret < 0)
  2514. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  2515. return ret;
  2516. }
  2517. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2518. enum cnss_fw_dump_type type, int seg_no,
  2519. void *va, phys_addr_t pa, size_t size)
  2520. {
  2521. struct md_region md_entry;
  2522. int ret;
  2523. switch (type) {
  2524. case CNSS_FW_IMAGE:
  2525. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2526. seg_no);
  2527. break;
  2528. case CNSS_FW_RDDM:
  2529. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2530. seg_no);
  2531. break;
  2532. case CNSS_FW_REMOTE_HEAP:
  2533. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2534. seg_no);
  2535. break;
  2536. default:
  2537. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2538. return -EINVAL;
  2539. }
  2540. md_entry.phys_addr = pa;
  2541. md_entry.virt_addr = (uintptr_t)va;
  2542. md_entry.size = size;
  2543. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2544. cnss_pr_dbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2545. md_entry.name, va, &pa, size);
  2546. ret = msm_minidump_remove_region(&md_entry);
  2547. if (ret)
  2548. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  2549. ret);
  2550. return ret;
  2551. }
  2552. #else
  2553. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2554. phys_addr_t *pa, unsigned long attrs)
  2555. {
  2556. return 0;
  2557. }
  2558. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2559. enum cnss_fw_dump_type type, int seg_no,
  2560. void *va, phys_addr_t pa, size_t size)
  2561. {
  2562. return 0;
  2563. }
  2564. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2565. enum cnss_fw_dump_type type, int seg_no,
  2566. void *va, phys_addr_t pa, size_t size)
  2567. {
  2568. return 0;
  2569. }
  2570. #endif /* CONFIG_QCOM_MINIDUMP */
  2571. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  2572. const struct firmware **fw_entry,
  2573. const char *filename)
  2574. {
  2575. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  2576. return request_firmware_direct(fw_entry, filename,
  2577. &plat_priv->plat_dev->dev);
  2578. else
  2579. return firmware_request_nowarn(fw_entry, filename,
  2580. &plat_priv->plat_dev->dev);
  2581. }
  2582. #if IS_ENABLED(CONFIG_INTERCONNECT)
  2583. /**
  2584. * cnss_register_bus_scale() - Setup interconnect voting data
  2585. * @plat_priv: Platform data structure
  2586. *
  2587. * For different interconnect path configured in device tree setup voting data
  2588. * for list of bandwidth requirements.
  2589. *
  2590. * Result: 0 for success. -EINVAL if not configured
  2591. */
  2592. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2593. {
  2594. int ret = -EINVAL;
  2595. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  2596. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2597. struct device *dev = &plat_priv->plat_dev->dev;
  2598. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  2599. ret = of_property_read_u32(dev->of_node,
  2600. "qcom,icc-path-count",
  2601. &plat_priv->icc.path_count);
  2602. if (ret) {
  2603. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  2604. return 0;
  2605. }
  2606. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  2607. "qcom,bus-bw-cfg-count",
  2608. &plat_priv->icc.bus_bw_cfg_count);
  2609. if (ret) {
  2610. cnss_pr_err("Failed to get Bus BW Config table size\n");
  2611. goto cleanup;
  2612. }
  2613. cfg_arr_size = plat_priv->icc.path_count *
  2614. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  2615. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  2616. if (!cfg_arr) {
  2617. cnss_pr_err("Failed to alloc cfg table mem\n");
  2618. ret = -ENOMEM;
  2619. goto cleanup;
  2620. }
  2621. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  2622. "qcom,bus-bw-cfg", cfg_arr,
  2623. cfg_arr_size);
  2624. if (ret) {
  2625. cnss_pr_err("Invalid Bus BW Config Table\n");
  2626. goto cleanup;
  2627. }
  2628. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  2629. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  2630. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  2631. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  2632. GFP_KERNEL);
  2633. if (!bus_bw_info) {
  2634. ret = -ENOMEM;
  2635. goto out;
  2636. }
  2637. ret = of_property_read_string_index(dev->of_node,
  2638. "interconnect-names", idx,
  2639. &bus_bw_info->icc_name);
  2640. if (ret)
  2641. goto out;
  2642. bus_bw_info->icc_path =
  2643. of_icc_get(&plat_priv->plat_dev->dev,
  2644. bus_bw_info->icc_name);
  2645. if (IS_ERR(bus_bw_info->icc_path)) {
  2646. ret = PTR_ERR(bus_bw_info->icc_path);
  2647. if (ret != -EPROBE_DEFER) {
  2648. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  2649. bus_bw_info->icc_name, ret);
  2650. goto out;
  2651. }
  2652. }
  2653. bus_bw_info->cfg_table =
  2654. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  2655. sizeof(*bus_bw_info->cfg_table),
  2656. GFP_KERNEL);
  2657. if (!bus_bw_info->cfg_table) {
  2658. ret = -ENOMEM;
  2659. goto out;
  2660. }
  2661. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  2662. bus_bw_info->icc_name);
  2663. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  2664. CNSS_ICC_VOTE_MAX);
  2665. i < plat_priv->icc.bus_bw_cfg_count;
  2666. i++, j += 2) {
  2667. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  2668. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  2669. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  2670. i, bus_bw_info->cfg_table[i].avg_bw,
  2671. bus_bw_info->cfg_table[i].peak_bw);
  2672. }
  2673. list_add_tail(&bus_bw_info->list,
  2674. &plat_priv->icc.list_head);
  2675. }
  2676. kfree(cfg_arr);
  2677. return 0;
  2678. out:
  2679. list_for_each_entry_safe(bus_bw_info, tmp,
  2680. &plat_priv->icc.list_head, list) {
  2681. list_del(&bus_bw_info->list);
  2682. }
  2683. cleanup:
  2684. kfree(cfg_arr);
  2685. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2686. return ret;
  2687. }
  2688. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  2689. {
  2690. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2691. list_for_each_entry_safe(bus_bw_info, tmp,
  2692. &plat_priv->icc.list_head, list) {
  2693. list_del(&bus_bw_info->list);
  2694. if (bus_bw_info->icc_path)
  2695. icc_put(bus_bw_info->icc_path);
  2696. }
  2697. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2698. }
  2699. #else
  2700. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2701. {
  2702. return 0;
  2703. }
  2704. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  2705. #endif /* CONFIG_INTERCONNECT */
  2706. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  2707. {
  2708. struct cnss_plat_data *plat_priv = cb_ctx;
  2709. if (!plat_priv) {
  2710. cnss_pr_err("%s: Invalid context\n", __func__);
  2711. return;
  2712. }
  2713. if (status) {
  2714. cnss_pr_info("CNSS Daemon connected\n");
  2715. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2716. complete(&plat_priv->daemon_connected);
  2717. } else {
  2718. cnss_pr_info("CNSS Daemon disconnected\n");
  2719. reinit_completion(&plat_priv->daemon_connected);
  2720. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2721. }
  2722. }
  2723. static ssize_t enable_hds_store(struct device *dev,
  2724. struct device_attribute *attr,
  2725. const char *buf, size_t count)
  2726. {
  2727. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2728. unsigned int enable_hds = 0;
  2729. if (!plat_priv)
  2730. return -ENODEV;
  2731. if (sscanf(buf, "%du", &enable_hds) != 1) {
  2732. cnss_pr_err("Invalid enable_hds sysfs command\n");
  2733. return -EINVAL;
  2734. }
  2735. if (enable_hds)
  2736. plat_priv->hds_enabled = true;
  2737. else
  2738. plat_priv->hds_enabled = false;
  2739. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  2740. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  2741. return count;
  2742. }
  2743. static ssize_t recovery_store(struct device *dev,
  2744. struct device_attribute *attr,
  2745. const char *buf, size_t count)
  2746. {
  2747. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2748. unsigned int recovery = 0;
  2749. if (!plat_priv)
  2750. return -ENODEV;
  2751. if (sscanf(buf, "%du", &recovery) != 1) {
  2752. cnss_pr_err("Invalid recovery sysfs command\n");
  2753. return -EINVAL;
  2754. }
  2755. if (recovery)
  2756. plat_priv->recovery_enabled = true;
  2757. else
  2758. plat_priv->recovery_enabled = false;
  2759. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  2760. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  2761. return count;
  2762. }
  2763. static ssize_t shutdown_store(struct device *dev,
  2764. struct device_attribute *attr,
  2765. const char *buf, size_t count)
  2766. {
  2767. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2768. if (plat_priv) {
  2769. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2770. del_timer(&plat_priv->fw_boot_timer);
  2771. complete_all(&plat_priv->power_up_complete);
  2772. complete_all(&plat_priv->cal_complete);
  2773. }
  2774. cnss_pr_dbg("Received shutdown notification\n");
  2775. return count;
  2776. }
  2777. static ssize_t fs_ready_store(struct device *dev,
  2778. struct device_attribute *attr,
  2779. const char *buf, size_t count)
  2780. {
  2781. int fs_ready = 0;
  2782. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2783. if (sscanf(buf, "%du", &fs_ready) != 1)
  2784. return -EINVAL;
  2785. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  2786. fs_ready, count);
  2787. if (!plat_priv) {
  2788. cnss_pr_err("plat_priv is NULL\n");
  2789. return count;
  2790. }
  2791. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  2792. cnss_pr_dbg("QMI is bypassed\n");
  2793. return count;
  2794. }
  2795. switch (plat_priv->device_id) {
  2796. case QCA6290_DEVICE_ID:
  2797. case QCA6390_DEVICE_ID:
  2798. case QCA6490_DEVICE_ID:
  2799. case KIWI_DEVICE_ID:
  2800. break;
  2801. default:
  2802. cnss_pr_err("Not supported for device ID 0x%lx\n",
  2803. plat_priv->device_id);
  2804. return count;
  2805. }
  2806. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  2807. cnss_driver_event_post(plat_priv,
  2808. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  2809. 0, NULL);
  2810. }
  2811. return count;
  2812. }
  2813. static ssize_t qdss_trace_start_store(struct device *dev,
  2814. struct device_attribute *attr,
  2815. const char *buf, size_t count)
  2816. {
  2817. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2818. wlfw_qdss_trace_start(plat_priv);
  2819. cnss_pr_dbg("Received QDSS start command\n");
  2820. return count;
  2821. }
  2822. static ssize_t qdss_trace_stop_store(struct device *dev,
  2823. struct device_attribute *attr,
  2824. const char *buf, size_t count)
  2825. {
  2826. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2827. u32 option = 0;
  2828. if (sscanf(buf, "%du", &option) != 1)
  2829. return -EINVAL;
  2830. wlfw_qdss_trace_stop(plat_priv, option);
  2831. cnss_pr_dbg("Received QDSS stop command\n");
  2832. return count;
  2833. }
  2834. static ssize_t qdss_conf_download_store(struct device *dev,
  2835. struct device_attribute *attr,
  2836. const char *buf, size_t count)
  2837. {
  2838. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2839. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  2840. cnss_pr_dbg("Received QDSS download config command\n");
  2841. return count;
  2842. }
  2843. static ssize_t hw_trace_override_store(struct device *dev,
  2844. struct device_attribute *attr,
  2845. const char *buf, size_t count)
  2846. {
  2847. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2848. int tmp = 0;
  2849. if (sscanf(buf, "%du", &tmp) != 1)
  2850. return -EINVAL;
  2851. plat_priv->hw_trc_override = tmp;
  2852. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  2853. return count;
  2854. }
  2855. static ssize_t charger_mode_store(struct device *dev,
  2856. struct device_attribute *attr,
  2857. const char *buf, size_t count)
  2858. {
  2859. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2860. int tmp = 0;
  2861. if (sscanf(buf, "%du", &tmp) != 1)
  2862. return -EINVAL;
  2863. plat_priv->charger_mode = tmp;
  2864. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  2865. return count;
  2866. }
  2867. static DEVICE_ATTR_WO(fs_ready);
  2868. static DEVICE_ATTR_WO(shutdown);
  2869. static DEVICE_ATTR_WO(recovery);
  2870. static DEVICE_ATTR_WO(enable_hds);
  2871. static DEVICE_ATTR_WO(qdss_trace_start);
  2872. static DEVICE_ATTR_WO(qdss_trace_stop);
  2873. static DEVICE_ATTR_WO(qdss_conf_download);
  2874. static DEVICE_ATTR_WO(hw_trace_override);
  2875. static DEVICE_ATTR_WO(charger_mode);
  2876. static struct attribute *cnss_attrs[] = {
  2877. &dev_attr_fs_ready.attr,
  2878. &dev_attr_shutdown.attr,
  2879. &dev_attr_recovery.attr,
  2880. &dev_attr_enable_hds.attr,
  2881. &dev_attr_qdss_trace_start.attr,
  2882. &dev_attr_qdss_trace_stop.attr,
  2883. &dev_attr_qdss_conf_download.attr,
  2884. &dev_attr_hw_trace_override.attr,
  2885. &dev_attr_charger_mode.attr,
  2886. NULL,
  2887. };
  2888. static struct attribute_group cnss_attr_group = {
  2889. .attrs = cnss_attrs,
  2890. };
  2891. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  2892. {
  2893. struct device *dev = &plat_priv->plat_dev->dev;
  2894. int ret;
  2895. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "cnss");
  2896. if (ret) {
  2897. cnss_pr_err("Failed to create cnss link, err = %d\n",
  2898. ret);
  2899. goto out;
  2900. }
  2901. /* This is only for backward compatibility. */
  2902. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "shutdown_wlan");
  2903. if (ret) {
  2904. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  2905. ret);
  2906. goto rm_cnss_link;
  2907. }
  2908. return 0;
  2909. rm_cnss_link:
  2910. sysfs_remove_link(kernel_kobj, "cnss");
  2911. out:
  2912. return ret;
  2913. }
  2914. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  2915. {
  2916. sysfs_remove_link(kernel_kobj, "shutdown_wlan");
  2917. sysfs_remove_link(kernel_kobj, "cnss");
  2918. }
  2919. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  2920. {
  2921. int ret = 0;
  2922. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  2923. &cnss_attr_group);
  2924. if (ret) {
  2925. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  2926. ret);
  2927. goto out;
  2928. }
  2929. cnss_create_sysfs_link(plat_priv);
  2930. return 0;
  2931. out:
  2932. return ret;
  2933. }
  2934. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  2935. {
  2936. cnss_remove_sysfs_link(plat_priv);
  2937. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  2938. }
  2939. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  2940. {
  2941. spin_lock_init(&plat_priv->event_lock);
  2942. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  2943. WQ_UNBOUND, 1);
  2944. if (!plat_priv->event_wq) {
  2945. cnss_pr_err("Failed to create event workqueue!\n");
  2946. return -EFAULT;
  2947. }
  2948. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  2949. INIT_LIST_HEAD(&plat_priv->event_list);
  2950. return 0;
  2951. }
  2952. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  2953. {
  2954. destroy_workqueue(plat_priv->event_wq);
  2955. }
  2956. static int cnss_reboot_notifier(struct notifier_block *nb,
  2957. unsigned long action,
  2958. void *data)
  2959. {
  2960. struct cnss_plat_data *plat_priv =
  2961. container_of(nb, struct cnss_plat_data, reboot_nb);
  2962. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2963. del_timer(&plat_priv->fw_boot_timer);
  2964. complete_all(&plat_priv->power_up_complete);
  2965. complete_all(&plat_priv->cal_complete);
  2966. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  2967. return NOTIFY_DONE;
  2968. }
  2969. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  2970. {
  2971. int ret;
  2972. ret = cnss_init_sol_gpio(plat_priv);
  2973. if (ret)
  2974. return ret;
  2975. timer_setup(&plat_priv->fw_boot_timer,
  2976. cnss_bus_fw_boot_timeout_hdlr, 0);
  2977. ret = register_pm_notifier(&cnss_pm_notifier);
  2978. if (ret)
  2979. cnss_pr_err("Failed to register PM notifier, err = %d\n", ret);
  2980. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  2981. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  2982. if (ret)
  2983. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  2984. ret);
  2985. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  2986. if (ret)
  2987. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  2988. ret);
  2989. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  2990. init_completion(&plat_priv->power_up_complete);
  2991. init_completion(&plat_priv->cal_complete);
  2992. init_completion(&plat_priv->rddm_complete);
  2993. init_completion(&plat_priv->recovery_complete);
  2994. init_completion(&plat_priv->daemon_connected);
  2995. mutex_init(&plat_priv->dev_lock);
  2996. mutex_init(&plat_priv->driver_ops_lock);
  2997. plat_priv->recovery_ws =
  2998. wakeup_source_register(&plat_priv->plat_dev->dev,
  2999. "CNSS_FW_RECOVERY");
  3000. if (!plat_priv->recovery_ws)
  3001. cnss_pr_err("Failed to setup FW recovery wake source\n");
  3002. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3003. cnss_daemon_connection_update_cb,
  3004. plat_priv);
  3005. if (ret)
  3006. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  3007. ret);
  3008. return 0;
  3009. }
  3010. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  3011. {
  3012. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3013. plat_priv);
  3014. complete_all(&plat_priv->recovery_complete);
  3015. complete_all(&plat_priv->rddm_complete);
  3016. complete_all(&plat_priv->cal_complete);
  3017. complete_all(&plat_priv->power_up_complete);
  3018. complete_all(&plat_priv->daemon_connected);
  3019. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  3020. unregister_reboot_notifier(&plat_priv->reboot_nb);
  3021. unregister_pm_notifier(&cnss_pm_notifier);
  3022. del_timer(&plat_priv->fw_boot_timer);
  3023. wakeup_source_unregister(plat_priv->recovery_ws);
  3024. cnss_deinit_sol_gpio(plat_priv);
  3025. }
  3026. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  3027. {
  3028. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  3029. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  3030. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3031. "qcom,wlan-cbc-enabled");
  3032. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  3033. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  3034. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  3035. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  3036. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  3037. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  3038. * enabled by default
  3039. */
  3040. plat_priv->adsp_pc_enabled = true;
  3041. }
  3042. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  3043. {
  3044. struct device *dev = &plat_priv->plat_dev->dev;
  3045. plat_priv->use_pm_domain =
  3046. of_property_read_bool(dev->of_node, "use-pm-domain");
  3047. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  3048. }
  3049. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  3050. {
  3051. struct device *dev = &plat_priv->plat_dev->dev;
  3052. plat_priv->set_wlaon_pwr_ctrl =
  3053. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  3054. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  3055. plat_priv->set_wlaon_pwr_ctrl);
  3056. }
  3057. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  3058. {
  3059. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3060. "qcom,converged-dt") ||
  3061. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3062. "qcom,same-dt-multi-dev") ||
  3063. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3064. "qcom,multi-wlan-exchg"));
  3065. }
  3066. static const struct platform_device_id cnss_platform_id_table[] = {
  3067. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  3068. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  3069. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  3070. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  3071. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  3072. { },
  3073. };
  3074. static const struct of_device_id cnss_of_match_table[] = {
  3075. {
  3076. .compatible = "qcom,cnss",
  3077. .data = (void *)&cnss_platform_id_table[0]},
  3078. {
  3079. .compatible = "qcom,cnss-qca6290",
  3080. .data = (void *)&cnss_platform_id_table[1]},
  3081. {
  3082. .compatible = "qcom,cnss-qca6390",
  3083. .data = (void *)&cnss_platform_id_table[2]},
  3084. {
  3085. .compatible = "qcom,cnss-qca6490",
  3086. .data = (void *)&cnss_platform_id_table[3]},
  3087. {
  3088. .compatible = "qcom,cnss-kiwi",
  3089. .data = (void *)&cnss_platform_id_table[4]},
  3090. { },
  3091. };
  3092. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  3093. static inline bool
  3094. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  3095. {
  3096. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3097. "use-nv-mac");
  3098. }
  3099. static int cnss_probe(struct platform_device *plat_dev)
  3100. {
  3101. int ret = 0;
  3102. struct cnss_plat_data *plat_priv;
  3103. const struct of_device_id *of_id;
  3104. const struct platform_device_id *device_id;
  3105. int retry = 0;
  3106. if (cnss_get_plat_priv(plat_dev)) {
  3107. cnss_pr_err("Driver is already initialized!\n");
  3108. ret = -EEXIST;
  3109. goto out;
  3110. }
  3111. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  3112. if (!of_id || !of_id->data) {
  3113. cnss_pr_err("Failed to find of match device!\n");
  3114. ret = -ENODEV;
  3115. goto out;
  3116. }
  3117. device_id = of_id->data;
  3118. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  3119. GFP_KERNEL);
  3120. if (!plat_priv) {
  3121. ret = -ENOMEM;
  3122. goto out;
  3123. }
  3124. plat_priv->plat_dev = plat_dev;
  3125. plat_priv->device_id = device_id->driver_data;
  3126. plat_priv->bus_type = cnss_get_bus_type(plat_priv->device_id);
  3127. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  3128. plat_priv->use_fw_path_with_prefix =
  3129. cnss_use_fw_path_with_prefix(plat_priv);
  3130. cnss_set_plat_priv(plat_dev, plat_priv);
  3131. platform_set_drvdata(plat_dev, plat_priv);
  3132. INIT_LIST_HEAD(&plat_priv->vreg_list);
  3133. INIT_LIST_HEAD(&plat_priv->clk_list);
  3134. cnss_get_pm_domain_info(plat_priv);
  3135. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  3136. cnss_get_tcs_info(plat_priv);
  3137. cnss_get_cpr_info(plat_priv);
  3138. cnss_aop_mbox_init(plat_priv);
  3139. cnss_init_control_params(plat_priv);
  3140. ret = cnss_get_resources(plat_priv);
  3141. if (ret)
  3142. goto reset_ctx;
  3143. ret = cnss_register_esoc(plat_priv);
  3144. if (ret)
  3145. goto free_res;
  3146. ret = cnss_register_bus_scale(plat_priv);
  3147. if (ret)
  3148. goto unreg_esoc;
  3149. ret = cnss_create_sysfs(plat_priv);
  3150. if (ret)
  3151. goto unreg_bus_scale;
  3152. ret = cnss_event_work_init(plat_priv);
  3153. if (ret)
  3154. goto remove_sysfs;
  3155. ret = cnss_qmi_init(plat_priv);
  3156. if (ret)
  3157. goto deinit_event_work;
  3158. ret = cnss_dms_init(plat_priv);
  3159. if (ret)
  3160. goto deinit_qmi;
  3161. ret = cnss_debugfs_create(plat_priv);
  3162. if (ret)
  3163. goto deinit_dms;
  3164. ret = cnss_misc_init(plat_priv);
  3165. if (ret)
  3166. goto destroy_debugfs;
  3167. /* Make sure all platform related init are done before
  3168. * device power on and bus init.
  3169. */
  3170. if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) {
  3171. retry:
  3172. ret = cnss_power_on_device(plat_priv);
  3173. if (ret)
  3174. goto deinit_misc;
  3175. ret = cnss_bus_init(plat_priv);
  3176. if (ret) {
  3177. if ((ret != -EPROBE_DEFER) &&
  3178. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  3179. cnss_power_off_device(plat_priv);
  3180. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  3181. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  3182. goto retry;
  3183. }
  3184. goto power_off;
  3185. }
  3186. }
  3187. cnss_register_coex_service(plat_priv);
  3188. cnss_register_ims_service(plat_priv);
  3189. ret = cnss_genl_init();
  3190. if (ret < 0)
  3191. cnss_pr_err("CNSS genl init failed %d\n", ret);
  3192. cnss_pr_info("Platform driver probed successfully.\n");
  3193. return 0;
  3194. power_off:
  3195. if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  3196. cnss_power_off_device(plat_priv);
  3197. deinit_misc:
  3198. cnss_misc_deinit(plat_priv);
  3199. destroy_debugfs:
  3200. cnss_debugfs_destroy(plat_priv);
  3201. deinit_dms:
  3202. cnss_dms_deinit(plat_priv);
  3203. deinit_qmi:
  3204. cnss_qmi_deinit(plat_priv);
  3205. deinit_event_work:
  3206. cnss_event_work_deinit(plat_priv);
  3207. remove_sysfs:
  3208. cnss_remove_sysfs(plat_priv);
  3209. unreg_bus_scale:
  3210. cnss_unregister_bus_scale(plat_priv);
  3211. unreg_esoc:
  3212. cnss_unregister_esoc(plat_priv);
  3213. free_res:
  3214. cnss_put_resources(plat_priv);
  3215. reset_ctx:
  3216. platform_set_drvdata(plat_dev, NULL);
  3217. cnss_set_plat_priv(plat_dev, NULL);
  3218. out:
  3219. return ret;
  3220. }
  3221. static int cnss_remove(struct platform_device *plat_dev)
  3222. {
  3223. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  3224. cnss_genl_exit();
  3225. cnss_unregister_ims_service(plat_priv);
  3226. cnss_unregister_coex_service(plat_priv);
  3227. cnss_bus_deinit(plat_priv);
  3228. cnss_misc_deinit(plat_priv);
  3229. cnss_debugfs_destroy(plat_priv);
  3230. cnss_dms_deinit(plat_priv);
  3231. cnss_qmi_deinit(plat_priv);
  3232. cnss_event_work_deinit(plat_priv);
  3233. cnss_remove_sysfs(plat_priv);
  3234. cnss_unregister_bus_scale(plat_priv);
  3235. cnss_unregister_esoc(plat_priv);
  3236. cnss_put_resources(plat_priv);
  3237. if (!IS_ERR_OR_NULL(plat_priv->mbox_chan))
  3238. mbox_free_channel(plat_priv->mbox_chan);
  3239. platform_set_drvdata(plat_dev, NULL);
  3240. plat_env = NULL;
  3241. return 0;
  3242. }
  3243. static struct platform_driver cnss_platform_driver = {
  3244. .probe = cnss_probe,
  3245. .remove = cnss_remove,
  3246. .driver = {
  3247. .name = "cnss2",
  3248. .of_match_table = cnss_of_match_table,
  3249. #ifdef CONFIG_CNSS_ASYNC
  3250. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  3251. #endif
  3252. },
  3253. };
  3254. /**
  3255. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  3256. *
  3257. * Valid device tree node means a node with "compatible" property from the
  3258. * device match table and "status" property is not disabled.
  3259. *
  3260. * Return: true if valid device tree node found, false if not found
  3261. */
  3262. static bool cnss_is_valid_dt_node_found(void)
  3263. {
  3264. struct device_node *dn = NULL;
  3265. for_each_matching_node(dn, cnss_of_match_table) {
  3266. if (of_device_is_available(dn))
  3267. break;
  3268. }
  3269. if (dn)
  3270. return true;
  3271. return false;
  3272. }
  3273. static int __init cnss_initialize(void)
  3274. {
  3275. int ret = 0;
  3276. if (!cnss_is_valid_dt_node_found())
  3277. return -ENODEV;
  3278. cnss_debug_init();
  3279. ret = platform_driver_register(&cnss_platform_driver);
  3280. if (ret)
  3281. cnss_debug_deinit();
  3282. return ret;
  3283. }
  3284. static void __exit cnss_exit(void)
  3285. {
  3286. platform_driver_unregister(&cnss_platform_driver);
  3287. cnss_debug_deinit();
  3288. }
  3289. module_init(cnss_initialize);
  3290. module_exit(cnss_exit);
  3291. MODULE_LICENSE("GPL v2");
  3292. MODULE_DESCRIPTION("CNSS2 Platform Driver");