debug.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
  3. /* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */
  4. #include <linux/err.h>
  5. #include <linux/seq_file.h>
  6. #include <linux/debugfs.h>
  7. #include "main.h"
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "pci.h"
  11. #define MMIO_REG_ACCESS_MEM_TYPE 0xFF
  12. #define MMIO_REG_RAW_ACCESS_MEM_TYPE 0xFE
  13. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  14. void *cnss_ipc_log_context;
  15. void *cnss_ipc_log_long_context;
  16. #endif
  17. static int cnss_pin_connect_show(struct seq_file *s, void *data)
  18. {
  19. struct cnss_plat_data *cnss_priv = s->private;
  20. seq_puts(s, "Pin connect results\n");
  21. seq_printf(s, "FW power pin result: %04x\n",
  22. cnss_priv->pin_result.fw_pwr_pin_result);
  23. seq_printf(s, "FW PHY IO pin result: %04x\n",
  24. cnss_priv->pin_result.fw_phy_io_pin_result);
  25. seq_printf(s, "FW RF pin result: %04x\n",
  26. cnss_priv->pin_result.fw_rf_pin_result);
  27. seq_printf(s, "Host pin result: %04x\n",
  28. cnss_priv->pin_result.host_pin_result);
  29. seq_puts(s, "\n");
  30. return 0;
  31. }
  32. static int cnss_pin_connect_open(struct inode *inode, struct file *file)
  33. {
  34. return single_open(file, cnss_pin_connect_show, inode->i_private);
  35. }
  36. static const struct file_operations cnss_pin_connect_fops = {
  37. .read = seq_read,
  38. .release = single_release,
  39. .open = cnss_pin_connect_open,
  40. .owner = THIS_MODULE,
  41. .llseek = seq_lseek,
  42. };
  43. static int cnss_stats_show_state(struct seq_file *s,
  44. struct cnss_plat_data *plat_priv)
  45. {
  46. enum cnss_driver_state i;
  47. int skip = 0;
  48. unsigned long state;
  49. seq_printf(s, "\nState: 0x%lx(", plat_priv->driver_state);
  50. for (i = 0, state = plat_priv->driver_state; state != 0;
  51. state >>= 1, i++) {
  52. if (!(state & 0x1))
  53. continue;
  54. if (skip++)
  55. seq_puts(s, " | ");
  56. switch (i) {
  57. case CNSS_QMI_WLFW_CONNECTED:
  58. seq_puts(s, "QMI_WLFW_CONNECTED");
  59. continue;
  60. case CNSS_FW_MEM_READY:
  61. seq_puts(s, "FW_MEM_READY");
  62. continue;
  63. case CNSS_FW_READY:
  64. seq_puts(s, "FW_READY");
  65. continue;
  66. case CNSS_IN_COLD_BOOT_CAL:
  67. seq_puts(s, "IN_COLD_BOOT_CAL");
  68. continue;
  69. case CNSS_DRIVER_LOADING:
  70. seq_puts(s, "DRIVER_LOADING");
  71. continue;
  72. case CNSS_DRIVER_UNLOADING:
  73. seq_puts(s, "DRIVER_UNLOADING");
  74. continue;
  75. case CNSS_DRIVER_IDLE_RESTART:
  76. seq_puts(s, "IDLE_RESTART");
  77. continue;
  78. case CNSS_DRIVER_IDLE_SHUTDOWN:
  79. seq_puts(s, "IDLE_SHUTDOWN");
  80. continue;
  81. case CNSS_DRIVER_PROBED:
  82. seq_puts(s, "DRIVER_PROBED");
  83. continue;
  84. case CNSS_DRIVER_RECOVERY:
  85. seq_puts(s, "DRIVER_RECOVERY");
  86. continue;
  87. case CNSS_FW_BOOT_RECOVERY:
  88. seq_puts(s, "FW_BOOT_RECOVERY");
  89. continue;
  90. case CNSS_DEV_ERR_NOTIFY:
  91. seq_puts(s, "DEV_ERR");
  92. continue;
  93. case CNSS_DRIVER_DEBUG:
  94. seq_puts(s, "DRIVER_DEBUG");
  95. continue;
  96. case CNSS_COEX_CONNECTED:
  97. seq_puts(s, "COEX_CONNECTED");
  98. continue;
  99. case CNSS_IMS_CONNECTED:
  100. seq_puts(s, "IMS_CONNECTED");
  101. continue;
  102. case CNSS_IN_SUSPEND_RESUME:
  103. seq_puts(s, "IN_SUSPEND_RESUME");
  104. continue;
  105. case CNSS_IN_REBOOT:
  106. seq_puts(s, "IN_REBOOT");
  107. continue;
  108. case CNSS_COLD_BOOT_CAL_DONE:
  109. seq_puts(s, "COLD_BOOT_CAL_DONE");
  110. continue;
  111. case CNSS_IN_PANIC:
  112. seq_puts(s, "IN_PANIC");
  113. continue;
  114. case CNSS_QMI_DEL_SERVER:
  115. seq_puts(s, "DEL_SERVER_IN_PROGRESS");
  116. continue;
  117. case CNSS_QMI_DMS_CONNECTED:
  118. seq_puts(s, "DMS_CONNECTED");
  119. continue;
  120. case CNSS_DAEMON_CONNECTED:
  121. seq_puts(s, "DAEMON_CONNECTED");
  122. continue;
  123. case CNSS_PCI_PROBE_DONE:
  124. seq_puts(s, "PCI PROBE DONE");
  125. continue;
  126. case CNSS_DRIVER_REGISTER:
  127. seq_puts(s, "DRIVER REGISTERED");
  128. continue;
  129. }
  130. seq_printf(s, "UNKNOWN-%d", i);
  131. }
  132. seq_puts(s, ")\n");
  133. return 0;
  134. }
  135. static int cnss_stats_show_gpio_state(struct seq_file *s,
  136. struct cnss_plat_data *plat_priv)
  137. {
  138. seq_printf(s, "\nHost SOL: %d", cnss_get_host_sol_value(plat_priv));
  139. seq_printf(s, "\nDev SOL: %d", cnss_get_dev_sol_value(plat_priv));
  140. return 0;
  141. }
  142. static int cnss_stats_show(struct seq_file *s, void *data)
  143. {
  144. struct cnss_plat_data *plat_priv = s->private;
  145. cnss_stats_show_state(s, plat_priv);
  146. cnss_stats_show_gpio_state(s, plat_priv);
  147. return 0;
  148. }
  149. static int cnss_stats_open(struct inode *inode, struct file *file)
  150. {
  151. return single_open(file, cnss_stats_show, inode->i_private);
  152. }
  153. static const struct file_operations cnss_stats_fops = {
  154. .read = seq_read,
  155. .release = single_release,
  156. .open = cnss_stats_open,
  157. .owner = THIS_MODULE,
  158. .llseek = seq_lseek,
  159. };
  160. static ssize_t cnss_dev_boot_debug_write(struct file *fp,
  161. const char __user *user_buf,
  162. size_t count, loff_t *off)
  163. {
  164. struct cnss_plat_data *plat_priv =
  165. ((struct seq_file *)fp->private_data)->private;
  166. struct cnss_pci_data *pci_priv;
  167. char buf[64];
  168. char *cmd;
  169. unsigned int len = 0;
  170. int ret = 0;
  171. if (!plat_priv)
  172. return -ENODEV;
  173. len = min(count, sizeof(buf) - 1);
  174. if (copy_from_user(buf, user_buf, len))
  175. return -EFAULT;
  176. buf[len] = '\0';
  177. cmd = buf;
  178. cnss_pr_dbg("Received dev_boot debug command: %s\n", cmd);
  179. if (sysfs_streq(cmd, "on")) {
  180. ret = cnss_power_on_device(plat_priv);
  181. } else if (sysfs_streq(cmd, "off")) {
  182. cnss_power_off_device(plat_priv);
  183. } else if (sysfs_streq(cmd, "enumerate")) {
  184. ret = cnss_pci_init(plat_priv);
  185. } else if (sysfs_streq(cmd, "powerup")) {
  186. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  187. ret = cnss_driver_event_post(plat_priv,
  188. CNSS_DRIVER_EVENT_POWER_UP,
  189. CNSS_EVENT_SYNC, NULL);
  190. } else if (sysfs_streq(cmd, "shutdown")) {
  191. ret = cnss_driver_event_post(plat_priv,
  192. CNSS_DRIVER_EVENT_POWER_DOWN,
  193. 0, NULL);
  194. clear_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  195. } else if (sysfs_streq(cmd, "assert_host_sol")) {
  196. ret = cnss_set_host_sol_value(plat_priv, 1);
  197. } else if (sysfs_streq(cmd, "deassert_host_sol")) {
  198. ret = cnss_set_host_sol_value(plat_priv, 0);
  199. } else {
  200. pci_priv = plat_priv->bus_priv;
  201. if (!pci_priv)
  202. return -ENODEV;
  203. if (sysfs_streq(cmd, "download")) {
  204. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  205. ret = cnss_pci_start_mhi(pci_priv);
  206. } else if (sysfs_streq(cmd, "linkup")) {
  207. ret = cnss_resume_pci_link(pci_priv);
  208. } else if (sysfs_streq(cmd, "linkdown")) {
  209. ret = cnss_suspend_pci_link(pci_priv);
  210. } else if (sysfs_streq(cmd, "assert")) {
  211. cnss_pr_info("FW Assert triggered for debug\n");
  212. ret = cnss_force_fw_assert(&pci_priv->pci_dev->dev);
  213. } else if (sysfs_streq(cmd, "set_cbc_done")) {
  214. cnss_pr_dbg("Force set cold boot cal done status\n");
  215. set_bit(CNSS_COLD_BOOT_CAL_DONE,
  216. &plat_priv->driver_state);
  217. } else {
  218. cnss_pr_err("Device boot debugfs command is invalid\n");
  219. ret = -EINVAL;
  220. }
  221. }
  222. if (ret < 0)
  223. return ret;
  224. return count;
  225. }
  226. static int cnss_dev_boot_debug_show(struct seq_file *s, void *data)
  227. {
  228. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/dev_boot\n");
  229. seq_puts(s, "<action> can be one of below:\n");
  230. seq_puts(s, "on: turn on device power, assert WLAN_EN\n");
  231. seq_puts(s, "off: de-assert WLAN_EN, turn off device power\n");
  232. seq_puts(s, "enumerate: de-assert PERST, enumerate PCIe\n");
  233. seq_puts(s, "download: download FW and do QMI handshake with FW\n");
  234. seq_puts(s, "linkup: bring up PCIe link\n");
  235. seq_puts(s, "linkdown: bring down PCIe link\n");
  236. seq_puts(s, "powerup: full power on sequence to boot device, download FW and do QMI handshake with FW\n");
  237. seq_puts(s, "shutdown: full power off sequence to shutdown device\n");
  238. seq_puts(s, "assert: trigger firmware assert\n");
  239. seq_puts(s, "set_cbc_done: Set cold boot calibration done status\n");
  240. return 0;
  241. }
  242. static int cnss_dev_boot_debug_open(struct inode *inode, struct file *file)
  243. {
  244. return single_open(file, cnss_dev_boot_debug_show, inode->i_private);
  245. }
  246. static const struct file_operations cnss_dev_boot_debug_fops = {
  247. .read = seq_read,
  248. .write = cnss_dev_boot_debug_write,
  249. .release = single_release,
  250. .open = cnss_dev_boot_debug_open,
  251. .owner = THIS_MODULE,
  252. .llseek = seq_lseek,
  253. };
  254. static int cnss_reg_read_debug_show(struct seq_file *s, void *data)
  255. {
  256. struct cnss_plat_data *plat_priv = s->private;
  257. mutex_lock(&plat_priv->dev_lock);
  258. if (!plat_priv->diag_reg_read_buf) {
  259. seq_puts(s, "\nUsage: echo <mem_type> <offset> <data_len> > <debugfs_path>/cnss/reg_read\n");
  260. seq_puts(s, "Use mem_type = 0xff for register read by IO access, data_len will be ignored\n");
  261. seq_puts(s, "Use mem_type = 0xfe for register read by raw IO access which skips sanity checks, data_len will be ignored\n");
  262. seq_puts(s, "Use other mem_type for register read by QMI\n");
  263. mutex_unlock(&plat_priv->dev_lock);
  264. return 0;
  265. }
  266. seq_printf(s, "\nRegister read, address: 0x%x memory type: 0x%x length: 0x%x\n\n",
  267. plat_priv->diag_reg_read_addr,
  268. plat_priv->diag_reg_read_mem_type,
  269. plat_priv->diag_reg_read_len);
  270. seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 32, 4,
  271. plat_priv->diag_reg_read_buf,
  272. plat_priv->diag_reg_read_len, false);
  273. plat_priv->diag_reg_read_len = 0;
  274. kfree(plat_priv->diag_reg_read_buf);
  275. plat_priv->diag_reg_read_buf = NULL;
  276. mutex_unlock(&plat_priv->dev_lock);
  277. return 0;
  278. }
  279. static ssize_t cnss_reg_read_debug_write(struct file *fp,
  280. const char __user *user_buf,
  281. size_t count, loff_t *off)
  282. {
  283. struct cnss_plat_data *plat_priv =
  284. ((struct seq_file *)fp->private_data)->private;
  285. char buf[64];
  286. char *sptr, *token;
  287. unsigned int len = 0;
  288. u32 reg_offset, mem_type;
  289. u32 data_len = 0, reg_val = 0;
  290. u8 *reg_buf = NULL;
  291. const char *delim = " ";
  292. int ret = 0;
  293. len = min(count, sizeof(buf) - 1);
  294. if (copy_from_user(buf, user_buf, len))
  295. return -EFAULT;
  296. buf[len] = '\0';
  297. sptr = buf;
  298. token = strsep(&sptr, delim);
  299. if (!token)
  300. return -EINVAL;
  301. if (!sptr)
  302. return -EINVAL;
  303. if (kstrtou32(token, 0, &mem_type))
  304. return -EINVAL;
  305. token = strsep(&sptr, delim);
  306. if (!token)
  307. return -EINVAL;
  308. if (!sptr)
  309. return -EINVAL;
  310. if (kstrtou32(token, 0, &reg_offset))
  311. return -EINVAL;
  312. token = strsep(&sptr, delim);
  313. if (!token)
  314. return -EINVAL;
  315. if (kstrtou32(token, 0, &data_len))
  316. return -EINVAL;
  317. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  318. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  319. ret = cnss_bus_debug_reg_read(plat_priv, reg_offset, &reg_val,
  320. mem_type ==
  321. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  322. if (ret)
  323. return ret;
  324. cnss_pr_dbg("Read 0x%x from register offset 0x%x\n", reg_val,
  325. reg_offset);
  326. return count;
  327. }
  328. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  329. cnss_pr_err("Firmware is not ready yet\n");
  330. return -EINVAL;
  331. }
  332. mutex_lock(&plat_priv->dev_lock);
  333. kfree(plat_priv->diag_reg_read_buf);
  334. plat_priv->diag_reg_read_buf = NULL;
  335. reg_buf = kzalloc(data_len, GFP_KERNEL);
  336. if (!reg_buf) {
  337. mutex_unlock(&plat_priv->dev_lock);
  338. return -ENOMEM;
  339. }
  340. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, reg_offset,
  341. mem_type, data_len,
  342. reg_buf);
  343. if (ret) {
  344. kfree(reg_buf);
  345. mutex_unlock(&plat_priv->dev_lock);
  346. return ret;
  347. }
  348. plat_priv->diag_reg_read_addr = reg_offset;
  349. plat_priv->diag_reg_read_mem_type = mem_type;
  350. plat_priv->diag_reg_read_len = data_len;
  351. plat_priv->diag_reg_read_buf = reg_buf;
  352. mutex_unlock(&plat_priv->dev_lock);
  353. return count;
  354. }
  355. static int cnss_reg_read_debug_open(struct inode *inode, struct file *file)
  356. {
  357. return single_open(file, cnss_reg_read_debug_show, inode->i_private);
  358. }
  359. static const struct file_operations cnss_reg_read_debug_fops = {
  360. .read = seq_read,
  361. .write = cnss_reg_read_debug_write,
  362. .open = cnss_reg_read_debug_open,
  363. .owner = THIS_MODULE,
  364. .llseek = seq_lseek,
  365. };
  366. static int cnss_reg_write_debug_show(struct seq_file *s, void *data)
  367. {
  368. seq_puts(s, "\nUsage: echo <mem_type> <offset> <reg_val> > <debugfs_path>/cnss/reg_write\n");
  369. seq_puts(s, "Use mem_type = 0xff for register write by IO access\n");
  370. seq_puts(s, "Use mem_type = 0xfe for register write by raw IO access which skips sanity checks\n");
  371. seq_puts(s, "Use other mem_type for register write by QMI\n");
  372. return 0;
  373. }
  374. static ssize_t cnss_reg_write_debug_write(struct file *fp,
  375. const char __user *user_buf,
  376. size_t count, loff_t *off)
  377. {
  378. struct cnss_plat_data *plat_priv =
  379. ((struct seq_file *)fp->private_data)->private;
  380. char buf[64];
  381. char *sptr, *token;
  382. unsigned int len = 0;
  383. u32 reg_offset, mem_type, reg_val;
  384. const char *delim = " ";
  385. int ret = 0;
  386. len = min(count, sizeof(buf) - 1);
  387. if (copy_from_user(buf, user_buf, len))
  388. return -EFAULT;
  389. buf[len] = '\0';
  390. sptr = buf;
  391. token = strsep(&sptr, delim);
  392. if (!token)
  393. return -EINVAL;
  394. if (!sptr)
  395. return -EINVAL;
  396. if (kstrtou32(token, 0, &mem_type))
  397. return -EINVAL;
  398. token = strsep(&sptr, delim);
  399. if (!token)
  400. return -EINVAL;
  401. if (!sptr)
  402. return -EINVAL;
  403. if (kstrtou32(token, 0, &reg_offset))
  404. return -EINVAL;
  405. token = strsep(&sptr, delim);
  406. if (!token)
  407. return -EINVAL;
  408. if (kstrtou32(token, 0, &reg_val))
  409. return -EINVAL;
  410. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  411. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  412. ret = cnss_bus_debug_reg_write(plat_priv, reg_offset, reg_val,
  413. mem_type ==
  414. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  415. if (ret)
  416. return ret;
  417. cnss_pr_dbg("Wrote 0x%x to register offset 0x%x\n", reg_val,
  418. reg_offset);
  419. return count;
  420. }
  421. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  422. cnss_pr_err("Firmware is not ready yet\n");
  423. return -EINVAL;
  424. }
  425. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, reg_offset, mem_type,
  426. sizeof(u32),
  427. (u8 *)&reg_val);
  428. if (ret)
  429. return ret;
  430. return count;
  431. }
  432. static int cnss_reg_write_debug_open(struct inode *inode, struct file *file)
  433. {
  434. return single_open(file, cnss_reg_write_debug_show, inode->i_private);
  435. }
  436. static const struct file_operations cnss_reg_write_debug_fops = {
  437. .read = seq_read,
  438. .write = cnss_reg_write_debug_write,
  439. .open = cnss_reg_write_debug_open,
  440. .owner = THIS_MODULE,
  441. .llseek = seq_lseek,
  442. };
  443. static ssize_t cnss_runtime_pm_debug_write(struct file *fp,
  444. const char __user *user_buf,
  445. size_t count, loff_t *off)
  446. {
  447. struct cnss_plat_data *plat_priv =
  448. ((struct seq_file *)fp->private_data)->private;
  449. struct cnss_pci_data *pci_priv;
  450. char buf[64];
  451. char *cmd;
  452. unsigned int len = 0;
  453. int ret = 0;
  454. if (!plat_priv)
  455. return -ENODEV;
  456. pci_priv = plat_priv->bus_priv;
  457. if (!pci_priv)
  458. return -ENODEV;
  459. len = min(count, sizeof(buf) - 1);
  460. if (copy_from_user(buf, user_buf, len))
  461. return -EFAULT;
  462. buf[len] = '\0';
  463. cmd = buf;
  464. if (sysfs_streq(cmd, "usage_count")) {
  465. cnss_pci_pm_runtime_show_usage_count(pci_priv);
  466. } else if (sysfs_streq(cmd, "request_resume")) {
  467. ret = cnss_pci_pm_request_resume(pci_priv);
  468. } else if (sysfs_streq(cmd, "resume")) {
  469. ret = cnss_pci_pm_runtime_resume(pci_priv);
  470. } else if (sysfs_streq(cmd, "get")) {
  471. ret = cnss_pci_pm_runtime_get(pci_priv, RTPM_ID_CNSS);
  472. } else if (sysfs_streq(cmd, "get_noresume")) {
  473. cnss_pci_pm_runtime_get_noresume(pci_priv, RTPM_ID_CNSS);
  474. } else if (sysfs_streq(cmd, "put_autosuspend")) {
  475. ret = cnss_pci_pm_runtime_put_autosuspend(pci_priv,
  476. RTPM_ID_CNSS);
  477. } else if (sysfs_streq(cmd, "put_noidle")) {
  478. cnss_pci_pm_runtime_put_noidle(pci_priv, RTPM_ID_CNSS);
  479. } else if (sysfs_streq(cmd, "mark_last_busy")) {
  480. cnss_pci_pm_runtime_mark_last_busy(pci_priv);
  481. } else if (sysfs_streq(cmd, "resume_bus")) {
  482. cnss_pci_resume_bus(pci_priv);
  483. } else if (sysfs_streq(cmd, "suspend_bus")) {
  484. cnss_pci_suspend_bus(pci_priv);
  485. } else {
  486. cnss_pr_err("Runtime PM debugfs command is invalid\n");
  487. ret = -EINVAL;
  488. }
  489. if (ret < 0)
  490. return ret;
  491. return count;
  492. }
  493. static int cnss_runtime_pm_debug_show(struct seq_file *s, void *data)
  494. {
  495. struct cnss_plat_data *plat_priv = s->private;
  496. struct cnss_pci_data *pci_priv;
  497. int i;
  498. if (!plat_priv)
  499. return -ENODEV;
  500. pci_priv = plat_priv->bus_priv;
  501. if (!pci_priv)
  502. return -ENODEV;
  503. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/runtime_pm\n");
  504. seq_puts(s, "<action> can be one of below:\n");
  505. seq_puts(s, "usage_count: get runtime PM usage count\n");
  506. seq_puts(s, "reques_resume: do async runtime PM resume\n");
  507. seq_puts(s, "resume: do sync runtime PM resume\n");
  508. seq_puts(s, "get: do runtime PM get\n");
  509. seq_puts(s, "get_noresume: do runtime PM get noresume\n");
  510. seq_puts(s, "put_noidle: do runtime PM put noidle\n");
  511. seq_puts(s, "put_autosuspend: do runtime PM put autosuspend\n");
  512. seq_puts(s, "mark_last_busy: do runtime PM mark last busy\n");
  513. seq_puts(s, "resume_bus: do bus resume only\n");
  514. seq_puts(s, "suspend_bus: do bus suspend only\n");
  515. seq_puts(s, "\nStats:\n");
  516. seq_printf(s, "%s: %u\n", "get count",
  517. atomic_read(&pci_priv->pm_stats.runtime_get));
  518. seq_printf(s, "%s: %u\n", "put count",
  519. atomic_read(&pci_priv->pm_stats.runtime_put));
  520. seq_printf(s, "%-10s%-10s%-10s%-15s%-15s\n",
  521. "id:", "get", "put", "get time(us)", "put time(us)");
  522. for (i = 0; i < RTPM_ID_MAX; i++) {
  523. seq_printf(s, "%d%-9s", i, ":");
  524. seq_printf(s, "%-10d",
  525. atomic_read(&pci_priv->pm_stats.runtime_get_id[i]));
  526. seq_printf(s, "%-10d",
  527. atomic_read(&pci_priv->pm_stats.runtime_put_id[i]));
  528. seq_printf(s, "%-15llu",
  529. pci_priv->pm_stats.runtime_get_timestamp_id[i]);
  530. seq_printf(s, "%-15llu\n",
  531. pci_priv->pm_stats.runtime_put_timestamp_id[i]);
  532. }
  533. return 0;
  534. }
  535. static int cnss_runtime_pm_debug_open(struct inode *inode, struct file *file)
  536. {
  537. return single_open(file, cnss_runtime_pm_debug_show, inode->i_private);
  538. }
  539. static const struct file_operations cnss_runtime_pm_debug_fops = {
  540. .read = seq_read,
  541. .write = cnss_runtime_pm_debug_write,
  542. .open = cnss_runtime_pm_debug_open,
  543. .owner = THIS_MODULE,
  544. .llseek = seq_lseek,
  545. };
  546. static ssize_t cnss_control_params_debug_write(struct file *fp,
  547. const char __user *user_buf,
  548. size_t count, loff_t *off)
  549. {
  550. struct cnss_plat_data *plat_priv =
  551. ((struct seq_file *)fp->private_data)->private;
  552. char buf[64];
  553. char *sptr, *token;
  554. char *cmd;
  555. u32 val;
  556. unsigned int len = 0;
  557. const char *delim = " ";
  558. if (!plat_priv)
  559. return -ENODEV;
  560. len = min(count, sizeof(buf) - 1);
  561. if (copy_from_user(buf, user_buf, len))
  562. return -EFAULT;
  563. buf[len] = '\0';
  564. sptr = buf;
  565. token = strsep(&sptr, delim);
  566. if (!token)
  567. return -EINVAL;
  568. if (!sptr)
  569. return -EINVAL;
  570. cmd = token;
  571. token = strsep(&sptr, delim);
  572. if (!token)
  573. return -EINVAL;
  574. if (kstrtou32(token, 0, &val))
  575. return -EINVAL;
  576. if (strcmp(cmd, "quirks") == 0)
  577. plat_priv->ctrl_params.quirks = val;
  578. else if (strcmp(cmd, "mhi_timeout") == 0)
  579. plat_priv->ctrl_params.mhi_timeout = val;
  580. else if (strcmp(cmd, "mhi_m2_timeout") == 0)
  581. plat_priv->ctrl_params.mhi_m2_timeout = val;
  582. else if (strcmp(cmd, "qmi_timeout") == 0)
  583. plat_priv->ctrl_params.qmi_timeout = val;
  584. else if (strcmp(cmd, "bdf_type") == 0)
  585. plat_priv->ctrl_params.bdf_type = val;
  586. else if (strcmp(cmd, "time_sync_period") == 0)
  587. plat_priv->ctrl_params.time_sync_period = val;
  588. else
  589. return -EINVAL;
  590. return count;
  591. }
  592. static int cnss_show_quirks_state(struct seq_file *s,
  593. struct cnss_plat_data *plat_priv)
  594. {
  595. enum cnss_debug_quirks i;
  596. int skip = 0;
  597. unsigned long state;
  598. seq_printf(s, "quirks: 0x%lx (", plat_priv->ctrl_params.quirks);
  599. for (i = 0, state = plat_priv->ctrl_params.quirks;
  600. state != 0; state >>= 1, i++) {
  601. if (!(state & 0x1))
  602. continue;
  603. if (skip++)
  604. seq_puts(s, " | ");
  605. switch (i) {
  606. case LINK_DOWN_SELF_RECOVERY:
  607. seq_puts(s, "LINK_DOWN_SELF_RECOVERY");
  608. continue;
  609. case SKIP_DEVICE_BOOT:
  610. seq_puts(s, "SKIP_DEVICE_BOOT");
  611. continue;
  612. case USE_CORE_ONLY_FW:
  613. seq_puts(s, "USE_CORE_ONLY_FW");
  614. continue;
  615. case SKIP_RECOVERY:
  616. seq_puts(s, "SKIP_RECOVERY");
  617. continue;
  618. case QMI_BYPASS:
  619. seq_puts(s, "QMI_BYPASS");
  620. continue;
  621. case ENABLE_WALTEST:
  622. seq_puts(s, "WALTEST");
  623. continue;
  624. case ENABLE_PCI_LINK_DOWN_PANIC:
  625. seq_puts(s, "PCI_LINK_DOWN_PANIC");
  626. continue;
  627. case FBC_BYPASS:
  628. seq_puts(s, "FBC_BYPASS");
  629. continue;
  630. case ENABLE_DAEMON_SUPPORT:
  631. seq_puts(s, "DAEMON_SUPPORT");
  632. continue;
  633. case DISABLE_DRV:
  634. seq_puts(s, "DISABLE_DRV");
  635. continue;
  636. case DISABLE_IO_COHERENCY:
  637. seq_puts(s, "DISABLE_IO_COHERENCY");
  638. continue;
  639. case IGNORE_PCI_LINK_FAILURE:
  640. seq_puts(s, "IGNORE_PCI_LINK_FAILURE");
  641. continue;
  642. case DISABLE_TIME_SYNC:
  643. seq_puts(s, "DISABLE_TIME_SYNC");
  644. continue;
  645. }
  646. seq_printf(s, "UNKNOWN-%d", i);
  647. }
  648. seq_puts(s, ")\n");
  649. return 0;
  650. }
  651. static int cnss_control_params_debug_show(struct seq_file *s, void *data)
  652. {
  653. struct cnss_plat_data *cnss_priv = s->private;
  654. seq_puts(s, "\nUsage: echo <params_name> <value> > <debugfs_path>/cnss/control_params\n");
  655. seq_puts(s, "<params_name> can be one of below:\n");
  656. seq_puts(s, "quirks: Debug quirks for driver\n");
  657. seq_puts(s, "mhi_timeout: Timeout for MHI operation in milliseconds\n");
  658. seq_puts(s, "qmi_timeout: Timeout for QMI message in milliseconds\n");
  659. seq_puts(s, "bdf_type: Type of board data file to be downloaded\n");
  660. seq_puts(s, "time_sync_period: Time period to do time sync with device in milliseconds\n");
  661. seq_puts(s, "\nCurrent value:\n");
  662. cnss_show_quirks_state(s, cnss_priv);
  663. seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout);
  664. seq_printf(s, "mhi_m2_timeout: %u\n",
  665. cnss_priv->ctrl_params.mhi_m2_timeout);
  666. seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout);
  667. seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type);
  668. seq_printf(s, "time_sync_period: %u\n",
  669. cnss_priv->ctrl_params.time_sync_period);
  670. return 0;
  671. }
  672. static int cnss_control_params_debug_open(struct inode *inode,
  673. struct file *file)
  674. {
  675. return single_open(file, cnss_control_params_debug_show,
  676. inode->i_private);
  677. }
  678. static const struct file_operations cnss_control_params_debug_fops = {
  679. .read = seq_read,
  680. .write = cnss_control_params_debug_write,
  681. .open = cnss_control_params_debug_open,
  682. .owner = THIS_MODULE,
  683. .llseek = seq_lseek,
  684. };
  685. static ssize_t cnss_dynamic_feature_write(struct file *fp,
  686. const char __user *user_buf,
  687. size_t count, loff_t *off)
  688. {
  689. struct cnss_plat_data *plat_priv =
  690. ((struct seq_file *)fp->private_data)->private;
  691. int ret = 0;
  692. u64 val;
  693. ret = kstrtou64_from_user(user_buf, count, 0, &val);
  694. if (ret)
  695. return ret;
  696. plat_priv->dynamic_feature = val;
  697. ret = cnss_wlfw_dynamic_feature_mask_send_sync(plat_priv);
  698. if (ret < 0)
  699. return ret;
  700. return count;
  701. }
  702. static int cnss_dynamic_feature_show(struct seq_file *s, void *data)
  703. {
  704. struct cnss_plat_data *cnss_priv = s->private;
  705. seq_printf(s, "dynamic_feature: 0x%llx\n", cnss_priv->dynamic_feature);
  706. return 0;
  707. }
  708. static int cnss_dynamic_feature_open(struct inode *inode,
  709. struct file *file)
  710. {
  711. return single_open(file, cnss_dynamic_feature_show,
  712. inode->i_private);
  713. }
  714. static const struct file_operations cnss_dynamic_feature_fops = {
  715. .read = seq_read,
  716. .write = cnss_dynamic_feature_write,
  717. .open = cnss_dynamic_feature_open,
  718. .owner = THIS_MODULE,
  719. .llseek = seq_lseek,
  720. };
  721. #ifdef CONFIG_DEBUG_FS
  722. #ifdef CONFIG_CNSS2_DEBUG
  723. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  724. {
  725. struct dentry *root_dentry = plat_priv->root_dentry;
  726. debugfs_create_file("dev_boot", 0600, root_dentry, plat_priv,
  727. &cnss_dev_boot_debug_fops);
  728. debugfs_create_file("reg_read", 0600, root_dentry, plat_priv,
  729. &cnss_reg_read_debug_fops);
  730. debugfs_create_file("reg_write", 0600, root_dentry, plat_priv,
  731. &cnss_reg_write_debug_fops);
  732. debugfs_create_file("runtime_pm", 0600, root_dentry, plat_priv,
  733. &cnss_runtime_pm_debug_fops);
  734. debugfs_create_file("control_params", 0600, root_dentry, plat_priv,
  735. &cnss_control_params_debug_fops);
  736. debugfs_create_file("dynamic_feature", 0600, root_dentry, plat_priv,
  737. &cnss_dynamic_feature_fops);
  738. return 0;
  739. }
  740. #else
  741. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  742. {
  743. return 0;
  744. }
  745. #endif
  746. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  747. {
  748. int ret = 0;
  749. struct dentry *root_dentry;
  750. root_dentry = debugfs_create_dir("cnss", 0);
  751. if (IS_ERR(root_dentry)) {
  752. ret = PTR_ERR(root_dentry);
  753. cnss_pr_err("Unable to create debugfs %d\n", ret);
  754. goto out;
  755. }
  756. plat_priv->root_dentry = root_dentry;
  757. debugfs_create_file("pin_connect_result", 0644, root_dentry, plat_priv,
  758. &cnss_pin_connect_fops);
  759. debugfs_create_file("stats", 0644, root_dentry, plat_priv,
  760. &cnss_stats_fops);
  761. cnss_create_debug_only_node(plat_priv);
  762. out:
  763. return ret;
  764. }
  765. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  766. {
  767. debugfs_remove_recursive(plat_priv->root_dentry);
  768. }
  769. #else
  770. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  771. {
  772. plat_priv->root_dentry = NULL;
  773. return 0;
  774. }
  775. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  776. {
  777. }
  778. #endif
  779. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  780. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  781. const char *log_level, char *fmt, ...)
  782. {
  783. struct va_format vaf;
  784. va_list va_args;
  785. va_start(va_args, fmt);
  786. vaf.fmt = fmt;
  787. vaf.va = &va_args;
  788. if (log_level)
  789. printk("%scnss: %pV", log_level, &vaf);
  790. ipc_log_string(log_ctx, "[%s] %s: %pV", process, fn, &vaf);
  791. va_end(va_args);
  792. }
  793. static int cnss_ipc_logging_init(void)
  794. {
  795. cnss_ipc_log_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  796. "cnss", 0);
  797. if (!cnss_ipc_log_context) {
  798. cnss_pr_err("Unable to create IPC log context\n");
  799. return -EINVAL;
  800. }
  801. cnss_ipc_log_long_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  802. "cnss-long", 0);
  803. if (!cnss_ipc_log_long_context) {
  804. cnss_pr_err("Unable to create IPC long log context\n");
  805. ipc_log_context_destroy(cnss_ipc_log_context);
  806. return -EINVAL;
  807. }
  808. return 0;
  809. }
  810. static void cnss_ipc_logging_deinit(void)
  811. {
  812. if (cnss_ipc_log_long_context) {
  813. ipc_log_context_destroy(cnss_ipc_log_long_context);
  814. cnss_ipc_log_long_context = NULL;
  815. }
  816. if (cnss_ipc_log_context) {
  817. ipc_log_context_destroy(cnss_ipc_log_context);
  818. cnss_ipc_log_context = NULL;
  819. }
  820. }
  821. #else
  822. static int cnss_ipc_logging_init(void) { return 0; }
  823. static void cnss_ipc_logging_deinit(void) {}
  824. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  825. const char *log_level, char *fmt, ...)
  826. {
  827. struct va_format vaf;
  828. va_list va_args;
  829. va_start(va_args, fmt);
  830. vaf.fmt = fmt;
  831. vaf.va = &va_args;
  832. if (log_level)
  833. printk("%scnss: %pV", log_level, &vaf);
  834. va_end(va_args);
  835. }
  836. #endif
  837. int cnss_debug_init(void)
  838. {
  839. return cnss_ipc_logging_init();
  840. }
  841. void cnss_debug_deinit(void)
  842. {
  843. cnss_ipc_logging_deinit();
  844. }