dp_tx.c 143 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. /* Flag to skip CCE classify when mesh or tid override enabled */
  52. #define DP_TX_SKIP_CCE_CLASSIFY \
  53. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  54. /* TODO Add support in TSO */
  55. #define DP_DESC_NUM_FRAG(x) 0
  56. /* disable TQM_BYPASS */
  57. #define TQM_BYPASS_WAR 0
  58. /* invalid peer id for reinject*/
  59. #define DP_INVALID_PEER 0XFFFE
  60. #define DP_RETRY_COUNT 7
  61. /*mapping between hal encrypt type and cdp_sec_type*/
  62. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  63. HAL_TX_ENCRYPT_TYPE_WEP_128,
  64. HAL_TX_ENCRYPT_TYPE_WEP_104,
  65. HAL_TX_ENCRYPT_TYPE_WEP_40,
  66. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  67. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  68. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  69. HAL_TX_ENCRYPT_TYPE_WAPI,
  70. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  71. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  72. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  73. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  74. qdf_export_symbol(sec_type_map);
  75. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  76. /**
  77. * dp_update_tx_desc_stats - Update the increase or decrease in
  78. * outstanding tx desc count
  79. * values on pdev and soc
  80. * @vdev: DP pdev handle
  81. *
  82. * Return: void
  83. */
  84. static inline void
  85. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  86. {
  87. int32_t tx_descs_cnt =
  88. qdf_atomic_read(&pdev->num_tx_outstanding);
  89. if (pdev->tx_descs_max < tx_descs_cnt)
  90. pdev->tx_descs_max = tx_descs_cnt;
  91. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  92. pdev->tx_descs_max);
  93. }
  94. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  95. static inline void
  96. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  97. {
  98. }
  99. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  100. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  101. static inline
  102. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  103. {
  104. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  105. QDF_DMA_TO_DEVICE,
  106. desc->nbuf->len);
  107. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  108. }
  109. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  110. {
  111. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  112. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  113. QDF_DMA_TO_DEVICE,
  114. desc->nbuf->len);
  115. }
  116. #else
  117. static inline
  118. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  119. {
  120. }
  121. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  122. {
  123. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  124. QDF_DMA_TO_DEVICE, desc->nbuf->len);
  125. }
  126. #endif
  127. #ifdef QCA_TX_LIMIT_CHECK
  128. /**
  129. * dp_tx_limit_check - Check if allocated tx descriptors reached
  130. * soc max limit and pdev max limit
  131. * @vdev: DP vdev handle
  132. *
  133. * Return: true if allocated tx descriptors reached max configured value, else
  134. * false
  135. */
  136. static inline bool
  137. dp_tx_limit_check(struct dp_vdev *vdev)
  138. {
  139. struct dp_pdev *pdev = vdev->pdev;
  140. struct dp_soc *soc = pdev->soc;
  141. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  142. soc->num_tx_allowed) {
  143. dp_tx_info("queued packets are more than max tx, drop the frame");
  144. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  145. return true;
  146. }
  147. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  148. pdev->num_tx_allowed) {
  149. dp_tx_info("queued packets are more than max tx, drop the frame");
  150. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  151. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  152. return true;
  153. }
  154. return false;
  155. }
  156. /**
  157. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  158. * reached soc max limit
  159. * @vdev: DP vdev handle
  160. *
  161. * Return: true if allocated tx descriptors reached max configured value, else
  162. * false
  163. */
  164. static inline bool
  165. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  166. {
  167. struct dp_pdev *pdev = vdev->pdev;
  168. struct dp_soc *soc = pdev->soc;
  169. if (qdf_atomic_read(&soc->num_tx_exception) >=
  170. soc->num_msdu_exception_desc) {
  171. dp_info("exc packets are more than max drop the exc pkt");
  172. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  173. return true;
  174. }
  175. return false;
  176. }
  177. /**
  178. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  179. * @vdev: DP pdev handle
  180. *
  181. * Return: void
  182. */
  183. static inline void
  184. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  185. {
  186. struct dp_soc *soc = pdev->soc;
  187. qdf_atomic_inc(&pdev->num_tx_outstanding);
  188. qdf_atomic_inc(&soc->num_tx_outstanding);
  189. dp_update_tx_desc_stats(pdev);
  190. }
  191. /**
  192. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  193. * @vdev: DP pdev handle
  194. *
  195. * Return: void
  196. */
  197. static inline void
  198. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  199. {
  200. struct dp_soc *soc = pdev->soc;
  201. qdf_atomic_dec(&pdev->num_tx_outstanding);
  202. qdf_atomic_dec(&soc->num_tx_outstanding);
  203. dp_update_tx_desc_stats(pdev);
  204. }
  205. #else //QCA_TX_LIMIT_CHECK
  206. static inline bool
  207. dp_tx_limit_check(struct dp_vdev *vdev)
  208. {
  209. return false;
  210. }
  211. static inline bool
  212. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  213. {
  214. return false;
  215. }
  216. static inline void
  217. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  218. {
  219. qdf_atomic_inc(&pdev->num_tx_outstanding);
  220. dp_update_tx_desc_stats(pdev);
  221. }
  222. static inline void
  223. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  224. {
  225. qdf_atomic_dec(&pdev->num_tx_outstanding);
  226. dp_update_tx_desc_stats(pdev);
  227. }
  228. #endif //QCA_TX_LIMIT_CHECK
  229. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  230. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  231. {
  232. enum dp_tx_event_type type;
  233. if (flags & DP_TX_DESC_FLAG_FLUSH)
  234. type = DP_TX_DESC_FLUSH;
  235. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  236. type = DP_TX_COMP_UNMAP_ERR;
  237. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  238. type = DP_TX_COMP_UNMAP;
  239. else
  240. type = DP_TX_DESC_UNMAP;
  241. return type;
  242. }
  243. static inline void
  244. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  245. qdf_nbuf_t skb, uint32_t sw_cookie,
  246. enum dp_tx_event_type type)
  247. {
  248. struct dp_tx_desc_event *entry;
  249. uint32_t idx;
  250. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  251. return;
  252. switch (type) {
  253. case DP_TX_COMP_UNMAP:
  254. case DP_TX_COMP_UNMAP_ERR:
  255. case DP_TX_COMP_MSDU_EXT:
  256. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  257. DP_TX_COMP_HISTORY_SIZE);
  258. entry = &soc->tx_comp_history->entry[idx];
  259. break;
  260. case DP_TX_DESC_MAP:
  261. case DP_TX_DESC_UNMAP:
  262. case DP_TX_DESC_COOKIE:
  263. case DP_TX_DESC_FLUSH:
  264. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  265. DP_TX_TCL_HISTORY_SIZE);
  266. entry = &soc->tx_tcl_history->entry[idx];
  267. break;
  268. default:
  269. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  270. return;
  271. }
  272. entry->skb = skb;
  273. entry->paddr = paddr;
  274. entry->sw_cookie = sw_cookie;
  275. entry->type = type;
  276. entry->ts = qdf_get_log_timestamp();
  277. }
  278. static inline void
  279. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  280. struct qdf_tso_seg_elem_t *tso_seg,
  281. qdf_nbuf_t skb, uint32_t sw_cookie,
  282. enum dp_tx_event_type type)
  283. {
  284. int i;
  285. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  286. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  287. skb, sw_cookie, type);
  288. }
  289. if (!tso_seg->next)
  290. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  291. skb, 0xFFFFFFFF, type);
  292. }
  293. static inline void
  294. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  295. qdf_nbuf_t skb, uint32_t sw_cookie,
  296. enum dp_tx_event_type type)
  297. {
  298. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  299. uint32_t num_segs = tso_info.num_segs;
  300. while (num_segs) {
  301. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  302. curr_seg = curr_seg->next;
  303. num_segs--;
  304. }
  305. }
  306. #else
  307. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  308. {
  309. return DP_TX_DESC_INVAL_EVT;
  310. }
  311. static inline void
  312. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  313. qdf_nbuf_t skb, uint32_t sw_cookie,
  314. enum dp_tx_event_type type)
  315. {
  316. }
  317. static inline void
  318. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  319. struct qdf_tso_seg_elem_t *tso_seg,
  320. qdf_nbuf_t skb, uint32_t sw_cookie,
  321. enum dp_tx_event_type type)
  322. {
  323. }
  324. static inline void
  325. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  326. qdf_nbuf_t skb, uint32_t sw_cookie,
  327. enum dp_tx_event_type type)
  328. {
  329. }
  330. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  331. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  332. /**
  333. * dp_is_tput_high() - Check if throughput is high
  334. *
  335. * @soc - core txrx main context
  336. *
  337. * The current function is based of the RTPM tput policy variable where RTPM is
  338. * avoided based on throughput.
  339. */
  340. static inline int dp_is_tput_high(struct dp_soc *soc)
  341. {
  342. return dp_get_rtpm_tput_policy_requirement(soc);
  343. }
  344. #if defined(FEATURE_TSO)
  345. /**
  346. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  347. *
  348. * @soc - core txrx main context
  349. * @seg_desc - tso segment descriptor
  350. * @num_seg_desc - tso number segment descriptor
  351. */
  352. static void dp_tx_tso_unmap_segment(
  353. struct dp_soc *soc,
  354. struct qdf_tso_seg_elem_t *seg_desc,
  355. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  356. {
  357. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  358. if (qdf_unlikely(!seg_desc)) {
  359. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  360. __func__, __LINE__);
  361. qdf_assert(0);
  362. } else if (qdf_unlikely(!num_seg_desc)) {
  363. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  364. __func__, __LINE__);
  365. qdf_assert(0);
  366. } else {
  367. bool is_last_seg;
  368. /* no tso segment left to do dma unmap */
  369. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  370. return;
  371. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  372. true : false;
  373. qdf_nbuf_unmap_tso_segment(soc->osdev,
  374. seg_desc, is_last_seg);
  375. num_seg_desc->num_seg.tso_cmn_num_seg--;
  376. }
  377. }
  378. /**
  379. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  380. * back to the freelist
  381. *
  382. * @soc - soc device handle
  383. * @tx_desc - Tx software descriptor
  384. */
  385. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  386. struct dp_tx_desc_s *tx_desc)
  387. {
  388. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  389. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  390. dp_tx_err("SO desc is NULL!");
  391. qdf_assert(0);
  392. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  393. dp_tx_err("TSO num desc is NULL!");
  394. qdf_assert(0);
  395. } else {
  396. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  397. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  398. msdu_ext_desc->tso_num_desc;
  399. /* Add the tso num segment into the free list */
  400. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  401. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  402. tx_desc->msdu_ext_desc->
  403. tso_num_desc);
  404. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  405. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  406. }
  407. /* Add the tso segment into the free list*/
  408. dp_tx_tso_desc_free(soc,
  409. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  410. tso_desc);
  411. tx_desc->msdu_ext_desc->tso_desc = NULL;
  412. }
  413. }
  414. #else
  415. static void dp_tx_tso_unmap_segment(
  416. struct dp_soc *soc,
  417. struct qdf_tso_seg_elem_t *seg_desc,
  418. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  419. {
  420. }
  421. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  422. struct dp_tx_desc_s *tx_desc)
  423. {
  424. }
  425. #endif
  426. /**
  427. * dp_tx_desc_release() - Release Tx Descriptor
  428. * @tx_desc : Tx Descriptor
  429. * @desc_pool_id: Descriptor Pool ID
  430. *
  431. * Deallocate all resources attached to Tx descriptor and free the Tx
  432. * descriptor.
  433. *
  434. * Return:
  435. */
  436. static void
  437. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  438. {
  439. struct dp_pdev *pdev = tx_desc->pdev;
  440. struct dp_soc *soc;
  441. uint8_t comp_status = 0;
  442. qdf_assert(pdev);
  443. soc = pdev->soc;
  444. dp_tx_outstanding_dec(pdev);
  445. if (tx_desc->msdu_ext_desc) {
  446. if (tx_desc->frm_type == dp_tx_frm_tso)
  447. dp_tx_tso_desc_release(soc, tx_desc);
  448. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  449. dp_tx_me_free_buf(tx_desc->pdev,
  450. tx_desc->msdu_ext_desc->me_buffer);
  451. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  452. }
  453. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  454. qdf_atomic_dec(&soc->num_tx_exception);
  455. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  456. tx_desc->buffer_src)
  457. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  458. soc->hal_soc);
  459. else
  460. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  461. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  462. tx_desc->id, comp_status,
  463. qdf_atomic_read(&pdev->num_tx_outstanding));
  464. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  465. return;
  466. }
  467. /**
  468. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  469. * @vdev: DP vdev Handle
  470. * @nbuf: skb
  471. * @msdu_info: msdu_info required to create HTT metadata
  472. *
  473. * Prepares and fills HTT metadata in the frame pre-header for special frames
  474. * that should be transmitted using varying transmit parameters.
  475. * There are 2 VDEV modes that currently needs this special metadata -
  476. * 1) Mesh Mode
  477. * 2) DSRC Mode
  478. *
  479. * Return: HTT metadata size
  480. *
  481. */
  482. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  483. struct dp_tx_msdu_info_s *msdu_info)
  484. {
  485. uint32_t *meta_data = msdu_info->meta_data;
  486. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  487. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  488. uint8_t htt_desc_size;
  489. /* Size rounded of multiple of 8 bytes */
  490. uint8_t htt_desc_size_aligned;
  491. uint8_t *hdr = NULL;
  492. /*
  493. * Metadata - HTT MSDU Extension header
  494. */
  495. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  496. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  497. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  498. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  499. meta_data[0])) {
  500. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  501. htt_desc_size_aligned)) {
  502. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  503. htt_desc_size_aligned);
  504. if (!nbuf) {
  505. /*
  506. * qdf_nbuf_realloc_headroom won't do skb_clone
  507. * as skb_realloc_headroom does. so, no free is
  508. * needed here.
  509. */
  510. DP_STATS_INC(vdev,
  511. tx_i.dropped.headroom_insufficient,
  512. 1);
  513. qdf_print(" %s[%d] skb_realloc_headroom failed",
  514. __func__, __LINE__);
  515. return 0;
  516. }
  517. }
  518. /* Fill and add HTT metaheader */
  519. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  520. if (!hdr) {
  521. dp_tx_err("Error in filling HTT metadata");
  522. return 0;
  523. }
  524. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  525. } else if (vdev->opmode == wlan_op_mode_ocb) {
  526. /* Todo - Add support for DSRC */
  527. }
  528. return htt_desc_size_aligned;
  529. }
  530. /**
  531. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  532. * @tso_seg: TSO segment to process
  533. * @ext_desc: Pointer to MSDU extension descriptor
  534. *
  535. * Return: void
  536. */
  537. #if defined(FEATURE_TSO)
  538. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  539. void *ext_desc)
  540. {
  541. uint8_t num_frag;
  542. uint32_t tso_flags;
  543. /*
  544. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  545. * tcp_flag_mask
  546. *
  547. * Checksum enable flags are set in TCL descriptor and not in Extension
  548. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  549. */
  550. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  551. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  552. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  553. tso_seg->tso_flags.ip_len);
  554. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  555. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  556. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  557. uint32_t lo = 0;
  558. uint32_t hi = 0;
  559. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  560. (tso_seg->tso_frags[num_frag].length));
  561. qdf_dmaaddr_to_32s(
  562. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  563. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  564. tso_seg->tso_frags[num_frag].length);
  565. }
  566. return;
  567. }
  568. #else
  569. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  570. void *ext_desc)
  571. {
  572. return;
  573. }
  574. #endif
  575. #if defined(FEATURE_TSO)
  576. /**
  577. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  578. * allocated and free them
  579. *
  580. * @soc: soc handle
  581. * @free_seg: list of tso segments
  582. * @msdu_info: msdu descriptor
  583. *
  584. * Return - void
  585. */
  586. static void dp_tx_free_tso_seg_list(
  587. struct dp_soc *soc,
  588. struct qdf_tso_seg_elem_t *free_seg,
  589. struct dp_tx_msdu_info_s *msdu_info)
  590. {
  591. struct qdf_tso_seg_elem_t *next_seg;
  592. while (free_seg) {
  593. next_seg = free_seg->next;
  594. dp_tx_tso_desc_free(soc,
  595. msdu_info->tx_queue.desc_pool_id,
  596. free_seg);
  597. free_seg = next_seg;
  598. }
  599. }
  600. /**
  601. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  602. * allocated and free them
  603. *
  604. * @soc: soc handle
  605. * @free_num_seg: list of tso number segments
  606. * @msdu_info: msdu descriptor
  607. * Return - void
  608. */
  609. static void dp_tx_free_tso_num_seg_list(
  610. struct dp_soc *soc,
  611. struct qdf_tso_num_seg_elem_t *free_num_seg,
  612. struct dp_tx_msdu_info_s *msdu_info)
  613. {
  614. struct qdf_tso_num_seg_elem_t *next_num_seg;
  615. while (free_num_seg) {
  616. next_num_seg = free_num_seg->next;
  617. dp_tso_num_seg_free(soc,
  618. msdu_info->tx_queue.desc_pool_id,
  619. free_num_seg);
  620. free_num_seg = next_num_seg;
  621. }
  622. }
  623. /**
  624. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  625. * do dma unmap for each segment
  626. *
  627. * @soc: soc handle
  628. * @free_seg: list of tso segments
  629. * @num_seg_desc: tso number segment descriptor
  630. *
  631. * Return - void
  632. */
  633. static void dp_tx_unmap_tso_seg_list(
  634. struct dp_soc *soc,
  635. struct qdf_tso_seg_elem_t *free_seg,
  636. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  637. {
  638. struct qdf_tso_seg_elem_t *next_seg;
  639. if (qdf_unlikely(!num_seg_desc)) {
  640. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  641. return;
  642. }
  643. while (free_seg) {
  644. next_seg = free_seg->next;
  645. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  646. free_seg = next_seg;
  647. }
  648. }
  649. #ifdef FEATURE_TSO_STATS
  650. /**
  651. * dp_tso_get_stats_idx: Retrieve the tso packet id
  652. * @pdev - pdev handle
  653. *
  654. * Return: id
  655. */
  656. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  657. {
  658. uint32_t stats_idx;
  659. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  660. % CDP_MAX_TSO_PACKETS);
  661. return stats_idx;
  662. }
  663. #else
  664. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  665. {
  666. return 0;
  667. }
  668. #endif /* FEATURE_TSO_STATS */
  669. /**
  670. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  671. * free the tso segments descriptor and
  672. * tso num segments descriptor
  673. *
  674. * @soc: soc handle
  675. * @msdu_info: msdu descriptor
  676. * @tso_seg_unmap: flag to show if dma unmap is necessary
  677. *
  678. * Return - void
  679. */
  680. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  681. struct dp_tx_msdu_info_s *msdu_info,
  682. bool tso_seg_unmap)
  683. {
  684. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  685. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  686. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  687. tso_info->tso_num_seg_list;
  688. /* do dma unmap for each segment */
  689. if (tso_seg_unmap)
  690. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  691. /* free all tso number segment descriptor though looks only have 1 */
  692. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  693. /* free all tso segment descriptor */
  694. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  695. }
  696. /**
  697. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  698. * @vdev: virtual device handle
  699. * @msdu: network buffer
  700. * @msdu_info: meta data associated with the msdu
  701. *
  702. * Return: QDF_STATUS_SUCCESS success
  703. */
  704. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  705. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  706. {
  707. struct qdf_tso_seg_elem_t *tso_seg;
  708. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  709. struct dp_soc *soc = vdev->pdev->soc;
  710. struct dp_pdev *pdev = vdev->pdev;
  711. struct qdf_tso_info_t *tso_info;
  712. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  713. tso_info = &msdu_info->u.tso_info;
  714. tso_info->curr_seg = NULL;
  715. tso_info->tso_seg_list = NULL;
  716. tso_info->num_segs = num_seg;
  717. msdu_info->frm_type = dp_tx_frm_tso;
  718. tso_info->tso_num_seg_list = NULL;
  719. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  720. while (num_seg) {
  721. tso_seg = dp_tx_tso_desc_alloc(
  722. soc, msdu_info->tx_queue.desc_pool_id);
  723. if (tso_seg) {
  724. tso_seg->next = tso_info->tso_seg_list;
  725. tso_info->tso_seg_list = tso_seg;
  726. num_seg--;
  727. } else {
  728. dp_err_rl("Failed to alloc tso seg desc");
  729. DP_STATS_INC_PKT(vdev->pdev,
  730. tso_stats.tso_no_mem_dropped, 1,
  731. qdf_nbuf_len(msdu));
  732. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  733. return QDF_STATUS_E_NOMEM;
  734. }
  735. }
  736. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  737. tso_num_seg = dp_tso_num_seg_alloc(soc,
  738. msdu_info->tx_queue.desc_pool_id);
  739. if (tso_num_seg) {
  740. tso_num_seg->next = tso_info->tso_num_seg_list;
  741. tso_info->tso_num_seg_list = tso_num_seg;
  742. } else {
  743. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  744. __func__);
  745. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  746. return QDF_STATUS_E_NOMEM;
  747. }
  748. msdu_info->num_seg =
  749. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  750. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  751. msdu_info->num_seg);
  752. if (!(msdu_info->num_seg)) {
  753. /*
  754. * Free allocated TSO seg desc and number seg desc,
  755. * do unmap for segments if dma map has done.
  756. */
  757. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  758. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  759. return QDF_STATUS_E_INVAL;
  760. }
  761. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  762. msdu, 0, DP_TX_DESC_MAP);
  763. tso_info->curr_seg = tso_info->tso_seg_list;
  764. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  765. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  766. msdu, msdu_info->num_seg);
  767. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  768. tso_info->msdu_stats_idx);
  769. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  770. return QDF_STATUS_SUCCESS;
  771. }
  772. #else
  773. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  774. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  775. {
  776. return QDF_STATUS_E_NOMEM;
  777. }
  778. #endif
  779. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  780. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  781. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  782. /**
  783. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  784. * @vdev: DP Vdev handle
  785. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  786. * @desc_pool_id: Descriptor Pool ID
  787. *
  788. * Return:
  789. */
  790. static
  791. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  792. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  793. {
  794. uint8_t i;
  795. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  796. struct dp_tx_seg_info_s *seg_info;
  797. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  798. struct dp_soc *soc = vdev->pdev->soc;
  799. /* Allocate an extension descriptor */
  800. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  801. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  802. if (!msdu_ext_desc) {
  803. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  804. return NULL;
  805. }
  806. if (msdu_info->exception_fw &&
  807. qdf_unlikely(vdev->mesh_vdev)) {
  808. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  809. &msdu_info->meta_data[0],
  810. sizeof(struct htt_tx_msdu_desc_ext2_t));
  811. qdf_atomic_inc(&soc->num_tx_exception);
  812. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  813. }
  814. switch (msdu_info->frm_type) {
  815. case dp_tx_frm_sg:
  816. case dp_tx_frm_me:
  817. case dp_tx_frm_raw:
  818. seg_info = msdu_info->u.sg_info.curr_seg;
  819. /* Update the buffer pointers in MSDU Extension Descriptor */
  820. for (i = 0; i < seg_info->frag_cnt; i++) {
  821. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  822. seg_info->frags[i].paddr_lo,
  823. seg_info->frags[i].paddr_hi,
  824. seg_info->frags[i].len);
  825. }
  826. break;
  827. case dp_tx_frm_tso:
  828. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  829. &cached_ext_desc[0]);
  830. break;
  831. default:
  832. break;
  833. }
  834. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  835. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  836. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  837. msdu_ext_desc->vaddr);
  838. return msdu_ext_desc;
  839. }
  840. /**
  841. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  842. *
  843. * @skb: skb to be traced
  844. * @msdu_id: msdu_id of the packet
  845. * @vdev_id: vdev_id of the packet
  846. *
  847. * Return: None
  848. */
  849. #ifdef DP_DISABLE_TX_PKT_TRACE
  850. static void dp_tx_trace_pkt(struct dp_soc *soc,
  851. qdf_nbuf_t skb, uint16_t msdu_id,
  852. uint8_t vdev_id)
  853. {
  854. }
  855. #else
  856. static void dp_tx_trace_pkt(struct dp_soc *soc,
  857. qdf_nbuf_t skb, uint16_t msdu_id,
  858. uint8_t vdev_id)
  859. {
  860. if (dp_is_tput_high(soc))
  861. return;
  862. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  863. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  864. DPTRACE(qdf_dp_trace_ptr(skb,
  865. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  866. QDF_TRACE_DEFAULT_PDEV_ID,
  867. qdf_nbuf_data_addr(skb),
  868. sizeof(qdf_nbuf_data(skb)),
  869. msdu_id, vdev_id, 0));
  870. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  871. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  872. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  873. msdu_id, QDF_TX));
  874. }
  875. #endif
  876. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  877. /**
  878. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  879. * exception by the upper layer (OS_IF)
  880. * @soc: DP soc handle
  881. * @nbuf: packet to be transmitted
  882. *
  883. * Returns: 1 if the packet is marked as exception,
  884. * 0, if the packet is not marked as exception.
  885. */
  886. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  887. qdf_nbuf_t nbuf)
  888. {
  889. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  890. }
  891. #else
  892. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  893. qdf_nbuf_t nbuf)
  894. {
  895. return 0;
  896. }
  897. #endif
  898. /**
  899. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  900. * @vdev: DP vdev handle
  901. * @nbuf: skb
  902. * @desc_pool_id: Descriptor pool ID
  903. * @meta_data: Metadata to the fw
  904. * @tx_exc_metadata: Handle that holds exception path metadata
  905. * Allocate and prepare Tx descriptor with msdu information.
  906. *
  907. * Return: Pointer to Tx Descriptor on success,
  908. * NULL on failure
  909. */
  910. static
  911. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  912. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  913. struct dp_tx_msdu_info_s *msdu_info,
  914. struct cdp_tx_exception_metadata *tx_exc_metadata)
  915. {
  916. uint8_t align_pad;
  917. uint8_t is_exception = 0;
  918. uint8_t htt_hdr_size;
  919. struct dp_tx_desc_s *tx_desc;
  920. struct dp_pdev *pdev = vdev->pdev;
  921. struct dp_soc *soc = pdev->soc;
  922. if (dp_tx_limit_check(vdev))
  923. return NULL;
  924. /* Allocate software Tx descriptor */
  925. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  926. if (qdf_unlikely(!tx_desc)) {
  927. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  928. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  929. return NULL;
  930. }
  931. dp_tx_outstanding_inc(pdev);
  932. /* Initialize the SW tx descriptor */
  933. tx_desc->nbuf = nbuf;
  934. tx_desc->frm_type = dp_tx_frm_std;
  935. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  936. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  937. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  938. tx_desc->vdev_id = vdev->vdev_id;
  939. tx_desc->pdev = pdev;
  940. tx_desc->msdu_ext_desc = NULL;
  941. tx_desc->pkt_offset = 0;
  942. tx_desc->length = qdf_nbuf_headlen(nbuf);
  943. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  944. if (qdf_unlikely(vdev->multipass_en)) {
  945. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  946. goto failure;
  947. }
  948. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  949. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  950. is_exception = 1;
  951. /*
  952. * For special modes (vdev_type == ocb or mesh), data frames should be
  953. * transmitted using varying transmit parameters (tx spec) which include
  954. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  955. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  956. * These frames are sent as exception packets to firmware.
  957. *
  958. * HW requirement is that metadata should always point to a
  959. * 8-byte aligned address. So we add alignment pad to start of buffer.
  960. * HTT Metadata should be ensured to be multiple of 8-bytes,
  961. * to get 8-byte aligned start address along with align_pad added
  962. *
  963. * |-----------------------------|
  964. * | |
  965. * |-----------------------------| <-----Buffer Pointer Address given
  966. * | | ^ in HW descriptor (aligned)
  967. * | HTT Metadata | |
  968. * | | |
  969. * | | | Packet Offset given in descriptor
  970. * | | |
  971. * |-----------------------------| |
  972. * | Alignment Pad | v
  973. * |-----------------------------| <----- Actual buffer start address
  974. * | SKB Data | (Unaligned)
  975. * | |
  976. * | |
  977. * | |
  978. * | |
  979. * | |
  980. * |-----------------------------|
  981. */
  982. if (qdf_unlikely((msdu_info->exception_fw)) ||
  983. (vdev->opmode == wlan_op_mode_ocb) ||
  984. (tx_exc_metadata &&
  985. tx_exc_metadata->is_tx_sniffer)) {
  986. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  987. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  988. DP_STATS_INC(vdev,
  989. tx_i.dropped.headroom_insufficient, 1);
  990. goto failure;
  991. }
  992. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  993. dp_tx_err("qdf_nbuf_push_head failed");
  994. goto failure;
  995. }
  996. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  997. msdu_info);
  998. if (htt_hdr_size == 0)
  999. goto failure;
  1000. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1001. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1002. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1003. is_exception = 1;
  1004. tx_desc->length -= tx_desc->pkt_offset;
  1005. }
  1006. #if !TQM_BYPASS_WAR
  1007. if (is_exception || tx_exc_metadata)
  1008. #endif
  1009. {
  1010. /* Temporary WAR due to TQM VP issues */
  1011. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1012. qdf_atomic_inc(&soc->num_tx_exception);
  1013. }
  1014. return tx_desc;
  1015. failure:
  1016. dp_tx_desc_release(tx_desc, desc_pool_id);
  1017. return NULL;
  1018. }
  1019. /**
  1020. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1021. * @vdev: DP vdev handle
  1022. * @nbuf: skb
  1023. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1024. * @desc_pool_id : Descriptor Pool ID
  1025. *
  1026. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1027. * information. For frames wth fragments, allocate and prepare
  1028. * an MSDU extension descriptor
  1029. *
  1030. * Return: Pointer to Tx Descriptor on success,
  1031. * NULL on failure
  1032. */
  1033. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1034. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1035. uint8_t desc_pool_id)
  1036. {
  1037. struct dp_tx_desc_s *tx_desc;
  1038. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1039. struct dp_pdev *pdev = vdev->pdev;
  1040. struct dp_soc *soc = pdev->soc;
  1041. if (dp_tx_limit_check(vdev))
  1042. return NULL;
  1043. /* Allocate software Tx descriptor */
  1044. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1045. if (!tx_desc) {
  1046. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1047. return NULL;
  1048. }
  1049. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1050. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1051. dp_tx_outstanding_inc(pdev);
  1052. /* Initialize the SW tx descriptor */
  1053. tx_desc->nbuf = nbuf;
  1054. tx_desc->frm_type = msdu_info->frm_type;
  1055. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1056. tx_desc->vdev_id = vdev->vdev_id;
  1057. tx_desc->pdev = pdev;
  1058. tx_desc->pkt_offset = 0;
  1059. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1060. /* Handle scattered frames - TSO/SG/ME */
  1061. /* Allocate and prepare an extension descriptor for scattered frames */
  1062. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1063. if (!msdu_ext_desc) {
  1064. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1065. goto failure;
  1066. }
  1067. #if TQM_BYPASS_WAR
  1068. /* Temporary WAR due to TQM VP issues */
  1069. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1070. qdf_atomic_inc(&soc->num_tx_exception);
  1071. #endif
  1072. if (qdf_unlikely(msdu_info->exception_fw))
  1073. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1074. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1075. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1076. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1077. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1078. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1079. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1080. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1081. else
  1082. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1083. return tx_desc;
  1084. failure:
  1085. dp_tx_desc_release(tx_desc, desc_pool_id);
  1086. return NULL;
  1087. }
  1088. /**
  1089. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1090. * @vdev: DP vdev handle
  1091. * @nbuf: buffer pointer
  1092. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1093. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1094. * descriptor
  1095. *
  1096. * Return:
  1097. */
  1098. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1099. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1100. {
  1101. qdf_nbuf_t curr_nbuf = NULL;
  1102. uint16_t total_len = 0;
  1103. qdf_dma_addr_t paddr;
  1104. int32_t i;
  1105. int32_t mapped_buf_num = 0;
  1106. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1107. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1108. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1109. /* Continue only if frames are of DATA type */
  1110. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1111. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1112. dp_tx_debug("Pkt. recd is of not data type");
  1113. goto error;
  1114. }
  1115. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1116. if (vdev->raw_mode_war &&
  1117. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1118. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1119. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1120. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1121. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1122. /*
  1123. * Number of nbuf's must not exceed the size of the frags
  1124. * array in seg_info.
  1125. */
  1126. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1127. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1128. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1129. goto error;
  1130. }
  1131. if (QDF_STATUS_SUCCESS !=
  1132. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1133. curr_nbuf,
  1134. QDF_DMA_TO_DEVICE,
  1135. curr_nbuf->len)) {
  1136. dp_tx_err("%s dma map error ", __func__);
  1137. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1138. goto error;
  1139. }
  1140. /* Update the count of mapped nbuf's */
  1141. mapped_buf_num++;
  1142. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1143. seg_info->frags[i].paddr_lo = paddr;
  1144. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1145. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1146. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1147. total_len += qdf_nbuf_len(curr_nbuf);
  1148. }
  1149. seg_info->frag_cnt = i;
  1150. seg_info->total_len = total_len;
  1151. seg_info->next = NULL;
  1152. sg_info->curr_seg = seg_info;
  1153. msdu_info->frm_type = dp_tx_frm_raw;
  1154. msdu_info->num_seg = 1;
  1155. return nbuf;
  1156. error:
  1157. i = 0;
  1158. while (nbuf) {
  1159. curr_nbuf = nbuf;
  1160. if (i < mapped_buf_num) {
  1161. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1162. QDF_DMA_TO_DEVICE,
  1163. curr_nbuf->len);
  1164. i++;
  1165. }
  1166. nbuf = qdf_nbuf_next(nbuf);
  1167. qdf_nbuf_free(curr_nbuf);
  1168. }
  1169. return NULL;
  1170. }
  1171. /**
  1172. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1173. * @soc: DP soc handle
  1174. * @nbuf: Buffer pointer
  1175. *
  1176. * unmap the chain of nbufs that belong to this RAW frame.
  1177. *
  1178. * Return: None
  1179. */
  1180. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1181. qdf_nbuf_t nbuf)
  1182. {
  1183. qdf_nbuf_t cur_nbuf = nbuf;
  1184. do {
  1185. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1186. QDF_DMA_TO_DEVICE,
  1187. cur_nbuf->len);
  1188. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1189. } while (cur_nbuf);
  1190. }
  1191. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1192. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1193. qdf_nbuf_t nbuf)
  1194. {
  1195. qdf_nbuf_t nbuf_local;
  1196. struct dp_vdev *vdev_local = vdev_hdl;
  1197. do {
  1198. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1199. break;
  1200. nbuf_local = nbuf;
  1201. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1202. htt_cmn_pkt_type_raw))
  1203. break;
  1204. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1205. break;
  1206. else if (qdf_nbuf_is_tso((nbuf_local)))
  1207. break;
  1208. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1209. (nbuf_local),
  1210. NULL, 1, 0);
  1211. } while (0);
  1212. }
  1213. #endif
  1214. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1215. /**
  1216. * dp_tx_update_stats() - Update soc level tx stats
  1217. * @soc: DP soc handle
  1218. * @nbuf: packet being transmitted
  1219. *
  1220. * Returns: none
  1221. */
  1222. void dp_tx_update_stats(struct dp_soc *soc,
  1223. qdf_nbuf_t nbuf)
  1224. {
  1225. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1226. }
  1227. int
  1228. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1229. struct dp_tx_desc_s *tx_desc,
  1230. uint8_t tid)
  1231. {
  1232. struct dp_swlm *swlm = &soc->swlm;
  1233. union swlm_data swlm_query_data;
  1234. struct dp_swlm_tcl_data tcl_data;
  1235. QDF_STATUS status;
  1236. int ret;
  1237. if (qdf_unlikely(!swlm->is_enabled))
  1238. return 0;
  1239. tcl_data.nbuf = tx_desc->nbuf;
  1240. tcl_data.tid = tid;
  1241. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1242. swlm_query_data.tcl_data = &tcl_data;
  1243. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1244. if (QDF_IS_STATUS_ERROR(status)) {
  1245. dp_swlm_tcl_reset_session_data(soc);
  1246. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1247. return 0;
  1248. }
  1249. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1250. if (ret) {
  1251. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1252. } else {
  1253. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1254. }
  1255. return ret;
  1256. }
  1257. void
  1258. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1259. int coalesce)
  1260. {
  1261. if (coalesce)
  1262. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1263. else
  1264. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1265. }
  1266. #endif
  1267. #ifdef FEATURE_RUNTIME_PM
  1268. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1269. {
  1270. return qdf_atomic_read(&soc->rtpm_high_tput_flag);
  1271. }
  1272. /**
  1273. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1274. * @soc: Datapath soc handle
  1275. * @hal_ring_hdl: HAL ring handle
  1276. * @coalesce: Coalesce the current write or not
  1277. *
  1278. * Wrapper for HAL ring access end for data transmission for
  1279. * FEATURE_RUNTIME_PM
  1280. *
  1281. * Returns: none
  1282. */
  1283. void
  1284. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1285. hal_ring_handle_t hal_ring_hdl,
  1286. int coalesce)
  1287. {
  1288. int ret;
  1289. /*
  1290. * Avoid runtime get and put APIs under high throughput scenarios.
  1291. */
  1292. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1293. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1294. return;
  1295. }
  1296. ret = hif_pm_runtime_get(soc->hif_handle,
  1297. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1298. switch (ret) {
  1299. case 0:
  1300. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1301. hif_pm_runtime_put(soc->hif_handle,
  1302. RTPM_ID_DW_TX_HW_ENQUEUE);
  1303. break;
  1304. /*
  1305. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1306. * take the dp runtime refcount using dp_runtime_get,
  1307. * check link state,if up, write TX ring HP, else just set flush event.
  1308. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1309. * zero or time out, then flush pending tx.
  1310. */
  1311. case -EBUSY:
  1312. case -EINPROGRESS:
  1313. dp_runtime_get(soc);
  1314. if (hif_pm_get_link_state(soc->hif_handle) ==
  1315. HIF_PM_LINK_STATE_UP) {
  1316. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1317. } else {
  1318. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1319. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1320. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1321. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1322. }
  1323. dp_runtime_put(soc);
  1324. break;
  1325. default:
  1326. dp_runtime_get(soc);
  1327. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1328. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1329. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1330. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1331. dp_runtime_put(soc);
  1332. }
  1333. }
  1334. #else
  1335. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1336. {
  1337. return 0;
  1338. }
  1339. #endif
  1340. /**
  1341. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1342. * @vdev: DP vdev handle
  1343. * @nbuf: skb
  1344. *
  1345. * Extract the DSCP or PCP information from frame and map into TID value.
  1346. *
  1347. * Return: void
  1348. */
  1349. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1350. struct dp_tx_msdu_info_s *msdu_info)
  1351. {
  1352. uint8_t tos = 0, dscp_tid_override = 0;
  1353. uint8_t *hdr_ptr, *L3datap;
  1354. uint8_t is_mcast = 0;
  1355. qdf_ether_header_t *eh = NULL;
  1356. qdf_ethervlan_header_t *evh = NULL;
  1357. uint16_t ether_type;
  1358. qdf_llc_t *llcHdr;
  1359. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1360. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1361. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1362. eh = (qdf_ether_header_t *)nbuf->data;
  1363. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1364. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1365. } else {
  1366. qdf_dot3_qosframe_t *qos_wh =
  1367. (qdf_dot3_qosframe_t *) nbuf->data;
  1368. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1369. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1370. return;
  1371. }
  1372. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1373. ether_type = eh->ether_type;
  1374. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1375. /*
  1376. * Check if packet is dot3 or eth2 type.
  1377. */
  1378. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1379. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1380. sizeof(*llcHdr));
  1381. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1382. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1383. sizeof(*llcHdr);
  1384. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1385. + sizeof(*llcHdr) +
  1386. sizeof(qdf_net_vlanhdr_t));
  1387. } else {
  1388. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1389. sizeof(*llcHdr);
  1390. }
  1391. } else {
  1392. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1393. evh = (qdf_ethervlan_header_t *) eh;
  1394. ether_type = evh->ether_type;
  1395. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1396. }
  1397. }
  1398. /*
  1399. * Find priority from IP TOS DSCP field
  1400. */
  1401. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1402. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1403. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1404. /* Only for unicast frames */
  1405. if (!is_mcast) {
  1406. /* send it on VO queue */
  1407. msdu_info->tid = DP_VO_TID;
  1408. }
  1409. } else {
  1410. /*
  1411. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1412. * from TOS byte.
  1413. */
  1414. tos = ip->ip_tos;
  1415. dscp_tid_override = 1;
  1416. }
  1417. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1418. /* TODO
  1419. * use flowlabel
  1420. *igmpmld cases to be handled in phase 2
  1421. */
  1422. unsigned long ver_pri_flowlabel;
  1423. unsigned long pri;
  1424. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1425. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1426. DP_IPV6_PRIORITY_SHIFT;
  1427. tos = pri;
  1428. dscp_tid_override = 1;
  1429. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1430. msdu_info->tid = DP_VO_TID;
  1431. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1432. /* Only for unicast frames */
  1433. if (!is_mcast) {
  1434. /* send ucast arp on VO queue */
  1435. msdu_info->tid = DP_VO_TID;
  1436. }
  1437. }
  1438. /*
  1439. * Assign all MCAST packets to BE
  1440. */
  1441. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1442. if (is_mcast) {
  1443. tos = 0;
  1444. dscp_tid_override = 1;
  1445. }
  1446. }
  1447. if (dscp_tid_override == 1) {
  1448. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1449. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1450. }
  1451. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1452. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1453. return;
  1454. }
  1455. /**
  1456. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1457. * @vdev: DP vdev handle
  1458. * @nbuf: skb
  1459. *
  1460. * Software based TID classification is required when more than 2 DSCP-TID
  1461. * mapping tables are needed.
  1462. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1463. *
  1464. * Return: void
  1465. */
  1466. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1467. struct dp_tx_msdu_info_s *msdu_info)
  1468. {
  1469. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1470. /*
  1471. * skip_sw_tid_classification flag will set in below cases-
  1472. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1473. * 2. hlos_tid_override enabled for vdev
  1474. * 3. mesh mode enabled for vdev
  1475. */
  1476. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1477. /* Update tid in msdu_info from skb priority */
  1478. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1479. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1480. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1481. if (tid == DP_TX_INVALID_QOS_TAG)
  1482. return;
  1483. msdu_info->tid = tid;
  1484. return;
  1485. }
  1486. return;
  1487. }
  1488. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1489. }
  1490. #ifdef FEATURE_WLAN_TDLS
  1491. /**
  1492. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1493. * @soc: datapath SOC
  1494. * @vdev: datapath vdev
  1495. * @tx_desc: TX descriptor
  1496. *
  1497. * Return: None
  1498. */
  1499. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1500. struct dp_vdev *vdev,
  1501. struct dp_tx_desc_s *tx_desc)
  1502. {
  1503. if (vdev) {
  1504. if (vdev->is_tdls_frame) {
  1505. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1506. vdev->is_tdls_frame = false;
  1507. }
  1508. }
  1509. }
  1510. /**
  1511. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1512. * @soc: dp_soc handle
  1513. * @tx_desc: TX descriptor
  1514. * @vdev: datapath vdev handle
  1515. *
  1516. * Return: None
  1517. */
  1518. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1519. struct dp_tx_desc_s *tx_desc)
  1520. {
  1521. struct hal_tx_completion_status ts = {0};
  1522. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1523. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1524. DP_MOD_ID_TDLS);
  1525. if (qdf_unlikely(!vdev)) {
  1526. dp_err_rl("vdev is null!");
  1527. goto error;
  1528. }
  1529. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1530. if (vdev->tx_non_std_data_callback.func) {
  1531. qdf_nbuf_set_next(nbuf, NULL);
  1532. vdev->tx_non_std_data_callback.func(
  1533. vdev->tx_non_std_data_callback.ctxt,
  1534. nbuf, ts.status);
  1535. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1536. return;
  1537. } else {
  1538. dp_err_rl("callback func is null");
  1539. }
  1540. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1541. error:
  1542. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1543. qdf_nbuf_free(nbuf);
  1544. }
  1545. /**
  1546. * dp_tx_msdu_single_map() - do nbuf map
  1547. * @vdev: DP vdev handle
  1548. * @tx_desc: DP TX descriptor pointer
  1549. * @nbuf: skb pointer
  1550. *
  1551. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1552. * operation done in other component.
  1553. *
  1554. * Return: QDF_STATUS
  1555. */
  1556. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1557. struct dp_tx_desc_s *tx_desc,
  1558. qdf_nbuf_t nbuf)
  1559. {
  1560. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1561. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1562. nbuf,
  1563. QDF_DMA_TO_DEVICE,
  1564. nbuf->len);
  1565. else
  1566. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1567. QDF_DMA_TO_DEVICE);
  1568. }
  1569. #else
  1570. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1571. struct dp_vdev *vdev,
  1572. struct dp_tx_desc_s *tx_desc)
  1573. {
  1574. }
  1575. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1576. struct dp_tx_desc_s *tx_desc)
  1577. {
  1578. }
  1579. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1580. struct dp_tx_desc_s *tx_desc,
  1581. qdf_nbuf_t nbuf)
  1582. {
  1583. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1584. nbuf,
  1585. QDF_DMA_TO_DEVICE,
  1586. nbuf->len);
  1587. }
  1588. #endif
  1589. #ifdef MESH_MODE_SUPPORT
  1590. /**
  1591. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1592. * @soc: datapath SOC
  1593. * @vdev: datapath vdev
  1594. * @tx_desc: TX descriptor
  1595. *
  1596. * Return: None
  1597. */
  1598. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1599. struct dp_vdev *vdev,
  1600. struct dp_tx_desc_s *tx_desc)
  1601. {
  1602. if (qdf_unlikely(vdev->mesh_vdev))
  1603. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1604. }
  1605. /**
  1606. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1607. * @soc: dp_soc handle
  1608. * @tx_desc: TX descriptor
  1609. * @vdev: datapath vdev handle
  1610. *
  1611. * Return: None
  1612. */
  1613. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1614. struct dp_tx_desc_s *tx_desc)
  1615. {
  1616. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1617. struct dp_vdev *vdev = NULL;
  1618. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1619. qdf_nbuf_free(nbuf);
  1620. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1621. } else {
  1622. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1623. DP_MOD_ID_MESH);
  1624. if (vdev && vdev->osif_tx_free_ext)
  1625. vdev->osif_tx_free_ext((nbuf));
  1626. else
  1627. qdf_nbuf_free(nbuf);
  1628. if (vdev)
  1629. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1630. }
  1631. }
  1632. #else
  1633. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1634. struct dp_vdev *vdev,
  1635. struct dp_tx_desc_s *tx_desc)
  1636. {
  1637. }
  1638. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1639. struct dp_tx_desc_s *tx_desc)
  1640. {
  1641. }
  1642. #endif
  1643. /**
  1644. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1645. * @vdev: DP vdev handle
  1646. * @nbuf: skb
  1647. *
  1648. * Return: 1 if frame needs to be dropped else 0
  1649. */
  1650. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1651. {
  1652. struct dp_pdev *pdev = NULL;
  1653. struct dp_ast_entry *src_ast_entry = NULL;
  1654. struct dp_ast_entry *dst_ast_entry = NULL;
  1655. struct dp_soc *soc = NULL;
  1656. qdf_assert(vdev);
  1657. pdev = vdev->pdev;
  1658. qdf_assert(pdev);
  1659. soc = pdev->soc;
  1660. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1661. (soc, dstmac, vdev->pdev->pdev_id);
  1662. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1663. (soc, srcmac, vdev->pdev->pdev_id);
  1664. if (dst_ast_entry && src_ast_entry) {
  1665. if (dst_ast_entry->peer_id ==
  1666. src_ast_entry->peer_id)
  1667. return 1;
  1668. }
  1669. return 0;
  1670. }
  1671. /**
  1672. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1673. * @vdev: DP vdev handle
  1674. * @nbuf: skb
  1675. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1676. * @meta_data: Metadata to the fw
  1677. * @tx_q: Tx queue to be used for this Tx frame
  1678. * @peer_id: peer_id of the peer in case of NAWDS frames
  1679. * @tx_exc_metadata: Handle that holds exception path metadata
  1680. *
  1681. * Return: NULL on success,
  1682. * nbuf when it fails to send
  1683. */
  1684. qdf_nbuf_t
  1685. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1686. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1687. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1688. {
  1689. struct dp_pdev *pdev = vdev->pdev;
  1690. struct dp_soc *soc = pdev->soc;
  1691. struct dp_tx_desc_s *tx_desc;
  1692. QDF_STATUS status;
  1693. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1694. uint16_t htt_tcl_metadata = 0;
  1695. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1696. uint8_t tid = msdu_info->tid;
  1697. struct cdp_tid_tx_stats *tid_stats = NULL;
  1698. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1699. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1700. msdu_info, tx_exc_metadata);
  1701. if (!tx_desc) {
  1702. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1703. vdev, tx_q->desc_pool_id);
  1704. drop_code = TX_DESC_ERR;
  1705. goto fail_return;
  1706. }
  1707. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1708. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1709. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1710. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1711. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1712. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1713. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1714. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1715. peer_id);
  1716. } else
  1717. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1718. if (msdu_info->exception_fw)
  1719. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1720. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1721. !pdev->enhanced_stats_en);
  1722. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1723. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1724. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1725. /* Handle failure */
  1726. dp_err("qdf_nbuf_map failed");
  1727. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1728. drop_code = TX_DMA_MAP_ERR;
  1729. goto release_desc;
  1730. }
  1731. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1732. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1733. tx_desc->id, DP_TX_DESC_MAP);
  1734. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1735. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1736. htt_tcl_metadata,
  1737. tx_exc_metadata, msdu_info);
  1738. if (status != QDF_STATUS_SUCCESS) {
  1739. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1740. tx_desc, tx_q->ring_id);
  1741. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1742. tx_desc->id, DP_TX_DESC_UNMAP);
  1743. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1744. QDF_DMA_TO_DEVICE,
  1745. nbuf->len);
  1746. drop_code = TX_HW_ENQUEUE;
  1747. goto release_desc;
  1748. }
  1749. return NULL;
  1750. release_desc:
  1751. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1752. fail_return:
  1753. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1754. tid_stats = &pdev->stats.tid_stats.
  1755. tid_tx_stats[tx_q->ring_id][tid];
  1756. tid_stats->swdrop_cnt[drop_code]++;
  1757. return nbuf;
  1758. }
  1759. /**
  1760. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1761. * @soc: Soc handle
  1762. * @desc: software Tx descriptor to be processed
  1763. *
  1764. * Return: none
  1765. */
  1766. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1767. struct dp_tx_desc_s *desc)
  1768. {
  1769. qdf_nbuf_t nbuf = desc->nbuf;
  1770. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1771. /* nbuf already freed in vdev detach path */
  1772. if (!nbuf)
  1773. return;
  1774. /* If it is TDLS mgmt, don't unmap or free the frame */
  1775. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1776. return dp_non_std_tx_comp_free_buff(soc, desc);
  1777. /* 0 : MSDU buffer, 1 : MLE */
  1778. if (desc->msdu_ext_desc) {
  1779. /* TSO free */
  1780. if (hal_tx_ext_desc_get_tso_enable(
  1781. desc->msdu_ext_desc->vaddr)) {
  1782. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1783. desc->id, DP_TX_COMP_MSDU_EXT);
  1784. dp_tx_tso_seg_history_add(soc,
  1785. desc->msdu_ext_desc->tso_desc,
  1786. desc->nbuf, desc->id, type);
  1787. /* unmap eash TSO seg before free the nbuf */
  1788. dp_tx_tso_unmap_segment(soc,
  1789. desc->msdu_ext_desc->tso_desc,
  1790. desc->msdu_ext_desc->
  1791. tso_num_desc);
  1792. qdf_nbuf_free(nbuf);
  1793. return;
  1794. }
  1795. }
  1796. /* If it's ME frame, dont unmap the cloned nbuf's */
  1797. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1798. goto nbuf_free;
  1799. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  1800. dp_tx_unmap(soc, desc);
  1801. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1802. return dp_mesh_tx_comp_free_buff(soc, desc);
  1803. nbuf_free:
  1804. qdf_nbuf_free(nbuf);
  1805. }
  1806. /**
  1807. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1808. * @vdev: DP vdev handle
  1809. * @nbuf: skb
  1810. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1811. *
  1812. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1813. *
  1814. * Return: NULL on success,
  1815. * nbuf when it fails to send
  1816. */
  1817. #if QDF_LOCK_STATS
  1818. noinline
  1819. #else
  1820. #endif
  1821. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1822. struct dp_tx_msdu_info_s *msdu_info)
  1823. {
  1824. uint32_t i;
  1825. struct dp_pdev *pdev = vdev->pdev;
  1826. struct dp_soc *soc = pdev->soc;
  1827. struct dp_tx_desc_s *tx_desc;
  1828. bool is_cce_classified = false;
  1829. QDF_STATUS status;
  1830. uint16_t htt_tcl_metadata = 0;
  1831. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1832. struct cdp_tid_tx_stats *tid_stats = NULL;
  1833. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1834. if (msdu_info->frm_type == dp_tx_frm_me)
  1835. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1836. i = 0;
  1837. /* Print statement to track i and num_seg */
  1838. /*
  1839. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1840. * descriptors using information in msdu_info
  1841. */
  1842. while (i < msdu_info->num_seg) {
  1843. /*
  1844. * Setup Tx descriptor for an MSDU, and MSDU extension
  1845. * descriptor
  1846. */
  1847. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1848. tx_q->desc_pool_id);
  1849. if (!tx_desc) {
  1850. if (msdu_info->frm_type == dp_tx_frm_me) {
  1851. prep_desc_fail++;
  1852. dp_tx_me_free_buf(pdev,
  1853. (void *)(msdu_info->u.sg_info
  1854. .curr_seg->frags[0].vaddr));
  1855. if (prep_desc_fail == msdu_info->num_seg) {
  1856. /*
  1857. * Unmap is needed only if descriptor
  1858. * preparation failed for all segments.
  1859. */
  1860. qdf_nbuf_unmap(soc->osdev,
  1861. msdu_info->u.sg_info.
  1862. curr_seg->nbuf,
  1863. QDF_DMA_TO_DEVICE);
  1864. }
  1865. /*
  1866. * Free the nbuf for the current segment
  1867. * and make it point to the next in the list.
  1868. * For me, there are as many segments as there
  1869. * are no of clients.
  1870. */
  1871. qdf_nbuf_free(msdu_info->u.sg_info
  1872. .curr_seg->nbuf);
  1873. if (msdu_info->u.sg_info.curr_seg->next) {
  1874. msdu_info->u.sg_info.curr_seg =
  1875. msdu_info->u.sg_info
  1876. .curr_seg->next;
  1877. nbuf = msdu_info->u.sg_info
  1878. .curr_seg->nbuf;
  1879. }
  1880. i++;
  1881. continue;
  1882. }
  1883. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1884. dp_tx_tso_seg_history_add(
  1885. soc,
  1886. msdu_info->u.tso_info.curr_seg,
  1887. nbuf, 0, DP_TX_DESC_UNMAP);
  1888. dp_tx_tso_unmap_segment(soc,
  1889. msdu_info->u.tso_info.
  1890. curr_seg,
  1891. msdu_info->u.tso_info.
  1892. tso_num_seg_list);
  1893. if (msdu_info->u.tso_info.curr_seg->next) {
  1894. msdu_info->u.tso_info.curr_seg =
  1895. msdu_info->u.tso_info.curr_seg->next;
  1896. i++;
  1897. continue;
  1898. }
  1899. }
  1900. goto done;
  1901. }
  1902. if (msdu_info->frm_type == dp_tx_frm_me) {
  1903. tx_desc->msdu_ext_desc->me_buffer =
  1904. (struct dp_tx_me_buf_t *)msdu_info->
  1905. u.sg_info.curr_seg->frags[0].vaddr;
  1906. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1907. }
  1908. if (is_cce_classified)
  1909. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1910. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1911. if (msdu_info->exception_fw) {
  1912. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1913. }
  1914. /*
  1915. * For frames with multiple segments (TSO, ME), jump to next
  1916. * segment.
  1917. */
  1918. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1919. if (msdu_info->u.tso_info.curr_seg->next) {
  1920. msdu_info->u.tso_info.curr_seg =
  1921. msdu_info->u.tso_info.curr_seg->next;
  1922. /*
  1923. * If this is a jumbo nbuf, then increment the
  1924. * number of nbuf users for each additional
  1925. * segment of the msdu. This will ensure that
  1926. * the skb is freed only after receiving tx
  1927. * completion for all segments of an nbuf
  1928. */
  1929. qdf_nbuf_inc_users(nbuf);
  1930. /* Check with MCL if this is needed */
  1931. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  1932. */
  1933. }
  1934. }
  1935. /*
  1936. * Enqueue the Tx MSDU descriptor to HW for transmit
  1937. */
  1938. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1939. htt_tcl_metadata,
  1940. NULL, msdu_info);
  1941. if (status != QDF_STATUS_SUCCESS) {
  1942. dp_info("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1943. tx_desc, tx_q->ring_id);
  1944. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1945. tid_stats = &pdev->stats.tid_stats.
  1946. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1947. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1948. if (msdu_info->frm_type == dp_tx_frm_me) {
  1949. hw_enq_fail++;
  1950. if (hw_enq_fail == msdu_info->num_seg) {
  1951. /*
  1952. * Unmap is needed only if enqueue
  1953. * failed for all segments.
  1954. */
  1955. qdf_nbuf_unmap(soc->osdev,
  1956. msdu_info->u.sg_info.
  1957. curr_seg->nbuf,
  1958. QDF_DMA_TO_DEVICE);
  1959. }
  1960. /*
  1961. * Free the nbuf for the current segment
  1962. * and make it point to the next in the list.
  1963. * For me, there are as many segments as there
  1964. * are no of clients.
  1965. */
  1966. qdf_nbuf_free(msdu_info->u.sg_info
  1967. .curr_seg->nbuf);
  1968. if (msdu_info->u.sg_info.curr_seg->next) {
  1969. msdu_info->u.sg_info.curr_seg =
  1970. msdu_info->u.sg_info
  1971. .curr_seg->next;
  1972. nbuf = msdu_info->u.sg_info
  1973. .curr_seg->nbuf;
  1974. } else
  1975. break;
  1976. i++;
  1977. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1978. continue;
  1979. }
  1980. /*
  1981. * For TSO frames, the nbuf users increment done for
  1982. * the current segment has to be reverted, since the
  1983. * hw enqueue for this segment failed
  1984. */
  1985. if (msdu_info->frm_type == dp_tx_frm_tso &&
  1986. msdu_info->u.tso_info.curr_seg) {
  1987. /*
  1988. * unmap and free current,
  1989. * retransmit remaining segments
  1990. */
  1991. dp_tx_comp_free_buf(soc, tx_desc);
  1992. i++;
  1993. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1994. continue;
  1995. }
  1996. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1997. goto done;
  1998. }
  1999. /*
  2000. * TODO
  2001. * if tso_info structure can be modified to have curr_seg
  2002. * as first element, following 2 blocks of code (for TSO and SG)
  2003. * can be combined into 1
  2004. */
  2005. /*
  2006. * For Multicast-Unicast converted packets,
  2007. * each converted frame (for a client) is represented as
  2008. * 1 segment
  2009. */
  2010. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2011. (msdu_info->frm_type == dp_tx_frm_me)) {
  2012. if (msdu_info->u.sg_info.curr_seg->next) {
  2013. msdu_info->u.sg_info.curr_seg =
  2014. msdu_info->u.sg_info.curr_seg->next;
  2015. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2016. } else
  2017. break;
  2018. }
  2019. i++;
  2020. }
  2021. nbuf = NULL;
  2022. done:
  2023. return nbuf;
  2024. }
  2025. /**
  2026. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2027. * for SG frames
  2028. * @vdev: DP vdev handle
  2029. * @nbuf: skb
  2030. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2031. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2032. *
  2033. * Return: NULL on success,
  2034. * nbuf when it fails to send
  2035. */
  2036. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2037. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2038. {
  2039. uint32_t cur_frag, nr_frags, i;
  2040. qdf_dma_addr_t paddr;
  2041. struct dp_tx_sg_info_s *sg_info;
  2042. sg_info = &msdu_info->u.sg_info;
  2043. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2044. if (QDF_STATUS_SUCCESS !=
  2045. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2046. QDF_DMA_TO_DEVICE,
  2047. qdf_nbuf_headlen(nbuf))) {
  2048. dp_tx_err("dma map error");
  2049. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2050. qdf_nbuf_free(nbuf);
  2051. return NULL;
  2052. }
  2053. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2054. seg_info->frags[0].paddr_lo = paddr;
  2055. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2056. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2057. seg_info->frags[0].vaddr = (void *) nbuf;
  2058. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2059. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2060. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2061. dp_tx_err("frag dma map error");
  2062. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2063. goto map_err;
  2064. }
  2065. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2066. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2067. seg_info->frags[cur_frag + 1].paddr_hi =
  2068. ((uint64_t) paddr) >> 32;
  2069. seg_info->frags[cur_frag + 1].len =
  2070. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2071. }
  2072. seg_info->frag_cnt = (cur_frag + 1);
  2073. seg_info->total_len = qdf_nbuf_len(nbuf);
  2074. seg_info->next = NULL;
  2075. sg_info->curr_seg = seg_info;
  2076. msdu_info->frm_type = dp_tx_frm_sg;
  2077. msdu_info->num_seg = 1;
  2078. return nbuf;
  2079. map_err:
  2080. /* restore paddr into nbuf before calling unmap */
  2081. qdf_nbuf_mapped_paddr_set(nbuf,
  2082. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2083. ((uint64_t)
  2084. seg_info->frags[0].paddr_hi) << 32));
  2085. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2086. QDF_DMA_TO_DEVICE,
  2087. seg_info->frags[0].len);
  2088. for (i = 1; i <= cur_frag; i++) {
  2089. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2090. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2091. seg_info->frags[i].paddr_hi) << 32),
  2092. seg_info->frags[i].len,
  2093. QDF_DMA_TO_DEVICE);
  2094. }
  2095. qdf_nbuf_free(nbuf);
  2096. return NULL;
  2097. }
  2098. /**
  2099. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2100. * @vdev: DP vdev handle
  2101. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2102. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2103. *
  2104. * Return: NULL on failure,
  2105. * nbuf when extracted successfully
  2106. */
  2107. static
  2108. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2109. struct dp_tx_msdu_info_s *msdu_info,
  2110. uint16_t ppdu_cookie)
  2111. {
  2112. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2113. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2114. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2115. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2116. (msdu_info->meta_data[5], 1);
  2117. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2118. (msdu_info->meta_data[5], 1);
  2119. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2120. (msdu_info->meta_data[6], ppdu_cookie);
  2121. msdu_info->exception_fw = 1;
  2122. msdu_info->is_tx_sniffer = 1;
  2123. }
  2124. #ifdef MESH_MODE_SUPPORT
  2125. /**
  2126. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2127. and prepare msdu_info for mesh frames.
  2128. * @vdev: DP vdev handle
  2129. * @nbuf: skb
  2130. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2131. *
  2132. * Return: NULL on failure,
  2133. * nbuf when extracted successfully
  2134. */
  2135. static
  2136. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2137. struct dp_tx_msdu_info_s *msdu_info)
  2138. {
  2139. struct meta_hdr_s *mhdr;
  2140. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2141. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2142. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2143. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2144. msdu_info->exception_fw = 0;
  2145. goto remove_meta_hdr;
  2146. }
  2147. msdu_info->exception_fw = 1;
  2148. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2149. meta_data->host_tx_desc_pool = 1;
  2150. meta_data->update_peer_cache = 1;
  2151. meta_data->learning_frame = 1;
  2152. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2153. meta_data->power = mhdr->power;
  2154. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2155. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2156. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2157. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2158. meta_data->dyn_bw = 1;
  2159. meta_data->valid_pwr = 1;
  2160. meta_data->valid_mcs_mask = 1;
  2161. meta_data->valid_nss_mask = 1;
  2162. meta_data->valid_preamble_type = 1;
  2163. meta_data->valid_retries = 1;
  2164. meta_data->valid_bw_info = 1;
  2165. }
  2166. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2167. meta_data->encrypt_type = 0;
  2168. meta_data->valid_encrypt_type = 1;
  2169. meta_data->learning_frame = 0;
  2170. }
  2171. meta_data->valid_key_flags = 1;
  2172. meta_data->key_flags = (mhdr->keyix & 0x3);
  2173. remove_meta_hdr:
  2174. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2175. dp_tx_err("qdf_nbuf_pull_head failed");
  2176. qdf_nbuf_free(nbuf);
  2177. return NULL;
  2178. }
  2179. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2180. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2181. " tid %d to_fw %d",
  2182. msdu_info->meta_data[0],
  2183. msdu_info->meta_data[1],
  2184. msdu_info->meta_data[2],
  2185. msdu_info->meta_data[3],
  2186. msdu_info->meta_data[4],
  2187. msdu_info->meta_data[5],
  2188. msdu_info->tid, msdu_info->exception_fw);
  2189. return nbuf;
  2190. }
  2191. #else
  2192. static
  2193. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2194. struct dp_tx_msdu_info_s *msdu_info)
  2195. {
  2196. return nbuf;
  2197. }
  2198. #endif
  2199. /**
  2200. * dp_check_exc_metadata() - Checks if parameters are valid
  2201. * @tx_exc - holds all exception path parameters
  2202. *
  2203. * Returns true when all the parameters are valid else false
  2204. *
  2205. */
  2206. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2207. {
  2208. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2209. HTT_INVALID_TID);
  2210. bool invalid_encap_type =
  2211. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2212. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2213. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2214. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2215. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2216. tx_exc->ppdu_cookie == 0);
  2217. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2218. invalid_cookie) {
  2219. return false;
  2220. }
  2221. return true;
  2222. }
  2223. #ifdef ATH_SUPPORT_IQUE
  2224. /**
  2225. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2226. * @vdev: vdev handle
  2227. * @nbuf: skb
  2228. *
  2229. * Return: true on success,
  2230. * false on failure
  2231. */
  2232. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2233. {
  2234. qdf_ether_header_t *eh;
  2235. /* Mcast to Ucast Conversion*/
  2236. if (qdf_likely(!vdev->mcast_enhancement_en))
  2237. return true;
  2238. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2239. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2240. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2241. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2242. qdf_nbuf_set_next(nbuf, NULL);
  2243. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2244. qdf_nbuf_len(nbuf));
  2245. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2246. QDF_STATUS_SUCCESS) {
  2247. return false;
  2248. }
  2249. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2250. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2251. QDF_STATUS_SUCCESS) {
  2252. return false;
  2253. }
  2254. }
  2255. }
  2256. return true;
  2257. }
  2258. #else
  2259. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2260. {
  2261. return true;
  2262. }
  2263. #endif
  2264. /**
  2265. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2266. * @nbuf: qdf_nbuf_t
  2267. * @vdev: struct dp_vdev *
  2268. *
  2269. * Allow packet for processing only if it is for peer client which is
  2270. * connected with same vap. Drop packet if client is connected to
  2271. * different vap.
  2272. *
  2273. * Return: QDF_STATUS
  2274. */
  2275. static inline QDF_STATUS
  2276. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2277. {
  2278. struct dp_ast_entry *dst_ast_entry = NULL;
  2279. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2280. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2281. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2282. return QDF_STATUS_SUCCESS;
  2283. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2284. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2285. eh->ether_dhost,
  2286. vdev->vdev_id);
  2287. /* If there is no ast entry, return failure */
  2288. if (qdf_unlikely(!dst_ast_entry)) {
  2289. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2290. return QDF_STATUS_E_FAILURE;
  2291. }
  2292. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2293. return QDF_STATUS_SUCCESS;
  2294. }
  2295. /**
  2296. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2297. * @soc: DP soc handle
  2298. * @vdev_id: id of DP vdev handle
  2299. * @nbuf: skb
  2300. * @tx_exc_metadata: Handle that holds exception path meta data
  2301. *
  2302. * Entry point for Core Tx layer (DP_TX) invoked from
  2303. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2304. *
  2305. * Return: NULL on success,
  2306. * nbuf when it fails to send
  2307. */
  2308. qdf_nbuf_t
  2309. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2310. qdf_nbuf_t nbuf,
  2311. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2312. {
  2313. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2314. qdf_ether_header_t *eh = NULL;
  2315. struct dp_tx_msdu_info_s msdu_info;
  2316. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2317. DP_MOD_ID_TX_EXCEPTION);
  2318. if (qdf_unlikely(!vdev))
  2319. goto fail;
  2320. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2321. if (!tx_exc_metadata)
  2322. goto fail;
  2323. msdu_info.tid = tx_exc_metadata->tid;
  2324. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2325. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2326. QDF_MAC_ADDR_REF(nbuf->data));
  2327. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2328. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2329. dp_tx_err("Invalid parameters in exception path");
  2330. goto fail;
  2331. }
  2332. /* Basic sanity checks for unsupported packets */
  2333. /* MESH mode */
  2334. if (qdf_unlikely(vdev->mesh_vdev)) {
  2335. dp_tx_err("Mesh mode is not supported in exception path");
  2336. goto fail;
  2337. }
  2338. /*
  2339. * Classify the frame and call corresponding
  2340. * "prepare" function which extracts the segment (TSO)
  2341. * and fragmentation information (for TSO , SG, ME, or Raw)
  2342. * into MSDU_INFO structure which is later used to fill
  2343. * SW and HW descriptors.
  2344. */
  2345. if (qdf_nbuf_is_tso(nbuf)) {
  2346. dp_verbose_debug("TSO frame %pK", vdev);
  2347. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2348. qdf_nbuf_len(nbuf));
  2349. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2350. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2351. qdf_nbuf_len(nbuf));
  2352. goto fail;
  2353. }
  2354. goto send_multiple;
  2355. }
  2356. /* SG */
  2357. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2358. struct dp_tx_seg_info_s seg_info = {0};
  2359. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2360. if (!nbuf)
  2361. goto fail;
  2362. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2363. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2364. qdf_nbuf_len(nbuf));
  2365. goto send_multiple;
  2366. }
  2367. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2368. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2369. qdf_nbuf_len(nbuf));
  2370. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2371. tx_exc_metadata->ppdu_cookie);
  2372. }
  2373. /*
  2374. * Get HW Queue to use for this frame.
  2375. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2376. * dedicated for data and 1 for command.
  2377. * "queue_id" maps to one hardware ring.
  2378. * With each ring, we also associate a unique Tx descriptor pool
  2379. * to minimize lock contention for these resources.
  2380. */
  2381. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2382. /*
  2383. * Check exception descriptors
  2384. */
  2385. if (dp_tx_exception_limit_check(vdev))
  2386. goto fail;
  2387. /* Single linear frame */
  2388. /*
  2389. * If nbuf is a simple linear frame, use send_single function to
  2390. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2391. * SRNG. There is no need to setup a MSDU extension descriptor.
  2392. */
  2393. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2394. tx_exc_metadata->peer_id, tx_exc_metadata);
  2395. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2396. return nbuf;
  2397. send_multiple:
  2398. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2399. fail:
  2400. if (vdev)
  2401. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2402. dp_verbose_debug("pkt send failed");
  2403. return nbuf;
  2404. }
  2405. /**
  2406. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2407. * in exception path in special case to avoid regular exception path chk.
  2408. * @soc: DP soc handle
  2409. * @vdev_id: id of DP vdev handle
  2410. * @nbuf: skb
  2411. * @tx_exc_metadata: Handle that holds exception path meta data
  2412. *
  2413. * Entry point for Core Tx layer (DP_TX) invoked from
  2414. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2415. *
  2416. * Return: NULL on success,
  2417. * nbuf when it fails to send
  2418. */
  2419. qdf_nbuf_t
  2420. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2421. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2422. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2423. {
  2424. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2425. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2426. DP_MOD_ID_TX_EXCEPTION);
  2427. if (qdf_unlikely(!vdev))
  2428. goto fail;
  2429. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2430. == QDF_STATUS_E_FAILURE)) {
  2431. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2432. goto fail;
  2433. }
  2434. /* Unref count as it will agin be taken inside dp_tx_exception */
  2435. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2436. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2437. fail:
  2438. if (vdev)
  2439. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2440. dp_verbose_debug("pkt send failed");
  2441. return nbuf;
  2442. }
  2443. /**
  2444. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2445. * @soc: DP soc handle
  2446. * @vdev_id: DP vdev handle
  2447. * @nbuf: skb
  2448. *
  2449. * Entry point for Core Tx layer (DP_TX) invoked from
  2450. * hard_start_xmit in OSIF/HDD
  2451. *
  2452. * Return: NULL on success,
  2453. * nbuf when it fails to send
  2454. */
  2455. #ifdef MESH_MODE_SUPPORT
  2456. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2457. qdf_nbuf_t nbuf)
  2458. {
  2459. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2460. struct meta_hdr_s *mhdr;
  2461. qdf_nbuf_t nbuf_mesh = NULL;
  2462. qdf_nbuf_t nbuf_clone = NULL;
  2463. struct dp_vdev *vdev;
  2464. uint8_t no_enc_frame = 0;
  2465. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2466. if (!nbuf_mesh) {
  2467. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2468. "qdf_nbuf_unshare failed");
  2469. return nbuf;
  2470. }
  2471. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2472. if (!vdev) {
  2473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2474. "vdev is NULL for vdev_id %d", vdev_id);
  2475. return nbuf;
  2476. }
  2477. nbuf = nbuf_mesh;
  2478. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2479. if ((vdev->sec_type != cdp_sec_type_none) &&
  2480. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2481. no_enc_frame = 1;
  2482. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2483. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2484. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2485. !no_enc_frame) {
  2486. nbuf_clone = qdf_nbuf_clone(nbuf);
  2487. if (!nbuf_clone) {
  2488. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2489. "qdf_nbuf_clone failed");
  2490. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2491. return nbuf;
  2492. }
  2493. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2494. }
  2495. if (nbuf_clone) {
  2496. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2497. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2498. } else {
  2499. qdf_nbuf_free(nbuf_clone);
  2500. }
  2501. }
  2502. if (no_enc_frame)
  2503. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2504. else
  2505. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2506. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2507. if ((!nbuf) && no_enc_frame) {
  2508. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2509. }
  2510. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2511. return nbuf;
  2512. }
  2513. #else
  2514. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2515. qdf_nbuf_t nbuf)
  2516. {
  2517. return dp_tx_send(soc, vdev_id, nbuf);
  2518. }
  2519. #endif
  2520. /**
  2521. * dp_tx_nawds_handler() - NAWDS handler
  2522. *
  2523. * @soc: DP soc handle
  2524. * @vdev_id: id of DP vdev handle
  2525. * @msdu_info: msdu_info required to create HTT metadata
  2526. * @nbuf: skb
  2527. *
  2528. * This API transfers the multicast frames with the peer id
  2529. * on NAWDS enabled peer.
  2530. * Return: none
  2531. */
  2532. static inline
  2533. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2534. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2535. {
  2536. struct dp_peer *peer = NULL;
  2537. qdf_nbuf_t nbuf_clone = NULL;
  2538. uint16_t peer_id = DP_INVALID_PEER;
  2539. uint16_t sa_peer_id = DP_INVALID_PEER;
  2540. struct dp_ast_entry *ast_entry = NULL;
  2541. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2542. if (!soc->ast_offload_support) {
  2543. qdf_spin_lock_bh(&soc->ast_lock);
  2544. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2545. (soc,
  2546. (uint8_t *)(eh->ether_shost),
  2547. vdev->pdev->pdev_id);
  2548. if (ast_entry)
  2549. sa_peer_id = ast_entry->peer_id;
  2550. qdf_spin_unlock_bh(&soc->ast_lock);
  2551. }
  2552. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2553. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2554. if (!peer->bss_peer && peer->nawds_enabled) {
  2555. peer_id = peer->peer_id;
  2556. /* Multicast packets needs to be
  2557. * dropped in case of intra bss forwarding
  2558. */
  2559. if (!soc->ast_offload_support) {
  2560. if (sa_peer_id == peer->peer_id) {
  2561. dp_tx_debug("multicast packet");
  2562. DP_STATS_INC(peer, tx.nawds_mcast_drop,
  2563. 1);
  2564. continue;
  2565. }
  2566. }
  2567. nbuf_clone = qdf_nbuf_clone(nbuf);
  2568. if (!nbuf_clone) {
  2569. QDF_TRACE(QDF_MODULE_ID_DP,
  2570. QDF_TRACE_LEVEL_ERROR,
  2571. FL("nbuf clone failed"));
  2572. break;
  2573. }
  2574. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2575. msdu_info, peer_id,
  2576. NULL);
  2577. if (nbuf_clone) {
  2578. dp_tx_debug("pkt send failed");
  2579. qdf_nbuf_free(nbuf_clone);
  2580. } else {
  2581. if (peer_id != DP_INVALID_PEER)
  2582. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2583. 1, qdf_nbuf_len(nbuf));
  2584. }
  2585. }
  2586. }
  2587. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2588. }
  2589. /**
  2590. * dp_tx_send() - Transmit a frame on a given VAP
  2591. * @soc: DP soc handle
  2592. * @vdev_id: id of DP vdev handle
  2593. * @nbuf: skb
  2594. *
  2595. * Entry point for Core Tx layer (DP_TX) invoked from
  2596. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2597. * cases
  2598. *
  2599. * Return: NULL on success,
  2600. * nbuf when it fails to send
  2601. */
  2602. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2603. qdf_nbuf_t nbuf)
  2604. {
  2605. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2606. uint16_t peer_id = HTT_INVALID_PEER;
  2607. /*
  2608. * doing a memzero is causing additional function call overhead
  2609. * so doing static stack clearing
  2610. */
  2611. struct dp_tx_msdu_info_s msdu_info = {0};
  2612. struct dp_vdev *vdev = NULL;
  2613. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2614. return nbuf;
  2615. /*
  2616. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2617. * this in per packet path.
  2618. *
  2619. * As in this path vdev memory is already protected with netdev
  2620. * tx lock
  2621. */
  2622. vdev = soc->vdev_id_map[vdev_id];
  2623. if (qdf_unlikely(!vdev))
  2624. return nbuf;
  2625. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2626. QDF_MAC_ADDR_REF(nbuf->data));
  2627. /*
  2628. * Set Default Host TID value to invalid TID
  2629. * (TID override disabled)
  2630. */
  2631. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2632. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2633. if (qdf_unlikely(vdev->mesh_vdev)) {
  2634. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2635. &msdu_info);
  2636. if (!nbuf_mesh) {
  2637. dp_verbose_debug("Extracting mesh metadata failed");
  2638. return nbuf;
  2639. }
  2640. nbuf = nbuf_mesh;
  2641. }
  2642. /*
  2643. * Get HW Queue to use for this frame.
  2644. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2645. * dedicated for data and 1 for command.
  2646. * "queue_id" maps to one hardware ring.
  2647. * With each ring, we also associate a unique Tx descriptor pool
  2648. * to minimize lock contention for these resources.
  2649. */
  2650. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2651. /*
  2652. * TCL H/W supports 2 DSCP-TID mapping tables.
  2653. * Table 1 - Default DSCP-TID mapping table
  2654. * Table 2 - 1 DSCP-TID override table
  2655. *
  2656. * If we need a different DSCP-TID mapping for this vap,
  2657. * call tid_classify to extract DSCP/ToS from frame and
  2658. * map to a TID and store in msdu_info. This is later used
  2659. * to fill in TCL Input descriptor (per-packet TID override).
  2660. */
  2661. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2662. /*
  2663. * Classify the frame and call corresponding
  2664. * "prepare" function which extracts the segment (TSO)
  2665. * and fragmentation information (for TSO , SG, ME, or Raw)
  2666. * into MSDU_INFO structure which is later used to fill
  2667. * SW and HW descriptors.
  2668. */
  2669. if (qdf_nbuf_is_tso(nbuf)) {
  2670. dp_verbose_debug("TSO frame %pK", vdev);
  2671. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2672. qdf_nbuf_len(nbuf));
  2673. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2674. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2675. qdf_nbuf_len(nbuf));
  2676. return nbuf;
  2677. }
  2678. goto send_multiple;
  2679. }
  2680. /* SG */
  2681. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2682. struct dp_tx_seg_info_s seg_info = {0};
  2683. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2684. if (!nbuf)
  2685. return NULL;
  2686. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2687. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2688. qdf_nbuf_len(nbuf));
  2689. goto send_multiple;
  2690. }
  2691. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2692. return NULL;
  2693. /* RAW */
  2694. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2695. struct dp_tx_seg_info_s seg_info = {0};
  2696. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2697. if (!nbuf)
  2698. return NULL;
  2699. dp_verbose_debug("Raw frame %pK", vdev);
  2700. goto send_multiple;
  2701. }
  2702. if (qdf_unlikely(vdev->nawds_enabled)) {
  2703. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2704. qdf_nbuf_data(nbuf);
  2705. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2706. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2707. peer_id = DP_INVALID_PEER;
  2708. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2709. 1, qdf_nbuf_len(nbuf));
  2710. }
  2711. /* Single linear frame */
  2712. /*
  2713. * If nbuf is a simple linear frame, use send_single function to
  2714. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2715. * SRNG. There is no need to setup a MSDU extension descriptor.
  2716. */
  2717. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2718. return nbuf;
  2719. send_multiple:
  2720. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2721. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2722. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2723. return nbuf;
  2724. }
  2725. /**
  2726. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2727. * case to vaoid check in perpkt path.
  2728. * @soc: DP soc handle
  2729. * @vdev_id: id of DP vdev handle
  2730. * @nbuf: skb
  2731. *
  2732. * Entry point for Core Tx layer (DP_TX) invoked from
  2733. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2734. * with special condition to avoid per pkt check in dp_tx_send
  2735. *
  2736. * Return: NULL on success,
  2737. * nbuf when it fails to send
  2738. */
  2739. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2740. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2741. {
  2742. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2743. struct dp_vdev *vdev = NULL;
  2744. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2745. return nbuf;
  2746. /*
  2747. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2748. * this in per packet path.
  2749. *
  2750. * As in this path vdev memory is already protected with netdev
  2751. * tx lock
  2752. */
  2753. vdev = soc->vdev_id_map[vdev_id];
  2754. if (qdf_unlikely(!vdev))
  2755. return nbuf;
  2756. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2757. == QDF_STATUS_E_FAILURE)) {
  2758. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2759. return nbuf;
  2760. }
  2761. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2762. }
  2763. #ifdef UMAC_SUPPORT_PROXY_ARP
  2764. /**
  2765. * dp_tx_proxy_arp() - Tx proxy arp handler
  2766. * @vdev: datapath vdev handle
  2767. * @buf: sk buffer
  2768. *
  2769. * Return: status
  2770. */
  2771. static inline
  2772. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2773. {
  2774. if (vdev->osif_proxy_arp)
  2775. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  2776. /*
  2777. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  2778. * osif_proxy_arp has a valid function pointer assigned
  2779. * to it
  2780. */
  2781. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  2782. return QDF_STATUS_NOT_INITIALIZED;
  2783. }
  2784. #else
  2785. /**
  2786. * dp_tx_proxy_arp() - Tx proxy arp handler
  2787. * @vdev: datapath vdev handle
  2788. * @buf: sk buffer
  2789. *
  2790. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  2791. * is not defined.
  2792. *
  2793. * Return: status
  2794. */
  2795. static inline
  2796. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2797. {
  2798. return QDF_STATUS_SUCCESS;
  2799. }
  2800. #endif
  2801. /**
  2802. * dp_tx_reinject_handler() - Tx Reinject Handler
  2803. * @soc: datapath soc handle
  2804. * @vdev: datapath vdev handle
  2805. * @tx_desc: software descriptor head pointer
  2806. * @status : Tx completion status from HTT descriptor
  2807. *
  2808. * This function reinjects frames back to Target.
  2809. * Todo - Host queue needs to be added
  2810. *
  2811. * Return: none
  2812. */
  2813. static
  2814. void dp_tx_reinject_handler(struct dp_soc *soc,
  2815. struct dp_vdev *vdev,
  2816. struct dp_tx_desc_s *tx_desc,
  2817. uint8_t *status)
  2818. {
  2819. struct dp_peer *peer = NULL;
  2820. uint32_t peer_id = HTT_INVALID_PEER;
  2821. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2822. qdf_nbuf_t nbuf_copy = NULL;
  2823. struct dp_tx_msdu_info_s msdu_info;
  2824. #ifdef WDS_VENDOR_EXTENSION
  2825. int is_mcast = 0, is_ucast = 0;
  2826. int num_peers_3addr = 0;
  2827. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2828. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2829. #endif
  2830. qdf_assert(vdev);
  2831. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2832. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2833. dp_tx_debug("Tx reinject path");
  2834. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2835. qdf_nbuf_len(tx_desc->nbuf));
  2836. #ifdef WDS_VENDOR_EXTENSION
  2837. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2838. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2839. } else {
  2840. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2841. }
  2842. is_ucast = !is_mcast;
  2843. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2844. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2845. if (peer->bss_peer)
  2846. continue;
  2847. /* Detect wds peers that use 3-addr framing for mcast.
  2848. * if there are any, the bss_peer is used to send the
  2849. * the mcast frame using 3-addr format. all wds enabled
  2850. * peers that use 4-addr framing for mcast frames will
  2851. * be duplicated and sent as 4-addr frames below.
  2852. */
  2853. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2854. num_peers_3addr = 1;
  2855. break;
  2856. }
  2857. }
  2858. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2859. #endif
  2860. if (qdf_unlikely(vdev->mesh_vdev)) {
  2861. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2862. } else {
  2863. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2864. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2865. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2866. #ifdef WDS_VENDOR_EXTENSION
  2867. /*
  2868. * . if 3-addr STA, then send on BSS Peer
  2869. * . if Peer WDS enabled and accept 4-addr mcast,
  2870. * send mcast on that peer only
  2871. * . if Peer WDS enabled and accept 4-addr ucast,
  2872. * send ucast on that peer only
  2873. */
  2874. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2875. (peer->wds_enabled &&
  2876. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2877. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2878. #else
  2879. (peer->bss_peer &&
  2880. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  2881. #endif
  2882. peer_id = DP_INVALID_PEER;
  2883. nbuf_copy = qdf_nbuf_copy(nbuf);
  2884. if (!nbuf_copy) {
  2885. dp_tx_debug("nbuf copy failed");
  2886. break;
  2887. }
  2888. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2889. nbuf_copy,
  2890. &msdu_info,
  2891. peer_id,
  2892. NULL);
  2893. if (nbuf_copy) {
  2894. dp_tx_debug("pkt send failed");
  2895. qdf_nbuf_free(nbuf_copy);
  2896. }
  2897. }
  2898. }
  2899. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2900. }
  2901. qdf_nbuf_free(nbuf);
  2902. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2903. }
  2904. /**
  2905. * dp_tx_inspect_handler() - Tx Inspect Handler
  2906. * @soc: datapath soc handle
  2907. * @vdev: datapath vdev handle
  2908. * @tx_desc: software descriptor head pointer
  2909. * @status : Tx completion status from HTT descriptor
  2910. *
  2911. * Handles Tx frames sent back to Host for inspection
  2912. * (ProxyARP)
  2913. *
  2914. * Return: none
  2915. */
  2916. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2917. struct dp_vdev *vdev,
  2918. struct dp_tx_desc_s *tx_desc,
  2919. uint8_t *status)
  2920. {
  2921. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2922. "%s Tx inspect path",
  2923. __func__);
  2924. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2925. qdf_nbuf_len(tx_desc->nbuf));
  2926. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2927. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2928. }
  2929. #ifdef MESH_MODE_SUPPORT
  2930. /**
  2931. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2932. * in mesh meta header
  2933. * @tx_desc: software descriptor head pointer
  2934. * @ts: pointer to tx completion stats
  2935. * Return: none
  2936. */
  2937. static
  2938. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2939. struct hal_tx_completion_status *ts)
  2940. {
  2941. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2942. if (!tx_desc->msdu_ext_desc) {
  2943. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2944. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2945. "netbuf %pK offset %d",
  2946. netbuf, tx_desc->pkt_offset);
  2947. return;
  2948. }
  2949. }
  2950. }
  2951. #else
  2952. static
  2953. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2954. struct hal_tx_completion_status *ts)
  2955. {
  2956. }
  2957. #endif
  2958. #ifdef QCA_PEER_EXT_STATS
  2959. /*
  2960. * dp_tx_compute_tid_delay() - Compute per TID delay
  2961. * @stats: Per TID delay stats
  2962. * @tx_desc: Software Tx descriptor
  2963. *
  2964. * Compute the software enqueue and hw enqueue delays and
  2965. * update the respective histograms
  2966. *
  2967. * Return: void
  2968. */
  2969. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  2970. struct dp_tx_desc_s *tx_desc)
  2971. {
  2972. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  2973. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2974. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  2975. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2976. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2977. timestamp_hw_enqueue = tx_desc->timestamp;
  2978. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2979. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2980. timestamp_hw_enqueue);
  2981. /*
  2982. * Update the Tx software enqueue delay and HW enque-Completion delay.
  2983. */
  2984. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  2985. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  2986. }
  2987. /*
  2988. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  2989. * @peer: DP peer context
  2990. * @tx_desc: Tx software descriptor
  2991. * @tid: Transmission ID
  2992. * @ring_id: Rx CPU context ID/CPU_ID
  2993. *
  2994. * Update the peer extended stats. These are enhanced other
  2995. * delay stats per msdu level.
  2996. *
  2997. * Return: void
  2998. */
  2999. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3000. struct dp_tx_desc_s *tx_desc,
  3001. uint8_t tid, uint8_t ring_id)
  3002. {
  3003. struct dp_pdev *pdev = peer->vdev->pdev;
  3004. struct dp_soc *soc = NULL;
  3005. struct cdp_peer_ext_stats *pext_stats = NULL;
  3006. soc = pdev->soc;
  3007. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3008. return;
  3009. pext_stats = peer->pext_stats;
  3010. qdf_assert(pext_stats);
  3011. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3012. /*
  3013. * For non-TID packets use the TID 9
  3014. */
  3015. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3016. tid = CDP_MAX_DATA_TIDS - 1;
  3017. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3018. tx_desc);
  3019. }
  3020. #else
  3021. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3022. struct dp_tx_desc_s *tx_desc,
  3023. uint8_t tid, uint8_t ring_id)
  3024. {
  3025. }
  3026. #endif
  3027. /**
  3028. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3029. * to pass in correct fields
  3030. *
  3031. * @vdev: pdev handle
  3032. * @tx_desc: tx descriptor
  3033. * @tid: tid value
  3034. * @ring_id: TCL or WBM ring number for transmit path
  3035. * Return: none
  3036. */
  3037. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3038. struct dp_tx_desc_s *tx_desc,
  3039. uint8_t tid, uint8_t ring_id)
  3040. {
  3041. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3042. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3043. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3044. return;
  3045. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3046. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3047. timestamp_hw_enqueue = tx_desc->timestamp;
  3048. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3049. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3050. timestamp_hw_enqueue);
  3051. interframe_delay = (uint32_t)(timestamp_ingress -
  3052. vdev->prev_tx_enq_tstamp);
  3053. /*
  3054. * Delay in software enqueue
  3055. */
  3056. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3057. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3058. /*
  3059. * Delay between packet enqueued to HW and Tx completion
  3060. */
  3061. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3062. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3063. /*
  3064. * Update interframe delay stats calculated at hardstart receive point.
  3065. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3066. * interframe delay will not be calculate correctly for 1st frame.
  3067. * On the other side, this will help in avoiding extra per packet check
  3068. * of !vdev->prev_tx_enq_tstamp.
  3069. */
  3070. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3071. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3072. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3073. }
  3074. #ifdef DISABLE_DP_STATS
  3075. static
  3076. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3077. {
  3078. }
  3079. #else
  3080. static
  3081. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3082. {
  3083. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3084. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3085. if (subtype != QDF_PROTO_INVALID)
  3086. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3087. }
  3088. #endif
  3089. /**
  3090. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3091. * per wbm ring
  3092. *
  3093. * @tx_desc: software descriptor head pointer
  3094. * @ts: Tx completion status
  3095. * @peer: peer handle
  3096. * @ring_id: ring number
  3097. *
  3098. * Return: None
  3099. */
  3100. static inline void
  3101. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3102. struct hal_tx_completion_status *ts,
  3103. struct dp_peer *peer, uint8_t ring_id)
  3104. {
  3105. struct dp_pdev *pdev = peer->vdev->pdev;
  3106. struct dp_soc *soc = NULL;
  3107. uint8_t mcs, pkt_type;
  3108. uint8_t tid = ts->tid;
  3109. uint32_t length;
  3110. struct cdp_tid_tx_stats *tid_stats;
  3111. if (!pdev)
  3112. return;
  3113. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3114. tid = CDP_MAX_DATA_TIDS - 1;
  3115. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3116. soc = pdev->soc;
  3117. mcs = ts->mcs;
  3118. pkt_type = ts->pkt_type;
  3119. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3120. dp_err("Release source is not from TQM");
  3121. return;
  3122. }
  3123. length = qdf_nbuf_len(tx_desc->nbuf);
  3124. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3125. if (qdf_unlikely(pdev->delay_stats_flag))
  3126. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3127. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3128. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3129. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3130. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3131. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3132. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3133. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3134. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3135. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3136. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3137. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3138. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3139. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3140. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3141. /*
  3142. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3143. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3144. * are no completions for failed cases. Hence updating tx_failed from
  3145. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3146. * then this has to be removed
  3147. */
  3148. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3149. peer->stats.tx.dropped.fw_rem_notx +
  3150. peer->stats.tx.dropped.fw_rem_tx +
  3151. peer->stats.tx.dropped.age_out +
  3152. peer->stats.tx.dropped.fw_reason1 +
  3153. peer->stats.tx.dropped.fw_reason2 +
  3154. peer->stats.tx.dropped.fw_reason3;
  3155. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3156. tid_stats->tqm_status_cnt[ts->status]++;
  3157. }
  3158. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3159. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3160. return;
  3161. }
  3162. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3163. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3164. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3165. /*
  3166. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3167. * Return from here if HTT PPDU events are enabled.
  3168. */
  3169. if (!(soc->process_tx_status))
  3170. return;
  3171. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3172. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3173. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3174. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3175. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3176. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3177. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3178. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3179. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3180. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3181. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3182. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3183. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3184. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3185. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3186. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3187. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3188. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3189. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3190. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3191. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3192. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3193. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3194. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3195. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3196. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3197. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3198. if (ts->first_msdu)
  3199. DP_STATS_INCC(peer, tx.mpdu_success_with_retries,
  3200. qdf_do_div(ts->transmit_cnt, DP_RETRY_COUNT),
  3201. ts->transmit_cnt > DP_RETRY_COUNT);
  3202. peer->stats.tx.last_tx_ts = qdf_system_ticks();
  3203. }
  3204. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3205. /**
  3206. * dp_tx_flow_pool_lock() - take flow pool lock
  3207. * @soc: core txrx main context
  3208. * @tx_desc: tx desc
  3209. *
  3210. * Return: None
  3211. */
  3212. static inline
  3213. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3214. struct dp_tx_desc_s *tx_desc)
  3215. {
  3216. struct dp_tx_desc_pool_s *pool;
  3217. uint8_t desc_pool_id;
  3218. desc_pool_id = tx_desc->pool_id;
  3219. pool = &soc->tx_desc[desc_pool_id];
  3220. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3221. }
  3222. /**
  3223. * dp_tx_flow_pool_unlock() - release flow pool lock
  3224. * @soc: core txrx main context
  3225. * @tx_desc: tx desc
  3226. *
  3227. * Return: None
  3228. */
  3229. static inline
  3230. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3231. struct dp_tx_desc_s *tx_desc)
  3232. {
  3233. struct dp_tx_desc_pool_s *pool;
  3234. uint8_t desc_pool_id;
  3235. desc_pool_id = tx_desc->pool_id;
  3236. pool = &soc->tx_desc[desc_pool_id];
  3237. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3238. }
  3239. #else
  3240. static inline
  3241. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3242. {
  3243. }
  3244. static inline
  3245. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3246. {
  3247. }
  3248. #endif
  3249. /**
  3250. * dp_tx_notify_completion() - Notify tx completion for this desc
  3251. * @soc: core txrx main context
  3252. * @vdev: datapath vdev handle
  3253. * @tx_desc: tx desc
  3254. * @netbuf: buffer
  3255. * @status: tx status
  3256. *
  3257. * Return: none
  3258. */
  3259. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3260. struct dp_vdev *vdev,
  3261. struct dp_tx_desc_s *tx_desc,
  3262. qdf_nbuf_t netbuf,
  3263. uint8_t status)
  3264. {
  3265. void *osif_dev;
  3266. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3267. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3268. qdf_assert(tx_desc);
  3269. dp_tx_flow_pool_lock(soc, tx_desc);
  3270. if (!vdev ||
  3271. !vdev->osif_vdev) {
  3272. dp_tx_flow_pool_unlock(soc, tx_desc);
  3273. return;
  3274. }
  3275. osif_dev = vdev->osif_vdev;
  3276. tx_compl_cbk = vdev->tx_comp;
  3277. dp_tx_flow_pool_unlock(soc, tx_desc);
  3278. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3279. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3280. if (tx_compl_cbk)
  3281. tx_compl_cbk(netbuf, osif_dev, flag);
  3282. }
  3283. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3284. * @pdev: pdev handle
  3285. * @tid: tid value
  3286. * @txdesc_ts: timestamp from txdesc
  3287. * @ppdu_id: ppdu id
  3288. *
  3289. * Return: none
  3290. */
  3291. #ifdef FEATURE_PERPKT_INFO
  3292. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3293. struct dp_peer *peer,
  3294. uint8_t tid,
  3295. uint64_t txdesc_ts,
  3296. uint32_t ppdu_id)
  3297. {
  3298. uint64_t delta_ms;
  3299. struct cdp_tx_sojourn_stats *sojourn_stats;
  3300. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3301. return;
  3302. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3303. tid >= CDP_DATA_TID_MAX))
  3304. return;
  3305. if (qdf_unlikely(!pdev->sojourn_buf))
  3306. return;
  3307. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3308. qdf_nbuf_data(pdev->sojourn_buf);
  3309. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3310. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3311. txdesc_ts;
  3312. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3313. delta_ms);
  3314. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3315. sojourn_stats->num_msdus[tid] = 1;
  3316. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3317. peer->avg_sojourn_msdu[tid].internal;
  3318. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3319. pdev->sojourn_buf, HTT_INVALID_PEER,
  3320. WDI_NO_VAL, pdev->pdev_id);
  3321. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3322. sojourn_stats->num_msdus[tid] = 0;
  3323. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3324. }
  3325. #else
  3326. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3327. struct dp_peer *peer,
  3328. uint8_t tid,
  3329. uint64_t txdesc_ts,
  3330. uint32_t ppdu_id)
  3331. {
  3332. }
  3333. #endif
  3334. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3335. /**
  3336. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3337. * @soc: dp_soc handle
  3338. * @desc: Tx Descriptor
  3339. * @ts: HAL Tx completion descriptor contents
  3340. *
  3341. * This function is used to send tx completion to packet capture
  3342. */
  3343. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3344. struct dp_tx_desc_s *desc,
  3345. struct hal_tx_completion_status *ts)
  3346. {
  3347. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3348. desc, ts->peer_id,
  3349. WDI_NO_VAL, desc->pdev->pdev_id);
  3350. }
  3351. #endif
  3352. /**
  3353. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3354. * @soc: DP Soc handle
  3355. * @tx_desc: software Tx descriptor
  3356. * @ts : Tx completion status from HAL/HTT descriptor
  3357. *
  3358. * Return: none
  3359. */
  3360. static inline void
  3361. dp_tx_comp_process_desc(struct dp_soc *soc,
  3362. struct dp_tx_desc_s *desc,
  3363. struct hal_tx_completion_status *ts,
  3364. struct dp_peer *peer)
  3365. {
  3366. uint64_t time_latency = 0;
  3367. /*
  3368. * m_copy/tx_capture modes are not supported for
  3369. * scatter gather packets
  3370. */
  3371. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3372. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3373. desc->timestamp);
  3374. }
  3375. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3376. if (!(desc->msdu_ext_desc)) {
  3377. dp_tx_enh_unmap(soc, desc);
  3378. if (QDF_STATUS_SUCCESS ==
  3379. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3380. return;
  3381. }
  3382. if (QDF_STATUS_SUCCESS ==
  3383. dp_get_completion_indication_for_stack(soc,
  3384. desc->pdev,
  3385. peer, ts,
  3386. desc->nbuf,
  3387. time_latency)) {
  3388. dp_send_completion_to_stack(soc,
  3389. desc->pdev,
  3390. ts->peer_id,
  3391. ts->ppdu_id,
  3392. desc->nbuf);
  3393. return;
  3394. }
  3395. }
  3396. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3397. dp_tx_comp_free_buf(soc, desc);
  3398. }
  3399. #ifdef DISABLE_DP_STATS
  3400. /**
  3401. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3402. * @soc: core txrx main context
  3403. * @tx_desc: tx desc
  3404. * @status: tx status
  3405. *
  3406. * Return: none
  3407. */
  3408. static inline
  3409. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3410. struct dp_vdev *vdev,
  3411. struct dp_tx_desc_s *tx_desc,
  3412. uint8_t status)
  3413. {
  3414. }
  3415. #else
  3416. static inline
  3417. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3418. struct dp_vdev *vdev,
  3419. struct dp_tx_desc_s *tx_desc,
  3420. uint8_t status)
  3421. {
  3422. void *osif_dev;
  3423. ol_txrx_stats_rx_fp stats_cbk;
  3424. uint8_t pkt_type;
  3425. qdf_assert(tx_desc);
  3426. if (!vdev ||
  3427. !vdev->osif_vdev ||
  3428. !vdev->stats_cb)
  3429. return;
  3430. osif_dev = vdev->osif_vdev;
  3431. stats_cbk = vdev->stats_cb;
  3432. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3433. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3434. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3435. &pkt_type);
  3436. }
  3437. #endif
  3438. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3439. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3440. uint32_t delta_tsf)
  3441. {
  3442. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3443. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3444. DP_MOD_ID_CDP);
  3445. if (!vdev) {
  3446. dp_err_rl("vdev %d does not exist", vdev_id);
  3447. return;
  3448. }
  3449. vdev->delta_tsf = delta_tsf;
  3450. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3451. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3452. }
  3453. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3454. uint8_t vdev_id, bool enable)
  3455. {
  3456. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3457. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3458. DP_MOD_ID_CDP);
  3459. if (!vdev) {
  3460. dp_err_rl("vdev %d does not exist", vdev_id);
  3461. return QDF_STATUS_E_FAILURE;
  3462. }
  3463. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3464. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3465. return QDF_STATUS_SUCCESS;
  3466. }
  3467. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3468. uint32_t *val)
  3469. {
  3470. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3471. struct dp_vdev *vdev;
  3472. uint32_t delay_accum;
  3473. uint32_t pkts_accum;
  3474. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  3475. if (!vdev) {
  3476. dp_err_rl("vdev %d does not exist", vdev_id);
  3477. return QDF_STATUS_E_FAILURE;
  3478. }
  3479. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  3480. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3481. return QDF_STATUS_E_FAILURE;
  3482. }
  3483. /* Average uplink delay based on current accumulated values */
  3484. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  3485. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  3486. *val = delay_accum / pkts_accum;
  3487. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  3488. delay_accum, pkts_accum);
  3489. /* Reset accumulated values to 0 */
  3490. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  3491. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  3492. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3493. return QDF_STATUS_SUCCESS;
  3494. }
  3495. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3496. struct hal_tx_completion_status *ts)
  3497. {
  3498. uint32_t buffer_ts;
  3499. uint32_t delta_tsf;
  3500. uint32_t ul_delay;
  3501. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3502. if (!ts->valid)
  3503. return;
  3504. if (qdf_unlikely(!vdev)) {
  3505. dp_info_rl("vdev is null or delete in progrss");
  3506. return;
  3507. }
  3508. if (!qdf_atomic_read(&vdev->ul_delay_report))
  3509. return;
  3510. delta_tsf = vdev->delta_tsf;
  3511. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3512. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3513. * valid up to 29 bits.
  3514. */
  3515. buffer_ts = ts->buffer_timestamp << 10;
  3516. ul_delay = ts->tsf - buffer_ts - delta_tsf;
  3517. ul_delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3518. if (ul_delay > 0x1000000) {
  3519. dp_info_rl("----------------------\n"
  3520. "Tx completion status:\n"
  3521. "----------------------\n"
  3522. "release_src = %d\n"
  3523. "ppdu_id = 0x%x\n"
  3524. "release_reason = %d\n"
  3525. "tsf = %u (0x%x)\n"
  3526. "buffer_timestamp = %u (0x%x)\n"
  3527. "delta_tsf = %u (0x%x)\n",
  3528. ts->release_src, ts->ppdu_id, ts->status,
  3529. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3530. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3531. return;
  3532. }
  3533. ul_delay /= 1000; /* in unit of ms */
  3534. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  3535. qdf_atomic_inc(&vdev->ul_pkts_accum);
  3536. }
  3537. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  3538. static inline
  3539. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3540. struct hal_tx_completion_status *ts)
  3541. {
  3542. }
  3543. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  3544. /**
  3545. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3546. * @soc: DP soc handle
  3547. * @tx_desc: software descriptor head pointer
  3548. * @ts: Tx completion status
  3549. * @peer: peer handle
  3550. * @ring_id: ring number
  3551. *
  3552. * Return: none
  3553. */
  3554. static inline
  3555. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3556. struct dp_tx_desc_s *tx_desc,
  3557. struct hal_tx_completion_status *ts,
  3558. struct dp_peer *peer, uint8_t ring_id)
  3559. {
  3560. uint32_t length;
  3561. qdf_ether_header_t *eh;
  3562. struct dp_vdev *vdev = NULL;
  3563. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3564. enum qdf_dp_tx_rx_status dp_status;
  3565. if (!nbuf) {
  3566. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3567. goto out;
  3568. }
  3569. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3570. length = qdf_nbuf_len(nbuf);
  3571. dp_status = dp_tx_hw_to_qdf(ts->status);
  3572. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3573. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3574. QDF_TRACE_DEFAULT_PDEV_ID,
  3575. qdf_nbuf_data_addr(nbuf),
  3576. sizeof(qdf_nbuf_data(nbuf)),
  3577. tx_desc->id, ts->status, dp_status));
  3578. dp_tx_comp_debug("-------------------- \n"
  3579. "Tx Completion Stats: \n"
  3580. "-------------------- \n"
  3581. "ack_frame_rssi = %d \n"
  3582. "first_msdu = %d \n"
  3583. "last_msdu = %d \n"
  3584. "msdu_part_of_amsdu = %d \n"
  3585. "rate_stats valid = %d \n"
  3586. "bw = %d \n"
  3587. "pkt_type = %d \n"
  3588. "stbc = %d \n"
  3589. "ldpc = %d \n"
  3590. "sgi = %d \n"
  3591. "mcs = %d \n"
  3592. "ofdma = %d \n"
  3593. "tones_in_ru = %d \n"
  3594. "tsf = %d \n"
  3595. "ppdu_id = %d \n"
  3596. "transmit_cnt = %d \n"
  3597. "tid = %d \n"
  3598. "peer_id = %d\n",
  3599. ts->ack_frame_rssi, ts->first_msdu,
  3600. ts->last_msdu, ts->msdu_part_of_amsdu,
  3601. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3602. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3603. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3604. ts->transmit_cnt, ts->tid, ts->peer_id);
  3605. /* Update SoC level stats */
  3606. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3607. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3608. if (!peer) {
  3609. dp_info_rl("peer is null or deletion in progress");
  3610. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3611. goto out;
  3612. }
  3613. vdev = peer->vdev;
  3614. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3615. dp_tx_update_uplink_delay(soc, vdev, ts);
  3616. /* Update per-packet stats for mesh mode */
  3617. if (qdf_unlikely(vdev->mesh_vdev) &&
  3618. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3619. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3620. /* Update peer level stats */
  3621. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3622. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3623. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3624. if ((peer->vdev->tx_encap_type ==
  3625. htt_cmn_pkt_type_ethernet) &&
  3626. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3627. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3628. }
  3629. }
  3630. } else {
  3631. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3632. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3633. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3634. if (qdf_unlikely(peer->in_twt)) {
  3635. DP_STATS_INC_PKT(peer,
  3636. tx.tx_success_twt,
  3637. 1, length);
  3638. }
  3639. }
  3640. }
  3641. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3642. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3643. #ifdef QCA_SUPPORT_RDK_STATS
  3644. if (soc->rdkstats_enabled)
  3645. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3646. tx_desc->timestamp,
  3647. ts->ppdu_id);
  3648. #endif
  3649. out:
  3650. return;
  3651. }
  3652. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  3653. defined(QCA_ENHANCED_STATS_SUPPORT)
  3654. /*
  3655. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  3656. * @peer: Datapath peer handle
  3657. * @length: Length of the packet
  3658. * @tx_status: Tx status from TQM/FW
  3659. * @update: enhanced flag value present in dp_pdev
  3660. *
  3661. * Return: none
  3662. */
  3663. static inline
  3664. void dp_tx_update_peer_basic_stats(struct dp_peer *peer, uint32_t length,
  3665. uint8_t tx_status, bool update)
  3666. {
  3667. if ((!peer->hw_txrx_stats_en) || update) {
  3668. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3669. DP_STATS_INCC(peer, tx.tx_failed, 1,
  3670. tx_status != HAL_TX_TQM_RR_FRAME_ACKED);
  3671. }
  3672. }
  3673. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  3674. static inline
  3675. void dp_tx_update_peer_basic_stats(struct dp_peer *peer, uint32_t length,
  3676. uint8_t tx_status, bool update)
  3677. {
  3678. if (!peer->hw_txrx_stats_en) {
  3679. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3680. DP_STATS_INCC(peer, tx.tx_failed, 1,
  3681. tx_status != HAL_TX_TQM_RR_FRAME_ACKED);
  3682. }
  3683. }
  3684. #else
  3685. static inline
  3686. void dp_tx_update_peer_basic_stats(struct dp_peer *peer, uint32_t length,
  3687. uint8_t tx_status, bool update)
  3688. {
  3689. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3690. DP_STATS_INCC(peer, tx.tx_failed, 1,
  3691. tx_status != HAL_TX_TQM_RR_FRAME_ACKED);
  3692. }
  3693. #endif
  3694. /**
  3695. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3696. * @soc: core txrx main context
  3697. * @comp_head: software descriptor head pointer
  3698. * @ring_id: ring number
  3699. *
  3700. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3701. * and release the software descriptors after processing is complete
  3702. *
  3703. * Return: none
  3704. */
  3705. static void
  3706. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3707. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3708. {
  3709. struct dp_tx_desc_s *desc;
  3710. struct dp_tx_desc_s *next;
  3711. struct hal_tx_completion_status ts;
  3712. struct dp_peer *peer = NULL;
  3713. uint16_t peer_id = DP_INVALID_PEER;
  3714. qdf_nbuf_t netbuf;
  3715. desc = comp_head;
  3716. while (desc) {
  3717. if (peer_id != desc->peer_id) {
  3718. if (peer)
  3719. dp_peer_unref_delete(peer,
  3720. DP_MOD_ID_TX_COMP);
  3721. peer_id = desc->peer_id;
  3722. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3723. DP_MOD_ID_TX_COMP);
  3724. }
  3725. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3726. struct dp_pdev *pdev = desc->pdev;
  3727. if (qdf_likely(peer))
  3728. dp_tx_update_peer_basic_stats(peer,
  3729. desc->length,
  3730. desc->tx_status,
  3731. false);
  3732. qdf_assert(pdev);
  3733. dp_tx_outstanding_dec(pdev);
  3734. /*
  3735. * Calling a QDF WRAPPER here is creating signifcant
  3736. * performance impact so avoided the wrapper call here
  3737. */
  3738. next = desc->next;
  3739. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  3740. desc->id, DP_TX_COMP_UNMAP);
  3741. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  3742. desc->nbuf,
  3743. desc->dma_addr,
  3744. QDF_DMA_TO_DEVICE,
  3745. desc->length);
  3746. qdf_nbuf_free(desc->nbuf);
  3747. dp_tx_desc_free(soc, desc, desc->pool_id);
  3748. desc = next;
  3749. continue;
  3750. }
  3751. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3752. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3753. netbuf = desc->nbuf;
  3754. /* check tx complete notification */
  3755. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3756. dp_tx_notify_completion(soc, peer->vdev, desc,
  3757. netbuf, ts.status);
  3758. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3759. next = desc->next;
  3760. dp_tx_desc_release(desc, desc->pool_id);
  3761. desc = next;
  3762. }
  3763. if (peer)
  3764. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3765. }
  3766. /**
  3767. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3768. * @soc: Handle to DP soc structure
  3769. * @tx_desc: software descriptor head pointer
  3770. * @status : Tx completion status from HTT descriptor
  3771. * @ring_id: ring number
  3772. *
  3773. * This function will process HTT Tx indication messages from Target
  3774. *
  3775. * Return: none
  3776. */
  3777. static
  3778. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3779. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3780. uint8_t ring_id)
  3781. {
  3782. uint8_t tx_status;
  3783. struct dp_pdev *pdev;
  3784. struct dp_vdev *vdev;
  3785. struct hal_tx_completion_status ts = {0};
  3786. uint32_t *htt_desc = (uint32_t *)status;
  3787. struct dp_peer *peer;
  3788. struct cdp_tid_tx_stats *tid_stats = NULL;
  3789. struct htt_soc *htt_handle;
  3790. uint8_t vdev_id;
  3791. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3792. htt_handle = (struct htt_soc *)soc->htt_handle;
  3793. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3794. /*
  3795. * There can be scenario where WBM consuming descriptor enqueued
  3796. * from TQM2WBM first and TQM completion can happen before MEC
  3797. * notification comes from FW2WBM. Avoid access any field of tx
  3798. * descriptor in case of MEC notify.
  3799. */
  3800. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3801. if (soc->mec_fw_offload)
  3802. return;
  3803. /*
  3804. * Get vdev id from HTT status word in case of MEC
  3805. * notification
  3806. */
  3807. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3808. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3809. return;
  3810. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3811. DP_MOD_ID_HTT_COMP);
  3812. if (!vdev)
  3813. return;
  3814. dp_tx_mec_handler(vdev, status);
  3815. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3816. return;
  3817. }
  3818. /*
  3819. * If the descriptor is already freed in vdev_detach,
  3820. * continue to next descriptor
  3821. */
  3822. if (qdf_unlikely(!tx_desc->flags)) {
  3823. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d", tx_desc->id);
  3824. return;
  3825. }
  3826. if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
  3827. dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
  3828. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  3829. dp_tx_comp_free_buf(soc, tx_desc);
  3830. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3831. return;
  3832. }
  3833. pdev = tx_desc->pdev;
  3834. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3835. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  3836. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  3837. dp_tx_comp_free_buf(soc, tx_desc);
  3838. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3839. return;
  3840. }
  3841. qdf_assert(tx_desc->pdev);
  3842. vdev_id = tx_desc->vdev_id;
  3843. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3844. DP_MOD_ID_HTT_COMP);
  3845. if (qdf_unlikely(!vdev)) {
  3846. dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
  3847. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  3848. dp_tx_comp_free_buf(soc, tx_desc);
  3849. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3850. return;
  3851. }
  3852. switch (tx_status) {
  3853. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3854. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3855. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3856. {
  3857. uint8_t tid;
  3858. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3859. ts.peer_id =
  3860. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3861. htt_desc[2]);
  3862. ts.tid =
  3863. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3864. htt_desc[2]);
  3865. } else {
  3866. ts.peer_id = HTT_INVALID_PEER;
  3867. ts.tid = HTT_INVALID_TID;
  3868. }
  3869. ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  3870. ts.ppdu_id =
  3871. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3872. htt_desc[1]);
  3873. ts.ack_frame_rssi =
  3874. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3875. htt_desc[1]);
  3876. ts.tsf = htt_desc[3];
  3877. ts.first_msdu = 1;
  3878. ts.last_msdu = 1;
  3879. tid = ts.tid;
  3880. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3881. tid = CDP_MAX_DATA_TIDS - 1;
  3882. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3883. if (qdf_unlikely(pdev->delay_stats_flag))
  3884. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3885. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3886. tid_stats->htt_status_cnt[tx_status]++;
  3887. }
  3888. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3889. DP_MOD_ID_HTT_COMP);
  3890. if (qdf_likely(peer))
  3891. dp_tx_update_peer_basic_stats(peer,
  3892. qdf_nbuf_len(tx_desc->nbuf),
  3893. tx_status,
  3894. pdev->enhanced_stats_en);
  3895. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3896. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3897. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3898. if (qdf_likely(peer))
  3899. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3900. break;
  3901. }
  3902. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3903. {
  3904. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3905. break;
  3906. }
  3907. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3908. {
  3909. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3910. break;
  3911. }
  3912. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  3913. {
  3914. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3915. goto release_tx_desc;
  3916. }
  3917. default:
  3918. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  3919. tx_status);
  3920. goto release_tx_desc;
  3921. }
  3922. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3923. return;
  3924. release_tx_desc:
  3925. dp_tx_comp_free_buf(soc, tx_desc);
  3926. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3927. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3928. }
  3929. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3930. static inline
  3931. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3932. int max_reap_limit)
  3933. {
  3934. bool limit_hit = false;
  3935. limit_hit =
  3936. (num_reaped >= max_reap_limit) ? true : false;
  3937. if (limit_hit)
  3938. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3939. return limit_hit;
  3940. }
  3941. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3942. {
  3943. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3944. }
  3945. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3946. {
  3947. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3948. return cfg->tx_comp_loop_pkt_limit;
  3949. }
  3950. #else
  3951. static inline
  3952. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3953. int max_reap_limit)
  3954. {
  3955. return false;
  3956. }
  3957. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3958. {
  3959. return false;
  3960. }
  3961. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3962. {
  3963. return 0;
  3964. }
  3965. #endif
  3966. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  3967. static inline int
  3968. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  3969. int *max_reap_limit)
  3970. {
  3971. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  3972. max_reap_limit);
  3973. }
  3974. #else
  3975. static inline int
  3976. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  3977. int *max_reap_limit)
  3978. {
  3979. return 0;
  3980. }
  3981. #endif
  3982. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3983. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3984. uint32_t quota)
  3985. {
  3986. void *tx_comp_hal_desc;
  3987. uint8_t buffer_src;
  3988. struct dp_tx_desc_s *tx_desc = NULL;
  3989. struct dp_tx_desc_s *head_desc = NULL;
  3990. struct dp_tx_desc_s *tail_desc = NULL;
  3991. uint32_t num_processed = 0;
  3992. uint32_t count;
  3993. uint32_t num_avail_for_reap = 0;
  3994. bool force_break = false;
  3995. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  3996. int max_reap_limit, ring_near_full;
  3997. DP_HIST_INIT();
  3998. more_data:
  3999. /* Re-initialize local variables to be re-used */
  4000. head_desc = NULL;
  4001. tail_desc = NULL;
  4002. count = 0;
  4003. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4004. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4005. &max_reap_limit);
  4006. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4007. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4008. return 0;
  4009. }
  4010. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  4011. if (num_avail_for_reap >= quota)
  4012. num_avail_for_reap = quota;
  4013. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4014. /* Find head descriptor from completion ring */
  4015. while (qdf_likely(num_avail_for_reap--)) {
  4016. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4017. if (qdf_unlikely(!tx_comp_hal_desc))
  4018. break;
  4019. buffer_src = hal_tx_comp_get_buffer_source(soc->hal_soc,
  4020. tx_comp_hal_desc);
  4021. /* If this buffer was not released by TQM or FW, then it is not
  4022. * Tx completion indication, assert */
  4023. if (qdf_unlikely(buffer_src !=
  4024. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4025. (qdf_unlikely(buffer_src !=
  4026. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4027. uint8_t wbm_internal_error;
  4028. dp_err_rl(
  4029. "Tx comp release_src != TQM | FW but from %d",
  4030. buffer_src);
  4031. hal_dump_comp_desc(tx_comp_hal_desc);
  4032. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4033. /* When WBM sees NULL buffer_addr_info in any of
  4034. * ingress rings it sends an error indication,
  4035. * with wbm_internal_error=1, to a specific ring.
  4036. * The WBM2SW ring used to indicate these errors is
  4037. * fixed in HW, and that ring is being used as Tx
  4038. * completion ring. These errors are not related to
  4039. * Tx completions, and should just be ignored
  4040. */
  4041. wbm_internal_error = hal_get_wbm_internal_error(
  4042. soc->hal_soc,
  4043. tx_comp_hal_desc);
  4044. if (wbm_internal_error) {
  4045. dp_err_rl("Tx comp wbm_internal_error!!");
  4046. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4047. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4048. buffer_src)
  4049. dp_handle_wbm_internal_error(
  4050. soc,
  4051. tx_comp_hal_desc,
  4052. hal_tx_comp_get_buffer_type(
  4053. tx_comp_hal_desc));
  4054. } else {
  4055. dp_err_rl("Tx comp wbm_internal_error false");
  4056. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4057. }
  4058. continue;
  4059. }
  4060. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4061. tx_comp_hal_desc,
  4062. &tx_desc);
  4063. if (!tx_desc) {
  4064. dp_err("unable to retrieve tx_desc!");
  4065. QDF_BUG(0);
  4066. continue;
  4067. }
  4068. tx_desc->buffer_src = buffer_src;
  4069. /*
  4070. * If the release source is FW, process the HTT status
  4071. */
  4072. if (qdf_unlikely(buffer_src ==
  4073. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4074. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4075. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4076. htt_tx_status);
  4077. dp_tx_process_htt_completion(soc, tx_desc,
  4078. htt_tx_status, ring_id);
  4079. } else {
  4080. tx_desc->tx_status =
  4081. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4082. tx_desc->buffer_src = buffer_src;
  4083. /*
  4084. * If the fast completion mode is enabled extended
  4085. * metadata from descriptor is not copied
  4086. */
  4087. if (qdf_likely(tx_desc->flags &
  4088. DP_TX_DESC_FLAG_SIMPLE))
  4089. goto add_to_pool;
  4090. /*
  4091. * If the descriptor is already freed in vdev_detach,
  4092. * continue to next descriptor
  4093. */
  4094. if (qdf_unlikely
  4095. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4096. !tx_desc->flags)) {
  4097. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4098. tx_desc->id);
  4099. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4100. continue;
  4101. }
  4102. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4103. dp_tx_comp_info_rl("pdev in down state %d",
  4104. tx_desc->id);
  4105. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4106. dp_tx_comp_free_buf(soc, tx_desc);
  4107. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4108. goto next_desc;
  4109. }
  4110. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4111. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4112. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4113. tx_desc->flags, tx_desc->id);
  4114. qdf_assert_always(0);
  4115. }
  4116. /* Collect hw completion contents */
  4117. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4118. &tx_desc->comp, 1);
  4119. add_to_pool:
  4120. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4121. /* First ring descriptor on the cycle */
  4122. if (!head_desc) {
  4123. head_desc = tx_desc;
  4124. tail_desc = tx_desc;
  4125. }
  4126. tail_desc->next = tx_desc;
  4127. tx_desc->next = NULL;
  4128. tail_desc = tx_desc;
  4129. }
  4130. next_desc:
  4131. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4132. /*
  4133. * Processed packet count is more than given quota
  4134. * stop to processing
  4135. */
  4136. count++;
  4137. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4138. break;
  4139. }
  4140. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4141. /* Process the reaped descriptors */
  4142. if (head_desc)
  4143. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4144. /*
  4145. * If we are processing in near-full condition, there are 3 scenario
  4146. * 1) Ring entries has reached critical state
  4147. * 2) Ring entries are still near high threshold
  4148. * 3) Ring entries are below the safe level
  4149. *
  4150. * One more loop will move te state to normal processing and yield
  4151. */
  4152. if (ring_near_full)
  4153. goto more_data;
  4154. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4155. if (num_processed >= quota)
  4156. force_break = true;
  4157. if (!force_break &&
  4158. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4159. hal_ring_hdl)) {
  4160. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4161. if (!hif_exec_should_yield(soc->hif_handle,
  4162. int_ctx->dp_intr_id))
  4163. goto more_data;
  4164. }
  4165. }
  4166. DP_TX_HIST_STATS_PER_PDEV();
  4167. return num_processed;
  4168. }
  4169. #ifdef FEATURE_WLAN_TDLS
  4170. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4171. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4172. {
  4173. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4174. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4175. DP_MOD_ID_TDLS);
  4176. if (!vdev) {
  4177. dp_err("vdev handle for id %d is NULL", vdev_id);
  4178. return NULL;
  4179. }
  4180. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4181. vdev->is_tdls_frame = true;
  4182. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4183. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4184. }
  4185. #endif
  4186. /**
  4187. * dp_tx_vdev_attach() - attach vdev to dp tx
  4188. * @vdev: virtual device instance
  4189. *
  4190. * Return: QDF_STATUS_SUCCESS: success
  4191. * QDF_STATUS_E_RESOURCES: Error return
  4192. */
  4193. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4194. {
  4195. int pdev_id;
  4196. /*
  4197. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4198. */
  4199. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4200. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4201. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4202. vdev->vdev_id);
  4203. pdev_id =
  4204. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4205. vdev->pdev->pdev_id);
  4206. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4207. /*
  4208. * Set HTT Extension Valid bit to 0 by default
  4209. */
  4210. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4211. dp_tx_vdev_update_search_flags(vdev);
  4212. return QDF_STATUS_SUCCESS;
  4213. }
  4214. #ifndef FEATURE_WDS
  4215. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4216. {
  4217. return false;
  4218. }
  4219. #endif
  4220. /**
  4221. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4222. * @vdev: virtual device instance
  4223. *
  4224. * Return: void
  4225. *
  4226. */
  4227. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4228. {
  4229. struct dp_soc *soc = vdev->pdev->soc;
  4230. /*
  4231. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4232. * for TDLS link
  4233. *
  4234. * Enable AddrY (SA based search) only for non-WDS STA and
  4235. * ProxySTA VAP (in HKv1) modes.
  4236. *
  4237. * In all other VAP modes, only DA based search should be
  4238. * enabled
  4239. */
  4240. if (vdev->opmode == wlan_op_mode_sta &&
  4241. vdev->tdls_link_connected)
  4242. vdev->hal_desc_addr_search_flags =
  4243. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4244. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4245. !dp_tx_da_search_override(vdev))
  4246. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4247. else
  4248. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4249. if (vdev->opmode == wlan_op_mode_sta)
  4250. vdev->search_type = soc->sta_mode_search_policy;
  4251. else
  4252. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4253. }
  4254. static inline bool
  4255. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4256. struct dp_vdev *vdev,
  4257. struct dp_tx_desc_s *tx_desc)
  4258. {
  4259. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4260. return false;
  4261. /*
  4262. * if vdev is given, then only check whether desc
  4263. * vdev match. if vdev is NULL, then check whether
  4264. * desc pdev match.
  4265. */
  4266. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4267. (tx_desc->pdev == pdev);
  4268. }
  4269. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4270. /**
  4271. * dp_tx_desc_flush() - release resources associated
  4272. * to TX Desc
  4273. *
  4274. * @dp_pdev: Handle to DP pdev structure
  4275. * @vdev: virtual device instance
  4276. * NULL: no specific Vdev is required and check all allcated TX desc
  4277. * on this pdev.
  4278. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4279. *
  4280. * @force_free:
  4281. * true: flush the TX desc.
  4282. * false: only reset the Vdev in each allocated TX desc
  4283. * that associated to current Vdev.
  4284. *
  4285. * This function will go through the TX desc pool to flush
  4286. * the outstanding TX data or reset Vdev to NULL in associated TX
  4287. * Desc.
  4288. */
  4289. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4290. bool force_free)
  4291. {
  4292. uint8_t i;
  4293. uint32_t j;
  4294. uint32_t num_desc, page_id, offset;
  4295. uint16_t num_desc_per_page;
  4296. struct dp_soc *soc = pdev->soc;
  4297. struct dp_tx_desc_s *tx_desc = NULL;
  4298. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4299. if (!vdev && !force_free) {
  4300. dp_err("Reset TX desc vdev, Vdev param is required!");
  4301. return;
  4302. }
  4303. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4304. tx_desc_pool = &soc->tx_desc[i];
  4305. if (!(tx_desc_pool->pool_size) ||
  4306. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4307. !(tx_desc_pool->desc_pages.cacheable_pages))
  4308. continue;
  4309. /*
  4310. * Add flow pool lock protection in case pool is freed
  4311. * due to all tx_desc is recycled when handle TX completion.
  4312. * this is not necessary when do force flush as:
  4313. * a. double lock will happen if dp_tx_desc_release is
  4314. * also trying to acquire it.
  4315. * b. dp interrupt has been disabled before do force TX desc
  4316. * flush in dp_pdev_deinit().
  4317. */
  4318. if (!force_free)
  4319. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4320. num_desc = tx_desc_pool->pool_size;
  4321. num_desc_per_page =
  4322. tx_desc_pool->desc_pages.num_element_per_page;
  4323. for (j = 0; j < num_desc; j++) {
  4324. page_id = j / num_desc_per_page;
  4325. offset = j % num_desc_per_page;
  4326. if (qdf_unlikely(!(tx_desc_pool->
  4327. desc_pages.cacheable_pages)))
  4328. break;
  4329. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4330. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4331. /*
  4332. * Free TX desc if force free is
  4333. * required, otherwise only reset vdev
  4334. * in this TX desc.
  4335. */
  4336. if (force_free) {
  4337. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4338. dp_tx_comp_free_buf(soc, tx_desc);
  4339. dp_tx_desc_release(tx_desc, i);
  4340. } else {
  4341. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4342. }
  4343. }
  4344. }
  4345. if (!force_free)
  4346. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4347. }
  4348. }
  4349. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4350. /**
  4351. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4352. *
  4353. * @soc: Handle to DP soc structure
  4354. * @tx_desc: pointer of one TX desc
  4355. * @desc_pool_id: TX Desc pool id
  4356. */
  4357. static inline void
  4358. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4359. uint8_t desc_pool_id)
  4360. {
  4361. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4362. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4363. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4364. }
  4365. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4366. bool force_free)
  4367. {
  4368. uint8_t i, num_pool;
  4369. uint32_t j;
  4370. uint32_t num_desc, page_id, offset;
  4371. uint16_t num_desc_per_page;
  4372. struct dp_soc *soc = pdev->soc;
  4373. struct dp_tx_desc_s *tx_desc = NULL;
  4374. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4375. if (!vdev && !force_free) {
  4376. dp_err("Reset TX desc vdev, Vdev param is required!");
  4377. return;
  4378. }
  4379. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4380. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4381. for (i = 0; i < num_pool; i++) {
  4382. tx_desc_pool = &soc->tx_desc[i];
  4383. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4384. continue;
  4385. num_desc_per_page =
  4386. tx_desc_pool->desc_pages.num_element_per_page;
  4387. for (j = 0; j < num_desc; j++) {
  4388. page_id = j / num_desc_per_page;
  4389. offset = j % num_desc_per_page;
  4390. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4391. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4392. if (force_free) {
  4393. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4394. dp_tx_comp_free_buf(soc, tx_desc);
  4395. dp_tx_desc_release(tx_desc, i);
  4396. } else {
  4397. dp_tx_desc_reset_vdev(soc, tx_desc,
  4398. i);
  4399. }
  4400. }
  4401. }
  4402. }
  4403. }
  4404. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4405. /**
  4406. * dp_tx_vdev_detach() - detach vdev from dp tx
  4407. * @vdev: virtual device instance
  4408. *
  4409. * Return: QDF_STATUS_SUCCESS: success
  4410. * QDF_STATUS_E_RESOURCES: Error return
  4411. */
  4412. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4413. {
  4414. struct dp_pdev *pdev = vdev->pdev;
  4415. /* Reset TX desc associated to this Vdev as NULL */
  4416. dp_tx_desc_flush(pdev, vdev, false);
  4417. return QDF_STATUS_SUCCESS;
  4418. }
  4419. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4420. /* Pools will be allocated dynamically */
  4421. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4422. int num_desc)
  4423. {
  4424. uint8_t i;
  4425. for (i = 0; i < num_pool; i++) {
  4426. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4427. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4428. }
  4429. return QDF_STATUS_SUCCESS;
  4430. }
  4431. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4432. int num_desc)
  4433. {
  4434. return QDF_STATUS_SUCCESS;
  4435. }
  4436. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4437. {
  4438. }
  4439. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4440. {
  4441. uint8_t i;
  4442. for (i = 0; i < num_pool; i++)
  4443. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4444. }
  4445. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4446. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4447. int num_desc)
  4448. {
  4449. uint8_t i, count;
  4450. /* Allocate software Tx descriptor pools */
  4451. for (i = 0; i < num_pool; i++) {
  4452. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4453. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4454. FL("Tx Desc Pool alloc %d failed %pK"),
  4455. i, soc);
  4456. goto fail;
  4457. }
  4458. }
  4459. return QDF_STATUS_SUCCESS;
  4460. fail:
  4461. for (count = 0; count < i; count++)
  4462. dp_tx_desc_pool_free(soc, count);
  4463. return QDF_STATUS_E_NOMEM;
  4464. }
  4465. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4466. int num_desc)
  4467. {
  4468. uint8_t i;
  4469. for (i = 0; i < num_pool; i++) {
  4470. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4471. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4472. FL("Tx Desc Pool init %d failed %pK"),
  4473. i, soc);
  4474. return QDF_STATUS_E_NOMEM;
  4475. }
  4476. }
  4477. return QDF_STATUS_SUCCESS;
  4478. }
  4479. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4480. {
  4481. uint8_t i;
  4482. for (i = 0; i < num_pool; i++)
  4483. dp_tx_desc_pool_deinit(soc, i);
  4484. }
  4485. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4486. {
  4487. uint8_t i;
  4488. for (i = 0; i < num_pool; i++)
  4489. dp_tx_desc_pool_free(soc, i);
  4490. }
  4491. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4492. /**
  4493. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4494. * @soc: core txrx main context
  4495. * @num_pool: number of pools
  4496. *
  4497. */
  4498. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4499. {
  4500. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4501. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4502. }
  4503. /**
  4504. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4505. * @soc: core txrx main context
  4506. * @num_pool: number of pools
  4507. *
  4508. */
  4509. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4510. {
  4511. dp_tx_tso_desc_pool_free(soc, num_pool);
  4512. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4513. }
  4514. /**
  4515. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4516. * @soc: core txrx main context
  4517. *
  4518. * This function frees all tx related descriptors as below
  4519. * 1. Regular TX descriptors (static pools)
  4520. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4521. * 3. TSO descriptors
  4522. *
  4523. */
  4524. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4525. {
  4526. uint8_t num_pool;
  4527. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4528. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4529. dp_tx_ext_desc_pool_free(soc, num_pool);
  4530. dp_tx_delete_static_pools(soc, num_pool);
  4531. }
  4532. /**
  4533. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4534. * @soc: core txrx main context
  4535. *
  4536. * This function de-initializes all tx related descriptors as below
  4537. * 1. Regular TX descriptors (static pools)
  4538. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4539. * 3. TSO descriptors
  4540. *
  4541. */
  4542. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4543. {
  4544. uint8_t num_pool;
  4545. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4546. dp_tx_flow_control_deinit(soc);
  4547. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4548. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4549. dp_tx_deinit_static_pools(soc, num_pool);
  4550. }
  4551. /**
  4552. * dp_tso_attach() - TSO attach handler
  4553. * @txrx_soc: Opaque Dp handle
  4554. *
  4555. * Reserve TSO descriptor buffers
  4556. *
  4557. * Return: QDF_STATUS_E_FAILURE on failure or
  4558. * QDF_STATUS_SUCCESS on success
  4559. */
  4560. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4561. uint8_t num_pool,
  4562. uint16_t num_desc)
  4563. {
  4564. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4565. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4566. return QDF_STATUS_E_FAILURE;
  4567. }
  4568. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4569. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4570. num_pool, soc);
  4571. return QDF_STATUS_E_FAILURE;
  4572. }
  4573. return QDF_STATUS_SUCCESS;
  4574. }
  4575. /**
  4576. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4577. * @soc: DP soc handle
  4578. * @num_pool: Number of pools
  4579. * @num_desc: Number of descriptors
  4580. *
  4581. * Initialize TSO descriptor pools
  4582. *
  4583. * Return: QDF_STATUS_E_FAILURE on failure or
  4584. * QDF_STATUS_SUCCESS on success
  4585. */
  4586. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4587. uint8_t num_pool,
  4588. uint16_t num_desc)
  4589. {
  4590. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4591. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4592. return QDF_STATUS_E_FAILURE;
  4593. }
  4594. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4595. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4596. num_pool, soc);
  4597. return QDF_STATUS_E_FAILURE;
  4598. }
  4599. return QDF_STATUS_SUCCESS;
  4600. }
  4601. /**
  4602. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4603. * @soc: core txrx main context
  4604. *
  4605. * This function allocates memory for following descriptor pools
  4606. * 1. regular sw tx descriptor pools (static pools)
  4607. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4608. * 3. TSO descriptor pools
  4609. *
  4610. * Return: QDF_STATUS_SUCCESS: success
  4611. * QDF_STATUS_E_RESOURCES: Error return
  4612. */
  4613. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4614. {
  4615. uint8_t num_pool;
  4616. uint32_t num_desc;
  4617. uint32_t num_ext_desc;
  4618. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4619. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4620. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4621. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4622. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4623. __func__, num_pool, num_desc);
  4624. if ((num_pool > MAX_TXDESC_POOLS) ||
  4625. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4626. goto fail1;
  4627. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4628. goto fail1;
  4629. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4630. goto fail2;
  4631. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4632. return QDF_STATUS_SUCCESS;
  4633. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4634. goto fail3;
  4635. return QDF_STATUS_SUCCESS;
  4636. fail3:
  4637. dp_tx_ext_desc_pool_free(soc, num_pool);
  4638. fail2:
  4639. dp_tx_delete_static_pools(soc, num_pool);
  4640. fail1:
  4641. return QDF_STATUS_E_RESOURCES;
  4642. }
  4643. /**
  4644. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4645. * @soc: core txrx main context
  4646. *
  4647. * This function initializes the following TX descriptor pools
  4648. * 1. regular sw tx descriptor pools (static pools)
  4649. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4650. * 3. TSO descriptor pools
  4651. *
  4652. * Return: QDF_STATUS_SUCCESS: success
  4653. * QDF_STATUS_E_RESOURCES: Error return
  4654. */
  4655. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4656. {
  4657. uint8_t num_pool;
  4658. uint32_t num_desc;
  4659. uint32_t num_ext_desc;
  4660. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4661. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4662. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4663. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4664. goto fail1;
  4665. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4666. goto fail2;
  4667. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4668. return QDF_STATUS_SUCCESS;
  4669. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4670. goto fail3;
  4671. dp_tx_flow_control_init(soc);
  4672. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4673. return QDF_STATUS_SUCCESS;
  4674. fail3:
  4675. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4676. fail2:
  4677. dp_tx_deinit_static_pools(soc, num_pool);
  4678. fail1:
  4679. return QDF_STATUS_E_RESOURCES;
  4680. }
  4681. /**
  4682. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4683. * @txrx_soc: dp soc handle
  4684. *
  4685. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4686. * QDF_STATUS_E_FAILURE
  4687. */
  4688. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4689. {
  4690. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4691. uint8_t num_pool;
  4692. uint32_t num_desc;
  4693. uint32_t num_ext_desc;
  4694. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4695. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4696. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4697. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4698. return QDF_STATUS_E_FAILURE;
  4699. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4700. return QDF_STATUS_E_FAILURE;
  4701. return QDF_STATUS_SUCCESS;
  4702. }
  4703. /**
  4704. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4705. * @txrx_soc: dp soc handle
  4706. *
  4707. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4708. */
  4709. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4710. {
  4711. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4712. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4713. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4714. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4715. return QDF_STATUS_SUCCESS;
  4716. }