internal.h 4.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _WCD938X_INTERNAL_H
  6. #define _WCD938X_INTERNAL_H
  7. #include <asoc/wcd-mbhc-v2.h>
  8. #include <asoc/wcd-irq.h>
  9. #include <asoc/wcd-clsh.h>
  10. #include "wcd938x-mbhc.h"
  11. #define WCD938X_MAX_MICBIAS 4
  12. /* Convert from vout ctl to micbias voltage in mV */
  13. #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
  14. #define MAX_PORT 8
  15. #define MAX_CH_PER_PORT 8
  16. #define TX_ADC_MAX 4
  17. enum {
  18. TX_HDR12 = 0,
  19. TX_HDR34,
  20. TX_HDR_MAX,
  21. };
  22. extern struct regmap_config wcd938x_regmap_config;
  23. struct codec_port_info {
  24. u32 slave_port_type;
  25. u32 master_port_type;
  26. u32 ch_mask;
  27. u32 num_ch;
  28. u32 ch_rate;
  29. };
  30. struct wcd938x_priv {
  31. struct device *dev;
  32. int variant;
  33. struct snd_soc_component *component;
  34. struct device_node *rst_np;
  35. struct regmap *regmap;
  36. struct swr_device *rx_swr_dev;
  37. struct swr_device *tx_swr_dev;
  38. s32 micb_ref[WCD938X_MAX_MICBIAS];
  39. s32 pullup_ref[WCD938X_MAX_MICBIAS];
  40. struct fw_info *fw_data;
  41. struct device_node *wcd_rst_np;
  42. struct mutex micb_lock;
  43. s32 dmic_0_1_clk_cnt;
  44. s32 dmic_2_3_clk_cnt;
  45. s32 dmic_4_5_clk_cnt;
  46. s32 dmic_6_7_clk_cnt;
  47. int hdr_en[TX_HDR_MAX];
  48. /* class h specific info */
  49. struct wcd_clsh_cdc_info clsh_info;
  50. /* mbhc module */
  51. struct wcd938x_mbhc *mbhc;
  52. u32 hph_mode;
  53. u32 tx_mode[TX_ADC_MAX];
  54. bool comp1_enable;
  55. bool comp2_enable;
  56. struct irq_domain *virq;
  57. struct wcd_irq_info irq_info;
  58. u32 rx_clk_cnt;
  59. int num_irq_regs;
  60. /* to track the status */
  61. unsigned long status_mask;
  62. u8 num_tx_ports;
  63. u8 num_rx_ports;
  64. struct codec_port_info
  65. tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  66. struct codec_port_info
  67. rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
  68. struct regulator_bulk_data *supplies;
  69. struct notifier_block nblock;
  70. /* wcd callback to bolero */
  71. void *handle;
  72. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  73. int (*register_notifier)(void *handle,
  74. struct notifier_block *nblock,
  75. bool enable);
  76. int (*wakeup)(void *handle, bool enable);
  77. u32 version;
  78. /* Entry for version info */
  79. struct snd_info_entry *entry;
  80. struct snd_info_entry *version_entry;
  81. };
  82. struct wcd938x_micbias_setting {
  83. u8 ldoh_v;
  84. u32 cfilt1_mv;
  85. u32 micb1_mv;
  86. u32 micb2_mv;
  87. u32 micb3_mv;
  88. u32 micb4_mv;
  89. u8 bias1_cfilt_sel;
  90. };
  91. struct wcd938x_pdata {
  92. struct device_node *rst_np;
  93. struct device_node *rx_slave;
  94. struct device_node *tx_slave;
  95. struct wcd938x_micbias_setting micbias;
  96. struct cdc_regulator *regulator;
  97. int num_supplies;
  98. };
  99. struct wcd_ctrl_platform_data {
  100. void *handle;
  101. int (*update_wcd_event)(void *handle, u16 event, u32 data);
  102. int (*register_notifier)(void *handle,
  103. struct notifier_block *nblock,
  104. bool enable);
  105. };
  106. enum {
  107. WCD_RX1,
  108. WCD_RX2,
  109. WCD_RX3
  110. };
  111. enum {
  112. BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR = 1,
  113. BOLERO_WCD_EVT_PA_OFF_PRE_SSR,
  114. BOLERO_WCD_EVT_SSR_DOWN,
  115. BOLERO_WCD_EVT_SSR_UP,
  116. BOLERO_WCD_EVT_CLK_NOTIFY,
  117. };
  118. enum {
  119. WCD_BOLERO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
  120. WCD_BOLERO_EVT_IMPED_TRUE, /* for imped true */
  121. WCD_BOLERO_EVT_IMPED_FALSE, /* for imped false */
  122. };
  123. enum {
  124. /* INTR_CTRL_INT_MASK_0 */
  125. WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET = 0,
  126. WCD938X_IRQ_MBHC_BUTTON_PRESS_DET,
  127. WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
  128. WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
  129. WCD938X_IRQ_MBHC_SW_DET,
  130. WCD938X_IRQ_HPHR_OCP_INT,
  131. WCD938X_IRQ_HPHR_CNP_INT,
  132. WCD938X_IRQ_HPHL_OCP_INT,
  133. /* INTR_CTRL_INT_MASK_1 */
  134. WCD938X_IRQ_HPHL_CNP_INT,
  135. WCD938X_IRQ_EAR_CNP_INT,
  136. WCD938X_IRQ_EAR_SCD_INT,
  137. WCD938X_IRQ_AUX_CNP_INT,
  138. WCD938X_IRQ_AUX_SCD_INT,
  139. WCD938X_IRQ_HPHL_PDM_WD_INT,
  140. WCD938X_IRQ_HPHR_PDM_WD_INT,
  141. WCD938X_IRQ_AUX_PDM_WD_INT,
  142. /* INTR_CTRL_INT_MASK_2 */
  143. WCD938X_IRQ_LDORT_SCD_INT,
  144. WCD938X_IRQ_MBHC_MOISTURE_INT,
  145. WCD938X_IRQ_HPHL_SURGE_DET_INT,
  146. WCD938X_IRQ_HPHR_SURGE_DET_INT,
  147. WCD938X_NUM_IRQS,
  148. };
  149. extern struct wcd938x_mbhc *wcd938x_soc_get_mbhc(
  150. struct snd_soc_component *component);
  151. extern int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  152. int volt, int micb_num);
  153. extern int wcd938x_get_micb_vout_ctl_val(u32 micb_mv);
  154. extern int wcd938x_micbias_control(struct snd_soc_component *component,
  155. int micb_num, int req, bool is_dapm);
  156. #endif /* _WCD938X_INTERNAL_H */