dp_tx.c 151 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef WLAN_MCAST_MLO
  66. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  67. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  68. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  69. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  78. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  79. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  80. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  82. #else
  83. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  84. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  85. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  86. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  95. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  96. HTT_TCL_METADATA_TYPE_PEER_BASED
  97. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  98. HTT_TCL_METADATA_TYPE_VDEV_BASED
  99. #endif
  100. /*mapping between hal encrypt type and cdp_sec_type*/
  101. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  102. HAL_TX_ENCRYPT_TYPE_WEP_128,
  103. HAL_TX_ENCRYPT_TYPE_WEP_104,
  104. HAL_TX_ENCRYPT_TYPE_WEP_40,
  105. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  106. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  107. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  108. HAL_TX_ENCRYPT_TYPE_WAPI,
  109. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  110. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  111. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  112. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  113. qdf_export_symbol(sec_type_map);
  114. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  115. /**
  116. * dp_update_tx_desc_stats - Update the increase or decrease in
  117. * outstanding tx desc count
  118. * values on pdev and soc
  119. * @vdev: DP pdev handle
  120. *
  121. * Return: void
  122. */
  123. static inline void
  124. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  125. {
  126. int32_t tx_descs_cnt =
  127. qdf_atomic_read(&pdev->num_tx_outstanding);
  128. if (pdev->tx_descs_max < tx_descs_cnt)
  129. pdev->tx_descs_max = tx_descs_cnt;
  130. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  131. pdev->tx_descs_max);
  132. }
  133. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  134. static inline void
  135. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  136. {
  137. }
  138. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  139. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  140. static inline
  141. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  142. {
  143. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  144. QDF_DMA_TO_DEVICE,
  145. desc->nbuf->len);
  146. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  147. }
  148. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  149. {
  150. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  151. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  152. QDF_DMA_TO_DEVICE,
  153. desc->nbuf->len);
  154. }
  155. #else
  156. static inline
  157. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  158. {
  159. }
  160. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  161. {
  162. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  163. QDF_DMA_TO_DEVICE, desc->nbuf->len);
  164. }
  165. #endif
  166. #ifdef QCA_TX_LIMIT_CHECK
  167. /**
  168. * dp_tx_limit_check - Check if allocated tx descriptors reached
  169. * soc max limit and pdev max limit
  170. * @vdev: DP vdev handle
  171. *
  172. * Return: true if allocated tx descriptors reached max configured value, else
  173. * false
  174. */
  175. static inline bool
  176. dp_tx_limit_check(struct dp_vdev *vdev)
  177. {
  178. struct dp_pdev *pdev = vdev->pdev;
  179. struct dp_soc *soc = pdev->soc;
  180. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  181. soc->num_tx_allowed) {
  182. dp_tx_info("queued packets are more than max tx, drop the frame");
  183. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  184. return true;
  185. }
  186. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  187. pdev->num_tx_allowed) {
  188. dp_tx_info("queued packets are more than max tx, drop the frame");
  189. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  190. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  191. return true;
  192. }
  193. return false;
  194. }
  195. /**
  196. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  197. * reached soc max limit
  198. * @vdev: DP vdev handle
  199. *
  200. * Return: true if allocated tx descriptors reached max configured value, else
  201. * false
  202. */
  203. static inline bool
  204. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  205. {
  206. struct dp_pdev *pdev = vdev->pdev;
  207. struct dp_soc *soc = pdev->soc;
  208. if (qdf_atomic_read(&soc->num_tx_exception) >=
  209. soc->num_msdu_exception_desc) {
  210. dp_info("exc packets are more than max drop the exc pkt");
  211. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  212. return true;
  213. }
  214. return false;
  215. }
  216. /**
  217. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  218. * @vdev: DP pdev handle
  219. *
  220. * Return: void
  221. */
  222. static inline void
  223. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  224. {
  225. struct dp_soc *soc = pdev->soc;
  226. qdf_atomic_inc(&pdev->num_tx_outstanding);
  227. qdf_atomic_inc(&soc->num_tx_outstanding);
  228. dp_update_tx_desc_stats(pdev);
  229. }
  230. /**
  231. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  232. * @vdev: DP pdev handle
  233. *
  234. * Return: void
  235. */
  236. static inline void
  237. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  238. {
  239. struct dp_soc *soc = pdev->soc;
  240. qdf_atomic_dec(&pdev->num_tx_outstanding);
  241. qdf_atomic_dec(&soc->num_tx_outstanding);
  242. dp_update_tx_desc_stats(pdev);
  243. }
  244. #else //QCA_TX_LIMIT_CHECK
  245. static inline bool
  246. dp_tx_limit_check(struct dp_vdev *vdev)
  247. {
  248. return false;
  249. }
  250. static inline bool
  251. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  252. {
  253. return false;
  254. }
  255. static inline void
  256. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  257. {
  258. qdf_atomic_inc(&pdev->num_tx_outstanding);
  259. dp_update_tx_desc_stats(pdev);
  260. }
  261. static inline void
  262. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  263. {
  264. qdf_atomic_dec(&pdev->num_tx_outstanding);
  265. dp_update_tx_desc_stats(pdev);
  266. }
  267. #endif //QCA_TX_LIMIT_CHECK
  268. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  269. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  270. {
  271. enum dp_tx_event_type type;
  272. if (flags & DP_TX_DESC_FLAG_FLUSH)
  273. type = DP_TX_DESC_FLUSH;
  274. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  275. type = DP_TX_COMP_UNMAP_ERR;
  276. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  277. type = DP_TX_COMP_UNMAP;
  278. else
  279. type = DP_TX_DESC_UNMAP;
  280. return type;
  281. }
  282. static inline void
  283. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  284. qdf_nbuf_t skb, uint32_t sw_cookie,
  285. enum dp_tx_event_type type)
  286. {
  287. struct dp_tx_desc_event *entry;
  288. uint32_t idx;
  289. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  290. return;
  291. switch (type) {
  292. case DP_TX_COMP_UNMAP:
  293. case DP_TX_COMP_UNMAP_ERR:
  294. case DP_TX_COMP_MSDU_EXT:
  295. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  296. DP_TX_COMP_HISTORY_SIZE);
  297. entry = &soc->tx_comp_history->entry[idx];
  298. break;
  299. case DP_TX_DESC_MAP:
  300. case DP_TX_DESC_UNMAP:
  301. case DP_TX_DESC_COOKIE:
  302. case DP_TX_DESC_FLUSH:
  303. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  304. DP_TX_TCL_HISTORY_SIZE);
  305. entry = &soc->tx_tcl_history->entry[idx];
  306. break;
  307. default:
  308. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  309. return;
  310. }
  311. entry->skb = skb;
  312. entry->paddr = paddr;
  313. entry->sw_cookie = sw_cookie;
  314. entry->type = type;
  315. entry->ts = qdf_get_log_timestamp();
  316. }
  317. static inline void
  318. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  319. struct qdf_tso_seg_elem_t *tso_seg,
  320. qdf_nbuf_t skb, uint32_t sw_cookie,
  321. enum dp_tx_event_type type)
  322. {
  323. int i;
  324. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  325. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  326. skb, sw_cookie, type);
  327. }
  328. if (!tso_seg->next)
  329. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  330. skb, 0xFFFFFFFF, type);
  331. }
  332. static inline void
  333. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  334. qdf_nbuf_t skb, uint32_t sw_cookie,
  335. enum dp_tx_event_type type)
  336. {
  337. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  338. uint32_t num_segs = tso_info.num_segs;
  339. while (num_segs) {
  340. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  341. curr_seg = curr_seg->next;
  342. num_segs--;
  343. }
  344. }
  345. #else
  346. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  347. {
  348. return DP_TX_DESC_INVAL_EVT;
  349. }
  350. static inline void
  351. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  352. qdf_nbuf_t skb, uint32_t sw_cookie,
  353. enum dp_tx_event_type type)
  354. {
  355. }
  356. static inline void
  357. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  358. struct qdf_tso_seg_elem_t *tso_seg,
  359. qdf_nbuf_t skb, uint32_t sw_cookie,
  360. enum dp_tx_event_type type)
  361. {
  362. }
  363. static inline void
  364. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  365. qdf_nbuf_t skb, uint32_t sw_cookie,
  366. enum dp_tx_event_type type)
  367. {
  368. }
  369. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  370. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  371. /**
  372. * dp_is_tput_high() - Check if throughput is high
  373. *
  374. * @soc - core txrx main context
  375. *
  376. * The current function is based of the RTPM tput policy variable where RTPM is
  377. * avoided based on throughput.
  378. */
  379. static inline int dp_is_tput_high(struct dp_soc *soc)
  380. {
  381. return dp_get_rtpm_tput_policy_requirement(soc);
  382. }
  383. #if defined(FEATURE_TSO)
  384. /**
  385. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  386. *
  387. * @soc - core txrx main context
  388. * @seg_desc - tso segment descriptor
  389. * @num_seg_desc - tso number segment descriptor
  390. */
  391. static void dp_tx_tso_unmap_segment(
  392. struct dp_soc *soc,
  393. struct qdf_tso_seg_elem_t *seg_desc,
  394. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  395. {
  396. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  397. if (qdf_unlikely(!seg_desc)) {
  398. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  399. __func__, __LINE__);
  400. qdf_assert(0);
  401. } else if (qdf_unlikely(!num_seg_desc)) {
  402. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  403. __func__, __LINE__);
  404. qdf_assert(0);
  405. } else {
  406. bool is_last_seg;
  407. /* no tso segment left to do dma unmap */
  408. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  409. return;
  410. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  411. true : false;
  412. qdf_nbuf_unmap_tso_segment(soc->osdev,
  413. seg_desc, is_last_seg);
  414. num_seg_desc->num_seg.tso_cmn_num_seg--;
  415. }
  416. }
  417. /**
  418. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  419. * back to the freelist
  420. *
  421. * @soc - soc device handle
  422. * @tx_desc - Tx software descriptor
  423. */
  424. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  425. struct dp_tx_desc_s *tx_desc)
  426. {
  427. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  428. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  429. dp_tx_err("SO desc is NULL!");
  430. qdf_assert(0);
  431. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  432. dp_tx_err("TSO num desc is NULL!");
  433. qdf_assert(0);
  434. } else {
  435. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  436. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  437. msdu_ext_desc->tso_num_desc;
  438. /* Add the tso num segment into the free list */
  439. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  440. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  441. tx_desc->msdu_ext_desc->
  442. tso_num_desc);
  443. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  444. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  445. }
  446. /* Add the tso segment into the free list*/
  447. dp_tx_tso_desc_free(soc,
  448. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  449. tso_desc);
  450. tx_desc->msdu_ext_desc->tso_desc = NULL;
  451. }
  452. }
  453. #else
  454. static void dp_tx_tso_unmap_segment(
  455. struct dp_soc *soc,
  456. struct qdf_tso_seg_elem_t *seg_desc,
  457. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  458. {
  459. }
  460. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  461. struct dp_tx_desc_s *tx_desc)
  462. {
  463. }
  464. #endif
  465. /**
  466. * dp_tx_desc_release() - Release Tx Descriptor
  467. * @tx_desc : Tx Descriptor
  468. * @desc_pool_id: Descriptor Pool ID
  469. *
  470. * Deallocate all resources attached to Tx descriptor and free the Tx
  471. * descriptor.
  472. *
  473. * Return:
  474. */
  475. void
  476. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  477. {
  478. struct dp_pdev *pdev = tx_desc->pdev;
  479. struct dp_soc *soc;
  480. uint8_t comp_status = 0;
  481. qdf_assert(pdev);
  482. soc = pdev->soc;
  483. dp_tx_outstanding_dec(pdev);
  484. if (tx_desc->msdu_ext_desc) {
  485. if (tx_desc->frm_type == dp_tx_frm_tso)
  486. dp_tx_tso_desc_release(soc, tx_desc);
  487. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  488. dp_tx_me_free_buf(tx_desc->pdev,
  489. tx_desc->msdu_ext_desc->me_buffer);
  490. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  491. }
  492. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  493. qdf_atomic_dec(&soc->num_tx_exception);
  494. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  495. tx_desc->buffer_src)
  496. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  497. soc->hal_soc);
  498. else
  499. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  500. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  501. tx_desc->id, comp_status,
  502. qdf_atomic_read(&pdev->num_tx_outstanding));
  503. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  504. return;
  505. }
  506. /**
  507. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  508. * @vdev: DP vdev Handle
  509. * @nbuf: skb
  510. * @msdu_info: msdu_info required to create HTT metadata
  511. *
  512. * Prepares and fills HTT metadata in the frame pre-header for special frames
  513. * that should be transmitted using varying transmit parameters.
  514. * There are 2 VDEV modes that currently needs this special metadata -
  515. * 1) Mesh Mode
  516. * 2) DSRC Mode
  517. *
  518. * Return: HTT metadata size
  519. *
  520. */
  521. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  522. struct dp_tx_msdu_info_s *msdu_info)
  523. {
  524. uint32_t *meta_data = msdu_info->meta_data;
  525. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  526. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  527. uint8_t htt_desc_size;
  528. /* Size rounded of multiple of 8 bytes */
  529. uint8_t htt_desc_size_aligned;
  530. uint8_t *hdr = NULL;
  531. /*
  532. * Metadata - HTT MSDU Extension header
  533. */
  534. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  535. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  536. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  537. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  538. meta_data[0])) {
  539. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  540. htt_desc_size_aligned)) {
  541. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  542. htt_desc_size_aligned);
  543. if (!nbuf) {
  544. /*
  545. * qdf_nbuf_realloc_headroom won't do skb_clone
  546. * as skb_realloc_headroom does. so, no free is
  547. * needed here.
  548. */
  549. DP_STATS_INC(vdev,
  550. tx_i.dropped.headroom_insufficient,
  551. 1);
  552. qdf_print(" %s[%d] skb_realloc_headroom failed",
  553. __func__, __LINE__);
  554. return 0;
  555. }
  556. }
  557. /* Fill and add HTT metaheader */
  558. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  559. if (!hdr) {
  560. dp_tx_err("Error in filling HTT metadata");
  561. return 0;
  562. }
  563. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  564. } else if (vdev->opmode == wlan_op_mode_ocb) {
  565. /* Todo - Add support for DSRC */
  566. }
  567. return htt_desc_size_aligned;
  568. }
  569. /**
  570. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  571. * @tso_seg: TSO segment to process
  572. * @ext_desc: Pointer to MSDU extension descriptor
  573. *
  574. * Return: void
  575. */
  576. #if defined(FEATURE_TSO)
  577. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  578. void *ext_desc)
  579. {
  580. uint8_t num_frag;
  581. uint32_t tso_flags;
  582. /*
  583. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  584. * tcp_flag_mask
  585. *
  586. * Checksum enable flags are set in TCL descriptor and not in Extension
  587. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  588. */
  589. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  590. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  591. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  592. tso_seg->tso_flags.ip_len);
  593. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  594. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  595. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  596. uint32_t lo = 0;
  597. uint32_t hi = 0;
  598. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  599. (tso_seg->tso_frags[num_frag].length));
  600. qdf_dmaaddr_to_32s(
  601. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  602. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  603. tso_seg->tso_frags[num_frag].length);
  604. }
  605. return;
  606. }
  607. #else
  608. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  609. void *ext_desc)
  610. {
  611. return;
  612. }
  613. #endif
  614. #if defined(FEATURE_TSO)
  615. /**
  616. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  617. * allocated and free them
  618. *
  619. * @soc: soc handle
  620. * @free_seg: list of tso segments
  621. * @msdu_info: msdu descriptor
  622. *
  623. * Return - void
  624. */
  625. static void dp_tx_free_tso_seg_list(
  626. struct dp_soc *soc,
  627. struct qdf_tso_seg_elem_t *free_seg,
  628. struct dp_tx_msdu_info_s *msdu_info)
  629. {
  630. struct qdf_tso_seg_elem_t *next_seg;
  631. while (free_seg) {
  632. next_seg = free_seg->next;
  633. dp_tx_tso_desc_free(soc,
  634. msdu_info->tx_queue.desc_pool_id,
  635. free_seg);
  636. free_seg = next_seg;
  637. }
  638. }
  639. /**
  640. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  641. * allocated and free them
  642. *
  643. * @soc: soc handle
  644. * @free_num_seg: list of tso number segments
  645. * @msdu_info: msdu descriptor
  646. * Return - void
  647. */
  648. static void dp_tx_free_tso_num_seg_list(
  649. struct dp_soc *soc,
  650. struct qdf_tso_num_seg_elem_t *free_num_seg,
  651. struct dp_tx_msdu_info_s *msdu_info)
  652. {
  653. struct qdf_tso_num_seg_elem_t *next_num_seg;
  654. while (free_num_seg) {
  655. next_num_seg = free_num_seg->next;
  656. dp_tso_num_seg_free(soc,
  657. msdu_info->tx_queue.desc_pool_id,
  658. free_num_seg);
  659. free_num_seg = next_num_seg;
  660. }
  661. }
  662. /**
  663. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  664. * do dma unmap for each segment
  665. *
  666. * @soc: soc handle
  667. * @free_seg: list of tso segments
  668. * @num_seg_desc: tso number segment descriptor
  669. *
  670. * Return - void
  671. */
  672. static void dp_tx_unmap_tso_seg_list(
  673. struct dp_soc *soc,
  674. struct qdf_tso_seg_elem_t *free_seg,
  675. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  676. {
  677. struct qdf_tso_seg_elem_t *next_seg;
  678. if (qdf_unlikely(!num_seg_desc)) {
  679. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  680. return;
  681. }
  682. while (free_seg) {
  683. next_seg = free_seg->next;
  684. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  685. free_seg = next_seg;
  686. }
  687. }
  688. #ifdef FEATURE_TSO_STATS
  689. /**
  690. * dp_tso_get_stats_idx: Retrieve the tso packet id
  691. * @pdev - pdev handle
  692. *
  693. * Return: id
  694. */
  695. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  696. {
  697. uint32_t stats_idx;
  698. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  699. % CDP_MAX_TSO_PACKETS);
  700. return stats_idx;
  701. }
  702. #else
  703. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  704. {
  705. return 0;
  706. }
  707. #endif /* FEATURE_TSO_STATS */
  708. /**
  709. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  710. * free the tso segments descriptor and
  711. * tso num segments descriptor
  712. *
  713. * @soc: soc handle
  714. * @msdu_info: msdu descriptor
  715. * @tso_seg_unmap: flag to show if dma unmap is necessary
  716. *
  717. * Return - void
  718. */
  719. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  720. struct dp_tx_msdu_info_s *msdu_info,
  721. bool tso_seg_unmap)
  722. {
  723. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  724. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  725. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  726. tso_info->tso_num_seg_list;
  727. /* do dma unmap for each segment */
  728. if (tso_seg_unmap)
  729. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  730. /* free all tso number segment descriptor though looks only have 1 */
  731. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  732. /* free all tso segment descriptor */
  733. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  734. }
  735. /**
  736. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  737. * @vdev: virtual device handle
  738. * @msdu: network buffer
  739. * @msdu_info: meta data associated with the msdu
  740. *
  741. * Return: QDF_STATUS_SUCCESS success
  742. */
  743. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  744. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  745. {
  746. struct qdf_tso_seg_elem_t *tso_seg;
  747. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  748. struct dp_soc *soc = vdev->pdev->soc;
  749. struct dp_pdev *pdev = vdev->pdev;
  750. struct qdf_tso_info_t *tso_info;
  751. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  752. tso_info = &msdu_info->u.tso_info;
  753. tso_info->curr_seg = NULL;
  754. tso_info->tso_seg_list = NULL;
  755. tso_info->num_segs = num_seg;
  756. msdu_info->frm_type = dp_tx_frm_tso;
  757. tso_info->tso_num_seg_list = NULL;
  758. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  759. while (num_seg) {
  760. tso_seg = dp_tx_tso_desc_alloc(
  761. soc, msdu_info->tx_queue.desc_pool_id);
  762. if (tso_seg) {
  763. tso_seg->next = tso_info->tso_seg_list;
  764. tso_info->tso_seg_list = tso_seg;
  765. num_seg--;
  766. } else {
  767. dp_err_rl("Failed to alloc tso seg desc");
  768. DP_STATS_INC_PKT(vdev->pdev,
  769. tso_stats.tso_no_mem_dropped, 1,
  770. qdf_nbuf_len(msdu));
  771. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  772. return QDF_STATUS_E_NOMEM;
  773. }
  774. }
  775. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  776. tso_num_seg = dp_tso_num_seg_alloc(soc,
  777. msdu_info->tx_queue.desc_pool_id);
  778. if (tso_num_seg) {
  779. tso_num_seg->next = tso_info->tso_num_seg_list;
  780. tso_info->tso_num_seg_list = tso_num_seg;
  781. } else {
  782. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  783. __func__);
  784. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  785. return QDF_STATUS_E_NOMEM;
  786. }
  787. msdu_info->num_seg =
  788. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  789. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  790. msdu_info->num_seg);
  791. if (!(msdu_info->num_seg)) {
  792. /*
  793. * Free allocated TSO seg desc and number seg desc,
  794. * do unmap for segments if dma map has done.
  795. */
  796. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  797. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  798. return QDF_STATUS_E_INVAL;
  799. }
  800. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  801. msdu, 0, DP_TX_DESC_MAP);
  802. tso_info->curr_seg = tso_info->tso_seg_list;
  803. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  804. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  805. msdu, msdu_info->num_seg);
  806. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  807. tso_info->msdu_stats_idx);
  808. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  809. return QDF_STATUS_SUCCESS;
  810. }
  811. #else
  812. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  813. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  814. {
  815. return QDF_STATUS_E_NOMEM;
  816. }
  817. #endif
  818. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  819. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  820. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  821. /**
  822. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  823. * @vdev: DP Vdev handle
  824. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  825. * @desc_pool_id: Descriptor Pool ID
  826. *
  827. * Return:
  828. */
  829. static
  830. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  831. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  832. {
  833. uint8_t i;
  834. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  835. struct dp_tx_seg_info_s *seg_info;
  836. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  837. struct dp_soc *soc = vdev->pdev->soc;
  838. /* Allocate an extension descriptor */
  839. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  840. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  841. if (!msdu_ext_desc) {
  842. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  843. return NULL;
  844. }
  845. if (msdu_info->exception_fw &&
  846. qdf_unlikely(vdev->mesh_vdev)) {
  847. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  848. &msdu_info->meta_data[0],
  849. sizeof(struct htt_tx_msdu_desc_ext2_t));
  850. qdf_atomic_inc(&soc->num_tx_exception);
  851. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  852. }
  853. switch (msdu_info->frm_type) {
  854. case dp_tx_frm_sg:
  855. case dp_tx_frm_me:
  856. case dp_tx_frm_raw:
  857. seg_info = msdu_info->u.sg_info.curr_seg;
  858. /* Update the buffer pointers in MSDU Extension Descriptor */
  859. for (i = 0; i < seg_info->frag_cnt; i++) {
  860. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  861. seg_info->frags[i].paddr_lo,
  862. seg_info->frags[i].paddr_hi,
  863. seg_info->frags[i].len);
  864. }
  865. break;
  866. case dp_tx_frm_tso:
  867. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  868. &cached_ext_desc[0]);
  869. break;
  870. default:
  871. break;
  872. }
  873. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  874. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  875. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  876. msdu_ext_desc->vaddr);
  877. return msdu_ext_desc;
  878. }
  879. /**
  880. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  881. *
  882. * @skb: skb to be traced
  883. * @msdu_id: msdu_id of the packet
  884. * @vdev_id: vdev_id of the packet
  885. *
  886. * Return: None
  887. */
  888. #ifdef DP_DISABLE_TX_PKT_TRACE
  889. static void dp_tx_trace_pkt(struct dp_soc *soc,
  890. qdf_nbuf_t skb, uint16_t msdu_id,
  891. uint8_t vdev_id)
  892. {
  893. }
  894. #else
  895. static void dp_tx_trace_pkt(struct dp_soc *soc,
  896. qdf_nbuf_t skb, uint16_t msdu_id,
  897. uint8_t vdev_id)
  898. {
  899. if (dp_is_tput_high(soc))
  900. return;
  901. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  902. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  903. DPTRACE(qdf_dp_trace_ptr(skb,
  904. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  905. QDF_TRACE_DEFAULT_PDEV_ID,
  906. qdf_nbuf_data_addr(skb),
  907. sizeof(qdf_nbuf_data(skb)),
  908. msdu_id, vdev_id, 0));
  909. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  910. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  911. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  912. msdu_id, QDF_TX));
  913. }
  914. #endif
  915. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  916. /**
  917. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  918. * exception by the upper layer (OS_IF)
  919. * @soc: DP soc handle
  920. * @nbuf: packet to be transmitted
  921. *
  922. * Returns: 1 if the packet is marked as exception,
  923. * 0, if the packet is not marked as exception.
  924. */
  925. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  926. qdf_nbuf_t nbuf)
  927. {
  928. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  929. }
  930. #else
  931. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  932. qdf_nbuf_t nbuf)
  933. {
  934. return 0;
  935. }
  936. #endif
  937. /**
  938. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  939. * @vdev: DP vdev handle
  940. * @nbuf: skb
  941. * @desc_pool_id: Descriptor pool ID
  942. * @meta_data: Metadata to the fw
  943. * @tx_exc_metadata: Handle that holds exception path metadata
  944. * Allocate and prepare Tx descriptor with msdu information.
  945. *
  946. * Return: Pointer to Tx Descriptor on success,
  947. * NULL on failure
  948. */
  949. static
  950. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  951. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  952. struct dp_tx_msdu_info_s *msdu_info,
  953. struct cdp_tx_exception_metadata *tx_exc_metadata)
  954. {
  955. uint8_t align_pad;
  956. uint8_t is_exception = 0;
  957. uint8_t htt_hdr_size;
  958. struct dp_tx_desc_s *tx_desc;
  959. struct dp_pdev *pdev = vdev->pdev;
  960. struct dp_soc *soc = pdev->soc;
  961. if (dp_tx_limit_check(vdev))
  962. return NULL;
  963. /* Allocate software Tx descriptor */
  964. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  965. if (qdf_unlikely(!tx_desc)) {
  966. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  967. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  968. return NULL;
  969. }
  970. dp_tx_outstanding_inc(pdev);
  971. /* Initialize the SW tx descriptor */
  972. tx_desc->nbuf = nbuf;
  973. tx_desc->frm_type = dp_tx_frm_std;
  974. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  975. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  976. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  977. tx_desc->vdev_id = vdev->vdev_id;
  978. tx_desc->pdev = pdev;
  979. tx_desc->msdu_ext_desc = NULL;
  980. tx_desc->pkt_offset = 0;
  981. tx_desc->length = qdf_nbuf_headlen(nbuf);
  982. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  983. if (qdf_unlikely(vdev->multipass_en)) {
  984. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  985. goto failure;
  986. }
  987. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  988. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  989. is_exception = 1;
  990. /*
  991. * For special modes (vdev_type == ocb or mesh), data frames should be
  992. * transmitted using varying transmit parameters (tx spec) which include
  993. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  994. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  995. * These frames are sent as exception packets to firmware.
  996. *
  997. * HW requirement is that metadata should always point to a
  998. * 8-byte aligned address. So we add alignment pad to start of buffer.
  999. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1000. * to get 8-byte aligned start address along with align_pad added
  1001. *
  1002. * |-----------------------------|
  1003. * | |
  1004. * |-----------------------------| <-----Buffer Pointer Address given
  1005. * | | ^ in HW descriptor (aligned)
  1006. * | HTT Metadata | |
  1007. * | | |
  1008. * | | | Packet Offset given in descriptor
  1009. * | | |
  1010. * |-----------------------------| |
  1011. * | Alignment Pad | v
  1012. * |-----------------------------| <----- Actual buffer start address
  1013. * | SKB Data | (Unaligned)
  1014. * | |
  1015. * | |
  1016. * | |
  1017. * | |
  1018. * | |
  1019. * |-----------------------------|
  1020. */
  1021. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1022. (vdev->opmode == wlan_op_mode_ocb) ||
  1023. (tx_exc_metadata &&
  1024. tx_exc_metadata->is_tx_sniffer)) {
  1025. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1026. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1027. DP_STATS_INC(vdev,
  1028. tx_i.dropped.headroom_insufficient, 1);
  1029. goto failure;
  1030. }
  1031. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1032. dp_tx_err("qdf_nbuf_push_head failed");
  1033. goto failure;
  1034. }
  1035. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1036. msdu_info);
  1037. if (htt_hdr_size == 0)
  1038. goto failure;
  1039. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1040. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1041. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1042. is_exception = 1;
  1043. tx_desc->length -= tx_desc->pkt_offset;
  1044. }
  1045. #if !TQM_BYPASS_WAR
  1046. if (is_exception || tx_exc_metadata)
  1047. #endif
  1048. {
  1049. /* Temporary WAR due to TQM VP issues */
  1050. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1051. qdf_atomic_inc(&soc->num_tx_exception);
  1052. }
  1053. return tx_desc;
  1054. failure:
  1055. dp_tx_desc_release(tx_desc, desc_pool_id);
  1056. return NULL;
  1057. }
  1058. /**
  1059. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1060. * @vdev: DP vdev handle
  1061. * @nbuf: skb
  1062. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1063. * @desc_pool_id : Descriptor Pool ID
  1064. *
  1065. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1066. * information. For frames wth fragments, allocate and prepare
  1067. * an MSDU extension descriptor
  1068. *
  1069. * Return: Pointer to Tx Descriptor on success,
  1070. * NULL on failure
  1071. */
  1072. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1073. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1074. uint8_t desc_pool_id)
  1075. {
  1076. struct dp_tx_desc_s *tx_desc;
  1077. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1078. struct dp_pdev *pdev = vdev->pdev;
  1079. struct dp_soc *soc = pdev->soc;
  1080. if (dp_tx_limit_check(vdev))
  1081. return NULL;
  1082. /* Allocate software Tx descriptor */
  1083. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1084. if (!tx_desc) {
  1085. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1086. return NULL;
  1087. }
  1088. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1089. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1090. dp_tx_outstanding_inc(pdev);
  1091. /* Initialize the SW tx descriptor */
  1092. tx_desc->nbuf = nbuf;
  1093. tx_desc->frm_type = msdu_info->frm_type;
  1094. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1095. tx_desc->vdev_id = vdev->vdev_id;
  1096. tx_desc->pdev = pdev;
  1097. tx_desc->pkt_offset = 0;
  1098. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1099. /* Handle scattered frames - TSO/SG/ME */
  1100. /* Allocate and prepare an extension descriptor for scattered frames */
  1101. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1102. if (!msdu_ext_desc) {
  1103. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1104. goto failure;
  1105. }
  1106. #if TQM_BYPASS_WAR
  1107. /* Temporary WAR due to TQM VP issues */
  1108. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1109. qdf_atomic_inc(&soc->num_tx_exception);
  1110. #endif
  1111. if (qdf_unlikely(msdu_info->exception_fw))
  1112. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1113. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1114. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1115. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1116. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1117. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1118. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1119. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1120. else
  1121. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1122. return tx_desc;
  1123. failure:
  1124. dp_tx_desc_release(tx_desc, desc_pool_id);
  1125. return NULL;
  1126. }
  1127. /**
  1128. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1129. * @vdev: DP vdev handle
  1130. * @nbuf: buffer pointer
  1131. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1132. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1133. * descriptor
  1134. *
  1135. * Return:
  1136. */
  1137. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1138. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1139. {
  1140. qdf_nbuf_t curr_nbuf = NULL;
  1141. uint16_t total_len = 0;
  1142. qdf_dma_addr_t paddr;
  1143. int32_t i;
  1144. int32_t mapped_buf_num = 0;
  1145. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1146. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1147. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1148. /* Continue only if frames are of DATA type */
  1149. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1150. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1151. dp_tx_debug("Pkt. recd is of not data type");
  1152. goto error;
  1153. }
  1154. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1155. if (vdev->raw_mode_war &&
  1156. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1157. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1158. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1159. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1160. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1161. /*
  1162. * Number of nbuf's must not exceed the size of the frags
  1163. * array in seg_info.
  1164. */
  1165. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1166. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1167. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1168. goto error;
  1169. }
  1170. if (QDF_STATUS_SUCCESS !=
  1171. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1172. curr_nbuf,
  1173. QDF_DMA_TO_DEVICE,
  1174. curr_nbuf->len)) {
  1175. dp_tx_err("%s dma map error ", __func__);
  1176. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1177. goto error;
  1178. }
  1179. /* Update the count of mapped nbuf's */
  1180. mapped_buf_num++;
  1181. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1182. seg_info->frags[i].paddr_lo = paddr;
  1183. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1184. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1185. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1186. total_len += qdf_nbuf_len(curr_nbuf);
  1187. }
  1188. seg_info->frag_cnt = i;
  1189. seg_info->total_len = total_len;
  1190. seg_info->next = NULL;
  1191. sg_info->curr_seg = seg_info;
  1192. msdu_info->frm_type = dp_tx_frm_raw;
  1193. msdu_info->num_seg = 1;
  1194. return nbuf;
  1195. error:
  1196. i = 0;
  1197. while (nbuf) {
  1198. curr_nbuf = nbuf;
  1199. if (i < mapped_buf_num) {
  1200. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1201. QDF_DMA_TO_DEVICE,
  1202. curr_nbuf->len);
  1203. i++;
  1204. }
  1205. nbuf = qdf_nbuf_next(nbuf);
  1206. qdf_nbuf_free(curr_nbuf);
  1207. }
  1208. return NULL;
  1209. }
  1210. /**
  1211. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1212. * @soc: DP soc handle
  1213. * @nbuf: Buffer pointer
  1214. *
  1215. * unmap the chain of nbufs that belong to this RAW frame.
  1216. *
  1217. * Return: None
  1218. */
  1219. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1220. qdf_nbuf_t nbuf)
  1221. {
  1222. qdf_nbuf_t cur_nbuf = nbuf;
  1223. do {
  1224. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1225. QDF_DMA_TO_DEVICE,
  1226. cur_nbuf->len);
  1227. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1228. } while (cur_nbuf);
  1229. }
  1230. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1231. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1232. qdf_nbuf_t nbuf)
  1233. {
  1234. qdf_nbuf_t nbuf_local;
  1235. struct dp_vdev *vdev_local = vdev_hdl;
  1236. do {
  1237. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1238. break;
  1239. nbuf_local = nbuf;
  1240. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1241. htt_cmn_pkt_type_raw))
  1242. break;
  1243. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1244. break;
  1245. else if (qdf_nbuf_is_tso((nbuf_local)))
  1246. break;
  1247. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1248. (nbuf_local),
  1249. NULL, 1, 0);
  1250. } while (0);
  1251. }
  1252. #endif
  1253. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1254. /**
  1255. * dp_tx_update_stats() - Update soc level tx stats
  1256. * @soc: DP soc handle
  1257. * @nbuf: packet being transmitted
  1258. *
  1259. * Returns: none
  1260. */
  1261. void dp_tx_update_stats(struct dp_soc *soc,
  1262. qdf_nbuf_t nbuf)
  1263. {
  1264. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1265. }
  1266. int
  1267. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1268. struct dp_tx_desc_s *tx_desc,
  1269. uint8_t tid)
  1270. {
  1271. struct dp_swlm *swlm = &soc->swlm;
  1272. union swlm_data swlm_query_data;
  1273. struct dp_swlm_tcl_data tcl_data;
  1274. QDF_STATUS status;
  1275. int ret;
  1276. if (qdf_unlikely(!swlm->is_enabled))
  1277. return 0;
  1278. tcl_data.nbuf = tx_desc->nbuf;
  1279. tcl_data.tid = tid;
  1280. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1281. swlm_query_data.tcl_data = &tcl_data;
  1282. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1283. if (QDF_IS_STATUS_ERROR(status)) {
  1284. dp_swlm_tcl_reset_session_data(soc);
  1285. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1286. return 0;
  1287. }
  1288. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1289. if (ret) {
  1290. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1291. } else {
  1292. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1293. }
  1294. return ret;
  1295. }
  1296. void
  1297. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1298. int coalesce)
  1299. {
  1300. if (coalesce)
  1301. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1302. else
  1303. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1304. }
  1305. #endif
  1306. #ifdef FEATURE_RUNTIME_PM
  1307. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1308. {
  1309. return qdf_atomic_read(&soc->rtpm_high_tput_flag);
  1310. }
  1311. /**
  1312. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1313. * @soc: Datapath soc handle
  1314. * @hal_ring_hdl: HAL ring handle
  1315. * @coalesce: Coalesce the current write or not
  1316. *
  1317. * Wrapper for HAL ring access end for data transmission for
  1318. * FEATURE_RUNTIME_PM
  1319. *
  1320. * Returns: none
  1321. */
  1322. void
  1323. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1324. hal_ring_handle_t hal_ring_hdl,
  1325. int coalesce)
  1326. {
  1327. int ret;
  1328. /*
  1329. * Avoid runtime get and put APIs under high throughput scenarios.
  1330. */
  1331. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1332. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1333. return;
  1334. }
  1335. ret = hif_pm_runtime_get(soc->hif_handle,
  1336. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1337. switch (ret) {
  1338. case 0:
  1339. if (hif_system_pm_state_check(soc->hif_handle)) {
  1340. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1341. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1342. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1343. } else {
  1344. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1345. }
  1346. hif_pm_runtime_put(soc->hif_handle,
  1347. RTPM_ID_DW_TX_HW_ENQUEUE);
  1348. break;
  1349. /*
  1350. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1351. * take the dp runtime refcount using dp_runtime_get,
  1352. * check link state,if up, write TX ring HP, else just set flush event.
  1353. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1354. * zero or time out, then flush pending tx.
  1355. */
  1356. case -EBUSY:
  1357. case -EINPROGRESS:
  1358. dp_runtime_get(soc);
  1359. if (hif_pm_get_link_state(soc->hif_handle) ==
  1360. HIF_PM_LINK_STATE_UP) {
  1361. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1362. } else {
  1363. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1364. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1365. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1366. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1367. }
  1368. dp_runtime_put(soc);
  1369. break;
  1370. default:
  1371. dp_runtime_get(soc);
  1372. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1373. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1374. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1375. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1376. dp_runtime_put(soc);
  1377. }
  1378. }
  1379. #else
  1380. #ifdef DP_POWER_SAVE
  1381. void
  1382. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1383. hal_ring_handle_t hal_ring_hdl,
  1384. int coalesce)
  1385. {
  1386. if (hif_system_pm_state_check(soc->hif_handle)) {
  1387. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1388. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1389. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1390. } else {
  1391. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1392. }
  1393. }
  1394. #endif
  1395. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1396. {
  1397. return 0;
  1398. }
  1399. #endif
  1400. /**
  1401. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1402. * @vdev: DP vdev handle
  1403. * @nbuf: skb
  1404. *
  1405. * Extract the DSCP or PCP information from frame and map into TID value.
  1406. *
  1407. * Return: void
  1408. */
  1409. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1410. struct dp_tx_msdu_info_s *msdu_info)
  1411. {
  1412. uint8_t tos = 0, dscp_tid_override = 0;
  1413. uint8_t *hdr_ptr, *L3datap;
  1414. uint8_t is_mcast = 0;
  1415. qdf_ether_header_t *eh = NULL;
  1416. qdf_ethervlan_header_t *evh = NULL;
  1417. uint16_t ether_type;
  1418. qdf_llc_t *llcHdr;
  1419. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1420. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1421. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1422. eh = (qdf_ether_header_t *)nbuf->data;
  1423. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1424. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1425. } else {
  1426. qdf_dot3_qosframe_t *qos_wh =
  1427. (qdf_dot3_qosframe_t *) nbuf->data;
  1428. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1429. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1430. return;
  1431. }
  1432. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1433. ether_type = eh->ether_type;
  1434. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1435. /*
  1436. * Check if packet is dot3 or eth2 type.
  1437. */
  1438. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1439. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1440. sizeof(*llcHdr));
  1441. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1442. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1443. sizeof(*llcHdr);
  1444. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1445. + sizeof(*llcHdr) +
  1446. sizeof(qdf_net_vlanhdr_t));
  1447. } else {
  1448. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1449. sizeof(*llcHdr);
  1450. }
  1451. } else {
  1452. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1453. evh = (qdf_ethervlan_header_t *) eh;
  1454. ether_type = evh->ether_type;
  1455. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1456. }
  1457. }
  1458. /*
  1459. * Find priority from IP TOS DSCP field
  1460. */
  1461. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1462. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1463. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1464. /* Only for unicast frames */
  1465. if (!is_mcast) {
  1466. /* send it on VO queue */
  1467. msdu_info->tid = DP_VO_TID;
  1468. }
  1469. } else {
  1470. /*
  1471. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1472. * from TOS byte.
  1473. */
  1474. tos = ip->ip_tos;
  1475. dscp_tid_override = 1;
  1476. }
  1477. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1478. /* TODO
  1479. * use flowlabel
  1480. *igmpmld cases to be handled in phase 2
  1481. */
  1482. unsigned long ver_pri_flowlabel;
  1483. unsigned long pri;
  1484. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1485. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1486. DP_IPV6_PRIORITY_SHIFT;
  1487. tos = pri;
  1488. dscp_tid_override = 1;
  1489. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1490. msdu_info->tid = DP_VO_TID;
  1491. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1492. /* Only for unicast frames */
  1493. if (!is_mcast) {
  1494. /* send ucast arp on VO queue */
  1495. msdu_info->tid = DP_VO_TID;
  1496. }
  1497. }
  1498. /*
  1499. * Assign all MCAST packets to BE
  1500. */
  1501. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1502. if (is_mcast) {
  1503. tos = 0;
  1504. dscp_tid_override = 1;
  1505. }
  1506. }
  1507. if (dscp_tid_override == 1) {
  1508. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1509. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1510. }
  1511. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1512. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1513. return;
  1514. }
  1515. /**
  1516. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1517. * @vdev: DP vdev handle
  1518. * @nbuf: skb
  1519. *
  1520. * Software based TID classification is required when more than 2 DSCP-TID
  1521. * mapping tables are needed.
  1522. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1523. *
  1524. * Return: void
  1525. */
  1526. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1527. struct dp_tx_msdu_info_s *msdu_info)
  1528. {
  1529. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1530. /*
  1531. * skip_sw_tid_classification flag will set in below cases-
  1532. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1533. * 2. hlos_tid_override enabled for vdev
  1534. * 3. mesh mode enabled for vdev
  1535. */
  1536. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1537. /* Update tid in msdu_info from skb priority */
  1538. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1539. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1540. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1541. if (tid == DP_TX_INVALID_QOS_TAG)
  1542. return;
  1543. msdu_info->tid = tid;
  1544. return;
  1545. }
  1546. return;
  1547. }
  1548. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1549. }
  1550. #ifdef FEATURE_WLAN_TDLS
  1551. /**
  1552. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1553. * @soc: datapath SOC
  1554. * @vdev: datapath vdev
  1555. * @tx_desc: TX descriptor
  1556. *
  1557. * Return: None
  1558. */
  1559. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1560. struct dp_vdev *vdev,
  1561. struct dp_tx_desc_s *tx_desc)
  1562. {
  1563. if (vdev) {
  1564. if (vdev->is_tdls_frame) {
  1565. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1566. vdev->is_tdls_frame = false;
  1567. }
  1568. }
  1569. }
  1570. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1571. {
  1572. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1573. switch (soc->arch_id) {
  1574. case CDP_ARCH_TYPE_LI:
  1575. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1576. break;
  1577. case CDP_ARCH_TYPE_BE:
  1578. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1579. break;
  1580. default:
  1581. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1582. QDF_BUG(0);
  1583. }
  1584. return tx_status;
  1585. }
  1586. /**
  1587. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1588. * @soc: dp_soc handle
  1589. * @tx_desc: TX descriptor
  1590. * @vdev: datapath vdev handle
  1591. *
  1592. * Return: None
  1593. */
  1594. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1595. struct dp_tx_desc_s *tx_desc)
  1596. {
  1597. uint8_t tx_status = 0;
  1598. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1599. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1600. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1601. DP_MOD_ID_TDLS);
  1602. if (qdf_unlikely(!vdev)) {
  1603. dp_err_rl("vdev is null!");
  1604. goto error;
  1605. }
  1606. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1607. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1608. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1609. if (vdev->tx_non_std_data_callback.func) {
  1610. qdf_nbuf_set_next(nbuf, NULL);
  1611. vdev->tx_non_std_data_callback.func(
  1612. vdev->tx_non_std_data_callback.ctxt,
  1613. nbuf, tx_status);
  1614. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1615. return;
  1616. } else {
  1617. dp_err_rl("callback func is null");
  1618. }
  1619. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1620. error:
  1621. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1622. qdf_nbuf_free(nbuf);
  1623. }
  1624. /**
  1625. * dp_tx_msdu_single_map() - do nbuf map
  1626. * @vdev: DP vdev handle
  1627. * @tx_desc: DP TX descriptor pointer
  1628. * @nbuf: skb pointer
  1629. *
  1630. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1631. * operation done in other component.
  1632. *
  1633. * Return: QDF_STATUS
  1634. */
  1635. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1636. struct dp_tx_desc_s *tx_desc,
  1637. qdf_nbuf_t nbuf)
  1638. {
  1639. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1640. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1641. nbuf,
  1642. QDF_DMA_TO_DEVICE,
  1643. nbuf->len);
  1644. else
  1645. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1646. QDF_DMA_TO_DEVICE);
  1647. }
  1648. #else
  1649. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1650. struct dp_vdev *vdev,
  1651. struct dp_tx_desc_s *tx_desc)
  1652. {
  1653. }
  1654. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1655. struct dp_tx_desc_s *tx_desc)
  1656. {
  1657. }
  1658. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1659. struct dp_tx_desc_s *tx_desc,
  1660. qdf_nbuf_t nbuf)
  1661. {
  1662. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1663. nbuf,
  1664. QDF_DMA_TO_DEVICE,
  1665. nbuf->len);
  1666. }
  1667. #endif
  1668. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1669. static inline
  1670. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1671. struct dp_tx_desc_s *tx_desc,
  1672. qdf_nbuf_t nbuf)
  1673. {
  1674. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1675. (void *)(nbuf->data + nbuf->len));
  1676. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1677. }
  1678. static inline
  1679. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1680. struct dp_tx_desc_s *desc)
  1681. {
  1682. }
  1683. #else
  1684. static inline
  1685. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1686. struct dp_tx_desc_s *tx_desc,
  1687. qdf_nbuf_t nbuf)
  1688. {
  1689. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1690. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1691. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1692. return 0;
  1693. return qdf_nbuf_mapped_paddr_get(nbuf);
  1694. }
  1695. static inline
  1696. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1697. struct dp_tx_desc_s *desc)
  1698. {
  1699. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1700. desc->nbuf,
  1701. desc->dma_addr,
  1702. QDF_DMA_TO_DEVICE,
  1703. desc->length);
  1704. }
  1705. #endif
  1706. #ifdef MESH_MODE_SUPPORT
  1707. /**
  1708. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1709. * @soc: datapath SOC
  1710. * @vdev: datapath vdev
  1711. * @tx_desc: TX descriptor
  1712. *
  1713. * Return: None
  1714. */
  1715. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1716. struct dp_vdev *vdev,
  1717. struct dp_tx_desc_s *tx_desc)
  1718. {
  1719. if (qdf_unlikely(vdev->mesh_vdev))
  1720. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1721. }
  1722. /**
  1723. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1724. * @soc: dp_soc handle
  1725. * @tx_desc: TX descriptor
  1726. * @vdev: datapath vdev handle
  1727. *
  1728. * Return: None
  1729. */
  1730. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1731. struct dp_tx_desc_s *tx_desc)
  1732. {
  1733. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1734. struct dp_vdev *vdev = NULL;
  1735. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1736. qdf_nbuf_free(nbuf);
  1737. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1738. } else {
  1739. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1740. DP_MOD_ID_MESH);
  1741. if (vdev && vdev->osif_tx_free_ext)
  1742. vdev->osif_tx_free_ext((nbuf));
  1743. else
  1744. qdf_nbuf_free(nbuf);
  1745. if (vdev)
  1746. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1747. }
  1748. }
  1749. #else
  1750. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1751. struct dp_vdev *vdev,
  1752. struct dp_tx_desc_s *tx_desc)
  1753. {
  1754. }
  1755. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1756. struct dp_tx_desc_s *tx_desc)
  1757. {
  1758. }
  1759. #endif
  1760. /**
  1761. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1762. * @vdev: DP vdev handle
  1763. * @nbuf: skb
  1764. *
  1765. * Return: 1 if frame needs to be dropped else 0
  1766. */
  1767. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1768. {
  1769. struct dp_pdev *pdev = NULL;
  1770. struct dp_ast_entry *src_ast_entry = NULL;
  1771. struct dp_ast_entry *dst_ast_entry = NULL;
  1772. struct dp_soc *soc = NULL;
  1773. qdf_assert(vdev);
  1774. pdev = vdev->pdev;
  1775. qdf_assert(pdev);
  1776. soc = pdev->soc;
  1777. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1778. (soc, dstmac, vdev->pdev->pdev_id);
  1779. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1780. (soc, srcmac, vdev->pdev->pdev_id);
  1781. if (dst_ast_entry && src_ast_entry) {
  1782. if (dst_ast_entry->peer_id ==
  1783. src_ast_entry->peer_id)
  1784. return 1;
  1785. }
  1786. return 0;
  1787. }
  1788. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1789. defined(WLAN_MCAST_MLO)
  1790. /* MLO peer id for reinject*/
  1791. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1792. /* MLO vdev id inc offset */
  1793. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1794. static inline void
  1795. dp_tx_update_mcast_param(uint16_t peer_id,
  1796. uint16_t *htt_tcl_metadata,
  1797. struct dp_vdev *vdev,
  1798. struct dp_tx_msdu_info_s *msdu_info)
  1799. {
  1800. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1801. *htt_tcl_metadata = 0;
  1802. DP_TX_TCL_METADATA_TYPE_SET(
  1803. *htt_tcl_metadata,
  1804. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1805. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1806. msdu_info->gsn);
  1807. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1808. } else {
  1809. msdu_info->vdev_id = vdev->vdev_id;
  1810. }
  1811. }
  1812. #else
  1813. static inline void
  1814. dp_tx_update_mcast_param(uint16_t peer_id,
  1815. uint16_t *htt_tcl_metadata,
  1816. struct dp_vdev *vdev,
  1817. struct dp_tx_msdu_info_s *msdu_info)
  1818. {
  1819. }
  1820. #endif
  1821. /**
  1822. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1823. * @vdev: DP vdev handle
  1824. * @nbuf: skb
  1825. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1826. * @meta_data: Metadata to the fw
  1827. * @tx_q: Tx queue to be used for this Tx frame
  1828. * @peer_id: peer_id of the peer in case of NAWDS frames
  1829. * @tx_exc_metadata: Handle that holds exception path metadata
  1830. *
  1831. * Return: NULL on success,
  1832. * nbuf when it fails to send
  1833. */
  1834. qdf_nbuf_t
  1835. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1836. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1837. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1838. {
  1839. struct dp_pdev *pdev = vdev->pdev;
  1840. struct dp_soc *soc = pdev->soc;
  1841. struct dp_tx_desc_s *tx_desc;
  1842. QDF_STATUS status;
  1843. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1844. uint16_t htt_tcl_metadata = 0;
  1845. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1846. uint8_t tid = msdu_info->tid;
  1847. struct cdp_tid_tx_stats *tid_stats = NULL;
  1848. qdf_dma_addr_t paddr;
  1849. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1850. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1851. msdu_info, tx_exc_metadata);
  1852. if (!tx_desc) {
  1853. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1854. vdev, tx_q->desc_pool_id);
  1855. drop_code = TX_DESC_ERR;
  1856. goto fail_return;
  1857. }
  1858. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1859. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1860. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1861. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1862. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1863. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1864. DP_TCL_METADATA_TYPE_PEER_BASED);
  1865. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1866. peer_id);
  1867. } else
  1868. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1869. if (msdu_info->exception_fw)
  1870. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1871. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1872. !pdev->enhanced_stats_en);
  1873. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1874. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  1875. if (!paddr) {
  1876. /* Handle failure */
  1877. dp_err("qdf_nbuf_map failed");
  1878. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1879. drop_code = TX_DMA_MAP_ERR;
  1880. goto release_desc;
  1881. }
  1882. tx_desc->dma_addr = paddr;
  1883. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1884. tx_desc->id, DP_TX_DESC_MAP);
  1885. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  1886. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1887. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1888. htt_tcl_metadata,
  1889. tx_exc_metadata, msdu_info);
  1890. if (status != QDF_STATUS_SUCCESS) {
  1891. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1892. tx_desc, tx_q->ring_id);
  1893. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1894. tx_desc->id, DP_TX_DESC_UNMAP);
  1895. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1896. QDF_DMA_TO_DEVICE,
  1897. nbuf->len);
  1898. drop_code = TX_HW_ENQUEUE;
  1899. goto release_desc;
  1900. }
  1901. return NULL;
  1902. release_desc:
  1903. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1904. fail_return:
  1905. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1906. tid_stats = &pdev->stats.tid_stats.
  1907. tid_tx_stats[tx_q->ring_id][tid];
  1908. tid_stats->swdrop_cnt[drop_code]++;
  1909. return nbuf;
  1910. }
  1911. /**
  1912. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1913. * @soc: Soc handle
  1914. * @desc: software Tx descriptor to be processed
  1915. *
  1916. * Return: none
  1917. */
  1918. void dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1919. {
  1920. qdf_nbuf_t nbuf = desc->nbuf;
  1921. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1922. /* nbuf already freed in vdev detach path */
  1923. if (!nbuf)
  1924. return;
  1925. /* If it is TDLS mgmt, don't unmap or free the frame */
  1926. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1927. return dp_non_std_htt_tx_comp_free_buff(soc, desc);
  1928. /* 0 : MSDU buffer, 1 : MLE */
  1929. if (desc->msdu_ext_desc) {
  1930. /* TSO free */
  1931. if (hal_tx_ext_desc_get_tso_enable(
  1932. desc->msdu_ext_desc->vaddr)) {
  1933. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1934. desc->id, DP_TX_COMP_MSDU_EXT);
  1935. dp_tx_tso_seg_history_add(soc,
  1936. desc->msdu_ext_desc->tso_desc,
  1937. desc->nbuf, desc->id, type);
  1938. /* unmap eash TSO seg before free the nbuf */
  1939. dp_tx_tso_unmap_segment(soc,
  1940. desc->msdu_ext_desc->tso_desc,
  1941. desc->msdu_ext_desc->
  1942. tso_num_desc);
  1943. qdf_nbuf_free(nbuf);
  1944. return;
  1945. }
  1946. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  1947. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  1948. qdf_dma_addr_t iova;
  1949. uint32_t frag_len;
  1950. uint32_t i;
  1951. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  1952. QDF_DMA_TO_DEVICE,
  1953. qdf_nbuf_headlen(nbuf));
  1954. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  1955. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  1956. &iova,
  1957. &frag_len);
  1958. if (!iova || !frag_len)
  1959. break;
  1960. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  1961. QDF_DMA_TO_DEVICE);
  1962. }
  1963. qdf_nbuf_free(nbuf);
  1964. return;
  1965. }
  1966. }
  1967. /* If it's ME frame, dont unmap the cloned nbuf's */
  1968. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1969. goto nbuf_free;
  1970. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  1971. dp_tx_unmap(soc, desc);
  1972. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1973. return dp_mesh_tx_comp_free_buff(soc, desc);
  1974. nbuf_free:
  1975. qdf_nbuf_free(nbuf);
  1976. }
  1977. /**
  1978. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  1979. * @soc: DP soc handle
  1980. * @nbuf: skb
  1981. * @msdu_info: MSDU info
  1982. *
  1983. * Return: None
  1984. */
  1985. static inline void
  1986. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  1987. struct dp_tx_msdu_info_s *msdu_info)
  1988. {
  1989. uint32_t cur_idx;
  1990. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  1991. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  1992. qdf_nbuf_headlen(nbuf));
  1993. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  1994. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  1995. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  1996. seg->frags[cur_idx].paddr_hi) << 32),
  1997. seg->frags[cur_idx].len,
  1998. QDF_DMA_TO_DEVICE);
  1999. }
  2000. /**
  2001. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2002. * @vdev: DP vdev handle
  2003. * @nbuf: skb
  2004. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2005. *
  2006. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2007. *
  2008. * Return: NULL on success,
  2009. * nbuf when it fails to send
  2010. */
  2011. #if QDF_LOCK_STATS
  2012. noinline
  2013. #else
  2014. #endif
  2015. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2016. struct dp_tx_msdu_info_s *msdu_info)
  2017. {
  2018. uint32_t i;
  2019. struct dp_pdev *pdev = vdev->pdev;
  2020. struct dp_soc *soc = pdev->soc;
  2021. struct dp_tx_desc_s *tx_desc;
  2022. bool is_cce_classified = false;
  2023. QDF_STATUS status;
  2024. uint16_t htt_tcl_metadata = 0;
  2025. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2026. struct cdp_tid_tx_stats *tid_stats = NULL;
  2027. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2028. if (msdu_info->frm_type == dp_tx_frm_me)
  2029. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2030. i = 0;
  2031. /* Print statement to track i and num_seg */
  2032. /*
  2033. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2034. * descriptors using information in msdu_info
  2035. */
  2036. while (i < msdu_info->num_seg) {
  2037. /*
  2038. * Setup Tx descriptor for an MSDU, and MSDU extension
  2039. * descriptor
  2040. */
  2041. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2042. tx_q->desc_pool_id);
  2043. if (!tx_desc) {
  2044. if (msdu_info->frm_type == dp_tx_frm_me) {
  2045. prep_desc_fail++;
  2046. dp_tx_me_free_buf(pdev,
  2047. (void *)(msdu_info->u.sg_info
  2048. .curr_seg->frags[0].vaddr));
  2049. if (prep_desc_fail == msdu_info->num_seg) {
  2050. /*
  2051. * Unmap is needed only if descriptor
  2052. * preparation failed for all segments.
  2053. */
  2054. qdf_nbuf_unmap(soc->osdev,
  2055. msdu_info->u.sg_info.
  2056. curr_seg->nbuf,
  2057. QDF_DMA_TO_DEVICE);
  2058. }
  2059. /*
  2060. * Free the nbuf for the current segment
  2061. * and make it point to the next in the list.
  2062. * For me, there are as many segments as there
  2063. * are no of clients.
  2064. */
  2065. qdf_nbuf_free(msdu_info->u.sg_info
  2066. .curr_seg->nbuf);
  2067. if (msdu_info->u.sg_info.curr_seg->next) {
  2068. msdu_info->u.sg_info.curr_seg =
  2069. msdu_info->u.sg_info
  2070. .curr_seg->next;
  2071. nbuf = msdu_info->u.sg_info
  2072. .curr_seg->nbuf;
  2073. }
  2074. i++;
  2075. continue;
  2076. }
  2077. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2078. dp_tx_tso_seg_history_add(
  2079. soc,
  2080. msdu_info->u.tso_info.curr_seg,
  2081. nbuf, 0, DP_TX_DESC_UNMAP);
  2082. dp_tx_tso_unmap_segment(soc,
  2083. msdu_info->u.tso_info.
  2084. curr_seg,
  2085. msdu_info->u.tso_info.
  2086. tso_num_seg_list);
  2087. if (msdu_info->u.tso_info.curr_seg->next) {
  2088. msdu_info->u.tso_info.curr_seg =
  2089. msdu_info->u.tso_info.curr_seg->next;
  2090. i++;
  2091. continue;
  2092. }
  2093. }
  2094. if (msdu_info->frm_type == dp_tx_frm_sg)
  2095. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2096. goto done;
  2097. }
  2098. if (msdu_info->frm_type == dp_tx_frm_me) {
  2099. tx_desc->msdu_ext_desc->me_buffer =
  2100. (struct dp_tx_me_buf_t *)msdu_info->
  2101. u.sg_info.curr_seg->frags[0].vaddr;
  2102. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2103. }
  2104. if (is_cce_classified)
  2105. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2106. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2107. if (msdu_info->exception_fw) {
  2108. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2109. }
  2110. /*
  2111. * For frames with multiple segments (TSO, ME), jump to next
  2112. * segment.
  2113. */
  2114. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2115. if (msdu_info->u.tso_info.curr_seg->next) {
  2116. msdu_info->u.tso_info.curr_seg =
  2117. msdu_info->u.tso_info.curr_seg->next;
  2118. /*
  2119. * If this is a jumbo nbuf, then increment the
  2120. * number of nbuf users for each additional
  2121. * segment of the msdu. This will ensure that
  2122. * the skb is freed only after receiving tx
  2123. * completion for all segments of an nbuf
  2124. */
  2125. qdf_nbuf_inc_users(nbuf);
  2126. /* Check with MCL if this is needed */
  2127. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2128. */
  2129. }
  2130. }
  2131. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2132. &htt_tcl_metadata,
  2133. vdev,
  2134. msdu_info);
  2135. /*
  2136. * Enqueue the Tx MSDU descriptor to HW for transmit
  2137. */
  2138. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2139. htt_tcl_metadata,
  2140. NULL, msdu_info);
  2141. if (status != QDF_STATUS_SUCCESS) {
  2142. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2143. tx_desc, tx_q->ring_id);
  2144. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2145. tid_stats = &pdev->stats.tid_stats.
  2146. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2147. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2148. if (msdu_info->frm_type == dp_tx_frm_me) {
  2149. hw_enq_fail++;
  2150. if (hw_enq_fail == msdu_info->num_seg) {
  2151. /*
  2152. * Unmap is needed only if enqueue
  2153. * failed for all segments.
  2154. */
  2155. qdf_nbuf_unmap(soc->osdev,
  2156. msdu_info->u.sg_info.
  2157. curr_seg->nbuf,
  2158. QDF_DMA_TO_DEVICE);
  2159. }
  2160. /*
  2161. * Free the nbuf for the current segment
  2162. * and make it point to the next in the list.
  2163. * For me, there are as many segments as there
  2164. * are no of clients.
  2165. */
  2166. qdf_nbuf_free(msdu_info->u.sg_info
  2167. .curr_seg->nbuf);
  2168. if (msdu_info->u.sg_info.curr_seg->next) {
  2169. msdu_info->u.sg_info.curr_seg =
  2170. msdu_info->u.sg_info
  2171. .curr_seg->next;
  2172. nbuf = msdu_info->u.sg_info
  2173. .curr_seg->nbuf;
  2174. } else
  2175. break;
  2176. i++;
  2177. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2178. continue;
  2179. }
  2180. /*
  2181. * For TSO frames, the nbuf users increment done for
  2182. * the current segment has to be reverted, since the
  2183. * hw enqueue for this segment failed
  2184. */
  2185. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2186. msdu_info->u.tso_info.curr_seg) {
  2187. /*
  2188. * unmap and free current,
  2189. * retransmit remaining segments
  2190. */
  2191. dp_tx_comp_free_buf(soc, tx_desc);
  2192. i++;
  2193. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2194. continue;
  2195. }
  2196. if (msdu_info->frm_type == dp_tx_frm_sg)
  2197. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2198. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2199. goto done;
  2200. }
  2201. /*
  2202. * TODO
  2203. * if tso_info structure can be modified to have curr_seg
  2204. * as first element, following 2 blocks of code (for TSO and SG)
  2205. * can be combined into 1
  2206. */
  2207. /*
  2208. * For Multicast-Unicast converted packets,
  2209. * each converted frame (for a client) is represented as
  2210. * 1 segment
  2211. */
  2212. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2213. (msdu_info->frm_type == dp_tx_frm_me)) {
  2214. if (msdu_info->u.sg_info.curr_seg->next) {
  2215. msdu_info->u.sg_info.curr_seg =
  2216. msdu_info->u.sg_info.curr_seg->next;
  2217. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2218. } else
  2219. break;
  2220. }
  2221. i++;
  2222. }
  2223. nbuf = NULL;
  2224. done:
  2225. return nbuf;
  2226. }
  2227. /**
  2228. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2229. * for SG frames
  2230. * @vdev: DP vdev handle
  2231. * @nbuf: skb
  2232. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2233. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2234. *
  2235. * Return: NULL on success,
  2236. * nbuf when it fails to send
  2237. */
  2238. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2239. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2240. {
  2241. uint32_t cur_frag, nr_frags, i;
  2242. qdf_dma_addr_t paddr;
  2243. struct dp_tx_sg_info_s *sg_info;
  2244. sg_info = &msdu_info->u.sg_info;
  2245. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2246. if (QDF_STATUS_SUCCESS !=
  2247. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2248. QDF_DMA_TO_DEVICE,
  2249. qdf_nbuf_headlen(nbuf))) {
  2250. dp_tx_err("dma map error");
  2251. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2252. qdf_nbuf_free(nbuf);
  2253. return NULL;
  2254. }
  2255. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2256. seg_info->frags[0].paddr_lo = paddr;
  2257. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2258. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2259. seg_info->frags[0].vaddr = (void *) nbuf;
  2260. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2261. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2262. nbuf, 0,
  2263. QDF_DMA_TO_DEVICE,
  2264. cur_frag)) {
  2265. dp_tx_err("frag dma map error");
  2266. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2267. goto map_err;
  2268. }
  2269. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2270. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2271. seg_info->frags[cur_frag + 1].paddr_hi =
  2272. ((uint64_t) paddr) >> 32;
  2273. seg_info->frags[cur_frag + 1].len =
  2274. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2275. }
  2276. seg_info->frag_cnt = (cur_frag + 1);
  2277. seg_info->total_len = qdf_nbuf_len(nbuf);
  2278. seg_info->next = NULL;
  2279. sg_info->curr_seg = seg_info;
  2280. msdu_info->frm_type = dp_tx_frm_sg;
  2281. msdu_info->num_seg = 1;
  2282. return nbuf;
  2283. map_err:
  2284. /* restore paddr into nbuf before calling unmap */
  2285. qdf_nbuf_mapped_paddr_set(nbuf,
  2286. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2287. ((uint64_t)
  2288. seg_info->frags[0].paddr_hi) << 32));
  2289. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2290. QDF_DMA_TO_DEVICE,
  2291. seg_info->frags[0].len);
  2292. for (i = 1; i <= cur_frag; i++) {
  2293. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2294. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2295. seg_info->frags[i].paddr_hi) << 32),
  2296. seg_info->frags[i].len,
  2297. QDF_DMA_TO_DEVICE);
  2298. }
  2299. qdf_nbuf_free(nbuf);
  2300. return NULL;
  2301. }
  2302. /**
  2303. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2304. * @vdev: DP vdev handle
  2305. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2306. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2307. *
  2308. * Return: NULL on failure,
  2309. * nbuf when extracted successfully
  2310. */
  2311. static
  2312. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2313. struct dp_tx_msdu_info_s *msdu_info,
  2314. uint16_t ppdu_cookie)
  2315. {
  2316. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2317. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2318. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2319. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2320. (msdu_info->meta_data[5], 1);
  2321. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2322. (msdu_info->meta_data[5], 1);
  2323. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2324. (msdu_info->meta_data[6], ppdu_cookie);
  2325. msdu_info->exception_fw = 1;
  2326. msdu_info->is_tx_sniffer = 1;
  2327. }
  2328. #ifdef MESH_MODE_SUPPORT
  2329. /**
  2330. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2331. and prepare msdu_info for mesh frames.
  2332. * @vdev: DP vdev handle
  2333. * @nbuf: skb
  2334. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2335. *
  2336. * Return: NULL on failure,
  2337. * nbuf when extracted successfully
  2338. */
  2339. static
  2340. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2341. struct dp_tx_msdu_info_s *msdu_info)
  2342. {
  2343. struct meta_hdr_s *mhdr;
  2344. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2345. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2346. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2347. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2348. msdu_info->exception_fw = 0;
  2349. goto remove_meta_hdr;
  2350. }
  2351. msdu_info->exception_fw = 1;
  2352. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2353. meta_data->host_tx_desc_pool = 1;
  2354. meta_data->update_peer_cache = 1;
  2355. meta_data->learning_frame = 1;
  2356. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2357. meta_data->power = mhdr->power;
  2358. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2359. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2360. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2361. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2362. meta_data->dyn_bw = 1;
  2363. meta_data->valid_pwr = 1;
  2364. meta_data->valid_mcs_mask = 1;
  2365. meta_data->valid_nss_mask = 1;
  2366. meta_data->valid_preamble_type = 1;
  2367. meta_data->valid_retries = 1;
  2368. meta_data->valid_bw_info = 1;
  2369. }
  2370. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2371. meta_data->encrypt_type = 0;
  2372. meta_data->valid_encrypt_type = 1;
  2373. meta_data->learning_frame = 0;
  2374. }
  2375. meta_data->valid_key_flags = 1;
  2376. meta_data->key_flags = (mhdr->keyix & 0x3);
  2377. remove_meta_hdr:
  2378. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2379. dp_tx_err("qdf_nbuf_pull_head failed");
  2380. qdf_nbuf_free(nbuf);
  2381. return NULL;
  2382. }
  2383. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2384. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2385. " tid %d to_fw %d",
  2386. msdu_info->meta_data[0],
  2387. msdu_info->meta_data[1],
  2388. msdu_info->meta_data[2],
  2389. msdu_info->meta_data[3],
  2390. msdu_info->meta_data[4],
  2391. msdu_info->meta_data[5],
  2392. msdu_info->tid, msdu_info->exception_fw);
  2393. return nbuf;
  2394. }
  2395. #else
  2396. static
  2397. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2398. struct dp_tx_msdu_info_s *msdu_info)
  2399. {
  2400. return nbuf;
  2401. }
  2402. #endif
  2403. /**
  2404. * dp_check_exc_metadata() - Checks if parameters are valid
  2405. * @tx_exc - holds all exception path parameters
  2406. *
  2407. * Returns true when all the parameters are valid else false
  2408. *
  2409. */
  2410. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2411. {
  2412. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2413. HTT_INVALID_TID);
  2414. bool invalid_encap_type =
  2415. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2416. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2417. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2418. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2419. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2420. tx_exc->ppdu_cookie == 0);
  2421. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2422. invalid_cookie) {
  2423. return false;
  2424. }
  2425. return true;
  2426. }
  2427. #ifdef ATH_SUPPORT_IQUE
  2428. /**
  2429. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2430. * @vdev: vdev handle
  2431. * @nbuf: skb
  2432. *
  2433. * Return: true on success,
  2434. * false on failure
  2435. */
  2436. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2437. {
  2438. qdf_ether_header_t *eh;
  2439. /* Mcast to Ucast Conversion*/
  2440. if (qdf_likely(!vdev->mcast_enhancement_en))
  2441. return true;
  2442. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2443. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2444. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2445. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2446. qdf_nbuf_set_next(nbuf, NULL);
  2447. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2448. qdf_nbuf_len(nbuf));
  2449. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2450. QDF_STATUS_SUCCESS) {
  2451. return false;
  2452. }
  2453. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2454. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2455. QDF_STATUS_SUCCESS) {
  2456. return false;
  2457. }
  2458. }
  2459. }
  2460. return true;
  2461. }
  2462. #else
  2463. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2464. {
  2465. return true;
  2466. }
  2467. #endif
  2468. /**
  2469. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2470. * @nbuf: qdf_nbuf_t
  2471. * @vdev: struct dp_vdev *
  2472. *
  2473. * Allow packet for processing only if it is for peer client which is
  2474. * connected with same vap. Drop packet if client is connected to
  2475. * different vap.
  2476. *
  2477. * Return: QDF_STATUS
  2478. */
  2479. static inline QDF_STATUS
  2480. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2481. {
  2482. struct dp_ast_entry *dst_ast_entry = NULL;
  2483. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2484. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2485. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2486. return QDF_STATUS_SUCCESS;
  2487. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2488. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2489. eh->ether_dhost,
  2490. vdev->vdev_id);
  2491. /* If there is no ast entry, return failure */
  2492. if (qdf_unlikely(!dst_ast_entry)) {
  2493. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2494. return QDF_STATUS_E_FAILURE;
  2495. }
  2496. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2497. return QDF_STATUS_SUCCESS;
  2498. }
  2499. /**
  2500. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2501. * @soc: DP soc handle
  2502. * @vdev_id: id of DP vdev handle
  2503. * @nbuf: skb
  2504. * @tx_exc_metadata: Handle that holds exception path meta data
  2505. *
  2506. * Entry point for Core Tx layer (DP_TX) invoked from
  2507. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2508. *
  2509. * Return: NULL on success,
  2510. * nbuf when it fails to send
  2511. */
  2512. qdf_nbuf_t
  2513. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2514. qdf_nbuf_t nbuf,
  2515. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2516. {
  2517. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2518. qdf_ether_header_t *eh = NULL;
  2519. struct dp_tx_msdu_info_s msdu_info;
  2520. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2521. DP_MOD_ID_TX_EXCEPTION);
  2522. if (qdf_unlikely(!vdev))
  2523. goto fail;
  2524. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2525. if (!tx_exc_metadata)
  2526. goto fail;
  2527. msdu_info.tid = tx_exc_metadata->tid;
  2528. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2529. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2530. QDF_MAC_ADDR_REF(nbuf->data));
  2531. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2532. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2533. dp_tx_err("Invalid parameters in exception path");
  2534. goto fail;
  2535. }
  2536. /* Basic sanity checks for unsupported packets */
  2537. /* MESH mode */
  2538. if (qdf_unlikely(vdev->mesh_vdev)) {
  2539. dp_tx_err("Mesh mode is not supported in exception path");
  2540. goto fail;
  2541. }
  2542. /*
  2543. * Classify the frame and call corresponding
  2544. * "prepare" function which extracts the segment (TSO)
  2545. * and fragmentation information (for TSO , SG, ME, or Raw)
  2546. * into MSDU_INFO structure which is later used to fill
  2547. * SW and HW descriptors.
  2548. */
  2549. if (qdf_nbuf_is_tso(nbuf)) {
  2550. dp_verbose_debug("TSO frame %pK", vdev);
  2551. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2552. qdf_nbuf_len(nbuf));
  2553. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2554. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2555. qdf_nbuf_len(nbuf));
  2556. goto fail;
  2557. }
  2558. goto send_multiple;
  2559. }
  2560. /* SG */
  2561. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2562. struct dp_tx_seg_info_s seg_info = {0};
  2563. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2564. if (!nbuf)
  2565. goto fail;
  2566. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2567. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2568. qdf_nbuf_len(nbuf));
  2569. goto send_multiple;
  2570. }
  2571. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2572. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2573. qdf_nbuf_len(nbuf));
  2574. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2575. tx_exc_metadata->ppdu_cookie);
  2576. }
  2577. /*
  2578. * Get HW Queue to use for this frame.
  2579. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2580. * dedicated for data and 1 for command.
  2581. * "queue_id" maps to one hardware ring.
  2582. * With each ring, we also associate a unique Tx descriptor pool
  2583. * to minimize lock contention for these resources.
  2584. */
  2585. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2586. /*
  2587. * Check exception descriptors
  2588. */
  2589. if (dp_tx_exception_limit_check(vdev))
  2590. goto fail;
  2591. /* Single linear frame */
  2592. /*
  2593. * If nbuf is a simple linear frame, use send_single function to
  2594. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2595. * SRNG. There is no need to setup a MSDU extension descriptor.
  2596. */
  2597. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2598. tx_exc_metadata->peer_id, tx_exc_metadata);
  2599. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2600. return nbuf;
  2601. send_multiple:
  2602. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2603. fail:
  2604. if (vdev)
  2605. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2606. dp_verbose_debug("pkt send failed");
  2607. return nbuf;
  2608. }
  2609. /**
  2610. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2611. * in exception path in special case to avoid regular exception path chk.
  2612. * @soc: DP soc handle
  2613. * @vdev_id: id of DP vdev handle
  2614. * @nbuf: skb
  2615. * @tx_exc_metadata: Handle that holds exception path meta data
  2616. *
  2617. * Entry point for Core Tx layer (DP_TX) invoked from
  2618. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2619. *
  2620. * Return: NULL on success,
  2621. * nbuf when it fails to send
  2622. */
  2623. qdf_nbuf_t
  2624. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2625. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2626. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2627. {
  2628. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2629. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2630. DP_MOD_ID_TX_EXCEPTION);
  2631. if (qdf_unlikely(!vdev))
  2632. goto fail;
  2633. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2634. == QDF_STATUS_E_FAILURE)) {
  2635. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2636. goto fail;
  2637. }
  2638. /* Unref count as it will agin be taken inside dp_tx_exception */
  2639. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2640. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2641. fail:
  2642. if (vdev)
  2643. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2644. dp_verbose_debug("pkt send failed");
  2645. return nbuf;
  2646. }
  2647. /**
  2648. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2649. * @soc: DP soc handle
  2650. * @vdev_id: DP vdev handle
  2651. * @nbuf: skb
  2652. *
  2653. * Entry point for Core Tx layer (DP_TX) invoked from
  2654. * hard_start_xmit in OSIF/HDD
  2655. *
  2656. * Return: NULL on success,
  2657. * nbuf when it fails to send
  2658. */
  2659. #ifdef MESH_MODE_SUPPORT
  2660. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2661. qdf_nbuf_t nbuf)
  2662. {
  2663. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2664. struct meta_hdr_s *mhdr;
  2665. qdf_nbuf_t nbuf_mesh = NULL;
  2666. qdf_nbuf_t nbuf_clone = NULL;
  2667. struct dp_vdev *vdev;
  2668. uint8_t no_enc_frame = 0;
  2669. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2670. if (!nbuf_mesh) {
  2671. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2672. "qdf_nbuf_unshare failed");
  2673. return nbuf;
  2674. }
  2675. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2676. if (!vdev) {
  2677. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2678. "vdev is NULL for vdev_id %d", vdev_id);
  2679. return nbuf;
  2680. }
  2681. nbuf = nbuf_mesh;
  2682. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2683. if ((vdev->sec_type != cdp_sec_type_none) &&
  2684. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2685. no_enc_frame = 1;
  2686. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2687. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2688. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2689. !no_enc_frame) {
  2690. nbuf_clone = qdf_nbuf_clone(nbuf);
  2691. if (!nbuf_clone) {
  2692. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2693. "qdf_nbuf_clone failed");
  2694. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2695. return nbuf;
  2696. }
  2697. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2698. }
  2699. if (nbuf_clone) {
  2700. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2701. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2702. } else {
  2703. qdf_nbuf_free(nbuf_clone);
  2704. }
  2705. }
  2706. if (no_enc_frame)
  2707. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2708. else
  2709. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2710. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2711. if ((!nbuf) && no_enc_frame) {
  2712. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2713. }
  2714. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2715. return nbuf;
  2716. }
  2717. #else
  2718. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2719. qdf_nbuf_t nbuf)
  2720. {
  2721. return dp_tx_send(soc, vdev_id, nbuf);
  2722. }
  2723. #endif
  2724. /**
  2725. * dp_tx_nawds_handler() - NAWDS handler
  2726. *
  2727. * @soc: DP soc handle
  2728. * @vdev_id: id of DP vdev handle
  2729. * @msdu_info: msdu_info required to create HTT metadata
  2730. * @nbuf: skb
  2731. *
  2732. * This API transfers the multicast frames with the peer id
  2733. * on NAWDS enabled peer.
  2734. * Return: none
  2735. */
  2736. static inline
  2737. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2738. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2739. {
  2740. struct dp_peer *peer = NULL;
  2741. qdf_nbuf_t nbuf_clone = NULL;
  2742. uint16_t peer_id = DP_INVALID_PEER;
  2743. uint16_t sa_peer_id = DP_INVALID_PEER;
  2744. struct dp_ast_entry *ast_entry = NULL;
  2745. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2746. struct dp_txrx_peer *txrx_peer;
  2747. if (!soc->ast_offload_support) {
  2748. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2749. qdf_spin_lock_bh(&soc->ast_lock);
  2750. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2751. (soc,
  2752. (uint8_t *)(eh->ether_shost),
  2753. vdev->pdev->pdev_id);
  2754. if (ast_entry)
  2755. sa_peer_id = ast_entry->peer_id;
  2756. qdf_spin_unlock_bh(&soc->ast_lock);
  2757. }
  2758. } else {
  2759. if ((qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) &&
  2760. qdf_nbuf_get_tx_fctx(nbuf))
  2761. sa_peer_id = *(uint32_t *)qdf_nbuf_get_tx_fctx(nbuf);
  2762. }
  2763. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2764. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2765. txrx_peer = dp_get_txrx_peer(peer);
  2766. if (!txrx_peer)
  2767. continue;
  2768. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2769. peer_id = peer->peer_id;
  2770. /* Multicast packets needs to be
  2771. * dropped in case of intra bss forwarding
  2772. */
  2773. if (sa_peer_id == peer->peer_id) {
  2774. dp_tx_debug("multicast packet");
  2775. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2776. tx.nawds_mcast_drop,
  2777. 1);
  2778. continue;
  2779. }
  2780. nbuf_clone = qdf_nbuf_clone(nbuf);
  2781. if (!nbuf_clone) {
  2782. QDF_TRACE(QDF_MODULE_ID_DP,
  2783. QDF_TRACE_LEVEL_ERROR,
  2784. FL("nbuf clone failed"));
  2785. break;
  2786. }
  2787. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2788. msdu_info, peer_id,
  2789. NULL);
  2790. if (nbuf_clone) {
  2791. dp_tx_debug("pkt send failed");
  2792. qdf_nbuf_free(nbuf_clone);
  2793. } else {
  2794. if (peer_id != DP_INVALID_PEER) {
  2795. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2796. tx.nawds_mcast,
  2797. 1, qdf_nbuf_len(nbuf));
  2798. }
  2799. }
  2800. }
  2801. }
  2802. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2803. }
  2804. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  2805. static inline
  2806. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2807. {
  2808. if (nbuf) {
  2809. qdf_prefetch(&nbuf->len);
  2810. qdf_prefetch(&nbuf->data);
  2811. }
  2812. }
  2813. #else
  2814. static inline
  2815. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2816. {
  2817. }
  2818. #endif
  2819. /**
  2820. * dp_tx_send() - Transmit a frame on a given VAP
  2821. * @soc: DP soc handle
  2822. * @vdev_id: id of DP vdev handle
  2823. * @nbuf: skb
  2824. *
  2825. * Entry point for Core Tx layer (DP_TX) invoked from
  2826. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2827. * cases
  2828. *
  2829. * Return: NULL on success,
  2830. * nbuf when it fails to send
  2831. */
  2832. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2833. qdf_nbuf_t nbuf)
  2834. {
  2835. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2836. uint16_t peer_id = HTT_INVALID_PEER;
  2837. /*
  2838. * doing a memzero is causing additional function call overhead
  2839. * so doing static stack clearing
  2840. */
  2841. struct dp_tx_msdu_info_s msdu_info = {0};
  2842. struct dp_vdev *vdev = NULL;
  2843. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2844. return nbuf;
  2845. /*
  2846. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2847. * this in per packet path.
  2848. *
  2849. * As in this path vdev memory is already protected with netdev
  2850. * tx lock
  2851. */
  2852. vdev = soc->vdev_id_map[vdev_id];
  2853. if (qdf_unlikely(!vdev))
  2854. return nbuf;
  2855. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2856. QDF_MAC_ADDR_REF(nbuf->data));
  2857. /*
  2858. * Set Default Host TID value to invalid TID
  2859. * (TID override disabled)
  2860. */
  2861. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2862. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2863. if (qdf_unlikely(vdev->mesh_vdev)) {
  2864. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2865. &msdu_info);
  2866. if (!nbuf_mesh) {
  2867. dp_verbose_debug("Extracting mesh metadata failed");
  2868. return nbuf;
  2869. }
  2870. nbuf = nbuf_mesh;
  2871. }
  2872. /*
  2873. * Get HW Queue to use for this frame.
  2874. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2875. * dedicated for data and 1 for command.
  2876. * "queue_id" maps to one hardware ring.
  2877. * With each ring, we also associate a unique Tx descriptor pool
  2878. * to minimize lock contention for these resources.
  2879. */
  2880. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2881. /*
  2882. * TCL H/W supports 2 DSCP-TID mapping tables.
  2883. * Table 1 - Default DSCP-TID mapping table
  2884. * Table 2 - 1 DSCP-TID override table
  2885. *
  2886. * If we need a different DSCP-TID mapping for this vap,
  2887. * call tid_classify to extract DSCP/ToS from frame and
  2888. * map to a TID and store in msdu_info. This is later used
  2889. * to fill in TCL Input descriptor (per-packet TID override).
  2890. */
  2891. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2892. /*
  2893. * Classify the frame and call corresponding
  2894. * "prepare" function which extracts the segment (TSO)
  2895. * and fragmentation information (for TSO , SG, ME, or Raw)
  2896. * into MSDU_INFO structure which is later used to fill
  2897. * SW and HW descriptors.
  2898. */
  2899. if (qdf_nbuf_is_tso(nbuf)) {
  2900. dp_verbose_debug("TSO frame %pK", vdev);
  2901. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2902. qdf_nbuf_len(nbuf));
  2903. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2904. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2905. qdf_nbuf_len(nbuf));
  2906. return nbuf;
  2907. }
  2908. goto send_multiple;
  2909. }
  2910. /* SG */
  2911. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2912. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  2913. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  2914. return nbuf;
  2915. } else {
  2916. struct dp_tx_seg_info_s seg_info = {0};
  2917. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  2918. &msdu_info);
  2919. if (!nbuf)
  2920. return NULL;
  2921. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2922. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2923. qdf_nbuf_len(nbuf));
  2924. goto send_multiple;
  2925. }
  2926. }
  2927. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2928. return NULL;
  2929. /* RAW */
  2930. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2931. struct dp_tx_seg_info_s seg_info = {0};
  2932. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2933. if (!nbuf)
  2934. return NULL;
  2935. dp_verbose_debug("Raw frame %pK", vdev);
  2936. goto send_multiple;
  2937. }
  2938. if (qdf_unlikely(vdev->nawds_enabled)) {
  2939. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2940. qdf_nbuf_data(nbuf);
  2941. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2942. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2943. peer_id = DP_INVALID_PEER;
  2944. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2945. 1, qdf_nbuf_len(nbuf));
  2946. }
  2947. /* Single linear frame */
  2948. /*
  2949. * If nbuf is a simple linear frame, use send_single function to
  2950. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2951. * SRNG. There is no need to setup a MSDU extension descriptor.
  2952. */
  2953. dp_tx_prefetch_nbuf_data(nbuf);
  2954. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2955. return nbuf;
  2956. send_multiple:
  2957. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2958. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2959. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2960. return nbuf;
  2961. }
  2962. /**
  2963. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2964. * case to vaoid check in perpkt path.
  2965. * @soc: DP soc handle
  2966. * @vdev_id: id of DP vdev handle
  2967. * @nbuf: skb
  2968. *
  2969. * Entry point for Core Tx layer (DP_TX) invoked from
  2970. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2971. * with special condition to avoid per pkt check in dp_tx_send
  2972. *
  2973. * Return: NULL on success,
  2974. * nbuf when it fails to send
  2975. */
  2976. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2977. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2978. {
  2979. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2980. struct dp_vdev *vdev = NULL;
  2981. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2982. return nbuf;
  2983. /*
  2984. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2985. * this in per packet path.
  2986. *
  2987. * As in this path vdev memory is already protected with netdev
  2988. * tx lock
  2989. */
  2990. vdev = soc->vdev_id_map[vdev_id];
  2991. if (qdf_unlikely(!vdev))
  2992. return nbuf;
  2993. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2994. == QDF_STATUS_E_FAILURE)) {
  2995. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2996. return nbuf;
  2997. }
  2998. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2999. }
  3000. #ifdef UMAC_SUPPORT_PROXY_ARP
  3001. /**
  3002. * dp_tx_proxy_arp() - Tx proxy arp handler
  3003. * @vdev: datapath vdev handle
  3004. * @buf: sk buffer
  3005. *
  3006. * Return: status
  3007. */
  3008. static inline
  3009. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3010. {
  3011. if (vdev->osif_proxy_arp)
  3012. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3013. /*
  3014. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3015. * osif_proxy_arp has a valid function pointer assigned
  3016. * to it
  3017. */
  3018. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3019. return QDF_STATUS_NOT_INITIALIZED;
  3020. }
  3021. #else
  3022. /**
  3023. * dp_tx_proxy_arp() - Tx proxy arp handler
  3024. * @vdev: datapath vdev handle
  3025. * @buf: sk buffer
  3026. *
  3027. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3028. * is not defined.
  3029. *
  3030. * Return: status
  3031. */
  3032. static inline
  3033. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3034. {
  3035. return QDF_STATUS_SUCCESS;
  3036. }
  3037. #endif
  3038. /**
  3039. * dp_tx_reinject_handler() - Tx Reinject Handler
  3040. * @soc: datapath soc handle
  3041. * @vdev: datapath vdev handle
  3042. * @tx_desc: software descriptor head pointer
  3043. * @status : Tx completion status from HTT descriptor
  3044. * @reinject_reason : reinject reason from HTT descriptor
  3045. *
  3046. * This function reinjects frames back to Target.
  3047. * Todo - Host queue needs to be added
  3048. *
  3049. * Return: none
  3050. */
  3051. void dp_tx_reinject_handler(struct dp_soc *soc,
  3052. struct dp_vdev *vdev,
  3053. struct dp_tx_desc_s *tx_desc,
  3054. uint8_t *status,
  3055. uint8_t reinject_reason)
  3056. {
  3057. struct dp_peer *peer = NULL;
  3058. uint32_t peer_id = HTT_INVALID_PEER;
  3059. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3060. qdf_nbuf_t nbuf_copy = NULL;
  3061. struct dp_tx_msdu_info_s msdu_info;
  3062. #ifdef WDS_VENDOR_EXTENSION
  3063. int is_mcast = 0, is_ucast = 0;
  3064. int num_peers_3addr = 0;
  3065. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3066. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3067. #endif
  3068. struct dp_txrx_peer *txrx_peer;
  3069. qdf_assert(vdev);
  3070. dp_tx_debug("Tx reinject path");
  3071. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3072. qdf_nbuf_len(tx_desc->nbuf));
  3073. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3074. #ifdef WLAN_MCAST_MLO
  3075. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3076. if (soc->arch_ops.dp_tx_mcast_handler)
  3077. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3078. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3079. return;
  3080. }
  3081. #endif
  3082. #endif
  3083. #ifdef WDS_VENDOR_EXTENSION
  3084. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3085. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3086. } else {
  3087. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3088. }
  3089. is_ucast = !is_mcast;
  3090. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3091. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3092. txrx_peer = dp_get_txrx_peer(peer);
  3093. if (!txrx_peer || txrx_peer->bss_peer)
  3094. continue;
  3095. /* Detect wds peers that use 3-addr framing for mcast.
  3096. * if there are any, the bss_peer is used to send the
  3097. * the mcast frame using 3-addr format. all wds enabled
  3098. * peers that use 4-addr framing for mcast frames will
  3099. * be duplicated and sent as 4-addr frames below.
  3100. */
  3101. if (!txrx_peer->wds_enabled ||
  3102. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3103. num_peers_3addr = 1;
  3104. break;
  3105. }
  3106. }
  3107. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3108. #endif
  3109. if (qdf_unlikely(vdev->mesh_vdev)) {
  3110. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3111. } else {
  3112. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3113. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3114. txrx_peer = dp_get_txrx_peer(peer);
  3115. if (!txrx_peer)
  3116. continue;
  3117. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3118. #ifdef WDS_VENDOR_EXTENSION
  3119. /*
  3120. * . if 3-addr STA, then send on BSS Peer
  3121. * . if Peer WDS enabled and accept 4-addr mcast,
  3122. * send mcast on that peer only
  3123. * . if Peer WDS enabled and accept 4-addr ucast,
  3124. * send ucast on that peer only
  3125. */
  3126. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3127. (txrx_peer->wds_enabled &&
  3128. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3129. (is_ucast &&
  3130. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3131. #else
  3132. (txrx_peer->bss_peer &&
  3133. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3134. #endif
  3135. peer_id = DP_INVALID_PEER;
  3136. nbuf_copy = qdf_nbuf_copy(nbuf);
  3137. if (!nbuf_copy) {
  3138. dp_tx_debug("nbuf copy failed");
  3139. break;
  3140. }
  3141. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3142. dp_tx_get_queue(vdev, nbuf,
  3143. &msdu_info.tx_queue);
  3144. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3145. nbuf_copy,
  3146. &msdu_info,
  3147. peer_id,
  3148. NULL);
  3149. if (nbuf_copy) {
  3150. dp_tx_debug("pkt send failed");
  3151. qdf_nbuf_free(nbuf_copy);
  3152. }
  3153. }
  3154. }
  3155. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3156. }
  3157. qdf_nbuf_free(nbuf);
  3158. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3159. }
  3160. /**
  3161. * dp_tx_inspect_handler() - Tx Inspect Handler
  3162. * @soc: datapath soc handle
  3163. * @vdev: datapath vdev handle
  3164. * @tx_desc: software descriptor head pointer
  3165. * @status : Tx completion status from HTT descriptor
  3166. *
  3167. * Handles Tx frames sent back to Host for inspection
  3168. * (ProxyARP)
  3169. *
  3170. * Return: none
  3171. */
  3172. void dp_tx_inspect_handler(struct dp_soc *soc,
  3173. struct dp_vdev *vdev,
  3174. struct dp_tx_desc_s *tx_desc,
  3175. uint8_t *status)
  3176. {
  3177. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3178. "%s Tx inspect path",
  3179. __func__);
  3180. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3181. qdf_nbuf_len(tx_desc->nbuf));
  3182. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3183. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3184. }
  3185. #ifdef MESH_MODE_SUPPORT
  3186. /**
  3187. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3188. * in mesh meta header
  3189. * @tx_desc: software descriptor head pointer
  3190. * @ts: pointer to tx completion stats
  3191. * Return: none
  3192. */
  3193. static
  3194. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3195. struct hal_tx_completion_status *ts)
  3196. {
  3197. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3198. if (!tx_desc->msdu_ext_desc) {
  3199. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3200. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3201. "netbuf %pK offset %d",
  3202. netbuf, tx_desc->pkt_offset);
  3203. return;
  3204. }
  3205. }
  3206. }
  3207. #else
  3208. static
  3209. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3210. struct hal_tx_completion_status *ts)
  3211. {
  3212. }
  3213. #endif
  3214. #ifdef CONFIG_SAWF
  3215. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3216. struct dp_vdev *vdev,
  3217. struct dp_txrx_peer *txrx_peer,
  3218. struct dp_tx_desc_s *tx_desc,
  3219. struct hal_tx_completion_status *ts,
  3220. uint8_t tid)
  3221. {
  3222. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3223. ts, tid);
  3224. }
  3225. #else
  3226. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3227. struct dp_vdev *vdev,
  3228. struct dp_txrx_peer *txrx_peer,
  3229. struct dp_tx_desc_s *tx_desc,
  3230. struct hal_tx_completion_status *ts,
  3231. uint8_t tid)
  3232. {
  3233. }
  3234. #endif
  3235. #ifdef QCA_PEER_EXT_STATS
  3236. /*
  3237. * dp_tx_compute_tid_delay() - Compute per TID delay
  3238. * @stats: Per TID delay stats
  3239. * @tx_desc: Software Tx descriptor
  3240. *
  3241. * Compute the software enqueue and hw enqueue delays and
  3242. * update the respective histograms
  3243. *
  3244. * Return: void
  3245. */
  3246. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3247. struct dp_tx_desc_s *tx_desc)
  3248. {
  3249. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3250. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3251. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3252. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3253. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3254. timestamp_hw_enqueue = tx_desc->timestamp;
  3255. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3256. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3257. timestamp_hw_enqueue);
  3258. /*
  3259. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3260. */
  3261. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3262. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3263. }
  3264. /*
  3265. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3266. * @txrx_peer: DP peer context
  3267. * @tx_desc: Tx software descriptor
  3268. * @tid: Transmission ID
  3269. * @ring_id: Rx CPU context ID/CPU_ID
  3270. *
  3271. * Update the peer extended stats. These are enhanced other
  3272. * delay stats per msdu level.
  3273. *
  3274. * Return: void
  3275. */
  3276. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3277. struct dp_tx_desc_s *tx_desc,
  3278. uint8_t tid, uint8_t ring_id)
  3279. {
  3280. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3281. struct dp_soc *soc = NULL;
  3282. struct dp_peer_delay_stats *delay_stats = NULL;
  3283. soc = pdev->soc;
  3284. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3285. return;
  3286. delay_stats = txrx_peer->delay_stats;
  3287. qdf_assert(delay_stats);
  3288. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3289. /*
  3290. * For non-TID packets use the TID 9
  3291. */
  3292. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3293. tid = CDP_MAX_DATA_TIDS - 1;
  3294. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3295. tx_desc);
  3296. }
  3297. #else
  3298. static inline void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3299. struct dp_tx_desc_s *tx_desc,
  3300. uint8_t tid, uint8_t ring_id)
  3301. {
  3302. }
  3303. #endif
  3304. /**
  3305. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3306. * to pass in correct fields
  3307. *
  3308. * @vdev: pdev handle
  3309. * @tx_desc: tx descriptor
  3310. * @tid: tid value
  3311. * @ring_id: TCL or WBM ring number for transmit path
  3312. * Return: none
  3313. */
  3314. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3315. uint8_t tid, uint8_t ring_id)
  3316. {
  3317. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3318. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3319. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3320. return;
  3321. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3322. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3323. timestamp_hw_enqueue = tx_desc->timestamp;
  3324. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3325. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3326. timestamp_hw_enqueue);
  3327. interframe_delay = (uint32_t)(timestamp_ingress -
  3328. vdev->prev_tx_enq_tstamp);
  3329. /*
  3330. * Delay in software enqueue
  3331. */
  3332. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3333. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3334. /*
  3335. * Delay between packet enqueued to HW and Tx completion
  3336. */
  3337. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3338. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3339. /*
  3340. * Update interframe delay stats calculated at hardstart receive point.
  3341. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3342. * interframe delay will not be calculate correctly for 1st frame.
  3343. * On the other side, this will help in avoiding extra per packet check
  3344. * of !vdev->prev_tx_enq_tstamp.
  3345. */
  3346. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3347. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3348. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3349. }
  3350. #ifdef DISABLE_DP_STATS
  3351. static
  3352. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3353. struct dp_txrx_peer *txrx_peer)
  3354. {
  3355. }
  3356. #else
  3357. static inline void
  3358. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3359. {
  3360. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3361. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3362. if (subtype != QDF_PROTO_INVALID)
  3363. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3364. 1);
  3365. }
  3366. #endif
  3367. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3368. /**
  3369. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3370. *
  3371. * @ts: Tx compltion status
  3372. * @txrx_peer: datapath txrx_peer handle
  3373. *
  3374. * Return: void
  3375. */
  3376. static inline void
  3377. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3378. struct dp_txrx_peer *txrx_peer)
  3379. {
  3380. uint8_t mcs, pkt_type;
  3381. mcs = ts->mcs;
  3382. pkt_type = ts->pkt_type;
  3383. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3384. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3385. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3386. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3387. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3388. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3389. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3390. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3391. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3392. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3393. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3394. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3395. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3396. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3397. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3398. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3399. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3400. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3401. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3402. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3403. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3404. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3405. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3406. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3407. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3408. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3409. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3410. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3411. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3412. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3413. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3414. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3415. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3416. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3417. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3418. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3419. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3420. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3421. if (ts->first_msdu) {
  3422. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3423. ts->transmit_cnt > 1);
  3424. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3425. qdf_do_div(ts->transmit_cnt, DP_RETRY_COUNT),
  3426. ts->transmit_cnt > DP_RETRY_COUNT);
  3427. }
  3428. }
  3429. #else
  3430. static inline void
  3431. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3432. struct dp_txrx_peer *txrx_peer)
  3433. {
  3434. }
  3435. #endif
  3436. /**
  3437. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3438. * per wbm ring
  3439. *
  3440. * @tx_desc: software descriptor head pointer
  3441. * @ts: Tx completion status
  3442. * @peer: peer handle
  3443. * @ring_id: ring number
  3444. *
  3445. * Return: None
  3446. */
  3447. static inline void
  3448. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3449. struct hal_tx_completion_status *ts,
  3450. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3451. {
  3452. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3453. uint8_t tid = ts->tid;
  3454. uint32_t length;
  3455. struct cdp_tid_tx_stats *tid_stats;
  3456. if (!pdev)
  3457. return;
  3458. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3459. tid = CDP_MAX_DATA_TIDS - 1;
  3460. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3461. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3462. dp_err("Release source is not from TQM");
  3463. return;
  3464. }
  3465. length = qdf_nbuf_len(tx_desc->nbuf);
  3466. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3467. if (qdf_unlikely(pdev->delay_stats_flag))
  3468. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  3469. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3470. tid_stats->tqm_status_cnt[ts->status]++;
  3471. }
  3472. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  3473. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  3474. ts->transmit_cnt > 1);
  3475. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  3476. 1, ts->transmit_cnt > 2);
  3477. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  3478. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  3479. ts->msdu_part_of_amsdu);
  3480. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  3481. !ts->msdu_part_of_amsdu);
  3482. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  3483. qdf_system_ticks();
  3484. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  3485. return;
  3486. }
  3487. /*
  3488. * tx_failed is ideally supposed to be updated from HTT ppdu
  3489. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  3490. * hw limitation there are no completions for failed cases.
  3491. * Hence updating tx_failed from data path. Please note that
  3492. * if tx_failed is fixed to be from ppdu, then this has to be
  3493. * removed
  3494. */
  3495. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  3496. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  3497. ts->transmit_cnt > DP_RETRY_COUNT);
  3498. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  3499. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  3500. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  3501. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  3502. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  3503. length);
  3504. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  3505. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  3506. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  3507. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  3508. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  3509. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  3510. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  3511. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  3512. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  3513. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  3514. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  3515. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3516. tx.dropped.fw_rem_queue_disable, 1);
  3517. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  3518. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3519. tx.dropped.fw_rem_no_match, 1);
  3520. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  3521. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3522. tx.dropped.drop_threshold, 1);
  3523. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  3524. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3525. tx.dropped.drop_link_desc_na, 1);
  3526. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  3527. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3528. tx.dropped.invalid_drop, 1);
  3529. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  3530. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3531. tx.dropped.mcast_vdev_drop, 1);
  3532. } else {
  3533. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  3534. }
  3535. }
  3536. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3537. /**
  3538. * dp_tx_flow_pool_lock() - take flow pool lock
  3539. * @soc: core txrx main context
  3540. * @tx_desc: tx desc
  3541. *
  3542. * Return: None
  3543. */
  3544. static inline
  3545. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3546. struct dp_tx_desc_s *tx_desc)
  3547. {
  3548. struct dp_tx_desc_pool_s *pool;
  3549. uint8_t desc_pool_id;
  3550. desc_pool_id = tx_desc->pool_id;
  3551. pool = &soc->tx_desc[desc_pool_id];
  3552. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3553. }
  3554. /**
  3555. * dp_tx_flow_pool_unlock() - release flow pool lock
  3556. * @soc: core txrx main context
  3557. * @tx_desc: tx desc
  3558. *
  3559. * Return: None
  3560. */
  3561. static inline
  3562. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3563. struct dp_tx_desc_s *tx_desc)
  3564. {
  3565. struct dp_tx_desc_pool_s *pool;
  3566. uint8_t desc_pool_id;
  3567. desc_pool_id = tx_desc->pool_id;
  3568. pool = &soc->tx_desc[desc_pool_id];
  3569. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3570. }
  3571. #else
  3572. static inline
  3573. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3574. {
  3575. }
  3576. static inline
  3577. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3578. {
  3579. }
  3580. #endif
  3581. /**
  3582. * dp_tx_notify_completion() - Notify tx completion for this desc
  3583. * @soc: core txrx main context
  3584. * @vdev: datapath vdev handle
  3585. * @tx_desc: tx desc
  3586. * @netbuf: buffer
  3587. * @status: tx status
  3588. *
  3589. * Return: none
  3590. */
  3591. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3592. struct dp_vdev *vdev,
  3593. struct dp_tx_desc_s *tx_desc,
  3594. qdf_nbuf_t netbuf,
  3595. uint8_t status)
  3596. {
  3597. void *osif_dev;
  3598. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3599. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3600. qdf_assert(tx_desc);
  3601. dp_tx_flow_pool_lock(soc, tx_desc);
  3602. if (!vdev ||
  3603. !vdev->osif_vdev) {
  3604. dp_tx_flow_pool_unlock(soc, tx_desc);
  3605. return;
  3606. }
  3607. osif_dev = vdev->osif_vdev;
  3608. tx_compl_cbk = vdev->tx_comp;
  3609. dp_tx_flow_pool_unlock(soc, tx_desc);
  3610. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3611. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3612. if (tx_compl_cbk)
  3613. tx_compl_cbk(netbuf, osif_dev, flag);
  3614. }
  3615. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3616. * @pdev: pdev handle
  3617. * @tid: tid value
  3618. * @txdesc_ts: timestamp from txdesc
  3619. * @ppdu_id: ppdu id
  3620. *
  3621. * Return: none
  3622. */
  3623. #ifdef FEATURE_PERPKT_INFO
  3624. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3625. struct dp_txrx_peer *txrx_peer,
  3626. uint8_t tid,
  3627. uint64_t txdesc_ts,
  3628. uint32_t ppdu_id)
  3629. {
  3630. uint64_t delta_ms;
  3631. struct cdp_tx_sojourn_stats *sojourn_stats;
  3632. struct dp_peer *primary_link_peer = NULL;
  3633. struct dp_soc *link_peer_soc = NULL;
  3634. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3635. return;
  3636. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3637. tid >= CDP_DATA_TID_MAX))
  3638. return;
  3639. if (qdf_unlikely(!pdev->sojourn_buf))
  3640. return;
  3641. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  3642. txrx_peer->peer_id,
  3643. DP_MOD_ID_TX_COMP);
  3644. if (qdf_unlikely(!primary_link_peer))
  3645. return;
  3646. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3647. qdf_nbuf_data(pdev->sojourn_buf);
  3648. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  3649. sojourn_stats->cookie = (void *)
  3650. dp_monitor_peer_get_rdkstats_ctx(link_peer_soc,
  3651. primary_link_peer);
  3652. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3653. txdesc_ts;
  3654. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  3655. delta_ms);
  3656. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3657. sojourn_stats->num_msdus[tid] = 1;
  3658. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3659. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  3660. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3661. pdev->sojourn_buf, HTT_INVALID_PEER,
  3662. WDI_NO_VAL, pdev->pdev_id);
  3663. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3664. sojourn_stats->num_msdus[tid] = 0;
  3665. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3666. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  3667. }
  3668. #else
  3669. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3670. struct dp_txrx_peer *txrx_peer,
  3671. uint8_t tid,
  3672. uint64_t txdesc_ts,
  3673. uint32_t ppdu_id)
  3674. {
  3675. }
  3676. #endif
  3677. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3678. /**
  3679. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3680. * @soc: dp_soc handle
  3681. * @desc: Tx Descriptor
  3682. * @ts: HAL Tx completion descriptor contents
  3683. *
  3684. * This function is used to send tx completion to packet capture
  3685. */
  3686. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3687. struct dp_tx_desc_s *desc,
  3688. struct hal_tx_completion_status *ts)
  3689. {
  3690. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3691. desc, ts->peer_id,
  3692. WDI_NO_VAL, desc->pdev->pdev_id);
  3693. }
  3694. #endif
  3695. /**
  3696. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3697. * @soc: DP Soc handle
  3698. * @tx_desc: software Tx descriptor
  3699. * @ts : Tx completion status from HAL/HTT descriptor
  3700. *
  3701. * Return: none
  3702. */
  3703. void
  3704. dp_tx_comp_process_desc(struct dp_soc *soc,
  3705. struct dp_tx_desc_s *desc,
  3706. struct hal_tx_completion_status *ts,
  3707. struct dp_txrx_peer *txrx_peer)
  3708. {
  3709. uint64_t time_latency = 0;
  3710. uint16_t peer_id = DP_INVALID_PEER_ID;
  3711. /*
  3712. * m_copy/tx_capture modes are not supported for
  3713. * scatter gather packets
  3714. */
  3715. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3716. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3717. desc->timestamp);
  3718. }
  3719. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3720. if (dp_tx_pkt_tracepoints_enabled())
  3721. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  3722. desc->msdu_ext_desc ?
  3723. desc->msdu_ext_desc->tso_desc : NULL,
  3724. desc->timestamp);
  3725. if (!(desc->msdu_ext_desc)) {
  3726. dp_tx_enh_unmap(soc, desc);
  3727. if (txrx_peer)
  3728. peer_id = txrx_peer->peer_id;
  3729. if (QDF_STATUS_SUCCESS ==
  3730. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  3731. return;
  3732. }
  3733. if (QDF_STATUS_SUCCESS ==
  3734. dp_get_completion_indication_for_stack(soc,
  3735. desc->pdev,
  3736. txrx_peer, ts,
  3737. desc->nbuf,
  3738. time_latency)) {
  3739. dp_send_completion_to_stack(soc,
  3740. desc->pdev,
  3741. ts->peer_id,
  3742. ts->ppdu_id,
  3743. desc->nbuf);
  3744. return;
  3745. }
  3746. }
  3747. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3748. dp_tx_comp_free_buf(soc, desc);
  3749. }
  3750. #ifdef DISABLE_DP_STATS
  3751. /**
  3752. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3753. * @soc: core txrx main context
  3754. * @tx_desc: tx desc
  3755. * @status: tx status
  3756. *
  3757. * Return: none
  3758. */
  3759. static inline
  3760. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3761. struct dp_vdev *vdev,
  3762. struct dp_tx_desc_s *tx_desc,
  3763. uint8_t status)
  3764. {
  3765. }
  3766. #else
  3767. static inline
  3768. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3769. struct dp_vdev *vdev,
  3770. struct dp_tx_desc_s *tx_desc,
  3771. uint8_t status)
  3772. {
  3773. void *osif_dev;
  3774. ol_txrx_stats_rx_fp stats_cbk;
  3775. uint8_t pkt_type;
  3776. qdf_assert(tx_desc);
  3777. if (!vdev ||
  3778. !vdev->osif_vdev ||
  3779. !vdev->stats_cb)
  3780. return;
  3781. osif_dev = vdev->osif_vdev;
  3782. stats_cbk = vdev->stats_cb;
  3783. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3784. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3785. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3786. &pkt_type);
  3787. }
  3788. #endif
  3789. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF)
  3790. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3791. uint32_t delta_tsf)
  3792. {
  3793. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3794. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3795. DP_MOD_ID_CDP);
  3796. if (!vdev) {
  3797. dp_err_rl("vdev %d does not exist", vdev_id);
  3798. return;
  3799. }
  3800. vdev->delta_tsf = delta_tsf;
  3801. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3802. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3803. }
  3804. #endif
  3805. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3806. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3807. uint8_t vdev_id, bool enable)
  3808. {
  3809. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3810. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3811. DP_MOD_ID_CDP);
  3812. if (!vdev) {
  3813. dp_err_rl("vdev %d does not exist", vdev_id);
  3814. return QDF_STATUS_E_FAILURE;
  3815. }
  3816. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3817. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3818. return QDF_STATUS_SUCCESS;
  3819. }
  3820. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3821. uint32_t *val)
  3822. {
  3823. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3824. struct dp_vdev *vdev;
  3825. uint32_t delay_accum;
  3826. uint32_t pkts_accum;
  3827. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  3828. if (!vdev) {
  3829. dp_err_rl("vdev %d does not exist", vdev_id);
  3830. return QDF_STATUS_E_FAILURE;
  3831. }
  3832. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  3833. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3834. return QDF_STATUS_E_FAILURE;
  3835. }
  3836. /* Average uplink delay based on current accumulated values */
  3837. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  3838. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  3839. *val = delay_accum / pkts_accum;
  3840. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  3841. delay_accum, pkts_accum);
  3842. /* Reset accumulated values to 0 */
  3843. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  3844. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  3845. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3846. return QDF_STATUS_SUCCESS;
  3847. }
  3848. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3849. struct hal_tx_completion_status *ts)
  3850. {
  3851. uint32_t buffer_ts;
  3852. uint32_t delta_tsf;
  3853. uint32_t ul_delay;
  3854. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3855. if (!ts->valid)
  3856. return;
  3857. if (qdf_unlikely(!vdev)) {
  3858. dp_info_rl("vdev is null or delete in progrss");
  3859. return;
  3860. }
  3861. if (!qdf_atomic_read(&vdev->ul_delay_report))
  3862. return;
  3863. delta_tsf = vdev->delta_tsf;
  3864. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3865. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3866. * valid up to 29 bits.
  3867. */
  3868. buffer_ts = ts->buffer_timestamp << 10;
  3869. ul_delay = ts->tsf - buffer_ts - delta_tsf;
  3870. ul_delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3871. if (ul_delay > 0x1000000) {
  3872. dp_info_rl("----------------------\n"
  3873. "Tx completion status:\n"
  3874. "----------------------\n"
  3875. "release_src = %d\n"
  3876. "ppdu_id = 0x%x\n"
  3877. "release_reason = %d\n"
  3878. "tsf = %u (0x%x)\n"
  3879. "buffer_timestamp = %u (0x%x)\n"
  3880. "delta_tsf = %u (0x%x)\n",
  3881. ts->release_src, ts->ppdu_id, ts->status,
  3882. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3883. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3884. return;
  3885. }
  3886. ul_delay /= 1000; /* in unit of ms */
  3887. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  3888. qdf_atomic_inc(&vdev->ul_pkts_accum);
  3889. }
  3890. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  3891. static inline
  3892. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3893. struct hal_tx_completion_status *ts)
  3894. {
  3895. }
  3896. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  3897. /**
  3898. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3899. * @soc: DP soc handle
  3900. * @tx_desc: software descriptor head pointer
  3901. * @ts: Tx completion status
  3902. * @txrx_peer: txrx peer handle
  3903. * @ring_id: ring number
  3904. *
  3905. * Return: none
  3906. */
  3907. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3908. struct dp_tx_desc_s *tx_desc,
  3909. struct hal_tx_completion_status *ts,
  3910. struct dp_txrx_peer *txrx_peer,
  3911. uint8_t ring_id)
  3912. {
  3913. uint32_t length;
  3914. qdf_ether_header_t *eh;
  3915. struct dp_vdev *vdev = NULL;
  3916. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3917. enum qdf_dp_tx_rx_status dp_status;
  3918. if (!nbuf) {
  3919. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3920. goto out;
  3921. }
  3922. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3923. length = qdf_nbuf_len(nbuf);
  3924. dp_status = dp_tx_hw_to_qdf(ts->status);
  3925. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3926. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3927. QDF_TRACE_DEFAULT_PDEV_ID,
  3928. qdf_nbuf_data_addr(nbuf),
  3929. sizeof(qdf_nbuf_data(nbuf)),
  3930. tx_desc->id, ts->status, dp_status));
  3931. dp_tx_comp_debug("-------------------- \n"
  3932. "Tx Completion Stats: \n"
  3933. "-------------------- \n"
  3934. "ack_frame_rssi = %d \n"
  3935. "first_msdu = %d \n"
  3936. "last_msdu = %d \n"
  3937. "msdu_part_of_amsdu = %d \n"
  3938. "rate_stats valid = %d \n"
  3939. "bw = %d \n"
  3940. "pkt_type = %d \n"
  3941. "stbc = %d \n"
  3942. "ldpc = %d \n"
  3943. "sgi = %d \n"
  3944. "mcs = %d \n"
  3945. "ofdma = %d \n"
  3946. "tones_in_ru = %d \n"
  3947. "tsf = %d \n"
  3948. "ppdu_id = %d \n"
  3949. "transmit_cnt = %d \n"
  3950. "tid = %d \n"
  3951. "peer_id = %d\n"
  3952. "tx_status = %d\n",
  3953. ts->ack_frame_rssi, ts->first_msdu,
  3954. ts->last_msdu, ts->msdu_part_of_amsdu,
  3955. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3956. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3957. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3958. ts->transmit_cnt, ts->tid, ts->peer_id,
  3959. ts->status);
  3960. /* Update SoC level stats */
  3961. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3962. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3963. if (!txrx_peer) {
  3964. dp_info_rl("peer is null or deletion in progress");
  3965. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3966. goto out;
  3967. }
  3968. vdev = txrx_peer->vdev;
  3969. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3970. dp_tx_update_uplink_delay(soc, vdev, ts);
  3971. /* Update per-packet stats for mesh mode */
  3972. if (qdf_unlikely(vdev->mesh_vdev) &&
  3973. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3974. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3975. /* Update peer level stats */
  3976. if (qdf_unlikely(txrx_peer->bss_peer &&
  3977. vdev->opmode == wlan_op_mode_ap)) {
  3978. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3979. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  3980. length);
  3981. if (txrx_peer->vdev->tx_encap_type ==
  3982. htt_cmn_pkt_type_ethernet &&
  3983. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3984. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  3985. tx.bcast, 1,
  3986. length);
  3987. }
  3988. }
  3989. } else {
  3990. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  3991. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3992. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  3993. 1, length);
  3994. if (qdf_unlikely(txrx_peer->in_twt)) {
  3995. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  3996. tx.tx_success_twt,
  3997. 1, length);
  3998. }
  3999. }
  4000. }
  4001. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4002. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts->tid, ring_id);
  4003. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4004. ts, ts->tid);
  4005. #ifdef QCA_SUPPORT_RDK_STATS
  4006. if (soc->rdkstats_enabled)
  4007. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4008. tx_desc->timestamp,
  4009. ts->ppdu_id);
  4010. #endif
  4011. out:
  4012. return;
  4013. }
  4014. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4015. defined(QCA_ENHANCED_STATS_SUPPORT)
  4016. /*
  4017. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4018. * @txrx_peer: Datapath txrx_peer handle
  4019. * @length: Length of the packet
  4020. * @tx_status: Tx status from TQM/FW
  4021. * @update: enhanced flag value present in dp_pdev
  4022. *
  4023. * Return: none
  4024. */
  4025. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4026. uint32_t length, uint8_t tx_status,
  4027. bool update)
  4028. {
  4029. if ((!txrx_peer->hw_txrx_stats_en) || update) {
  4030. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4031. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4032. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4033. }
  4034. }
  4035. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4036. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4037. uint32_t length, uint8_t tx_status,
  4038. bool update)
  4039. {
  4040. if (!peer->hw_txrx_stats_en) {
  4041. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4042. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4043. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4044. }
  4045. }
  4046. #else
  4047. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4048. uint32_t length, uint8_t tx_status,
  4049. bool update)
  4050. {
  4051. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4052. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4053. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4054. }
  4055. #endif
  4056. /*
  4057. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4058. * @nbuf: skb buffer
  4059. *
  4060. * Return: none
  4061. */
  4062. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4063. static inline
  4064. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4065. {
  4066. qdf_nbuf_t nbuf = NULL;
  4067. if (next)
  4068. nbuf = next->nbuf;
  4069. if (nbuf) {
  4070. /* prefetch skb->next and first few bytes of skb->cb */
  4071. qdf_prefetch(nbuf);
  4072. /* prefetch skb fields present in different cachelines */
  4073. qdf_prefetch(&nbuf->len);
  4074. qdf_prefetch(&nbuf->users);
  4075. }
  4076. }
  4077. #else
  4078. static inline
  4079. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4080. {
  4081. }
  4082. #endif
  4083. /**
  4084. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4085. * @soc: core txrx main context
  4086. * @comp_head: software descriptor head pointer
  4087. * @ring_id: ring number
  4088. *
  4089. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4090. * and release the software descriptors after processing is complete
  4091. *
  4092. * Return: none
  4093. */
  4094. static void
  4095. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4096. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4097. {
  4098. struct dp_tx_desc_s *desc;
  4099. struct dp_tx_desc_s *next;
  4100. struct hal_tx_completion_status ts;
  4101. struct dp_txrx_peer *txrx_peer = NULL;
  4102. uint16_t peer_id = DP_INVALID_PEER;
  4103. qdf_nbuf_t netbuf;
  4104. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4105. desc = comp_head;
  4106. while (desc) {
  4107. next = desc->next;
  4108. dp_tx_prefetch_next_nbuf_data(next);
  4109. if (peer_id != desc->peer_id) {
  4110. if (txrx_peer)
  4111. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4112. DP_MOD_ID_TX_COMP);
  4113. peer_id = desc->peer_id;
  4114. txrx_peer =
  4115. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4116. &txrx_ref_handle,
  4117. DP_MOD_ID_TX_COMP);
  4118. }
  4119. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4120. struct dp_pdev *pdev = desc->pdev;
  4121. if (qdf_likely(txrx_peer))
  4122. dp_tx_update_peer_basic_stats(txrx_peer,
  4123. desc->length,
  4124. desc->tx_status,
  4125. false);
  4126. qdf_assert(pdev);
  4127. dp_tx_outstanding_dec(pdev);
  4128. /*
  4129. * Calling a QDF WRAPPER here is creating signifcant
  4130. * performance impact so avoided the wrapper call here
  4131. */
  4132. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4133. desc->id, DP_TX_COMP_UNMAP);
  4134. dp_tx_nbuf_unmap(soc, desc);
  4135. qdf_nbuf_free(desc->nbuf);
  4136. dp_tx_desc_free(soc, desc, desc->pool_id);
  4137. desc = next;
  4138. continue;
  4139. }
  4140. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4141. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4142. ring_id);
  4143. netbuf = desc->nbuf;
  4144. /* check tx complete notification */
  4145. if (txrx_peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  4146. dp_tx_notify_completion(soc, txrx_peer->vdev, desc,
  4147. netbuf, ts.status);
  4148. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4149. dp_tx_desc_release(desc, desc->pool_id);
  4150. desc = next;
  4151. }
  4152. if (txrx_peer)
  4153. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4154. }
  4155. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4156. static inline
  4157. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4158. int max_reap_limit)
  4159. {
  4160. bool limit_hit = false;
  4161. limit_hit =
  4162. (num_reaped >= max_reap_limit) ? true : false;
  4163. if (limit_hit)
  4164. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4165. return limit_hit;
  4166. }
  4167. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4168. {
  4169. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4170. }
  4171. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4172. {
  4173. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4174. return cfg->tx_comp_loop_pkt_limit;
  4175. }
  4176. #else
  4177. static inline
  4178. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4179. int max_reap_limit)
  4180. {
  4181. return false;
  4182. }
  4183. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4184. {
  4185. return false;
  4186. }
  4187. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4188. {
  4189. return 0;
  4190. }
  4191. #endif
  4192. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4193. static inline int
  4194. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4195. int *max_reap_limit)
  4196. {
  4197. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4198. max_reap_limit);
  4199. }
  4200. #else
  4201. static inline int
  4202. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4203. int *max_reap_limit)
  4204. {
  4205. return 0;
  4206. }
  4207. #endif
  4208. #ifdef DP_TX_TRACKING
  4209. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4210. {
  4211. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4212. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4213. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4214. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4215. }
  4216. }
  4217. #endif
  4218. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4219. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4220. uint32_t quota)
  4221. {
  4222. void *tx_comp_hal_desc;
  4223. void *last_prefetched_hw_desc = NULL;
  4224. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4225. hal_soc_handle_t hal_soc;
  4226. uint8_t buffer_src;
  4227. struct dp_tx_desc_s *tx_desc = NULL;
  4228. struct dp_tx_desc_s *head_desc = NULL;
  4229. struct dp_tx_desc_s *tail_desc = NULL;
  4230. uint32_t num_processed = 0;
  4231. uint32_t count;
  4232. uint32_t num_avail_for_reap = 0;
  4233. bool force_break = false;
  4234. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4235. int max_reap_limit, ring_near_full;
  4236. DP_HIST_INIT();
  4237. more_data:
  4238. hal_soc = soc->hal_soc;
  4239. /* Re-initialize local variables to be re-used */
  4240. head_desc = NULL;
  4241. tail_desc = NULL;
  4242. count = 0;
  4243. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4244. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4245. &max_reap_limit);
  4246. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4247. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4248. return 0;
  4249. }
  4250. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4251. if (num_avail_for_reap >= quota)
  4252. num_avail_for_reap = quota;
  4253. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4254. last_prefetched_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  4255. num_avail_for_reap);
  4256. /* Find head descriptor from completion ring */
  4257. while (qdf_likely(num_avail_for_reap--)) {
  4258. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4259. if (qdf_unlikely(!tx_comp_hal_desc))
  4260. break;
  4261. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4262. tx_comp_hal_desc);
  4263. /* If this buffer was not released by TQM or FW, then it is not
  4264. * Tx completion indication, assert */
  4265. if (qdf_unlikely(buffer_src !=
  4266. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4267. (qdf_unlikely(buffer_src !=
  4268. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4269. uint8_t wbm_internal_error;
  4270. dp_err_rl(
  4271. "Tx comp release_src != TQM | FW but from %d",
  4272. buffer_src);
  4273. hal_dump_comp_desc(tx_comp_hal_desc);
  4274. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4275. /* When WBM sees NULL buffer_addr_info in any of
  4276. * ingress rings it sends an error indication,
  4277. * with wbm_internal_error=1, to a specific ring.
  4278. * The WBM2SW ring used to indicate these errors is
  4279. * fixed in HW, and that ring is being used as Tx
  4280. * completion ring. These errors are not related to
  4281. * Tx completions, and should just be ignored
  4282. */
  4283. wbm_internal_error = hal_get_wbm_internal_error(
  4284. hal_soc,
  4285. tx_comp_hal_desc);
  4286. if (wbm_internal_error) {
  4287. dp_err_rl("Tx comp wbm_internal_error!!");
  4288. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4289. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4290. buffer_src)
  4291. dp_handle_wbm_internal_error(
  4292. soc,
  4293. tx_comp_hal_desc,
  4294. hal_tx_comp_get_buffer_type(
  4295. tx_comp_hal_desc));
  4296. } else {
  4297. dp_err_rl("Tx comp wbm_internal_error false");
  4298. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4299. }
  4300. continue;
  4301. }
  4302. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4303. tx_comp_hal_desc,
  4304. &tx_desc);
  4305. if (!tx_desc) {
  4306. dp_err("unable to retrieve tx_desc!");
  4307. QDF_BUG(0);
  4308. continue;
  4309. }
  4310. tx_desc->buffer_src = buffer_src;
  4311. /*
  4312. * If the release source is FW, process the HTT status
  4313. */
  4314. if (qdf_unlikely(buffer_src ==
  4315. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4316. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4317. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4318. htt_tx_status);
  4319. /* Collect hw completion contents */
  4320. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4321. &tx_desc->comp, 1);
  4322. soc->arch_ops.dp_tx_process_htt_completion(
  4323. soc,
  4324. tx_desc,
  4325. htt_tx_status,
  4326. ring_id);
  4327. } else {
  4328. tx_desc->tx_status =
  4329. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4330. tx_desc->buffer_src = buffer_src;
  4331. /*
  4332. * If the fast completion mode is enabled extended
  4333. * metadata from descriptor is not copied
  4334. */
  4335. if (qdf_likely(tx_desc->flags &
  4336. DP_TX_DESC_FLAG_SIMPLE))
  4337. goto add_to_pool;
  4338. /*
  4339. * If the descriptor is already freed in vdev_detach,
  4340. * continue to next descriptor
  4341. */
  4342. if (qdf_unlikely
  4343. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4344. !tx_desc->flags)) {
  4345. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4346. tx_desc->id);
  4347. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4348. dp_tx_desc_check_corruption(tx_desc);
  4349. continue;
  4350. }
  4351. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4352. dp_tx_comp_info_rl("pdev in down state %d",
  4353. tx_desc->id);
  4354. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4355. dp_tx_comp_free_buf(soc, tx_desc);
  4356. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4357. goto next_desc;
  4358. }
  4359. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4360. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4361. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4362. tx_desc->flags, tx_desc->id);
  4363. qdf_assert_always(0);
  4364. }
  4365. /* Collect hw completion contents */
  4366. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4367. &tx_desc->comp, 1);
  4368. add_to_pool:
  4369. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4370. /* First ring descriptor on the cycle */
  4371. if (!head_desc) {
  4372. head_desc = tx_desc;
  4373. tail_desc = tx_desc;
  4374. }
  4375. tail_desc->next = tx_desc;
  4376. tx_desc->next = NULL;
  4377. tail_desc = tx_desc;
  4378. }
  4379. next_desc:
  4380. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4381. /*
  4382. * Processed packet count is more than given quota
  4383. * stop to processing
  4384. */
  4385. count++;
  4386. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  4387. num_avail_for_reap,
  4388. hal_ring_hdl,
  4389. &last_prefetched_hw_desc,
  4390. &last_prefetched_sw_desc);
  4391. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4392. break;
  4393. }
  4394. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4395. /* Process the reaped descriptors */
  4396. if (head_desc)
  4397. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4398. /*
  4399. * If we are processing in near-full condition, there are 3 scenario
  4400. * 1) Ring entries has reached critical state
  4401. * 2) Ring entries are still near high threshold
  4402. * 3) Ring entries are below the safe level
  4403. *
  4404. * One more loop will move te state to normal processing and yield
  4405. */
  4406. if (ring_near_full)
  4407. goto more_data;
  4408. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4409. if (num_processed >= quota)
  4410. force_break = true;
  4411. if (!force_break &&
  4412. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4413. hal_ring_hdl)) {
  4414. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4415. if (!hif_exec_should_yield(soc->hif_handle,
  4416. int_ctx->dp_intr_id))
  4417. goto more_data;
  4418. }
  4419. }
  4420. DP_TX_HIST_STATS_PER_PDEV();
  4421. return num_processed;
  4422. }
  4423. #ifdef FEATURE_WLAN_TDLS
  4424. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4425. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4426. {
  4427. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4428. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4429. DP_MOD_ID_TDLS);
  4430. if (!vdev) {
  4431. dp_err("vdev handle for id %d is NULL", vdev_id);
  4432. return NULL;
  4433. }
  4434. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4435. vdev->is_tdls_frame = true;
  4436. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4437. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4438. }
  4439. #endif
  4440. /**
  4441. * dp_tx_vdev_attach() - attach vdev to dp tx
  4442. * @vdev: virtual device instance
  4443. *
  4444. * Return: QDF_STATUS_SUCCESS: success
  4445. * QDF_STATUS_E_RESOURCES: Error return
  4446. */
  4447. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4448. {
  4449. int pdev_id;
  4450. /*
  4451. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4452. */
  4453. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4454. DP_TCL_METADATA_TYPE_VDEV_BASED);
  4455. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4456. vdev->vdev_id);
  4457. pdev_id =
  4458. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4459. vdev->pdev->pdev_id);
  4460. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4461. /*
  4462. * Set HTT Extension Valid bit to 0 by default
  4463. */
  4464. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4465. dp_tx_vdev_update_search_flags(vdev);
  4466. return QDF_STATUS_SUCCESS;
  4467. }
  4468. #ifndef FEATURE_WDS
  4469. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4470. {
  4471. return false;
  4472. }
  4473. #endif
  4474. /**
  4475. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4476. * @vdev: virtual device instance
  4477. *
  4478. * Return: void
  4479. *
  4480. */
  4481. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4482. {
  4483. struct dp_soc *soc = vdev->pdev->soc;
  4484. /*
  4485. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4486. * for TDLS link
  4487. *
  4488. * Enable AddrY (SA based search) only for non-WDS STA and
  4489. * ProxySTA VAP (in HKv1) modes.
  4490. *
  4491. * In all other VAP modes, only DA based search should be
  4492. * enabled
  4493. */
  4494. if (vdev->opmode == wlan_op_mode_sta &&
  4495. vdev->tdls_link_connected)
  4496. vdev->hal_desc_addr_search_flags =
  4497. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4498. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4499. !dp_tx_da_search_override(vdev))
  4500. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4501. else
  4502. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4503. if (vdev->opmode == wlan_op_mode_sta)
  4504. vdev->search_type = soc->sta_mode_search_policy;
  4505. else
  4506. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4507. }
  4508. static inline bool
  4509. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4510. struct dp_vdev *vdev,
  4511. struct dp_tx_desc_s *tx_desc)
  4512. {
  4513. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4514. return false;
  4515. /*
  4516. * if vdev is given, then only check whether desc
  4517. * vdev match. if vdev is NULL, then check whether
  4518. * desc pdev match.
  4519. */
  4520. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4521. (tx_desc->pdev == pdev);
  4522. }
  4523. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4524. /**
  4525. * dp_tx_desc_flush() - release resources associated
  4526. * to TX Desc
  4527. *
  4528. * @dp_pdev: Handle to DP pdev structure
  4529. * @vdev: virtual device instance
  4530. * NULL: no specific Vdev is required and check all allcated TX desc
  4531. * on this pdev.
  4532. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4533. *
  4534. * @force_free:
  4535. * true: flush the TX desc.
  4536. * false: only reset the Vdev in each allocated TX desc
  4537. * that associated to current Vdev.
  4538. *
  4539. * This function will go through the TX desc pool to flush
  4540. * the outstanding TX data or reset Vdev to NULL in associated TX
  4541. * Desc.
  4542. */
  4543. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4544. bool force_free)
  4545. {
  4546. uint8_t i;
  4547. uint32_t j;
  4548. uint32_t num_desc, page_id, offset;
  4549. uint16_t num_desc_per_page;
  4550. struct dp_soc *soc = pdev->soc;
  4551. struct dp_tx_desc_s *tx_desc = NULL;
  4552. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4553. if (!vdev && !force_free) {
  4554. dp_err("Reset TX desc vdev, Vdev param is required!");
  4555. return;
  4556. }
  4557. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4558. tx_desc_pool = &soc->tx_desc[i];
  4559. if (!(tx_desc_pool->pool_size) ||
  4560. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4561. !(tx_desc_pool->desc_pages.cacheable_pages))
  4562. continue;
  4563. /*
  4564. * Add flow pool lock protection in case pool is freed
  4565. * due to all tx_desc is recycled when handle TX completion.
  4566. * this is not necessary when do force flush as:
  4567. * a. double lock will happen if dp_tx_desc_release is
  4568. * also trying to acquire it.
  4569. * b. dp interrupt has been disabled before do force TX desc
  4570. * flush in dp_pdev_deinit().
  4571. */
  4572. if (!force_free)
  4573. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4574. num_desc = tx_desc_pool->pool_size;
  4575. num_desc_per_page =
  4576. tx_desc_pool->desc_pages.num_element_per_page;
  4577. for (j = 0; j < num_desc; j++) {
  4578. page_id = j / num_desc_per_page;
  4579. offset = j % num_desc_per_page;
  4580. if (qdf_unlikely(!(tx_desc_pool->
  4581. desc_pages.cacheable_pages)))
  4582. break;
  4583. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4584. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4585. /*
  4586. * Free TX desc if force free is
  4587. * required, otherwise only reset vdev
  4588. * in this TX desc.
  4589. */
  4590. if (force_free) {
  4591. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4592. dp_tx_comp_free_buf(soc, tx_desc);
  4593. dp_tx_desc_release(tx_desc, i);
  4594. } else {
  4595. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4596. }
  4597. }
  4598. }
  4599. if (!force_free)
  4600. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4601. }
  4602. }
  4603. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4604. /**
  4605. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4606. *
  4607. * @soc: Handle to DP soc structure
  4608. * @tx_desc: pointer of one TX desc
  4609. * @desc_pool_id: TX Desc pool id
  4610. */
  4611. static inline void
  4612. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4613. uint8_t desc_pool_id)
  4614. {
  4615. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4616. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4617. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4618. }
  4619. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4620. bool force_free)
  4621. {
  4622. uint8_t i, num_pool;
  4623. uint32_t j;
  4624. uint32_t num_desc, page_id, offset;
  4625. uint16_t num_desc_per_page;
  4626. struct dp_soc *soc = pdev->soc;
  4627. struct dp_tx_desc_s *tx_desc = NULL;
  4628. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4629. if (!vdev && !force_free) {
  4630. dp_err("Reset TX desc vdev, Vdev param is required!");
  4631. return;
  4632. }
  4633. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4634. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4635. for (i = 0; i < num_pool; i++) {
  4636. tx_desc_pool = &soc->tx_desc[i];
  4637. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4638. continue;
  4639. num_desc_per_page =
  4640. tx_desc_pool->desc_pages.num_element_per_page;
  4641. for (j = 0; j < num_desc; j++) {
  4642. page_id = j / num_desc_per_page;
  4643. offset = j % num_desc_per_page;
  4644. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4645. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4646. if (force_free) {
  4647. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4648. dp_tx_comp_free_buf(soc, tx_desc);
  4649. dp_tx_desc_release(tx_desc, i);
  4650. } else {
  4651. dp_tx_desc_reset_vdev(soc, tx_desc,
  4652. i);
  4653. }
  4654. }
  4655. }
  4656. }
  4657. }
  4658. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4659. /**
  4660. * dp_tx_vdev_detach() - detach vdev from dp tx
  4661. * @vdev: virtual device instance
  4662. *
  4663. * Return: QDF_STATUS_SUCCESS: success
  4664. * QDF_STATUS_E_RESOURCES: Error return
  4665. */
  4666. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4667. {
  4668. struct dp_pdev *pdev = vdev->pdev;
  4669. /* Reset TX desc associated to this Vdev as NULL */
  4670. dp_tx_desc_flush(pdev, vdev, false);
  4671. return QDF_STATUS_SUCCESS;
  4672. }
  4673. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4674. /* Pools will be allocated dynamically */
  4675. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4676. int num_desc)
  4677. {
  4678. uint8_t i;
  4679. for (i = 0; i < num_pool; i++) {
  4680. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4681. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4682. }
  4683. return QDF_STATUS_SUCCESS;
  4684. }
  4685. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4686. int num_desc)
  4687. {
  4688. return QDF_STATUS_SUCCESS;
  4689. }
  4690. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4691. {
  4692. }
  4693. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4694. {
  4695. uint8_t i;
  4696. for (i = 0; i < num_pool; i++)
  4697. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4698. }
  4699. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4700. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4701. int num_desc)
  4702. {
  4703. uint8_t i, count;
  4704. /* Allocate software Tx descriptor pools */
  4705. for (i = 0; i < num_pool; i++) {
  4706. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4707. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4708. FL("Tx Desc Pool alloc %d failed %pK"),
  4709. i, soc);
  4710. goto fail;
  4711. }
  4712. }
  4713. return QDF_STATUS_SUCCESS;
  4714. fail:
  4715. for (count = 0; count < i; count++)
  4716. dp_tx_desc_pool_free(soc, count);
  4717. return QDF_STATUS_E_NOMEM;
  4718. }
  4719. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4720. int num_desc)
  4721. {
  4722. uint8_t i;
  4723. for (i = 0; i < num_pool; i++) {
  4724. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4725. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4726. FL("Tx Desc Pool init %d failed %pK"),
  4727. i, soc);
  4728. return QDF_STATUS_E_NOMEM;
  4729. }
  4730. }
  4731. return QDF_STATUS_SUCCESS;
  4732. }
  4733. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4734. {
  4735. uint8_t i;
  4736. for (i = 0; i < num_pool; i++)
  4737. dp_tx_desc_pool_deinit(soc, i);
  4738. }
  4739. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4740. {
  4741. uint8_t i;
  4742. for (i = 0; i < num_pool; i++)
  4743. dp_tx_desc_pool_free(soc, i);
  4744. }
  4745. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4746. /**
  4747. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4748. * @soc: core txrx main context
  4749. * @num_pool: number of pools
  4750. *
  4751. */
  4752. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4753. {
  4754. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4755. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4756. }
  4757. /**
  4758. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4759. * @soc: core txrx main context
  4760. * @num_pool: number of pools
  4761. *
  4762. */
  4763. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4764. {
  4765. dp_tx_tso_desc_pool_free(soc, num_pool);
  4766. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4767. }
  4768. /**
  4769. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4770. * @soc: core txrx main context
  4771. *
  4772. * This function frees all tx related descriptors as below
  4773. * 1. Regular TX descriptors (static pools)
  4774. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4775. * 3. TSO descriptors
  4776. *
  4777. */
  4778. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4779. {
  4780. uint8_t num_pool;
  4781. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4782. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4783. dp_tx_ext_desc_pool_free(soc, num_pool);
  4784. dp_tx_delete_static_pools(soc, num_pool);
  4785. }
  4786. /**
  4787. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4788. * @soc: core txrx main context
  4789. *
  4790. * This function de-initializes all tx related descriptors as below
  4791. * 1. Regular TX descriptors (static pools)
  4792. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4793. * 3. TSO descriptors
  4794. *
  4795. */
  4796. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4797. {
  4798. uint8_t num_pool;
  4799. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4800. dp_tx_flow_control_deinit(soc);
  4801. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4802. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4803. dp_tx_deinit_static_pools(soc, num_pool);
  4804. }
  4805. /**
  4806. * dp_tso_attach() - TSO attach handler
  4807. * @txrx_soc: Opaque Dp handle
  4808. *
  4809. * Reserve TSO descriptor buffers
  4810. *
  4811. * Return: QDF_STATUS_E_FAILURE on failure or
  4812. * QDF_STATUS_SUCCESS on success
  4813. */
  4814. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4815. uint8_t num_pool,
  4816. uint16_t num_desc)
  4817. {
  4818. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4819. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4820. return QDF_STATUS_E_FAILURE;
  4821. }
  4822. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4823. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4824. num_pool, soc);
  4825. return QDF_STATUS_E_FAILURE;
  4826. }
  4827. return QDF_STATUS_SUCCESS;
  4828. }
  4829. /**
  4830. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4831. * @soc: DP soc handle
  4832. * @num_pool: Number of pools
  4833. * @num_desc: Number of descriptors
  4834. *
  4835. * Initialize TSO descriptor pools
  4836. *
  4837. * Return: QDF_STATUS_E_FAILURE on failure or
  4838. * QDF_STATUS_SUCCESS on success
  4839. */
  4840. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4841. uint8_t num_pool,
  4842. uint16_t num_desc)
  4843. {
  4844. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4845. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4846. return QDF_STATUS_E_FAILURE;
  4847. }
  4848. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4849. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4850. num_pool, soc);
  4851. return QDF_STATUS_E_FAILURE;
  4852. }
  4853. return QDF_STATUS_SUCCESS;
  4854. }
  4855. /**
  4856. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4857. * @soc: core txrx main context
  4858. *
  4859. * This function allocates memory for following descriptor pools
  4860. * 1. regular sw tx descriptor pools (static pools)
  4861. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4862. * 3. TSO descriptor pools
  4863. *
  4864. * Return: QDF_STATUS_SUCCESS: success
  4865. * QDF_STATUS_E_RESOURCES: Error return
  4866. */
  4867. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4868. {
  4869. uint8_t num_pool;
  4870. uint32_t num_desc;
  4871. uint32_t num_ext_desc;
  4872. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4873. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4874. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4875. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4876. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4877. __func__, num_pool, num_desc);
  4878. if ((num_pool > MAX_TXDESC_POOLS) ||
  4879. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4880. goto fail1;
  4881. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4882. goto fail1;
  4883. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4884. goto fail2;
  4885. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4886. return QDF_STATUS_SUCCESS;
  4887. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4888. goto fail3;
  4889. return QDF_STATUS_SUCCESS;
  4890. fail3:
  4891. dp_tx_ext_desc_pool_free(soc, num_pool);
  4892. fail2:
  4893. dp_tx_delete_static_pools(soc, num_pool);
  4894. fail1:
  4895. return QDF_STATUS_E_RESOURCES;
  4896. }
  4897. /**
  4898. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4899. * @soc: core txrx main context
  4900. *
  4901. * This function initializes the following TX descriptor pools
  4902. * 1. regular sw tx descriptor pools (static pools)
  4903. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4904. * 3. TSO descriptor pools
  4905. *
  4906. * Return: QDF_STATUS_SUCCESS: success
  4907. * QDF_STATUS_E_RESOURCES: Error return
  4908. */
  4909. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4910. {
  4911. uint8_t num_pool;
  4912. uint32_t num_desc;
  4913. uint32_t num_ext_desc;
  4914. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4915. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4916. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4917. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4918. goto fail1;
  4919. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4920. goto fail2;
  4921. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4922. return QDF_STATUS_SUCCESS;
  4923. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4924. goto fail3;
  4925. dp_tx_flow_control_init(soc);
  4926. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4927. return QDF_STATUS_SUCCESS;
  4928. fail3:
  4929. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4930. fail2:
  4931. dp_tx_deinit_static_pools(soc, num_pool);
  4932. fail1:
  4933. return QDF_STATUS_E_RESOURCES;
  4934. }
  4935. /**
  4936. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4937. * @txrx_soc: dp soc handle
  4938. *
  4939. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4940. * QDF_STATUS_E_FAILURE
  4941. */
  4942. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4943. {
  4944. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4945. uint8_t num_pool;
  4946. uint32_t num_desc;
  4947. uint32_t num_ext_desc;
  4948. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4949. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4950. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4951. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4952. return QDF_STATUS_E_FAILURE;
  4953. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4954. return QDF_STATUS_E_FAILURE;
  4955. return QDF_STATUS_SUCCESS;
  4956. }
  4957. /**
  4958. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4959. * @txrx_soc: dp soc handle
  4960. *
  4961. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4962. */
  4963. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4964. {
  4965. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4966. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4967. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4968. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4969. return QDF_STATUS_SUCCESS;
  4970. }