main.c 111 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, 2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #define pr_fmt(fmt) "icnss2: " fmt
  7. #include <linux/of_address.h>
  8. #include <linux/clk.h>
  9. #include <linux/iommu.h>
  10. #include <linux/export.h>
  11. #include <linux/err.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/init.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/debugfs.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/slab.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/sched.h>
  24. #include <linux/delay.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/thread_info.h>
  27. #include <linux/uaccess.h>
  28. #include <linux/etherdevice.h>
  29. #include <linux/of.h>
  30. #include <linux/of_irq.h>
  31. #include <linux/pm_runtime.h>
  32. #include <linux/soc/qcom/qmi.h>
  33. #include <linux/sysfs.h>
  34. #include <linux/thermal.h>
  35. #include <soc/qcom/memory_dump.h>
  36. #include <soc/qcom/secure_buffer.h>
  37. #include <soc/qcom/socinfo.h>
  38. #include <soc/qcom/qcom_ramdump.h>
  39. #include <linux/soc/qcom/smem.h>
  40. #include <linux/soc/qcom/smem_state.h>
  41. #include <linux/remoteproc.h>
  42. #include <linux/remoteproc/qcom_rproc.h>
  43. #include <linux/soc/qcom/pdr.h>
  44. #include <linux/remoteproc.h>
  45. #include <trace/hooks/remoteproc.h>
  46. #include "main.h"
  47. #include "qmi.h"
  48. #include "debug.h"
  49. #include "power.h"
  50. #include "genl.h"
  51. #define MAX_PROP_SIZE 32
  52. #define NUM_LOG_PAGES 10
  53. #define NUM_LOG_LONG_PAGES 4
  54. #define ICNSS_MAGIC 0x5abc5abc
  55. #define ICNSS_WLAN_SERVICE_NAME "wlan/fw"
  56. #define ICNSS_WLANPD_NAME "msm/modem/wlan_pd"
  57. #define ICNSS_DEFAULT_FEATURE_MASK 0x01
  58. #define ICNSS_M3_SEGMENT(segment) "wcnss_"segment
  59. #define ICNSS_M3_SEGMENT_PHYAREG "phyareg"
  60. #define ICNSS_M3_SEGMENT_PHYA "phydbg"
  61. #define ICNSS_M3_SEGMENT_WMACREG "wmac0reg"
  62. #define ICNSS_M3_SEGMENT_WCSSDBG "WCSSDBG"
  63. #define ICNSS_M3_SEGMENT_PHYAM3 "PHYAPDMEM"
  64. #define ICNSS_QUIRKS_DEFAULT BIT(FW_REJUVENATE_ENABLE)
  65. #define ICNSS_MAX_PROBE_CNT 2
  66. #define ICNSS_BDF_TYPE_DEFAULT ICNSS_BDF_ELF
  67. #define PROBE_TIMEOUT 15000
  68. #define SMP2P_SOC_WAKE_TIMEOUT 500
  69. #ifdef CONFIG_ICNSS2_DEBUG
  70. static unsigned long qmi_timeout = 3000;
  71. module_param(qmi_timeout, ulong, 0600);
  72. #define WLFW_TIMEOUT msecs_to_jiffies(qmi_timeout)
  73. #else
  74. #define WLFW_TIMEOUT msecs_to_jiffies(3000)
  75. #endif
  76. static struct icnss_priv *penv;
  77. static struct work_struct wpss_loader;
  78. uint64_t dynamic_feature_mask = ICNSS_DEFAULT_FEATURE_MASK;
  79. #define ICNSS_EVENT_PENDING 2989
  80. #define ICNSS_EVENT_SYNC BIT(0)
  81. #define ICNSS_EVENT_UNINTERRUPTIBLE BIT(1)
  82. #define ICNSS_EVENT_SYNC_UNINTERRUPTIBLE (ICNSS_EVENT_UNINTERRUPTIBLE | \
  83. ICNSS_EVENT_SYNC)
  84. #define ICNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  85. #define ICNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  86. #define SMP2P_GET_MAX_RETRY 4
  87. #define SMP2P_GET_RETRY_DELAY_MS 500
  88. #define RAMDUMP_NUM_DEVICES 256
  89. #define ICNSS_RAMDUMP_NAME "icnss_ramdump"
  90. #define ICNSS_RPROC_LEN 10
  91. static DEFINE_IDA(rd_minor_id);
  92. enum icnss_pdr_cause_index {
  93. ICNSS_FW_CRASH,
  94. ICNSS_ROOT_PD_CRASH,
  95. ICNSS_ROOT_PD_SHUTDOWN,
  96. ICNSS_HOST_ERROR,
  97. };
  98. static const char * const icnss_pdr_cause[] = {
  99. [ICNSS_FW_CRASH] = "FW crash",
  100. [ICNSS_ROOT_PD_CRASH] = "Root PD crashed",
  101. [ICNSS_ROOT_PD_SHUTDOWN] = "Root PD shutdown",
  102. [ICNSS_HOST_ERROR] = "Host error",
  103. };
  104. static void icnss_set_plat_priv(struct icnss_priv *priv)
  105. {
  106. penv = priv;
  107. }
  108. static struct icnss_priv *icnss_get_plat_priv()
  109. {
  110. return penv;
  111. }
  112. static ssize_t icnss_sysfs_store(struct kobject *kobj,
  113. struct kobj_attribute *attr,
  114. const char *buf, size_t count)
  115. {
  116. struct icnss_priv *priv = icnss_get_plat_priv();
  117. atomic_set(&priv->is_shutdown, true);
  118. icnss_pr_dbg("Received shutdown indication");
  119. return count;
  120. }
  121. static struct kobj_attribute icnss_sysfs_attribute =
  122. __ATTR(shutdown, 0660, NULL, icnss_sysfs_store);
  123. static void icnss_pm_stay_awake(struct icnss_priv *priv)
  124. {
  125. if (atomic_inc_return(&priv->pm_count) != 1)
  126. return;
  127. icnss_pr_vdbg("PM stay awake, state: 0x%lx, count: %d\n", priv->state,
  128. atomic_read(&priv->pm_count));
  129. pm_stay_awake(&priv->pdev->dev);
  130. priv->stats.pm_stay_awake++;
  131. }
  132. static void icnss_pm_relax(struct icnss_priv *priv)
  133. {
  134. int r = atomic_dec_return(&priv->pm_count);
  135. WARN_ON(r < 0);
  136. if (r != 0)
  137. return;
  138. icnss_pr_vdbg("PM relax, state: 0x%lx, count: %d\n", priv->state,
  139. atomic_read(&priv->pm_count));
  140. pm_relax(&priv->pdev->dev);
  141. priv->stats.pm_relax++;
  142. }
  143. char *icnss_driver_event_to_str(enum icnss_driver_event_type type)
  144. {
  145. switch (type) {
  146. case ICNSS_DRIVER_EVENT_SERVER_ARRIVE:
  147. return "SERVER_ARRIVE";
  148. case ICNSS_DRIVER_EVENT_SERVER_EXIT:
  149. return "SERVER_EXIT";
  150. case ICNSS_DRIVER_EVENT_FW_READY_IND:
  151. return "FW_READY";
  152. case ICNSS_DRIVER_EVENT_REGISTER_DRIVER:
  153. return "REGISTER_DRIVER";
  154. case ICNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  155. return "UNREGISTER_DRIVER";
  156. case ICNSS_DRIVER_EVENT_PD_SERVICE_DOWN:
  157. return "PD_SERVICE_DOWN";
  158. case ICNSS_DRIVER_EVENT_FW_EARLY_CRASH_IND:
  159. return "FW_EARLY_CRASH_IND";
  160. case ICNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  161. return "IDLE_SHUTDOWN";
  162. case ICNSS_DRIVER_EVENT_IDLE_RESTART:
  163. return "IDLE_RESTART";
  164. case ICNSS_DRIVER_EVENT_FW_INIT_DONE_IND:
  165. return "FW_INIT_DONE";
  166. case ICNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  167. return "QDSS_TRACE_REQ_MEM";
  168. case ICNSS_DRIVER_EVENT_QDSS_TRACE_SAVE:
  169. return "QDSS_TRACE_SAVE";
  170. case ICNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  171. return "QDSS_TRACE_FREE";
  172. case ICNSS_DRIVER_EVENT_M3_DUMP_UPLOAD_REQ:
  173. return "M3_DUMP_UPLOAD";
  174. case ICNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  175. return "QDSS_TRACE_REQ_DATA";
  176. case ICNSS_DRIVER_EVENT_SUBSYS_RESTART_LEVEL:
  177. return "SUBSYS_RESTART_LEVEL";
  178. case ICNSS_DRIVER_EVENT_MAX:
  179. return "EVENT_MAX";
  180. }
  181. return "UNKNOWN";
  182. };
  183. char *icnss_soc_wake_event_to_str(enum icnss_soc_wake_event_type type)
  184. {
  185. switch (type) {
  186. case ICNSS_SOC_WAKE_REQUEST_EVENT:
  187. return "SOC_WAKE_REQUEST";
  188. case ICNSS_SOC_WAKE_RELEASE_EVENT:
  189. return "SOC_WAKE_RELEASE";
  190. case ICNSS_SOC_WAKE_EVENT_MAX:
  191. return "SOC_EVENT_MAX";
  192. }
  193. return "UNKNOWN";
  194. };
  195. int icnss_driver_event_post(struct icnss_priv *priv,
  196. enum icnss_driver_event_type type,
  197. u32 flags, void *data)
  198. {
  199. struct icnss_driver_event *event;
  200. unsigned long irq_flags;
  201. int gfp = GFP_KERNEL;
  202. int ret = 0;
  203. if (!priv)
  204. return -ENODEV;
  205. icnss_pr_dbg("Posting event: %s(%d), %s, flags: 0x%x, state: 0x%lx\n",
  206. icnss_driver_event_to_str(type), type, current->comm,
  207. flags, priv->state);
  208. if (type >= ICNSS_DRIVER_EVENT_MAX) {
  209. icnss_pr_err("Invalid Event type: %d, can't post", type);
  210. return -EINVAL;
  211. }
  212. if (in_interrupt() || irqs_disabled())
  213. gfp = GFP_ATOMIC;
  214. event = kzalloc(sizeof(*event), gfp);
  215. if (event == NULL)
  216. return -ENOMEM;
  217. icnss_pm_stay_awake(priv);
  218. event->type = type;
  219. event->data = data;
  220. init_completion(&event->complete);
  221. event->ret = ICNSS_EVENT_PENDING;
  222. event->sync = !!(flags & ICNSS_EVENT_SYNC);
  223. spin_lock_irqsave(&priv->event_lock, irq_flags);
  224. list_add_tail(&event->list, &priv->event_list);
  225. spin_unlock_irqrestore(&priv->event_lock, irq_flags);
  226. priv->stats.events[type].posted++;
  227. queue_work(priv->event_wq, &priv->event_work);
  228. if (!(flags & ICNSS_EVENT_SYNC))
  229. goto out;
  230. if (flags & ICNSS_EVENT_UNINTERRUPTIBLE)
  231. wait_for_completion(&event->complete);
  232. else
  233. ret = wait_for_completion_interruptible(&event->complete);
  234. icnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  235. icnss_driver_event_to_str(type), type, priv->state, ret,
  236. event->ret);
  237. spin_lock_irqsave(&priv->event_lock, irq_flags);
  238. if (ret == -ERESTARTSYS && event->ret == ICNSS_EVENT_PENDING) {
  239. event->sync = false;
  240. spin_unlock_irqrestore(&priv->event_lock, irq_flags);
  241. ret = -EINTR;
  242. goto out;
  243. }
  244. spin_unlock_irqrestore(&priv->event_lock, irq_flags);
  245. ret = event->ret;
  246. kfree(event);
  247. out:
  248. icnss_pm_relax(priv);
  249. return ret;
  250. }
  251. int icnss_soc_wake_event_post(struct icnss_priv *priv,
  252. enum icnss_soc_wake_event_type type,
  253. u32 flags, void *data)
  254. {
  255. struct icnss_soc_wake_event *event;
  256. unsigned long irq_flags;
  257. int gfp = GFP_KERNEL;
  258. int ret = 0;
  259. if (!priv)
  260. return -ENODEV;
  261. icnss_pr_soc_wake("Posting event: %s(%d), %s, flags: 0x%x, state: 0x%lx\n",
  262. icnss_soc_wake_event_to_str(type),
  263. type, current->comm, flags, priv->state);
  264. if (type >= ICNSS_SOC_WAKE_EVENT_MAX) {
  265. icnss_pr_err("Invalid Event type: %d, can't post", type);
  266. return -EINVAL;
  267. }
  268. if (in_interrupt() || irqs_disabled())
  269. gfp = GFP_ATOMIC;
  270. event = kzalloc(sizeof(*event), gfp);
  271. if (!event)
  272. return -ENOMEM;
  273. icnss_pm_stay_awake(priv);
  274. event->type = type;
  275. event->data = data;
  276. init_completion(&event->complete);
  277. event->ret = ICNSS_EVENT_PENDING;
  278. event->sync = !!(flags & ICNSS_EVENT_SYNC);
  279. spin_lock_irqsave(&priv->soc_wake_msg_lock, irq_flags);
  280. list_add_tail(&event->list, &priv->soc_wake_msg_list);
  281. spin_unlock_irqrestore(&priv->soc_wake_msg_lock, irq_flags);
  282. priv->stats.soc_wake_events[type].posted++;
  283. queue_work(priv->soc_wake_wq, &priv->soc_wake_msg_work);
  284. if (!(flags & ICNSS_EVENT_SYNC))
  285. goto out;
  286. if (flags & ICNSS_EVENT_UNINTERRUPTIBLE)
  287. wait_for_completion(&event->complete);
  288. else
  289. ret = wait_for_completion_interruptible(&event->complete);
  290. icnss_pr_soc_wake("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  291. icnss_soc_wake_event_to_str(type),
  292. type, priv->state, ret, event->ret);
  293. spin_lock_irqsave(&priv->soc_wake_msg_lock, irq_flags);
  294. if (ret == -ERESTARTSYS && event->ret == ICNSS_EVENT_PENDING) {
  295. event->sync = false;
  296. spin_unlock_irqrestore(&priv->soc_wake_msg_lock, irq_flags);
  297. ret = -EINTR;
  298. goto out;
  299. }
  300. spin_unlock_irqrestore(&priv->soc_wake_msg_lock, irq_flags);
  301. ret = event->ret;
  302. kfree(event);
  303. out:
  304. icnss_pm_relax(priv);
  305. return ret;
  306. }
  307. bool icnss_is_fw_ready(void)
  308. {
  309. if (!penv)
  310. return false;
  311. else
  312. return test_bit(ICNSS_FW_READY, &penv->state);
  313. }
  314. EXPORT_SYMBOL(icnss_is_fw_ready);
  315. void icnss_block_shutdown(bool status)
  316. {
  317. if (!penv)
  318. return;
  319. if (status) {
  320. set_bit(ICNSS_BLOCK_SHUTDOWN, &penv->state);
  321. reinit_completion(&penv->unblock_shutdown);
  322. } else {
  323. clear_bit(ICNSS_BLOCK_SHUTDOWN, &penv->state);
  324. complete(&penv->unblock_shutdown);
  325. }
  326. }
  327. EXPORT_SYMBOL(icnss_block_shutdown);
  328. bool icnss_is_fw_down(void)
  329. {
  330. struct icnss_priv *priv = icnss_get_plat_priv();
  331. if (!priv)
  332. return false;
  333. return test_bit(ICNSS_FW_DOWN, &priv->state) ||
  334. test_bit(ICNSS_PD_RESTART, &priv->state) ||
  335. test_bit(ICNSS_REJUVENATE, &priv->state);
  336. }
  337. EXPORT_SYMBOL(icnss_is_fw_down);
  338. unsigned long icnss_get_device_config(void)
  339. {
  340. struct icnss_priv *priv = icnss_get_plat_priv();
  341. if (!priv)
  342. return 0;
  343. return priv->device_config;
  344. }
  345. EXPORT_SYMBOL(icnss_get_device_config);
  346. bool icnss_is_rejuvenate(void)
  347. {
  348. if (!penv)
  349. return false;
  350. else
  351. return test_bit(ICNSS_REJUVENATE, &penv->state);
  352. }
  353. EXPORT_SYMBOL(icnss_is_rejuvenate);
  354. bool icnss_is_pdr(void)
  355. {
  356. if (!penv)
  357. return false;
  358. else
  359. return test_bit(ICNSS_PDR, &penv->state);
  360. }
  361. EXPORT_SYMBOL(icnss_is_pdr);
  362. static int icnss_send_smp2p(struct icnss_priv *priv,
  363. enum icnss_smp2p_msg_id msg_id,
  364. enum smp2p_out_entry smp2p_entry)
  365. {
  366. unsigned int value = 0;
  367. int ret;
  368. if (IS_ERR(priv->smp2p_info[smp2p_entry].smem_state))
  369. return -EINVAL;
  370. /* No Need to check FW_DOWN for ICNSS_RESET_MSG */
  371. if (msg_id == ICNSS_RESET_MSG) {
  372. priv->smp2p_info[smp2p_entry].seq = 0;
  373. ret = qcom_smem_state_update_bits(
  374. priv->smp2p_info[smp2p_entry].smem_state,
  375. ICNSS_SMEM_VALUE_MASK,
  376. 0);
  377. if (ret)
  378. icnss_pr_err("Error in SMP2P sent. ret: %d, %s\n",
  379. ret, icnss_smp2p_str[smp2p_entry]);
  380. return ret;
  381. }
  382. if (test_bit(ICNSS_FW_DOWN, &priv->state))
  383. return -ENODEV;
  384. value |= priv->smp2p_info[smp2p_entry].seq++;
  385. value <<= ICNSS_SMEM_SEQ_NO_POS;
  386. value |= msg_id;
  387. icnss_pr_smp2p("Sending SMP2P value: 0x%X\n", value);
  388. if (msg_id == ICNSS_SOC_WAKE_REQ || msg_id == ICNSS_SOC_WAKE_REL)
  389. reinit_completion(&penv->smp2p_soc_wake_wait);
  390. ret = qcom_smem_state_update_bits(
  391. priv->smp2p_info[smp2p_entry].smem_state,
  392. ICNSS_SMEM_VALUE_MASK,
  393. value);
  394. if (ret) {
  395. icnss_pr_smp2p("Error in SMP2P send ret: %d, %s\n", ret,
  396. icnss_smp2p_str[smp2p_entry]);
  397. } else {
  398. if (msg_id == ICNSS_SOC_WAKE_REQ ||
  399. msg_id == ICNSS_SOC_WAKE_REL) {
  400. if (!wait_for_completion_timeout(
  401. &priv->smp2p_soc_wake_wait,
  402. msecs_to_jiffies(SMP2P_SOC_WAKE_TIMEOUT))) {
  403. icnss_pr_err("SMP2P Soc Wake timeout msg %d, %s\n", msg_id,
  404. icnss_smp2p_str[smp2p_entry]);
  405. if (!test_bit(ICNSS_FW_DOWN, &priv->state))
  406. ICNSS_ASSERT(0);
  407. }
  408. }
  409. }
  410. return ret;
  411. }
  412. static irqreturn_t fw_error_fatal_handler(int irq, void *ctx)
  413. {
  414. struct icnss_priv *priv = ctx;
  415. if (priv)
  416. priv->force_err_fatal = true;
  417. icnss_pr_err("Received force error fatal request from FW\n");
  418. return IRQ_HANDLED;
  419. }
  420. static irqreturn_t fw_crash_indication_handler(int irq, void *ctx)
  421. {
  422. struct icnss_priv *priv = ctx;
  423. struct icnss_uevent_fw_down_data fw_down_data = {0};
  424. icnss_pr_err("Received early crash indication from FW\n");
  425. if (priv) {
  426. set_bit(ICNSS_FW_DOWN, &priv->state);
  427. icnss_ignore_fw_timeout(true);
  428. if (test_bit(ICNSS_FW_READY, &priv->state)) {
  429. clear_bit(ICNSS_FW_READY, &priv->state);
  430. fw_down_data.crashed = true;
  431. icnss_call_driver_uevent(priv, ICNSS_UEVENT_FW_DOWN,
  432. &fw_down_data);
  433. }
  434. }
  435. icnss_driver_event_post(priv, ICNSS_DRIVER_EVENT_FW_EARLY_CRASH_IND,
  436. 0, NULL);
  437. return IRQ_HANDLED;
  438. }
  439. static void register_fw_error_notifications(struct device *dev)
  440. {
  441. struct icnss_priv *priv = dev_get_drvdata(dev);
  442. struct device_node *dev_node;
  443. int irq = 0, ret = 0;
  444. if (!priv)
  445. return;
  446. dev_node = of_find_node_by_name(NULL, "qcom,smp2p_map_wlan_1_in");
  447. if (!dev_node) {
  448. icnss_pr_err("Failed to get smp2p node for force-fatal-error\n");
  449. return;
  450. }
  451. icnss_pr_dbg("smp2p node->name=%s\n", dev_node->name);
  452. if (strcmp("qcom,smp2p_map_wlan_1_in", dev_node->name) == 0) {
  453. ret = irq = of_irq_get_byname(dev_node,
  454. "qcom,smp2p-force-fatal-error");
  455. if (ret < 0) {
  456. icnss_pr_err("Unable to get force-fatal-error irq %d\n",
  457. irq);
  458. return;
  459. }
  460. }
  461. ret = devm_request_threaded_irq(dev, irq, NULL, fw_error_fatal_handler,
  462. IRQF_ONESHOT | IRQF_TRIGGER_RISING,
  463. "wlanfw-err", priv);
  464. if (ret < 0) {
  465. icnss_pr_err("Unable to register for error fatal IRQ handler %d ret = %d",
  466. irq, ret);
  467. return;
  468. }
  469. icnss_pr_dbg("FW force error fatal handler registered irq = %d\n", irq);
  470. priv->fw_error_fatal_irq = irq;
  471. }
  472. static void register_early_crash_notifications(struct device *dev)
  473. {
  474. struct icnss_priv *priv = dev_get_drvdata(dev);
  475. struct device_node *dev_node;
  476. int irq = 0, ret = 0;
  477. if (!priv)
  478. return;
  479. dev_node = of_find_node_by_name(NULL, "qcom,smp2p_map_wlan_1_in");
  480. if (!dev_node) {
  481. icnss_pr_err("Failed to get smp2p node for early-crash-ind\n");
  482. return;
  483. }
  484. icnss_pr_dbg("smp2p node->name=%s\n", dev_node->name);
  485. if (strcmp("qcom,smp2p_map_wlan_1_in", dev_node->name) == 0) {
  486. ret = irq = of_irq_get_byname(dev_node,
  487. "qcom,smp2p-early-crash-ind");
  488. if (ret < 0) {
  489. icnss_pr_err("Unable to get early-crash-ind irq %d\n",
  490. irq);
  491. return;
  492. }
  493. }
  494. ret = devm_request_threaded_irq(dev, irq, NULL,
  495. fw_crash_indication_handler,
  496. IRQF_ONESHOT | IRQF_TRIGGER_RISING,
  497. "wlanfw-early-crash-ind", priv);
  498. if (ret < 0) {
  499. icnss_pr_err("Unable to register for early crash indication IRQ handler %d ret = %d",
  500. irq, ret);
  501. return;
  502. }
  503. icnss_pr_dbg("FW crash indication handler registered irq = %d\n", irq);
  504. priv->fw_early_crash_irq = irq;
  505. }
  506. static irqreturn_t fw_soc_wake_ack_handler(int irq, void *ctx)
  507. {
  508. struct icnss_priv *priv = ctx;
  509. if (priv)
  510. complete(&priv->smp2p_soc_wake_wait);
  511. return IRQ_HANDLED;
  512. }
  513. static void register_soc_wake_notif(struct device *dev)
  514. {
  515. struct icnss_priv *priv = dev_get_drvdata(dev);
  516. struct device_node *dev_node;
  517. int irq = 0, ret = 0;
  518. if (!priv)
  519. return;
  520. dev_node = of_find_node_by_name(NULL, "qcom,smp2p_map_wlan_2_in");
  521. if (!dev_node) {
  522. icnss_pr_err("Failed to get smp2p node for soc-wake-ack\n");
  523. return;
  524. }
  525. icnss_pr_dbg("smp2p node->name=%s\n", dev_node->name);
  526. if (strcmp("qcom,smp2p_map_wlan_2_in", dev_node->name) == 0) {
  527. ret = irq = of_irq_get_byname(dev_node,
  528. "qcom,smp2p-soc-wake-ack");
  529. if (ret < 0) {
  530. icnss_pr_err("Unable to get soc wake ack irq %d\n",
  531. irq);
  532. return;
  533. }
  534. }
  535. ret = devm_request_threaded_irq(dev, irq, NULL,
  536. fw_soc_wake_ack_handler,
  537. IRQF_ONESHOT | IRQF_TRIGGER_RISING |
  538. IRQF_TRIGGER_FALLING,
  539. "wlanfw-soc-wake-ack", priv);
  540. if (ret < 0) {
  541. icnss_pr_err("Unable to register for SOC Wake ACK IRQ handler %d ret = %d",
  542. irq, ret);
  543. return;
  544. }
  545. icnss_pr_dbg("FW SOC Wake ACK handler registered irq = %d\n", irq);
  546. priv->fw_soc_wake_ack_irq = irq;
  547. }
  548. int icnss_call_driver_uevent(struct icnss_priv *priv,
  549. enum icnss_uevent uevent, void *data)
  550. {
  551. struct icnss_uevent_data uevent_data;
  552. if (!priv->ops || !priv->ops->uevent)
  553. return 0;
  554. icnss_pr_dbg("Calling driver uevent state: 0x%lx, uevent: %d\n",
  555. priv->state, uevent);
  556. uevent_data.uevent = uevent;
  557. uevent_data.data = data;
  558. return priv->ops->uevent(&priv->pdev->dev, &uevent_data);
  559. }
  560. static int icnss_setup_dms_mac(struct icnss_priv *priv)
  561. {
  562. int i;
  563. int ret = 0;
  564. ret = icnss_qmi_get_dms_mac(priv);
  565. if (ret == 0 && priv->dms.mac_valid)
  566. goto qmi_send;
  567. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  568. * Thus assert on failure to get MAC from DMS even after retries
  569. */
  570. if (priv->use_nv_mac) {
  571. for (i = 0; i < ICNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  572. if (priv->dms.mac_valid)
  573. break;
  574. ret = icnss_qmi_get_dms_mac(priv);
  575. if (ret != -EAGAIN)
  576. break;
  577. msleep(ICNSS_DMS_QMI_CONNECTION_WAIT_MS);
  578. }
  579. if (!priv->dms.nv_mac_not_prov && !priv->dms.mac_valid) {
  580. icnss_pr_err("Unable to get MAC from DMS after retries\n");
  581. ICNSS_ASSERT(0);
  582. return -EINVAL;
  583. }
  584. }
  585. qmi_send:
  586. if (priv->dms.mac_valid)
  587. ret =
  588. icnss_wlfw_wlan_mac_req_send_sync(priv, priv->dms.mac,
  589. ARRAY_SIZE(priv->dms.mac));
  590. return ret;
  591. }
  592. static void icnss_get_smp2p_info(struct icnss_priv *priv,
  593. enum smp2p_out_entry smp2p_entry)
  594. {
  595. int retry = 0;
  596. int error;
  597. if (priv->smp2p_info[smp2p_entry].smem_state)
  598. return;
  599. retry:
  600. priv->smp2p_info[smp2p_entry].smem_state =
  601. qcom_smem_state_get(&priv->pdev->dev,
  602. icnss_smp2p_str[smp2p_entry],
  603. &priv->smp2p_info[smp2p_entry].smem_bit);
  604. if (IS_ERR(priv->smp2p_info[smp2p_entry].smem_state)) {
  605. if (retry++ < SMP2P_GET_MAX_RETRY) {
  606. error = PTR_ERR(priv->smp2p_info[smp2p_entry].smem_state);
  607. icnss_pr_err("Failed to get smem state, ret: %d Entry: %s",
  608. error, icnss_smp2p_str[smp2p_entry]);
  609. msleep(SMP2P_GET_RETRY_DELAY_MS);
  610. goto retry;
  611. }
  612. ICNSS_ASSERT(0);
  613. return;
  614. }
  615. icnss_pr_dbg("smem state, Entry: %s", icnss_smp2p_str[smp2p_entry]);
  616. }
  617. static int icnss_driver_event_server_arrive(struct icnss_priv *priv,
  618. void *data)
  619. {
  620. int ret = 0;
  621. bool ignore_assert = false;
  622. if (!priv)
  623. return -ENODEV;
  624. set_bit(ICNSS_WLFW_EXISTS, &priv->state);
  625. clear_bit(ICNSS_FW_DOWN, &priv->state);
  626. clear_bit(ICNSS_FW_READY, &priv->state);
  627. icnss_ignore_fw_timeout(false);
  628. if (test_bit(ICNSS_WLFW_CONNECTED, &priv->state)) {
  629. icnss_pr_err("QMI Server already in Connected State\n");
  630. ICNSS_ASSERT(0);
  631. }
  632. ret = icnss_connect_to_fw_server(priv, data);
  633. if (ret)
  634. goto fail;
  635. set_bit(ICNSS_WLFW_CONNECTED, &priv->state);
  636. ret = wlfw_ind_register_send_sync_msg(priv);
  637. if (ret < 0) {
  638. if (ret == -EALREADY) {
  639. ret = 0;
  640. goto qmi_registered;
  641. }
  642. ignore_assert = true;
  643. goto fail;
  644. }
  645. if (priv->device_id == WCN6750_DEVICE_ID) {
  646. ret = wlfw_host_cap_send_sync(priv);
  647. if (ret < 0)
  648. goto fail;
  649. }
  650. if (priv->device_id == ADRASTEA_DEVICE_ID) {
  651. if (!priv->msa_va) {
  652. icnss_pr_err("Invalid MSA address\n");
  653. ret = -EINVAL;
  654. goto fail;
  655. }
  656. ret = wlfw_msa_mem_info_send_sync_msg(priv);
  657. if (ret < 0) {
  658. ignore_assert = true;
  659. goto fail;
  660. }
  661. ret = wlfw_msa_ready_send_sync_msg(priv);
  662. if (ret < 0) {
  663. ignore_assert = true;
  664. goto fail;
  665. }
  666. }
  667. ret = wlfw_cap_send_sync_msg(priv);
  668. if (ret < 0) {
  669. ignore_assert = true;
  670. goto fail;
  671. }
  672. ret = icnss_hw_power_on(priv);
  673. if (ret)
  674. goto fail;
  675. if (priv->device_id == WCN6750_DEVICE_ID) {
  676. ret = wlfw_device_info_send_msg(priv);
  677. if (ret < 0) {
  678. ignore_assert = true;
  679. goto device_info_failure;
  680. }
  681. priv->mem_base_va = devm_ioremap(&priv->pdev->dev,
  682. priv->mem_base_pa,
  683. priv->mem_base_size);
  684. if (!priv->mem_base_va) {
  685. icnss_pr_err("Ioremap failed for bar address\n");
  686. goto device_info_failure;
  687. }
  688. icnss_pr_dbg("Non-Secured Bar Address pa: %pa, va: 0x%pK\n",
  689. &priv->mem_base_pa,
  690. priv->mem_base_va);
  691. if (priv->mhi_state_info_pa)
  692. priv->mhi_state_info_va = devm_ioremap(&priv->pdev->dev,
  693. priv->mhi_state_info_pa,
  694. PAGE_SIZE);
  695. if (!priv->mhi_state_info_va)
  696. icnss_pr_err("Ioremap failed for MHI info address\n");
  697. icnss_pr_dbg("MHI state info Address pa: %pa, va: 0x%pK\n",
  698. &priv->mhi_state_info_pa,
  699. priv->mhi_state_info_va);
  700. }
  701. if (priv->bdf_download_support) {
  702. icnss_wlfw_bdf_dnld_send_sync(priv, ICNSS_BDF_REGDB);
  703. ret = icnss_wlfw_bdf_dnld_send_sync(priv,
  704. priv->ctrl_params.bdf_type);
  705. if (ret < 0)
  706. goto device_info_failure;
  707. }
  708. if (priv->device_id == WCN6750_DEVICE_ID) {
  709. if (!priv->fw_soc_wake_ack_irq)
  710. register_soc_wake_notif(&priv->pdev->dev);
  711. icnss_get_smp2p_info(priv, ICNSS_SMP2P_OUT_POWER_SAVE);
  712. icnss_get_smp2p_info(priv, ICNSS_SMP2P_OUT_SOC_WAKE);
  713. icnss_get_smp2p_info(priv, ICNSS_SMP2P_OUT_EP_POWER_SAVE);
  714. }
  715. if (priv->device_id == ADRASTEA_DEVICE_ID) {
  716. if (priv->bdf_download_support) {
  717. ret = wlfw_cal_report_req(priv);
  718. if (ret < 0)
  719. goto device_info_failure;
  720. }
  721. wlfw_dynamic_feature_mask_send_sync_msg(priv,
  722. dynamic_feature_mask);
  723. }
  724. if (!priv->fw_error_fatal_irq)
  725. register_fw_error_notifications(&priv->pdev->dev);
  726. if (!priv->fw_early_crash_irq)
  727. register_early_crash_notifications(&priv->pdev->dev);
  728. return ret;
  729. device_info_failure:
  730. icnss_hw_power_off(priv);
  731. fail:
  732. ICNSS_ASSERT(ignore_assert);
  733. qmi_registered:
  734. return ret;
  735. }
  736. static int icnss_driver_event_server_exit(struct icnss_priv *priv)
  737. {
  738. if (!priv)
  739. return -ENODEV;
  740. icnss_pr_info("WLAN FW Service Disconnected: 0x%lx\n", priv->state);
  741. icnss_clear_server(priv);
  742. return 0;
  743. }
  744. static int icnss_call_driver_probe(struct icnss_priv *priv)
  745. {
  746. int ret = 0;
  747. int probe_cnt = 0;
  748. if (!priv->ops || !priv->ops->probe)
  749. return 0;
  750. if (test_bit(ICNSS_DRIVER_PROBED, &priv->state))
  751. return -EINVAL;
  752. icnss_pr_dbg("Calling driver probe state: 0x%lx\n", priv->state);
  753. icnss_hw_power_on(priv);
  754. icnss_block_shutdown(true);
  755. while (probe_cnt < ICNSS_MAX_PROBE_CNT) {
  756. ret = priv->ops->probe(&priv->pdev->dev);
  757. probe_cnt++;
  758. if (ret != -EPROBE_DEFER)
  759. break;
  760. }
  761. if (ret < 0) {
  762. icnss_pr_err("Driver probe failed: %d, state: 0x%lx, probe_cnt: %d\n",
  763. ret, priv->state, probe_cnt);
  764. icnss_block_shutdown(false);
  765. goto out;
  766. }
  767. icnss_block_shutdown(false);
  768. set_bit(ICNSS_DRIVER_PROBED, &priv->state);
  769. return 0;
  770. out:
  771. icnss_hw_power_off(priv);
  772. return ret;
  773. }
  774. static int icnss_call_driver_shutdown(struct icnss_priv *priv)
  775. {
  776. if (!test_bit(ICNSS_DRIVER_PROBED, &priv->state))
  777. goto out;
  778. if (!priv->ops || !priv->ops->shutdown)
  779. goto out;
  780. if (test_bit(ICNSS_SHUTDOWN_DONE, &priv->state))
  781. goto out;
  782. icnss_pr_dbg("Calling driver shutdown state: 0x%lx\n", priv->state);
  783. priv->ops->shutdown(&priv->pdev->dev);
  784. set_bit(ICNSS_SHUTDOWN_DONE, &priv->state);
  785. out:
  786. return 0;
  787. }
  788. static int icnss_pd_restart_complete(struct icnss_priv *priv)
  789. {
  790. int ret = 0;
  791. icnss_pm_relax(priv);
  792. icnss_call_driver_shutdown(priv);
  793. clear_bit(ICNSS_PDR, &priv->state);
  794. clear_bit(ICNSS_REJUVENATE, &priv->state);
  795. clear_bit(ICNSS_PD_RESTART, &priv->state);
  796. priv->early_crash_ind = false;
  797. priv->is_ssr = false;
  798. if (!priv->ops || !priv->ops->reinit)
  799. goto out;
  800. if (test_bit(ICNSS_FW_DOWN, &priv->state)) {
  801. icnss_pr_err("FW is in bad state, state: 0x%lx\n",
  802. priv->state);
  803. goto out;
  804. }
  805. if (!test_bit(ICNSS_DRIVER_PROBED, &priv->state))
  806. goto call_probe;
  807. icnss_pr_dbg("Calling driver reinit state: 0x%lx\n", priv->state);
  808. icnss_hw_power_on(priv);
  809. icnss_block_shutdown(true);
  810. ret = priv->ops->reinit(&priv->pdev->dev);
  811. if (ret < 0) {
  812. icnss_fatal_err("Driver reinit failed: %d, state: 0x%lx\n",
  813. ret, priv->state);
  814. if (!priv->allow_recursive_recovery)
  815. ICNSS_ASSERT(false);
  816. icnss_block_shutdown(false);
  817. goto out_power_off;
  818. }
  819. icnss_block_shutdown(false);
  820. clear_bit(ICNSS_SHUTDOWN_DONE, &priv->state);
  821. return 0;
  822. call_probe:
  823. return icnss_call_driver_probe(priv);
  824. out_power_off:
  825. icnss_hw_power_off(priv);
  826. out:
  827. return ret;
  828. }
  829. static int icnss_driver_event_fw_ready_ind(struct icnss_priv *priv, void *data)
  830. {
  831. int ret = 0;
  832. if (!priv)
  833. return -ENODEV;
  834. set_bit(ICNSS_FW_READY, &priv->state);
  835. clear_bit(ICNSS_MODE_ON, &priv->state);
  836. atomic_set(&priv->soc_wake_ref_count, 0);
  837. if (priv->device_id == WCN6750_DEVICE_ID)
  838. icnss_free_qdss_mem(priv);
  839. icnss_pr_info("WLAN FW is ready: 0x%lx\n", priv->state);
  840. icnss_hw_power_off(priv);
  841. if (!priv->pdev) {
  842. icnss_pr_err("Device is not ready\n");
  843. ret = -ENODEV;
  844. goto out;
  845. }
  846. if (test_bit(ICNSS_PD_RESTART, &priv->state)) {
  847. ret = icnss_pd_restart_complete(priv);
  848. } else {
  849. if (priv->wpss_supported)
  850. icnss_setup_dms_mac(priv);
  851. ret = icnss_call_driver_probe(priv);
  852. }
  853. icnss_vreg_unvote(priv);
  854. out:
  855. return ret;
  856. }
  857. static int icnss_driver_event_fw_init_done(struct icnss_priv *priv, void *data)
  858. {
  859. int ret = 0;
  860. if (!priv)
  861. return -ENODEV;
  862. icnss_pr_info("WLAN FW Initialization done: 0x%lx\n", priv->state);
  863. if (icnss_wlfw_qdss_dnld_send_sync(priv))
  864. icnss_pr_info("Failed to download qdss configuration file");
  865. if (test_bit(ICNSS_COLD_BOOT_CAL, &priv->state))
  866. ret = wlfw_wlan_mode_send_sync_msg(priv,
  867. (enum wlfw_driver_mode_enum_v01)ICNSS_CALIBRATION);
  868. else
  869. icnss_driver_event_fw_ready_ind(priv, NULL);
  870. return ret;
  871. }
  872. int icnss_alloc_qdss_mem(struct icnss_priv *priv)
  873. {
  874. struct platform_device *pdev = priv->pdev;
  875. struct icnss_fw_mem *qdss_mem = priv->qdss_mem;
  876. int i, j;
  877. for (i = 0; i < priv->qdss_mem_seg_len; i++) {
  878. if (!qdss_mem[i].va && qdss_mem[i].size) {
  879. qdss_mem[i].va =
  880. dma_alloc_coherent(&pdev->dev,
  881. qdss_mem[i].size,
  882. &qdss_mem[i].pa,
  883. GFP_KERNEL);
  884. if (!qdss_mem[i].va) {
  885. icnss_pr_err("Failed to allocate QDSS memory for FW, size: 0x%zx, type: %u, chuck-ID: %d\n",
  886. qdss_mem[i].size,
  887. qdss_mem[i].type, i);
  888. break;
  889. }
  890. }
  891. }
  892. /* Best-effort allocation for QDSS trace */
  893. if (i < priv->qdss_mem_seg_len) {
  894. for (j = i; j < priv->qdss_mem_seg_len; j++) {
  895. qdss_mem[j].type = 0;
  896. qdss_mem[j].size = 0;
  897. }
  898. priv->qdss_mem_seg_len = i;
  899. }
  900. return 0;
  901. }
  902. void icnss_free_qdss_mem(struct icnss_priv *priv)
  903. {
  904. struct platform_device *pdev = priv->pdev;
  905. struct icnss_fw_mem *qdss_mem = priv->qdss_mem;
  906. int i;
  907. for (i = 0; i < priv->qdss_mem_seg_len; i++) {
  908. if (qdss_mem[i].va && qdss_mem[i].size) {
  909. icnss_pr_dbg("Freeing memory for QDSS: pa: %pa, size: 0x%zx, type: %u\n",
  910. &qdss_mem[i].pa, qdss_mem[i].size,
  911. qdss_mem[i].type);
  912. dma_free_coherent(&pdev->dev,
  913. qdss_mem[i].size, qdss_mem[i].va,
  914. qdss_mem[i].pa);
  915. qdss_mem[i].va = NULL;
  916. qdss_mem[i].pa = 0;
  917. qdss_mem[i].size = 0;
  918. qdss_mem[i].type = 0;
  919. }
  920. }
  921. priv->qdss_mem_seg_len = 0;
  922. }
  923. static int icnss_qdss_trace_req_mem_hdlr(struct icnss_priv *priv)
  924. {
  925. int ret = 0;
  926. ret = icnss_alloc_qdss_mem(priv);
  927. if (ret < 0)
  928. return ret;
  929. return wlfw_qdss_trace_mem_info_send_sync(priv);
  930. }
  931. static void *icnss_qdss_trace_pa_to_va(struct icnss_priv *priv,
  932. u64 pa, u32 size, int *seg_id)
  933. {
  934. int i = 0;
  935. struct icnss_fw_mem *qdss_mem = priv->qdss_mem;
  936. u64 offset = 0;
  937. void *va = NULL;
  938. u64 local_pa;
  939. u32 local_size;
  940. for (i = 0; i < priv->qdss_mem_seg_len; i++) {
  941. local_pa = (u64)qdss_mem[i].pa;
  942. local_size = (u32)qdss_mem[i].size;
  943. if (pa == local_pa && size <= local_size) {
  944. va = qdss_mem[i].va;
  945. break;
  946. }
  947. if (pa > local_pa &&
  948. pa < local_pa + local_size &&
  949. pa + size <= local_pa + local_size) {
  950. offset = pa - local_pa;
  951. va = qdss_mem[i].va + offset;
  952. break;
  953. }
  954. }
  955. *seg_id = i;
  956. return va;
  957. }
  958. static int icnss_qdss_trace_save_hdlr(struct icnss_priv *priv,
  959. void *data)
  960. {
  961. struct icnss_qmi_event_qdss_trace_save_data *event_data = data;
  962. struct icnss_fw_mem *qdss_mem = priv->qdss_mem;
  963. int ret = 0;
  964. int i;
  965. void *va = NULL;
  966. u64 pa;
  967. u32 size;
  968. int seg_id = 0;
  969. if (!priv->qdss_mem_seg_len) {
  970. icnss_pr_err("Memory for QDSS trace is not available\n");
  971. return -ENOMEM;
  972. }
  973. if (event_data->mem_seg_len == 0) {
  974. for (i = 0; i < priv->qdss_mem_seg_len; i++) {
  975. ret = icnss_genl_send_msg(qdss_mem[i].va,
  976. ICNSS_GENL_MSG_TYPE_QDSS,
  977. event_data->file_name,
  978. qdss_mem[i].size);
  979. if (ret < 0) {
  980. icnss_pr_err("Fail to save QDSS data: %d\n",
  981. ret);
  982. break;
  983. }
  984. }
  985. } else {
  986. for (i = 0; i < event_data->mem_seg_len; i++) {
  987. pa = event_data->mem_seg[i].addr;
  988. size = event_data->mem_seg[i].size;
  989. va = icnss_qdss_trace_pa_to_va(priv, pa,
  990. size, &seg_id);
  991. if (!va) {
  992. icnss_pr_err("Fail to find matching va for pa %pa\n",
  993. &pa);
  994. ret = -EINVAL;
  995. break;
  996. }
  997. ret = icnss_genl_send_msg(va, ICNSS_GENL_MSG_TYPE_QDSS,
  998. event_data->file_name, size);
  999. if (ret < 0) {
  1000. icnss_pr_err("Fail to save QDSS data: %d\n",
  1001. ret);
  1002. break;
  1003. }
  1004. }
  1005. }
  1006. kfree(data);
  1007. return ret;
  1008. }
  1009. static inline int icnss_atomic_dec_if_greater_one(atomic_t *v)
  1010. {
  1011. int dec, c = atomic_read(v);
  1012. do {
  1013. dec = c - 1;
  1014. if (unlikely(dec < 1))
  1015. break;
  1016. } while (!atomic_try_cmpxchg(v, &c, dec));
  1017. return dec;
  1018. }
  1019. static int icnss_qdss_trace_req_data_hdlr(struct icnss_priv *priv,
  1020. void *data)
  1021. {
  1022. int ret = 0;
  1023. struct icnss_qmi_event_qdss_trace_save_data *event_data = data;
  1024. if (!priv)
  1025. return -ENODEV;
  1026. if (!data)
  1027. return -EINVAL;
  1028. ret = icnss_wlfw_qdss_data_send_sync(priv, event_data->file_name,
  1029. event_data->total_size);
  1030. kfree(data);
  1031. return ret;
  1032. }
  1033. static int icnss_event_soc_wake_request(struct icnss_priv *priv, void *data)
  1034. {
  1035. int ret = 0;
  1036. if (!priv)
  1037. return -ENODEV;
  1038. if (atomic_inc_not_zero(&priv->soc_wake_ref_count)) {
  1039. icnss_pr_soc_wake("SOC awake after posting work, Ref count: %d",
  1040. atomic_read(&priv->soc_wake_ref_count));
  1041. return 0;
  1042. }
  1043. ret = icnss_send_smp2p(priv, ICNSS_SOC_WAKE_REQ,
  1044. ICNSS_SMP2P_OUT_SOC_WAKE);
  1045. if (!ret)
  1046. atomic_inc(&priv->soc_wake_ref_count);
  1047. return ret;
  1048. }
  1049. static int icnss_event_soc_wake_release(struct icnss_priv *priv, void *data)
  1050. {
  1051. int ret = 0;
  1052. if (!priv)
  1053. return -ENODEV;
  1054. if (atomic_dec_if_positive(&priv->soc_wake_ref_count)) {
  1055. icnss_pr_soc_wake("Wake release not called. Ref count: %d",
  1056. priv->soc_wake_ref_count);
  1057. return 0;
  1058. }
  1059. ret = icnss_send_smp2p(priv, ICNSS_SOC_WAKE_REL,
  1060. ICNSS_SMP2P_OUT_SOC_WAKE);
  1061. return ret;
  1062. }
  1063. static int icnss_driver_event_register_driver(struct icnss_priv *priv,
  1064. void *data)
  1065. {
  1066. int ret = 0;
  1067. int probe_cnt = 0;
  1068. if (priv->ops)
  1069. return -EEXIST;
  1070. priv->ops = data;
  1071. if (test_bit(SKIP_QMI, &priv->ctrl_params.quirks))
  1072. set_bit(ICNSS_FW_READY, &priv->state);
  1073. if (test_bit(ICNSS_FW_DOWN, &priv->state)) {
  1074. icnss_pr_err("FW is in bad state, state: 0x%lx\n",
  1075. priv->state);
  1076. return -ENODEV;
  1077. }
  1078. if (!test_bit(ICNSS_FW_READY, &priv->state)) {
  1079. icnss_pr_dbg("FW is not ready yet, state: 0x%lx\n",
  1080. priv->state);
  1081. goto out;
  1082. }
  1083. ret = icnss_hw_power_on(priv);
  1084. if (ret)
  1085. goto out;
  1086. icnss_block_shutdown(true);
  1087. while (probe_cnt < ICNSS_MAX_PROBE_CNT) {
  1088. ret = priv->ops->probe(&priv->pdev->dev);
  1089. probe_cnt++;
  1090. if (ret != -EPROBE_DEFER)
  1091. break;
  1092. }
  1093. if (ret) {
  1094. icnss_pr_err("Driver probe failed: %d, state: 0x%lx, probe_cnt: %d\n",
  1095. ret, priv->state, probe_cnt);
  1096. icnss_block_shutdown(false);
  1097. goto power_off;
  1098. }
  1099. icnss_block_shutdown(false);
  1100. set_bit(ICNSS_DRIVER_PROBED, &priv->state);
  1101. return 0;
  1102. power_off:
  1103. icnss_hw_power_off(priv);
  1104. out:
  1105. return ret;
  1106. }
  1107. static int icnss_driver_event_unregister_driver(struct icnss_priv *priv,
  1108. void *data)
  1109. {
  1110. if (!test_bit(ICNSS_DRIVER_PROBED, &priv->state)) {
  1111. priv->ops = NULL;
  1112. goto out;
  1113. }
  1114. set_bit(ICNSS_DRIVER_UNLOADING, &priv->state);
  1115. icnss_block_shutdown(true);
  1116. if (priv->ops)
  1117. priv->ops->remove(&priv->pdev->dev);
  1118. icnss_block_shutdown(false);
  1119. clear_bit(ICNSS_DRIVER_UNLOADING, &priv->state);
  1120. clear_bit(ICNSS_DRIVER_PROBED, &priv->state);
  1121. priv->ops = NULL;
  1122. icnss_hw_power_off(priv);
  1123. out:
  1124. return 0;
  1125. }
  1126. static int icnss_fw_crashed(struct icnss_priv *priv,
  1127. struct icnss_event_pd_service_down_data *event_data)
  1128. {
  1129. icnss_pr_dbg("FW crashed, state: 0x%lx\n", priv->state);
  1130. set_bit(ICNSS_PD_RESTART, &priv->state);
  1131. clear_bit(ICNSS_FW_READY, &priv->state);
  1132. icnss_pm_stay_awake(priv);
  1133. if (test_bit(ICNSS_DRIVER_PROBED, &priv->state))
  1134. icnss_call_driver_uevent(priv, ICNSS_UEVENT_FW_CRASHED, NULL);
  1135. if (event_data && event_data->fw_rejuvenate)
  1136. wlfw_rejuvenate_ack_send_sync_msg(priv);
  1137. return 0;
  1138. }
  1139. int icnss_update_hang_event_data(struct icnss_priv *priv,
  1140. struct icnss_uevent_hang_data *hang_data)
  1141. {
  1142. if (!priv->hang_event_data_va)
  1143. return -EINVAL;
  1144. priv->hang_event_data = kmemdup(priv->hang_event_data_va,
  1145. priv->hang_event_data_len,
  1146. GFP_ATOMIC);
  1147. if (!priv->hang_event_data)
  1148. return -ENOMEM;
  1149. // Update the hang event params
  1150. hang_data->hang_event_data = priv->hang_event_data;
  1151. hang_data->hang_event_data_len = priv->hang_event_data_len;
  1152. return 0;
  1153. }
  1154. int icnss_send_hang_event_data(struct icnss_priv *priv)
  1155. {
  1156. struct icnss_uevent_hang_data hang_data = {0};
  1157. int ret = 0xFF;
  1158. if (priv->early_crash_ind) {
  1159. ret = icnss_update_hang_event_data(priv, &hang_data);
  1160. if (ret)
  1161. icnss_pr_err("Unable to allocate memory for Hang event data\n");
  1162. }
  1163. icnss_call_driver_uevent(priv, ICNSS_UEVENT_HANG_DATA,
  1164. &hang_data);
  1165. if (!ret) {
  1166. kfree(priv->hang_event_data);
  1167. priv->hang_event_data = NULL;
  1168. }
  1169. return 0;
  1170. }
  1171. static int icnss_driver_event_pd_service_down(struct icnss_priv *priv,
  1172. void *data)
  1173. {
  1174. struct icnss_event_pd_service_down_data *event_data = data;
  1175. if (!test_bit(ICNSS_WLFW_EXISTS, &priv->state)) {
  1176. icnss_ignore_fw_timeout(false);
  1177. goto out;
  1178. }
  1179. if (priv->force_err_fatal)
  1180. ICNSS_ASSERT(0);
  1181. if (priv->device_id == WCN6750_DEVICE_ID) {
  1182. icnss_send_smp2p(priv, ICNSS_RESET_MSG,
  1183. ICNSS_SMP2P_OUT_POWER_SAVE);
  1184. icnss_send_smp2p(priv, ICNSS_RESET_MSG,
  1185. ICNSS_SMP2P_OUT_SOC_WAKE);
  1186. icnss_send_smp2p(priv, ICNSS_RESET_MSG,
  1187. ICNSS_SMP2P_OUT_EP_POWER_SAVE);
  1188. }
  1189. icnss_send_hang_event_data(priv);
  1190. if (priv->early_crash_ind) {
  1191. icnss_pr_dbg("PD Down ignored as early indication is processed: %d, state: 0x%lx\n",
  1192. event_data->crashed, priv->state);
  1193. goto out;
  1194. }
  1195. if (test_bit(ICNSS_PD_RESTART, &priv->state) && event_data->crashed) {
  1196. icnss_fatal_err("PD Down while recovery inprogress, crashed: %d, state: 0x%lx\n",
  1197. event_data->crashed, priv->state);
  1198. if (!priv->allow_recursive_recovery)
  1199. ICNSS_ASSERT(0);
  1200. goto out;
  1201. }
  1202. if (!test_bit(ICNSS_PD_RESTART, &priv->state))
  1203. icnss_fw_crashed(priv, event_data);
  1204. out:
  1205. kfree(data);
  1206. return 0;
  1207. }
  1208. static int icnss_driver_event_early_crash_ind(struct icnss_priv *priv,
  1209. void *data)
  1210. {
  1211. if (!test_bit(ICNSS_WLFW_EXISTS, &priv->state)) {
  1212. icnss_ignore_fw_timeout(false);
  1213. goto out;
  1214. }
  1215. priv->early_crash_ind = true;
  1216. icnss_fw_crashed(priv, NULL);
  1217. out:
  1218. kfree(data);
  1219. return 0;
  1220. }
  1221. static int icnss_driver_event_idle_shutdown(struct icnss_priv *priv,
  1222. void *data)
  1223. {
  1224. int ret = 0;
  1225. if (!priv->ops || !priv->ops->idle_shutdown)
  1226. return 0;
  1227. if (priv->is_ssr || test_bit(ICNSS_PDR, &priv->state) ||
  1228. test_bit(ICNSS_REJUVENATE, &priv->state)) {
  1229. icnss_pr_err("SSR/PDR is already in-progress during idle shutdown callback\n");
  1230. ret = -EBUSY;
  1231. } else {
  1232. icnss_pr_dbg("Calling driver idle shutdown, state: 0x%lx\n",
  1233. priv->state);
  1234. icnss_block_shutdown(true);
  1235. ret = priv->ops->idle_shutdown(&priv->pdev->dev);
  1236. icnss_block_shutdown(false);
  1237. }
  1238. return ret;
  1239. }
  1240. static int icnss_driver_event_idle_restart(struct icnss_priv *priv,
  1241. void *data)
  1242. {
  1243. int ret = 0;
  1244. if (!priv->ops || !priv->ops->idle_restart)
  1245. return 0;
  1246. if (priv->is_ssr || test_bit(ICNSS_PDR, &priv->state) ||
  1247. test_bit(ICNSS_REJUVENATE, &priv->state)) {
  1248. icnss_pr_err("SSR/PDR is already in-progress during idle restart callback\n");
  1249. ret = -EBUSY;
  1250. } else {
  1251. icnss_pr_dbg("Calling driver idle restart, state: 0x%lx\n",
  1252. priv->state);
  1253. icnss_block_shutdown(true);
  1254. ret = priv->ops->idle_restart(&priv->pdev->dev);
  1255. icnss_block_shutdown(false);
  1256. }
  1257. return ret;
  1258. }
  1259. static int icnss_qdss_trace_free_hdlr(struct icnss_priv *priv)
  1260. {
  1261. icnss_free_qdss_mem(priv);
  1262. return 0;
  1263. }
  1264. static int icnss_m3_dump_upload_req_hdlr(struct icnss_priv *priv,
  1265. void *data)
  1266. {
  1267. struct icnss_m3_upload_segments_req_data *event_data = data;
  1268. struct qcom_dump_segment segment;
  1269. int i, status = 0, ret = 0;
  1270. struct list_head head;
  1271. if (!dump_enabled()) {
  1272. icnss_pr_info("Dump collection is not enabled\n");
  1273. return ret;
  1274. }
  1275. if (IS_ERR_OR_NULL(priv->m3_dump_phyareg) ||
  1276. IS_ERR_OR_NULL(priv->m3_dump_phydbg) ||
  1277. IS_ERR_OR_NULL(priv->m3_dump_wmac0reg) ||
  1278. IS_ERR_OR_NULL(priv->m3_dump_wcssdbg) ||
  1279. IS_ERR_OR_NULL(priv->m3_dump_phyapdmem))
  1280. return ret;
  1281. INIT_LIST_HEAD(&head);
  1282. for (i = 0; i < event_data->no_of_valid_segments; i++) {
  1283. memset(&segment, 0, sizeof(segment));
  1284. segment.va = devm_ioremap(&priv->pdev->dev,
  1285. event_data->m3_segment[i].addr,
  1286. event_data->m3_segment[i].size);
  1287. if (!segment.va) {
  1288. icnss_pr_err("Failed to ioremap M3 Dump region");
  1289. ret = -ENOMEM;
  1290. goto send_resp;
  1291. }
  1292. segment.size = event_data->m3_segment[i].size;
  1293. list_add(&segment.node, &head);
  1294. icnss_pr_dbg("Started Dump colletcion for %s segment",
  1295. event_data->m3_segment[i].name);
  1296. switch (event_data->m3_segment[i].type) {
  1297. case QMI_M3_SEGMENT_PHYAREG_V01:
  1298. ret = qcom_dump(&head, priv->m3_dump_phyareg->dev);
  1299. break;
  1300. case QMI_M3_SEGMENT_PHYDBG_V01:
  1301. ret = qcom_dump(&head, priv->m3_dump_phydbg->dev);
  1302. break;
  1303. case QMI_M3_SEGMENT_WMAC0_REG_V01:
  1304. ret = qcom_dump(&head, priv->m3_dump_wmac0reg->dev);
  1305. break;
  1306. case QMI_M3_SEGMENT_WCSSDBG_V01:
  1307. ret = qcom_dump(&head, priv->m3_dump_wcssdbg->dev);
  1308. break;
  1309. case QMI_M3_SEGMENT_PHYAPDMEM_V01:
  1310. ret = qcom_dump(&head, priv->m3_dump_phyapdmem->dev);
  1311. break;
  1312. default:
  1313. icnss_pr_err("Invalid Segment type: %d",
  1314. event_data->m3_segment[i].type);
  1315. }
  1316. if (ret) {
  1317. status = ret;
  1318. icnss_pr_err("Failed to dump m3 %s segment, err = %d\n",
  1319. event_data->m3_segment[i].name, ret);
  1320. }
  1321. list_del(&segment.node);
  1322. }
  1323. send_resp:
  1324. icnss_wlfw_m3_dump_upload_done_send_sync(priv, event_data->pdev_id,
  1325. status);
  1326. return ret;
  1327. }
  1328. static int icnss_subsys_restart_level(struct icnss_priv *priv, void *data)
  1329. {
  1330. int ret = 0;
  1331. struct icnss_subsys_restart_level_data *event_data = data;
  1332. if (!priv)
  1333. return -ENODEV;
  1334. if (!data)
  1335. return -EINVAL;
  1336. ret = wlfw_subsys_restart_level_msg(priv, event_data->restart_level);
  1337. kfree(data);
  1338. return ret;
  1339. }
  1340. static void icnss_driver_event_work(struct work_struct *work)
  1341. {
  1342. struct icnss_priv *priv =
  1343. container_of(work, struct icnss_priv, event_work);
  1344. struct icnss_driver_event *event;
  1345. unsigned long flags;
  1346. int ret;
  1347. icnss_pm_stay_awake(priv);
  1348. spin_lock_irqsave(&priv->event_lock, flags);
  1349. while (!list_empty(&priv->event_list)) {
  1350. event = list_first_entry(&priv->event_list,
  1351. struct icnss_driver_event, list);
  1352. list_del(&event->list);
  1353. spin_unlock_irqrestore(&priv->event_lock, flags);
  1354. icnss_pr_dbg("Processing event: %s%s(%d), state: 0x%lx\n",
  1355. icnss_driver_event_to_str(event->type),
  1356. event->sync ? "-sync" : "", event->type,
  1357. priv->state);
  1358. switch (event->type) {
  1359. case ICNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1360. ret = icnss_driver_event_server_arrive(priv,
  1361. event->data);
  1362. break;
  1363. case ICNSS_DRIVER_EVENT_SERVER_EXIT:
  1364. ret = icnss_driver_event_server_exit(priv);
  1365. break;
  1366. case ICNSS_DRIVER_EVENT_FW_READY_IND:
  1367. ret = icnss_driver_event_fw_ready_ind(priv,
  1368. event->data);
  1369. break;
  1370. case ICNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1371. ret = icnss_driver_event_register_driver(priv,
  1372. event->data);
  1373. break;
  1374. case ICNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1375. ret = icnss_driver_event_unregister_driver(priv,
  1376. event->data);
  1377. break;
  1378. case ICNSS_DRIVER_EVENT_PD_SERVICE_DOWN:
  1379. ret = icnss_driver_event_pd_service_down(priv,
  1380. event->data);
  1381. break;
  1382. case ICNSS_DRIVER_EVENT_FW_EARLY_CRASH_IND:
  1383. ret = icnss_driver_event_early_crash_ind(priv,
  1384. event->data);
  1385. break;
  1386. case ICNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1387. ret = icnss_driver_event_idle_shutdown(priv,
  1388. event->data);
  1389. break;
  1390. case ICNSS_DRIVER_EVENT_IDLE_RESTART:
  1391. ret = icnss_driver_event_idle_restart(priv,
  1392. event->data);
  1393. break;
  1394. case ICNSS_DRIVER_EVENT_FW_INIT_DONE_IND:
  1395. ret = icnss_driver_event_fw_init_done(priv,
  1396. event->data);
  1397. break;
  1398. case ICNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1399. ret = icnss_qdss_trace_req_mem_hdlr(priv);
  1400. break;
  1401. case ICNSS_DRIVER_EVENT_QDSS_TRACE_SAVE:
  1402. ret = icnss_qdss_trace_save_hdlr(priv,
  1403. event->data);
  1404. break;
  1405. case ICNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1406. ret = icnss_qdss_trace_free_hdlr(priv);
  1407. break;
  1408. case ICNSS_DRIVER_EVENT_M3_DUMP_UPLOAD_REQ:
  1409. ret = icnss_m3_dump_upload_req_hdlr(priv, event->data);
  1410. break;
  1411. case ICNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1412. ret = icnss_qdss_trace_req_data_hdlr(priv,
  1413. event->data);
  1414. break;
  1415. case ICNSS_DRIVER_EVENT_SUBSYS_RESTART_LEVEL:
  1416. ret = icnss_subsys_restart_level(priv, event->data);
  1417. break;
  1418. default:
  1419. icnss_pr_err("Invalid Event type: %d", event->type);
  1420. kfree(event);
  1421. continue;
  1422. }
  1423. priv->stats.events[event->type].processed++;
  1424. icnss_pr_dbg("Event Processed: %s%s(%d), ret: %d, state: 0x%lx\n",
  1425. icnss_driver_event_to_str(event->type),
  1426. event->sync ? "-sync" : "", event->type, ret,
  1427. priv->state);
  1428. spin_lock_irqsave(&priv->event_lock, flags);
  1429. if (event->sync) {
  1430. event->ret = ret;
  1431. complete(&event->complete);
  1432. continue;
  1433. }
  1434. spin_unlock_irqrestore(&priv->event_lock, flags);
  1435. kfree(event);
  1436. spin_lock_irqsave(&priv->event_lock, flags);
  1437. }
  1438. spin_unlock_irqrestore(&priv->event_lock, flags);
  1439. icnss_pm_relax(priv);
  1440. }
  1441. static void icnss_soc_wake_msg_work(struct work_struct *work)
  1442. {
  1443. struct icnss_priv *priv =
  1444. container_of(work, struct icnss_priv, soc_wake_msg_work);
  1445. struct icnss_soc_wake_event *event;
  1446. unsigned long flags;
  1447. int ret;
  1448. icnss_pm_stay_awake(priv);
  1449. spin_lock_irqsave(&priv->soc_wake_msg_lock, flags);
  1450. while (!list_empty(&priv->soc_wake_msg_list)) {
  1451. event = list_first_entry(&priv->soc_wake_msg_list,
  1452. struct icnss_soc_wake_event, list);
  1453. list_del(&event->list);
  1454. spin_unlock_irqrestore(&priv->soc_wake_msg_lock, flags);
  1455. icnss_pr_soc_wake("Processing event: %s%s(%d), state: 0x%lx\n",
  1456. icnss_soc_wake_event_to_str(event->type),
  1457. event->sync ? "-sync" : "", event->type,
  1458. priv->state);
  1459. switch (event->type) {
  1460. case ICNSS_SOC_WAKE_REQUEST_EVENT:
  1461. ret = icnss_event_soc_wake_request(priv,
  1462. event->data);
  1463. break;
  1464. case ICNSS_SOC_WAKE_RELEASE_EVENT:
  1465. ret = icnss_event_soc_wake_release(priv,
  1466. event->data);
  1467. break;
  1468. default:
  1469. icnss_pr_err("Invalid Event type: %d", event->type);
  1470. kfree(event);
  1471. continue;
  1472. }
  1473. priv->stats.soc_wake_events[event->type].processed++;
  1474. icnss_pr_soc_wake("Event Processed: %s%s(%d), ret: %d, state: 0x%lx\n",
  1475. icnss_soc_wake_event_to_str(event->type),
  1476. event->sync ? "-sync" : "", event->type, ret,
  1477. priv->state);
  1478. spin_lock_irqsave(&priv->soc_wake_msg_lock, flags);
  1479. if (event->sync) {
  1480. event->ret = ret;
  1481. complete(&event->complete);
  1482. continue;
  1483. }
  1484. spin_unlock_irqrestore(&priv->soc_wake_msg_lock, flags);
  1485. kfree(event);
  1486. spin_lock_irqsave(&priv->soc_wake_msg_lock, flags);
  1487. }
  1488. spin_unlock_irqrestore(&priv->soc_wake_msg_lock, flags);
  1489. icnss_pm_relax(priv);
  1490. }
  1491. static int icnss_msa0_ramdump(struct icnss_priv *priv)
  1492. {
  1493. int ret = 0;
  1494. struct qcom_dump_segment segment;
  1495. struct icnss_ramdump_info *msa0_dump_dev = priv->msa0_dump_dev;
  1496. struct list_head head;
  1497. if (!dump_enabled()) {
  1498. icnss_pr_info("Dump collection is not enabled\n");
  1499. return ret;
  1500. }
  1501. if (IS_ERR_OR_NULL(msa0_dump_dev))
  1502. return ret;
  1503. INIT_LIST_HEAD(&head);
  1504. memset(&segment, 0, sizeof(segment));
  1505. segment.va = priv->msa_va;
  1506. segment.size = priv->msa_mem_size;
  1507. list_add(&segment.node, &head);
  1508. if (!msa0_dump_dev->dev) {
  1509. icnss_pr_err("Created Dump Device not found\n");
  1510. return 0;
  1511. }
  1512. ret = qcom_dump(&head, msa0_dump_dev->dev);
  1513. if (ret) {
  1514. icnss_pr_err("Failed to dump msa0, err = %d\n", ret);
  1515. return ret;
  1516. }
  1517. list_del(&segment.node);
  1518. return ret;
  1519. }
  1520. static void icnss_update_state_send_modem_shutdown(struct icnss_priv *priv,
  1521. void *data)
  1522. {
  1523. struct qcom_ssr_notify_data *notif = data;
  1524. int ret = 0;
  1525. if (!notif->crashed) {
  1526. if (atomic_read(&priv->is_shutdown)) {
  1527. atomic_set(&priv->is_shutdown, false);
  1528. if (!test_bit(ICNSS_PD_RESTART, &priv->state) &&
  1529. !test_bit(ICNSS_SHUTDOWN_DONE, &priv->state) &&
  1530. !test_bit(ICNSS_BLOCK_SHUTDOWN, &priv->state)) {
  1531. clear_bit(ICNSS_FW_READY, &priv->state);
  1532. icnss_driver_event_post(priv,
  1533. ICNSS_DRIVER_EVENT_UNREGISTER_DRIVER,
  1534. ICNSS_EVENT_SYNC_UNINTERRUPTIBLE,
  1535. NULL);
  1536. }
  1537. }
  1538. if (test_bit(ICNSS_BLOCK_SHUTDOWN, &priv->state)) {
  1539. if (!wait_for_completion_timeout(
  1540. &priv->unblock_shutdown,
  1541. msecs_to_jiffies(PROBE_TIMEOUT)))
  1542. icnss_pr_err("modem block shutdown timeout\n");
  1543. }
  1544. ret = wlfw_send_modem_shutdown_msg(priv);
  1545. if (ret < 0)
  1546. icnss_pr_err("Fail to send modem shutdown Indication %d\n",
  1547. ret);
  1548. }
  1549. }
  1550. static char *icnss_qcom_ssr_notify_state_to_str(enum qcom_ssr_notify_type code)
  1551. {
  1552. switch (code) {
  1553. case QCOM_SSR_BEFORE_POWERUP:
  1554. return "BEFORE_POWERUP";
  1555. case QCOM_SSR_AFTER_POWERUP:
  1556. return "AFTER_POWERUP";
  1557. case QCOM_SSR_BEFORE_SHUTDOWN:
  1558. return "BEFORE_SHUTDOWN";
  1559. case QCOM_SSR_AFTER_SHUTDOWN:
  1560. return "AFTER_SHUTDOWN";
  1561. default:
  1562. return "UNKNOWN";
  1563. }
  1564. };
  1565. static int icnss_wpss_early_notifier_nb(struct notifier_block *nb,
  1566. unsigned long code,
  1567. void *data)
  1568. {
  1569. struct icnss_priv *priv = container_of(nb, struct icnss_priv,
  1570. wpss_early_ssr_nb);
  1571. icnss_pr_vdbg("WPSS-EARLY-Notify: event %s(%lu)\n",
  1572. icnss_qcom_ssr_notify_state_to_str(code), code);
  1573. if (code == QCOM_SSR_BEFORE_SHUTDOWN) {
  1574. set_bit(ICNSS_FW_DOWN, &priv->state);
  1575. icnss_ignore_fw_timeout(true);
  1576. }
  1577. return NOTIFY_DONE;
  1578. }
  1579. static int icnss_wpss_notifier_nb(struct notifier_block *nb,
  1580. unsigned long code,
  1581. void *data)
  1582. {
  1583. struct icnss_event_pd_service_down_data *event_data;
  1584. struct qcom_ssr_notify_data *notif = data;
  1585. struct icnss_priv *priv = container_of(nb, struct icnss_priv,
  1586. wpss_ssr_nb);
  1587. struct icnss_uevent_fw_down_data fw_down_data = {0};
  1588. icnss_pr_vdbg("WPSS-Notify: event %s(%lu)\n",
  1589. icnss_qcom_ssr_notify_state_to_str(code), code);
  1590. if (code == QCOM_SSR_AFTER_SHUTDOWN) {
  1591. icnss_pr_info("Collecting msa0 segment dump\n");
  1592. icnss_msa0_ramdump(priv);
  1593. goto out;
  1594. }
  1595. if (code != QCOM_SSR_BEFORE_SHUTDOWN)
  1596. goto out;
  1597. priv->is_ssr = true;
  1598. icnss_pr_info("WPSS went down, state: 0x%lx, crashed: %d\n",
  1599. priv->state, notif->crashed);
  1600. set_bit(ICNSS_FW_DOWN, &priv->state);
  1601. if (notif->crashed)
  1602. priv->stats.recovery.root_pd_crash++;
  1603. else
  1604. priv->stats.recovery.root_pd_shutdown++;
  1605. icnss_ignore_fw_timeout(true);
  1606. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  1607. if (event_data == NULL)
  1608. return notifier_from_errno(-ENOMEM);
  1609. event_data->crashed = notif->crashed;
  1610. fw_down_data.crashed = !!notif->crashed;
  1611. if (test_bit(ICNSS_FW_READY, &priv->state)) {
  1612. clear_bit(ICNSS_FW_READY, &priv->state);
  1613. fw_down_data.crashed = !!notif->crashed;
  1614. icnss_call_driver_uevent(priv,
  1615. ICNSS_UEVENT_FW_DOWN,
  1616. &fw_down_data);
  1617. }
  1618. icnss_driver_event_post(priv, ICNSS_DRIVER_EVENT_PD_SERVICE_DOWN,
  1619. ICNSS_EVENT_SYNC, event_data);
  1620. out:
  1621. icnss_pr_vdbg("Exit %s,state: 0x%lx\n", __func__, priv->state);
  1622. return NOTIFY_OK;
  1623. }
  1624. static int icnss_modem_notifier_nb(struct notifier_block *nb,
  1625. unsigned long code,
  1626. void *data)
  1627. {
  1628. struct icnss_event_pd_service_down_data *event_data;
  1629. struct qcom_ssr_notify_data *notif = data;
  1630. struct icnss_priv *priv = container_of(nb, struct icnss_priv,
  1631. modem_ssr_nb);
  1632. struct icnss_uevent_fw_down_data fw_down_data = {0};
  1633. icnss_pr_vdbg("Modem-Notify: event %s(%lu)\n",
  1634. icnss_qcom_ssr_notify_state_to_str(code), code);
  1635. if (code == QCOM_SSR_AFTER_SHUTDOWN) {
  1636. icnss_pr_info("Collecting msa0 segment dump\n");
  1637. icnss_msa0_ramdump(priv);
  1638. goto out;
  1639. }
  1640. if (code != QCOM_SSR_BEFORE_SHUTDOWN)
  1641. goto out;
  1642. priv->is_ssr = true;
  1643. if (notif->crashed) {
  1644. priv->stats.recovery.root_pd_crash++;
  1645. priv->root_pd_shutdown = false;
  1646. } else {
  1647. priv->stats.recovery.root_pd_shutdown++;
  1648. priv->root_pd_shutdown = true;
  1649. }
  1650. icnss_update_state_send_modem_shutdown(priv, data);
  1651. if (test_bit(ICNSS_PDR_REGISTERED, &priv->state)) {
  1652. set_bit(ICNSS_FW_DOWN, &priv->state);
  1653. icnss_ignore_fw_timeout(true);
  1654. if (test_bit(ICNSS_FW_READY, &priv->state)) {
  1655. clear_bit(ICNSS_FW_READY, &priv->state);
  1656. fw_down_data.crashed = !!notif->crashed;
  1657. icnss_call_driver_uevent(priv,
  1658. ICNSS_UEVENT_FW_DOWN,
  1659. &fw_down_data);
  1660. }
  1661. goto out;
  1662. }
  1663. icnss_pr_info("Modem went down, state: 0x%lx, crashed: %d\n",
  1664. priv->state, notif->crashed);
  1665. set_bit(ICNSS_FW_DOWN, &priv->state);
  1666. icnss_ignore_fw_timeout(true);
  1667. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  1668. if (event_data == NULL)
  1669. return notifier_from_errno(-ENOMEM);
  1670. event_data->crashed = notif->crashed;
  1671. fw_down_data.crashed = !!notif->crashed;
  1672. if (test_bit(ICNSS_FW_READY, &priv->state)) {
  1673. clear_bit(ICNSS_FW_READY, &priv->state);
  1674. fw_down_data.crashed = !!notif->crashed;
  1675. icnss_call_driver_uevent(priv,
  1676. ICNSS_UEVENT_FW_DOWN,
  1677. &fw_down_data);
  1678. }
  1679. icnss_driver_event_post(priv, ICNSS_DRIVER_EVENT_PD_SERVICE_DOWN,
  1680. ICNSS_EVENT_SYNC, event_data);
  1681. out:
  1682. icnss_pr_vdbg("Exit %s,state: 0x%lx\n", __func__, priv->state);
  1683. return NOTIFY_OK;
  1684. }
  1685. static int icnss_wpss_early_ssr_register_notifier(struct icnss_priv *priv)
  1686. {
  1687. int ret = 0;
  1688. priv->wpss_early_ssr_nb.notifier_call = icnss_wpss_early_notifier_nb;
  1689. priv->wpss_early_notify_handler =
  1690. qcom_register_early_ssr_notifier("wpss",
  1691. &priv->wpss_early_ssr_nb);
  1692. if (IS_ERR(priv->wpss_early_notify_handler)) {
  1693. ret = PTR_ERR(priv->wpss_early_notify_handler);
  1694. icnss_pr_err("WPSS register early notifier failed: %d\n", ret);
  1695. }
  1696. return ret;
  1697. }
  1698. static int icnss_wpss_ssr_register_notifier(struct icnss_priv *priv)
  1699. {
  1700. int ret = 0;
  1701. priv->wpss_ssr_nb.notifier_call = icnss_wpss_notifier_nb;
  1702. /*
  1703. * Assign priority of icnss wpss notifier callback over IPA
  1704. * modem notifier callback which is 0
  1705. */
  1706. priv->wpss_ssr_nb.priority = 1;
  1707. priv->wpss_notify_handler =
  1708. qcom_register_ssr_notifier("wpss", &priv->wpss_ssr_nb);
  1709. if (IS_ERR(priv->wpss_notify_handler)) {
  1710. ret = PTR_ERR(priv->wpss_notify_handler);
  1711. icnss_pr_err("WPSS register notifier failed: %d\n", ret);
  1712. }
  1713. set_bit(ICNSS_SSR_REGISTERED, &priv->state);
  1714. return ret;
  1715. }
  1716. static int icnss_modem_ssr_register_notifier(struct icnss_priv *priv)
  1717. {
  1718. int ret = 0;
  1719. priv->modem_ssr_nb.notifier_call = icnss_modem_notifier_nb;
  1720. /*
  1721. * Assign priority of icnss modem notifier callback over IPA
  1722. * modem notifier callback which is 0
  1723. */
  1724. priv->modem_ssr_nb.priority = 1;
  1725. priv->modem_notify_handler =
  1726. qcom_register_ssr_notifier("modem", &priv->modem_ssr_nb);
  1727. if (IS_ERR(priv->modem_notify_handler)) {
  1728. ret = PTR_ERR(priv->modem_notify_handler);
  1729. icnss_pr_err("Modem register notifier failed: %d\n", ret);
  1730. }
  1731. set_bit(ICNSS_SSR_REGISTERED, &priv->state);
  1732. return ret;
  1733. }
  1734. static void icnss_wpss_early_ssr_unregister_notifier(struct icnss_priv *priv)
  1735. {
  1736. if (IS_ERR(priv->wpss_early_notify_handler))
  1737. return;
  1738. qcom_unregister_early_ssr_notifier(priv->wpss_early_notify_handler,
  1739. &priv->wpss_early_ssr_nb);
  1740. priv->wpss_early_notify_handler = NULL;
  1741. }
  1742. static int icnss_wpss_ssr_unregister_notifier(struct icnss_priv *priv)
  1743. {
  1744. if (!test_and_clear_bit(ICNSS_SSR_REGISTERED, &priv->state))
  1745. return 0;
  1746. qcom_unregister_ssr_notifier(priv->wpss_notify_handler,
  1747. &priv->wpss_ssr_nb);
  1748. priv->wpss_notify_handler = NULL;
  1749. return 0;
  1750. }
  1751. static int icnss_modem_ssr_unregister_notifier(struct icnss_priv *priv)
  1752. {
  1753. if (!test_and_clear_bit(ICNSS_SSR_REGISTERED, &priv->state))
  1754. return 0;
  1755. qcom_unregister_ssr_notifier(priv->modem_notify_handler,
  1756. &priv->modem_ssr_nb);
  1757. priv->modem_notify_handler = NULL;
  1758. return 0;
  1759. }
  1760. static void icnss_pdr_notifier_cb(int state, char *service_path, void *priv_cb)
  1761. {
  1762. struct icnss_priv *priv = priv_cb;
  1763. struct icnss_event_pd_service_down_data *event_data;
  1764. struct icnss_uevent_fw_down_data fw_down_data = {0};
  1765. enum icnss_pdr_cause_index cause = ICNSS_ROOT_PD_CRASH;
  1766. icnss_pr_dbg("PD service notification: 0x%lx state: 0x%lx\n",
  1767. state, priv->state);
  1768. switch (state) {
  1769. case SERVREG_SERVICE_STATE_DOWN:
  1770. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  1771. if (!event_data)
  1772. return;
  1773. event_data->crashed = true;
  1774. if (!priv->is_ssr) {
  1775. set_bit(ICNSS_PDR, &penv->state);
  1776. if (test_bit(ICNSS_HOST_TRIGGERED_PDR, &priv->state)) {
  1777. cause = ICNSS_HOST_ERROR;
  1778. priv->stats.recovery.pdr_host_error++;
  1779. } else {
  1780. cause = ICNSS_FW_CRASH;
  1781. priv->stats.recovery.pdr_fw_crash++;
  1782. }
  1783. } else if (priv->root_pd_shutdown) {
  1784. cause = ICNSS_ROOT_PD_SHUTDOWN;
  1785. event_data->crashed = false;
  1786. }
  1787. icnss_pr_info("PD service down, state: 0x%lx: cause: %s\n",
  1788. priv->state, icnss_pdr_cause[cause]);
  1789. if (!test_bit(ICNSS_FW_DOWN, &priv->state)) {
  1790. set_bit(ICNSS_FW_DOWN, &priv->state);
  1791. icnss_ignore_fw_timeout(true);
  1792. if (test_bit(ICNSS_FW_READY, &priv->state)) {
  1793. clear_bit(ICNSS_FW_READY, &priv->state);
  1794. fw_down_data.crashed = event_data->crashed;
  1795. icnss_call_driver_uevent(priv,
  1796. ICNSS_UEVENT_FW_DOWN,
  1797. &fw_down_data);
  1798. }
  1799. }
  1800. clear_bit(ICNSS_HOST_TRIGGERED_PDR, &priv->state);
  1801. icnss_driver_event_post(priv, ICNSS_DRIVER_EVENT_PD_SERVICE_DOWN,
  1802. ICNSS_EVENT_SYNC, event_data);
  1803. break;
  1804. case SERVREG_SERVICE_STATE_UP:
  1805. clear_bit(ICNSS_FW_DOWN, &priv->state);
  1806. break;
  1807. default:
  1808. break;
  1809. }
  1810. return;
  1811. }
  1812. static int icnss_pd_restart_enable(struct icnss_priv *priv)
  1813. {
  1814. struct pdr_handle *handle = NULL;
  1815. struct pdr_service *service = NULL;
  1816. int err = 0;
  1817. handle = pdr_handle_alloc(icnss_pdr_notifier_cb, priv);
  1818. if (IS_ERR_OR_NULL(handle)) {
  1819. err = PTR_ERR(handle);
  1820. icnss_pr_err("Failed to alloc pdr handle, err %d", err);
  1821. goto out;
  1822. }
  1823. service = pdr_add_lookup(handle, ICNSS_WLAN_SERVICE_NAME, ICNSS_WLANPD_NAME);
  1824. if (IS_ERR_OR_NULL(service)) {
  1825. err = PTR_ERR(service);
  1826. icnss_pr_err("Failed to add lookup, err %d", err);
  1827. goto out;
  1828. }
  1829. priv->pdr_handle = handle;
  1830. priv->pdr_service = service;
  1831. set_bit(ICNSS_PDR_REGISTERED, &priv->state);
  1832. icnss_pr_info("PDR registration happened");
  1833. out:
  1834. return err;
  1835. }
  1836. static void icnss_pdr_unregister_notifier(struct icnss_priv *priv)
  1837. {
  1838. if (!test_and_clear_bit(ICNSS_PDR_REGISTERED, &priv->state))
  1839. return;
  1840. pdr_handle_release(priv->pdr_handle);
  1841. }
  1842. static int icnss_ramdump_devnode_init(struct icnss_priv *priv)
  1843. {
  1844. int ret = 0;
  1845. priv->icnss_ramdump_class = class_create(THIS_MODULE, ICNSS_RAMDUMP_NAME);
  1846. if (IS_ERR_OR_NULL(priv->icnss_ramdump_class)) {
  1847. ret = PTR_ERR(priv->icnss_ramdump_class);
  1848. icnss_pr_err("%s:Class create failed for ramdump devices (%d)\n", __func__, ret);
  1849. return ret;
  1850. }
  1851. ret = alloc_chrdev_region(&priv->icnss_ramdump_dev, 0, RAMDUMP_NUM_DEVICES,
  1852. ICNSS_RAMDUMP_NAME);
  1853. if (ret < 0) {
  1854. icnss_pr_err("%s: Unable to allocate major\n", __func__);
  1855. goto fail_alloc_major;
  1856. }
  1857. return 0;
  1858. fail_alloc_major:
  1859. class_destroy(priv->icnss_ramdump_class);
  1860. return ret;
  1861. }
  1862. void *icnss_create_ramdump_device(struct icnss_priv *priv, const char *dev_name)
  1863. {
  1864. int ret = 0;
  1865. struct icnss_ramdump_info *ramdump_info;
  1866. ramdump_info = kzalloc(sizeof(*ramdump_info), GFP_KERNEL);
  1867. if (!ramdump_info)
  1868. return ERR_PTR(-ENOMEM);
  1869. if (!dev_name) {
  1870. icnss_pr_err("%s: Invalid device name.\n", __func__);
  1871. return NULL;
  1872. }
  1873. snprintf(ramdump_info->name, ARRAY_SIZE(ramdump_info->name), "icnss_%s", dev_name);
  1874. ramdump_info->minor = ida_simple_get(&rd_minor_id, 0, RAMDUMP_NUM_DEVICES, GFP_KERNEL);
  1875. if (ramdump_info->minor < 0) {
  1876. icnss_pr_err("%s: No more minor numbers left! rc:%d\n", __func__,
  1877. ramdump_info->minor);
  1878. ret = -ENODEV;
  1879. goto fail_out_of_minors;
  1880. }
  1881. ramdump_info->dev = device_create(priv->icnss_ramdump_class, NULL,
  1882. MKDEV(MAJOR(priv->icnss_ramdump_dev),
  1883. ramdump_info->minor),
  1884. ramdump_info, ramdump_info->name);
  1885. if (IS_ERR_OR_NULL(ramdump_info->dev)) {
  1886. ret = PTR_ERR(ramdump_info->dev);
  1887. icnss_pr_err("%s: Device create failed for %s (%d)\n", __func__,
  1888. ramdump_info->name, ret);
  1889. goto fail_device_create;
  1890. }
  1891. return (void *)ramdump_info;
  1892. fail_device_create:
  1893. ida_simple_remove(&rd_minor_id, ramdump_info->minor);
  1894. fail_out_of_minors:
  1895. kfree(ramdump_info);
  1896. return ERR_PTR(ret);
  1897. }
  1898. static int icnss_register_ramdump_devices(struct icnss_priv *priv)
  1899. {
  1900. int ret = 0;
  1901. if (!priv || !priv->pdev) {
  1902. icnss_pr_err("Platform priv or pdev is NULL\n");
  1903. return -EINVAL;
  1904. }
  1905. ret = icnss_ramdump_devnode_init(priv);
  1906. if (ret)
  1907. return ret;
  1908. priv->msa0_dump_dev = icnss_create_ramdump_device(priv, "wcss_msa0");
  1909. if (IS_ERR_OR_NULL(priv->msa0_dump_dev) || !priv->msa0_dump_dev->dev) {
  1910. icnss_pr_err("Failed to create msa0 dump device!");
  1911. return -ENOMEM;
  1912. }
  1913. if (priv->device_id == WCN6750_DEVICE_ID) {
  1914. priv->m3_dump_phyareg = icnss_create_ramdump_device(priv,
  1915. ICNSS_M3_SEGMENT(
  1916. ICNSS_M3_SEGMENT_PHYAREG));
  1917. if (IS_ERR_OR_NULL(priv->m3_dump_phyareg) ||
  1918. !priv->m3_dump_phyareg->dev) {
  1919. icnss_pr_err("Failed to create m3 dump for Phyareg segment device!");
  1920. return -ENOMEM;
  1921. }
  1922. priv->m3_dump_phydbg = icnss_create_ramdump_device(priv,
  1923. ICNSS_M3_SEGMENT(
  1924. ICNSS_M3_SEGMENT_PHYA));
  1925. if (IS_ERR_OR_NULL(priv->m3_dump_phydbg) ||
  1926. !priv->m3_dump_phydbg->dev) {
  1927. icnss_pr_err("Failed to create m3 dump for Phydbg segment device!");
  1928. return -ENOMEM;
  1929. }
  1930. priv->m3_dump_wmac0reg = icnss_create_ramdump_device(priv,
  1931. ICNSS_M3_SEGMENT(
  1932. ICNSS_M3_SEGMENT_WMACREG));
  1933. if (IS_ERR_OR_NULL(priv->m3_dump_wmac0reg) ||
  1934. !priv->m3_dump_wmac0reg->dev) {
  1935. icnss_pr_err("Failed to create m3 dump for Wmac0reg segment device!");
  1936. return -ENOMEM;
  1937. }
  1938. priv->m3_dump_wcssdbg = icnss_create_ramdump_device(priv,
  1939. ICNSS_M3_SEGMENT(
  1940. ICNSS_M3_SEGMENT_WCSSDBG));
  1941. if (IS_ERR_OR_NULL(priv->m3_dump_wcssdbg) ||
  1942. !priv->m3_dump_wcssdbg->dev) {
  1943. icnss_pr_err("Failed to create m3 dump for Wcssdbg segment device!");
  1944. return -ENOMEM;
  1945. }
  1946. priv->m3_dump_phyapdmem = icnss_create_ramdump_device(priv,
  1947. ICNSS_M3_SEGMENT(
  1948. ICNSS_M3_SEGMENT_PHYAM3));
  1949. if (IS_ERR_OR_NULL(priv->m3_dump_phyapdmem) ||
  1950. !priv->m3_dump_phyapdmem->dev) {
  1951. icnss_pr_err("Failed to create m3 dump for Phyapdmem segment device!");
  1952. return -ENOMEM;
  1953. }
  1954. }
  1955. return 0;
  1956. }
  1957. static int icnss_enable_recovery(struct icnss_priv *priv)
  1958. {
  1959. int ret;
  1960. if (test_bit(RECOVERY_DISABLE, &priv->ctrl_params.quirks)) {
  1961. icnss_pr_dbg("Recovery disabled through module parameter\n");
  1962. return 0;
  1963. }
  1964. if (test_bit(PDR_ONLY, &priv->ctrl_params.quirks)) {
  1965. icnss_pr_dbg("SSR disabled through module parameter\n");
  1966. goto enable_pdr;
  1967. }
  1968. ret = icnss_register_ramdump_devices(priv);
  1969. if (ret)
  1970. return ret;
  1971. if (priv->wpss_supported) {
  1972. icnss_wpss_early_ssr_register_notifier(priv);
  1973. icnss_wpss_ssr_register_notifier(priv);
  1974. return 0;
  1975. }
  1976. icnss_modem_ssr_register_notifier(priv);
  1977. if (test_bit(SSR_ONLY, &priv->ctrl_params.quirks)) {
  1978. icnss_pr_dbg("PDR disabled through module parameter\n");
  1979. return 0;
  1980. }
  1981. enable_pdr:
  1982. ret = icnss_pd_restart_enable(priv);
  1983. if (ret)
  1984. return ret;
  1985. return 0;
  1986. }
  1987. static int icnss_dev_id_match(struct icnss_priv *priv,
  1988. struct device_info *dev_info)
  1989. {
  1990. while (dev_info->device_id) {
  1991. if (priv->device_id == dev_info->device_id)
  1992. return 1;
  1993. dev_info++;
  1994. }
  1995. return 0;
  1996. }
  1997. static int icnss_tcdev_get_max_state(struct thermal_cooling_device *tcdev,
  1998. unsigned long *thermal_state)
  1999. {
  2000. struct icnss_thermal_cdev *icnss_tcdev = tcdev->devdata;
  2001. *thermal_state = icnss_tcdev->max_thermal_state;
  2002. return 0;
  2003. }
  2004. static int icnss_tcdev_get_cur_state(struct thermal_cooling_device *tcdev,
  2005. unsigned long *thermal_state)
  2006. {
  2007. struct icnss_thermal_cdev *icnss_tcdev = tcdev->devdata;
  2008. *thermal_state = icnss_tcdev->curr_thermal_state;
  2009. return 0;
  2010. }
  2011. static int icnss_tcdev_set_cur_state(struct thermal_cooling_device *tcdev,
  2012. unsigned long thermal_state)
  2013. {
  2014. struct icnss_thermal_cdev *icnss_tcdev = tcdev->devdata;
  2015. struct device *dev = &penv->pdev->dev;
  2016. int ret = 0;
  2017. if (!penv->ops || !penv->ops->set_therm_cdev_state)
  2018. return 0;
  2019. if (thermal_state > icnss_tcdev->max_thermal_state)
  2020. return -EINVAL;
  2021. icnss_pr_vdbg("Cooling device set current state: %ld,for cdev id %d",
  2022. thermal_state, icnss_tcdev->tcdev_id);
  2023. mutex_lock(&penv->tcdev_lock);
  2024. ret = penv->ops->set_therm_cdev_state(dev, thermal_state,
  2025. icnss_tcdev->tcdev_id);
  2026. if (!ret)
  2027. icnss_tcdev->curr_thermal_state = thermal_state;
  2028. mutex_unlock(&penv->tcdev_lock);
  2029. if (ret) {
  2030. icnss_pr_err("Setting Current Thermal State Failed: %d,for cdev id %d",
  2031. ret, icnss_tcdev->tcdev_id);
  2032. return ret;
  2033. }
  2034. return 0;
  2035. }
  2036. static struct thermal_cooling_device_ops icnss_cooling_ops = {
  2037. .get_max_state = icnss_tcdev_get_max_state,
  2038. .get_cur_state = icnss_tcdev_get_cur_state,
  2039. .set_cur_state = icnss_tcdev_set_cur_state,
  2040. };
  2041. int icnss_thermal_cdev_register(struct device *dev, unsigned long max_state,
  2042. int tcdev_id)
  2043. {
  2044. struct icnss_priv *priv = dev_get_drvdata(dev);
  2045. struct icnss_thermal_cdev *icnss_tcdev = NULL;
  2046. char cdev_node_name[THERMAL_NAME_LENGTH] = "";
  2047. struct device_node *dev_node;
  2048. int ret = 0;
  2049. icnss_tcdev = kzalloc(sizeof(*icnss_tcdev), GFP_KERNEL);
  2050. if (!icnss_tcdev)
  2051. return -ENOMEM;
  2052. icnss_tcdev->tcdev_id = tcdev_id;
  2053. icnss_tcdev->max_thermal_state = max_state;
  2054. snprintf(cdev_node_name, THERMAL_NAME_LENGTH,
  2055. "qcom,icnss_cdev%d", tcdev_id);
  2056. dev_node = of_find_node_by_name(NULL, cdev_node_name);
  2057. if (!dev_node) {
  2058. icnss_pr_err("Failed to get cooling device node\n");
  2059. return -EINVAL;
  2060. }
  2061. icnss_pr_dbg("tcdev node->name=%s\n", dev_node->name);
  2062. if (of_find_property(dev_node, "#cooling-cells", NULL)) {
  2063. icnss_tcdev->tcdev = thermal_of_cooling_device_register(
  2064. dev_node,
  2065. cdev_node_name, icnss_tcdev,
  2066. &icnss_cooling_ops);
  2067. if (IS_ERR_OR_NULL(icnss_tcdev->tcdev)) {
  2068. ret = PTR_ERR(icnss_tcdev->tcdev);
  2069. icnss_pr_err("Cooling device register failed: %d, for cdev id %d\n",
  2070. ret, icnss_tcdev->tcdev_id);
  2071. } else {
  2072. icnss_pr_dbg("Cooling device registered for cdev id %d",
  2073. icnss_tcdev->tcdev_id);
  2074. list_add(&icnss_tcdev->tcdev_list,
  2075. &priv->icnss_tcdev_list);
  2076. }
  2077. } else {
  2078. icnss_pr_dbg("Cooling device registration not supported");
  2079. ret = -EOPNOTSUPP;
  2080. }
  2081. return ret;
  2082. }
  2083. EXPORT_SYMBOL(icnss_thermal_cdev_register);
  2084. void icnss_thermal_cdev_unregister(struct device *dev, int tcdev_id)
  2085. {
  2086. struct icnss_priv *priv = dev_get_drvdata(dev);
  2087. struct icnss_thermal_cdev *icnss_tcdev = NULL;
  2088. while (!list_empty(&priv->icnss_tcdev_list)) {
  2089. icnss_tcdev = list_first_entry(&priv->icnss_tcdev_list,
  2090. struct icnss_thermal_cdev,
  2091. tcdev_list);
  2092. thermal_cooling_device_unregister(icnss_tcdev->tcdev);
  2093. list_del(&icnss_tcdev->tcdev_list);
  2094. kfree(icnss_tcdev);
  2095. }
  2096. }
  2097. EXPORT_SYMBOL(icnss_thermal_cdev_unregister);
  2098. int icnss_get_curr_therm_cdev_state(struct device *dev,
  2099. unsigned long *thermal_state,
  2100. int tcdev_id)
  2101. {
  2102. struct icnss_priv *priv = dev_get_drvdata(dev);
  2103. struct icnss_thermal_cdev *icnss_tcdev = NULL;
  2104. mutex_lock(&priv->tcdev_lock);
  2105. list_for_each_entry(icnss_tcdev, &priv->icnss_tcdev_list, tcdev_list) {
  2106. if (icnss_tcdev->tcdev_id != tcdev_id)
  2107. continue;
  2108. *thermal_state = icnss_tcdev->curr_thermal_state;
  2109. mutex_unlock(&priv->tcdev_lock);
  2110. icnss_pr_dbg("Cooling device current state: %ld, for cdev id %d",
  2111. icnss_tcdev->curr_thermal_state, tcdev_id);
  2112. return 0;
  2113. }
  2114. mutex_unlock(&priv->tcdev_lock);
  2115. icnss_pr_dbg("Cooling device ID not found: %d", tcdev_id);
  2116. return -EINVAL;
  2117. }
  2118. EXPORT_SYMBOL(icnss_get_curr_therm_cdev_state);
  2119. int icnss_qmi_send(struct device *dev, int type, void *cmd,
  2120. int cmd_len, void *cb_ctx,
  2121. int (*cb)(void *ctx, void *event, int event_len))
  2122. {
  2123. struct icnss_priv *priv = icnss_get_plat_priv();
  2124. int ret;
  2125. if (!priv)
  2126. return -ENODEV;
  2127. if (!test_bit(ICNSS_WLFW_CONNECTED, &priv->state))
  2128. return -EINVAL;
  2129. priv->get_info_cb = cb;
  2130. priv->get_info_cb_ctx = cb_ctx;
  2131. ret = icnss_wlfw_get_info_send_sync(priv, type, cmd, cmd_len);
  2132. if (ret) {
  2133. priv->get_info_cb = NULL;
  2134. priv->get_info_cb_ctx = NULL;
  2135. }
  2136. return ret;
  2137. }
  2138. EXPORT_SYMBOL(icnss_qmi_send);
  2139. int __icnss_register_driver(struct icnss_driver_ops *ops,
  2140. struct module *owner, const char *mod_name)
  2141. {
  2142. int ret = 0;
  2143. struct icnss_priv *priv = icnss_get_plat_priv();
  2144. if (!priv || !priv->pdev) {
  2145. ret = -ENODEV;
  2146. goto out;
  2147. }
  2148. icnss_pr_dbg("Registering driver, state: 0x%lx\n", priv->state);
  2149. if (priv->ops) {
  2150. icnss_pr_err("Driver already registered\n");
  2151. ret = -EEXIST;
  2152. goto out;
  2153. }
  2154. if (!ops->dev_info) {
  2155. icnss_pr_err("WLAN driver devinfo is null, Reject wlan driver loading");
  2156. return -EINVAL;
  2157. }
  2158. if (!icnss_dev_id_match(priv, ops->dev_info)) {
  2159. icnss_pr_err("WLAN driver dev name is %s, not supported by platform driver\n",
  2160. ops->dev_info->name);
  2161. return -ENODEV;
  2162. }
  2163. if (!ops->probe || !ops->remove) {
  2164. ret = -EINVAL;
  2165. goto out;
  2166. }
  2167. ret = icnss_driver_event_post(priv, ICNSS_DRIVER_EVENT_REGISTER_DRIVER,
  2168. 0, ops);
  2169. if (ret == -EINTR)
  2170. ret = 0;
  2171. out:
  2172. return ret;
  2173. }
  2174. EXPORT_SYMBOL(__icnss_register_driver);
  2175. int icnss_unregister_driver(struct icnss_driver_ops *ops)
  2176. {
  2177. int ret;
  2178. struct icnss_priv *priv = icnss_get_plat_priv();
  2179. if (!priv || !priv->pdev) {
  2180. ret = -ENODEV;
  2181. goto out;
  2182. }
  2183. icnss_pr_dbg("Unregistering driver, state: 0x%lx\n", priv->state);
  2184. if (!priv->ops) {
  2185. icnss_pr_err("Driver not registered\n");
  2186. ret = -ENOENT;
  2187. goto out;
  2188. }
  2189. ret = icnss_driver_event_post(priv,
  2190. ICNSS_DRIVER_EVENT_UNREGISTER_DRIVER,
  2191. ICNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  2192. out:
  2193. return ret;
  2194. }
  2195. EXPORT_SYMBOL(icnss_unregister_driver);
  2196. static struct icnss_msi_config msi_config = {
  2197. .total_vectors = 28,
  2198. .total_users = 2,
  2199. .users = (struct icnss_msi_user[]) {
  2200. { .name = "CE", .num_vectors = 10, .base_vector = 0 },
  2201. { .name = "DP", .num_vectors = 18, .base_vector = 10 },
  2202. },
  2203. };
  2204. static int icnss_get_msi_assignment(struct icnss_priv *priv)
  2205. {
  2206. priv->msi_config = &msi_config;
  2207. return 0;
  2208. }
  2209. int icnss_get_user_msi_assignment(struct device *dev, char *user_name,
  2210. int *num_vectors, u32 *user_base_data,
  2211. u32 *base_vector)
  2212. {
  2213. struct icnss_priv *priv = dev_get_drvdata(dev);
  2214. struct icnss_msi_config *msi_config;
  2215. int idx;
  2216. if (!priv)
  2217. return -ENODEV;
  2218. msi_config = priv->msi_config;
  2219. if (!msi_config) {
  2220. icnss_pr_err("MSI is not supported.\n");
  2221. return -EINVAL;
  2222. }
  2223. for (idx = 0; idx < msi_config->total_users; idx++) {
  2224. if (strcmp(user_name, msi_config->users[idx].name) == 0) {
  2225. *num_vectors = msi_config->users[idx].num_vectors;
  2226. *user_base_data = msi_config->users[idx].base_vector
  2227. + priv->msi_base_data;
  2228. *base_vector = msi_config->users[idx].base_vector;
  2229. icnss_pr_dbg("Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
  2230. user_name, *num_vectors, *user_base_data,
  2231. *base_vector);
  2232. return 0;
  2233. }
  2234. }
  2235. icnss_pr_err("Failed to find MSI assignment for %s!\n", user_name);
  2236. return -EINVAL;
  2237. }
  2238. EXPORT_SYMBOL(icnss_get_user_msi_assignment);
  2239. int icnss_get_msi_irq(struct device *dev, unsigned int vector)
  2240. {
  2241. struct icnss_priv *priv = dev_get_drvdata(dev);
  2242. int irq_num;
  2243. irq_num = priv->srng_irqs[vector];
  2244. icnss_pr_dbg("Get IRQ number %d for vector index %d\n",
  2245. irq_num, vector);
  2246. return irq_num;
  2247. }
  2248. EXPORT_SYMBOL(icnss_get_msi_irq);
  2249. void icnss_get_msi_address(struct device *dev, u32 *msi_addr_low,
  2250. u32 *msi_addr_high)
  2251. {
  2252. struct icnss_priv *priv = dev_get_drvdata(dev);
  2253. *msi_addr_low = lower_32_bits(priv->msi_addr_iova);
  2254. *msi_addr_high = upper_32_bits(priv->msi_addr_iova);
  2255. }
  2256. EXPORT_SYMBOL(icnss_get_msi_address);
  2257. int icnss_ce_request_irq(struct device *dev, unsigned int ce_id,
  2258. irqreturn_t (*handler)(int, void *),
  2259. unsigned long flags, const char *name, void *ctx)
  2260. {
  2261. int ret = 0;
  2262. unsigned int irq;
  2263. struct ce_irq_list *irq_entry;
  2264. struct icnss_priv *priv = dev_get_drvdata(dev);
  2265. if (!priv || !priv->pdev) {
  2266. ret = -ENODEV;
  2267. goto out;
  2268. }
  2269. icnss_pr_vdbg("CE request IRQ: %d, state: 0x%lx\n", ce_id, priv->state);
  2270. if (ce_id >= ICNSS_MAX_IRQ_REGISTRATIONS) {
  2271. icnss_pr_err("Invalid CE ID, ce_id: %d\n", ce_id);
  2272. ret = -EINVAL;
  2273. goto out;
  2274. }
  2275. irq = priv->ce_irqs[ce_id];
  2276. irq_entry = &priv->ce_irq_list[ce_id];
  2277. if (irq_entry->handler || irq_entry->irq) {
  2278. icnss_pr_err("IRQ already requested: %d, ce_id: %d\n",
  2279. irq, ce_id);
  2280. ret = -EEXIST;
  2281. goto out;
  2282. }
  2283. ret = request_irq(irq, handler, flags, name, ctx);
  2284. if (ret) {
  2285. icnss_pr_err("IRQ request failed: %d, ce_id: %d, ret: %d\n",
  2286. irq, ce_id, ret);
  2287. goto out;
  2288. }
  2289. irq_entry->irq = irq;
  2290. irq_entry->handler = handler;
  2291. icnss_pr_vdbg("IRQ requested: %d, ce_id: %d\n", irq, ce_id);
  2292. penv->stats.ce_irqs[ce_id].request++;
  2293. out:
  2294. return ret;
  2295. }
  2296. EXPORT_SYMBOL(icnss_ce_request_irq);
  2297. int icnss_ce_free_irq(struct device *dev, unsigned int ce_id, void *ctx)
  2298. {
  2299. int ret = 0;
  2300. unsigned int irq;
  2301. struct ce_irq_list *irq_entry;
  2302. if (!penv || !penv->pdev || !dev) {
  2303. ret = -ENODEV;
  2304. goto out;
  2305. }
  2306. icnss_pr_vdbg("CE free IRQ: %d, state: 0x%lx\n", ce_id, penv->state);
  2307. if (ce_id >= ICNSS_MAX_IRQ_REGISTRATIONS) {
  2308. icnss_pr_err("Invalid CE ID to free, ce_id: %d\n", ce_id);
  2309. ret = -EINVAL;
  2310. goto out;
  2311. }
  2312. irq = penv->ce_irqs[ce_id];
  2313. irq_entry = &penv->ce_irq_list[ce_id];
  2314. if (!irq_entry->handler || !irq_entry->irq) {
  2315. icnss_pr_err("IRQ not requested: %d, ce_id: %d\n", irq, ce_id);
  2316. ret = -EEXIST;
  2317. goto out;
  2318. }
  2319. free_irq(irq, ctx);
  2320. irq_entry->irq = 0;
  2321. irq_entry->handler = NULL;
  2322. penv->stats.ce_irqs[ce_id].free++;
  2323. out:
  2324. return ret;
  2325. }
  2326. EXPORT_SYMBOL(icnss_ce_free_irq);
  2327. void icnss_enable_irq(struct device *dev, unsigned int ce_id)
  2328. {
  2329. unsigned int irq;
  2330. if (!penv || !penv->pdev || !dev) {
  2331. icnss_pr_err("Platform driver not initialized\n");
  2332. return;
  2333. }
  2334. icnss_pr_vdbg("Enable IRQ: ce_id: %d, state: 0x%lx\n", ce_id,
  2335. penv->state);
  2336. if (ce_id >= ICNSS_MAX_IRQ_REGISTRATIONS) {
  2337. icnss_pr_err("Invalid CE ID to enable IRQ, ce_id: %d\n", ce_id);
  2338. return;
  2339. }
  2340. penv->stats.ce_irqs[ce_id].enable++;
  2341. irq = penv->ce_irqs[ce_id];
  2342. enable_irq(irq);
  2343. }
  2344. EXPORT_SYMBOL(icnss_enable_irq);
  2345. void icnss_disable_irq(struct device *dev, unsigned int ce_id)
  2346. {
  2347. unsigned int irq;
  2348. if (!penv || !penv->pdev || !dev) {
  2349. icnss_pr_err("Platform driver not initialized\n");
  2350. return;
  2351. }
  2352. icnss_pr_vdbg("Disable IRQ: ce_id: %d, state: 0x%lx\n", ce_id,
  2353. penv->state);
  2354. if (ce_id >= ICNSS_MAX_IRQ_REGISTRATIONS) {
  2355. icnss_pr_err("Invalid CE ID to disable IRQ, ce_id: %d\n",
  2356. ce_id);
  2357. return;
  2358. }
  2359. irq = penv->ce_irqs[ce_id];
  2360. disable_irq(irq);
  2361. penv->stats.ce_irqs[ce_id].disable++;
  2362. }
  2363. EXPORT_SYMBOL(icnss_disable_irq);
  2364. int icnss_get_soc_info(struct device *dev, struct icnss_soc_info *info)
  2365. {
  2366. char *fw_build_timestamp = NULL;
  2367. struct icnss_priv *priv = dev_get_drvdata(dev);
  2368. if (!priv) {
  2369. icnss_pr_err("Platform driver not initialized\n");
  2370. return -EINVAL;
  2371. }
  2372. info->v_addr = priv->mem_base_va;
  2373. info->p_addr = priv->mem_base_pa;
  2374. info->chip_id = priv->chip_info.chip_id;
  2375. info->chip_family = priv->chip_info.chip_family;
  2376. info->board_id = priv->board_id;
  2377. info->soc_id = priv->soc_id;
  2378. info->fw_version = priv->fw_version_info.fw_version;
  2379. fw_build_timestamp = priv->fw_version_info.fw_build_timestamp;
  2380. fw_build_timestamp[WLFW_MAX_TIMESTAMP_LEN] = '\0';
  2381. strlcpy(info->fw_build_timestamp,
  2382. priv->fw_version_info.fw_build_timestamp,
  2383. WLFW_MAX_TIMESTAMP_LEN + 1);
  2384. return 0;
  2385. }
  2386. EXPORT_SYMBOL(icnss_get_soc_info);
  2387. int icnss_get_mhi_state(struct device *dev)
  2388. {
  2389. struct icnss_priv *priv = dev_get_drvdata(dev);
  2390. if (!priv) {
  2391. icnss_pr_err("Platform driver not initialized\n");
  2392. return -EINVAL;
  2393. }
  2394. if (!priv->mhi_state_info_va)
  2395. return -ENOMEM;
  2396. return ioread32(priv->mhi_state_info_va);
  2397. }
  2398. EXPORT_SYMBOL(icnss_get_mhi_state);
  2399. int icnss_set_fw_log_mode(struct device *dev, uint8_t fw_log_mode)
  2400. {
  2401. int ret;
  2402. struct icnss_priv *priv;
  2403. if (!dev)
  2404. return -ENODEV;
  2405. priv = dev_get_drvdata(dev);
  2406. if (!priv) {
  2407. icnss_pr_err("Platform driver not initialized\n");
  2408. return -EINVAL;
  2409. }
  2410. if (test_bit(ICNSS_FW_DOWN, &penv->state) ||
  2411. !test_bit(ICNSS_FW_READY, &penv->state)) {
  2412. icnss_pr_err("FW down, ignoring fw_log_mode state: 0x%lx\n",
  2413. priv->state);
  2414. return -EINVAL;
  2415. }
  2416. icnss_pr_dbg("FW log mode: %u\n", fw_log_mode);
  2417. ret = wlfw_ini_send_sync_msg(priv, fw_log_mode);
  2418. if (ret)
  2419. icnss_pr_err("Fail to send ini, ret = %d, fw_log_mode: %u\n",
  2420. ret, fw_log_mode);
  2421. return ret;
  2422. }
  2423. EXPORT_SYMBOL(icnss_set_fw_log_mode);
  2424. int icnss_force_wake_request(struct device *dev)
  2425. {
  2426. struct icnss_priv *priv;
  2427. if (!dev)
  2428. return -ENODEV;
  2429. priv = dev_get_drvdata(dev);
  2430. if (!priv) {
  2431. icnss_pr_err("Platform driver not initialized\n");
  2432. return -EINVAL;
  2433. }
  2434. if (atomic_inc_not_zero(&priv->soc_wake_ref_count)) {
  2435. icnss_pr_soc_wake("SOC already awake, Ref count: %d",
  2436. atomic_read(&priv->soc_wake_ref_count));
  2437. return 0;
  2438. }
  2439. icnss_pr_soc_wake("Calling SOC Wake request");
  2440. icnss_soc_wake_event_post(priv, ICNSS_SOC_WAKE_REQUEST_EVENT,
  2441. 0, NULL);
  2442. return 0;
  2443. }
  2444. EXPORT_SYMBOL(icnss_force_wake_request);
  2445. int icnss_force_wake_release(struct device *dev)
  2446. {
  2447. struct icnss_priv *priv;
  2448. if (!dev)
  2449. return -ENODEV;
  2450. priv = dev_get_drvdata(dev);
  2451. if (!priv) {
  2452. icnss_pr_err("Platform driver not initialized\n");
  2453. return -EINVAL;
  2454. }
  2455. icnss_pr_soc_wake("Calling SOC Wake response");
  2456. if (atomic_read(&priv->soc_wake_ref_count) &&
  2457. icnss_atomic_dec_if_greater_one(&priv->soc_wake_ref_count)) {
  2458. icnss_pr_soc_wake("SOC previous release pending, Ref count: %d",
  2459. atomic_read(&priv->soc_wake_ref_count));
  2460. return 0;
  2461. }
  2462. icnss_soc_wake_event_post(priv, ICNSS_SOC_WAKE_RELEASE_EVENT,
  2463. 0, NULL);
  2464. return 0;
  2465. }
  2466. EXPORT_SYMBOL(icnss_force_wake_release);
  2467. int icnss_is_device_awake(struct device *dev)
  2468. {
  2469. struct icnss_priv *priv = dev_get_drvdata(dev);
  2470. if (!priv) {
  2471. icnss_pr_err("Platform driver not initialized\n");
  2472. return -EINVAL;
  2473. }
  2474. return atomic_read(&priv->soc_wake_ref_count);
  2475. }
  2476. EXPORT_SYMBOL(icnss_is_device_awake);
  2477. int icnss_is_pci_ep_awake(struct device *dev)
  2478. {
  2479. struct icnss_priv *priv = dev_get_drvdata(dev);
  2480. if (!priv) {
  2481. icnss_pr_err("Platform driver not initialized\n");
  2482. return -EINVAL;
  2483. }
  2484. if (!priv->mhi_state_info_va)
  2485. return -ENOMEM;
  2486. return ioread32(priv->mhi_state_info_va + ICNSS_PCI_EP_WAKE_OFFSET);
  2487. }
  2488. EXPORT_SYMBOL(icnss_is_pci_ep_awake);
  2489. int icnss_athdiag_read(struct device *dev, uint32_t offset,
  2490. uint32_t mem_type, uint32_t data_len,
  2491. uint8_t *output)
  2492. {
  2493. int ret = 0;
  2494. struct icnss_priv *priv = dev_get_drvdata(dev);
  2495. if (priv->magic != ICNSS_MAGIC) {
  2496. icnss_pr_err("Invalid drvdata for diag read: dev %pK, data %pK, magic 0x%x\n",
  2497. dev, priv, priv->magic);
  2498. return -EINVAL;
  2499. }
  2500. if (!output || data_len == 0
  2501. || data_len > WLFW_MAX_DATA_SIZE) {
  2502. icnss_pr_err("Invalid parameters for diag read: output %pK, data_len %u\n",
  2503. output, data_len);
  2504. ret = -EINVAL;
  2505. goto out;
  2506. }
  2507. if (!test_bit(ICNSS_FW_READY, &priv->state) ||
  2508. !test_bit(ICNSS_POWER_ON, &priv->state)) {
  2509. icnss_pr_err("Invalid state for diag read: 0x%lx\n",
  2510. priv->state);
  2511. ret = -EINVAL;
  2512. goto out;
  2513. }
  2514. ret = wlfw_athdiag_read_send_sync_msg(priv, offset, mem_type,
  2515. data_len, output);
  2516. out:
  2517. return ret;
  2518. }
  2519. EXPORT_SYMBOL(icnss_athdiag_read);
  2520. int icnss_athdiag_write(struct device *dev, uint32_t offset,
  2521. uint32_t mem_type, uint32_t data_len,
  2522. uint8_t *input)
  2523. {
  2524. int ret = 0;
  2525. struct icnss_priv *priv = dev_get_drvdata(dev);
  2526. if (priv->magic != ICNSS_MAGIC) {
  2527. icnss_pr_err("Invalid drvdata for diag write: dev %pK, data %pK, magic 0x%x\n",
  2528. dev, priv, priv->magic);
  2529. return -EINVAL;
  2530. }
  2531. if (!input || data_len == 0
  2532. || data_len > WLFW_MAX_DATA_SIZE) {
  2533. icnss_pr_err("Invalid parameters for diag write: input %pK, data_len %u\n",
  2534. input, data_len);
  2535. ret = -EINVAL;
  2536. goto out;
  2537. }
  2538. if (!test_bit(ICNSS_FW_READY, &priv->state) ||
  2539. !test_bit(ICNSS_POWER_ON, &priv->state)) {
  2540. icnss_pr_err("Invalid state for diag write: 0x%lx\n",
  2541. priv->state);
  2542. ret = -EINVAL;
  2543. goto out;
  2544. }
  2545. ret = wlfw_athdiag_write_send_sync_msg(priv, offset, mem_type,
  2546. data_len, input);
  2547. out:
  2548. return ret;
  2549. }
  2550. EXPORT_SYMBOL(icnss_athdiag_write);
  2551. int icnss_wlan_enable(struct device *dev, struct icnss_wlan_enable_cfg *config,
  2552. enum icnss_driver_mode mode,
  2553. const char *host_version)
  2554. {
  2555. struct icnss_priv *priv = dev_get_drvdata(dev);
  2556. if (test_bit(ICNSS_FW_DOWN, &priv->state) ||
  2557. !test_bit(ICNSS_FW_READY, &priv->state)) {
  2558. icnss_pr_err("FW down, ignoring wlan_enable state: 0x%lx\n",
  2559. priv->state);
  2560. return -EINVAL;
  2561. }
  2562. if (test_bit(ICNSS_MODE_ON, &priv->state)) {
  2563. icnss_pr_err("Already Mode on, ignoring wlan_enable state: 0x%lx\n",
  2564. priv->state);
  2565. return -EINVAL;
  2566. }
  2567. if (priv->wpss_supported &&
  2568. !priv->dms.nv_mac_not_prov && !priv->dms.mac_valid)
  2569. icnss_setup_dms_mac(priv);
  2570. return icnss_send_wlan_enable_to_fw(priv, config, mode, host_version);
  2571. }
  2572. EXPORT_SYMBOL(icnss_wlan_enable);
  2573. int icnss_wlan_disable(struct device *dev, enum icnss_driver_mode mode)
  2574. {
  2575. struct icnss_priv *priv = dev_get_drvdata(dev);
  2576. if (test_bit(ICNSS_FW_DOWN, &priv->state)) {
  2577. icnss_pr_dbg("FW down, ignoring wlan_disable state: 0x%lx\n",
  2578. priv->state);
  2579. return 0;
  2580. }
  2581. return icnss_send_wlan_disable_to_fw(priv);
  2582. }
  2583. EXPORT_SYMBOL(icnss_wlan_disable);
  2584. bool icnss_is_qmi_disable(struct device *dev)
  2585. {
  2586. return test_bit(SKIP_QMI, &penv->ctrl_params.quirks) ? true : false;
  2587. }
  2588. EXPORT_SYMBOL(icnss_is_qmi_disable);
  2589. int icnss_get_ce_id(struct device *dev, int irq)
  2590. {
  2591. int i;
  2592. if (!penv || !penv->pdev || !dev)
  2593. return -ENODEV;
  2594. for (i = 0; i < ICNSS_MAX_IRQ_REGISTRATIONS; i++) {
  2595. if (penv->ce_irqs[i] == irq)
  2596. return i;
  2597. }
  2598. icnss_pr_err("No matching CE id for irq %d\n", irq);
  2599. return -EINVAL;
  2600. }
  2601. EXPORT_SYMBOL(icnss_get_ce_id);
  2602. int icnss_get_irq(struct device *dev, int ce_id)
  2603. {
  2604. int irq;
  2605. if (!penv || !penv->pdev || !dev)
  2606. return -ENODEV;
  2607. if (ce_id >= ICNSS_MAX_IRQ_REGISTRATIONS)
  2608. return -EINVAL;
  2609. irq = penv->ce_irqs[ce_id];
  2610. return irq;
  2611. }
  2612. EXPORT_SYMBOL(icnss_get_irq);
  2613. struct iommu_domain *icnss_smmu_get_domain(struct device *dev)
  2614. {
  2615. struct icnss_priv *priv = dev_get_drvdata(dev);
  2616. if (!priv) {
  2617. icnss_pr_err("Invalid drvdata: dev %pK\n", dev);
  2618. return NULL;
  2619. }
  2620. return priv->iommu_domain;
  2621. }
  2622. EXPORT_SYMBOL(icnss_smmu_get_domain);
  2623. int icnss_smmu_map(struct device *dev,
  2624. phys_addr_t paddr, uint32_t *iova_addr, size_t size)
  2625. {
  2626. struct icnss_priv *priv = dev_get_drvdata(dev);
  2627. int flag = IOMMU_READ | IOMMU_WRITE;
  2628. bool dma_coherent = false;
  2629. unsigned long iova;
  2630. int prop_len = 0;
  2631. size_t len;
  2632. int ret = 0;
  2633. if (!priv) {
  2634. icnss_pr_err("Invalid drvdata: dev %pK, data %pK\n",
  2635. dev, priv);
  2636. return -EINVAL;
  2637. }
  2638. if (!iova_addr) {
  2639. icnss_pr_err("iova_addr is NULL, paddr %pa, size %zu\n",
  2640. &paddr, size);
  2641. return -EINVAL;
  2642. }
  2643. len = roundup(size + paddr - rounddown(paddr, PAGE_SIZE), PAGE_SIZE);
  2644. iova = roundup(priv->smmu_iova_ipa_current, PAGE_SIZE);
  2645. if (of_get_property(dev->of_node, "qcom,iommu-geometry", &prop_len) &&
  2646. iova >= priv->smmu_iova_ipa_start + priv->smmu_iova_ipa_len) {
  2647. icnss_pr_err("No IOVA space to map, iova %lx, smmu_iova_ipa_start %pad, smmu_iova_ipa_len %zu\n",
  2648. iova,
  2649. &priv->smmu_iova_ipa_start,
  2650. priv->smmu_iova_ipa_len);
  2651. return -ENOMEM;
  2652. }
  2653. dma_coherent = of_property_read_bool(dev->of_node, "dma-coherent");
  2654. icnss_pr_dbg("dma-coherent is %s\n",
  2655. dma_coherent ? "enabled" : "disabled");
  2656. if (dma_coherent)
  2657. flag |= IOMMU_CACHE;
  2658. icnss_pr_dbg("IOMMU Map: iova %lx, len %zu\n", iova, len);
  2659. ret = iommu_map(priv->iommu_domain, iova,
  2660. rounddown(paddr, PAGE_SIZE), len,
  2661. flag);
  2662. if (ret) {
  2663. icnss_pr_err("PA to IOVA mapping failed, ret %d\n", ret);
  2664. return ret;
  2665. }
  2666. priv->smmu_iova_ipa_current = iova + len;
  2667. *iova_addr = (uint32_t)(iova + paddr - rounddown(paddr, PAGE_SIZE));
  2668. icnss_pr_dbg("IOVA addr mapped to physical addr %lx\n", *iova_addr);
  2669. return 0;
  2670. }
  2671. EXPORT_SYMBOL(icnss_smmu_map);
  2672. int icnss_smmu_unmap(struct device *dev,
  2673. uint32_t iova_addr, size_t size)
  2674. {
  2675. struct icnss_priv *priv = dev_get_drvdata(dev);
  2676. unsigned long iova;
  2677. size_t len, unmapped_len;
  2678. if (!priv) {
  2679. icnss_pr_err("Invalid drvdata: dev %pK, data %pK\n",
  2680. dev, priv);
  2681. return -EINVAL;
  2682. }
  2683. if (!iova_addr) {
  2684. icnss_pr_err("iova_addr is NULL, size %zu\n",
  2685. size);
  2686. return -EINVAL;
  2687. }
  2688. len = roundup(size + iova_addr - rounddown(iova_addr, PAGE_SIZE),
  2689. PAGE_SIZE);
  2690. iova = rounddown(iova_addr, PAGE_SIZE);
  2691. if (iova >= priv->smmu_iova_ipa_start + priv->smmu_iova_ipa_len) {
  2692. icnss_pr_err("Out of IOVA space during unmap, iova %lx, smmu_iova_ipa_start %pad, smmu_iova_ipa_len %zu\n",
  2693. iova,
  2694. &priv->smmu_iova_ipa_start,
  2695. priv->smmu_iova_ipa_len);
  2696. return -ENOMEM;
  2697. }
  2698. icnss_pr_dbg("IOMMU Unmap: iova %lx, len %zu\n",
  2699. iova, len);
  2700. unmapped_len = iommu_unmap(priv->iommu_domain, iova, len);
  2701. if (unmapped_len != len) {
  2702. icnss_pr_err("Failed to unmap, %zu\n", unmapped_len);
  2703. return -EINVAL;
  2704. }
  2705. priv->smmu_iova_ipa_current = iova;
  2706. return 0;
  2707. }
  2708. EXPORT_SYMBOL(icnss_smmu_unmap);
  2709. unsigned int icnss_socinfo_get_serial_number(struct device *dev)
  2710. {
  2711. return socinfo_get_serial_number();
  2712. }
  2713. EXPORT_SYMBOL(icnss_socinfo_get_serial_number);
  2714. int icnss_trigger_recovery(struct device *dev)
  2715. {
  2716. int ret = 0;
  2717. struct icnss_priv *priv = dev_get_drvdata(dev);
  2718. if (priv->magic != ICNSS_MAGIC) {
  2719. icnss_pr_err("Invalid drvdata: magic 0x%x\n", priv->magic);
  2720. ret = -EINVAL;
  2721. goto out;
  2722. }
  2723. if (test_bit(ICNSS_PD_RESTART, &priv->state)) {
  2724. icnss_pr_err("PD recovery already in progress: state: 0x%lx\n",
  2725. priv->state);
  2726. ret = -EPERM;
  2727. goto out;
  2728. }
  2729. if (priv->device_id == WCN6750_DEVICE_ID) {
  2730. icnss_pr_vdbg("Initiate Root PD restart");
  2731. ret = icnss_send_smp2p(priv, ICNSS_TRIGGER_SSR,
  2732. ICNSS_SMP2P_OUT_POWER_SAVE);
  2733. if (!ret)
  2734. set_bit(ICNSS_HOST_TRIGGERED_PDR, &priv->state);
  2735. return ret;
  2736. }
  2737. if (!test_bit(ICNSS_PDR_REGISTERED, &priv->state)) {
  2738. icnss_pr_err("PD restart not enabled to trigger recovery: state: 0x%lx\n",
  2739. priv->state);
  2740. ret = -EOPNOTSUPP;
  2741. goto out;
  2742. }
  2743. icnss_pr_warn("Initiate PD restart at WLAN FW, state: 0x%lx\n",
  2744. priv->state);
  2745. ret = pdr_restart_pd(priv->pdr_handle, priv->pdr_service);
  2746. if (!ret)
  2747. set_bit(ICNSS_HOST_TRIGGERED_PDR, &priv->state);
  2748. out:
  2749. return ret;
  2750. }
  2751. EXPORT_SYMBOL(icnss_trigger_recovery);
  2752. int icnss_idle_shutdown(struct device *dev)
  2753. {
  2754. struct icnss_priv *priv = dev_get_drvdata(dev);
  2755. if (!priv) {
  2756. icnss_pr_err("Invalid drvdata: dev %pK", dev);
  2757. return -EINVAL;
  2758. }
  2759. if (priv->is_ssr || test_bit(ICNSS_PDR, &priv->state) ||
  2760. test_bit(ICNSS_REJUVENATE, &priv->state)) {
  2761. icnss_pr_err("SSR/PDR is already in-progress during idle shutdown\n");
  2762. return -EBUSY;
  2763. }
  2764. return icnss_driver_event_post(priv, ICNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  2765. ICNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  2766. }
  2767. EXPORT_SYMBOL(icnss_idle_shutdown);
  2768. int icnss_idle_restart(struct device *dev)
  2769. {
  2770. struct icnss_priv *priv = dev_get_drvdata(dev);
  2771. if (!priv) {
  2772. icnss_pr_err("Invalid drvdata: dev %pK", dev);
  2773. return -EINVAL;
  2774. }
  2775. if (priv->is_ssr || test_bit(ICNSS_PDR, &priv->state) ||
  2776. test_bit(ICNSS_REJUVENATE, &priv->state)) {
  2777. icnss_pr_err("SSR/PDR is already in-progress during idle restart\n");
  2778. return -EBUSY;
  2779. }
  2780. return icnss_driver_event_post(priv, ICNSS_DRIVER_EVENT_IDLE_RESTART,
  2781. ICNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  2782. }
  2783. EXPORT_SYMBOL(icnss_idle_restart);
  2784. int icnss_exit_power_save(struct device *dev)
  2785. {
  2786. struct icnss_priv *priv = dev_get_drvdata(dev);
  2787. icnss_pr_vdbg("Calling Exit Power Save\n");
  2788. if (test_bit(ICNSS_PD_RESTART, &priv->state) ||
  2789. !test_bit(ICNSS_MODE_ON, &priv->state))
  2790. return 0;
  2791. return icnss_send_smp2p(priv, ICNSS_POWER_SAVE_EXIT,
  2792. ICNSS_SMP2P_OUT_POWER_SAVE);
  2793. }
  2794. EXPORT_SYMBOL(icnss_exit_power_save);
  2795. int icnss_prevent_l1(struct device *dev)
  2796. {
  2797. struct icnss_priv *priv = dev_get_drvdata(dev);
  2798. if (test_bit(ICNSS_PD_RESTART, &priv->state) ||
  2799. !test_bit(ICNSS_MODE_ON, &priv->state))
  2800. return 0;
  2801. return icnss_send_smp2p(priv, ICNSS_PCI_EP_POWER_SAVE_EXIT,
  2802. ICNSS_SMP2P_OUT_EP_POWER_SAVE);
  2803. }
  2804. EXPORT_SYMBOL(icnss_prevent_l1);
  2805. void icnss_allow_l1(struct device *dev)
  2806. {
  2807. struct icnss_priv *priv = dev_get_drvdata(dev);
  2808. if (test_bit(ICNSS_PD_RESTART, &priv->state) ||
  2809. !test_bit(ICNSS_MODE_ON, &priv->state))
  2810. return;
  2811. icnss_send_smp2p(priv, ICNSS_PCI_EP_POWER_SAVE_ENTER,
  2812. ICNSS_SMP2P_OUT_EP_POWER_SAVE);
  2813. }
  2814. EXPORT_SYMBOL(icnss_allow_l1);
  2815. void icnss_allow_recursive_recovery(struct device *dev)
  2816. {
  2817. struct icnss_priv *priv = dev_get_drvdata(dev);
  2818. priv->allow_recursive_recovery = true;
  2819. icnss_pr_info("Recursive recovery allowed for WLAN\n");
  2820. }
  2821. void icnss_disallow_recursive_recovery(struct device *dev)
  2822. {
  2823. struct icnss_priv *priv = dev_get_drvdata(dev);
  2824. priv->allow_recursive_recovery = false;
  2825. icnss_pr_info("Recursive recovery disallowed for WLAN\n");
  2826. }
  2827. static int icnss_create_shutdown_sysfs(struct icnss_priv *priv)
  2828. {
  2829. struct kobject *icnss_kobject;
  2830. int ret = 0;
  2831. atomic_set(&priv->is_shutdown, false);
  2832. icnss_kobject = kobject_create_and_add("shutdown_wlan", kernel_kobj);
  2833. if (!icnss_kobject) {
  2834. icnss_pr_err("Unable to create shutdown_wlan kernel object");
  2835. return -EINVAL;
  2836. }
  2837. priv->icnss_kobject = icnss_kobject;
  2838. ret = sysfs_create_file(icnss_kobject, &icnss_sysfs_attribute.attr);
  2839. if (ret) {
  2840. icnss_pr_err("Unable to create icnss sysfs file err:%d", ret);
  2841. return ret;
  2842. }
  2843. return ret;
  2844. }
  2845. static void icnss_destroy_shutdown_sysfs(struct icnss_priv *priv)
  2846. {
  2847. struct kobject *icnss_kobject;
  2848. icnss_kobject = priv->icnss_kobject;
  2849. if (icnss_kobject)
  2850. kobject_put(icnss_kobject);
  2851. }
  2852. static ssize_t qdss_tr_start_store(struct device *dev,
  2853. struct device_attribute *attr,
  2854. const char *buf, size_t count)
  2855. {
  2856. struct icnss_priv *priv = dev_get_drvdata(dev);
  2857. wlfw_qdss_trace_start(priv);
  2858. icnss_pr_dbg("Received QDSS start command\n");
  2859. return count;
  2860. }
  2861. static ssize_t qdss_tr_stop_store(struct device *dev,
  2862. struct device_attribute *attr,
  2863. const char *user_buf, size_t count)
  2864. {
  2865. struct icnss_priv *priv = dev_get_drvdata(dev);
  2866. u32 option = 0;
  2867. if (sscanf(user_buf, "%du", &option) != 1)
  2868. return -EINVAL;
  2869. wlfw_qdss_trace_stop(priv, option);
  2870. icnss_pr_dbg("Received QDSS stop command\n");
  2871. return count;
  2872. }
  2873. static ssize_t qdss_conf_download_store(struct device *dev,
  2874. struct device_attribute *attr,
  2875. const char *buf, size_t count)
  2876. {
  2877. struct icnss_priv *priv = dev_get_drvdata(dev);
  2878. icnss_wlfw_qdss_dnld_send_sync(priv);
  2879. icnss_pr_dbg("Received QDSS download config command\n");
  2880. return count;
  2881. }
  2882. static ssize_t hw_trc_override_store(struct device *dev,
  2883. struct device_attribute *attr,
  2884. const char *buf, size_t count)
  2885. {
  2886. struct icnss_priv *priv = dev_get_drvdata(dev);
  2887. int tmp = 0;
  2888. if (sscanf(buf, "%du", &tmp) != 1)
  2889. return -EINVAL;
  2890. priv->hw_trc_override = tmp;
  2891. icnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  2892. return count;
  2893. }
  2894. static void icnss_wpss_load(struct work_struct *wpss_load_work)
  2895. {
  2896. struct icnss_priv *priv = icnss_get_plat_priv();
  2897. phandle rproc_phandle;
  2898. int ret;
  2899. if (of_property_read_u32(priv->pdev->dev.of_node, "qcom,rproc-handle",
  2900. &rproc_phandle)) {
  2901. icnss_pr_err("error reading rproc phandle\n");
  2902. return;
  2903. }
  2904. priv->rproc = rproc_get_by_phandle(rproc_phandle);
  2905. if (IS_ERR_OR_NULL(priv->rproc)) {
  2906. icnss_pr_err("rproc not found");
  2907. return;
  2908. }
  2909. ret = rproc_boot(priv->rproc);
  2910. if (ret) {
  2911. icnss_pr_err("Failed to boot wpss rproc, ret: %d", ret);
  2912. rproc_put(priv->rproc);
  2913. }
  2914. }
  2915. static inline void icnss_wpss_unload(struct icnss_priv *priv)
  2916. {
  2917. if (priv && priv->rproc) {
  2918. rproc_shutdown(priv->rproc);
  2919. rproc_put(priv->rproc);
  2920. priv->rproc = NULL;
  2921. }
  2922. }
  2923. static ssize_t wpss_boot_store(struct device *dev,
  2924. struct device_attribute *attr,
  2925. const char *buf, size_t count)
  2926. {
  2927. struct icnss_priv *priv = dev_get_drvdata(dev);
  2928. int wpss_rproc = 0;
  2929. if (!priv->wpss_supported)
  2930. return count;
  2931. if (sscanf(buf, "%du", &wpss_rproc) != 1) {
  2932. icnss_pr_err("Failed to read wpss rproc info");
  2933. return -EINVAL;
  2934. }
  2935. icnss_pr_dbg("WPSS Remote Processor: %s", wpss_rproc ? "GET" : "PUT");
  2936. if (wpss_rproc == 1)
  2937. schedule_work(&wpss_loader);
  2938. else if (wpss_rproc == 0)
  2939. icnss_wpss_unload(priv);
  2940. return count;
  2941. }
  2942. static ssize_t wlan_en_delay_store(struct device *dev,
  2943. struct device_attribute *attr,
  2944. const char *buf, size_t count)
  2945. {
  2946. struct icnss_priv *priv = dev_get_drvdata(dev);
  2947. uint32_t wlan_en_delay = 0;
  2948. if (priv->device_id != WCN6750_DEVICE_ID)
  2949. return count;
  2950. if (sscanf(buf, "%du", &wlan_en_delay) != 1) {
  2951. icnss_pr_err("Failed to read wlan_en_delay");
  2952. return -EINVAL;
  2953. }
  2954. icnss_pr_dbg("WLAN_EN delay: %dms", wlan_en_delay);
  2955. priv->wlan_en_delay_ms = wlan_en_delay;
  2956. return count;
  2957. }
  2958. static DEVICE_ATTR_WO(qdss_tr_start);
  2959. static DEVICE_ATTR_WO(qdss_tr_stop);
  2960. static DEVICE_ATTR_WO(qdss_conf_download);
  2961. static DEVICE_ATTR_WO(hw_trc_override);
  2962. static DEVICE_ATTR_WO(wpss_boot);
  2963. static DEVICE_ATTR_WO(wlan_en_delay);
  2964. static struct attribute *icnss_attrs[] = {
  2965. &dev_attr_qdss_tr_start.attr,
  2966. &dev_attr_qdss_tr_stop.attr,
  2967. &dev_attr_qdss_conf_download.attr,
  2968. &dev_attr_hw_trc_override.attr,
  2969. &dev_attr_wpss_boot.attr,
  2970. &dev_attr_wlan_en_delay.attr,
  2971. NULL,
  2972. };
  2973. static struct attribute_group icnss_attr_group = {
  2974. .attrs = icnss_attrs,
  2975. };
  2976. static int icnss_create_sysfs_link(struct icnss_priv *priv)
  2977. {
  2978. struct device *dev = &priv->pdev->dev;
  2979. int ret;
  2980. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "icnss");
  2981. if (ret) {
  2982. icnss_pr_err("Failed to create icnss link, err = %d\n",
  2983. ret);
  2984. goto out;
  2985. }
  2986. return 0;
  2987. out:
  2988. return ret;
  2989. }
  2990. static void icnss_remove_sysfs_link(struct icnss_priv *priv)
  2991. {
  2992. sysfs_remove_link(kernel_kobj, "icnss");
  2993. }
  2994. static int icnss_sysfs_create(struct icnss_priv *priv)
  2995. {
  2996. int ret = 0;
  2997. ret = devm_device_add_group(&priv->pdev->dev,
  2998. &icnss_attr_group);
  2999. if (ret) {
  3000. icnss_pr_err("Failed to create icnss device group, err = %d\n",
  3001. ret);
  3002. goto out;
  3003. }
  3004. icnss_create_sysfs_link(priv);
  3005. ret = icnss_create_shutdown_sysfs(priv);
  3006. if (ret)
  3007. goto remove_icnss_group;
  3008. return 0;
  3009. remove_icnss_group:
  3010. devm_device_remove_group(&priv->pdev->dev, &icnss_attr_group);
  3011. out:
  3012. return ret;
  3013. }
  3014. static void icnss_sysfs_destroy(struct icnss_priv *priv)
  3015. {
  3016. icnss_destroy_shutdown_sysfs(priv);
  3017. icnss_remove_sysfs_link(priv);
  3018. devm_device_remove_group(&priv->pdev->dev, &icnss_attr_group);
  3019. }
  3020. static int icnss_resource_parse(struct icnss_priv *priv)
  3021. {
  3022. int ret = 0, i = 0;
  3023. struct platform_device *pdev = priv->pdev;
  3024. struct device *dev = &pdev->dev;
  3025. struct resource *res;
  3026. u32 int_prop;
  3027. ret = icnss_get_vreg(priv);
  3028. if (ret) {
  3029. icnss_pr_err("Failed to get vreg, err = %d\n", ret);
  3030. goto out;
  3031. }
  3032. ret = icnss_get_clk(priv);
  3033. if (ret) {
  3034. icnss_pr_err("Failed to get clocks, err = %d\n", ret);
  3035. goto put_vreg;
  3036. }
  3037. if (priv->device_id == ADRASTEA_DEVICE_ID) {
  3038. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  3039. "membase");
  3040. if (!res) {
  3041. icnss_pr_err("Memory base not found in DT\n");
  3042. ret = -EINVAL;
  3043. goto put_clk;
  3044. }
  3045. priv->mem_base_pa = res->start;
  3046. priv->mem_base_va = devm_ioremap(dev, priv->mem_base_pa,
  3047. resource_size(res));
  3048. if (!priv->mem_base_va) {
  3049. icnss_pr_err("Memory base ioremap failed: phy addr: %pa\n",
  3050. &priv->mem_base_pa);
  3051. ret = -EINVAL;
  3052. goto put_clk;
  3053. }
  3054. icnss_pr_dbg("MEM_BASE pa: %pa, va: 0x%pK\n",
  3055. &priv->mem_base_pa,
  3056. priv->mem_base_va);
  3057. for (i = 0; i < ICNSS_MAX_IRQ_REGISTRATIONS; i++) {
  3058. res = platform_get_resource(priv->pdev,
  3059. IORESOURCE_IRQ, i);
  3060. if (!res) {
  3061. icnss_pr_err("Fail to get IRQ-%d\n", i);
  3062. ret = -ENODEV;
  3063. goto put_clk;
  3064. } else {
  3065. priv->ce_irqs[i] = res->start;
  3066. }
  3067. }
  3068. } else if (priv->device_id == WCN6750_DEVICE_ID) {
  3069. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  3070. "msi_addr");
  3071. if (!res) {
  3072. icnss_pr_err("MSI address not found in DT\n");
  3073. ret = -EINVAL;
  3074. goto put_clk;
  3075. }
  3076. priv->msi_addr_pa = res->start;
  3077. priv->msi_addr_iova = dma_map_resource(dev, priv->msi_addr_pa,
  3078. PAGE_SIZE,
  3079. DMA_FROM_DEVICE, 0);
  3080. if (dma_mapping_error(dev, priv->msi_addr_iova)) {
  3081. icnss_pr_err("MSI: failed to map msi address\n");
  3082. priv->msi_addr_iova = 0;
  3083. ret = -ENOMEM;
  3084. goto put_clk;
  3085. }
  3086. icnss_pr_dbg("MSI Addr pa: %pa, iova: 0x%pK\n",
  3087. &priv->msi_addr_pa,
  3088. priv->msi_addr_iova);
  3089. ret = of_property_read_u32_index(dev->of_node,
  3090. "interrupts",
  3091. 1,
  3092. &int_prop);
  3093. if (ret) {
  3094. icnss_pr_dbg("Read interrupt prop failed");
  3095. goto put_clk;
  3096. }
  3097. priv->msi_base_data = int_prop + 32;
  3098. icnss_pr_dbg(" MSI Base Data: %d, IRQ Index: %d\n",
  3099. priv->msi_base_data, int_prop);
  3100. icnss_get_msi_assignment(priv);
  3101. for (i = 0; i < msi_config.total_vectors; i++) {
  3102. res = platform_get_resource(priv->pdev,
  3103. IORESOURCE_IRQ, i);
  3104. if (!res) {
  3105. icnss_pr_err("Fail to get IRQ-%d\n", i);
  3106. ret = -ENODEV;
  3107. goto put_clk;
  3108. } else {
  3109. priv->srng_irqs[i] = res->start;
  3110. }
  3111. }
  3112. }
  3113. return 0;
  3114. put_clk:
  3115. icnss_put_clk(priv);
  3116. put_vreg:
  3117. icnss_put_vreg(priv);
  3118. out:
  3119. return ret;
  3120. }
  3121. static int icnss_msa_dt_parse(struct icnss_priv *priv)
  3122. {
  3123. int ret = 0;
  3124. struct platform_device *pdev = priv->pdev;
  3125. struct device *dev = &pdev->dev;
  3126. struct device_node *np = NULL;
  3127. u64 prop_size = 0;
  3128. const __be32 *addrp = NULL;
  3129. np = of_parse_phandle(dev->of_node,
  3130. "qcom,wlan-msa-fixed-region", 0);
  3131. if (np) {
  3132. addrp = of_get_address(np, 0, &prop_size, NULL);
  3133. if (!addrp) {
  3134. icnss_pr_err("Failed to get assigned-addresses or property\n");
  3135. ret = -EINVAL;
  3136. of_node_put(np);
  3137. goto out;
  3138. }
  3139. priv->msa_pa = of_translate_address(np, addrp);
  3140. if (priv->msa_pa == OF_BAD_ADDR) {
  3141. icnss_pr_err("Failed to translate MSA PA from device-tree\n");
  3142. ret = -EINVAL;
  3143. of_node_put(np);
  3144. goto out;
  3145. }
  3146. of_node_put(np);
  3147. priv->msa_va = memremap(priv->msa_pa,
  3148. (unsigned long)prop_size, MEMREMAP_WT);
  3149. if (!priv->msa_va) {
  3150. icnss_pr_err("MSA PA ioremap failed: phy addr: %pa\n",
  3151. &priv->msa_pa);
  3152. ret = -EINVAL;
  3153. goto out;
  3154. }
  3155. priv->msa_mem_size = prop_size;
  3156. } else {
  3157. ret = of_property_read_u32(dev->of_node, "qcom,wlan-msa-memory",
  3158. &priv->msa_mem_size);
  3159. if (ret || priv->msa_mem_size == 0) {
  3160. icnss_pr_err("Fail to get MSA Memory Size: %u ret: %d\n",
  3161. priv->msa_mem_size, ret);
  3162. goto out;
  3163. }
  3164. priv->msa_va = dmam_alloc_coherent(&pdev->dev,
  3165. priv->msa_mem_size, &priv->msa_pa, GFP_KERNEL);
  3166. if (!priv->msa_va) {
  3167. icnss_pr_err("DMA alloc failed for MSA\n");
  3168. ret = -ENOMEM;
  3169. goto out;
  3170. }
  3171. }
  3172. icnss_pr_dbg("MSA pa: %pa, MSA va: 0x%pK MSA Memory Size: 0x%x\n",
  3173. &priv->msa_pa, (void *)priv->msa_va, priv->msa_mem_size);
  3174. priv->use_prefix_path = of_property_read_bool(priv->pdev->dev.of_node,
  3175. "qcom,fw-prefix");
  3176. return 0;
  3177. out:
  3178. return ret;
  3179. }
  3180. static int icnss_smmu_fault_handler(struct iommu_domain *domain,
  3181. struct device *dev, unsigned long iova,
  3182. int flags, void *handler_token)
  3183. {
  3184. struct icnss_priv *priv = handler_token;
  3185. struct icnss_uevent_fw_down_data fw_down_data = {0};
  3186. icnss_fatal_err("SMMU fault happened with IOVA 0x%lx\n", iova);
  3187. if (!priv) {
  3188. icnss_pr_err("priv is NULL\n");
  3189. return -ENODEV;
  3190. }
  3191. if (test_bit(ICNSS_FW_READY, &priv->state)) {
  3192. fw_down_data.crashed = true;
  3193. icnss_call_driver_uevent(priv, ICNSS_UEVENT_FW_DOWN,
  3194. &fw_down_data);
  3195. }
  3196. icnss_trigger_recovery(&priv->pdev->dev);
  3197. /* IOMMU driver requires non-zero return value to print debug info. */
  3198. return -EINVAL;
  3199. }
  3200. static int icnss_smmu_dt_parse(struct icnss_priv *priv)
  3201. {
  3202. int ret = 0;
  3203. struct platform_device *pdev = priv->pdev;
  3204. struct device *dev = &pdev->dev;
  3205. const char *iommu_dma_type;
  3206. struct resource *res;
  3207. u32 addr_win[2];
  3208. ret = of_property_read_u32_array(dev->of_node,
  3209. "qcom,iommu-dma-addr-pool",
  3210. addr_win,
  3211. ARRAY_SIZE(addr_win));
  3212. if (ret) {
  3213. icnss_pr_err("SMMU IOVA base not found\n");
  3214. } else {
  3215. priv->smmu_iova_start = addr_win[0];
  3216. priv->smmu_iova_len = addr_win[1];
  3217. icnss_pr_dbg("SMMU IOVA start: %pa, len: %zx\n",
  3218. &priv->smmu_iova_start,
  3219. priv->smmu_iova_len);
  3220. priv->iommu_domain =
  3221. iommu_get_domain_for_dev(&pdev->dev);
  3222. ret = of_property_read_string(dev->of_node, "qcom,iommu-dma",
  3223. &iommu_dma_type);
  3224. if (!ret && !strcmp("fastmap", iommu_dma_type)) {
  3225. icnss_pr_dbg("SMMU S1 stage enabled\n");
  3226. priv->smmu_s1_enable = true;
  3227. if (priv->device_id == WCN6750_DEVICE_ID)
  3228. iommu_set_fault_handler(priv->iommu_domain,
  3229. icnss_smmu_fault_handler,
  3230. priv);
  3231. }
  3232. res = platform_get_resource_byname(pdev,
  3233. IORESOURCE_MEM,
  3234. "smmu_iova_ipa");
  3235. if (!res) {
  3236. icnss_pr_err("SMMU IOVA IPA not found\n");
  3237. } else {
  3238. priv->smmu_iova_ipa_start = res->start;
  3239. priv->smmu_iova_ipa_current = res->start;
  3240. priv->smmu_iova_ipa_len = resource_size(res);
  3241. icnss_pr_dbg("SMMU IOVA IPA start: %pa, len: %zx\n",
  3242. &priv->smmu_iova_ipa_start,
  3243. priv->smmu_iova_ipa_len);
  3244. }
  3245. }
  3246. return 0;
  3247. }
  3248. int icnss_get_iova(struct icnss_priv *priv, u64 *addr, u64 *size)
  3249. {
  3250. if (!priv)
  3251. return -ENODEV;
  3252. if (!priv->smmu_iova_len)
  3253. return -EINVAL;
  3254. *addr = priv->smmu_iova_start;
  3255. *size = priv->smmu_iova_len;
  3256. return 0;
  3257. }
  3258. int icnss_get_iova_ipa(struct icnss_priv *priv, u64 *addr, u64 *size)
  3259. {
  3260. if (!priv)
  3261. return -ENODEV;
  3262. if (!priv->smmu_iova_ipa_len)
  3263. return -EINVAL;
  3264. *addr = priv->smmu_iova_ipa_start;
  3265. *size = priv->smmu_iova_ipa_len;
  3266. return 0;
  3267. }
  3268. void icnss_add_fw_prefix_name(struct icnss_priv *priv, char *prefix_name,
  3269. char *name)
  3270. {
  3271. if (!priv)
  3272. return;
  3273. if (!priv->use_prefix_path) {
  3274. scnprintf(prefix_name, ICNSS_MAX_FILE_NAME, "%s", name);
  3275. return;
  3276. }
  3277. if (priv->device_id == ADRASTEA_DEVICE_ID)
  3278. scnprintf(prefix_name, ICNSS_MAX_FILE_NAME,
  3279. ADRASTEA_PATH_PREFIX "%s", name);
  3280. else
  3281. scnprintf(prefix_name, ICNSS_MAX_FILE_NAME,
  3282. QCA6750_PATH_PREFIX "%s", name);
  3283. icnss_pr_dbg("File added with prefix: %s\n", prefix_name);
  3284. }
  3285. static const struct platform_device_id icnss_platform_id_table[] = {
  3286. { .name = "wcn6750", .driver_data = WCN6750_DEVICE_ID, },
  3287. { .name = "adrastea", .driver_data = ADRASTEA_DEVICE_ID, },
  3288. { },
  3289. };
  3290. static const struct of_device_id icnss_dt_match[] = {
  3291. {
  3292. .compatible = "qcom,wcn6750",
  3293. .data = (void *)&icnss_platform_id_table[0]},
  3294. {
  3295. .compatible = "qcom,icnss",
  3296. .data = (void *)&icnss_platform_id_table[1]},
  3297. { },
  3298. };
  3299. MODULE_DEVICE_TABLE(of, icnss_dt_match);
  3300. static void icnss_init_control_params(struct icnss_priv *priv)
  3301. {
  3302. priv->ctrl_params.qmi_timeout = WLFW_TIMEOUT;
  3303. priv->ctrl_params.quirks = ICNSS_QUIRKS_DEFAULT;
  3304. priv->ctrl_params.bdf_type = ICNSS_BDF_TYPE_DEFAULT;
  3305. if (priv->device_id == WCN6750_DEVICE_ID ||
  3306. of_property_read_bool(priv->pdev->dev.of_node,
  3307. "wpss-support-enable"))
  3308. priv->wpss_supported = true;
  3309. if (of_property_read_bool(priv->pdev->dev.of_node,
  3310. "bdf-download-support"))
  3311. priv->bdf_download_support = true;
  3312. if (priv->bdf_download_support && priv->device_id == ADRASTEA_DEVICE_ID)
  3313. priv->ctrl_params.bdf_type = ICNSS_BDF_BIN;
  3314. }
  3315. static void icnss_read_device_configs(struct icnss_priv *priv)
  3316. {
  3317. if (of_property_read_bool(priv->pdev->dev.of_node,
  3318. "wlan-ipa-disabled")) {
  3319. set_bit(ICNSS_IPA_DISABLED, &priv->device_config);
  3320. }
  3321. }
  3322. static inline void icnss_runtime_pm_init(struct icnss_priv *priv)
  3323. {
  3324. pm_runtime_get_sync(&priv->pdev->dev);
  3325. pm_runtime_forbid(&priv->pdev->dev);
  3326. pm_runtime_set_active(&priv->pdev->dev);
  3327. pm_runtime_enable(&priv->pdev->dev);
  3328. }
  3329. static inline void icnss_runtime_pm_deinit(struct icnss_priv *priv)
  3330. {
  3331. pm_runtime_disable(&priv->pdev->dev);
  3332. pm_runtime_allow(&priv->pdev->dev);
  3333. pm_runtime_put_sync(&priv->pdev->dev);
  3334. }
  3335. static inline bool icnss_use_nv_mac(struct icnss_priv *priv)
  3336. {
  3337. return of_property_read_bool(priv->pdev->dev.of_node,
  3338. "use-nv-mac");
  3339. }
  3340. static void rproc_restart_level_notifier(void *data, struct rproc *rproc)
  3341. {
  3342. struct icnss_subsys_restart_level_data *restart_level_data;
  3343. icnss_pr_info("rproc name: %s recovery disable: %d",
  3344. rproc->name, rproc->recovery_disabled);
  3345. restart_level_data = kzalloc(sizeof(*restart_level_data), GFP_ATOMIC);
  3346. if (!restart_level_data)
  3347. return;
  3348. if (strnstr(rproc->name, "wpss", ICNSS_RPROC_LEN)) {
  3349. if (rproc->recovery_disabled)
  3350. restart_level_data->restart_level = ICNSS_DISABLE_M3_SSR;
  3351. else
  3352. restart_level_data->restart_level = ICNSS_ENABLE_M3_SSR;
  3353. icnss_driver_event_post(penv, ICNSS_DRIVER_EVENT_SUBSYS_RESTART_LEVEL,
  3354. 0, restart_level_data);
  3355. }
  3356. }
  3357. static int icnss_probe(struct platform_device *pdev)
  3358. {
  3359. int ret = 0;
  3360. struct device *dev = &pdev->dev;
  3361. struct icnss_priv *priv;
  3362. const struct of_device_id *of_id;
  3363. const struct platform_device_id *device_id;
  3364. if (dev_get_drvdata(dev)) {
  3365. icnss_pr_err("Driver is already initialized\n");
  3366. return -EEXIST;
  3367. }
  3368. of_id = of_match_device(icnss_dt_match, &pdev->dev);
  3369. if (!of_id || !of_id->data) {
  3370. icnss_pr_err("Failed to find of match device!\n");
  3371. ret = -ENODEV;
  3372. goto out_reset_drvdata;
  3373. }
  3374. device_id = of_id->data;
  3375. icnss_pr_dbg("Platform driver probe\n");
  3376. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  3377. if (!priv)
  3378. return -ENOMEM;
  3379. priv->magic = ICNSS_MAGIC;
  3380. dev_set_drvdata(dev, priv);
  3381. priv->pdev = pdev;
  3382. priv->device_id = device_id->driver_data;
  3383. priv->is_chain1_supported = true;
  3384. INIT_LIST_HEAD(&priv->vreg_list);
  3385. INIT_LIST_HEAD(&priv->clk_list);
  3386. icnss_allow_recursive_recovery(dev);
  3387. icnss_init_control_params(priv);
  3388. icnss_read_device_configs(priv);
  3389. ret = icnss_resource_parse(priv);
  3390. if (ret)
  3391. goto out_reset_drvdata;
  3392. ret = icnss_msa_dt_parse(priv);
  3393. if (ret)
  3394. goto out_free_resources;
  3395. ret = icnss_smmu_dt_parse(priv);
  3396. if (ret)
  3397. goto out_free_resources;
  3398. spin_lock_init(&priv->event_lock);
  3399. spin_lock_init(&priv->on_off_lock);
  3400. spin_lock_init(&priv->soc_wake_msg_lock);
  3401. mutex_init(&priv->dev_lock);
  3402. mutex_init(&priv->tcdev_lock);
  3403. priv->event_wq = alloc_workqueue("icnss_driver_event", WQ_UNBOUND, 1);
  3404. if (!priv->event_wq) {
  3405. icnss_pr_err("Workqueue creation failed\n");
  3406. ret = -EFAULT;
  3407. goto smmu_cleanup;
  3408. }
  3409. INIT_WORK(&priv->event_work, icnss_driver_event_work);
  3410. INIT_LIST_HEAD(&priv->event_list);
  3411. ret = icnss_register_fw_service(priv);
  3412. if (ret < 0) {
  3413. icnss_pr_err("fw service registration failed: %d\n", ret);
  3414. goto out_destroy_wq;
  3415. }
  3416. icnss_enable_recovery(priv);
  3417. icnss_debugfs_create(priv);
  3418. icnss_sysfs_create(priv);
  3419. ret = device_init_wakeup(&priv->pdev->dev, true);
  3420. if (ret)
  3421. icnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  3422. ret);
  3423. icnss_set_plat_priv(priv);
  3424. init_completion(&priv->unblock_shutdown);
  3425. if (priv->device_id == WCN6750_DEVICE_ID) {
  3426. priv->soc_wake_wq = alloc_workqueue("icnss_soc_wake_event",
  3427. WQ_UNBOUND|WQ_HIGHPRI, 1);
  3428. if (!priv->soc_wake_wq) {
  3429. icnss_pr_err("Soc wake Workqueue creation failed\n");
  3430. ret = -EFAULT;
  3431. goto out_unregister_fw_service;
  3432. }
  3433. INIT_WORK(&priv->soc_wake_msg_work, icnss_soc_wake_msg_work);
  3434. INIT_LIST_HEAD(&priv->soc_wake_msg_list);
  3435. ret = icnss_genl_init();
  3436. if (ret < 0)
  3437. icnss_pr_err("ICNSS genl init failed %d\n", ret);
  3438. init_completion(&priv->smp2p_soc_wake_wait);
  3439. icnss_runtime_pm_init(priv);
  3440. icnss_aop_mbox_init(priv);
  3441. set_bit(ICNSS_COLD_BOOT_CAL, &priv->state);
  3442. priv->bdf_download_support = true;
  3443. register_trace_android_vh_rproc_recovery_set(rproc_restart_level_notifier, NULL);
  3444. }
  3445. if (priv->wpss_supported) {
  3446. ret = icnss_dms_init(priv);
  3447. if (ret)
  3448. icnss_pr_err("ICNSS DMS init failed %d\n", ret);
  3449. priv->use_nv_mac = icnss_use_nv_mac(priv);
  3450. icnss_pr_dbg("NV MAC feature is %s\n",
  3451. priv->use_nv_mac ? "Mandatory":"Not Mandatory");
  3452. INIT_WORK(&wpss_loader, icnss_wpss_load);
  3453. }
  3454. INIT_LIST_HEAD(&priv->icnss_tcdev_list);
  3455. icnss_pr_info("Platform driver probed successfully\n");
  3456. return 0;
  3457. out_unregister_fw_service:
  3458. icnss_unregister_fw_service(priv);
  3459. out_destroy_wq:
  3460. destroy_workqueue(priv->event_wq);
  3461. smmu_cleanup:
  3462. priv->iommu_domain = NULL;
  3463. out_free_resources:
  3464. icnss_put_resources(priv);
  3465. out_reset_drvdata:
  3466. dev_set_drvdata(dev, NULL);
  3467. return ret;
  3468. }
  3469. void icnss_destroy_ramdump_device(struct icnss_ramdump_info *ramdump_info)
  3470. {
  3471. if (IS_ERR_OR_NULL(ramdump_info))
  3472. return;
  3473. device_unregister(ramdump_info->dev);
  3474. ida_simple_remove(&rd_minor_id, ramdump_info->minor);
  3475. kfree(ramdump_info);
  3476. }
  3477. static int icnss_remove(struct platform_device *pdev)
  3478. {
  3479. struct icnss_priv *priv = dev_get_drvdata(&pdev->dev);
  3480. icnss_pr_info("Removing driver: state: 0x%lx\n", priv->state);
  3481. device_init_wakeup(&priv->pdev->dev, false);
  3482. icnss_debugfs_destroy(priv);
  3483. icnss_sysfs_destroy(priv);
  3484. complete_all(&priv->unblock_shutdown);
  3485. icnss_destroy_ramdump_device(priv->msa0_dump_dev);
  3486. if (priv->wpss_supported) {
  3487. icnss_dms_deinit(priv);
  3488. icnss_wpss_early_ssr_unregister_notifier(priv);
  3489. icnss_wpss_ssr_unregister_notifier(priv);
  3490. } else {
  3491. icnss_modem_ssr_unregister_notifier(priv);
  3492. icnss_pdr_unregister_notifier(priv);
  3493. }
  3494. if (priv->device_id == WCN6750_DEVICE_ID) {
  3495. icnss_genl_exit();
  3496. icnss_runtime_pm_deinit(priv);
  3497. if (!IS_ERR_OR_NULL(priv->mbox_chan))
  3498. mbox_free_channel(priv->mbox_chan);
  3499. unregister_trace_android_vh_rproc_recovery_set(rproc_restart_level_notifier, NULL);
  3500. complete_all(&priv->smp2p_soc_wake_wait);
  3501. icnss_destroy_ramdump_device(priv->m3_dump_phyareg);
  3502. icnss_destroy_ramdump_device(priv->m3_dump_phydbg);
  3503. icnss_destroy_ramdump_device(priv->m3_dump_wmac0reg);
  3504. icnss_destroy_ramdump_device(priv->m3_dump_wcssdbg);
  3505. icnss_destroy_ramdump_device(priv->m3_dump_phyapdmem);
  3506. if (priv->soc_wake_wq)
  3507. destroy_workqueue(priv->soc_wake_wq);
  3508. }
  3509. class_destroy(priv->icnss_ramdump_class);
  3510. unregister_chrdev_region(priv->icnss_ramdump_dev, RAMDUMP_NUM_DEVICES);
  3511. icnss_unregister_fw_service(priv);
  3512. if (priv->event_wq)
  3513. destroy_workqueue(priv->event_wq);
  3514. priv->iommu_domain = NULL;
  3515. icnss_hw_power_off(priv);
  3516. icnss_put_resources(priv);
  3517. dev_set_drvdata(&pdev->dev, NULL);
  3518. return 0;
  3519. }
  3520. #ifdef CONFIG_PM_SLEEP
  3521. static int icnss_pm_suspend(struct device *dev)
  3522. {
  3523. struct icnss_priv *priv = dev_get_drvdata(dev);
  3524. int ret = 0;
  3525. if (priv->magic != ICNSS_MAGIC) {
  3526. icnss_pr_err("Invalid drvdata for pm suspend: dev %pK, data %pK, magic 0x%x\n",
  3527. dev, priv, priv->magic);
  3528. return -EINVAL;
  3529. }
  3530. icnss_pr_vdbg("PM Suspend, state: 0x%lx\n", priv->state);
  3531. if (!priv->ops || !priv->ops->pm_suspend ||
  3532. IS_ERR(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state) ||
  3533. !test_bit(ICNSS_DRIVER_PROBED, &priv->state))
  3534. return 0;
  3535. ret = priv->ops->pm_suspend(dev);
  3536. if (ret == 0) {
  3537. if (priv->device_id == WCN6750_DEVICE_ID) {
  3538. if (test_bit(ICNSS_PD_RESTART, &priv->state) ||
  3539. !test_bit(ICNSS_MODE_ON, &priv->state))
  3540. return 0;
  3541. ret = icnss_send_smp2p(priv, ICNSS_POWER_SAVE_ENTER,
  3542. ICNSS_SMP2P_OUT_POWER_SAVE);
  3543. }
  3544. priv->stats.pm_suspend++;
  3545. set_bit(ICNSS_PM_SUSPEND, &priv->state);
  3546. } else {
  3547. priv->stats.pm_suspend_err++;
  3548. }
  3549. return ret;
  3550. }
  3551. static int icnss_pm_resume(struct device *dev)
  3552. {
  3553. struct icnss_priv *priv = dev_get_drvdata(dev);
  3554. int ret = 0;
  3555. if (priv->magic != ICNSS_MAGIC) {
  3556. icnss_pr_err("Invalid drvdata for pm resume: dev %pK, data %pK, magic 0x%x\n",
  3557. dev, priv, priv->magic);
  3558. return -EINVAL;
  3559. }
  3560. icnss_pr_vdbg("PM resume, state: 0x%lx\n", priv->state);
  3561. if (!priv->ops || !priv->ops->pm_resume ||
  3562. IS_ERR(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state) ||
  3563. !test_bit(ICNSS_DRIVER_PROBED, &priv->state))
  3564. goto out;
  3565. ret = priv->ops->pm_resume(dev);
  3566. out:
  3567. if (ret == 0) {
  3568. priv->stats.pm_resume++;
  3569. clear_bit(ICNSS_PM_SUSPEND, &priv->state);
  3570. } else {
  3571. priv->stats.pm_resume_err++;
  3572. }
  3573. return ret;
  3574. }
  3575. static int icnss_pm_suspend_noirq(struct device *dev)
  3576. {
  3577. struct icnss_priv *priv = dev_get_drvdata(dev);
  3578. int ret = 0;
  3579. if (priv->magic != ICNSS_MAGIC) {
  3580. icnss_pr_err("Invalid drvdata for pm suspend_noirq: dev %pK, data %pK, magic 0x%x\n",
  3581. dev, priv, priv->magic);
  3582. return -EINVAL;
  3583. }
  3584. icnss_pr_vdbg("PM suspend_noirq, state: 0x%lx\n", priv->state);
  3585. if (!priv->ops || !priv->ops->suspend_noirq ||
  3586. !test_bit(ICNSS_DRIVER_PROBED, &priv->state))
  3587. goto out;
  3588. ret = priv->ops->suspend_noirq(dev);
  3589. out:
  3590. if (ret == 0) {
  3591. priv->stats.pm_suspend_noirq++;
  3592. set_bit(ICNSS_PM_SUSPEND_NOIRQ, &priv->state);
  3593. } else {
  3594. priv->stats.pm_suspend_noirq_err++;
  3595. }
  3596. return ret;
  3597. }
  3598. static int icnss_pm_resume_noirq(struct device *dev)
  3599. {
  3600. struct icnss_priv *priv = dev_get_drvdata(dev);
  3601. int ret = 0;
  3602. if (priv->magic != ICNSS_MAGIC) {
  3603. icnss_pr_err("Invalid drvdata for pm resume_noirq: dev %pK, data %pK, magic 0x%x\n",
  3604. dev, priv, priv->magic);
  3605. return -EINVAL;
  3606. }
  3607. icnss_pr_vdbg("PM resume_noirq, state: 0x%lx\n", priv->state);
  3608. if (!priv->ops || !priv->ops->resume_noirq ||
  3609. !test_bit(ICNSS_DRIVER_PROBED, &priv->state))
  3610. goto out;
  3611. ret = priv->ops->resume_noirq(dev);
  3612. out:
  3613. if (ret == 0) {
  3614. priv->stats.pm_resume_noirq++;
  3615. clear_bit(ICNSS_PM_SUSPEND_NOIRQ, &priv->state);
  3616. } else {
  3617. priv->stats.pm_resume_noirq_err++;
  3618. }
  3619. return ret;
  3620. }
  3621. static int icnss_pm_runtime_suspend(struct device *dev)
  3622. {
  3623. struct icnss_priv *priv = dev_get_drvdata(dev);
  3624. int ret = 0;
  3625. if (priv->device_id != WCN6750_DEVICE_ID) {
  3626. icnss_pr_err("Ignore runtime suspend:\n");
  3627. goto out;
  3628. }
  3629. if (priv->magic != ICNSS_MAGIC) {
  3630. icnss_pr_err("Invalid drvdata for runtime suspend: dev %pK, data %pK, magic 0x%x\n",
  3631. dev, priv, priv->magic);
  3632. return -EINVAL;
  3633. }
  3634. if (!priv->ops || !priv->ops->runtime_suspend ||
  3635. IS_ERR(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state))
  3636. goto out;
  3637. icnss_pr_vdbg("Runtime suspend\n");
  3638. ret = priv->ops->runtime_suspend(dev);
  3639. if (!ret) {
  3640. if (test_bit(ICNSS_PD_RESTART, &priv->state) ||
  3641. !test_bit(ICNSS_MODE_ON, &priv->state))
  3642. return 0;
  3643. ret = icnss_send_smp2p(priv, ICNSS_POWER_SAVE_ENTER,
  3644. ICNSS_SMP2P_OUT_POWER_SAVE);
  3645. }
  3646. out:
  3647. return ret;
  3648. }
  3649. static int icnss_pm_runtime_resume(struct device *dev)
  3650. {
  3651. struct icnss_priv *priv = dev_get_drvdata(dev);
  3652. int ret = 0;
  3653. if (priv->device_id != WCN6750_DEVICE_ID) {
  3654. icnss_pr_err("Ignore runtime resume:\n");
  3655. goto out;
  3656. }
  3657. if (priv->magic != ICNSS_MAGIC) {
  3658. icnss_pr_err("Invalid drvdata for runtime resume: dev %pK, data %pK, magic 0x%x\n",
  3659. dev, priv, priv->magic);
  3660. return -EINVAL;
  3661. }
  3662. if (!priv->ops || !priv->ops->runtime_resume ||
  3663. IS_ERR(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state))
  3664. goto out;
  3665. icnss_pr_vdbg("Runtime resume, state: 0x%lx\n", priv->state);
  3666. ret = priv->ops->runtime_resume(dev);
  3667. out:
  3668. return ret;
  3669. }
  3670. static int icnss_pm_runtime_idle(struct device *dev)
  3671. {
  3672. struct icnss_priv *priv = dev_get_drvdata(dev);
  3673. if (priv->device_id != WCN6750_DEVICE_ID) {
  3674. icnss_pr_err("Ignore runtime idle:\n");
  3675. goto out;
  3676. }
  3677. icnss_pr_vdbg("Runtime idle\n");
  3678. pm_request_autosuspend(dev);
  3679. out:
  3680. return -EBUSY;
  3681. }
  3682. #endif
  3683. static const struct dev_pm_ops icnss_pm_ops = {
  3684. SET_SYSTEM_SLEEP_PM_OPS(icnss_pm_suspend,
  3685. icnss_pm_resume)
  3686. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(icnss_pm_suspend_noirq,
  3687. icnss_pm_resume_noirq)
  3688. SET_RUNTIME_PM_OPS(icnss_pm_runtime_suspend, icnss_pm_runtime_resume,
  3689. icnss_pm_runtime_idle)
  3690. };
  3691. static struct platform_driver icnss_driver = {
  3692. .probe = icnss_probe,
  3693. .remove = icnss_remove,
  3694. .driver = {
  3695. .name = "icnss2",
  3696. .pm = &icnss_pm_ops,
  3697. .of_match_table = icnss_dt_match,
  3698. },
  3699. };
  3700. static int __init icnss_initialize(void)
  3701. {
  3702. icnss_debug_init();
  3703. return platform_driver_register(&icnss_driver);
  3704. }
  3705. static void __exit icnss_exit(void)
  3706. {
  3707. platform_driver_unregister(&icnss_driver);
  3708. icnss_debug_deinit();
  3709. }
  3710. module_init(icnss_initialize);
  3711. module_exit(icnss_exit);
  3712. MODULE_LICENSE("GPL v2");
  3713. MODULE_DESCRIPTION("iWCN CORE platform driver");