qcs405.c 231 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/i2c.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/input.h>
  22. #include <linux/of_device.h>
  23. #include <linux/pm_qos.h>
  24. #include <linux/regulator/consumer.h>
  25. #include <sound/core.h>
  26. #include <sound/soc.h>
  27. #include <sound/soc-dapm.h>
  28. #include <sound/pcm.h>
  29. #include <sound/pcm_params.h>
  30. #include <sound/info.h>
  31. #include <dsp/audio_notifier.h>
  32. #include <dsp/q6afe-v2.h>
  33. #include <dsp/q6core.h>
  34. #include <dsp/msm_mdf.h>
  35. #include "device_event.h"
  36. #include "msm-pcm-routing-v2.h"
  37. #include "codecs/msm-cdc-pinctrl.h"
  38. #include "codecs/wcd9335.h"
  39. #include "codecs/wsa881x.h"
  40. #include "codecs/csra66x0/csra66x0.h"
  41. #include <dt-bindings/sound/audio-codec-port-types.h>
  42. #include "codecs/bolero/bolero-cdc.h"
  43. #include "codecs/bolero/wsa-macro.h"
  44. #define DRV_NAME "qcs405-asoc-snd"
  45. #define __CHIPSET__ "QCS405 "
  46. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  47. #define DEV_NAME_STR_LEN 32
  48. #define SAMPLING_RATE_8KHZ 8000
  49. #define SAMPLING_RATE_11P025KHZ 11025
  50. #define SAMPLING_RATE_16KHZ 16000
  51. #define SAMPLING_RATE_22P05KHZ 22050
  52. #define SAMPLING_RATE_32KHZ 32000
  53. #define SAMPLING_RATE_44P1KHZ 44100
  54. #define SAMPLING_RATE_48KHZ 48000
  55. #define SAMPLING_RATE_88P2KHZ 88200
  56. #define SAMPLING_RATE_96KHZ 96000
  57. #define SAMPLING_RATE_176P4KHZ 176400
  58. #define SAMPLING_RATE_192KHZ 192000
  59. #define SAMPLING_RATE_352P8KHZ 352800
  60. #define SAMPLING_RATE_384KHZ 384000
  61. #define SPDIF_TX_CORE_CLK_204_P8_MHZ 204800000
  62. #define TLMM_EAST_SPARE 0x07BA0000
  63. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 3
  68. #define TDM_CHANNEL_MAX 8
  69. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  70. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  71. enum {
  72. SLIM_RX_0 = 0,
  73. SLIM_RX_1,
  74. SLIM_RX_2,
  75. SLIM_RX_3,
  76. SLIM_RX_4,
  77. SLIM_RX_5,
  78. SLIM_RX_6,
  79. SLIM_RX_7,
  80. SLIM_RX_MAX,
  81. };
  82. enum {
  83. SLIM_TX_0 = 0,
  84. SLIM_TX_1,
  85. SLIM_TX_2,
  86. SLIM_TX_3,
  87. SLIM_TX_4,
  88. SLIM_TX_5,
  89. SLIM_TX_6,
  90. SLIM_TX_7,
  91. SLIM_TX_8,
  92. SLIM_TX_MAX,
  93. };
  94. enum {
  95. PRIM_MI2S = 0,
  96. SEC_MI2S,
  97. TERT_MI2S,
  98. QUAT_MI2S,
  99. QUIN_MI2S,
  100. MI2S_MAX,
  101. };
  102. enum {
  103. PRIM_AUX_PCM = 0,
  104. SEC_AUX_PCM,
  105. TERT_AUX_PCM,
  106. QUAT_AUX_PCM,
  107. QUIN_AUX_PCM,
  108. AUX_PCM_MAX,
  109. };
  110. enum {
  111. WSA_CDC_DMA_RX_0 = 0,
  112. WSA_CDC_DMA_RX_1,
  113. CDC_DMA_RX_MAX,
  114. };
  115. enum {
  116. WSA_CDC_DMA_TX_0 = 0,
  117. WSA_CDC_DMA_TX_1,
  118. WSA_CDC_DMA_TX_2,
  119. VA_CDC_DMA_TX_0,
  120. VA_CDC_DMA_TX_1,
  121. CDC_DMA_TX_MAX,
  122. };
  123. enum {
  124. PRIM_SPDIF_RX = 0,
  125. SEC_SPDIF_RX,
  126. SPDIF_RX_MAX,
  127. };
  128. enum {
  129. PRIM_SPDIF_TX = 0,
  130. SEC_SPDIF_TX,
  131. SPDIF_TX_MAX,
  132. };
  133. struct mi2s_conf {
  134. struct mutex lock;
  135. u32 ref_cnt;
  136. u32 msm_is_mi2s_master;
  137. };
  138. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  139. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  141. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  142. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  143. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  144. };
  145. struct dev_config {
  146. u32 sample_rate;
  147. u32 bit_format;
  148. u32 channels;
  149. };
  150. struct msm_wsa881x_dev_info {
  151. struct device_node *of_node;
  152. u32 index;
  153. };
  154. struct msm_csra66x0_dev_info {
  155. struct device_node *of_node;
  156. u32 index;
  157. };
  158. struct msm_asoc_mach_data {
  159. struct snd_info_entry *codec_root;
  160. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  161. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  162. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  163. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  164. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  165. int dmic_01_gpio_cnt;
  166. int dmic_23_gpio_cnt;
  167. int dmic_45_gpio_cnt;
  168. int dmic_67_gpio_cnt;
  169. struct regulator *tdm_micb_supply;
  170. u32 tdm_micb_voltage;
  171. u32 tdm_micb_current;
  172. };
  173. struct msm_asoc_wcd93xx_codec {
  174. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  175. enum afe_config_type config_type);
  176. };
  177. static const char *const pin_states[] = {"sleep", "i2s-active",
  178. "tdm-active"};
  179. enum {
  180. TDM_0 = 0,
  181. TDM_1,
  182. TDM_2,
  183. TDM_3,
  184. TDM_4,
  185. TDM_5,
  186. TDM_6,
  187. TDM_7,
  188. TDM_PORT_MAX,
  189. };
  190. enum {
  191. TDM_PRI = 0,
  192. TDM_SEC,
  193. TDM_TERT,
  194. TDM_QUAT,
  195. TDM_QUIN,
  196. TDM_INTERFACE_MAX,
  197. };
  198. struct tdm_port {
  199. u32 mode;
  200. u32 channel;
  201. };
  202. /* TDM default config */
  203. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  204. { /* PRI TDM */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  213. },
  214. { /* SEC TDM */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  223. },
  224. { /* TERT TDM */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  233. },
  234. { /* QUAT TDM */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  243. },
  244. { /* QUIN TDM */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  253. }
  254. };
  255. /* TDM default config */
  256. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  257. { /* PRI TDM */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  266. },
  267. { /* SEC TDM */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  276. },
  277. { /* TERT TDM */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  286. },
  287. { /* QUAT TDM */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  296. },
  297. { /* QUIN TDM */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  306. }
  307. };
  308. /* Default configuration of slimbus channels */
  309. static struct dev_config slim_rx_cfg[] = {
  310. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  318. };
  319. static struct dev_config slim_tx_cfg[] = {
  320. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  328. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  329. };
  330. /* Default configuration of Codec DMA Interface Tx */
  331. static struct dev_config cdc_dma_rx_cfg[] = {
  332. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  334. };
  335. /* Default configuration of Codec DMA Interface Rx */
  336. static struct dev_config cdc_dma_tx_cfg[] = {
  337. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  339. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  340. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  341. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  342. };
  343. static struct dev_config usb_rx_cfg = {
  344. .sample_rate = SAMPLING_RATE_48KHZ,
  345. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  346. .channels = 2,
  347. };
  348. static struct dev_config usb_tx_cfg = {
  349. .sample_rate = SAMPLING_RATE_48KHZ,
  350. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  351. .channels = 1,
  352. };
  353. static struct dev_config proxy_rx_cfg = {
  354. .sample_rate = SAMPLING_RATE_48KHZ,
  355. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  356. .channels = 2,
  357. };
  358. /* Default configuration of MI2S channels */
  359. static struct dev_config mi2s_rx_cfg[] = {
  360. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  361. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  362. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  363. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  364. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  365. };
  366. /* Default configuration of SPDIF channels */
  367. static struct dev_config spdif_rx_cfg[] = {
  368. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  369. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. };
  371. static struct dev_config spdif_tx_cfg[] = {
  372. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  373. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. };
  375. static struct dev_config mi2s_tx_cfg[] = {
  376. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  377. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  379. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  380. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  381. };
  382. static struct dev_config aux_pcm_rx_cfg[] = {
  383. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  384. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  385. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. };
  389. static struct dev_config aux_pcm_tx_cfg[] = {
  390. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  391. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  392. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  393. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. };
  396. static int msm_vi_feed_tx_ch = 2;
  397. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  398. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  399. "Five", "Six", "Seven",
  400. "Eight"};
  401. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  402. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  403. "S32_LE"};
  404. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  405. "KHZ_32", "KHZ_44P1", "KHZ_48",
  406. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  407. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  408. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  409. "KHZ_44P1", "KHZ_48",
  410. "KHZ_88P2", "KHZ_96"};
  411. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  412. "Five", "Six", "Seven",
  413. "Eight"};
  414. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  415. "Six", "Seven", "Eight"};
  416. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  417. "KHZ_16", "KHZ_22P05",
  418. "KHZ_32", "KHZ_44P1", "KHZ_48",
  419. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  420. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  421. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  422. "Five", "Six", "Seven", "Eight"};
  423. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  424. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  425. "KHZ_48", "KHZ_176P4",
  426. "KHZ_352P8"};
  427. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  428. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  429. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  430. "KHZ_48", "KHZ_96", "KHZ_192"};
  431. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  432. "Five", "Six", "Seven",
  433. "Eight"};
  434. static const char *const qos_text[] = {"Disable", "Enable"};
  435. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  436. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  437. "Five", "Six", "Seven",
  438. "Eight"};
  439. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  440. "KHZ_16", "KHZ_22P05",
  441. "KHZ_32", "KHZ_44P1", "KHZ_48",
  442. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  443. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  444. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  445. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  446. "KHZ_192"};
  447. static const char *spdif_ch_text[] = {"One", "Two"};
  448. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  449. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  527. cdc_dma_sample_rate_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  529. cdc_dma_sample_rate_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  531. cdc_dma_sample_rate_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  533. cdc_dma_sample_rate_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  535. cdc_dma_sample_rate_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  537. cdc_dma_sample_rate_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  539. cdc_dma_sample_rate_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  546. static struct platform_device *spdev;
  547. static bool is_initial_boot;
  548. static bool codec_reg_done;
  549. static struct snd_soc_aux_dev *msm_aux_dev;
  550. static struct snd_soc_codec_conf *msm_codec_conf;
  551. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  552. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  553. int enable, bool dapm);
  554. static int msm_wsa881x_init(struct snd_soc_component *component);
  555. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  556. struct snd_ctl_elem_value *ucontrol);
  557. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  558. {"MIC BIAS1", NULL, "MCLK TX"},
  559. {"MIC BIAS2", NULL, "MCLK TX"},
  560. {"MIC BIAS3", NULL, "MCLK TX"},
  561. {"MIC BIAS4", NULL, "MCLK TX"},
  562. };
  563. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  564. {
  565. AFE_API_VERSION_I2S_CONFIG,
  566. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  567. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  568. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  569. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  570. 0,
  571. },
  572. {
  573. AFE_API_VERSION_I2S_CONFIG,
  574. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  575. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  576. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  577. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  578. 0,
  579. },
  580. {
  581. AFE_API_VERSION_I2S_CONFIG,
  582. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  583. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  584. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  585. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  586. 0,
  587. },
  588. {
  589. AFE_API_VERSION_I2S_CONFIG,
  590. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  591. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  592. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  593. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  594. 0,
  595. },
  596. {
  597. AFE_API_VERSION_I2S_CONFIG,
  598. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  599. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  600. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  601. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  602. 0,
  603. }
  604. };
  605. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  606. static int slim_get_sample_rate_val(int sample_rate)
  607. {
  608. int sample_rate_val = 0;
  609. switch (sample_rate) {
  610. case SAMPLING_RATE_8KHZ:
  611. sample_rate_val = 0;
  612. break;
  613. case SAMPLING_RATE_16KHZ:
  614. sample_rate_val = 1;
  615. break;
  616. case SAMPLING_RATE_32KHZ:
  617. sample_rate_val = 2;
  618. break;
  619. case SAMPLING_RATE_44P1KHZ:
  620. sample_rate_val = 3;
  621. break;
  622. case SAMPLING_RATE_48KHZ:
  623. sample_rate_val = 4;
  624. break;
  625. case SAMPLING_RATE_88P2KHZ:
  626. sample_rate_val = 5;
  627. break;
  628. case SAMPLING_RATE_96KHZ:
  629. sample_rate_val = 6;
  630. break;
  631. case SAMPLING_RATE_176P4KHZ:
  632. sample_rate_val = 7;
  633. break;
  634. case SAMPLING_RATE_192KHZ:
  635. sample_rate_val = 8;
  636. break;
  637. case SAMPLING_RATE_352P8KHZ:
  638. sample_rate_val = 9;
  639. break;
  640. case SAMPLING_RATE_384KHZ:
  641. sample_rate_val = 10;
  642. break;
  643. default:
  644. sample_rate_val = 4;
  645. break;
  646. }
  647. return sample_rate_val;
  648. }
  649. static int slim_get_sample_rate(int value)
  650. {
  651. int sample_rate = 0;
  652. switch (value) {
  653. case 0:
  654. sample_rate = SAMPLING_RATE_8KHZ;
  655. break;
  656. case 1:
  657. sample_rate = SAMPLING_RATE_16KHZ;
  658. break;
  659. case 2:
  660. sample_rate = SAMPLING_RATE_32KHZ;
  661. break;
  662. case 3:
  663. sample_rate = SAMPLING_RATE_44P1KHZ;
  664. break;
  665. case 4:
  666. sample_rate = SAMPLING_RATE_48KHZ;
  667. break;
  668. case 5:
  669. sample_rate = SAMPLING_RATE_88P2KHZ;
  670. break;
  671. case 6:
  672. sample_rate = SAMPLING_RATE_96KHZ;
  673. break;
  674. case 7:
  675. sample_rate = SAMPLING_RATE_176P4KHZ;
  676. break;
  677. case 8:
  678. sample_rate = SAMPLING_RATE_192KHZ;
  679. break;
  680. case 9:
  681. sample_rate = SAMPLING_RATE_352P8KHZ;
  682. break;
  683. case 10:
  684. sample_rate = SAMPLING_RATE_384KHZ;
  685. break;
  686. default:
  687. sample_rate = SAMPLING_RATE_48KHZ;
  688. break;
  689. }
  690. return sample_rate;
  691. }
  692. static int slim_get_bit_format_val(int bit_format)
  693. {
  694. int val = 0;
  695. switch (bit_format) {
  696. case SNDRV_PCM_FORMAT_S32_LE:
  697. val = 3;
  698. break;
  699. case SNDRV_PCM_FORMAT_S24_3LE:
  700. val = 2;
  701. break;
  702. case SNDRV_PCM_FORMAT_S24_LE:
  703. val = 1;
  704. break;
  705. case SNDRV_PCM_FORMAT_S16_LE:
  706. default:
  707. val = 0;
  708. break;
  709. }
  710. return val;
  711. }
  712. static int slim_get_bit_format(int val)
  713. {
  714. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  715. switch (val) {
  716. case 0:
  717. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  718. break;
  719. case 1:
  720. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  721. break;
  722. case 2:
  723. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  724. break;
  725. case 3:
  726. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  727. break;
  728. default:
  729. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  730. break;
  731. }
  732. return bit_fmt;
  733. }
  734. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  735. {
  736. int port_id = 0;
  737. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  738. port_id = SLIM_RX_0;
  739. } else if (strnstr(kcontrol->id.name,
  740. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  741. port_id = SLIM_RX_2;
  742. } else if (strnstr(kcontrol->id.name,
  743. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  744. port_id = SLIM_RX_5;
  745. } else if (strnstr(kcontrol->id.name,
  746. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  747. port_id = SLIM_RX_6;
  748. } else if (strnstr(kcontrol->id.name,
  749. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  750. port_id = SLIM_TX_0;
  751. } else if (strnstr(kcontrol->id.name,
  752. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  753. port_id = SLIM_TX_1;
  754. } else {
  755. pr_err("%s: unsupported channel: %s",
  756. __func__, kcontrol->id.name);
  757. return -EINVAL;
  758. }
  759. return port_id;
  760. }
  761. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  762. struct snd_ctl_elem_value *ucontrol)
  763. {
  764. int ch_num = slim_get_port_idx(kcontrol);
  765. if (ch_num < 0)
  766. return ch_num;
  767. ucontrol->value.enumerated.item[0] =
  768. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  769. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  770. ch_num, slim_rx_cfg[ch_num].sample_rate,
  771. ucontrol->value.enumerated.item[0]);
  772. return 0;
  773. }
  774. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  775. struct snd_ctl_elem_value *ucontrol)
  776. {
  777. int ch_num = slim_get_port_idx(kcontrol);
  778. if (ch_num < 0)
  779. return ch_num;
  780. slim_rx_cfg[ch_num].sample_rate =
  781. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  782. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  783. ch_num, slim_rx_cfg[ch_num].sample_rate,
  784. ucontrol->value.enumerated.item[0]);
  785. return 0;
  786. }
  787. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  788. struct snd_ctl_elem_value *ucontrol)
  789. {
  790. int ch_num = slim_get_port_idx(kcontrol);
  791. if (ch_num < 0)
  792. return ch_num;
  793. ucontrol->value.enumerated.item[0] =
  794. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  795. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  796. ch_num, slim_tx_cfg[ch_num].sample_rate,
  797. ucontrol->value.enumerated.item[0]);
  798. return 0;
  799. }
  800. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  801. struct snd_ctl_elem_value *ucontrol)
  802. {
  803. int sample_rate = 0;
  804. int ch_num = slim_get_port_idx(kcontrol);
  805. if (ch_num < 0)
  806. return ch_num;
  807. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  808. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  809. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  810. __func__, sample_rate);
  811. return -EINVAL;
  812. }
  813. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  814. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  815. ch_num, slim_tx_cfg[ch_num].sample_rate,
  816. ucontrol->value.enumerated.item[0]);
  817. return 0;
  818. }
  819. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  820. struct snd_ctl_elem_value *ucontrol)
  821. {
  822. int ch_num = slim_get_port_idx(kcontrol);
  823. if (ch_num < 0)
  824. return ch_num;
  825. ucontrol->value.enumerated.item[0] =
  826. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  827. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  828. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  829. ucontrol->value.enumerated.item[0]);
  830. return 0;
  831. }
  832. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  833. struct snd_ctl_elem_value *ucontrol)
  834. {
  835. int ch_num = slim_get_port_idx(kcontrol);
  836. if (ch_num < 0)
  837. return ch_num;
  838. slim_rx_cfg[ch_num].bit_format =
  839. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  840. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  841. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  842. ucontrol->value.enumerated.item[0]);
  843. return 0;
  844. }
  845. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  846. struct snd_ctl_elem_value *ucontrol)
  847. {
  848. int ch_num = slim_get_port_idx(kcontrol);
  849. if (ch_num < 0)
  850. return ch_num;
  851. ucontrol->value.enumerated.item[0] =
  852. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  853. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  854. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  855. ucontrol->value.enumerated.item[0]);
  856. return 0;
  857. }
  858. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  859. struct snd_ctl_elem_value *ucontrol)
  860. {
  861. int ch_num = slim_get_port_idx(kcontrol);
  862. if (ch_num < 0)
  863. return ch_num;
  864. slim_tx_cfg[ch_num].bit_format =
  865. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  866. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  867. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  868. ucontrol->value.enumerated.item[0]);
  869. return 0;
  870. }
  871. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  872. struct snd_ctl_elem_value *ucontrol)
  873. {
  874. int ch_num = slim_get_port_idx(kcontrol);
  875. if (ch_num < 0)
  876. return ch_num;
  877. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  878. ch_num, slim_rx_cfg[ch_num].channels);
  879. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  880. return 0;
  881. }
  882. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  883. struct snd_ctl_elem_value *ucontrol)
  884. {
  885. int ch_num = slim_get_port_idx(kcontrol);
  886. if (ch_num < 0)
  887. return ch_num;
  888. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  889. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  890. ch_num, slim_rx_cfg[ch_num].channels);
  891. return 1;
  892. }
  893. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  894. struct snd_ctl_elem_value *ucontrol)
  895. {
  896. int ch_num = slim_get_port_idx(kcontrol);
  897. if (ch_num < 0)
  898. return ch_num;
  899. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  900. ch_num, slim_tx_cfg[ch_num].channels);
  901. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  902. return 0;
  903. }
  904. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  905. struct snd_ctl_elem_value *ucontrol)
  906. {
  907. int ch_num = slim_get_port_idx(kcontrol);
  908. if (ch_num < 0)
  909. return ch_num;
  910. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  911. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  912. ch_num, slim_tx_cfg[ch_num].channels);
  913. return 1;
  914. }
  915. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  916. struct snd_ctl_elem_value *ucontrol)
  917. {
  918. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  919. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  920. ucontrol->value.integer.value[0]);
  921. return 0;
  922. }
  923. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  924. struct snd_ctl_elem_value *ucontrol)
  925. {
  926. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  927. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  928. return 1;
  929. }
  930. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  931. struct snd_ctl_elem_value *ucontrol)
  932. {
  933. /*
  934. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  935. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  936. * value.
  937. */
  938. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  939. case SAMPLING_RATE_96KHZ:
  940. ucontrol->value.integer.value[0] = 5;
  941. break;
  942. case SAMPLING_RATE_88P2KHZ:
  943. ucontrol->value.integer.value[0] = 4;
  944. break;
  945. case SAMPLING_RATE_48KHZ:
  946. ucontrol->value.integer.value[0] = 3;
  947. break;
  948. case SAMPLING_RATE_44P1KHZ:
  949. ucontrol->value.integer.value[0] = 2;
  950. break;
  951. case SAMPLING_RATE_16KHZ:
  952. ucontrol->value.integer.value[0] = 1;
  953. break;
  954. case SAMPLING_RATE_8KHZ:
  955. default:
  956. ucontrol->value.integer.value[0] = 0;
  957. break;
  958. }
  959. pr_debug("%s: sample rate = %d", __func__,
  960. slim_rx_cfg[SLIM_RX_7].sample_rate);
  961. return 0;
  962. }
  963. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  964. struct snd_ctl_elem_value *ucontrol)
  965. {
  966. switch (ucontrol->value.integer.value[0]) {
  967. case 1:
  968. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  969. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  970. break;
  971. case 2:
  972. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  973. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  974. break;
  975. case 3:
  976. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  977. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  978. break;
  979. case 4:
  980. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  981. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  982. break;
  983. case 5:
  984. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  985. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  986. break;
  987. case 0:
  988. default:
  989. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  990. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  991. break;
  992. }
  993. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  994. __func__,
  995. slim_rx_cfg[SLIM_RX_7].sample_rate,
  996. slim_tx_cfg[SLIM_TX_7].sample_rate,
  997. ucontrol->value.enumerated.item[0]);
  998. return 0;
  999. }
  1000. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1001. {
  1002. int idx = 0;
  1003. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1004. sizeof("WSA_CDC_DMA_RX_0")))
  1005. idx = WSA_CDC_DMA_RX_0;
  1006. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1007. sizeof("WSA_CDC_DMA_RX_0")))
  1008. idx = WSA_CDC_DMA_RX_1;
  1009. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1010. sizeof("WSA_CDC_DMA_TX_0")))
  1011. idx = WSA_CDC_DMA_TX_0;
  1012. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1013. sizeof("WSA_CDC_DMA_TX_1")))
  1014. idx = WSA_CDC_DMA_TX_1;
  1015. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1016. sizeof("WSA_CDC_DMA_TX_2")))
  1017. idx = WSA_CDC_DMA_TX_2;
  1018. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1019. sizeof("VA_CDC_DMA_TX_0")))
  1020. idx = VA_CDC_DMA_TX_0;
  1021. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1022. sizeof("VA_CDC_DMA_TX_1")))
  1023. idx = VA_CDC_DMA_TX_1;
  1024. else {
  1025. pr_err("%s: unsupported port: %s\n",
  1026. __func__, kcontrol->id.name);
  1027. return -EINVAL;
  1028. }
  1029. return idx;
  1030. }
  1031. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1032. struct snd_ctl_elem_value *ucontrol)
  1033. {
  1034. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1035. if (ch_num < 0)
  1036. return ch_num;
  1037. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1038. cdc_dma_rx_cfg[ch_num].channels - 1);
  1039. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1040. return 0;
  1041. }
  1042. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1043. struct snd_ctl_elem_value *ucontrol)
  1044. {
  1045. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1046. if (ch_num < 0)
  1047. return ch_num;
  1048. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1049. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1050. cdc_dma_rx_cfg[ch_num].channels);
  1051. return 1;
  1052. }
  1053. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1054. struct snd_ctl_elem_value *ucontrol)
  1055. {
  1056. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1057. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1058. case SNDRV_PCM_FORMAT_S32_LE:
  1059. ucontrol->value.integer.value[0] = 3;
  1060. break;
  1061. case SNDRV_PCM_FORMAT_S24_3LE:
  1062. ucontrol->value.integer.value[0] = 2;
  1063. break;
  1064. case SNDRV_PCM_FORMAT_S24_LE:
  1065. ucontrol->value.integer.value[0] = 1;
  1066. break;
  1067. case SNDRV_PCM_FORMAT_S16_LE:
  1068. default:
  1069. ucontrol->value.integer.value[0] = 0;
  1070. break;
  1071. }
  1072. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1073. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1074. ucontrol->value.integer.value[0]);
  1075. return 0;
  1076. }
  1077. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1078. struct snd_ctl_elem_value *ucontrol)
  1079. {
  1080. int rc = 0;
  1081. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1082. switch (ucontrol->value.integer.value[0]) {
  1083. case 3:
  1084. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1085. break;
  1086. case 2:
  1087. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1088. break;
  1089. case 1:
  1090. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1091. break;
  1092. case 0:
  1093. default:
  1094. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1095. break;
  1096. }
  1097. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1098. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1099. ucontrol->value.integer.value[0]);
  1100. return rc;
  1101. }
  1102. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1103. {
  1104. int sample_rate_val = 0;
  1105. switch (sample_rate) {
  1106. case SAMPLING_RATE_8KHZ:
  1107. sample_rate_val = 0;
  1108. break;
  1109. case SAMPLING_RATE_11P025KHZ:
  1110. sample_rate_val = 1;
  1111. break;
  1112. case SAMPLING_RATE_16KHZ:
  1113. sample_rate_val = 2;
  1114. break;
  1115. case SAMPLING_RATE_22P05KHZ:
  1116. sample_rate_val = 3;
  1117. break;
  1118. case SAMPLING_RATE_32KHZ:
  1119. sample_rate_val = 4;
  1120. break;
  1121. case SAMPLING_RATE_44P1KHZ:
  1122. sample_rate_val = 5;
  1123. break;
  1124. case SAMPLING_RATE_48KHZ:
  1125. sample_rate_val = 6;
  1126. break;
  1127. case SAMPLING_RATE_88P2KHZ:
  1128. sample_rate_val = 7;
  1129. break;
  1130. case SAMPLING_RATE_96KHZ:
  1131. sample_rate_val = 8;
  1132. break;
  1133. case SAMPLING_RATE_176P4KHZ:
  1134. sample_rate_val = 9;
  1135. break;
  1136. case SAMPLING_RATE_192KHZ:
  1137. sample_rate_val = 10;
  1138. break;
  1139. case SAMPLING_RATE_352P8KHZ:
  1140. sample_rate_val = 11;
  1141. break;
  1142. case SAMPLING_RATE_384KHZ:
  1143. sample_rate_val = 12;
  1144. break;
  1145. default:
  1146. sample_rate_val = 6;
  1147. break;
  1148. }
  1149. return sample_rate_val;
  1150. }
  1151. static int cdc_dma_get_sample_rate(int value)
  1152. {
  1153. int sample_rate = 0;
  1154. switch (value) {
  1155. case 0:
  1156. sample_rate = SAMPLING_RATE_8KHZ;
  1157. break;
  1158. case 1:
  1159. sample_rate = SAMPLING_RATE_11P025KHZ;
  1160. break;
  1161. case 2:
  1162. sample_rate = SAMPLING_RATE_16KHZ;
  1163. break;
  1164. case 3:
  1165. sample_rate = SAMPLING_RATE_22P05KHZ;
  1166. break;
  1167. case 4:
  1168. sample_rate = SAMPLING_RATE_32KHZ;
  1169. break;
  1170. case 5:
  1171. sample_rate = SAMPLING_RATE_44P1KHZ;
  1172. break;
  1173. case 6:
  1174. sample_rate = SAMPLING_RATE_48KHZ;
  1175. break;
  1176. case 7:
  1177. sample_rate = SAMPLING_RATE_88P2KHZ;
  1178. break;
  1179. case 8:
  1180. sample_rate = SAMPLING_RATE_96KHZ;
  1181. break;
  1182. case 9:
  1183. sample_rate = SAMPLING_RATE_176P4KHZ;
  1184. break;
  1185. case 10:
  1186. sample_rate = SAMPLING_RATE_192KHZ;
  1187. break;
  1188. case 11:
  1189. sample_rate = SAMPLING_RATE_352P8KHZ;
  1190. break;
  1191. case 12:
  1192. sample_rate = SAMPLING_RATE_384KHZ;
  1193. break;
  1194. default:
  1195. sample_rate = SAMPLING_RATE_48KHZ;
  1196. break;
  1197. }
  1198. return sample_rate;
  1199. }
  1200. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1201. struct snd_ctl_elem_value *ucontrol)
  1202. {
  1203. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1204. if (ch_num < 0)
  1205. return ch_num;
  1206. ucontrol->value.enumerated.item[0] =
  1207. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1208. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1209. cdc_dma_rx_cfg[ch_num].sample_rate);
  1210. return 0;
  1211. }
  1212. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1213. struct snd_ctl_elem_value *ucontrol)
  1214. {
  1215. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1216. if (ch_num < 0)
  1217. return ch_num;
  1218. cdc_dma_rx_cfg[ch_num].sample_rate =
  1219. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1220. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1221. __func__, ucontrol->value.enumerated.item[0],
  1222. cdc_dma_rx_cfg[ch_num].sample_rate);
  1223. return 0;
  1224. }
  1225. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1226. struct snd_ctl_elem_value *ucontrol)
  1227. {
  1228. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1229. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1230. cdc_dma_tx_cfg[ch_num].channels);
  1231. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1232. return 0;
  1233. }
  1234. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1235. struct snd_ctl_elem_value *ucontrol)
  1236. {
  1237. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1238. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1239. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1240. cdc_dma_tx_cfg[ch_num].channels);
  1241. return 1;
  1242. }
  1243. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1244. struct snd_ctl_elem_value *ucontrol)
  1245. {
  1246. int sample_rate_val;
  1247. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1248. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1249. case SAMPLING_RATE_384KHZ:
  1250. sample_rate_val = 12;
  1251. break;
  1252. case SAMPLING_RATE_352P8KHZ:
  1253. sample_rate_val = 11;
  1254. break;
  1255. case SAMPLING_RATE_192KHZ:
  1256. sample_rate_val = 10;
  1257. break;
  1258. case SAMPLING_RATE_176P4KHZ:
  1259. sample_rate_val = 9;
  1260. break;
  1261. case SAMPLING_RATE_96KHZ:
  1262. sample_rate_val = 8;
  1263. break;
  1264. case SAMPLING_RATE_88P2KHZ:
  1265. sample_rate_val = 7;
  1266. break;
  1267. case SAMPLING_RATE_48KHZ:
  1268. sample_rate_val = 6;
  1269. break;
  1270. case SAMPLING_RATE_44P1KHZ:
  1271. sample_rate_val = 5;
  1272. break;
  1273. case SAMPLING_RATE_32KHZ:
  1274. sample_rate_val = 4;
  1275. break;
  1276. case SAMPLING_RATE_22P05KHZ:
  1277. sample_rate_val = 3;
  1278. break;
  1279. case SAMPLING_RATE_16KHZ:
  1280. sample_rate_val = 2;
  1281. break;
  1282. case SAMPLING_RATE_11P025KHZ:
  1283. sample_rate_val = 1;
  1284. break;
  1285. case SAMPLING_RATE_8KHZ:
  1286. sample_rate_val = 0;
  1287. break;
  1288. default:
  1289. sample_rate_val = 6;
  1290. break;
  1291. }
  1292. ucontrol->value.integer.value[0] = sample_rate_val;
  1293. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1294. cdc_dma_tx_cfg[ch_num].sample_rate);
  1295. return 0;
  1296. }
  1297. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1298. struct snd_ctl_elem_value *ucontrol)
  1299. {
  1300. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1301. switch (ucontrol->value.integer.value[0]) {
  1302. case 12:
  1303. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1304. break;
  1305. case 11:
  1306. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1307. break;
  1308. case 10:
  1309. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1310. break;
  1311. case 9:
  1312. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1313. break;
  1314. case 8:
  1315. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1316. break;
  1317. case 7:
  1318. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1319. break;
  1320. case 6:
  1321. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1322. break;
  1323. case 5:
  1324. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1325. break;
  1326. case 4:
  1327. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1328. break;
  1329. case 3:
  1330. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1331. break;
  1332. case 2:
  1333. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1334. break;
  1335. case 1:
  1336. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1337. break;
  1338. case 0:
  1339. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1340. break;
  1341. default:
  1342. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1343. break;
  1344. }
  1345. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1346. __func__, ucontrol->value.integer.value[0],
  1347. cdc_dma_tx_cfg[ch_num].sample_rate);
  1348. return 0;
  1349. }
  1350. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1351. struct snd_ctl_elem_value *ucontrol)
  1352. {
  1353. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1354. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1355. case SNDRV_PCM_FORMAT_S32_LE:
  1356. ucontrol->value.integer.value[0] = 3;
  1357. break;
  1358. case SNDRV_PCM_FORMAT_S24_3LE:
  1359. ucontrol->value.integer.value[0] = 2;
  1360. break;
  1361. case SNDRV_PCM_FORMAT_S24_LE:
  1362. ucontrol->value.integer.value[0] = 1;
  1363. break;
  1364. case SNDRV_PCM_FORMAT_S16_LE:
  1365. default:
  1366. ucontrol->value.integer.value[0] = 0;
  1367. break;
  1368. }
  1369. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1370. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1371. ucontrol->value.integer.value[0]);
  1372. return 0;
  1373. }
  1374. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1375. struct snd_ctl_elem_value *ucontrol)
  1376. {
  1377. int rc = 0;
  1378. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1379. switch (ucontrol->value.integer.value[0]) {
  1380. case 3:
  1381. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1382. break;
  1383. case 2:
  1384. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1385. break;
  1386. case 1:
  1387. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1388. break;
  1389. case 0:
  1390. default:
  1391. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1392. break;
  1393. }
  1394. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1395. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1396. ucontrol->value.integer.value[0]);
  1397. return rc;
  1398. }
  1399. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1400. struct snd_ctl_elem_value *ucontrol)
  1401. {
  1402. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1403. usb_rx_cfg.channels);
  1404. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1405. return 0;
  1406. }
  1407. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1408. struct snd_ctl_elem_value *ucontrol)
  1409. {
  1410. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1411. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1412. return 1;
  1413. }
  1414. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1415. struct snd_ctl_elem_value *ucontrol)
  1416. {
  1417. int sample_rate_val;
  1418. switch (usb_rx_cfg.sample_rate) {
  1419. case SAMPLING_RATE_384KHZ:
  1420. sample_rate_val = 12;
  1421. break;
  1422. case SAMPLING_RATE_352P8KHZ:
  1423. sample_rate_val = 11;
  1424. break;
  1425. case SAMPLING_RATE_192KHZ:
  1426. sample_rate_val = 10;
  1427. break;
  1428. case SAMPLING_RATE_176P4KHZ:
  1429. sample_rate_val = 9;
  1430. break;
  1431. case SAMPLING_RATE_96KHZ:
  1432. sample_rate_val = 8;
  1433. break;
  1434. case SAMPLING_RATE_88P2KHZ:
  1435. sample_rate_val = 7;
  1436. break;
  1437. case SAMPLING_RATE_48KHZ:
  1438. sample_rate_val = 6;
  1439. break;
  1440. case SAMPLING_RATE_44P1KHZ:
  1441. sample_rate_val = 5;
  1442. break;
  1443. case SAMPLING_RATE_32KHZ:
  1444. sample_rate_val = 4;
  1445. break;
  1446. case SAMPLING_RATE_22P05KHZ:
  1447. sample_rate_val = 3;
  1448. break;
  1449. case SAMPLING_RATE_16KHZ:
  1450. sample_rate_val = 2;
  1451. break;
  1452. case SAMPLING_RATE_11P025KHZ:
  1453. sample_rate_val = 1;
  1454. break;
  1455. case SAMPLING_RATE_8KHZ:
  1456. default:
  1457. sample_rate_val = 0;
  1458. break;
  1459. }
  1460. ucontrol->value.integer.value[0] = sample_rate_val;
  1461. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1462. usb_rx_cfg.sample_rate);
  1463. return 0;
  1464. }
  1465. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1466. struct snd_ctl_elem_value *ucontrol)
  1467. {
  1468. switch (ucontrol->value.integer.value[0]) {
  1469. case 12:
  1470. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1471. break;
  1472. case 11:
  1473. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1474. break;
  1475. case 10:
  1476. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1477. break;
  1478. case 9:
  1479. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1480. break;
  1481. case 8:
  1482. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1483. break;
  1484. case 7:
  1485. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1486. break;
  1487. case 6:
  1488. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1489. break;
  1490. case 5:
  1491. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1492. break;
  1493. case 4:
  1494. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1495. break;
  1496. case 3:
  1497. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1498. break;
  1499. case 2:
  1500. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1501. break;
  1502. case 1:
  1503. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1504. break;
  1505. case 0:
  1506. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1507. break;
  1508. default:
  1509. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1510. break;
  1511. }
  1512. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1513. __func__, ucontrol->value.integer.value[0],
  1514. usb_rx_cfg.sample_rate);
  1515. return 0;
  1516. }
  1517. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1518. struct snd_ctl_elem_value *ucontrol)
  1519. {
  1520. switch (usb_rx_cfg.bit_format) {
  1521. case SNDRV_PCM_FORMAT_S32_LE:
  1522. ucontrol->value.integer.value[0] = 3;
  1523. break;
  1524. case SNDRV_PCM_FORMAT_S24_3LE:
  1525. ucontrol->value.integer.value[0] = 2;
  1526. break;
  1527. case SNDRV_PCM_FORMAT_S24_LE:
  1528. ucontrol->value.integer.value[0] = 1;
  1529. break;
  1530. case SNDRV_PCM_FORMAT_S16_LE:
  1531. default:
  1532. ucontrol->value.integer.value[0] = 0;
  1533. break;
  1534. }
  1535. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1536. __func__, usb_rx_cfg.bit_format,
  1537. ucontrol->value.integer.value[0]);
  1538. return 0;
  1539. }
  1540. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1541. struct snd_ctl_elem_value *ucontrol)
  1542. {
  1543. int rc = 0;
  1544. switch (ucontrol->value.integer.value[0]) {
  1545. case 3:
  1546. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1547. break;
  1548. case 2:
  1549. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1550. break;
  1551. case 1:
  1552. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1553. break;
  1554. case 0:
  1555. default:
  1556. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1557. break;
  1558. }
  1559. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1560. __func__, usb_rx_cfg.bit_format,
  1561. ucontrol->value.integer.value[0]);
  1562. return rc;
  1563. }
  1564. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1565. struct snd_ctl_elem_value *ucontrol)
  1566. {
  1567. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1568. usb_tx_cfg.channels);
  1569. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1570. return 0;
  1571. }
  1572. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1573. struct snd_ctl_elem_value *ucontrol)
  1574. {
  1575. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1576. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1577. return 1;
  1578. }
  1579. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1580. struct snd_ctl_elem_value *ucontrol)
  1581. {
  1582. int sample_rate_val;
  1583. switch (usb_tx_cfg.sample_rate) {
  1584. case SAMPLING_RATE_384KHZ:
  1585. sample_rate_val = 12;
  1586. break;
  1587. case SAMPLING_RATE_352P8KHZ:
  1588. sample_rate_val = 11;
  1589. break;
  1590. case SAMPLING_RATE_192KHZ:
  1591. sample_rate_val = 10;
  1592. break;
  1593. case SAMPLING_RATE_176P4KHZ:
  1594. sample_rate_val = 9;
  1595. break;
  1596. case SAMPLING_RATE_96KHZ:
  1597. sample_rate_val = 8;
  1598. break;
  1599. case SAMPLING_RATE_88P2KHZ:
  1600. sample_rate_val = 7;
  1601. break;
  1602. case SAMPLING_RATE_48KHZ:
  1603. sample_rate_val = 6;
  1604. break;
  1605. case SAMPLING_RATE_44P1KHZ:
  1606. sample_rate_val = 5;
  1607. break;
  1608. case SAMPLING_RATE_32KHZ:
  1609. sample_rate_val = 4;
  1610. break;
  1611. case SAMPLING_RATE_22P05KHZ:
  1612. sample_rate_val = 3;
  1613. break;
  1614. case SAMPLING_RATE_16KHZ:
  1615. sample_rate_val = 2;
  1616. break;
  1617. case SAMPLING_RATE_11P025KHZ:
  1618. sample_rate_val = 1;
  1619. break;
  1620. case SAMPLING_RATE_8KHZ:
  1621. sample_rate_val = 0;
  1622. break;
  1623. default:
  1624. sample_rate_val = 6;
  1625. break;
  1626. }
  1627. ucontrol->value.integer.value[0] = sample_rate_val;
  1628. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1629. usb_tx_cfg.sample_rate);
  1630. return 0;
  1631. }
  1632. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1633. struct snd_ctl_elem_value *ucontrol)
  1634. {
  1635. switch (ucontrol->value.integer.value[0]) {
  1636. case 12:
  1637. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1638. break;
  1639. case 11:
  1640. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1641. break;
  1642. case 10:
  1643. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1644. break;
  1645. case 9:
  1646. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1647. break;
  1648. case 8:
  1649. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1650. break;
  1651. case 7:
  1652. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1653. break;
  1654. case 6:
  1655. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1656. break;
  1657. case 5:
  1658. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1659. break;
  1660. case 4:
  1661. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1662. break;
  1663. case 3:
  1664. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1665. break;
  1666. case 2:
  1667. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1668. break;
  1669. case 1:
  1670. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1671. break;
  1672. case 0:
  1673. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1674. break;
  1675. default:
  1676. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1677. break;
  1678. }
  1679. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1680. __func__, ucontrol->value.integer.value[0],
  1681. usb_tx_cfg.sample_rate);
  1682. return 0;
  1683. }
  1684. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1685. struct snd_ctl_elem_value *ucontrol)
  1686. {
  1687. switch (usb_tx_cfg.bit_format) {
  1688. case SNDRV_PCM_FORMAT_S32_LE:
  1689. ucontrol->value.integer.value[0] = 3;
  1690. break;
  1691. case SNDRV_PCM_FORMAT_S24_3LE:
  1692. ucontrol->value.integer.value[0] = 2;
  1693. break;
  1694. case SNDRV_PCM_FORMAT_S24_LE:
  1695. ucontrol->value.integer.value[0] = 1;
  1696. break;
  1697. case SNDRV_PCM_FORMAT_S16_LE:
  1698. default:
  1699. ucontrol->value.integer.value[0] = 0;
  1700. break;
  1701. }
  1702. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1703. __func__, usb_tx_cfg.bit_format,
  1704. ucontrol->value.integer.value[0]);
  1705. return 0;
  1706. }
  1707. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1708. struct snd_ctl_elem_value *ucontrol)
  1709. {
  1710. int rc = 0;
  1711. switch (ucontrol->value.integer.value[0]) {
  1712. case 3:
  1713. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1714. break;
  1715. case 2:
  1716. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1717. break;
  1718. case 1:
  1719. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1720. break;
  1721. case 0:
  1722. default:
  1723. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1724. break;
  1725. }
  1726. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1727. __func__, usb_tx_cfg.bit_format,
  1728. ucontrol->value.integer.value[0]);
  1729. return rc;
  1730. }
  1731. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1732. struct snd_ctl_elem_value *ucontrol)
  1733. {
  1734. pr_debug("%s: proxy_rx channels = %d\n",
  1735. __func__, proxy_rx_cfg.channels);
  1736. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1737. return 0;
  1738. }
  1739. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1740. struct snd_ctl_elem_value *ucontrol)
  1741. {
  1742. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1743. pr_debug("%s: proxy_rx channels = %d\n",
  1744. __func__, proxy_rx_cfg.channels);
  1745. return 1;
  1746. }
  1747. static int tdm_get_sample_rate(int value)
  1748. {
  1749. int sample_rate = 0;
  1750. switch (value) {
  1751. case 0:
  1752. sample_rate = SAMPLING_RATE_8KHZ;
  1753. break;
  1754. case 1:
  1755. sample_rate = SAMPLING_RATE_16KHZ;
  1756. break;
  1757. case 2:
  1758. sample_rate = SAMPLING_RATE_32KHZ;
  1759. break;
  1760. case 3:
  1761. sample_rate = SAMPLING_RATE_48KHZ;
  1762. break;
  1763. case 4:
  1764. sample_rate = SAMPLING_RATE_176P4KHZ;
  1765. break;
  1766. case 5:
  1767. sample_rate = SAMPLING_RATE_352P8KHZ;
  1768. break;
  1769. default:
  1770. sample_rate = SAMPLING_RATE_48KHZ;
  1771. break;
  1772. }
  1773. return sample_rate;
  1774. }
  1775. static int aux_pcm_get_sample_rate(int value)
  1776. {
  1777. int sample_rate;
  1778. switch (value) {
  1779. case 1:
  1780. sample_rate = SAMPLING_RATE_16KHZ;
  1781. break;
  1782. case 0:
  1783. default:
  1784. sample_rate = SAMPLING_RATE_8KHZ;
  1785. break;
  1786. }
  1787. return sample_rate;
  1788. }
  1789. static int tdm_get_sample_rate_val(int sample_rate)
  1790. {
  1791. int sample_rate_val = 0;
  1792. switch (sample_rate) {
  1793. case SAMPLING_RATE_8KHZ:
  1794. sample_rate_val = 0;
  1795. break;
  1796. case SAMPLING_RATE_16KHZ:
  1797. sample_rate_val = 1;
  1798. break;
  1799. case SAMPLING_RATE_32KHZ:
  1800. sample_rate_val = 2;
  1801. break;
  1802. case SAMPLING_RATE_48KHZ:
  1803. sample_rate_val = 3;
  1804. break;
  1805. case SAMPLING_RATE_176P4KHZ:
  1806. sample_rate_val = 4;
  1807. break;
  1808. case SAMPLING_RATE_352P8KHZ:
  1809. sample_rate_val = 5;
  1810. break;
  1811. default:
  1812. sample_rate_val = 3;
  1813. break;
  1814. }
  1815. return sample_rate_val;
  1816. }
  1817. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1818. {
  1819. int sample_rate_val;
  1820. switch (sample_rate) {
  1821. case SAMPLING_RATE_16KHZ:
  1822. sample_rate_val = 1;
  1823. break;
  1824. case SAMPLING_RATE_8KHZ:
  1825. default:
  1826. sample_rate_val = 0;
  1827. break;
  1828. }
  1829. return sample_rate_val;
  1830. }
  1831. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1832. struct tdm_port *port)
  1833. {
  1834. if (port) {
  1835. if (strnstr(kcontrol->id.name, "PRI",
  1836. sizeof(kcontrol->id.name))) {
  1837. port->mode = TDM_PRI;
  1838. } else if (strnstr(kcontrol->id.name, "SEC",
  1839. sizeof(kcontrol->id.name))) {
  1840. port->mode = TDM_SEC;
  1841. } else if (strnstr(kcontrol->id.name, "TERT",
  1842. sizeof(kcontrol->id.name))) {
  1843. port->mode = TDM_TERT;
  1844. } else if (strnstr(kcontrol->id.name, "QUAT",
  1845. sizeof(kcontrol->id.name))) {
  1846. port->mode = TDM_QUAT;
  1847. } else if (strnstr(kcontrol->id.name, "QUIN",
  1848. sizeof(kcontrol->id.name))) {
  1849. port->mode = TDM_QUIN;
  1850. } else {
  1851. pr_err("%s: unsupported mode in: %s",
  1852. __func__, kcontrol->id.name);
  1853. return -EINVAL;
  1854. }
  1855. if (strnstr(kcontrol->id.name, "RX_0",
  1856. sizeof(kcontrol->id.name)) ||
  1857. strnstr(kcontrol->id.name, "TX_0",
  1858. sizeof(kcontrol->id.name))) {
  1859. port->channel = TDM_0;
  1860. } else if (strnstr(kcontrol->id.name, "RX_1",
  1861. sizeof(kcontrol->id.name)) ||
  1862. strnstr(kcontrol->id.name, "TX_1",
  1863. sizeof(kcontrol->id.name))) {
  1864. port->channel = TDM_1;
  1865. } else if (strnstr(kcontrol->id.name, "RX_2",
  1866. sizeof(kcontrol->id.name)) ||
  1867. strnstr(kcontrol->id.name, "TX_2",
  1868. sizeof(kcontrol->id.name))) {
  1869. port->channel = TDM_2;
  1870. } else if (strnstr(kcontrol->id.name, "RX_3",
  1871. sizeof(kcontrol->id.name)) ||
  1872. strnstr(kcontrol->id.name, "TX_3",
  1873. sizeof(kcontrol->id.name))) {
  1874. port->channel = TDM_3;
  1875. } else if (strnstr(kcontrol->id.name, "RX_4",
  1876. sizeof(kcontrol->id.name)) ||
  1877. strnstr(kcontrol->id.name, "TX_4",
  1878. sizeof(kcontrol->id.name))) {
  1879. port->channel = TDM_4;
  1880. } else if (strnstr(kcontrol->id.name, "RX_5",
  1881. sizeof(kcontrol->id.name)) ||
  1882. strnstr(kcontrol->id.name, "TX_5",
  1883. sizeof(kcontrol->id.name))) {
  1884. port->channel = TDM_5;
  1885. } else if (strnstr(kcontrol->id.name, "RX_6",
  1886. sizeof(kcontrol->id.name)) ||
  1887. strnstr(kcontrol->id.name, "TX_6",
  1888. sizeof(kcontrol->id.name))) {
  1889. port->channel = TDM_6;
  1890. } else if (strnstr(kcontrol->id.name, "RX_7",
  1891. sizeof(kcontrol->id.name)) ||
  1892. strnstr(kcontrol->id.name, "TX_7",
  1893. sizeof(kcontrol->id.name))) {
  1894. port->channel = TDM_7;
  1895. } else {
  1896. pr_err("%s: unsupported channel in: %s",
  1897. __func__, kcontrol->id.name);
  1898. return -EINVAL;
  1899. }
  1900. } else
  1901. return -EINVAL;
  1902. return 0;
  1903. }
  1904. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1905. struct snd_ctl_elem_value *ucontrol)
  1906. {
  1907. struct tdm_port port;
  1908. int ret = tdm_get_port_idx(kcontrol, &port);
  1909. if (ret) {
  1910. pr_err("%s: unsupported control: %s",
  1911. __func__, kcontrol->id.name);
  1912. } else {
  1913. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1914. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1915. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1916. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1917. ucontrol->value.enumerated.item[0]);
  1918. }
  1919. return ret;
  1920. }
  1921. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1922. struct snd_ctl_elem_value *ucontrol)
  1923. {
  1924. struct tdm_port port;
  1925. int ret = tdm_get_port_idx(kcontrol, &port);
  1926. if (ret) {
  1927. pr_err("%s: unsupported control: %s",
  1928. __func__, kcontrol->id.name);
  1929. } else {
  1930. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1931. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1932. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1933. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1934. ucontrol->value.enumerated.item[0]);
  1935. }
  1936. return ret;
  1937. }
  1938. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1939. struct snd_ctl_elem_value *ucontrol)
  1940. {
  1941. struct tdm_port port;
  1942. int ret = tdm_get_port_idx(kcontrol, &port);
  1943. if (ret) {
  1944. pr_err("%s: unsupported control: %s",
  1945. __func__, kcontrol->id.name);
  1946. } else {
  1947. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1948. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1949. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1950. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1951. ucontrol->value.enumerated.item[0]);
  1952. }
  1953. return ret;
  1954. }
  1955. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1956. struct snd_ctl_elem_value *ucontrol)
  1957. {
  1958. struct tdm_port port;
  1959. int ret = tdm_get_port_idx(kcontrol, &port);
  1960. if (ret) {
  1961. pr_err("%s: unsupported control: %s",
  1962. __func__, kcontrol->id.name);
  1963. } else {
  1964. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1965. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1966. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1967. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1968. ucontrol->value.enumerated.item[0]);
  1969. }
  1970. return ret;
  1971. }
  1972. static int tdm_get_format(int value)
  1973. {
  1974. int format = 0;
  1975. switch (value) {
  1976. case 0:
  1977. format = SNDRV_PCM_FORMAT_S16_LE;
  1978. break;
  1979. case 1:
  1980. format = SNDRV_PCM_FORMAT_S24_LE;
  1981. break;
  1982. case 2:
  1983. format = SNDRV_PCM_FORMAT_S32_LE;
  1984. break;
  1985. default:
  1986. format = SNDRV_PCM_FORMAT_S16_LE;
  1987. break;
  1988. }
  1989. return format;
  1990. }
  1991. static int tdm_get_format_val(int format)
  1992. {
  1993. int value = 0;
  1994. switch (format) {
  1995. case SNDRV_PCM_FORMAT_S16_LE:
  1996. value = 0;
  1997. break;
  1998. case SNDRV_PCM_FORMAT_S24_LE:
  1999. value = 1;
  2000. break;
  2001. case SNDRV_PCM_FORMAT_S32_LE:
  2002. value = 2;
  2003. break;
  2004. default:
  2005. value = 0;
  2006. break;
  2007. }
  2008. return value;
  2009. }
  2010. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2011. struct snd_ctl_elem_value *ucontrol)
  2012. {
  2013. struct tdm_port port;
  2014. int ret = tdm_get_port_idx(kcontrol, &port);
  2015. if (ret) {
  2016. pr_err("%s: unsupported control: %s",
  2017. __func__, kcontrol->id.name);
  2018. } else {
  2019. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2020. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2021. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2022. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2023. ucontrol->value.enumerated.item[0]);
  2024. }
  2025. return ret;
  2026. }
  2027. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2028. struct snd_ctl_elem_value *ucontrol)
  2029. {
  2030. struct tdm_port port;
  2031. int ret = tdm_get_port_idx(kcontrol, &port);
  2032. if (ret) {
  2033. pr_err("%s: unsupported control: %s",
  2034. __func__, kcontrol->id.name);
  2035. } else {
  2036. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2037. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2038. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2039. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2040. ucontrol->value.enumerated.item[0]);
  2041. }
  2042. return ret;
  2043. }
  2044. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2045. struct snd_ctl_elem_value *ucontrol)
  2046. {
  2047. struct tdm_port port;
  2048. int ret = tdm_get_port_idx(kcontrol, &port);
  2049. if (ret) {
  2050. pr_err("%s: unsupported control: %s",
  2051. __func__, kcontrol->id.name);
  2052. } else {
  2053. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2054. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2055. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2056. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2057. ucontrol->value.enumerated.item[0]);
  2058. }
  2059. return ret;
  2060. }
  2061. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2062. struct snd_ctl_elem_value *ucontrol)
  2063. {
  2064. struct tdm_port port;
  2065. int ret = tdm_get_port_idx(kcontrol, &port);
  2066. if (ret) {
  2067. pr_err("%s: unsupported control: %s",
  2068. __func__, kcontrol->id.name);
  2069. } else {
  2070. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2071. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2072. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2073. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2074. ucontrol->value.enumerated.item[0]);
  2075. }
  2076. return ret;
  2077. }
  2078. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2079. struct snd_ctl_elem_value *ucontrol)
  2080. {
  2081. struct tdm_port port;
  2082. int ret = tdm_get_port_idx(kcontrol, &port);
  2083. if (ret) {
  2084. pr_err("%s: unsupported control: %s",
  2085. __func__, kcontrol->id.name);
  2086. } else {
  2087. ucontrol->value.enumerated.item[0] =
  2088. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2089. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2090. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2091. ucontrol->value.enumerated.item[0]);
  2092. }
  2093. return ret;
  2094. }
  2095. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2096. struct snd_ctl_elem_value *ucontrol)
  2097. {
  2098. struct tdm_port port;
  2099. int ret = tdm_get_port_idx(kcontrol, &port);
  2100. if (ret) {
  2101. pr_err("%s: unsupported control: %s",
  2102. __func__, kcontrol->id.name);
  2103. } else {
  2104. tdm_rx_cfg[port.mode][port.channel].channels =
  2105. ucontrol->value.enumerated.item[0] + 1;
  2106. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2107. tdm_rx_cfg[port.mode][port.channel].channels,
  2108. ucontrol->value.enumerated.item[0] + 1);
  2109. }
  2110. return ret;
  2111. }
  2112. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2113. struct snd_ctl_elem_value *ucontrol)
  2114. {
  2115. struct tdm_port port;
  2116. int ret = tdm_get_port_idx(kcontrol, &port);
  2117. if (ret) {
  2118. pr_err("%s: unsupported control: %s",
  2119. __func__, kcontrol->id.name);
  2120. } else {
  2121. ucontrol->value.enumerated.item[0] =
  2122. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2123. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2124. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2125. ucontrol->value.enumerated.item[0]);
  2126. }
  2127. return ret;
  2128. }
  2129. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2130. struct snd_ctl_elem_value *ucontrol)
  2131. {
  2132. struct tdm_port port;
  2133. int ret = tdm_get_port_idx(kcontrol, &port);
  2134. if (ret) {
  2135. pr_err("%s: unsupported control: %s",
  2136. __func__, kcontrol->id.name);
  2137. } else {
  2138. tdm_tx_cfg[port.mode][port.channel].channels =
  2139. ucontrol->value.enumerated.item[0] + 1;
  2140. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2141. tdm_tx_cfg[port.mode][port.channel].channels,
  2142. ucontrol->value.enumerated.item[0] + 1);
  2143. }
  2144. return ret;
  2145. }
  2146. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2147. {
  2148. int idx;
  2149. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2150. sizeof("PRIM_AUX_PCM")))
  2151. idx = PRIM_AUX_PCM;
  2152. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2153. sizeof("SEC_AUX_PCM")))
  2154. idx = SEC_AUX_PCM;
  2155. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2156. sizeof("TERT_AUX_PCM")))
  2157. idx = TERT_AUX_PCM;
  2158. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2159. sizeof("QUAT_AUX_PCM")))
  2160. idx = QUAT_AUX_PCM;
  2161. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2162. sizeof("QUIN_AUX_PCM")))
  2163. idx = QUIN_AUX_PCM;
  2164. else {
  2165. pr_err("%s: unsupported port: %s",
  2166. __func__, kcontrol->id.name);
  2167. idx = -EINVAL;
  2168. }
  2169. return idx;
  2170. }
  2171. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2172. struct snd_ctl_elem_value *ucontrol)
  2173. {
  2174. int idx = aux_pcm_get_port_idx(kcontrol);
  2175. if (idx < 0)
  2176. return idx;
  2177. aux_pcm_rx_cfg[idx].sample_rate =
  2178. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2179. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2180. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2181. ucontrol->value.enumerated.item[0]);
  2182. return 0;
  2183. }
  2184. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2185. struct snd_ctl_elem_value *ucontrol)
  2186. {
  2187. int idx = aux_pcm_get_port_idx(kcontrol);
  2188. if (idx < 0)
  2189. return idx;
  2190. ucontrol->value.enumerated.item[0] =
  2191. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2192. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2193. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2194. ucontrol->value.enumerated.item[0]);
  2195. return 0;
  2196. }
  2197. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2198. struct snd_ctl_elem_value *ucontrol)
  2199. {
  2200. int idx = aux_pcm_get_port_idx(kcontrol);
  2201. if (idx < 0)
  2202. return idx;
  2203. aux_pcm_tx_cfg[idx].sample_rate =
  2204. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2205. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2206. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2207. ucontrol->value.enumerated.item[0]);
  2208. return 0;
  2209. }
  2210. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2211. struct snd_ctl_elem_value *ucontrol)
  2212. {
  2213. int idx = aux_pcm_get_port_idx(kcontrol);
  2214. if (idx < 0)
  2215. return idx;
  2216. ucontrol->value.enumerated.item[0] =
  2217. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2218. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2219. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2220. ucontrol->value.enumerated.item[0]);
  2221. return 0;
  2222. }
  2223. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2224. {
  2225. int idx;
  2226. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2227. sizeof("PRIM_MI2S_RX")))
  2228. idx = PRIM_MI2S;
  2229. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2230. sizeof("SEC_MI2S_RX")))
  2231. idx = SEC_MI2S;
  2232. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2233. sizeof("TERT_MI2S_RX")))
  2234. idx = TERT_MI2S;
  2235. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2236. sizeof("QUAT_MI2S_RX")))
  2237. idx = QUAT_MI2S;
  2238. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2239. sizeof("QUIN_MI2S_RX")))
  2240. idx = QUIN_MI2S;
  2241. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2242. sizeof("PRIM_MI2S_TX")))
  2243. idx = PRIM_MI2S;
  2244. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2245. sizeof("SEC_MI2S_TX")))
  2246. idx = SEC_MI2S;
  2247. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2248. sizeof("TERT_MI2S_TX")))
  2249. idx = TERT_MI2S;
  2250. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2251. sizeof("QUAT_MI2S_TX")))
  2252. idx = QUAT_MI2S;
  2253. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2254. sizeof("QUIN_MI2S_TX")))
  2255. idx = QUIN_MI2S;
  2256. else {
  2257. pr_err("%s: unsupported channel: %s",
  2258. __func__, kcontrol->id.name);
  2259. idx = -EINVAL;
  2260. }
  2261. return idx;
  2262. }
  2263. static int mi2s_get_sample_rate_val(int sample_rate)
  2264. {
  2265. int sample_rate_val;
  2266. switch (sample_rate) {
  2267. case SAMPLING_RATE_8KHZ:
  2268. sample_rate_val = 0;
  2269. break;
  2270. case SAMPLING_RATE_11P025KHZ:
  2271. sample_rate_val = 1;
  2272. break;
  2273. case SAMPLING_RATE_16KHZ:
  2274. sample_rate_val = 2;
  2275. break;
  2276. case SAMPLING_RATE_22P05KHZ:
  2277. sample_rate_val = 3;
  2278. break;
  2279. case SAMPLING_RATE_32KHZ:
  2280. sample_rate_val = 4;
  2281. break;
  2282. case SAMPLING_RATE_44P1KHZ:
  2283. sample_rate_val = 5;
  2284. break;
  2285. case SAMPLING_RATE_48KHZ:
  2286. sample_rate_val = 6;
  2287. break;
  2288. case SAMPLING_RATE_96KHZ:
  2289. sample_rate_val = 7;
  2290. break;
  2291. case SAMPLING_RATE_192KHZ:
  2292. sample_rate_val = 8;
  2293. break;
  2294. default:
  2295. sample_rate_val = 6;
  2296. break;
  2297. }
  2298. return sample_rate_val;
  2299. }
  2300. static int mi2s_get_sample_rate(int value)
  2301. {
  2302. int sample_rate;
  2303. switch (value) {
  2304. case 0:
  2305. sample_rate = SAMPLING_RATE_8KHZ;
  2306. break;
  2307. case 1:
  2308. sample_rate = SAMPLING_RATE_11P025KHZ;
  2309. break;
  2310. case 2:
  2311. sample_rate = SAMPLING_RATE_16KHZ;
  2312. break;
  2313. case 3:
  2314. sample_rate = SAMPLING_RATE_22P05KHZ;
  2315. break;
  2316. case 4:
  2317. sample_rate = SAMPLING_RATE_32KHZ;
  2318. break;
  2319. case 5:
  2320. sample_rate = SAMPLING_RATE_44P1KHZ;
  2321. break;
  2322. case 6:
  2323. sample_rate = SAMPLING_RATE_48KHZ;
  2324. break;
  2325. case 7:
  2326. sample_rate = SAMPLING_RATE_96KHZ;
  2327. break;
  2328. case 8:
  2329. sample_rate = SAMPLING_RATE_192KHZ;
  2330. break;
  2331. default:
  2332. sample_rate = SAMPLING_RATE_48KHZ;
  2333. break;
  2334. }
  2335. return sample_rate;
  2336. }
  2337. static int mi2s_auxpcm_get_format(int value)
  2338. {
  2339. int format;
  2340. switch (value) {
  2341. case 0:
  2342. format = SNDRV_PCM_FORMAT_S16_LE;
  2343. break;
  2344. case 1:
  2345. format = SNDRV_PCM_FORMAT_S24_LE;
  2346. break;
  2347. case 2:
  2348. format = SNDRV_PCM_FORMAT_S24_3LE;
  2349. break;
  2350. case 3:
  2351. format = SNDRV_PCM_FORMAT_S32_LE;
  2352. break;
  2353. default:
  2354. format = SNDRV_PCM_FORMAT_S16_LE;
  2355. break;
  2356. }
  2357. return format;
  2358. }
  2359. static int mi2s_auxpcm_get_format_value(int format)
  2360. {
  2361. int value;
  2362. switch (format) {
  2363. case SNDRV_PCM_FORMAT_S16_LE:
  2364. value = 0;
  2365. break;
  2366. case SNDRV_PCM_FORMAT_S24_LE:
  2367. value = 1;
  2368. break;
  2369. case SNDRV_PCM_FORMAT_S24_3LE:
  2370. value = 2;
  2371. break;
  2372. case SNDRV_PCM_FORMAT_S32_LE:
  2373. value = 3;
  2374. break;
  2375. default:
  2376. value = 0;
  2377. break;
  2378. }
  2379. return value;
  2380. }
  2381. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2382. struct snd_ctl_elem_value *ucontrol)
  2383. {
  2384. int idx = mi2s_get_port_idx(kcontrol);
  2385. if (idx < 0)
  2386. return idx;
  2387. mi2s_rx_cfg[idx].sample_rate =
  2388. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2389. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2390. idx, mi2s_rx_cfg[idx].sample_rate,
  2391. ucontrol->value.enumerated.item[0]);
  2392. return 0;
  2393. }
  2394. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2395. struct snd_ctl_elem_value *ucontrol)
  2396. {
  2397. int idx = mi2s_get_port_idx(kcontrol);
  2398. if (idx < 0)
  2399. return idx;
  2400. ucontrol->value.enumerated.item[0] =
  2401. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2402. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2403. idx, mi2s_rx_cfg[idx].sample_rate,
  2404. ucontrol->value.enumerated.item[0]);
  2405. return 0;
  2406. }
  2407. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2408. struct snd_ctl_elem_value *ucontrol)
  2409. {
  2410. int idx = mi2s_get_port_idx(kcontrol);
  2411. if (idx < 0)
  2412. return idx;
  2413. mi2s_tx_cfg[idx].sample_rate =
  2414. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2415. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2416. idx, mi2s_tx_cfg[idx].sample_rate,
  2417. ucontrol->value.enumerated.item[0]);
  2418. return 0;
  2419. }
  2420. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2421. struct snd_ctl_elem_value *ucontrol)
  2422. {
  2423. int idx = mi2s_get_port_idx(kcontrol);
  2424. if (idx < 0)
  2425. return idx;
  2426. ucontrol->value.enumerated.item[0] =
  2427. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2428. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2429. idx, mi2s_tx_cfg[idx].sample_rate,
  2430. ucontrol->value.enumerated.item[0]);
  2431. return 0;
  2432. }
  2433. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2434. struct snd_ctl_elem_value *ucontrol)
  2435. {
  2436. int idx = mi2s_get_port_idx(kcontrol);
  2437. if (idx < 0)
  2438. return idx;
  2439. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2440. idx, mi2s_rx_cfg[idx].channels);
  2441. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2442. return 0;
  2443. }
  2444. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2445. struct snd_ctl_elem_value *ucontrol)
  2446. {
  2447. int idx = mi2s_get_port_idx(kcontrol);
  2448. if (idx < 0)
  2449. return idx;
  2450. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2451. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2452. idx, mi2s_rx_cfg[idx].channels);
  2453. return 1;
  2454. }
  2455. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2456. struct snd_ctl_elem_value *ucontrol)
  2457. {
  2458. int idx = mi2s_get_port_idx(kcontrol);
  2459. if (idx < 0)
  2460. return idx;
  2461. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2462. idx, mi2s_tx_cfg[idx].channels);
  2463. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2464. return 0;
  2465. }
  2466. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2467. struct snd_ctl_elem_value *ucontrol)
  2468. {
  2469. int idx = mi2s_get_port_idx(kcontrol);
  2470. if (idx < 0)
  2471. return idx;
  2472. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2473. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2474. idx, mi2s_tx_cfg[idx].channels);
  2475. return 1;
  2476. }
  2477. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2478. struct snd_ctl_elem_value *ucontrol)
  2479. {
  2480. int idx = mi2s_get_port_idx(kcontrol);
  2481. if (idx < 0)
  2482. return idx;
  2483. ucontrol->value.enumerated.item[0] =
  2484. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2485. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2486. idx, mi2s_rx_cfg[idx].bit_format,
  2487. ucontrol->value.enumerated.item[0]);
  2488. return 0;
  2489. }
  2490. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2491. struct snd_ctl_elem_value *ucontrol)
  2492. {
  2493. int idx = mi2s_get_port_idx(kcontrol);
  2494. if (idx < 0)
  2495. return idx;
  2496. mi2s_rx_cfg[idx].bit_format =
  2497. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2498. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2499. idx, mi2s_rx_cfg[idx].bit_format,
  2500. ucontrol->value.enumerated.item[0]);
  2501. return 0;
  2502. }
  2503. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2504. struct snd_ctl_elem_value *ucontrol)
  2505. {
  2506. int idx = mi2s_get_port_idx(kcontrol);
  2507. if (idx < 0)
  2508. return idx;
  2509. ucontrol->value.enumerated.item[0] =
  2510. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2511. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2512. idx, mi2s_tx_cfg[idx].bit_format,
  2513. ucontrol->value.enumerated.item[0]);
  2514. return 0;
  2515. }
  2516. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2517. struct snd_ctl_elem_value *ucontrol)
  2518. {
  2519. int idx = mi2s_get_port_idx(kcontrol);
  2520. if (idx < 0)
  2521. return idx;
  2522. mi2s_tx_cfg[idx].bit_format =
  2523. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2524. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2525. idx, mi2s_tx_cfg[idx].bit_format,
  2526. ucontrol->value.enumerated.item[0]);
  2527. return 0;
  2528. }
  2529. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2530. struct snd_ctl_elem_value *ucontrol)
  2531. {
  2532. int idx = aux_pcm_get_port_idx(kcontrol);
  2533. if (idx < 0)
  2534. return idx;
  2535. ucontrol->value.enumerated.item[0] =
  2536. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2537. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2538. idx, aux_pcm_rx_cfg[idx].bit_format,
  2539. ucontrol->value.enumerated.item[0]);
  2540. return 0;
  2541. }
  2542. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2543. struct snd_ctl_elem_value *ucontrol)
  2544. {
  2545. int idx = aux_pcm_get_port_idx(kcontrol);
  2546. if (idx < 0)
  2547. return idx;
  2548. aux_pcm_rx_cfg[idx].bit_format =
  2549. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2550. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2551. idx, aux_pcm_rx_cfg[idx].bit_format,
  2552. ucontrol->value.enumerated.item[0]);
  2553. return 0;
  2554. }
  2555. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2556. struct snd_ctl_elem_value *ucontrol)
  2557. {
  2558. int idx = aux_pcm_get_port_idx(kcontrol);
  2559. if (idx < 0)
  2560. return idx;
  2561. ucontrol->value.enumerated.item[0] =
  2562. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2563. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2564. idx, aux_pcm_tx_cfg[idx].bit_format,
  2565. ucontrol->value.enumerated.item[0]);
  2566. return 0;
  2567. }
  2568. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2569. struct snd_ctl_elem_value *ucontrol)
  2570. {
  2571. int idx = aux_pcm_get_port_idx(kcontrol);
  2572. if (idx < 0)
  2573. return idx;
  2574. aux_pcm_tx_cfg[idx].bit_format =
  2575. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2576. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2577. idx, aux_pcm_tx_cfg[idx].bit_format,
  2578. ucontrol->value.enumerated.item[0]);
  2579. return 0;
  2580. }
  2581. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2582. {
  2583. int idx;
  2584. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2585. sizeof("PRIM_SPDIF_RX")))
  2586. idx = PRIM_SPDIF_RX;
  2587. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2588. sizeof("SEC_SPDIF_RX")))
  2589. idx = SEC_SPDIF_RX;
  2590. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2591. sizeof("PRIM_SPDIF_TX")))
  2592. idx = PRIM_SPDIF_TX;
  2593. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2594. sizeof("SEC_SPDIF_TX")))
  2595. idx = SEC_SPDIF_TX;
  2596. else {
  2597. pr_err("%s: unsupported channel: %s",
  2598. __func__, kcontrol->id.name);
  2599. idx = -EINVAL;
  2600. }
  2601. return idx;
  2602. }
  2603. static int spdif_get_sample_rate_val(int sample_rate)
  2604. {
  2605. int sample_rate_val;
  2606. switch (sample_rate) {
  2607. case SAMPLING_RATE_32KHZ:
  2608. sample_rate_val = 0;
  2609. break;
  2610. case SAMPLING_RATE_44P1KHZ:
  2611. sample_rate_val = 1;
  2612. break;
  2613. case SAMPLING_RATE_48KHZ:
  2614. sample_rate_val = 2;
  2615. break;
  2616. case SAMPLING_RATE_88P2KHZ:
  2617. sample_rate_val = 3;
  2618. break;
  2619. case SAMPLING_RATE_96KHZ:
  2620. sample_rate_val = 4;
  2621. break;
  2622. case SAMPLING_RATE_176P4KHZ:
  2623. sample_rate_val = 5;
  2624. break;
  2625. case SAMPLING_RATE_192KHZ:
  2626. sample_rate_val = 6;
  2627. break;
  2628. default:
  2629. sample_rate_val = 2;
  2630. break;
  2631. }
  2632. return sample_rate_val;
  2633. }
  2634. static int spdif_get_sample_rate(int value)
  2635. {
  2636. int sample_rate;
  2637. switch (value) {
  2638. case 0:
  2639. sample_rate = SAMPLING_RATE_32KHZ;
  2640. break;
  2641. case 1:
  2642. sample_rate = SAMPLING_RATE_44P1KHZ;
  2643. break;
  2644. case 2:
  2645. sample_rate = SAMPLING_RATE_48KHZ;
  2646. break;
  2647. case 3:
  2648. sample_rate = SAMPLING_RATE_88P2KHZ;
  2649. break;
  2650. case 4:
  2651. sample_rate = SAMPLING_RATE_96KHZ;
  2652. break;
  2653. case 5:
  2654. sample_rate = SAMPLING_RATE_176P4KHZ;
  2655. break;
  2656. case 6:
  2657. sample_rate = SAMPLING_RATE_192KHZ;
  2658. break;
  2659. default:
  2660. sample_rate = SAMPLING_RATE_48KHZ;
  2661. break;
  2662. }
  2663. return sample_rate;
  2664. }
  2665. static int spdif_get_format(int value)
  2666. {
  2667. int format;
  2668. switch (value) {
  2669. case 0:
  2670. format = SNDRV_PCM_FORMAT_S16_LE;
  2671. break;
  2672. case 1:
  2673. format = SNDRV_PCM_FORMAT_S24_LE;
  2674. break;
  2675. default:
  2676. format = SNDRV_PCM_FORMAT_S16_LE;
  2677. break;
  2678. }
  2679. return format;
  2680. }
  2681. static int spdif_get_format_value(int format)
  2682. {
  2683. int value;
  2684. switch (format) {
  2685. case SNDRV_PCM_FORMAT_S16_LE:
  2686. value = 0;
  2687. break;
  2688. case SNDRV_PCM_FORMAT_S24_LE:
  2689. value = 1;
  2690. break;
  2691. default:
  2692. value = 0;
  2693. break;
  2694. }
  2695. return value;
  2696. }
  2697. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2698. struct snd_ctl_elem_value *ucontrol)
  2699. {
  2700. int idx = spdif_get_port_idx(kcontrol);
  2701. if (idx < 0)
  2702. return idx;
  2703. spdif_rx_cfg[idx].sample_rate =
  2704. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2705. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2706. idx, spdif_rx_cfg[idx].sample_rate,
  2707. ucontrol->value.enumerated.item[0]);
  2708. return 0;
  2709. }
  2710. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2711. struct snd_ctl_elem_value *ucontrol)
  2712. {
  2713. int idx = spdif_get_port_idx(kcontrol);
  2714. if (idx < 0)
  2715. return idx;
  2716. ucontrol->value.enumerated.item[0] =
  2717. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2718. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2719. idx, spdif_rx_cfg[idx].sample_rate,
  2720. ucontrol->value.enumerated.item[0]);
  2721. return 0;
  2722. }
  2723. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2724. struct snd_ctl_elem_value *ucontrol)
  2725. {
  2726. int idx = spdif_get_port_idx(kcontrol);
  2727. if (idx < 0)
  2728. return idx;
  2729. spdif_tx_cfg[idx].sample_rate =
  2730. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2731. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2732. idx, spdif_tx_cfg[idx].sample_rate,
  2733. ucontrol->value.enumerated.item[0]);
  2734. return 0;
  2735. }
  2736. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2737. struct snd_ctl_elem_value *ucontrol)
  2738. {
  2739. int idx = spdif_get_port_idx(kcontrol);
  2740. if (idx < 0)
  2741. return idx;
  2742. ucontrol->value.enumerated.item[0] =
  2743. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2744. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2745. idx, spdif_tx_cfg[idx].sample_rate,
  2746. ucontrol->value.enumerated.item[0]);
  2747. return 0;
  2748. }
  2749. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2750. struct snd_ctl_elem_value *ucontrol)
  2751. {
  2752. int idx = spdif_get_port_idx(kcontrol);
  2753. if (idx < 0)
  2754. return idx;
  2755. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2756. idx, spdif_rx_cfg[idx].channels);
  2757. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2758. return 0;
  2759. }
  2760. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2761. struct snd_ctl_elem_value *ucontrol)
  2762. {
  2763. int idx = spdif_get_port_idx(kcontrol);
  2764. if (idx < 0)
  2765. return idx;
  2766. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2767. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2768. idx, spdif_rx_cfg[idx].channels);
  2769. return 1;
  2770. }
  2771. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2772. struct snd_ctl_elem_value *ucontrol)
  2773. {
  2774. int idx = spdif_get_port_idx(kcontrol);
  2775. if (idx < 0)
  2776. return idx;
  2777. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2778. idx, spdif_tx_cfg[idx].channels);
  2779. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2780. return 0;
  2781. }
  2782. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2783. struct snd_ctl_elem_value *ucontrol)
  2784. {
  2785. int idx = spdif_get_port_idx(kcontrol);
  2786. if (idx < 0)
  2787. return idx;
  2788. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2789. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2790. idx, spdif_tx_cfg[idx].channels);
  2791. return 1;
  2792. }
  2793. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2794. struct snd_ctl_elem_value *ucontrol)
  2795. {
  2796. int idx = spdif_get_port_idx(kcontrol);
  2797. if (idx < 0)
  2798. return idx;
  2799. ucontrol->value.enumerated.item[0] =
  2800. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2801. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2802. idx, spdif_rx_cfg[idx].bit_format,
  2803. ucontrol->value.enumerated.item[0]);
  2804. return 0;
  2805. }
  2806. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2807. struct snd_ctl_elem_value *ucontrol)
  2808. {
  2809. int idx = spdif_get_port_idx(kcontrol);
  2810. if (idx < 0)
  2811. return idx;
  2812. spdif_rx_cfg[idx].bit_format =
  2813. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2814. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2815. idx, spdif_rx_cfg[idx].bit_format,
  2816. ucontrol->value.enumerated.item[0]);
  2817. return 0;
  2818. }
  2819. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2820. struct snd_ctl_elem_value *ucontrol)
  2821. {
  2822. int idx = spdif_get_port_idx(kcontrol);
  2823. if (idx < 0)
  2824. return idx;
  2825. ucontrol->value.enumerated.item[0] =
  2826. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2827. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2828. idx, spdif_tx_cfg[idx].bit_format,
  2829. ucontrol->value.enumerated.item[0]);
  2830. return 0;
  2831. }
  2832. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2833. struct snd_ctl_elem_value *ucontrol)
  2834. {
  2835. int idx = spdif_get_port_idx(kcontrol);
  2836. if (idx < 0)
  2837. return idx;
  2838. spdif_tx_cfg[idx].bit_format =
  2839. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2840. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2841. idx, spdif_tx_cfg[idx].bit_format,
  2842. ucontrol->value.enumerated.item[0]);
  2843. return 0;
  2844. }
  2845. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2846. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2847. slim_rx_ch_get, slim_rx_ch_put),
  2848. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2849. slim_rx_ch_get, slim_rx_ch_put),
  2850. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2851. slim_tx_ch_get, slim_tx_ch_put),
  2852. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2853. slim_tx_ch_get, slim_tx_ch_put),
  2854. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2855. slim_rx_ch_get, slim_rx_ch_put),
  2856. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2857. slim_rx_ch_get, slim_rx_ch_put),
  2858. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2859. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2860. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2861. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2862. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2863. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2864. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2865. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2866. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2867. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2868. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2869. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2870. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2871. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2872. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2873. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2874. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2875. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2876. };
  2877. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2878. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2879. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2880. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2881. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2882. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2883. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2884. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2885. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2886. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2887. va_cdc_dma_tx_0_sample_rate,
  2888. cdc_dma_tx_sample_rate_get,
  2889. cdc_dma_tx_sample_rate_put),
  2890. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2891. va_cdc_dma_tx_1_sample_rate,
  2892. cdc_dma_tx_sample_rate_get,
  2893. cdc_dma_tx_sample_rate_put),
  2894. };
  2895. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2896. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2897. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2898. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2899. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2900. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2901. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2902. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2903. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2904. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2905. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2906. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2907. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2908. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2909. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2910. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2911. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2912. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2913. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2914. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2915. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2916. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2917. wsa_cdc_dma_rx_0_sample_rate,
  2918. cdc_dma_rx_sample_rate_get,
  2919. cdc_dma_rx_sample_rate_put),
  2920. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2921. wsa_cdc_dma_rx_1_sample_rate,
  2922. cdc_dma_rx_sample_rate_get,
  2923. cdc_dma_rx_sample_rate_put),
  2924. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2925. wsa_cdc_dma_tx_0_sample_rate,
  2926. cdc_dma_tx_sample_rate_get,
  2927. cdc_dma_tx_sample_rate_put),
  2928. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2929. wsa_cdc_dma_tx_1_sample_rate,
  2930. cdc_dma_tx_sample_rate_get,
  2931. cdc_dma_tx_sample_rate_put),
  2932. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2933. wsa_cdc_dma_tx_2_sample_rate,
  2934. cdc_dma_tx_sample_rate_get,
  2935. cdc_dma_tx_sample_rate_put),
  2936. };
  2937. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2938. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2939. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2940. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2941. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2942. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2943. proxy_rx_ch_get, proxy_rx_ch_put),
  2944. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2945. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2946. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2947. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2948. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2949. msm_bt_sample_rate_get,
  2950. msm_bt_sample_rate_put),
  2951. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2952. usb_audio_rx_sample_rate_get,
  2953. usb_audio_rx_sample_rate_put),
  2954. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2955. usb_audio_tx_sample_rate_get,
  2956. usb_audio_tx_sample_rate_put),
  2957. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2958. tdm_rx_sample_rate_get,
  2959. tdm_rx_sample_rate_put),
  2960. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2961. tdm_tx_sample_rate_get,
  2962. tdm_tx_sample_rate_put),
  2963. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2964. tdm_rx_format_get,
  2965. tdm_rx_format_put),
  2966. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2967. tdm_tx_format_get,
  2968. tdm_tx_format_put),
  2969. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2970. tdm_rx_ch_get,
  2971. tdm_rx_ch_put),
  2972. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2973. tdm_tx_ch_get,
  2974. tdm_tx_ch_put),
  2975. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2976. tdm_rx_sample_rate_get,
  2977. tdm_rx_sample_rate_put),
  2978. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2979. tdm_tx_sample_rate_get,
  2980. tdm_tx_sample_rate_put),
  2981. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2982. tdm_rx_format_get,
  2983. tdm_rx_format_put),
  2984. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2985. tdm_tx_format_get,
  2986. tdm_tx_format_put),
  2987. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2988. tdm_rx_ch_get,
  2989. tdm_rx_ch_put),
  2990. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2991. tdm_tx_ch_get,
  2992. tdm_tx_ch_put),
  2993. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2994. tdm_rx_sample_rate_get,
  2995. tdm_rx_sample_rate_put),
  2996. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2997. tdm_tx_sample_rate_get,
  2998. tdm_tx_sample_rate_put),
  2999. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3000. tdm_rx_format_get,
  3001. tdm_rx_format_put),
  3002. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3003. tdm_tx_format_get,
  3004. tdm_tx_format_put),
  3005. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3006. tdm_rx_ch_get,
  3007. tdm_rx_ch_put),
  3008. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3009. tdm_tx_ch_get,
  3010. tdm_tx_ch_put),
  3011. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3012. tdm_rx_sample_rate_get,
  3013. tdm_rx_sample_rate_put),
  3014. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3015. tdm_tx_sample_rate_get,
  3016. tdm_tx_sample_rate_put),
  3017. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3018. tdm_rx_format_get,
  3019. tdm_rx_format_put),
  3020. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3021. tdm_tx_format_get,
  3022. tdm_tx_format_put),
  3023. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3024. tdm_rx_ch_get,
  3025. tdm_rx_ch_put),
  3026. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3027. tdm_tx_ch_get,
  3028. tdm_tx_ch_put),
  3029. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3030. tdm_rx_sample_rate_get,
  3031. tdm_rx_sample_rate_put),
  3032. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3033. tdm_tx_sample_rate_get,
  3034. tdm_tx_sample_rate_put),
  3035. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3036. tdm_rx_format_get,
  3037. tdm_rx_format_put),
  3038. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3039. tdm_tx_format_get,
  3040. tdm_tx_format_put),
  3041. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3042. tdm_rx_ch_get,
  3043. tdm_rx_ch_put),
  3044. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3045. tdm_tx_ch_get,
  3046. tdm_tx_ch_put),
  3047. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3048. aux_pcm_rx_sample_rate_get,
  3049. aux_pcm_rx_sample_rate_put),
  3050. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3051. aux_pcm_rx_sample_rate_get,
  3052. aux_pcm_rx_sample_rate_put),
  3053. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3054. aux_pcm_rx_sample_rate_get,
  3055. aux_pcm_rx_sample_rate_put),
  3056. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3057. aux_pcm_rx_sample_rate_get,
  3058. aux_pcm_rx_sample_rate_put),
  3059. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3060. aux_pcm_rx_sample_rate_get,
  3061. aux_pcm_rx_sample_rate_put),
  3062. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3063. aux_pcm_tx_sample_rate_get,
  3064. aux_pcm_tx_sample_rate_put),
  3065. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3066. aux_pcm_tx_sample_rate_get,
  3067. aux_pcm_tx_sample_rate_put),
  3068. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3069. aux_pcm_tx_sample_rate_get,
  3070. aux_pcm_tx_sample_rate_put),
  3071. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3072. aux_pcm_tx_sample_rate_get,
  3073. aux_pcm_tx_sample_rate_put),
  3074. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3075. aux_pcm_tx_sample_rate_get,
  3076. aux_pcm_tx_sample_rate_put),
  3077. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3078. mi2s_rx_sample_rate_get,
  3079. mi2s_rx_sample_rate_put),
  3080. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3081. mi2s_rx_sample_rate_get,
  3082. mi2s_rx_sample_rate_put),
  3083. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3084. mi2s_rx_sample_rate_get,
  3085. mi2s_rx_sample_rate_put),
  3086. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3087. mi2s_rx_sample_rate_get,
  3088. mi2s_rx_sample_rate_put),
  3089. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3090. mi2s_rx_sample_rate_get,
  3091. mi2s_rx_sample_rate_put),
  3092. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3093. mi2s_tx_sample_rate_get,
  3094. mi2s_tx_sample_rate_put),
  3095. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3096. mi2s_tx_sample_rate_get,
  3097. mi2s_tx_sample_rate_put),
  3098. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3099. mi2s_tx_sample_rate_get,
  3100. mi2s_tx_sample_rate_put),
  3101. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3102. mi2s_tx_sample_rate_get,
  3103. mi2s_tx_sample_rate_put),
  3104. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3105. mi2s_tx_sample_rate_get,
  3106. mi2s_tx_sample_rate_put),
  3107. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3108. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3109. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3110. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3111. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3112. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3113. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3114. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3115. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3116. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3117. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3118. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3119. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3120. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3121. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3122. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3123. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3124. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3125. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3126. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3127. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3128. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3129. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3130. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3131. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3132. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3133. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3134. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3135. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3136. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3137. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3138. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3139. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3140. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3141. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3142. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3143. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3144. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3145. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3146. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3147. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3148. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3149. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3150. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3151. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3152. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3153. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3154. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3155. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3156. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3157. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3158. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3159. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3160. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3161. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3162. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3163. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3164. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3165. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3166. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3167. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3168. msm_snd_vad_cfg_put),
  3169. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3170. msm_spdif_rx_sample_rate_get,
  3171. msm_spdif_rx_sample_rate_put),
  3172. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3173. msm_spdif_tx_sample_rate_get,
  3174. msm_spdif_tx_sample_rate_put),
  3175. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3176. msm_spdif_rx_sample_rate_get,
  3177. msm_spdif_rx_sample_rate_put),
  3178. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3179. msm_spdif_tx_sample_rate_get,
  3180. msm_spdif_tx_sample_rate_put),
  3181. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3182. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3183. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3184. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3185. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3186. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3187. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3188. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3189. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3190. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3191. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3192. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3193. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3194. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3195. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3196. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3197. };
  3198. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  3199. int enable, bool dapm)
  3200. {
  3201. int ret = 0;
  3202. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3203. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  3204. } else {
  3205. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  3206. __func__);
  3207. ret = -EINVAL;
  3208. }
  3209. return ret;
  3210. }
  3211. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  3212. int enable, bool dapm)
  3213. {
  3214. int ret = 0;
  3215. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3216. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  3217. } else {
  3218. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  3219. __func__);
  3220. ret = -EINVAL;
  3221. }
  3222. return ret;
  3223. }
  3224. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3225. struct snd_kcontrol *kcontrol, int event)
  3226. {
  3227. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3228. pr_debug("%s: event = %d\n", __func__, event);
  3229. switch (event) {
  3230. case SND_SOC_DAPM_PRE_PMU:
  3231. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  3232. case SND_SOC_DAPM_POST_PMD:
  3233. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  3234. }
  3235. return 0;
  3236. }
  3237. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3238. struct snd_kcontrol *kcontrol, int event)
  3239. {
  3240. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3241. pr_debug("%s: event = %d\n", __func__, event);
  3242. switch (event) {
  3243. case SND_SOC_DAPM_PRE_PMU:
  3244. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  3245. case SND_SOC_DAPM_POST_PMD:
  3246. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  3247. }
  3248. return 0;
  3249. }
  3250. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3251. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3252. msm_mclk_event,
  3253. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3254. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3255. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3256. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3257. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3258. };
  3259. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3260. struct snd_kcontrol *kcontrol, int event)
  3261. {
  3262. struct msm_asoc_mach_data *pdata = NULL;
  3263. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3264. int ret = 0;
  3265. uint32_t dmic_idx;
  3266. int *dmic_gpio_cnt;
  3267. struct device_node *dmic_gpio;
  3268. char *wname;
  3269. wname = strpbrk(w->name, "01234567");
  3270. if (!wname) {
  3271. dev_err(codec->dev, "%s: widget not found\n", __func__);
  3272. return -EINVAL;
  3273. }
  3274. ret = kstrtouint(wname, 10, &dmic_idx);
  3275. if (ret < 0) {
  3276. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  3277. __func__);
  3278. return -EINVAL;
  3279. }
  3280. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3281. switch (dmic_idx) {
  3282. case 0:
  3283. case 1:
  3284. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3285. dmic_gpio = pdata->dmic_01_gpio_p;
  3286. break;
  3287. case 2:
  3288. case 3:
  3289. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3290. dmic_gpio = pdata->dmic_23_gpio_p;
  3291. break;
  3292. case 4:
  3293. case 5:
  3294. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3295. dmic_gpio = pdata->dmic_45_gpio_p;
  3296. break;
  3297. case 6:
  3298. case 7:
  3299. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3300. dmic_gpio = pdata->dmic_67_gpio_p;
  3301. break;
  3302. default:
  3303. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  3304. __func__);
  3305. return -EINVAL;
  3306. }
  3307. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3308. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3309. switch (event) {
  3310. case SND_SOC_DAPM_PRE_PMU:
  3311. (*dmic_gpio_cnt)++;
  3312. if (*dmic_gpio_cnt == 1) {
  3313. ret = msm_cdc_pinctrl_select_active_state(
  3314. dmic_gpio);
  3315. if (ret < 0) {
  3316. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  3317. __func__, "dmic_gpio");
  3318. return ret;
  3319. }
  3320. }
  3321. break;
  3322. case SND_SOC_DAPM_POST_PMD:
  3323. (*dmic_gpio_cnt)--;
  3324. if (*dmic_gpio_cnt == 0) {
  3325. ret = msm_cdc_pinctrl_select_sleep_state(
  3326. dmic_gpio);
  3327. if (ret < 0) {
  3328. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  3329. __func__, "dmic_gpio");
  3330. return ret;
  3331. }
  3332. }
  3333. break;
  3334. default:
  3335. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3336. __func__, event);
  3337. return -EINVAL;
  3338. }
  3339. return 0;
  3340. }
  3341. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3342. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3343. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3344. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3345. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3346. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3347. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3348. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3349. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3350. };
  3351. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3352. };
  3353. static inline int param_is_mask(int p)
  3354. {
  3355. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3356. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3357. }
  3358. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3359. int n)
  3360. {
  3361. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3362. }
  3363. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3364. unsigned int bit)
  3365. {
  3366. if (bit >= SNDRV_MASK_MAX)
  3367. return;
  3368. if (param_is_mask(n)) {
  3369. struct snd_mask *m = param_to_mask(p, n);
  3370. m->bits[0] = 0;
  3371. m->bits[1] = 0;
  3372. m->bits[bit >> 5] |= (1 << (bit & 31));
  3373. }
  3374. }
  3375. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3376. {
  3377. int ch_id = 0;
  3378. switch (be_id) {
  3379. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3380. ch_id = SLIM_RX_0;
  3381. break;
  3382. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3383. ch_id = SLIM_RX_1;
  3384. break;
  3385. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3386. ch_id = SLIM_RX_2;
  3387. break;
  3388. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3389. ch_id = SLIM_RX_3;
  3390. break;
  3391. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3392. ch_id = SLIM_RX_4;
  3393. break;
  3394. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3395. ch_id = SLIM_RX_6;
  3396. break;
  3397. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3398. ch_id = SLIM_TX_0;
  3399. break;
  3400. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3401. ch_id = SLIM_TX_3;
  3402. break;
  3403. default:
  3404. ch_id = SLIM_RX_0;
  3405. break;
  3406. }
  3407. return ch_id;
  3408. }
  3409. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3410. {
  3411. *port_id = 0xFFFF;
  3412. switch (be_id) {
  3413. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3414. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3415. break;
  3416. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3417. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3418. break;
  3419. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3420. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3421. break;
  3422. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3423. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3424. break;
  3425. default:
  3426. return -EINVAL;
  3427. }
  3428. return 0;
  3429. }
  3430. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3431. {
  3432. int idx = 0;
  3433. switch (be_id) {
  3434. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3435. idx = WSA_CDC_DMA_RX_0;
  3436. break;
  3437. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3438. idx = WSA_CDC_DMA_TX_0;
  3439. break;
  3440. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3441. idx = WSA_CDC_DMA_RX_1;
  3442. break;
  3443. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3444. idx = WSA_CDC_DMA_TX_1;
  3445. break;
  3446. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3447. idx = WSA_CDC_DMA_TX_2;
  3448. break;
  3449. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3450. idx = VA_CDC_DMA_TX_0;
  3451. break;
  3452. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3453. idx = VA_CDC_DMA_TX_1;
  3454. break;
  3455. default:
  3456. idx = VA_CDC_DMA_TX_0;
  3457. break;
  3458. }
  3459. return idx;
  3460. }
  3461. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3462. struct snd_pcm_hw_params *params)
  3463. {
  3464. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3465. struct snd_interval *rate = hw_param_interval(params,
  3466. SNDRV_PCM_HW_PARAM_RATE);
  3467. struct snd_interval *channels = hw_param_interval(params,
  3468. SNDRV_PCM_HW_PARAM_CHANNELS);
  3469. int rc = 0;
  3470. int idx;
  3471. void *config = NULL;
  3472. struct snd_soc_codec *codec = NULL;
  3473. pr_debug("%s: format = %d, rate = %d\n",
  3474. __func__, params_format(params), params_rate(params));
  3475. switch (dai_link->id) {
  3476. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3477. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3478. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3479. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3480. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3481. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3482. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3483. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3484. slim_rx_cfg[idx].bit_format);
  3485. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3486. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3487. break;
  3488. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3489. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3490. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3491. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3492. slim_tx_cfg[idx].bit_format);
  3493. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3494. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3495. break;
  3496. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3497. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3498. slim_tx_cfg[1].bit_format);
  3499. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3500. channels->min = channels->max = slim_tx_cfg[1].channels;
  3501. break;
  3502. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3503. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3504. SNDRV_PCM_FORMAT_S32_LE);
  3505. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3506. channels->min = channels->max = msm_vi_feed_tx_ch;
  3507. break;
  3508. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3509. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3510. slim_rx_cfg[5].bit_format);
  3511. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3512. channels->min = channels->max = slim_rx_cfg[5].channels;
  3513. break;
  3514. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3515. codec = rtd->codec;
  3516. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3517. channels->min = channels->max = 1;
  3518. config = msm_codec_fn.get_afe_config_fn(codec,
  3519. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3520. if (config) {
  3521. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3522. config, SLIMBUS_5_TX);
  3523. if (rc)
  3524. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3525. __func__, rc);
  3526. }
  3527. break;
  3528. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3529. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3530. slim_rx_cfg[SLIM_RX_7].bit_format);
  3531. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3532. channels->min = channels->max =
  3533. slim_rx_cfg[SLIM_RX_7].channels;
  3534. break;
  3535. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3536. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3537. channels->min = channels->max =
  3538. slim_tx_cfg[SLIM_TX_7].channels;
  3539. break;
  3540. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3541. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3542. channels->min = channels->max =
  3543. slim_tx_cfg[SLIM_TX_8].channels;
  3544. break;
  3545. case MSM_BACKEND_DAI_USB_RX:
  3546. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3547. usb_rx_cfg.bit_format);
  3548. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3549. channels->min = channels->max = usb_rx_cfg.channels;
  3550. break;
  3551. case MSM_BACKEND_DAI_USB_TX:
  3552. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3553. usb_tx_cfg.bit_format);
  3554. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3555. channels->min = channels->max = usb_tx_cfg.channels;
  3556. break;
  3557. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3558. channels->min = channels->max = proxy_rx_cfg.channels;
  3559. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3560. break;
  3561. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3562. channels->min = channels->max =
  3563. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3564. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3565. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3566. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3567. break;
  3568. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3569. channels->min = channels->max =
  3570. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3571. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3572. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3573. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3574. break;
  3575. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3576. channels->min = channels->max =
  3577. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3578. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3579. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3580. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3581. break;
  3582. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3583. channels->min = channels->max =
  3584. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3585. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3586. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3587. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3588. break;
  3589. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3590. channels->min = channels->max =
  3591. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3592. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3593. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3594. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3595. break;
  3596. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3597. channels->min = channels->max =
  3598. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3599. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3600. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3601. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3602. break;
  3603. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3604. channels->min = channels->max =
  3605. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3606. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3607. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3608. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3609. break;
  3610. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3611. channels->min = channels->max =
  3612. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3613. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3614. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3615. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3616. break;
  3617. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3618. channels->min = channels->max =
  3619. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3620. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3621. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3622. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3623. break;
  3624. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3625. channels->min = channels->max =
  3626. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3627. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3628. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3629. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3630. break;
  3631. case MSM_BACKEND_DAI_AUXPCM_RX:
  3632. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3633. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3634. rate->min = rate->max =
  3635. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3636. channels->min = channels->max =
  3637. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3638. break;
  3639. case MSM_BACKEND_DAI_AUXPCM_TX:
  3640. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3641. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3642. rate->min = rate->max =
  3643. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3644. channels->min = channels->max =
  3645. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3646. break;
  3647. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3648. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3649. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3650. rate->min = rate->max =
  3651. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3652. channels->min = channels->max =
  3653. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3654. break;
  3655. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3656. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3657. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3658. rate->min = rate->max =
  3659. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3660. channels->min = channels->max =
  3661. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3662. break;
  3663. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3664. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3665. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3666. rate->min = rate->max =
  3667. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3668. channels->min = channels->max =
  3669. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3670. break;
  3671. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3672. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3673. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3674. rate->min = rate->max =
  3675. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3676. channels->min = channels->max =
  3677. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3678. break;
  3679. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3680. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3681. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3682. rate->min = rate->max =
  3683. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3684. channels->min = channels->max =
  3685. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3686. break;
  3687. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3688. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3689. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3690. rate->min = rate->max =
  3691. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3692. channels->min = channels->max =
  3693. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3694. break;
  3695. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3696. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3697. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3698. rate->min = rate->max =
  3699. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3700. channels->min = channels->max =
  3701. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3702. break;
  3703. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3704. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3705. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3706. rate->min = rate->max =
  3707. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3708. channels->min = channels->max =
  3709. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3710. break;
  3711. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3712. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3713. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3714. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3715. channels->min = channels->max =
  3716. mi2s_rx_cfg[PRIM_MI2S].channels;
  3717. break;
  3718. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3719. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3720. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3721. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3722. channels->min = channels->max =
  3723. mi2s_tx_cfg[PRIM_MI2S].channels;
  3724. break;
  3725. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3726. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3727. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3728. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3729. channels->min = channels->max =
  3730. mi2s_rx_cfg[SEC_MI2S].channels;
  3731. break;
  3732. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3733. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3734. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3735. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3736. channels->min = channels->max =
  3737. mi2s_tx_cfg[SEC_MI2S].channels;
  3738. break;
  3739. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3740. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3741. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3742. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3743. channels->min = channels->max =
  3744. mi2s_rx_cfg[TERT_MI2S].channels;
  3745. break;
  3746. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3747. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3748. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3749. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3750. channels->min = channels->max =
  3751. mi2s_tx_cfg[TERT_MI2S].channels;
  3752. break;
  3753. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3754. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3755. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3756. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3757. channels->min = channels->max =
  3758. mi2s_rx_cfg[QUAT_MI2S].channels;
  3759. break;
  3760. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3761. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3762. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3763. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3764. channels->min = channels->max =
  3765. mi2s_tx_cfg[QUAT_MI2S].channels;
  3766. break;
  3767. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3768. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3769. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3770. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3771. channels->min = channels->max =
  3772. mi2s_rx_cfg[QUIN_MI2S].channels;
  3773. break;
  3774. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3775. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3776. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3777. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3778. channels->min = channels->max =
  3779. mi2s_tx_cfg[QUIN_MI2S].channels;
  3780. break;
  3781. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3782. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3783. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3784. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3785. cdc_dma_rx_cfg[idx].bit_format);
  3786. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3787. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3788. break;
  3789. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3790. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3791. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3792. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3793. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3794. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3795. cdc_dma_tx_cfg[idx].bit_format);
  3796. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3797. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3798. break;
  3799. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3800. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3801. SNDRV_PCM_FORMAT_S32_LE);
  3802. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3803. channels->min = channels->max = msm_vi_feed_tx_ch;
  3804. break;
  3805. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  3806. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3807. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  3808. rate->min = rate->max =
  3809. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  3810. channels->min = channels->max =
  3811. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  3812. break;
  3813. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  3814. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3815. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  3816. rate->min = rate->max =
  3817. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  3818. channels->min = channels->max =
  3819. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  3820. break;
  3821. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  3822. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3823. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  3824. rate->min = rate->max =
  3825. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  3826. channels->min = channels->max =
  3827. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  3828. break;
  3829. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  3830. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3831. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  3832. rate->min = rate->max =
  3833. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  3834. channels->min = channels->max =
  3835. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  3836. break;
  3837. default:
  3838. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3839. break;
  3840. }
  3841. return rc;
  3842. }
  3843. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3844. {
  3845. int ret = 0;
  3846. void *config_data = NULL;
  3847. if (!msm_codec_fn.get_afe_config_fn) {
  3848. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3849. __func__);
  3850. return -EINVAL;
  3851. }
  3852. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3853. AFE_CDC_REGISTERS_CONFIG);
  3854. if (config_data) {
  3855. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3856. if (ret) {
  3857. dev_err(codec->dev,
  3858. "%s: Failed to set codec registers config %d\n",
  3859. __func__, ret);
  3860. return ret;
  3861. }
  3862. }
  3863. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3864. AFE_CDC_REGISTER_PAGE_CONFIG);
  3865. if (config_data) {
  3866. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3867. 0);
  3868. if (ret)
  3869. dev_err(codec->dev,
  3870. "%s: Failed to set cdc register page config\n",
  3871. __func__);
  3872. }
  3873. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3874. AFE_SLIMBUS_SLAVE_CONFIG);
  3875. if (config_data) {
  3876. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3877. if (ret) {
  3878. dev_err(codec->dev,
  3879. "%s: Failed to set slimbus slave config %d\n",
  3880. __func__, ret);
  3881. return ret;
  3882. }
  3883. }
  3884. return 0;
  3885. }
  3886. static void msm_afe_clear_config(void)
  3887. {
  3888. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3889. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3890. }
  3891. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3892. struct snd_card *card)
  3893. {
  3894. int ret = 0;
  3895. unsigned long timeout;
  3896. int adsp_ready = 0;
  3897. bool snd_card_online = 0;
  3898. timeout = jiffies +
  3899. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3900. do {
  3901. if (!snd_card_online) {
  3902. snd_card_online = snd_card_is_online_state(card);
  3903. pr_debug("%s: Sound card is %s\n", __func__,
  3904. snd_card_online ? "Online" : "Offline");
  3905. }
  3906. if (!adsp_ready) {
  3907. adsp_ready = q6core_is_adsp_ready();
  3908. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3909. adsp_ready ? "ready" : "not ready");
  3910. }
  3911. if (snd_card_online && adsp_ready)
  3912. break;
  3913. /*
  3914. * Sound card/ADSP will be coming up after subsystem restart and
  3915. * it might not be fully up when the control reaches
  3916. * here. So, wait for 50msec before checking ADSP state
  3917. */
  3918. msleep(50);
  3919. } while (time_after(timeout, jiffies));
  3920. if (!snd_card_online || !adsp_ready) {
  3921. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3922. __func__,
  3923. snd_card_online ? "Online" : "Offline",
  3924. adsp_ready ? "ready" : "not ready");
  3925. ret = -ETIMEDOUT;
  3926. goto err;
  3927. }
  3928. ret = msm_afe_set_config(codec);
  3929. if (ret)
  3930. pr_err("%s: Failed to set AFE config. err %d\n",
  3931. __func__, ret);
  3932. return 0;
  3933. err:
  3934. return ret;
  3935. }
  3936. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3937. unsigned long opcode, void *ptr)
  3938. {
  3939. int ret;
  3940. struct snd_soc_card *card = NULL;
  3941. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3942. struct snd_soc_pcm_runtime *rtd;
  3943. struct snd_soc_codec *codec;
  3944. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3945. switch (opcode) {
  3946. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3947. /*
  3948. * Use flag to ignore initial boot notifications
  3949. * On initial boot msm_adsp_power_up_config is
  3950. * called on init. There is no need to clear
  3951. * and set the config again on initial boot.
  3952. */
  3953. if (is_initial_boot)
  3954. break;
  3955. msm_afe_clear_config();
  3956. break;
  3957. case AUDIO_NOTIFIER_SERVICE_UP:
  3958. if (is_initial_boot) {
  3959. is_initial_boot = false;
  3960. break;
  3961. }
  3962. if (!spdev)
  3963. return -EINVAL;
  3964. card = platform_get_drvdata(spdev);
  3965. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3966. if (!rtd) {
  3967. dev_err(card->dev,
  3968. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3969. __func__, be_dl_name);
  3970. ret = -EINVAL;
  3971. goto err;
  3972. }
  3973. codec = rtd->codec;
  3974. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3975. if (ret < 0) {
  3976. dev_err(card->dev,
  3977. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3978. __func__, ret);
  3979. goto err;
  3980. }
  3981. break;
  3982. default:
  3983. break;
  3984. }
  3985. err:
  3986. return NOTIFY_OK;
  3987. }
  3988. static struct notifier_block service_nb = {
  3989. .notifier_call = qcs405_notifier_service_cb,
  3990. .priority = -INT_MAX,
  3991. };
  3992. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3993. {
  3994. int ret = 0;
  3995. void *config_data;
  3996. struct snd_soc_codec *codec = rtd->codec;
  3997. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3998. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3999. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4000. struct snd_card *card;
  4001. struct msm_asoc_mach_data *pdata =
  4002. snd_soc_card_get_drvdata(rtd->card);
  4003. /*
  4004. * Codec SLIMBUS configuration
  4005. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4006. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4007. * TX14, TX15, TX16
  4008. */
  4009. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4010. 151, 152, 153, 154, 155, 156};
  4011. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4012. 134, 135, 136, 137, 138, 139,
  4013. 140, 141, 142, 143};
  4014. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4015. rtd->pmdown_time = 0;
  4016. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  4017. ARRAY_SIZE(msm_snd_sb_controls));
  4018. if (ret < 0) {
  4019. pr_err("%s: add_codec_controls failed, err %d\n",
  4020. __func__, ret);
  4021. return ret;
  4022. }
  4023. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4024. ARRAY_SIZE(msm_dapm_widgets));
  4025. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4026. ARRAY_SIZE(wcd_audio_paths));
  4027. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4028. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4029. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4030. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4031. snd_soc_dapm_sync(dapm);
  4032. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4033. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4034. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4035. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  4036. if (ret) {
  4037. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  4038. __func__, ret);
  4039. goto err;
  4040. }
  4041. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4042. AFE_AANC_VERSION);
  4043. if (config_data) {
  4044. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4045. if (ret) {
  4046. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  4047. __func__, ret);
  4048. goto err;
  4049. }
  4050. }
  4051. card = rtd->card->snd_card;
  4052. if (!pdata->codec_root)
  4053. pdata->codec_root = snd_info_create_subdir(card->module,
  4054. "codecs", card->proc_root);
  4055. if (!pdata->codec_root) {
  4056. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4057. __func__);
  4058. ret = 0;
  4059. goto err;
  4060. }
  4061. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  4062. codec_reg_done = true;
  4063. return 0;
  4064. err:
  4065. return ret;
  4066. }
  4067. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4068. {
  4069. int ret = 0;
  4070. struct snd_soc_codec *codec = rtd->codec;
  4071. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4072. struct snd_card *card;
  4073. struct msm_asoc_mach_data *pdata =
  4074. snd_soc_card_get_drvdata(rtd->card);
  4075. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  4076. ARRAY_SIZE(msm_snd_va_controls));
  4077. if (ret < 0) {
  4078. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  4079. __func__, ret);
  4080. return ret;
  4081. }
  4082. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4083. ARRAY_SIZE(msm_va_dapm_widgets));
  4084. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4085. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4086. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4087. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4088. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4089. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4090. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4091. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4092. snd_soc_dapm_sync(dapm);
  4093. card = rtd->card->snd_card;
  4094. if (!pdata->codec_root)
  4095. pdata->codec_root = snd_info_create_subdir(card->module,
  4096. "codecs", card->proc_root);
  4097. if (!pdata->codec_root) {
  4098. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4099. __func__);
  4100. ret = 0;
  4101. goto done;
  4102. }
  4103. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4104. done:
  4105. return ret;
  4106. }
  4107. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4108. {
  4109. int ret = 0;
  4110. struct snd_soc_codec *codec = rtd->codec;
  4111. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4112. struct snd_soc_component *aux_comp;
  4113. struct snd_card *card;
  4114. struct msm_asoc_mach_data *pdata =
  4115. snd_soc_card_get_drvdata(rtd->card);
  4116. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  4117. ARRAY_SIZE(msm_snd_wsa_controls));
  4118. if (ret < 0) {
  4119. dev_err(codec->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4120. __func__, ret);
  4121. return ret;
  4122. }
  4123. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4124. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4125. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4126. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4127. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4128. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4129. snd_soc_dapm_sync(dapm);
  4130. /*
  4131. * Send speaker configuration only for WSA8810.
  4132. * Default configuration is for WSA8815.
  4133. */
  4134. dev_dbg(codec->dev, "%s: Number of aux devices: %d\n",
  4135. __func__, rtd->card->num_aux_devs);
  4136. if (rtd->card->num_aux_devs &&
  4137. !list_empty(&rtd->card->component_dev_list)) {
  4138. aux_comp = list_first_entry(
  4139. &rtd->card->component_dev_list,
  4140. struct snd_soc_component,
  4141. card_aux_list);
  4142. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4143. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4144. wsa_macro_set_spkr_mode(rtd->codec,
  4145. WSA_MACRO_SPKR_MODE_1);
  4146. wsa_macro_set_spkr_gain_offset(rtd->codec,
  4147. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4148. }
  4149. }
  4150. card = rtd->card->snd_card;
  4151. if (!pdata->codec_root)
  4152. pdata->codec_root = snd_info_create_subdir(card->module,
  4153. "codecs", card->proc_root);
  4154. if (!pdata->codec_root) {
  4155. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4156. __func__);
  4157. ret = 0;
  4158. goto done;
  4159. }
  4160. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4161. done:
  4162. return ret;
  4163. }
  4164. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4165. {
  4166. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4167. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  4168. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4169. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4170. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4171. }
  4172. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4173. struct snd_pcm_hw_params *params)
  4174. {
  4175. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4176. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4177. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4178. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4179. int ret = 0;
  4180. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4181. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4182. u32 user_set_tx_ch = 0;
  4183. u32 rx_ch_count;
  4184. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4185. ret = snd_soc_dai_get_channel_map(codec_dai,
  4186. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4187. if (ret < 0) {
  4188. pr_err("%s: failed to get codec chan map, err:%d\n",
  4189. __func__, ret);
  4190. goto err;
  4191. }
  4192. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4193. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4194. slim_rx_cfg[5].channels);
  4195. rx_ch_count = slim_rx_cfg[5].channels;
  4196. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4197. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4198. slim_rx_cfg[2].channels);
  4199. rx_ch_count = slim_rx_cfg[2].channels;
  4200. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4201. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4202. slim_rx_cfg[6].channels);
  4203. rx_ch_count = slim_rx_cfg[6].channels;
  4204. } else {
  4205. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4206. slim_rx_cfg[0].channels);
  4207. rx_ch_count = slim_rx_cfg[0].channels;
  4208. }
  4209. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4210. rx_ch_count, rx_ch);
  4211. if (ret < 0) {
  4212. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4213. __func__, ret);
  4214. goto err;
  4215. }
  4216. } else {
  4217. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4218. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4219. ret = snd_soc_dai_get_channel_map(codec_dai,
  4220. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4221. if (ret < 0) {
  4222. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4223. __func__, ret);
  4224. goto err;
  4225. }
  4226. /* For <codec>_tx1 case */
  4227. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4228. user_set_tx_ch = slim_tx_cfg[0].channels;
  4229. /* For <codec>_tx3 case */
  4230. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4231. user_set_tx_ch = slim_tx_cfg[1].channels;
  4232. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4233. user_set_tx_ch = msm_vi_feed_tx_ch;
  4234. else
  4235. user_set_tx_ch = tx_ch_cnt;
  4236. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4237. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4238. tx_ch_cnt, dai_link->id);
  4239. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4240. user_set_tx_ch, tx_ch, 0, 0);
  4241. if (ret < 0)
  4242. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4243. __func__, ret);
  4244. }
  4245. err:
  4246. return ret;
  4247. }
  4248. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4249. struct snd_pcm_hw_params *params)
  4250. {
  4251. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4252. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4253. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4254. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4255. int ret = 0;
  4256. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4257. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4258. u32 user_set_tx_ch = 0;
  4259. u32 user_set_rx_ch = 0;
  4260. u32 ch_id;
  4261. ret = snd_soc_dai_get_channel_map(codec_dai,
  4262. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4263. &rx_ch_cdc_dma);
  4264. if (ret < 0) {
  4265. pr_err("%s: failed to get codec chan map, err:%d\n",
  4266. __func__, ret);
  4267. goto err;
  4268. }
  4269. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4270. switch (dai_link->id) {
  4271. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4272. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4273. {
  4274. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4275. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4276. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4277. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4278. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4279. user_set_rx_ch, &rx_ch_cdc_dma);
  4280. if (ret < 0) {
  4281. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4282. __func__, ret);
  4283. goto err;
  4284. }
  4285. }
  4286. break;
  4287. }
  4288. } else {
  4289. switch (dai_link->id) {
  4290. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4291. {
  4292. user_set_tx_ch = msm_vi_feed_tx_ch;
  4293. }
  4294. break;
  4295. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4296. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4297. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4298. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4299. {
  4300. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4301. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4302. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4303. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4304. }
  4305. break;
  4306. }
  4307. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4308. &tx_ch_cdc_dma, 0, 0);
  4309. if (ret < 0) {
  4310. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4311. __func__, ret);
  4312. goto err;
  4313. }
  4314. }
  4315. err:
  4316. return ret;
  4317. }
  4318. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4319. struct snd_pcm_hw_params *params)
  4320. {
  4321. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4322. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4323. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4324. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4325. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4326. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4327. int ret;
  4328. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4329. codec_dai->name, codec_dai->id);
  4330. ret = snd_soc_dai_get_channel_map(codec_dai,
  4331. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4332. if (ret) {
  4333. dev_err(rtd->dev,
  4334. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4335. __func__, ret);
  4336. goto err;
  4337. }
  4338. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4339. __func__, tx_ch_cnt, dai_link->id);
  4340. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4341. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4342. if (ret)
  4343. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4344. __func__, ret);
  4345. err:
  4346. return ret;
  4347. }
  4348. static int msm_get_port_id(int be_id)
  4349. {
  4350. int afe_port_id;
  4351. switch (be_id) {
  4352. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4353. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4354. break;
  4355. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4356. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4357. break;
  4358. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4359. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4360. break;
  4361. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4362. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4363. break;
  4364. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4365. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4366. break;
  4367. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4368. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4369. break;
  4370. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4371. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4372. break;
  4373. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4374. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4375. break;
  4376. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4377. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4378. break;
  4379. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4380. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4381. break;
  4382. default:
  4383. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4384. afe_port_id = -EINVAL;
  4385. }
  4386. return afe_port_id;
  4387. }
  4388. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4389. {
  4390. u32 bit_per_sample;
  4391. switch (bit_format) {
  4392. case SNDRV_PCM_FORMAT_S32_LE:
  4393. case SNDRV_PCM_FORMAT_S24_3LE:
  4394. case SNDRV_PCM_FORMAT_S24_LE:
  4395. bit_per_sample = 32;
  4396. break;
  4397. case SNDRV_PCM_FORMAT_S16_LE:
  4398. default:
  4399. bit_per_sample = 16;
  4400. break;
  4401. }
  4402. return bit_per_sample;
  4403. }
  4404. static void update_mi2s_clk_val(int dai_id, int stream)
  4405. {
  4406. u32 bit_per_sample;
  4407. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4408. bit_per_sample =
  4409. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4410. mi2s_clk[dai_id].clk_freq_in_hz =
  4411. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4412. } else {
  4413. bit_per_sample =
  4414. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4415. mi2s_clk[dai_id].clk_freq_in_hz =
  4416. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4417. }
  4418. }
  4419. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4420. {
  4421. int ret = 0;
  4422. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4423. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4424. int port_id = 0;
  4425. int index = cpu_dai->id;
  4426. port_id = msm_get_port_id(rtd->dai_link->id);
  4427. if (port_id < 0) {
  4428. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4429. ret = port_id;
  4430. goto err;
  4431. }
  4432. if (enable) {
  4433. update_mi2s_clk_val(index, substream->stream);
  4434. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4435. mi2s_clk[index].clk_freq_in_hz);
  4436. }
  4437. mi2s_clk[index].enable = enable;
  4438. ret = afe_set_lpass_clock_v2(port_id,
  4439. &mi2s_clk[index]);
  4440. if (ret < 0) {
  4441. dev_err(rtd->card->dev,
  4442. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4443. __func__, port_id, ret);
  4444. goto err;
  4445. }
  4446. err:
  4447. return ret;
  4448. }
  4449. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4450. struct snd_pcm_hw_params *params)
  4451. {
  4452. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4453. struct snd_interval *rate = hw_param_interval(params,
  4454. SNDRV_PCM_HW_PARAM_RATE);
  4455. struct snd_interval *channels = hw_param_interval(params,
  4456. SNDRV_PCM_HW_PARAM_CHANNELS);
  4457. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4458. channels->min = channels->max =
  4459. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4460. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4461. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4462. rate->min = rate->max =
  4463. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4464. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4465. channels->min = channels->max =
  4466. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4467. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4468. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4469. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4470. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4471. channels->min = channels->max =
  4472. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4473. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4474. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4475. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4476. } else {
  4477. pr_err("%s: dai id 0x%x not supported\n",
  4478. __func__, cpu_dai->id);
  4479. return -EINVAL;
  4480. }
  4481. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4482. __func__, cpu_dai->id, channels->max, rate->max,
  4483. params_format(params));
  4484. return 0;
  4485. }
  4486. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4487. struct snd_pcm_hw_params *params)
  4488. {
  4489. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4490. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4491. int ret = 0;
  4492. int slot_width = 32;
  4493. int channels, slots = 8;
  4494. unsigned int slot_mask, rate, clk_freq;
  4495. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4496. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4497. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4498. switch (cpu_dai->id) {
  4499. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4500. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4501. break;
  4502. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4503. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4504. break;
  4505. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4506. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4507. break;
  4508. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4509. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4510. break;
  4511. case AFE_PORT_ID_QUINARY_TDM_RX:
  4512. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4513. break;
  4514. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4515. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4516. break;
  4517. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4518. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4519. break;
  4520. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4521. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4522. break;
  4523. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4524. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4525. break;
  4526. case AFE_PORT_ID_QUINARY_TDM_TX:
  4527. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4528. break;
  4529. default:
  4530. pr_err("%s: dai id 0x%x not supported\n",
  4531. __func__, cpu_dai->id);
  4532. return -EINVAL;
  4533. }
  4534. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4535. /*2 slot config - bits 0 and 1 set for the first two slots */
  4536. slot_mask = 0x0000FFFF >> (16-channels);
  4537. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4538. __func__, slot_width, slots);
  4539. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4540. slots, slot_width);
  4541. if (ret < 0) {
  4542. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4543. __func__, ret);
  4544. goto end;
  4545. }
  4546. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4547. 0, NULL, channels, slot_offset);
  4548. if (ret < 0) {
  4549. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4550. __func__, ret);
  4551. goto end;
  4552. }
  4553. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4554. /*2 slot config - bits 0 and 1 set for the first two slots */
  4555. slot_mask = 0x0000FFFF >> (16-channels);
  4556. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4557. __func__, slot_width, slots);
  4558. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4559. slots, slot_width);
  4560. if (ret < 0) {
  4561. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4562. __func__, ret);
  4563. goto end;
  4564. }
  4565. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4566. channels, slot_offset, 0, NULL);
  4567. if (ret < 0) {
  4568. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4569. __func__, ret);
  4570. goto end;
  4571. }
  4572. } else {
  4573. ret = -EINVAL;
  4574. pr_err("%s: invalid use case, err:%d\n",
  4575. __func__, ret);
  4576. goto end;
  4577. }
  4578. rate = params_rate(params);
  4579. clk_freq = rate * slot_width * slots;
  4580. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4581. if (ret < 0)
  4582. pr_err("%s: failed to set tdm clk, err:%d\n",
  4583. __func__, ret);
  4584. end:
  4585. return ret;
  4586. }
  4587. static int msm_get_tdm_mode(u32 port_id)
  4588. {
  4589. u32 tdm_mode;
  4590. switch (port_id) {
  4591. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4592. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4593. tdm_mode = TDM_PRI;
  4594. break;
  4595. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4596. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4597. tdm_mode = TDM_SEC;
  4598. break;
  4599. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4600. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4601. tdm_mode = TDM_TERT;
  4602. break;
  4603. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4604. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4605. tdm_mode = TDM_QUAT;
  4606. break;
  4607. case AFE_PORT_ID_QUINARY_TDM_RX:
  4608. case AFE_PORT_ID_QUINARY_TDM_TX:
  4609. tdm_mode = TDM_QUIN;
  4610. break;
  4611. default:
  4612. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  4613. tdm_mode = -EINVAL;
  4614. }
  4615. return tdm_mode;
  4616. }
  4617. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4618. {
  4619. int ret = 0;
  4620. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4621. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4622. struct snd_soc_card *card = rtd->card;
  4623. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4624. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4625. if (tdm_mode >= TDM_INTERFACE_MAX) {
  4626. ret = -EINVAL;
  4627. pr_err("%s: Invalid TDM interface %d\n",
  4628. __func__, ret);
  4629. return ret;
  4630. }
  4631. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4632. ret = msm_cdc_pinctrl_select_active_state(
  4633. pdata->mi2s_gpio_p[tdm_mode]);
  4634. if (ret)
  4635. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4636. __func__, ret);
  4637. }
  4638. /* Enable Mic bias for TDM Mics */
  4639. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4640. if (pdata->tdm_micb_supply) {
  4641. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  4642. pdata->tdm_micb_voltage,
  4643. pdata->tdm_micb_voltage);
  4644. if (ret) {
  4645. pr_err("%s: Setting voltage failed, err = %d\n",
  4646. __func__, ret);
  4647. return ret;
  4648. }
  4649. ret = regulator_set_load(pdata->tdm_micb_supply,
  4650. pdata->tdm_micb_current);
  4651. if (ret) {
  4652. pr_err("%s: Setting current failed, err = %d\n",
  4653. __func__, ret);
  4654. return ret;
  4655. }
  4656. ret = regulator_enable(pdata->tdm_micb_supply);
  4657. if (ret) {
  4658. pr_err("%s: regulator enable failed, err = %d\n",
  4659. __func__, ret);
  4660. return ret;
  4661. }
  4662. }
  4663. }
  4664. return ret;
  4665. }
  4666. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4667. {
  4668. int ret = 0;
  4669. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4670. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4671. struct snd_soc_card *card = rtd->card;
  4672. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4673. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4674. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4675. if (pdata->tdm_micb_supply) {
  4676. ret = regulator_disable(pdata->tdm_micb_supply);
  4677. if (ret)
  4678. pr_err("%s: regulator disable failed, err = %d\n",
  4679. __func__, ret);
  4680. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  4681. pdata->tdm_micb_voltage);
  4682. regulator_set_load(pdata->tdm_micb_supply, 0);
  4683. }
  4684. }
  4685. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4686. ret = msm_cdc_pinctrl_select_sleep_state(
  4687. pdata->mi2s_gpio_p[tdm_mode]);
  4688. if (ret)
  4689. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4690. __func__, ret);
  4691. }
  4692. }
  4693. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4694. .hw_params = qcs405_tdm_snd_hw_params,
  4695. .startup = qcs405_tdm_snd_startup,
  4696. .shutdown = qcs405_tdm_snd_shutdown
  4697. };
  4698. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4699. {
  4700. cpumask_t mask;
  4701. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4702. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4703. cpumask_clear(&mask);
  4704. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4705. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4706. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4707. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4708. pm_qos_add_request(&substream->latency_pm_qos_req,
  4709. PM_QOS_CPU_DMA_LATENCY,
  4710. MSM_LL_QOS_VALUE);
  4711. return 0;
  4712. }
  4713. static struct snd_soc_ops msm_fe_qos_ops = {
  4714. .prepare = msm_fe_qos_prepare,
  4715. };
  4716. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4717. {
  4718. int ret = 0;
  4719. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4720. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4721. int index = cpu_dai->id;
  4722. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4723. struct snd_soc_card *card = rtd->card;
  4724. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4725. dev_dbg(rtd->card->dev,
  4726. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4727. __func__, substream->name, substream->stream,
  4728. cpu_dai->name, cpu_dai->id);
  4729. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4730. ret = -EINVAL;
  4731. dev_err(rtd->card->dev,
  4732. "%s: CPU DAI id (%d) out of range\n",
  4733. __func__, cpu_dai->id);
  4734. goto err;
  4735. }
  4736. /*
  4737. * Mutex protection in case the same MI2S
  4738. * interface using for both TX and RX so
  4739. * that the same clock won't be enable twice.
  4740. */
  4741. mutex_lock(&mi2s_intf_conf[index].lock);
  4742. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4743. /* Check if msm needs to provide the clock to the interface */
  4744. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4745. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4746. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4747. }
  4748. ret = msm_mi2s_set_sclk(substream, true);
  4749. if (ret < 0) {
  4750. dev_err(rtd->card->dev,
  4751. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4752. __func__, ret);
  4753. goto clean_up;
  4754. }
  4755. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4756. if (ret < 0) {
  4757. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4758. __func__, index, ret);
  4759. goto clk_off;
  4760. }
  4761. if (pdata->mi2s_gpio_p[index])
  4762. msm_cdc_pinctrl_select_active_state(
  4763. pdata->mi2s_gpio_p[index]);
  4764. }
  4765. clk_off:
  4766. if (ret < 0)
  4767. msm_mi2s_set_sclk(substream, false);
  4768. clean_up:
  4769. if (ret < 0)
  4770. mi2s_intf_conf[index].ref_cnt--;
  4771. mutex_unlock(&mi2s_intf_conf[index].lock);
  4772. err:
  4773. return ret;
  4774. }
  4775. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4776. {
  4777. int ret;
  4778. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4779. int index = rtd->cpu_dai->id;
  4780. struct snd_soc_card *card = rtd->card;
  4781. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4782. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4783. substream->name, substream->stream);
  4784. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4785. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4786. return;
  4787. }
  4788. mutex_lock(&mi2s_intf_conf[index].lock);
  4789. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4790. if (pdata->mi2s_gpio_p[index])
  4791. msm_cdc_pinctrl_select_sleep_state(
  4792. pdata->mi2s_gpio_p[index]);
  4793. ret = msm_mi2s_set_sclk(substream, false);
  4794. if (ret < 0)
  4795. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4796. __func__, index, ret);
  4797. }
  4798. mutex_unlock(&mi2s_intf_conf[index].lock);
  4799. }
  4800. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  4801. {
  4802. int ret = 0;
  4803. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4804. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4805. int port_id = cpu_dai->id;
  4806. struct afe_clk_set clk_cfg;
  4807. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  4808. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  4809. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  4810. clk_cfg.enable = enable;
  4811. /* Set core clock (based on sample rate for RX, fixed for TX) */
  4812. switch (port_id) {
  4813. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4814. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  4815. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  4816. clk_cfg.clk_freq_in_hz =
  4817. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4818. break;
  4819. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4820. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  4821. clk_cfg.clk_freq_in_hz =
  4822. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  4823. break;
  4824. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  4825. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  4826. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_204_P8_MHZ;
  4827. break;
  4828. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  4829. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  4830. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_204_P8_MHZ;
  4831. break;
  4832. }
  4833. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4834. if (ret < 0) {
  4835. dev_err(rtd->card->dev,
  4836. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4837. __func__, port_id, ret);
  4838. goto err;
  4839. }
  4840. /* Set NPL clock for RX in addition */
  4841. switch (port_id) {
  4842. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  4843. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  4844. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4845. if (ret < 0) {
  4846. dev_err(rtd->card->dev,
  4847. "%s: afe NPL failed port 0x%x, err:%d\n",
  4848. __func__, port_id, ret);
  4849. goto err;
  4850. }
  4851. break;
  4852. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  4853. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  4854. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  4855. if (ret < 0) {
  4856. dev_err(rtd->card->dev,
  4857. "%s: afe NPL failed for port 0x%x, err:%d\n",
  4858. __func__, port_id, ret);
  4859. goto err;
  4860. }
  4861. break;
  4862. }
  4863. if (enable) {
  4864. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4865. clk_cfg.clk_freq_in_hz);
  4866. }
  4867. err:
  4868. return ret;
  4869. }
  4870. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  4871. {
  4872. int ret = 0;
  4873. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4874. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4875. int port_id = cpu_dai->id;
  4876. dev_dbg(rtd->card->dev,
  4877. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4878. __func__, substream->name, substream->stream,
  4879. cpu_dai->name, cpu_dai->id);
  4880. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4881. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  4882. ret = -EINVAL;
  4883. dev_err(rtd->card->dev,
  4884. "%s: CPU DAI id (%d) out of range\n",
  4885. __func__, cpu_dai->id);
  4886. goto err;
  4887. }
  4888. ret = msm_spdif_set_clk(substream, true);
  4889. if (ret < 0) {
  4890. dev_err(rtd->card->dev,
  4891. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  4892. __func__, port_id, ret);
  4893. }
  4894. err:
  4895. return ret;
  4896. }
  4897. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  4898. {
  4899. int ret;
  4900. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4901. int port_id = rtd->cpu_dai->id;
  4902. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4903. substream->name, substream->stream);
  4904. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  4905. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  4906. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  4907. return;
  4908. }
  4909. ret = msm_spdif_set_clk(substream, false);
  4910. if (ret < 0)
  4911. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  4912. __func__, port_id, ret);
  4913. }
  4914. static struct snd_soc_ops msm_mi2s_be_ops = {
  4915. .startup = msm_mi2s_snd_startup,
  4916. .shutdown = msm_mi2s_snd_shutdown,
  4917. };
  4918. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4919. .hw_params = msm_snd_cdc_dma_hw_params,
  4920. };
  4921. static struct snd_soc_ops msm_be_ops = {
  4922. .hw_params = msm_snd_hw_params,
  4923. };
  4924. static struct snd_soc_ops msm_wcn_ops = {
  4925. .hw_params = msm_wcn_hw_params,
  4926. };
  4927. static struct snd_soc_ops msm_spdif_be_ops = {
  4928. .startup = msm_spdif_snd_startup,
  4929. .shutdown = msm_spdif_snd_shutdown,
  4930. };
  4931. /* Digital audio interface glue - connects codec <---> CPU */
  4932. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4933. /* FrontEnd DAI Links */
  4934. {
  4935. .name = MSM_DAILINK_NAME(Media1),
  4936. .stream_name = "MultiMedia1",
  4937. .cpu_dai_name = "MultiMedia1",
  4938. .platform_name = "msm-pcm-dsp.0",
  4939. .dynamic = 1,
  4940. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4941. .dpcm_playback = 1,
  4942. .dpcm_capture = 1,
  4943. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4944. SND_SOC_DPCM_TRIGGER_POST},
  4945. .codec_dai_name = "snd-soc-dummy-dai",
  4946. .codec_name = "snd-soc-dummy",
  4947. .ignore_suspend = 1,
  4948. /* this dainlink has playback support */
  4949. .ignore_pmdown_time = 1,
  4950. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4951. },
  4952. {
  4953. .name = MSM_DAILINK_NAME(Media2),
  4954. .stream_name = "MultiMedia2",
  4955. .cpu_dai_name = "MultiMedia2",
  4956. .platform_name = "msm-pcm-dsp.0",
  4957. .dynamic = 1,
  4958. .dpcm_playback = 1,
  4959. .dpcm_capture = 1,
  4960. .codec_dai_name = "snd-soc-dummy-dai",
  4961. .codec_name = "snd-soc-dummy",
  4962. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4963. SND_SOC_DPCM_TRIGGER_POST},
  4964. .ignore_suspend = 1,
  4965. /* this dainlink has playback support */
  4966. .ignore_pmdown_time = 1,
  4967. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4968. },
  4969. {
  4970. .name = "VoiceMMode1",
  4971. .stream_name = "VoiceMMode1",
  4972. .cpu_dai_name = "VoiceMMode1",
  4973. .platform_name = "msm-pcm-voice",
  4974. .dynamic = 1,
  4975. .dpcm_playback = 1,
  4976. .dpcm_capture = 1,
  4977. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4978. SND_SOC_DPCM_TRIGGER_POST},
  4979. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4980. .ignore_suspend = 1,
  4981. .ignore_pmdown_time = 1,
  4982. .codec_dai_name = "snd-soc-dummy-dai",
  4983. .codec_name = "snd-soc-dummy",
  4984. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4985. },
  4986. {
  4987. .name = "MSM VoIP",
  4988. .stream_name = "VoIP",
  4989. .cpu_dai_name = "VoIP",
  4990. .platform_name = "msm-voip-dsp",
  4991. .dynamic = 1,
  4992. .dpcm_playback = 1,
  4993. .dpcm_capture = 1,
  4994. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4995. SND_SOC_DPCM_TRIGGER_POST},
  4996. .codec_dai_name = "snd-soc-dummy-dai",
  4997. .codec_name = "snd-soc-dummy",
  4998. .ignore_suspend = 1,
  4999. /* this dainlink has playback support */
  5000. .ignore_pmdown_time = 1,
  5001. .id = MSM_FRONTEND_DAI_VOIP,
  5002. },
  5003. {
  5004. .name = MSM_DAILINK_NAME(ULL),
  5005. .stream_name = "MultiMedia3",
  5006. .cpu_dai_name = "MultiMedia3",
  5007. .platform_name = "msm-pcm-dsp.2",
  5008. .dynamic = 1,
  5009. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5010. .dpcm_playback = 1,
  5011. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5012. SND_SOC_DPCM_TRIGGER_POST},
  5013. .codec_dai_name = "snd-soc-dummy-dai",
  5014. .codec_name = "snd-soc-dummy",
  5015. .ignore_suspend = 1,
  5016. /* this dainlink has playback support */
  5017. .ignore_pmdown_time = 1,
  5018. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5019. },
  5020. /* Hostless PCM purpose */
  5021. {
  5022. .name = "SLIMBUS_0 Hostless",
  5023. .stream_name = "SLIMBUS_0 Hostless",
  5024. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5025. .platform_name = "msm-pcm-hostless",
  5026. .dynamic = 1,
  5027. .dpcm_playback = 1,
  5028. .dpcm_capture = 1,
  5029. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5030. SND_SOC_DPCM_TRIGGER_POST},
  5031. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5032. .ignore_suspend = 1,
  5033. /* this dailink has playback support */
  5034. .ignore_pmdown_time = 1,
  5035. .codec_dai_name = "snd-soc-dummy-dai",
  5036. .codec_name = "snd-soc-dummy",
  5037. },
  5038. {
  5039. .name = "MSM AFE-PCM RX",
  5040. .stream_name = "AFE-PROXY RX",
  5041. .cpu_dai_name = "msm-dai-q6-dev.241",
  5042. .codec_name = "msm-stub-codec.1",
  5043. .codec_dai_name = "msm-stub-rx",
  5044. .platform_name = "msm-pcm-afe",
  5045. .dpcm_playback = 1,
  5046. .ignore_suspend = 1,
  5047. /* this dainlink has playback support */
  5048. .ignore_pmdown_time = 1,
  5049. },
  5050. {
  5051. .name = "MSM AFE-PCM TX",
  5052. .stream_name = "AFE-PROXY TX",
  5053. .cpu_dai_name = "msm-dai-q6-dev.240",
  5054. .codec_name = "msm-stub-codec.1",
  5055. .codec_dai_name = "msm-stub-tx",
  5056. .platform_name = "msm-pcm-afe",
  5057. .dpcm_capture = 1,
  5058. .ignore_suspend = 1,
  5059. },
  5060. {
  5061. .name = MSM_DAILINK_NAME(Compress1),
  5062. .stream_name = "Compress1",
  5063. .cpu_dai_name = "MultiMedia4",
  5064. .platform_name = "msm-compress-dsp",
  5065. .dynamic = 1,
  5066. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5067. .dpcm_playback = 1,
  5068. .dpcm_capture = 1,
  5069. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5070. SND_SOC_DPCM_TRIGGER_POST},
  5071. .codec_dai_name = "snd-soc-dummy-dai",
  5072. .codec_name = "snd-soc-dummy",
  5073. .ignore_suspend = 1,
  5074. .ignore_pmdown_time = 1,
  5075. /* this dainlink has playback support */
  5076. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5077. },
  5078. {
  5079. .name = "AUXPCM Hostless",
  5080. .stream_name = "AUXPCM Hostless",
  5081. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5082. .platform_name = "msm-pcm-hostless",
  5083. .dynamic = 1,
  5084. .dpcm_playback = 1,
  5085. .dpcm_capture = 1,
  5086. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5087. SND_SOC_DPCM_TRIGGER_POST},
  5088. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5089. .ignore_suspend = 1,
  5090. /* this dainlink has playback support */
  5091. .ignore_pmdown_time = 1,
  5092. .codec_dai_name = "snd-soc-dummy-dai",
  5093. .codec_name = "snd-soc-dummy",
  5094. },
  5095. {
  5096. .name = "SLIMBUS_1 Hostless",
  5097. .stream_name = "SLIMBUS_1 Hostless",
  5098. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5099. .platform_name = "msm-pcm-hostless",
  5100. .dynamic = 1,
  5101. .dpcm_playback = 1,
  5102. .dpcm_capture = 1,
  5103. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5104. SND_SOC_DPCM_TRIGGER_POST},
  5105. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5106. .ignore_suspend = 1,
  5107. /* this dailink has playback support */
  5108. .ignore_pmdown_time = 1,
  5109. .codec_dai_name = "snd-soc-dummy-dai",
  5110. .codec_name = "snd-soc-dummy",
  5111. },
  5112. {
  5113. .name = "SLIMBUS_3 Hostless",
  5114. .stream_name = "SLIMBUS_3 Hostless",
  5115. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5116. .platform_name = "msm-pcm-hostless",
  5117. .dynamic = 1,
  5118. .dpcm_playback = 1,
  5119. .dpcm_capture = 1,
  5120. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5121. SND_SOC_DPCM_TRIGGER_POST},
  5122. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5123. .ignore_suspend = 1,
  5124. /* this dailink has playback support */
  5125. .ignore_pmdown_time = 1,
  5126. .codec_dai_name = "snd-soc-dummy-dai",
  5127. .codec_name = "snd-soc-dummy",
  5128. },
  5129. {
  5130. .name = "SLIMBUS_4 Hostless",
  5131. .stream_name = "SLIMBUS_4 Hostless",
  5132. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5133. .platform_name = "msm-pcm-hostless",
  5134. .dynamic = 1,
  5135. .dpcm_playback = 1,
  5136. .dpcm_capture = 1,
  5137. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5138. SND_SOC_DPCM_TRIGGER_POST},
  5139. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5140. .ignore_suspend = 1,
  5141. /* this dailink has playback support */
  5142. .ignore_pmdown_time = 1,
  5143. .codec_dai_name = "snd-soc-dummy-dai",
  5144. .codec_name = "snd-soc-dummy",
  5145. },
  5146. {
  5147. .name = MSM_DAILINK_NAME(LowLatency),
  5148. .stream_name = "MultiMedia5",
  5149. .cpu_dai_name = "MultiMedia5",
  5150. .platform_name = "msm-pcm-dsp.1",
  5151. .dynamic = 1,
  5152. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5153. .dpcm_playback = 1,
  5154. .dpcm_capture = 1,
  5155. .codec_dai_name = "snd-soc-dummy-dai",
  5156. .codec_name = "snd-soc-dummy",
  5157. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5158. SND_SOC_DPCM_TRIGGER_POST},
  5159. .ignore_suspend = 1,
  5160. /* this dainlink has playback support */
  5161. .ignore_pmdown_time = 1,
  5162. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5163. .ops = &msm_fe_qos_ops,
  5164. },
  5165. {
  5166. .name = "Listen 1 Audio Service",
  5167. .stream_name = "Listen 1 Audio Service",
  5168. .cpu_dai_name = "LSM1",
  5169. .platform_name = "msm-lsm-client",
  5170. .dynamic = 1,
  5171. .dpcm_capture = 1,
  5172. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5173. SND_SOC_DPCM_TRIGGER_POST },
  5174. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5175. .ignore_suspend = 1,
  5176. .codec_dai_name = "snd-soc-dummy-dai",
  5177. .codec_name = "snd-soc-dummy",
  5178. .id = MSM_FRONTEND_DAI_LSM1,
  5179. },
  5180. /* Multiple Tunnel instances */
  5181. {
  5182. .name = MSM_DAILINK_NAME(Compress2),
  5183. .stream_name = "Compress2",
  5184. .cpu_dai_name = "MultiMedia7",
  5185. .platform_name = "msm-compress-dsp",
  5186. .dynamic = 1,
  5187. .dpcm_playback = 1,
  5188. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5189. SND_SOC_DPCM_TRIGGER_POST},
  5190. .codec_dai_name = "snd-soc-dummy-dai",
  5191. .codec_name = "snd-soc-dummy",
  5192. .ignore_suspend = 1,
  5193. .ignore_pmdown_time = 1,
  5194. /* this dainlink has playback support */
  5195. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5196. },
  5197. {
  5198. .name = MSM_DAILINK_NAME(MultiMedia10),
  5199. .stream_name = "MultiMedia10",
  5200. .cpu_dai_name = "MultiMedia10",
  5201. .platform_name = "msm-pcm-dsp.1",
  5202. .dynamic = 1,
  5203. .dpcm_playback = 1,
  5204. .dpcm_capture = 1,
  5205. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5206. SND_SOC_DPCM_TRIGGER_POST},
  5207. .codec_dai_name = "snd-soc-dummy-dai",
  5208. .codec_name = "snd-soc-dummy",
  5209. .ignore_suspend = 1,
  5210. .ignore_pmdown_time = 1,
  5211. /* this dainlink has playback support */
  5212. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5213. },
  5214. {
  5215. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5216. .stream_name = "MM_NOIRQ",
  5217. .cpu_dai_name = "MultiMedia8",
  5218. .platform_name = "msm-pcm-dsp-noirq",
  5219. .dynamic = 1,
  5220. .dpcm_playback = 1,
  5221. .dpcm_capture = 1,
  5222. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5223. SND_SOC_DPCM_TRIGGER_POST},
  5224. .codec_dai_name = "snd-soc-dummy-dai",
  5225. .codec_name = "snd-soc-dummy",
  5226. .ignore_suspend = 1,
  5227. .ignore_pmdown_time = 1,
  5228. /* this dainlink has playback support */
  5229. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5230. .ops = &msm_fe_qos_ops,
  5231. },
  5232. /* HDMI Hostless */
  5233. {
  5234. .name = "HDMI_RX_HOSTLESS",
  5235. .stream_name = "HDMI_RX_HOSTLESS",
  5236. .cpu_dai_name = "HDMI_HOSTLESS",
  5237. .platform_name = "msm-pcm-hostless",
  5238. .dynamic = 1,
  5239. .dpcm_playback = 1,
  5240. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5241. SND_SOC_DPCM_TRIGGER_POST},
  5242. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5243. .ignore_suspend = 1,
  5244. .ignore_pmdown_time = 1,
  5245. .codec_dai_name = "snd-soc-dummy-dai",
  5246. .codec_name = "snd-soc-dummy",
  5247. },
  5248. {
  5249. .name = "VoiceMMode2",
  5250. .stream_name = "VoiceMMode2",
  5251. .cpu_dai_name = "VoiceMMode2",
  5252. .platform_name = "msm-pcm-voice",
  5253. .dynamic = 1,
  5254. .dpcm_playback = 1,
  5255. .dpcm_capture = 1,
  5256. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5257. SND_SOC_DPCM_TRIGGER_POST},
  5258. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5259. .ignore_suspend = 1,
  5260. .ignore_pmdown_time = 1,
  5261. .codec_dai_name = "snd-soc-dummy-dai",
  5262. .codec_name = "snd-soc-dummy",
  5263. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5264. },
  5265. /* LSM FE */
  5266. {
  5267. .name = "Listen 2 Audio Service",
  5268. .stream_name = "Listen 2 Audio Service",
  5269. .cpu_dai_name = "LSM2",
  5270. .platform_name = "msm-lsm-client",
  5271. .dynamic = 1,
  5272. .dpcm_capture = 1,
  5273. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5274. SND_SOC_DPCM_TRIGGER_POST },
  5275. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5276. .ignore_suspend = 1,
  5277. .codec_dai_name = "snd-soc-dummy-dai",
  5278. .codec_name = "snd-soc-dummy",
  5279. .id = MSM_FRONTEND_DAI_LSM2,
  5280. },
  5281. {
  5282. .name = "Listen 3 Audio Service",
  5283. .stream_name = "Listen 3 Audio Service",
  5284. .cpu_dai_name = "LSM3",
  5285. .platform_name = "msm-lsm-client",
  5286. .dynamic = 1,
  5287. .dpcm_capture = 1,
  5288. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5289. SND_SOC_DPCM_TRIGGER_POST },
  5290. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5291. .ignore_suspend = 1,
  5292. .codec_dai_name = "snd-soc-dummy-dai",
  5293. .codec_name = "snd-soc-dummy",
  5294. .id = MSM_FRONTEND_DAI_LSM3,
  5295. },
  5296. {
  5297. .name = "Listen 4 Audio Service",
  5298. .stream_name = "Listen 4 Audio Service",
  5299. .cpu_dai_name = "LSM4",
  5300. .platform_name = "msm-lsm-client",
  5301. .dynamic = 1,
  5302. .dpcm_capture = 1,
  5303. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5304. SND_SOC_DPCM_TRIGGER_POST },
  5305. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5306. .ignore_suspend = 1,
  5307. .codec_dai_name = "snd-soc-dummy-dai",
  5308. .codec_name = "snd-soc-dummy",
  5309. .id = MSM_FRONTEND_DAI_LSM4,
  5310. },
  5311. {
  5312. .name = "Listen 5 Audio Service",
  5313. .stream_name = "Listen 5 Audio Service",
  5314. .cpu_dai_name = "LSM5",
  5315. .platform_name = "msm-lsm-client",
  5316. .dynamic = 1,
  5317. .dpcm_capture = 1,
  5318. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5319. SND_SOC_DPCM_TRIGGER_POST },
  5320. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5321. .ignore_suspend = 1,
  5322. .codec_dai_name = "snd-soc-dummy-dai",
  5323. .codec_name = "snd-soc-dummy",
  5324. .id = MSM_FRONTEND_DAI_LSM5,
  5325. },
  5326. {
  5327. .name = "Listen 6 Audio Service",
  5328. .stream_name = "Listen 6 Audio Service",
  5329. .cpu_dai_name = "LSM6",
  5330. .platform_name = "msm-lsm-client",
  5331. .dynamic = 1,
  5332. .dpcm_capture = 1,
  5333. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5334. SND_SOC_DPCM_TRIGGER_POST },
  5335. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5336. .ignore_suspend = 1,
  5337. .codec_dai_name = "snd-soc-dummy-dai",
  5338. .codec_name = "snd-soc-dummy",
  5339. .id = MSM_FRONTEND_DAI_LSM6,
  5340. },
  5341. {
  5342. .name = "Listen 7 Audio Service",
  5343. .stream_name = "Listen 7 Audio Service",
  5344. .cpu_dai_name = "LSM7",
  5345. .platform_name = "msm-lsm-client",
  5346. .dynamic = 1,
  5347. .dpcm_capture = 1,
  5348. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5349. SND_SOC_DPCM_TRIGGER_POST },
  5350. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5351. .ignore_suspend = 1,
  5352. .codec_dai_name = "snd-soc-dummy-dai",
  5353. .codec_name = "snd-soc-dummy",
  5354. .id = MSM_FRONTEND_DAI_LSM7,
  5355. },
  5356. {
  5357. .name = "Listen 8 Audio Service",
  5358. .stream_name = "Listen 8 Audio Service",
  5359. .cpu_dai_name = "LSM8",
  5360. .platform_name = "msm-lsm-client",
  5361. .dynamic = 1,
  5362. .dpcm_capture = 1,
  5363. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5364. SND_SOC_DPCM_TRIGGER_POST },
  5365. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5366. .ignore_suspend = 1,
  5367. .codec_dai_name = "snd-soc-dummy-dai",
  5368. .codec_name = "snd-soc-dummy",
  5369. .id = MSM_FRONTEND_DAI_LSM8,
  5370. },
  5371. {
  5372. .name = MSM_DAILINK_NAME(Media9),
  5373. .stream_name = "MultiMedia9",
  5374. .cpu_dai_name = "MultiMedia9",
  5375. .platform_name = "msm-pcm-dsp.0",
  5376. .dynamic = 1,
  5377. .dpcm_playback = 1,
  5378. .dpcm_capture = 1,
  5379. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5380. SND_SOC_DPCM_TRIGGER_POST},
  5381. .codec_dai_name = "snd-soc-dummy-dai",
  5382. .codec_name = "snd-soc-dummy",
  5383. .ignore_suspend = 1,
  5384. /* this dainlink has playback support */
  5385. .ignore_pmdown_time = 1,
  5386. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5387. },
  5388. {
  5389. .name = MSM_DAILINK_NAME(Compress4),
  5390. .stream_name = "Compress4",
  5391. .cpu_dai_name = "MultiMedia11",
  5392. .platform_name = "msm-compress-dsp",
  5393. .dynamic = 1,
  5394. .dpcm_playback = 1,
  5395. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5396. SND_SOC_DPCM_TRIGGER_POST},
  5397. .codec_dai_name = "snd-soc-dummy-dai",
  5398. .codec_name = "snd-soc-dummy",
  5399. .ignore_suspend = 1,
  5400. .ignore_pmdown_time = 1,
  5401. /* this dainlink has playback support */
  5402. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5403. },
  5404. {
  5405. .name = MSM_DAILINK_NAME(Compress5),
  5406. .stream_name = "Compress5",
  5407. .cpu_dai_name = "MultiMedia12",
  5408. .platform_name = "msm-compress-dsp",
  5409. .dynamic = 1,
  5410. .dpcm_playback = 1,
  5411. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5412. SND_SOC_DPCM_TRIGGER_POST},
  5413. .codec_dai_name = "snd-soc-dummy-dai",
  5414. .codec_name = "snd-soc-dummy",
  5415. .ignore_suspend = 1,
  5416. .ignore_pmdown_time = 1,
  5417. /* this dainlink has playback support */
  5418. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5419. },
  5420. {
  5421. .name = MSM_DAILINK_NAME(Compress6),
  5422. .stream_name = "Compress6",
  5423. .cpu_dai_name = "MultiMedia13",
  5424. .platform_name = "msm-compress-dsp",
  5425. .dynamic = 1,
  5426. .dpcm_playback = 1,
  5427. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5428. SND_SOC_DPCM_TRIGGER_POST},
  5429. .codec_dai_name = "snd-soc-dummy-dai",
  5430. .codec_name = "snd-soc-dummy",
  5431. .ignore_suspend = 1,
  5432. .ignore_pmdown_time = 1,
  5433. /* this dainlink has playback support */
  5434. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5435. },
  5436. {
  5437. .name = MSM_DAILINK_NAME(Compress7),
  5438. .stream_name = "Compress7",
  5439. .cpu_dai_name = "MultiMedia14",
  5440. .platform_name = "msm-compress-dsp",
  5441. .dynamic = 1,
  5442. .dpcm_playback = 1,
  5443. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5444. SND_SOC_DPCM_TRIGGER_POST},
  5445. .codec_dai_name = "snd-soc-dummy-dai",
  5446. .codec_name = "snd-soc-dummy",
  5447. .ignore_suspend = 1,
  5448. .ignore_pmdown_time = 1,
  5449. /* this dainlink has playback support */
  5450. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5451. },
  5452. {
  5453. .name = MSM_DAILINK_NAME(Compress8),
  5454. .stream_name = "Compress8",
  5455. .cpu_dai_name = "MultiMedia15",
  5456. .platform_name = "msm-compress-dsp",
  5457. .dynamic = 1,
  5458. .dpcm_playback = 1,
  5459. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5460. SND_SOC_DPCM_TRIGGER_POST},
  5461. .codec_dai_name = "snd-soc-dummy-dai",
  5462. .codec_name = "snd-soc-dummy",
  5463. .ignore_suspend = 1,
  5464. .ignore_pmdown_time = 1,
  5465. /* this dainlink has playback support */
  5466. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5467. },
  5468. {
  5469. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5470. .stream_name = "MM_NOIRQ_2",
  5471. .cpu_dai_name = "MultiMedia16",
  5472. .platform_name = "msm-pcm-dsp-noirq",
  5473. .dynamic = 1,
  5474. .dpcm_playback = 1,
  5475. .dpcm_capture = 1,
  5476. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5477. SND_SOC_DPCM_TRIGGER_POST},
  5478. .codec_dai_name = "snd-soc-dummy-dai",
  5479. .codec_name = "snd-soc-dummy",
  5480. .ignore_suspend = 1,
  5481. .ignore_pmdown_time = 1,
  5482. /* this dainlink has playback support */
  5483. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5484. },
  5485. {
  5486. .name = "SLIMBUS_8 Hostless",
  5487. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5488. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5489. .platform_name = "msm-pcm-hostless",
  5490. .dynamic = 1,
  5491. .dpcm_capture = 1,
  5492. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5493. SND_SOC_DPCM_TRIGGER_POST},
  5494. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5495. .ignore_suspend = 1,
  5496. .codec_dai_name = "snd-soc-dummy-dai",
  5497. .codec_name = "snd-soc-dummy",
  5498. },
  5499. /* Hostless PCM purpose */
  5500. {
  5501. .name = "CDC_DMA Hostless",
  5502. .stream_name = "CDC_DMA Hostless",
  5503. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5504. .platform_name = "msm-pcm-hostless",
  5505. .dynamic = 1,
  5506. .dpcm_playback = 1,
  5507. .dpcm_capture = 1,
  5508. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5509. SND_SOC_DPCM_TRIGGER_POST},
  5510. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5511. .ignore_suspend = 1,
  5512. /* this dailink has playback support */
  5513. .ignore_pmdown_time = 1,
  5514. .codec_dai_name = "snd-soc-dummy-dai",
  5515. .codec_name = "snd-soc-dummy",
  5516. },
  5517. };
  5518. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5519. {
  5520. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5521. .stream_name = "WSA CDC DMA0 Capture",
  5522. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5523. .platform_name = "msm-pcm-hostless",
  5524. .codec_name = "bolero_codec",
  5525. .codec_dai_name = "wsa_macro_vifeedback",
  5526. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5527. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5528. .ignore_suspend = 1,
  5529. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5530. .ops = &msm_cdc_dma_be_ops,
  5531. },
  5532. };
  5533. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5534. {
  5535. .name = MSM_DAILINK_NAME(ASM Loopback),
  5536. .stream_name = "MultiMedia6",
  5537. .cpu_dai_name = "MultiMedia6",
  5538. .platform_name = "msm-pcm-loopback",
  5539. .dynamic = 1,
  5540. .dpcm_playback = 1,
  5541. .dpcm_capture = 1,
  5542. .codec_dai_name = "snd-soc-dummy-dai",
  5543. .codec_name = "snd-soc-dummy",
  5544. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5545. SND_SOC_DPCM_TRIGGER_POST},
  5546. .ignore_suspend = 1,
  5547. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5548. .ignore_pmdown_time = 1,
  5549. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5550. },
  5551. {
  5552. .name = "USB Audio Hostless",
  5553. .stream_name = "USB Audio Hostless",
  5554. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5555. .platform_name = "msm-pcm-hostless",
  5556. .dynamic = 1,
  5557. .dpcm_playback = 1,
  5558. .dpcm_capture = 1,
  5559. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5560. SND_SOC_DPCM_TRIGGER_POST},
  5561. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5562. .ignore_suspend = 1,
  5563. .ignore_pmdown_time = 1,
  5564. .codec_dai_name = "snd-soc-dummy-dai",
  5565. .codec_name = "snd-soc-dummy",
  5566. },
  5567. {
  5568. .name = "SLIMBUS_7 Hostless",
  5569. .stream_name = "SLIMBUS_7 Hostless",
  5570. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5571. .platform_name = "msm-pcm-hostless",
  5572. .dynamic = 1,
  5573. .dpcm_capture = 1,
  5574. .dpcm_playback = 1,
  5575. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5576. SND_SOC_DPCM_TRIGGER_POST},
  5577. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5578. .ignore_suspend = 1,
  5579. .ignore_pmdown_time = 1,
  5580. .codec_dai_name = "snd-soc-dummy-dai",
  5581. .codec_name = "snd-soc-dummy",
  5582. },
  5583. {
  5584. .name = MSM_DAILINK_NAME(Compr Capture),
  5585. .stream_name = "Compr Capture",
  5586. .cpu_dai_name = "MultiMedia18",
  5587. .platform_name = "msm-compress-dsp",
  5588. .dynamic = 1,
  5589. .dpcm_capture = 1,
  5590. .codec_dai_name = "snd-soc-dummy-dai",
  5591. .codec_name = "snd-soc-dummy",
  5592. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5593. SND_SOC_DPCM_TRIGGER_POST},
  5594. .ignore_pmdown_time = 1,
  5595. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5596. },
  5597. };
  5598. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5599. /* Backend AFE DAI Links */
  5600. {
  5601. .name = LPASS_BE_AFE_PCM_RX,
  5602. .stream_name = "AFE Playback",
  5603. .cpu_dai_name = "msm-dai-q6-dev.224",
  5604. .platform_name = "msm-pcm-routing",
  5605. .codec_name = "msm-stub-codec.1",
  5606. .codec_dai_name = "msm-stub-rx",
  5607. .no_pcm = 1,
  5608. .dpcm_playback = 1,
  5609. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5610. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5611. /* this dainlink has playback support */
  5612. .ignore_pmdown_time = 1,
  5613. .ignore_suspend = 1,
  5614. },
  5615. {
  5616. .name = LPASS_BE_AFE_PCM_TX,
  5617. .stream_name = "AFE Capture",
  5618. .cpu_dai_name = "msm-dai-q6-dev.225",
  5619. .platform_name = "msm-pcm-routing",
  5620. .codec_name = "msm-stub-codec.1",
  5621. .codec_dai_name = "msm-stub-tx",
  5622. .no_pcm = 1,
  5623. .dpcm_capture = 1,
  5624. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5625. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5626. .ignore_suspend = 1,
  5627. },
  5628. /* Incall Record Uplink BACK END DAI Link */
  5629. {
  5630. .name = LPASS_BE_INCALL_RECORD_TX,
  5631. .stream_name = "Voice Uplink Capture",
  5632. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5633. .platform_name = "msm-pcm-routing",
  5634. .codec_name = "msm-stub-codec.1",
  5635. .codec_dai_name = "msm-stub-tx",
  5636. .no_pcm = 1,
  5637. .dpcm_capture = 1,
  5638. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5639. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5640. .ignore_suspend = 1,
  5641. },
  5642. /* Incall Record Downlink BACK END DAI Link */
  5643. {
  5644. .name = LPASS_BE_INCALL_RECORD_RX,
  5645. .stream_name = "Voice Downlink Capture",
  5646. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5647. .platform_name = "msm-pcm-routing",
  5648. .codec_name = "msm-stub-codec.1",
  5649. .codec_dai_name = "msm-stub-tx",
  5650. .no_pcm = 1,
  5651. .dpcm_capture = 1,
  5652. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5653. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5654. .ignore_suspend = 1,
  5655. },
  5656. /* Incall Music BACK END DAI Link */
  5657. {
  5658. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5659. .stream_name = "Voice Farend Playback",
  5660. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5661. .platform_name = "msm-pcm-routing",
  5662. .codec_name = "msm-stub-codec.1",
  5663. .codec_dai_name = "msm-stub-rx",
  5664. .no_pcm = 1,
  5665. .dpcm_playback = 1,
  5666. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5667. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5668. .ignore_suspend = 1,
  5669. .ignore_pmdown_time = 1,
  5670. },
  5671. /* Incall Music 2 BACK END DAI Link */
  5672. {
  5673. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5674. .stream_name = "Voice2 Farend Playback",
  5675. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5676. .platform_name = "msm-pcm-routing",
  5677. .codec_name = "msm-stub-codec.1",
  5678. .codec_dai_name = "msm-stub-rx",
  5679. .no_pcm = 1,
  5680. .dpcm_playback = 1,
  5681. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5682. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5683. .ignore_suspend = 1,
  5684. .ignore_pmdown_time = 1,
  5685. },
  5686. {
  5687. .name = LPASS_BE_USB_AUDIO_RX,
  5688. .stream_name = "USB Audio Playback",
  5689. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5690. .platform_name = "msm-pcm-routing",
  5691. .codec_name = "msm-stub-codec.1",
  5692. .codec_dai_name = "msm-stub-rx",
  5693. .no_pcm = 1,
  5694. .dpcm_playback = 1,
  5695. .id = MSM_BACKEND_DAI_USB_RX,
  5696. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5697. .ignore_pmdown_time = 1,
  5698. .ignore_suspend = 1,
  5699. },
  5700. {
  5701. .name = LPASS_BE_USB_AUDIO_TX,
  5702. .stream_name = "USB Audio Capture",
  5703. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5704. .platform_name = "msm-pcm-routing",
  5705. .codec_name = "msm-stub-codec.1",
  5706. .codec_dai_name = "msm-stub-tx",
  5707. .no_pcm = 1,
  5708. .dpcm_capture = 1,
  5709. .id = MSM_BACKEND_DAI_USB_TX,
  5710. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5711. .ignore_suspend = 1,
  5712. },
  5713. {
  5714. .name = LPASS_BE_PRI_TDM_RX_0,
  5715. .stream_name = "Primary TDM0 Playback",
  5716. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5717. .platform_name = "msm-pcm-routing",
  5718. .codec_name = "msm-stub-codec.1",
  5719. .codec_dai_name = "msm-stub-rx",
  5720. .no_pcm = 1,
  5721. .dpcm_playback = 1,
  5722. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5723. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5724. .ops = &qcs405_tdm_be_ops,
  5725. .ignore_suspend = 1,
  5726. .ignore_pmdown_time = 1,
  5727. },
  5728. {
  5729. .name = LPASS_BE_PRI_TDM_TX_0,
  5730. .stream_name = "Primary TDM0 Capture",
  5731. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5732. .platform_name = "msm-pcm-routing",
  5733. .codec_name = "msm-stub-codec.1",
  5734. .codec_dai_name = "msm-stub-tx",
  5735. .no_pcm = 1,
  5736. .dpcm_capture = 1,
  5737. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5738. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5739. .ops = &qcs405_tdm_be_ops,
  5740. .ignore_suspend = 1,
  5741. },
  5742. {
  5743. .name = LPASS_BE_SEC_TDM_RX_0,
  5744. .stream_name = "Secondary TDM0 Playback",
  5745. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5746. .platform_name = "msm-pcm-routing",
  5747. .codec_name = "msm-stub-codec.1",
  5748. .codec_dai_name = "msm-stub-rx",
  5749. .no_pcm = 1,
  5750. .dpcm_playback = 1,
  5751. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5752. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5753. .ops = &qcs405_tdm_be_ops,
  5754. .ignore_suspend = 1,
  5755. .ignore_pmdown_time = 1,
  5756. },
  5757. {
  5758. .name = LPASS_BE_SEC_TDM_TX_0,
  5759. .stream_name = "Secondary TDM0 Capture",
  5760. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5761. .platform_name = "msm-pcm-routing",
  5762. .codec_name = "msm-stub-codec.1",
  5763. .codec_dai_name = "msm-stub-tx",
  5764. .no_pcm = 1,
  5765. .dpcm_capture = 1,
  5766. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5767. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5768. .ops = &qcs405_tdm_be_ops,
  5769. .ignore_suspend = 1,
  5770. },
  5771. {
  5772. .name = LPASS_BE_TERT_TDM_RX_0,
  5773. .stream_name = "Tertiary TDM0 Playback",
  5774. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5775. .platform_name = "msm-pcm-routing",
  5776. .codec_name = "msm-stub-codec.1",
  5777. .codec_dai_name = "msm-stub-rx",
  5778. .no_pcm = 1,
  5779. .dpcm_playback = 1,
  5780. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5781. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5782. .ops = &qcs405_tdm_be_ops,
  5783. .ignore_suspend = 1,
  5784. .ignore_pmdown_time = 1,
  5785. },
  5786. {
  5787. .name = LPASS_BE_TERT_TDM_TX_0,
  5788. .stream_name = "Tertiary TDM0 Capture",
  5789. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5790. .platform_name = "msm-pcm-routing",
  5791. .codec_name = "msm-stub-codec.1",
  5792. .codec_dai_name = "msm-stub-tx",
  5793. .no_pcm = 1,
  5794. .dpcm_capture = 1,
  5795. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5796. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5797. .ops = &qcs405_tdm_be_ops,
  5798. .ignore_suspend = 1,
  5799. },
  5800. {
  5801. .name = LPASS_BE_QUAT_TDM_RX_0,
  5802. .stream_name = "Quaternary TDM0 Playback",
  5803. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5804. .platform_name = "msm-pcm-routing",
  5805. .codec_name = "msm-stub-codec.1",
  5806. .codec_dai_name = "msm-stub-rx",
  5807. .no_pcm = 1,
  5808. .dpcm_playback = 1,
  5809. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5810. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5811. .ops = &qcs405_tdm_be_ops,
  5812. .ignore_suspend = 1,
  5813. .ignore_pmdown_time = 1,
  5814. },
  5815. {
  5816. .name = LPASS_BE_QUAT_TDM_TX_0,
  5817. .stream_name = "Quaternary TDM0 Capture",
  5818. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5819. .platform_name = "msm-pcm-routing",
  5820. .codec_name = "msm-stub-codec.1",
  5821. .codec_dai_name = "msm-stub-tx",
  5822. .no_pcm = 1,
  5823. .dpcm_capture = 1,
  5824. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5825. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5826. .ops = &qcs405_tdm_be_ops,
  5827. .ignore_suspend = 1,
  5828. },
  5829. {
  5830. .name = LPASS_BE_QUIN_TDM_RX_0,
  5831. .stream_name = "Quinary TDM0 Playback",
  5832. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5833. .platform_name = "msm-pcm-routing",
  5834. .codec_name = "msm-stub-codec.1",
  5835. .codec_dai_name = "msm-stub-rx",
  5836. .no_pcm = 1,
  5837. .dpcm_playback = 1,
  5838. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5839. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5840. .ops = &qcs405_tdm_be_ops,
  5841. .ignore_suspend = 1,
  5842. .ignore_pmdown_time = 1,
  5843. },
  5844. {
  5845. .name = LPASS_BE_QUIN_TDM_TX_0,
  5846. .stream_name = "Quinary TDM0 Capture",
  5847. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5848. .platform_name = "msm-pcm-routing",
  5849. .codec_name = "msm-stub-codec.1",
  5850. .codec_dai_name = "msm-stub-tx",
  5851. .no_pcm = 1,
  5852. .dpcm_capture = 1,
  5853. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5854. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5855. .ops = &qcs405_tdm_be_ops,
  5856. .ignore_suspend = 1,
  5857. },
  5858. };
  5859. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5860. {
  5861. .name = LPASS_BE_SLIMBUS_0_RX,
  5862. .stream_name = "Slimbus Playback",
  5863. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5864. .platform_name = "msm-pcm-routing",
  5865. .codec_name = "tasha_codec",
  5866. .codec_dai_name = "tasha_mix_rx1",
  5867. .no_pcm = 1,
  5868. .dpcm_playback = 1,
  5869. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5870. .init = &msm_audrx_init,
  5871. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5872. /* this dainlink has playback support */
  5873. .ignore_pmdown_time = 1,
  5874. .ignore_suspend = 1,
  5875. .ops = &msm_be_ops,
  5876. },
  5877. {
  5878. .name = LPASS_BE_SLIMBUS_0_TX,
  5879. .stream_name = "Slimbus Capture",
  5880. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5881. .platform_name = "msm-pcm-routing",
  5882. .codec_name = "tasha_codec",
  5883. .codec_dai_name = "tasha_tx1",
  5884. .no_pcm = 1,
  5885. .dpcm_capture = 1,
  5886. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5887. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5888. .ignore_suspend = 1,
  5889. .ops = &msm_be_ops,
  5890. },
  5891. {
  5892. .name = LPASS_BE_SLIMBUS_1_RX,
  5893. .stream_name = "Slimbus1 Playback",
  5894. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5895. .platform_name = "msm-pcm-routing",
  5896. .codec_name = "tasha_codec",
  5897. .codec_dai_name = "tasha_mix_rx1",
  5898. .no_pcm = 1,
  5899. .dpcm_playback = 1,
  5900. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5901. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5902. .ops = &msm_be_ops,
  5903. /* dai link has playback support */
  5904. .ignore_pmdown_time = 1,
  5905. .ignore_suspend = 1,
  5906. },
  5907. {
  5908. .name = LPASS_BE_SLIMBUS_1_TX,
  5909. .stream_name = "Slimbus1 Capture",
  5910. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5911. .platform_name = "msm-pcm-routing",
  5912. .codec_name = "tasha_codec",
  5913. .codec_dai_name = "tasha_tx3",
  5914. .no_pcm = 1,
  5915. .dpcm_capture = 1,
  5916. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5917. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5918. .ops = &msm_be_ops,
  5919. .ignore_suspend = 1,
  5920. },
  5921. {
  5922. .name = LPASS_BE_SLIMBUS_2_RX,
  5923. .stream_name = "Slimbus2 Playback",
  5924. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5925. .platform_name = "msm-pcm-routing",
  5926. .codec_name = "tasha_codec",
  5927. .codec_dai_name = "tasha_rx2",
  5928. .no_pcm = 1,
  5929. .dpcm_playback = 1,
  5930. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  5931. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5932. .ops = &msm_be_ops,
  5933. .ignore_pmdown_time = 1,
  5934. .ignore_suspend = 1,
  5935. },
  5936. {
  5937. .name = LPASS_BE_SLIMBUS_3_RX,
  5938. .stream_name = "Slimbus3 Playback",
  5939. .cpu_dai_name = "msm-dai-q6-dev.16390",
  5940. .platform_name = "msm-pcm-routing",
  5941. .codec_name = "tasha_codec",
  5942. .codec_dai_name = "tasha_mix_rx1",
  5943. .no_pcm = 1,
  5944. .dpcm_playback = 1,
  5945. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  5946. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5947. .ops = &msm_be_ops,
  5948. /* dai link has playback support */
  5949. .ignore_pmdown_time = 1,
  5950. .ignore_suspend = 1,
  5951. },
  5952. {
  5953. .name = LPASS_BE_SLIMBUS_3_TX,
  5954. .stream_name = "Slimbus3 Capture",
  5955. .cpu_dai_name = "msm-dai-q6-dev.16391",
  5956. .platform_name = "msm-pcm-routing",
  5957. .codec_name = "tasha_codec",
  5958. .codec_dai_name = "tasha_tx1",
  5959. .no_pcm = 1,
  5960. .dpcm_capture = 1,
  5961. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  5962. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5963. .ops = &msm_be_ops,
  5964. .ignore_suspend = 1,
  5965. },
  5966. {
  5967. .name = LPASS_BE_SLIMBUS_4_RX,
  5968. .stream_name = "Slimbus4 Playback",
  5969. .cpu_dai_name = "msm-dai-q6-dev.16392",
  5970. .platform_name = "msm-pcm-routing",
  5971. .codec_name = "tasha_codec",
  5972. .codec_dai_name = "tasha_mix_rx1",
  5973. .no_pcm = 1,
  5974. .dpcm_playback = 1,
  5975. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  5976. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5977. .ops = &msm_be_ops,
  5978. /* dai link has playback support */
  5979. .ignore_pmdown_time = 1,
  5980. .ignore_suspend = 1,
  5981. },
  5982. {
  5983. .name = LPASS_BE_SLIMBUS_5_RX,
  5984. .stream_name = "Slimbus5 Playback",
  5985. .cpu_dai_name = "msm-dai-q6-dev.16394",
  5986. .platform_name = "msm-pcm-routing",
  5987. .codec_name = "tasha_codec",
  5988. .codec_dai_name = "tasha_rx3",
  5989. .no_pcm = 1,
  5990. .dpcm_playback = 1,
  5991. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  5992. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5993. .ops = &msm_be_ops,
  5994. /* dai link has playback support */
  5995. .ignore_pmdown_time = 1,
  5996. .ignore_suspend = 1,
  5997. },
  5998. {
  5999. .name = LPASS_BE_SLIMBUS_6_RX,
  6000. .stream_name = "Slimbus6 Playback",
  6001. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6002. .platform_name = "msm-pcm-routing",
  6003. .codec_name = "tasha_codec",
  6004. .codec_dai_name = "tasha_rx4",
  6005. .no_pcm = 1,
  6006. .dpcm_playback = 1,
  6007. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6008. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6009. .ops = &msm_be_ops,
  6010. /* dai link has playback support */
  6011. .ignore_pmdown_time = 1,
  6012. .ignore_suspend = 1,
  6013. },
  6014. /* Slimbus VI Recording */
  6015. {
  6016. .name = LPASS_BE_SLIMBUS_TX_VI,
  6017. .stream_name = "Slimbus4 Capture",
  6018. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6019. .platform_name = "msm-pcm-routing",
  6020. .codec_name = "tasha_codec",
  6021. .codec_dai_name = "tasha_vifeedback",
  6022. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6023. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6024. .ops = &msm_be_ops,
  6025. .ignore_suspend = 1,
  6026. .no_pcm = 1,
  6027. .dpcm_capture = 1,
  6028. .ignore_pmdown_time = 1,
  6029. },
  6030. };
  6031. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6032. {
  6033. .name = LPASS_BE_SLIMBUS_7_RX,
  6034. .stream_name = "Slimbus7 Playback",
  6035. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6036. .platform_name = "msm-pcm-routing",
  6037. .codec_name = "btfmslim_slave",
  6038. /* BT codec driver determines capabilities based on
  6039. * dai name, bt codecdai name should always contains
  6040. * supported usecase information
  6041. */
  6042. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6043. .no_pcm = 1,
  6044. .dpcm_playback = 1,
  6045. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6046. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6047. .ops = &msm_wcn_ops,
  6048. /* dai link has playback support */
  6049. .ignore_pmdown_time = 1,
  6050. .ignore_suspend = 1,
  6051. },
  6052. {
  6053. .name = LPASS_BE_SLIMBUS_7_TX,
  6054. .stream_name = "Slimbus7 Capture",
  6055. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6056. .platform_name = "msm-pcm-routing",
  6057. .codec_name = "btfmslim_slave",
  6058. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6059. .no_pcm = 1,
  6060. .dpcm_capture = 1,
  6061. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6062. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6063. .ops = &msm_wcn_ops,
  6064. .ignore_suspend = 1,
  6065. },
  6066. {
  6067. .name = LPASS_BE_SLIMBUS_8_TX,
  6068. .stream_name = "Slimbus8 Capture",
  6069. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6070. .platform_name = "msm-pcm-routing",
  6071. .codec_name = "btfmslim_slave",
  6072. .codec_dai_name = "btfm_fm_slim_tx",
  6073. .no_pcm = 1,
  6074. .dpcm_capture = 1,
  6075. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6076. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6077. .init = &msm_wcn_init,
  6078. .ops = &msm_wcn_ops,
  6079. .ignore_suspend = 1,
  6080. },
  6081. };
  6082. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6083. {
  6084. .name = LPASS_BE_PRI_MI2S_RX,
  6085. .stream_name = "Primary MI2S Playback",
  6086. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6087. .platform_name = "msm-pcm-routing",
  6088. .codec_name = "msm-stub-codec.1",
  6089. .codec_dai_name = "msm-stub-rx",
  6090. .no_pcm = 1,
  6091. .dpcm_playback = 1,
  6092. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6093. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6094. .ops = &msm_mi2s_be_ops,
  6095. .ignore_suspend = 1,
  6096. .ignore_pmdown_time = 1,
  6097. },
  6098. {
  6099. .name = LPASS_BE_PRI_MI2S_TX,
  6100. .stream_name = "Primary MI2S Capture",
  6101. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6102. .platform_name = "msm-pcm-routing",
  6103. .codec_name = "msm-stub-codec.1",
  6104. .codec_dai_name = "msm-stub-tx",
  6105. .no_pcm = 1,
  6106. .dpcm_capture = 1,
  6107. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6108. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6109. .ops = &msm_mi2s_be_ops,
  6110. .ignore_suspend = 1,
  6111. },
  6112. {
  6113. .name = LPASS_BE_SEC_MI2S_RX,
  6114. .stream_name = "Secondary MI2S Playback",
  6115. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6116. .platform_name = "msm-pcm-routing",
  6117. .codec_name = "msm-stub-codec.1",
  6118. .codec_dai_name = "msm-stub-rx",
  6119. .no_pcm = 1,
  6120. .dpcm_playback = 1,
  6121. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6122. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6123. .ops = &msm_mi2s_be_ops,
  6124. .ignore_suspend = 1,
  6125. .ignore_pmdown_time = 1,
  6126. },
  6127. {
  6128. .name = LPASS_BE_SEC_MI2S_TX,
  6129. .stream_name = "Secondary MI2S Capture",
  6130. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6131. .platform_name = "msm-pcm-routing",
  6132. .codec_name = "msm-stub-codec.1",
  6133. .codec_dai_name = "msm-stub-tx",
  6134. .no_pcm = 1,
  6135. .dpcm_capture = 1,
  6136. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6137. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6138. .ops = &msm_mi2s_be_ops,
  6139. .ignore_suspend = 1,
  6140. },
  6141. {
  6142. .name = LPASS_BE_TERT_MI2S_RX,
  6143. .stream_name = "Tertiary MI2S Playback",
  6144. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6145. .platform_name = "msm-pcm-routing",
  6146. .codec_name = "msm-stub-codec.1",
  6147. .codec_dai_name = "msm-stub-rx",
  6148. .no_pcm = 1,
  6149. .dpcm_playback = 1,
  6150. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6151. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6152. .ops = &msm_mi2s_be_ops,
  6153. .ignore_suspend = 1,
  6154. .ignore_pmdown_time = 1,
  6155. },
  6156. {
  6157. .name = LPASS_BE_TERT_MI2S_TX,
  6158. .stream_name = "Tertiary MI2S Capture",
  6159. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6160. .platform_name = "msm-pcm-routing",
  6161. .codec_name = "msm-stub-codec.1",
  6162. .codec_dai_name = "msm-stub-tx",
  6163. .no_pcm = 1,
  6164. .dpcm_capture = 1,
  6165. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6166. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6167. .ops = &msm_mi2s_be_ops,
  6168. .ignore_suspend = 1,
  6169. },
  6170. {
  6171. .name = LPASS_BE_QUAT_MI2S_RX,
  6172. .stream_name = "Quaternary MI2S Playback",
  6173. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6174. .platform_name = "msm-pcm-routing",
  6175. .codec_name = "msm-stub-codec.1",
  6176. .codec_dai_name = "msm-stub-rx",
  6177. .no_pcm = 1,
  6178. .dpcm_playback = 1,
  6179. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6180. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6181. .ops = &msm_mi2s_be_ops,
  6182. .ignore_suspend = 1,
  6183. .ignore_pmdown_time = 1,
  6184. },
  6185. {
  6186. .name = LPASS_BE_QUAT_MI2S_TX,
  6187. .stream_name = "Quaternary MI2S Capture",
  6188. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6189. .platform_name = "msm-pcm-routing",
  6190. .codec_name = "msm-stub-codec.1",
  6191. .codec_dai_name = "msm-stub-tx",
  6192. .no_pcm = 1,
  6193. .dpcm_capture = 1,
  6194. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6195. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6196. .ops = &msm_mi2s_be_ops,
  6197. .ignore_suspend = 1,
  6198. },
  6199. {
  6200. .name = LPASS_BE_QUIN_MI2S_RX,
  6201. .stream_name = "Quinary MI2S Playback",
  6202. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6203. .platform_name = "msm-pcm-routing",
  6204. .codec_name = "msm-stub-codec.1",
  6205. .codec_dai_name = "msm-stub-rx",
  6206. .no_pcm = 1,
  6207. .dpcm_playback = 1,
  6208. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6209. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6210. .ops = &msm_mi2s_be_ops,
  6211. .ignore_suspend = 1,
  6212. .ignore_pmdown_time = 1,
  6213. },
  6214. {
  6215. .name = LPASS_BE_QUIN_MI2S_TX,
  6216. .stream_name = "Quinary MI2S Capture",
  6217. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6218. .platform_name = "msm-pcm-routing",
  6219. .codec_name = "msm-stub-codec.1",
  6220. .codec_dai_name = "msm-stub-tx",
  6221. .no_pcm = 1,
  6222. .dpcm_capture = 1,
  6223. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6224. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6225. .ops = &msm_mi2s_be_ops,
  6226. .ignore_suspend = 1,
  6227. },
  6228. };
  6229. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6230. /* Primary AUX PCM Backend DAI Links */
  6231. {
  6232. .name = LPASS_BE_AUXPCM_RX,
  6233. .stream_name = "AUX PCM Playback",
  6234. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6235. .platform_name = "msm-pcm-routing",
  6236. .codec_name = "msm-stub-codec.1",
  6237. .codec_dai_name = "msm-stub-rx",
  6238. .no_pcm = 1,
  6239. .dpcm_playback = 1,
  6240. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6241. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6242. .ignore_pmdown_time = 1,
  6243. .ignore_suspend = 1,
  6244. },
  6245. {
  6246. .name = LPASS_BE_AUXPCM_TX,
  6247. .stream_name = "AUX PCM Capture",
  6248. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6249. .platform_name = "msm-pcm-routing",
  6250. .codec_name = "msm-stub-codec.1",
  6251. .codec_dai_name = "msm-stub-tx",
  6252. .no_pcm = 1,
  6253. .dpcm_capture = 1,
  6254. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6255. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6256. .ignore_suspend = 1,
  6257. },
  6258. /* Secondary AUX PCM Backend DAI Links */
  6259. {
  6260. .name = LPASS_BE_SEC_AUXPCM_RX,
  6261. .stream_name = "Sec AUX PCM Playback",
  6262. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6263. .platform_name = "msm-pcm-routing",
  6264. .codec_name = "msm-stub-codec.1",
  6265. .codec_dai_name = "msm-stub-rx",
  6266. .no_pcm = 1,
  6267. .dpcm_playback = 1,
  6268. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6269. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6270. .ignore_pmdown_time = 1,
  6271. .ignore_suspend = 1,
  6272. },
  6273. {
  6274. .name = LPASS_BE_SEC_AUXPCM_TX,
  6275. .stream_name = "Sec AUX PCM Capture",
  6276. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6277. .platform_name = "msm-pcm-routing",
  6278. .codec_name = "msm-stub-codec.1",
  6279. .codec_dai_name = "msm-stub-tx",
  6280. .no_pcm = 1,
  6281. .dpcm_capture = 1,
  6282. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6283. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6284. .ignore_suspend = 1,
  6285. },
  6286. /* Tertiary AUX PCM Backend DAI Links */
  6287. {
  6288. .name = LPASS_BE_TERT_AUXPCM_RX,
  6289. .stream_name = "Tert AUX PCM Playback",
  6290. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6291. .platform_name = "msm-pcm-routing",
  6292. .codec_name = "msm-stub-codec.1",
  6293. .codec_dai_name = "msm-stub-rx",
  6294. .no_pcm = 1,
  6295. .dpcm_playback = 1,
  6296. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6297. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6298. .ignore_suspend = 1,
  6299. },
  6300. {
  6301. .name = LPASS_BE_TERT_AUXPCM_TX,
  6302. .stream_name = "Tert AUX PCM Capture",
  6303. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6304. .platform_name = "msm-pcm-routing",
  6305. .codec_name = "msm-stub-codec.1",
  6306. .codec_dai_name = "msm-stub-tx",
  6307. .no_pcm = 1,
  6308. .dpcm_capture = 1,
  6309. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6310. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6311. .ignore_suspend = 1,
  6312. },
  6313. /* Quaternary AUX PCM Backend DAI Links */
  6314. {
  6315. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6316. .stream_name = "Quat AUX PCM Playback",
  6317. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6318. .platform_name = "msm-pcm-routing",
  6319. .codec_name = "msm-stub-codec.1",
  6320. .codec_dai_name = "msm-stub-rx",
  6321. .no_pcm = 1,
  6322. .dpcm_playback = 1,
  6323. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6324. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6325. .ignore_pmdown_time = 1,
  6326. .ignore_suspend = 1,
  6327. },
  6328. {
  6329. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6330. .stream_name = "Quat AUX PCM Capture",
  6331. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6332. .platform_name = "msm-pcm-routing",
  6333. .codec_name = "msm-stub-codec.1",
  6334. .codec_dai_name = "msm-stub-tx",
  6335. .no_pcm = 1,
  6336. .dpcm_capture = 1,
  6337. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6338. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6339. .ignore_suspend = 1,
  6340. },
  6341. /* Quinary AUX PCM Backend DAI Links */
  6342. {
  6343. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6344. .stream_name = "Quin AUX PCM Playback",
  6345. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6346. .platform_name = "msm-pcm-routing",
  6347. .codec_name = "msm-stub-codec.1",
  6348. .codec_dai_name = "msm-stub-rx",
  6349. .no_pcm = 1,
  6350. .dpcm_playback = 1,
  6351. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6352. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6353. .ignore_pmdown_time = 1,
  6354. .ignore_suspend = 1,
  6355. },
  6356. {
  6357. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6358. .stream_name = "Quin AUX PCM Capture",
  6359. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6360. .platform_name = "msm-pcm-routing",
  6361. .codec_name = "msm-stub-codec.1",
  6362. .codec_dai_name = "msm-stub-tx",
  6363. .no_pcm = 1,
  6364. .dpcm_capture = 1,
  6365. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6366. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6367. .ignore_suspend = 1,
  6368. },
  6369. };
  6370. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6371. /* WSA CDC DMA Backend DAI Links */
  6372. {
  6373. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6374. .stream_name = "WSA CDC DMA0 Playback",
  6375. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6376. .platform_name = "msm-pcm-routing",
  6377. .codec_name = "bolero_codec",
  6378. .codec_dai_name = "wsa_macro_rx1",
  6379. .no_pcm = 1,
  6380. .dpcm_playback = 1,
  6381. .init = &msm_wsa_cdc_dma_init,
  6382. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6383. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6384. .ignore_pmdown_time = 1,
  6385. .ignore_suspend = 1,
  6386. .ops = &msm_cdc_dma_be_ops,
  6387. },
  6388. {
  6389. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6390. .stream_name = "WSA CDC DMA1 Playback",
  6391. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6392. .platform_name = "msm-pcm-routing",
  6393. .codec_name = "bolero_codec",
  6394. .codec_dai_name = "wsa_macro_rx_mix",
  6395. .no_pcm = 1,
  6396. .dpcm_playback = 1,
  6397. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6398. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6399. .ignore_pmdown_time = 1,
  6400. .ignore_suspend = 1,
  6401. .ops = &msm_cdc_dma_be_ops,
  6402. },
  6403. {
  6404. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6405. .stream_name = "WSA CDC DMA1 Capture",
  6406. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6407. .platform_name = "msm-pcm-routing",
  6408. .codec_name = "bolero_codec",
  6409. .codec_dai_name = "wsa_macro_echo",
  6410. .no_pcm = 1,
  6411. .dpcm_capture = 1,
  6412. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6413. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6414. .ignore_suspend = 1,
  6415. .ops = &msm_cdc_dma_be_ops,
  6416. },
  6417. };
  6418. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6419. {
  6420. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6421. .stream_name = "VA CDC DMA0 Capture",
  6422. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6423. .platform_name = "msm-pcm-routing",
  6424. .codec_name = "bolero_codec",
  6425. .codec_dai_name = "va_macro_tx1",
  6426. .no_pcm = 1,
  6427. .dpcm_capture = 1,
  6428. .init = &msm_va_cdc_dma_init,
  6429. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6430. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6431. .ignore_suspend = 1,
  6432. .ops = &msm_cdc_dma_be_ops,
  6433. },
  6434. {
  6435. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6436. .stream_name = "VA CDC DMA1 Capture",
  6437. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6438. .platform_name = "msm-pcm-routing",
  6439. .codec_name = "bolero_codec",
  6440. .codec_dai_name = "va_macro_tx2",
  6441. .no_pcm = 1,
  6442. .dpcm_capture = 1,
  6443. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6444. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6445. .ignore_suspend = 1,
  6446. .ops = &msm_cdc_dma_be_ops,
  6447. },
  6448. };
  6449. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6450. {
  6451. .name = LPASS_BE_PRI_SPDIF_RX,
  6452. .stream_name = "Primary SPDIF Playback",
  6453. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6454. .platform_name = "msm-pcm-routing",
  6455. .codec_name = "msm-stub-codec.1",
  6456. .codec_dai_name = "msm-stub-rx",
  6457. .no_pcm = 1,
  6458. .dpcm_playback = 1,
  6459. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6460. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6461. .ops = &msm_spdif_be_ops,
  6462. .ignore_suspend = 1,
  6463. .ignore_pmdown_time = 1,
  6464. },
  6465. {
  6466. .name = LPASS_BE_PRI_SPDIF_TX,
  6467. .stream_name = "Primary SPDIF Capture",
  6468. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6469. .platform_name = "msm-pcm-routing",
  6470. .codec_name = "msm-stub-codec.1",
  6471. .codec_dai_name = "msm-stub-tx",
  6472. .no_pcm = 1,
  6473. .dpcm_capture = 1,
  6474. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6475. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6476. .ops = &msm_spdif_be_ops,
  6477. .ignore_suspend = 1,
  6478. },
  6479. {
  6480. .name = LPASS_BE_SEC_SPDIF_RX,
  6481. .stream_name = "Secondary SPDIF Playback",
  6482. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6483. .platform_name = "msm-pcm-routing",
  6484. .codec_name = "msm-stub-codec.1",
  6485. .codec_dai_name = "msm-stub-rx",
  6486. .no_pcm = 1,
  6487. .dpcm_playback = 1,
  6488. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6489. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6490. .ops = &msm_spdif_be_ops,
  6491. .ignore_suspend = 1,
  6492. .ignore_pmdown_time = 1,
  6493. },
  6494. {
  6495. .name = LPASS_BE_SEC_SPDIF_TX,
  6496. .stream_name = "Secondary SPDIF Capture",
  6497. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6498. .platform_name = "msm-pcm-routing",
  6499. .codec_name = "msm-stub-codec.1",
  6500. .codec_dai_name = "msm-stub-tx",
  6501. .no_pcm = 1,
  6502. .dpcm_capture = 1,
  6503. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6504. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6505. .ops = &msm_spdif_be_ops,
  6506. .ignore_suspend = 1,
  6507. },
  6508. };
  6509. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6510. ARRAY_SIZE(msm_common_dai_links) +
  6511. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6512. ARRAY_SIZE(msm_common_be_dai_links) +
  6513. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6514. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6515. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6516. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6517. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6518. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6519. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6520. ARRAY_SIZE(msm_spdif_be_dai_links)];
  6521. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6522. {
  6523. int ret = 0;
  6524. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6525. &service_nb);
  6526. if (ret < 0)
  6527. pr_err("%s: Audio notifier register failed ret = %d\n",
  6528. __func__, ret);
  6529. return ret;
  6530. }
  6531. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6532. struct snd_ctl_elem_value *ucontrol)
  6533. {
  6534. int ret = 0;
  6535. int port_id;
  6536. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6537. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6538. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6539. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6540. (vad_enable < 0) || (vad_enable > 1) ||
  6541. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6542. pr_err("%s: Invalid arguments\n", __func__);
  6543. ret = -EINVAL;
  6544. goto done;
  6545. }
  6546. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6547. vad_enable, preroll_config, vad_intf);
  6548. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6549. if (ret) {
  6550. pr_err("%s: Invalid vad interface\n", __func__);
  6551. goto done;
  6552. }
  6553. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6554. done:
  6555. return ret;
  6556. }
  6557. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6558. {
  6559. int ret = 0;
  6560. uint32_t tasha_codec = 0;
  6561. ret = afe_cal_init_hwdep(card);
  6562. if (ret) {
  6563. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6564. ret = 0;
  6565. }
  6566. /* tasha late probe when it is present */
  6567. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6568. &tasha_codec);
  6569. if (ret) {
  6570. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6571. ret = 0;
  6572. } else {
  6573. if (tasha_codec) {
  6574. ret = msm_snd_card_tasha_late_probe(card);
  6575. if (ret)
  6576. dev_err(card->dev, "%s: tasha late probe err\n",
  6577. __func__);
  6578. }
  6579. }
  6580. return ret;
  6581. }
  6582. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6583. .name = "qcs405-snd-card",
  6584. .controls = msm_snd_controls,
  6585. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6586. .late_probe = msm_snd_card_codec_late_probe,
  6587. };
  6588. static int msm_populate_dai_link_component_of_node(
  6589. struct snd_soc_card *card)
  6590. {
  6591. int i, index, ret = 0;
  6592. struct device *cdev = card->dev;
  6593. struct snd_soc_dai_link *dai_link = card->dai_link;
  6594. struct device_node *np;
  6595. if (!cdev) {
  6596. pr_err("%s: Sound card device memory NULL\n", __func__);
  6597. return -ENODEV;
  6598. }
  6599. for (i = 0; i < card->num_links; i++) {
  6600. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6601. continue;
  6602. /* populate platform_of_node for snd card dai links */
  6603. if (dai_link[i].platform_name &&
  6604. !dai_link[i].platform_of_node) {
  6605. index = of_property_match_string(cdev->of_node,
  6606. "asoc-platform-names",
  6607. dai_link[i].platform_name);
  6608. if (index < 0) {
  6609. pr_err("%s: No match found for platform name: %s\n",
  6610. __func__, dai_link[i].platform_name);
  6611. ret = index;
  6612. goto err;
  6613. }
  6614. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6615. index);
  6616. if (!np) {
  6617. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6618. __func__, dai_link[i].platform_name,
  6619. index);
  6620. ret = -ENODEV;
  6621. goto err;
  6622. }
  6623. dai_link[i].platform_of_node = np;
  6624. dai_link[i].platform_name = NULL;
  6625. }
  6626. /* populate cpu_of_node for snd card dai links */
  6627. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6628. index = of_property_match_string(cdev->of_node,
  6629. "asoc-cpu-names",
  6630. dai_link[i].cpu_dai_name);
  6631. if (index >= 0) {
  6632. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6633. index);
  6634. if (!np) {
  6635. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6636. __func__,
  6637. dai_link[i].cpu_dai_name);
  6638. ret = -ENODEV;
  6639. goto err;
  6640. }
  6641. dai_link[i].cpu_of_node = np;
  6642. dai_link[i].cpu_dai_name = NULL;
  6643. }
  6644. }
  6645. /* populate codec_of_node for snd card dai links */
  6646. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6647. index = of_property_match_string(cdev->of_node,
  6648. "asoc-codec-names",
  6649. dai_link[i].codec_name);
  6650. if (index < 0)
  6651. continue;
  6652. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6653. index);
  6654. if (!np) {
  6655. pr_err("%s: retrieving phandle for codec %s failed\n",
  6656. __func__, dai_link[i].codec_name);
  6657. ret = -ENODEV;
  6658. goto err;
  6659. }
  6660. dai_link[i].codec_of_node = np;
  6661. dai_link[i].codec_name = NULL;
  6662. }
  6663. }
  6664. err:
  6665. return ret;
  6666. }
  6667. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6668. /* FrontEnd DAI Links */
  6669. {
  6670. .name = "MSMSTUB Media1",
  6671. .stream_name = "MultiMedia1",
  6672. .cpu_dai_name = "MultiMedia1",
  6673. .platform_name = "msm-pcm-dsp.0",
  6674. .dynamic = 1,
  6675. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6676. .dpcm_playback = 1,
  6677. .dpcm_capture = 1,
  6678. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6679. SND_SOC_DPCM_TRIGGER_POST},
  6680. .codec_dai_name = "snd-soc-dummy-dai",
  6681. .codec_name = "snd-soc-dummy",
  6682. .ignore_suspend = 1,
  6683. /* this dainlink has playback support */
  6684. .ignore_pmdown_time = 1,
  6685. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6686. },
  6687. };
  6688. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6689. /* Backend DAI Links */
  6690. {
  6691. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6692. .stream_name = "VA CDC DMA0 Capture",
  6693. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6694. .platform_name = "msm-pcm-routing",
  6695. .codec_name = "bolero_codec",
  6696. .codec_dai_name = "va_macro_tx1",
  6697. .no_pcm = 1,
  6698. .dpcm_capture = 1,
  6699. .init = &msm_va_cdc_dma_init,
  6700. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6701. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6702. .ignore_suspend = 1,
  6703. .ops = &msm_cdc_dma_be_ops,
  6704. },
  6705. {
  6706. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6707. .stream_name = "VA CDC DMA1 Capture",
  6708. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6709. .platform_name = "msm-pcm-routing",
  6710. .codec_name = "bolero_codec",
  6711. .codec_dai_name = "va_macro_tx2",
  6712. .no_pcm = 1,
  6713. .dpcm_capture = 1,
  6714. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6715. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6716. .ignore_suspend = 1,
  6717. .ops = &msm_cdc_dma_be_ops,
  6718. },
  6719. };
  6720. static struct snd_soc_dai_link msm_stub_dai_links[
  6721. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6722. ARRAY_SIZE(msm_stub_be_dai_links)];
  6723. struct snd_soc_card snd_soc_card_stub_msm = {
  6724. .name = "qcs405-stub-snd-card",
  6725. };
  6726. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6727. { .compatible = "qcom,qcs405-asoc-snd",
  6728. .data = "codec"},
  6729. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6730. .data = "stub_codec"},
  6731. {},
  6732. };
  6733. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6734. {
  6735. struct snd_soc_card *card = NULL;
  6736. struct snd_soc_dai_link *dailink;
  6737. int total_links = 0;
  6738. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6739. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6740. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  6741. const struct of_device_id *match;
  6742. char __iomem *spdif_cfg, *spdif_pin_ctl;
  6743. int rc = 0;
  6744. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6745. if (!match) {
  6746. dev_err(dev, "%s: No DT match found for sound card\n",
  6747. __func__);
  6748. return NULL;
  6749. }
  6750. if (!strcmp(match->data, "codec")) {
  6751. card = &snd_soc_card_qcs405_msm;
  6752. memcpy(msm_qcs405_dai_links + total_links,
  6753. msm_common_dai_links,
  6754. sizeof(msm_common_dai_links));
  6755. total_links += ARRAY_SIZE(msm_common_dai_links);
  6756. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6757. &wsa_bolero_codec);
  6758. if (rc) {
  6759. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6760. __func__);
  6761. } else {
  6762. if (wsa_bolero_codec) {
  6763. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6764. __func__);
  6765. memcpy(msm_qcs405_dai_links + total_links,
  6766. msm_bolero_fe_dai_links,
  6767. sizeof(msm_bolero_fe_dai_links));
  6768. total_links +=
  6769. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6770. }
  6771. }
  6772. memcpy(msm_qcs405_dai_links + total_links,
  6773. msm_common_misc_fe_dai_links,
  6774. sizeof(msm_common_misc_fe_dai_links));
  6775. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6776. memcpy(msm_qcs405_dai_links + total_links,
  6777. msm_common_be_dai_links,
  6778. sizeof(msm_common_be_dai_links));
  6779. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6780. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6781. &tasha_codec);
  6782. if (rc) {
  6783. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6784. __func__);
  6785. } else {
  6786. if (tasha_codec) {
  6787. memcpy(msm_qcs405_dai_links + total_links,
  6788. msm_tasha_be_dai_links,
  6789. sizeof(msm_tasha_be_dai_links));
  6790. total_links +=
  6791. ARRAY_SIZE(msm_tasha_be_dai_links);
  6792. }
  6793. }
  6794. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6795. &va_bolero_codec);
  6796. if (rc) {
  6797. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6798. __func__);
  6799. } else {
  6800. if (va_bolero_codec) {
  6801. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6802. __func__);
  6803. memcpy(msm_qcs405_dai_links + total_links,
  6804. msm_va_cdc_dma_be_dai_links,
  6805. sizeof(msm_va_cdc_dma_be_dai_links));
  6806. total_links +=
  6807. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6808. }
  6809. }
  6810. if (wsa_bolero_codec) {
  6811. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6812. __func__);
  6813. memcpy(msm_qcs405_dai_links + total_links,
  6814. msm_wsa_cdc_dma_be_dai_links,
  6815. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6816. total_links +=
  6817. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6818. }
  6819. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6820. &mi2s_audio_intf);
  6821. if (rc) {
  6822. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6823. __func__);
  6824. } else {
  6825. if (mi2s_audio_intf) {
  6826. memcpy(msm_qcs405_dai_links + total_links,
  6827. msm_mi2s_be_dai_links,
  6828. sizeof(msm_mi2s_be_dai_links));
  6829. total_links +=
  6830. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6831. }
  6832. }
  6833. rc = of_property_read_u32(dev->of_node,
  6834. "qcom,auxpcm-audio-intf",
  6835. &auxpcm_audio_intf);
  6836. if (rc) {
  6837. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6838. __func__);
  6839. } else {
  6840. if (auxpcm_audio_intf) {
  6841. memcpy(msm_qcs405_dai_links + total_links,
  6842. msm_auxpcm_be_dai_links,
  6843. sizeof(msm_auxpcm_be_dai_links));
  6844. total_links +=
  6845. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6846. }
  6847. }
  6848. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  6849. &spdif_audio_intf);
  6850. if (rc) {
  6851. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  6852. __func__);
  6853. } else {
  6854. if (spdif_audio_intf) {
  6855. memcpy(msm_qcs405_dai_links + total_links,
  6856. msm_spdif_be_dai_links,
  6857. sizeof(msm_spdif_be_dai_links));
  6858. total_links +=
  6859. ARRAY_SIZE(msm_spdif_be_dai_links);
  6860. /* enable spdif coax pins */
  6861. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  6862. spdif_pin_ctl =
  6863. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  6864. iowrite32(0xc0, spdif_cfg);
  6865. iowrite32(0x2220, spdif_pin_ctl);
  6866. }
  6867. }
  6868. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  6869. &wcn_audio_intf);
  6870. if (rc) {
  6871. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  6872. __func__);
  6873. } else {
  6874. if (wcn_audio_intf) {
  6875. memcpy(msm_qcs405_dai_links + total_links,
  6876. msm_wcn_be_dai_links,
  6877. sizeof(msm_wcn_be_dai_links));
  6878. total_links +=
  6879. ARRAY_SIZE(msm_wcn_be_dai_links);
  6880. }
  6881. }
  6882. dailink = msm_qcs405_dai_links;
  6883. } else if (!strcmp(match->data, "stub_codec")) {
  6884. card = &snd_soc_card_stub_msm;
  6885. memcpy(msm_stub_dai_links + total_links,
  6886. msm_stub_fe_dai_links,
  6887. sizeof(msm_stub_fe_dai_links));
  6888. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6889. memcpy(msm_stub_dai_links + total_links,
  6890. msm_stub_be_dai_links,
  6891. sizeof(msm_stub_be_dai_links));
  6892. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6893. dailink = msm_stub_dai_links;
  6894. }
  6895. if (card) {
  6896. card->dai_link = dailink;
  6897. card->num_links = total_links;
  6898. }
  6899. return card;
  6900. }
  6901. static int msm_wsa881x_init(struct snd_soc_component *component)
  6902. {
  6903. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6904. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6905. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6906. SPKR_L_BOOST, SPKR_L_VI};
  6907. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6908. SPKR_R_BOOST, SPKR_R_VI};
  6909. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6910. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6911. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6912. struct msm_asoc_mach_data *pdata;
  6913. struct snd_soc_dapm_context *dapm;
  6914. int ret = 0;
  6915. if (!codec) {
  6916. pr_err("%s codec is NULL\n", __func__);
  6917. return -EINVAL;
  6918. }
  6919. dapm = snd_soc_codec_get_dapm(codec);
  6920. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6921. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6922. __func__, codec->component.name);
  6923. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6924. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6925. &ch_rate[0], &spkleft_port_types[0]);
  6926. if (dapm->component) {
  6927. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6928. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6929. }
  6930. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6931. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6932. __func__, codec->component.name);
  6933. wsa881x_set_channel_map(codec, &spkright_ports[0],
  6934. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6935. &ch_rate[0], &spkright_port_types[0]);
  6936. if (dapm->component) {
  6937. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6938. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6939. }
  6940. } else {
  6941. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  6942. codec->component.name);
  6943. ret = -EINVAL;
  6944. goto err;
  6945. }
  6946. pdata = snd_soc_card_get_drvdata(component->card);
  6947. if (pdata && pdata->codec_root)
  6948. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6949. codec);
  6950. err:
  6951. return ret;
  6952. }
  6953. static int msm_init_wsa_dev(struct platform_device *pdev,
  6954. struct snd_soc_card *card)
  6955. {
  6956. struct device_node *wsa_of_node;
  6957. u32 wsa_max_devs;
  6958. u32 wsa_dev_cnt;
  6959. int i;
  6960. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6961. const char *wsa_auxdev_name_prefix[1];
  6962. char *dev_name_str = NULL;
  6963. int found = 0;
  6964. int ret = 0;
  6965. /* Get maximum WSA device count for this platform */
  6966. ret = of_property_read_u32(pdev->dev.of_node,
  6967. "qcom,wsa-max-devs", &wsa_max_devs);
  6968. if (ret) {
  6969. dev_info(&pdev->dev,
  6970. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6971. __func__, pdev->dev.of_node->full_name, ret);
  6972. card->num_aux_devs = 0;
  6973. return 0;
  6974. }
  6975. if (wsa_max_devs == 0) {
  6976. dev_warn(&pdev->dev,
  6977. "%s: Max WSA devices is 0 for this target?\n",
  6978. __func__);
  6979. card->num_aux_devs = 0;
  6980. return 0;
  6981. }
  6982. /* Get count of WSA device phandles for this platform */
  6983. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6984. "qcom,wsa-devs", NULL);
  6985. if (wsa_dev_cnt == -ENOENT) {
  6986. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6987. __func__);
  6988. goto err;
  6989. } else if (wsa_dev_cnt <= 0) {
  6990. dev_err(&pdev->dev,
  6991. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6992. __func__, wsa_dev_cnt);
  6993. ret = -EINVAL;
  6994. goto err;
  6995. }
  6996. /*
  6997. * Expect total phandles count to be NOT less than maximum possible
  6998. * WSA count. However, if it is less, then assign same value to
  6999. * max count as well.
  7000. */
  7001. if (wsa_dev_cnt < wsa_max_devs) {
  7002. dev_dbg(&pdev->dev,
  7003. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7004. __func__, wsa_max_devs, wsa_dev_cnt);
  7005. wsa_max_devs = wsa_dev_cnt;
  7006. }
  7007. /* Make sure prefix string passed for each WSA device */
  7008. ret = of_property_count_strings(pdev->dev.of_node,
  7009. "qcom,wsa-aux-dev-prefix");
  7010. if (ret != wsa_dev_cnt) {
  7011. dev_err(&pdev->dev,
  7012. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7013. __func__, wsa_dev_cnt, ret);
  7014. ret = -EINVAL;
  7015. goto err;
  7016. }
  7017. /*
  7018. * Alloc mem to store phandle and index info of WSA device, if already
  7019. * registered with ALSA core
  7020. */
  7021. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7022. sizeof(struct msm_wsa881x_dev_info),
  7023. GFP_KERNEL);
  7024. if (!wsa881x_dev_info) {
  7025. ret = -ENOMEM;
  7026. goto err;
  7027. }
  7028. /*
  7029. * search and check whether all WSA devices are already
  7030. * registered with ALSA core or not. If found a node, store
  7031. * the node and the index in a local array of struct for later
  7032. * use.
  7033. */
  7034. for (i = 0; i < wsa_dev_cnt; i++) {
  7035. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7036. "qcom,wsa-devs", i);
  7037. if (unlikely(!wsa_of_node)) {
  7038. /* we should not be here */
  7039. dev_err(&pdev->dev,
  7040. "%s: wsa dev node is not present\n",
  7041. __func__);
  7042. ret = -EINVAL;
  7043. goto err_free_dev_info;
  7044. }
  7045. if (soc_find_component(wsa_of_node, NULL)) {
  7046. /* WSA device registered with ALSA core */
  7047. wsa881x_dev_info[found].of_node = wsa_of_node;
  7048. wsa881x_dev_info[found].index = i;
  7049. found++;
  7050. if (found == wsa_max_devs)
  7051. break;
  7052. }
  7053. }
  7054. if (found < wsa_max_devs) {
  7055. dev_err(&pdev->dev,
  7056. "%s: failed to find %d components. Found only %d\n",
  7057. __func__, wsa_max_devs, found);
  7058. return -EPROBE_DEFER;
  7059. }
  7060. dev_info(&pdev->dev,
  7061. "%s: found %d wsa881x devices registered with ALSA core\n",
  7062. __func__, found);
  7063. card->num_aux_devs = wsa_max_devs;
  7064. card->num_configs = wsa_max_devs;
  7065. /* Alloc array of AUX devs struct */
  7066. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7067. sizeof(struct snd_soc_aux_dev),
  7068. GFP_KERNEL);
  7069. if (!msm_aux_dev) {
  7070. ret = -ENOMEM;
  7071. goto err_free_dev_info;
  7072. }
  7073. /* Alloc array of codec conf struct */
  7074. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7075. sizeof(struct snd_soc_codec_conf),
  7076. GFP_KERNEL);
  7077. if (!msm_codec_conf) {
  7078. ret = -ENOMEM;
  7079. goto err_free_aux_dev;
  7080. }
  7081. for (i = 0; i < card->num_aux_devs; i++) {
  7082. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7083. GFP_KERNEL);
  7084. if (!dev_name_str) {
  7085. ret = -ENOMEM;
  7086. goto err_free_cdc_conf;
  7087. }
  7088. ret = of_property_read_string_index(pdev->dev.of_node,
  7089. "qcom,wsa-aux-dev-prefix",
  7090. wsa881x_dev_info[i].index,
  7091. wsa_auxdev_name_prefix);
  7092. if (ret) {
  7093. dev_err(&pdev->dev,
  7094. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7095. __func__, ret);
  7096. ret = -EINVAL;
  7097. goto err_free_dev_name_str;
  7098. }
  7099. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7100. msm_aux_dev[i].name = dev_name_str;
  7101. msm_aux_dev[i].codec_name = NULL;
  7102. msm_aux_dev[i].codec_of_node =
  7103. wsa881x_dev_info[i].of_node;
  7104. msm_aux_dev[i].init = msm_wsa881x_init;
  7105. msm_codec_conf[i].dev_name = NULL;
  7106. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7107. msm_codec_conf[i].of_node =
  7108. wsa881x_dev_info[i].of_node;
  7109. }
  7110. card->codec_conf = msm_codec_conf;
  7111. card->aux_dev = msm_aux_dev;
  7112. return 0;
  7113. err_free_dev_name_str:
  7114. devm_kfree(&pdev->dev, dev_name_str);
  7115. err_free_cdc_conf:
  7116. devm_kfree(&pdev->dev, msm_codec_conf);
  7117. err_free_aux_dev:
  7118. devm_kfree(&pdev->dev, msm_aux_dev);
  7119. err_free_dev_info:
  7120. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7121. err:
  7122. return ret;
  7123. }
  7124. static int msm_csra66x0_init(struct snd_soc_component *component)
  7125. {
  7126. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7127. if (!codec) {
  7128. pr_err("%s codec is NULL\n", __func__);
  7129. return -EINVAL;
  7130. }
  7131. return 0;
  7132. }
  7133. static int msm_init_csra_dev(struct platform_device *pdev,
  7134. struct snd_soc_card *card)
  7135. {
  7136. struct device_node *csra_of_node;
  7137. u32 csra_max_devs;
  7138. u32 csra_dev_cnt;
  7139. char *dev_name_str = NULL;
  7140. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7141. const char *csra_auxdev_name_prefix[1];
  7142. int i;
  7143. int found = 0;
  7144. int ret = 0;
  7145. /* Get maximum CSRA device count for this platform */
  7146. ret = of_property_read_u32(pdev->dev.of_node,
  7147. "qcom,csra-max-devs", &csra_max_devs);
  7148. if (ret) {
  7149. dev_info(&pdev->dev,
  7150. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7151. __func__, pdev->dev.of_node->full_name, ret);
  7152. card->num_aux_devs = 0;
  7153. return 0;
  7154. }
  7155. if (csra_max_devs == 0) {
  7156. dev_warn(&pdev->dev,
  7157. "%s: Max CSRA devices is 0 for this target?\n",
  7158. __func__);
  7159. return 0;
  7160. }
  7161. /* Get count of CSRA device phandles for this platform */
  7162. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7163. "qcom,csra-devs", NULL);
  7164. if (csra_dev_cnt == -ENOENT) {
  7165. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7166. __func__);
  7167. goto err;
  7168. } else if (csra_dev_cnt <= 0) {
  7169. dev_err(&pdev->dev,
  7170. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7171. __func__, csra_dev_cnt);
  7172. ret = -EINVAL;
  7173. goto err;
  7174. }
  7175. /*
  7176. * Expect total phandles count to be NOT less than maximum possible
  7177. * CSRA count. However, if it is less, then assign same value to
  7178. * max count as well.
  7179. */
  7180. if (csra_dev_cnt < csra_max_devs) {
  7181. dev_dbg(&pdev->dev,
  7182. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7183. __func__, csra_max_devs, csra_dev_cnt);
  7184. csra_max_devs = csra_dev_cnt;
  7185. }
  7186. /* Make sure prefix string passed for each CSRA device */
  7187. ret = of_property_count_strings(pdev->dev.of_node,
  7188. "qcom,csra-aux-dev-prefix");
  7189. if (ret != csra_dev_cnt) {
  7190. dev_err(&pdev->dev,
  7191. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7192. __func__, csra_dev_cnt, ret);
  7193. ret = -EINVAL;
  7194. goto err;
  7195. }
  7196. /*
  7197. * Alloc mem to store phandle and index info of CSRA device, if already
  7198. * registered with ALSA core
  7199. */
  7200. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7201. sizeof(struct msm_csra66x0_dev_info),
  7202. GFP_KERNEL);
  7203. if (!csra66x0_dev_info) {
  7204. ret = -ENOMEM;
  7205. goto err;
  7206. }
  7207. /*
  7208. * search and check whether all CSRA devices are already
  7209. * registered with ALSA core or not. If found a node, store
  7210. * the node and the index in a local array of struct for later
  7211. * use.
  7212. */
  7213. for (i = 0; i < csra_dev_cnt; i++) {
  7214. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7215. "qcom,csra-devs", i);
  7216. if (unlikely(!csra_of_node)) {
  7217. /* we should not be here */
  7218. dev_err(&pdev->dev,
  7219. "%s: csra dev node is not present\n",
  7220. __func__);
  7221. ret = -EINVAL;
  7222. goto err_free_dev_info;
  7223. }
  7224. if (soc_find_component(csra_of_node, NULL)) {
  7225. /* CSRA device registered with ALSA core */
  7226. csra66x0_dev_info[found].of_node = csra_of_node;
  7227. csra66x0_dev_info[found].index = i;
  7228. found++;
  7229. if (found == csra_max_devs)
  7230. break;
  7231. }
  7232. }
  7233. if (found < csra_max_devs) {
  7234. dev_dbg(&pdev->dev,
  7235. "%s: failed to find %d components. Found only %d\n",
  7236. __func__, csra_max_devs, found);
  7237. return -EPROBE_DEFER;
  7238. }
  7239. dev_info(&pdev->dev,
  7240. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7241. __func__, found);
  7242. card->num_aux_devs = csra_max_devs;
  7243. card->num_configs = csra_max_devs;
  7244. /* Alloc array of AUX devs struct */
  7245. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7246. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7247. if (!msm_aux_dev) {
  7248. ret = -ENOMEM;
  7249. goto err_free_dev_info;
  7250. }
  7251. /* Alloc array of codec conf struct */
  7252. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7253. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7254. if (!msm_codec_conf) {
  7255. ret = -ENOMEM;
  7256. goto err_free_aux_dev;
  7257. }
  7258. for (i = 0; i < card->num_aux_devs; i++) {
  7259. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7260. GFP_KERNEL);
  7261. if (!dev_name_str) {
  7262. ret = -ENOMEM;
  7263. goto err_free_cdc_conf;
  7264. }
  7265. ret = of_property_read_string_index(pdev->dev.of_node,
  7266. "qcom,csra-aux-dev-prefix",
  7267. csra66x0_dev_info[i].index,
  7268. csra_auxdev_name_prefix);
  7269. if (ret) {
  7270. dev_err(&pdev->dev,
  7271. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7272. __func__, ret);
  7273. ret = -EINVAL;
  7274. goto err_free_dev_name_str;
  7275. }
  7276. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7277. msm_aux_dev[i].name = dev_name_str;
  7278. msm_aux_dev[i].codec_name = NULL;
  7279. msm_aux_dev[i].codec_of_node =
  7280. csra66x0_dev_info[i].of_node;
  7281. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7282. msm_codec_conf[i].dev_name = NULL;
  7283. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7284. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7285. }
  7286. card->codec_conf = msm_codec_conf;
  7287. card->aux_dev = msm_aux_dev;
  7288. return 0;
  7289. err_free_dev_name_str:
  7290. devm_kfree(&pdev->dev, dev_name_str);
  7291. err_free_cdc_conf:
  7292. devm_kfree(&pdev->dev, msm_codec_conf);
  7293. err_free_aux_dev:
  7294. devm_kfree(&pdev->dev, msm_aux_dev);
  7295. err_free_dev_info:
  7296. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7297. err:
  7298. return ret;
  7299. }
  7300. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7301. {
  7302. int count;
  7303. u32 mi2s_master_slave[MI2S_MAX];
  7304. int ret;
  7305. for (count = 0; count < MI2S_MAX; count++) {
  7306. mutex_init(&mi2s_intf_conf[count].lock);
  7307. mi2s_intf_conf[count].ref_cnt = 0;
  7308. }
  7309. ret = of_property_read_u32_array(pdev->dev.of_node,
  7310. "qcom,msm-mi2s-master",
  7311. mi2s_master_slave, MI2S_MAX);
  7312. if (ret) {
  7313. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7314. __func__);
  7315. } else {
  7316. for (count = 0; count < MI2S_MAX; count++) {
  7317. mi2s_intf_conf[count].msm_is_mi2s_master =
  7318. mi2s_master_slave[count];
  7319. }
  7320. }
  7321. }
  7322. static void msm_i2s_auxpcm_deinit(void)
  7323. {
  7324. int count;
  7325. for (count = 0; count < MI2S_MAX; count++) {
  7326. mutex_destroy(&mi2s_intf_conf[count].lock);
  7327. mi2s_intf_conf[count].ref_cnt = 0;
  7328. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7329. }
  7330. }
  7331. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7332. uint32_t busnum, uint32_t addr)
  7333. {
  7334. struct i2c_adapter *adap;
  7335. u8 rbuf;
  7336. struct i2c_msg msg;
  7337. int status = 0;
  7338. adap = i2c_get_adapter(busnum);
  7339. if (!adap) {
  7340. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7341. __func__, busnum);
  7342. return -EBUSY;
  7343. }
  7344. /* to test presence, read one byte from device */
  7345. msg.addr = addr;
  7346. msg.flags = I2C_M_RD;
  7347. msg.len = 1;
  7348. msg.buf = &rbuf;
  7349. status = i2c_transfer(adap, &msg, 1);
  7350. i2c_put_adapter(adap);
  7351. if (status != 1) {
  7352. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7353. __func__, addr);
  7354. return -ENODEV;
  7355. }
  7356. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7357. __func__, addr);
  7358. return 0;
  7359. }
  7360. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7361. struct snd_soc_card *card)
  7362. {
  7363. int i;
  7364. uint32_t ep92_busnum = 0;
  7365. uint32_t ep92_reg = 0;
  7366. const char *ep92_name = NULL;
  7367. struct snd_soc_dai_link *dai;
  7368. int rc = 0;
  7369. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7370. &ep92_busnum);
  7371. if (rc) {
  7372. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7373. return 0;
  7374. }
  7375. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7376. &ep92_reg);
  7377. if (rc) {
  7378. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7379. return 0;
  7380. }
  7381. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7382. &ep92_name);
  7383. if (rc) {
  7384. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7385. return 0;
  7386. }
  7387. /* check I2C bus for connected ep92 chip */
  7388. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7389. /* check a second time after a short delay */
  7390. msleep(20);
  7391. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7392. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  7393. __func__);
  7394. /* continue with snd_card registration without ep92 */
  7395. return 0;
  7396. }
  7397. }
  7398. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  7399. /* update codec info in MI2S dai link */
  7400. dai = &msm_mi2s_be_dai_links[0];
  7401. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  7402. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  7403. dev_dbg(&pdev->dev,
  7404. "%s: Set Sec MI2S dai to ep92 codec\n",
  7405. __func__);
  7406. dai->codec_name = ep92_name;
  7407. dai->codec_dai_name = "ep92-hdmi";
  7408. break;
  7409. }
  7410. dai++;
  7411. }
  7412. /* update codec info in SPDIF dai link */
  7413. dai = &msm_spdif_be_dai_links[0];
  7414. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  7415. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  7416. dev_dbg(&pdev->dev,
  7417. "%s: Set Sec SPDIF dai to ep92 codec\n",
  7418. __func__);
  7419. dai->codec_name = ep92_name;
  7420. dai->codec_dai_name = "ep92-arc";
  7421. break;
  7422. }
  7423. dai++;
  7424. }
  7425. return 0;
  7426. }
  7427. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7428. {
  7429. struct snd_soc_card *card;
  7430. struct msm_asoc_mach_data *pdata;
  7431. int ret;
  7432. u32 val;
  7433. const char *micb_supply_str = "tdm-vdd-micb-supply";
  7434. const char *micb_supply_str1 = "tdm-vdd-micb";
  7435. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  7436. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  7437. if (!pdev->dev.of_node) {
  7438. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7439. return -EINVAL;
  7440. }
  7441. pdata = devm_kzalloc(&pdev->dev,
  7442. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7443. if (!pdata)
  7444. return -ENOMEM;
  7445. /* test for ep92 HDMI bridge and update dai links accordingly */
  7446. ret = msm_detect_ep92_dev(pdev, card);
  7447. if (ret)
  7448. goto err;
  7449. card = populate_snd_card_dailinks(&pdev->dev);
  7450. if (!card) {
  7451. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7452. ret = -EINVAL;
  7453. goto err;
  7454. }
  7455. card->dev = &pdev->dev;
  7456. platform_set_drvdata(pdev, card);
  7457. snd_soc_card_set_drvdata(card, pdata);
  7458. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7459. if (ret) {
  7460. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7461. ret);
  7462. goto err;
  7463. }
  7464. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7465. if (ret) {
  7466. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7467. ret);
  7468. goto err;
  7469. }
  7470. ret = msm_populate_dai_link_component_of_node(card);
  7471. if (ret) {
  7472. ret = -EPROBE_DEFER;
  7473. goto err;
  7474. }
  7475. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7476. if (ret) {
  7477. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7478. val = 0;
  7479. }
  7480. if (val) {
  7481. ret = msm_init_csra_dev(pdev, card);
  7482. if (ret)
  7483. goto err;
  7484. } else {
  7485. ret = msm_init_wsa_dev(pdev, card);
  7486. if (ret)
  7487. goto err;
  7488. }
  7489. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7490. "qcom,cdc-dmic01-gpios", 0);
  7491. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7492. "qcom,cdc-dmic23-gpios", 0);
  7493. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7494. "qcom,cdc-dmic45-gpios", 0);
  7495. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7496. "qcom,cdc-dmic67-gpios", 0);
  7497. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7498. "qcom,pri-mi2s-gpios", 0);
  7499. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7500. "qcom,sec-mi2s-gpios", 0);
  7501. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7502. "qcom,tert-mi2s-gpios", 0);
  7503. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7504. "qcom,quat-mi2s-gpios", 0);
  7505. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7506. "qcom,quin-mi2s-gpios", 0);
  7507. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  7508. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  7509. micb_supply_str1);
  7510. if (IS_ERR(pdata->tdm_micb_supply)) {
  7511. ret = PTR_ERR(pdata->tdm_micb_supply);
  7512. dev_err(&pdev->dev,
  7513. "%s:Failed to get micbias supply for TDM Mic %d\n",
  7514. __func__, ret);
  7515. }
  7516. ret = of_property_read_u32(pdev->dev.of_node,
  7517. micb_voltage_str,
  7518. &pdata->tdm_micb_voltage);
  7519. if (ret) {
  7520. dev_err(&pdev->dev,
  7521. "%s:Looking up %s property in node %s failed\n",
  7522. __func__, micb_voltage_str,
  7523. pdev->dev.of_node->full_name);
  7524. }
  7525. ret = of_property_read_u32(pdev->dev.of_node,
  7526. micb_current_str,
  7527. &pdata->tdm_micb_current);
  7528. if (ret) {
  7529. dev_err(&pdev->dev,
  7530. "%s:Looking up %s property in node %s failed\n",
  7531. __func__, micb_current_str,
  7532. pdev->dev.of_node->full_name);
  7533. }
  7534. }
  7535. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7536. if (ret == -EPROBE_DEFER) {
  7537. if (codec_reg_done)
  7538. ret = -EINVAL;
  7539. goto err;
  7540. } else if (ret) {
  7541. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7542. ret);
  7543. goto err;
  7544. }
  7545. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7546. spdev = pdev;
  7547. ret = msm_mdf_mem_init();
  7548. if (ret)
  7549. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  7550. ret);
  7551. msm_i2s_auxpcm_init(pdev);
  7552. is_initial_boot = true;
  7553. return 0;
  7554. err:
  7555. return ret;
  7556. }
  7557. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7558. {
  7559. audio_notifier_deregister("qcs405");
  7560. msm_i2s_auxpcm_deinit();
  7561. msm_mdf_mem_deinit();
  7562. return 0;
  7563. }
  7564. static struct platform_driver qcs405_asoc_machine_driver = {
  7565. .driver = {
  7566. .name = DRV_NAME,
  7567. .owner = THIS_MODULE,
  7568. .pm = &snd_soc_pm_ops,
  7569. .of_match_table = qcs405_asoc_machine_of_match,
  7570. },
  7571. .probe = msm_asoc_machine_probe,
  7572. .remove = msm_asoc_machine_remove,
  7573. };
  7574. module_platform_driver(qcs405_asoc_machine_driver);
  7575. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7576. MODULE_LICENSE("GPL v2");
  7577. MODULE_ALIAS("platform:" DRV_NAME);
  7578. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);