dsi_drm.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <drm/drm_atomic_helper.h>
  6. #include <drm/drm_atomic.h>
  7. #include "msm_kms.h"
  8. #include "sde_connector.h"
  9. #include "dsi_drm.h"
  10. #include "sde_trace.h"
  11. #include "sde_encoder.h"
  12. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  13. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  14. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  15. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  16. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  17. #define DEFAULT_PANEL_PREFILL_LINES 25
  18. static struct dsi_display_mode_priv_info default_priv_info = {
  19. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  20. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  21. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  22. .dsc_enabled = false,
  23. };
  24. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  25. struct dsi_display_mode *dsi_mode)
  26. {
  27. memset(dsi_mode, 0, sizeof(*dsi_mode));
  28. dsi_mode->timing.h_active = drm_mode->hdisplay;
  29. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  30. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  31. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  32. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  33. drm_mode->hdisplay;
  34. dsi_mode->timing.h_skew = drm_mode->hskew;
  35. dsi_mode->timing.v_active = drm_mode->vdisplay;
  36. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  37. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  38. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  39. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  40. drm_mode->vdisplay;
  41. dsi_mode->timing.refresh_rate = drm_mode->vrefresh;
  42. dsi_mode->pixel_clk_khz = drm_mode->clock;
  43. dsi_mode->priv_info =
  44. (struct dsi_display_mode_priv_info *)drm_mode->private;
  45. if (dsi_mode->priv_info) {
  46. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  47. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  48. dsi_mode->timing.vdc_enabled = dsi_mode->priv_info->vdc_enabled;
  49. dsi_mode->timing.vdc = &dsi_mode->priv_info->vdc;
  50. dsi_mode->timing.pclk_scale = dsi_mode->priv_info->pclk_scale;
  51. }
  52. if (msm_is_mode_seamless(drm_mode))
  53. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  54. if (msm_is_mode_dynamic_fps(drm_mode))
  55. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  56. if (msm_needs_vblank_pre_modeset(drm_mode))
  57. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  58. if (msm_is_mode_seamless_dms(drm_mode))
  59. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  60. if (msm_is_mode_seamless_vrr(drm_mode))
  61. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  62. if (msm_is_mode_seamless_poms(drm_mode))
  63. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  64. if (msm_is_mode_seamless_dyn_clk(drm_mode))
  65. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  66. dsi_mode->timing.h_sync_polarity =
  67. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  68. dsi_mode->timing.v_sync_polarity =
  69. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  70. if (drm_mode->flags & DRM_MODE_FLAG_VID_MODE_PANEL)
  71. dsi_mode->panel_mode = DSI_OP_VIDEO_MODE;
  72. if (drm_mode->flags & DRM_MODE_FLAG_CMD_MODE_PANEL)
  73. dsi_mode->panel_mode = DSI_OP_CMD_MODE;
  74. }
  75. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  76. struct drm_display_mode *drm_mode)
  77. {
  78. bool video_mode = (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE);
  79. memset(drm_mode, 0, sizeof(*drm_mode));
  80. drm_mode->hdisplay = dsi_mode->timing.h_active;
  81. drm_mode->hsync_start = drm_mode->hdisplay +
  82. dsi_mode->timing.h_front_porch;
  83. drm_mode->hsync_end = drm_mode->hsync_start +
  84. dsi_mode->timing.h_sync_width;
  85. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  86. drm_mode->hskew = dsi_mode->timing.h_skew;
  87. drm_mode->vdisplay = dsi_mode->timing.v_active;
  88. drm_mode->vsync_start = drm_mode->vdisplay +
  89. dsi_mode->timing.v_front_porch;
  90. drm_mode->vsync_end = drm_mode->vsync_start +
  91. dsi_mode->timing.v_sync_width;
  92. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  93. drm_mode->vrefresh = dsi_mode->timing.refresh_rate;
  94. drm_mode->clock = dsi_mode->pixel_clk_khz;
  95. drm_mode->private = (int *)dsi_mode->priv_info;
  96. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  97. drm_mode->flags |= DRM_MODE_FLAG_SEAMLESS;
  98. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  99. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  100. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  101. drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  102. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  103. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  104. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  105. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  106. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)
  107. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS;
  108. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  109. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  110. if (dsi_mode->timing.h_sync_polarity)
  111. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  112. if (dsi_mode->timing.v_sync_polarity)
  113. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  114. if (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE)
  115. drm_mode->flags |= DRM_MODE_FLAG_VID_MODE_PANEL;
  116. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  117. drm_mode->flags |= DRM_MODE_FLAG_CMD_MODE_PANEL;
  118. /* set mode name */
  119. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%dx%d%s",
  120. drm_mode->hdisplay, drm_mode->vdisplay,
  121. drm_mode->vrefresh, drm_mode->clock,
  122. video_mode ? "vid" : "cmd");
  123. }
  124. static int dsi_bridge_attach(struct drm_bridge *bridge)
  125. {
  126. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  127. if (!bridge) {
  128. DSI_ERR("Invalid params\n");
  129. return -EINVAL;
  130. }
  131. DSI_DEBUG("[%d] attached\n", c_bridge->id);
  132. return 0;
  133. }
  134. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  135. {
  136. int rc = 0;
  137. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  138. if (!bridge) {
  139. DSI_ERR("Invalid params\n");
  140. return;
  141. }
  142. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  143. DSI_ERR("Incorrect bridge details\n");
  144. return;
  145. }
  146. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  147. /* By this point mode should have been validated through mode_fixup */
  148. rc = dsi_display_set_mode(c_bridge->display,
  149. &(c_bridge->dsi_mode), 0x0);
  150. if (rc) {
  151. DSI_ERR("[%d] failed to perform a mode set, rc=%d\n",
  152. c_bridge->id, rc);
  153. return;
  154. }
  155. if (c_bridge->dsi_mode.dsi_mode_flags &
  156. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  157. DSI_MODE_FLAG_DYN_CLK)) {
  158. DSI_DEBUG("[%d] seamless pre-enable\n", c_bridge->id);
  159. return;
  160. }
  161. SDE_ATRACE_BEGIN("dsi_display_prepare");
  162. rc = dsi_display_prepare(c_bridge->display);
  163. if (rc) {
  164. DSI_ERR("[%d] DSI display prepare failed, rc=%d\n",
  165. c_bridge->id, rc);
  166. SDE_ATRACE_END("dsi_display_prepare");
  167. return;
  168. }
  169. SDE_ATRACE_END("dsi_display_prepare");
  170. SDE_ATRACE_BEGIN("dsi_display_enable");
  171. rc = dsi_display_enable(c_bridge->display);
  172. if (rc) {
  173. DSI_ERR("[%d] DSI display enable failed, rc=%d\n",
  174. c_bridge->id, rc);
  175. (void)dsi_display_unprepare(c_bridge->display);
  176. }
  177. SDE_ATRACE_END("dsi_display_enable");
  178. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  179. if (rc)
  180. DSI_ERR("Continuous splash pipeline cleanup failed, rc=%d\n",
  181. rc);
  182. }
  183. static void dsi_bridge_enable(struct drm_bridge *bridge)
  184. {
  185. int rc = 0;
  186. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  187. struct dsi_display *display;
  188. if (!bridge) {
  189. DSI_ERR("Invalid params\n");
  190. return;
  191. }
  192. if (c_bridge->dsi_mode.dsi_mode_flags &
  193. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  194. DSI_MODE_FLAG_DYN_CLK)) {
  195. DSI_DEBUG("[%d] seamless enable\n", c_bridge->id);
  196. return;
  197. }
  198. display = c_bridge->display;
  199. rc = dsi_display_post_enable(display);
  200. if (rc)
  201. DSI_ERR("[%d] DSI display post enabled failed, rc=%d\n",
  202. c_bridge->id, rc);
  203. if (display && display->drm_conn) {
  204. sde_connector_helper_bridge_enable(display->drm_conn);
  205. if (c_bridge->dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)
  206. sde_connector_schedule_status_work(display->drm_conn,
  207. true);
  208. }
  209. }
  210. static void dsi_bridge_disable(struct drm_bridge *bridge)
  211. {
  212. int rc = 0;
  213. int private_flags;
  214. struct dsi_display *display;
  215. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  216. if (!bridge) {
  217. DSI_ERR("Invalid params\n");
  218. return;
  219. }
  220. display = c_bridge->display;
  221. private_flags =
  222. bridge->encoder->crtc->state->adjusted_mode.private_flags;
  223. if (display && display->drm_conn) {
  224. display->poms_pending =
  225. private_flags & MSM_MODE_FLAG_SEAMLESS_POMS;
  226. sde_connector_helper_bridge_disable(display->drm_conn);
  227. }
  228. rc = dsi_display_pre_disable(c_bridge->display);
  229. if (rc) {
  230. DSI_ERR("[%d] DSI display pre disable failed, rc=%d\n",
  231. c_bridge->id, rc);
  232. }
  233. }
  234. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  235. {
  236. int rc = 0;
  237. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  238. if (!bridge) {
  239. DSI_ERR("Invalid params\n");
  240. return;
  241. }
  242. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  243. SDE_ATRACE_BEGIN("dsi_display_disable");
  244. rc = dsi_display_disable(c_bridge->display);
  245. if (rc) {
  246. DSI_ERR("[%d] DSI display disable failed, rc=%d\n",
  247. c_bridge->id, rc);
  248. SDE_ATRACE_END("dsi_display_disable");
  249. return;
  250. }
  251. SDE_ATRACE_END("dsi_display_disable");
  252. rc = dsi_display_unprepare(c_bridge->display);
  253. if (rc) {
  254. DSI_ERR("[%d] DSI display unprepare failed, rc=%d\n",
  255. c_bridge->id, rc);
  256. SDE_ATRACE_END("dsi_bridge_post_disable");
  257. return;
  258. }
  259. SDE_ATRACE_END("dsi_bridge_post_disable");
  260. }
  261. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  262. const struct drm_display_mode *mode,
  263. const struct drm_display_mode *adjusted_mode)
  264. {
  265. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  266. if (!bridge || !mode || !adjusted_mode) {
  267. DSI_ERR("Invalid params\n");
  268. return;
  269. }
  270. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  271. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  272. /* restore bit_clk_rate also for dynamic clk use cases */
  273. c_bridge->dsi_mode.timing.clk_rate_hz =
  274. dsi_drm_find_bit_clk_rate(c_bridge->display, adjusted_mode);
  275. DSI_DEBUG("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  276. }
  277. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  278. const struct drm_display_mode *mode,
  279. struct drm_display_mode *adjusted_mode)
  280. {
  281. int rc = 0;
  282. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  283. struct dsi_display *display;
  284. struct dsi_display_mode dsi_mode, cur_dsi_mode, *panel_dsi_mode;
  285. struct drm_crtc_state *crtc_state;
  286. bool clone_mode = false;
  287. struct drm_encoder *encoder;
  288. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  289. if (!bridge || !mode || !adjusted_mode) {
  290. DSI_ERR("Invalid params\n");
  291. return false;
  292. }
  293. display = c_bridge->display;
  294. if (!display) {
  295. DSI_ERR("Invalid params\n");
  296. return false;
  297. }
  298. /*
  299. * if no timing defined in panel, it must be external mode
  300. * and we'll use empty priv info to populate the mode
  301. */
  302. if (display->panel && !display->panel->num_timing_nodes) {
  303. *adjusted_mode = *mode;
  304. adjusted_mode->private = (int *)&default_priv_info;
  305. adjusted_mode->private_flags = 0;
  306. return true;
  307. }
  308. convert_to_dsi_mode(mode, &dsi_mode);
  309. /*
  310. * retrieve dsi mode from dsi driver's cache since not safe to take
  311. * the drm mode config mutex in all paths
  312. */
  313. rc = dsi_display_find_mode(display, &dsi_mode, &panel_dsi_mode);
  314. if (rc)
  315. return rc;
  316. /* propagate the private info to the adjusted_mode derived dsi mode */
  317. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  318. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  319. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  320. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  321. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  322. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  323. if (rc) {
  324. DSI_ERR("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  325. return false;
  326. }
  327. if (bridge->encoder && bridge->encoder->crtc &&
  328. crtc_state->crtc) {
  329. const struct drm_display_mode *cur_mode =
  330. &crtc_state->crtc->state->mode;
  331. convert_to_dsi_mode(cur_mode, &cur_dsi_mode);
  332. cur_dsi_mode.timing.dsc_enabled =
  333. dsi_mode.priv_info->dsc_enabled;
  334. cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  335. rc = dsi_display_validate_mode_change(c_bridge->display,
  336. &cur_dsi_mode, &dsi_mode);
  337. if (rc) {
  338. DSI_ERR("[%s] seamless mode mismatch failure rc=%d\n",
  339. c_bridge->display->name, rc);
  340. return false;
  341. }
  342. drm_for_each_encoder(encoder, crtc_state->crtc->dev) {
  343. if (encoder->crtc != crtc_state->crtc)
  344. continue;
  345. if (sde_encoder_in_clone_mode(encoder))
  346. clone_mode = true;
  347. }
  348. /* No panel mode switch when drm pipeline is changing */
  349. if ((dsi_mode.panel_mode != cur_dsi_mode.panel_mode) &&
  350. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  351. (crtc_state->enable ==
  352. crtc_state->crtc->state->enable))
  353. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  354. /* No DMS/VRR when drm pipeline is changing */
  355. if (!drm_mode_equal(cur_mode, adjusted_mode) &&
  356. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  357. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)) &&
  358. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  359. (!crtc_state->active_changed ||
  360. display->is_cont_splash_enabled))
  361. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  362. }
  363. /* Reject seamless transition when active/connectors changed */
  364. if ((crtc_state->active_changed ||
  365. (crtc_state->connectors_changed && clone_mode)) &&
  366. ((dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) ||
  367. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS) ||
  368. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))) {
  369. DSI_ERR("seamless on active/conn(%d/%d) changed 0x%x\n",
  370. crtc_state->active_changed,
  371. crtc_state->connectors_changed,
  372. dsi_mode.dsi_mode_flags);
  373. return false;
  374. }
  375. /* convert back to drm mode, propagating the private info & flags */
  376. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  377. return true;
  378. }
  379. u64 dsi_drm_find_bit_clk_rate(void *display,
  380. const struct drm_display_mode *drm_mode)
  381. {
  382. int i = 0, count = 0;
  383. struct dsi_display *dsi_display = display;
  384. struct dsi_display_mode *dsi_mode;
  385. u64 bit_clk_rate = 0;
  386. if (!dsi_display || !drm_mode)
  387. return 0;
  388. dsi_display_get_mode_count(dsi_display, &count);
  389. for (i = 0; i < count; i++) {
  390. dsi_mode = &dsi_display->modes[i];
  391. if ((dsi_mode->timing.v_active == drm_mode->vdisplay) &&
  392. (dsi_mode->timing.h_active == drm_mode->hdisplay) &&
  393. (dsi_mode->pixel_clk_khz == drm_mode->clock) &&
  394. (dsi_mode->timing.refresh_rate == drm_mode->vrefresh)) {
  395. bit_clk_rate = dsi_mode->timing.clk_rate_hz;
  396. break;
  397. }
  398. }
  399. return bit_clk_rate;
  400. }
  401. int dsi_conn_get_mode_info(struct drm_connector *connector,
  402. const struct drm_display_mode *drm_mode,
  403. struct msm_mode_info *mode_info,
  404. void *display, const struct msm_resource_caps_info *avail_res)
  405. {
  406. struct dsi_display_mode dsi_mode;
  407. struct dsi_mode_info *timing;
  408. int src_bpp, tar_bpp;
  409. if (!drm_mode || !mode_info)
  410. return -EINVAL;
  411. convert_to_dsi_mode(drm_mode, &dsi_mode);
  412. if (!dsi_mode.priv_info)
  413. return -EINVAL;
  414. memset(mode_info, 0, sizeof(*mode_info));
  415. timing = &dsi_mode.timing;
  416. mode_info->frame_rate = dsi_mode.timing.refresh_rate;
  417. mode_info->vtotal = DSI_V_TOTAL(timing);
  418. mode_info->prefill_lines = dsi_mode.priv_info->panel_prefill_lines;
  419. mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer;
  420. mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom;
  421. mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode);
  422. mode_info->mdp_transfer_time_us =
  423. dsi_mode.priv_info->mdp_transfer_time_us;
  424. memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,
  425. sizeof(struct msm_display_topology));
  426. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  427. if (dsi_mode.priv_info->dsc_enabled) {
  428. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  429. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode.priv_info->dsc,
  430. sizeof(dsi_mode.priv_info->dsc));
  431. } else if (dsi_mode.priv_info->vdc_enabled) {
  432. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  433. memcpy(&mode_info->comp_info.vdc_info, &dsi_mode.priv_info->vdc,
  434. sizeof(dsi_mode.priv_info->vdc));
  435. }
  436. if (mode_info->comp_info.comp_type) {
  437. tar_bpp = dsi_mode.priv_info->pclk_scale.numer;
  438. src_bpp = dsi_mode.priv_info->pclk_scale.denom;
  439. mode_info->comp_info.comp_ratio = mult_frac(1, src_bpp,
  440. tar_bpp);
  441. mode_info->wide_bus_en = dsi_mode.priv_info->widebus_support;
  442. }
  443. if (dsi_mode.priv_info->roi_caps.enabled) {
  444. memcpy(&mode_info->roi_caps, &dsi_mode.priv_info->roi_caps,
  445. sizeof(dsi_mode.priv_info->roi_caps));
  446. }
  447. return 0;
  448. }
  449. static const struct drm_bridge_funcs dsi_bridge_ops = {
  450. .attach = dsi_bridge_attach,
  451. .mode_fixup = dsi_bridge_mode_fixup,
  452. .pre_enable = dsi_bridge_pre_enable,
  453. .enable = dsi_bridge_enable,
  454. .disable = dsi_bridge_disable,
  455. .post_disable = dsi_bridge_post_disable,
  456. .mode_set = dsi_bridge_mode_set,
  457. };
  458. int dsi_conn_set_info_blob(struct drm_connector *connector,
  459. void *info, void *display, struct msm_mode_info *mode_info)
  460. {
  461. struct dsi_display *dsi_display = display;
  462. struct dsi_panel *panel;
  463. enum dsi_pixel_format fmt;
  464. u32 bpp;
  465. if (!info || !dsi_display)
  466. return -EINVAL;
  467. dsi_display->drm_conn = connector;
  468. sde_kms_info_add_keystr(info,
  469. "display type", dsi_display->display_type);
  470. switch (dsi_display->type) {
  471. case DSI_DISPLAY_SINGLE:
  472. sde_kms_info_add_keystr(info, "display config",
  473. "single display");
  474. break;
  475. case DSI_DISPLAY_EXT_BRIDGE:
  476. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  477. break;
  478. case DSI_DISPLAY_SPLIT:
  479. sde_kms_info_add_keystr(info, "display config",
  480. "split display");
  481. break;
  482. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  483. sde_kms_info_add_keystr(info, "display config",
  484. "split ext bridge");
  485. break;
  486. default:
  487. DSI_DEBUG("invalid display type:%d\n", dsi_display->type);
  488. break;
  489. }
  490. if (!dsi_display->panel) {
  491. DSI_DEBUG("invalid panel data\n");
  492. goto end;
  493. }
  494. panel = dsi_display->panel;
  495. sde_kms_info_add_keystr(info, "panel name", panel->name);
  496. switch (panel->panel_mode) {
  497. case DSI_OP_VIDEO_MODE:
  498. sde_kms_info_add_keystr(info, "panel mode", "video");
  499. sde_kms_info_add_keystr(info, "qsync support",
  500. panel->qsync_min_fps ? "true" : "false");
  501. break;
  502. case DSI_OP_CMD_MODE:
  503. sde_kms_info_add_keystr(info, "panel mode", "command");
  504. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  505. mode_info->mdp_transfer_time_us);
  506. sde_kms_info_add_keystr(info, "qsync support",
  507. panel->qsync_min_fps ? "true" : "false");
  508. break;
  509. default:
  510. DSI_DEBUG("invalid panel type:%d\n", panel->panel_mode);
  511. break;
  512. }
  513. sde_kms_info_add_keystr(info, "dfps support",
  514. panel->dfps_caps.dfps_support ? "true" : "false");
  515. if (panel->dfps_caps.dfps_support) {
  516. sde_kms_info_add_keyint(info, "min_fps",
  517. panel->dfps_caps.min_refresh_rate);
  518. sde_kms_info_add_keyint(info, "max_fps",
  519. panel->dfps_caps.max_refresh_rate);
  520. }
  521. sde_kms_info_add_keystr(info, "dyn bitclk support",
  522. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  523. switch (panel->phy_props.rotation) {
  524. case DSI_PANEL_ROTATE_NONE:
  525. sde_kms_info_add_keystr(info, "panel orientation", "none");
  526. break;
  527. case DSI_PANEL_ROTATE_H_FLIP:
  528. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  529. break;
  530. case DSI_PANEL_ROTATE_V_FLIP:
  531. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  532. break;
  533. case DSI_PANEL_ROTATE_HV_FLIP:
  534. sde_kms_info_add_keystr(info, "panel orientation",
  535. "horz & vert flip");
  536. break;
  537. default:
  538. DSI_DEBUG("invalid panel rotation:%d\n",
  539. panel->phy_props.rotation);
  540. break;
  541. }
  542. switch (panel->bl_config.type) {
  543. case DSI_BACKLIGHT_PWM:
  544. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  545. break;
  546. case DSI_BACKLIGHT_WLED:
  547. sde_kms_info_add_keystr(info, "backlight type", "wled");
  548. break;
  549. case DSI_BACKLIGHT_DCS:
  550. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  551. break;
  552. default:
  553. DSI_DEBUG("invalid panel backlight type:%d\n",
  554. panel->bl_config.type);
  555. break;
  556. }
  557. if (panel->spr_info.enable)
  558. sde_kms_info_add_keystr(info, "spr_pack_type",
  559. msm_spr_pack_type_str[panel->spr_info.pack_type]);
  560. if (mode_info && mode_info->roi_caps.enabled) {
  561. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  562. mode_info->roi_caps.num_roi);
  563. sde_kms_info_add_keyint(info, "partial_update_xstart",
  564. mode_info->roi_caps.align.xstart_pix_align);
  565. sde_kms_info_add_keyint(info, "partial_update_walign",
  566. mode_info->roi_caps.align.width_pix_align);
  567. sde_kms_info_add_keyint(info, "partial_update_wmin",
  568. mode_info->roi_caps.align.min_width);
  569. sde_kms_info_add_keyint(info, "partial_update_ystart",
  570. mode_info->roi_caps.align.ystart_pix_align);
  571. sde_kms_info_add_keyint(info, "partial_update_halign",
  572. mode_info->roi_caps.align.height_pix_align);
  573. sde_kms_info_add_keyint(info, "partial_update_hmin",
  574. mode_info->roi_caps.align.min_height);
  575. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  576. mode_info->roi_caps.merge_rois);
  577. }
  578. fmt = dsi_display->config.common_config.dst_format;
  579. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  580. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  581. end:
  582. return 0;
  583. }
  584. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  585. bool force,
  586. void *display)
  587. {
  588. enum drm_connector_status status = connector_status_unknown;
  589. struct msm_display_info info;
  590. int rc;
  591. if (!conn || !display)
  592. return status;
  593. /* get display dsi_info */
  594. memset(&info, 0x0, sizeof(info));
  595. rc = dsi_display_get_info(conn, &info, display);
  596. if (rc) {
  597. DSI_ERR("failed to get display info, rc=%d\n", rc);
  598. return connector_status_disconnected;
  599. }
  600. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  601. status = (info.is_connected ? connector_status_connected :
  602. connector_status_disconnected);
  603. else
  604. status = connector_status_connected;
  605. conn->display_info.width_mm = info.width_mm;
  606. conn->display_info.height_mm = info.height_mm;
  607. return status;
  608. }
  609. void dsi_connector_put_modes(struct drm_connector *connector,
  610. void *display)
  611. {
  612. struct drm_display_mode *drm_mode;
  613. struct dsi_display_mode dsi_mode;
  614. struct dsi_display *dsi_display;
  615. if (!connector || !display)
  616. return;
  617. list_for_each_entry(drm_mode, &connector->modes, head) {
  618. convert_to_dsi_mode(drm_mode, &dsi_mode);
  619. dsi_display_put_mode(display, &dsi_mode);
  620. }
  621. /* free the display structure modes also */
  622. dsi_display = display;
  623. kfree(dsi_display->modes);
  624. dsi_display->modes = NULL;
  625. }
  626. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  627. {
  628. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  629. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  630. u32 dtd_size = 18;
  631. u32 header_size = sizeof(standard_header);
  632. if (!name)
  633. return -EINVAL;
  634. /* Fill standard header */
  635. memcpy(dtd, standard_header, header_size);
  636. dtd_size -= header_size;
  637. dtd_size = min_t(u32, dtd_size, strlen(name));
  638. memcpy(dtd + header_size, name, dtd_size);
  639. return 0;
  640. }
  641. static void dsi_drm_update_dtd(struct edid *edid,
  642. struct dsi_display_mode *modes, u32 modes_count)
  643. {
  644. u32 i;
  645. u32 count = min_t(u32, modes_count, 3);
  646. for (i = 0; i < count; i++) {
  647. struct detailed_timing *dtd = &edid->detailed_timings[i];
  648. struct dsi_display_mode *mode = &modes[i];
  649. struct dsi_mode_info *timing = &mode->timing;
  650. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  651. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  652. timing->h_back_porch;
  653. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  654. timing->v_back_porch;
  655. u32 h_img = 0, v_img = 0;
  656. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  657. pd->hactive_lo = timing->h_active & 0xFF;
  658. pd->hblank_lo = h_blank & 0xFF;
  659. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  660. ((timing->h_active >> 8) & 0xF) << 4;
  661. pd->vactive_lo = timing->v_active & 0xFF;
  662. pd->vblank_lo = v_blank & 0xFF;
  663. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  664. ((timing->v_active >> 8) & 0xF) << 4;
  665. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  666. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  667. pd->vsync_offset_pulse_width_lo =
  668. ((timing->v_front_porch & 0xF) << 4) |
  669. (timing->v_sync_width & 0xF);
  670. pd->hsync_vsync_offset_pulse_width_hi =
  671. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  672. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  673. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  674. (((timing->v_sync_width >> 4) & 0x3) << 0);
  675. pd->width_mm_lo = h_img & 0xFF;
  676. pd->height_mm_lo = v_img & 0xFF;
  677. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  678. ((v_img >> 8) & 0xF);
  679. pd->hborder = 0;
  680. pd->vborder = 0;
  681. pd->misc = 0;
  682. }
  683. }
  684. static void dsi_drm_update_checksum(struct edid *edid)
  685. {
  686. u8 *data = (u8 *)edid;
  687. u32 i, sum = 0;
  688. for (i = 0; i < EDID_LENGTH - 1; i++)
  689. sum += data[i];
  690. edid->checksum = 0x100 - (sum & 0xFF);
  691. }
  692. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  693. const struct msm_resource_caps_info *avail_res)
  694. {
  695. int rc, i;
  696. u32 count = 0, edid_size;
  697. struct dsi_display_mode *modes = NULL;
  698. struct drm_display_mode drm_mode;
  699. struct dsi_display *display = data;
  700. struct edid edid;
  701. u8 width_mm = connector->display_info.width_mm;
  702. u8 height_mm = connector->display_info.height_mm;
  703. const u8 edid_buf[EDID_LENGTH] = {
  704. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  705. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  706. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  707. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  708. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  709. 0x01, 0x01, 0x01, 0x01,
  710. };
  711. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  712. memcpy(&edid, edid_buf, edid_size);
  713. rc = dsi_display_get_mode_count(display, &count);
  714. if (rc) {
  715. DSI_ERR("failed to get num of modes, rc=%d\n", rc);
  716. goto end;
  717. }
  718. rc = dsi_display_get_modes(display, &modes);
  719. if (rc) {
  720. DSI_ERR("failed to get modes, rc=%d\n", rc);
  721. count = 0;
  722. goto end;
  723. }
  724. for (i = 0; i < count; i++) {
  725. struct drm_display_mode *m;
  726. memset(&drm_mode, 0x0, sizeof(drm_mode));
  727. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  728. m = drm_mode_duplicate(connector->dev, &drm_mode);
  729. if (!m) {
  730. DSI_ERR("failed to add mode %ux%u\n",
  731. drm_mode.hdisplay,
  732. drm_mode.vdisplay);
  733. count = -ENOMEM;
  734. goto end;
  735. }
  736. m->width_mm = connector->display_info.width_mm;
  737. m->height_mm = connector->display_info.height_mm;
  738. /* set the first mode in list as preferred */
  739. if (i == 0)
  740. m->type |= DRM_MODE_TYPE_PREFERRED;
  741. drm_mode_probed_add(connector, m);
  742. }
  743. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  744. if (rc) {
  745. count = 0;
  746. goto end;
  747. }
  748. edid.width_cm = (connector->display_info.width_mm) / 10;
  749. edid.height_cm = (connector->display_info.height_mm) / 10;
  750. dsi_drm_update_dtd(&edid, modes, count);
  751. dsi_drm_update_checksum(&edid);
  752. rc = drm_connector_update_edid_property(connector, &edid);
  753. if (rc)
  754. count = 0;
  755. /*
  756. * DRM EDID structure maintains panel physical dimensions in
  757. * centimeters, we will be losing the precision anything below cm.
  758. * Changing DRM framework will effect other clients at this
  759. * moment, overriding the values back to millimeter.
  760. */
  761. connector->display_info.width_mm = width_mm;
  762. connector->display_info.height_mm = height_mm;
  763. end:
  764. DSI_DEBUG("MODE COUNT =%d\n\n", count);
  765. return count;
  766. }
  767. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  768. struct drm_display_mode *mode,
  769. void *display, const struct msm_resource_caps_info *avail_res)
  770. {
  771. struct dsi_display_mode dsi_mode;
  772. int rc;
  773. if (!connector || !mode) {
  774. DSI_ERR("Invalid params\n");
  775. return MODE_ERROR;
  776. }
  777. convert_to_dsi_mode(mode, &dsi_mode);
  778. rc = dsi_display_validate_mode(display, &dsi_mode,
  779. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  780. if (rc) {
  781. DSI_ERR("mode not supported, rc=%d\n", rc);
  782. return MODE_BAD;
  783. }
  784. return MODE_OK;
  785. }
  786. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  787. void *display,
  788. struct msm_display_kickoff_params *params)
  789. {
  790. if (!connector || !display || !params) {
  791. DSI_ERR("Invalid params\n");
  792. return -EINVAL;
  793. }
  794. return dsi_display_pre_kickoff(connector, display, params);
  795. }
  796. int dsi_conn_prepare_commit(void *display,
  797. struct msm_display_conn_params *params)
  798. {
  799. if (!display || !params) {
  800. pr_err("Invalid params\n");
  801. return -EINVAL;
  802. }
  803. return dsi_display_pre_commit(display, params);
  804. }
  805. void dsi_conn_enable_event(struct drm_connector *connector,
  806. uint32_t event_idx, bool enable, void *display)
  807. {
  808. struct dsi_event_cb_info event_info;
  809. memset(&event_info, 0, sizeof(event_info));
  810. event_info.event_cb = sde_connector_trigger_event;
  811. event_info.event_usr_ptr = connector;
  812. dsi_display_enable_event(connector, display,
  813. event_idx, &event_info, enable);
  814. }
  815. int dsi_conn_post_kickoff(struct drm_connector *connector,
  816. struct msm_display_conn_params *params)
  817. {
  818. struct drm_encoder *encoder;
  819. struct dsi_bridge *c_bridge;
  820. struct dsi_display_mode adj_mode;
  821. struct dsi_display *display;
  822. struct dsi_display_ctrl *m_ctrl, *ctrl;
  823. int i, rc = 0;
  824. bool enable;
  825. if (!connector || !connector->state) {
  826. DSI_ERR("invalid connector or connector state\n");
  827. return -EINVAL;
  828. }
  829. encoder = connector->state->best_encoder;
  830. if (!encoder) {
  831. DSI_DEBUG("best encoder is not available\n");
  832. return 0;
  833. }
  834. c_bridge = to_dsi_bridge(encoder->bridge);
  835. adj_mode = c_bridge->dsi_mode;
  836. display = c_bridge->display;
  837. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  838. m_ctrl = &display->ctrl[display->clk_master_idx];
  839. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  840. if (rc) {
  841. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  842. display->name, rc);
  843. return -EINVAL;
  844. }
  845. /* Update the rest of the controllers */
  846. display_for_each_ctrl(i, display) {
  847. ctrl = &display->ctrl[i];
  848. if (!ctrl->ctrl || (ctrl == m_ctrl))
  849. continue;
  850. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  851. if (rc) {
  852. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  853. display->name, rc);
  854. return -EINVAL;
  855. }
  856. }
  857. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  858. }
  859. /* ensure dynamic clk switch flag is reset */
  860. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  861. if (params->qsync_update) {
  862. enable = (params->qsync_mode > 0) ? true : false;
  863. display_for_each_ctrl(i, display)
  864. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  865. }
  866. return 0;
  867. }
  868. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  869. struct drm_device *dev,
  870. struct drm_encoder *encoder)
  871. {
  872. int rc = 0;
  873. struct dsi_bridge *bridge;
  874. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  875. if (!bridge) {
  876. rc = -ENOMEM;
  877. goto error;
  878. }
  879. bridge->display = display;
  880. bridge->base.funcs = &dsi_bridge_ops;
  881. bridge->base.encoder = encoder;
  882. rc = drm_bridge_attach(encoder, &bridge->base, NULL);
  883. if (rc) {
  884. DSI_ERR("failed to attach bridge, rc=%d\n", rc);
  885. goto error_free_bridge;
  886. }
  887. encoder->bridge = &bridge->base;
  888. return bridge;
  889. error_free_bridge:
  890. kfree(bridge);
  891. error:
  892. return ERR_PTR(rc);
  893. }
  894. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  895. {
  896. if (bridge && bridge->base.encoder)
  897. bridge->base.encoder->bridge = NULL;
  898. kfree(bridge);
  899. }