ubwcp_hw.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #ifndef __UBWCP_HW_H_
  6. #define __UBWCP_HW_H_
  7. #define HW_BUFFER_FORMAT_RGBA 0x0
  8. #define HW_BUFFER_FORMAT_NV12 0x2
  9. #define HW_BUFFER_FORMAT_NV124R 0x4
  10. #define HW_BUFFER_FORMAT_P010 0x6
  11. #define HW_BUFFER_FORMAT_TP10 0x8
  12. #define HW_BUFFER_FORMAT_P016 0xA
  13. #define HW_BUFFER_FORMAT_LINEAR 0xF
  14. /* interrupt id. also bit location for set/clear */
  15. #define INTERRUPT_READ_ERROR 0
  16. #define INTERRUPT_WRITE_ERROR 1
  17. #define INTERRUPT_DECODE_ERROR 2
  18. #define INTERRUPT_ENCODE_ERROR 3
  19. /**
  20. * struct msm_ubwcp_- UBWCP hardware instance
  21. * dev:UBWCP device
  22. * irq:Interrupt number
  23. * clk:The bus clock for this IOMMU hardware instance
  24. * pclk:The clock for the IOMMU IOMMU bus interconnect
  25. */
  26. struct ubwcp_dev {
  27. void __iomem *base;
  28. struct device *dev;
  29. int irq;
  30. struct clk *clk;
  31. struct clk *pclk;
  32. /* TBD:
  33. * struct list_head dev_node;
  34. * struct list_head dom_node;
  35. * struct list_head ctx_list;
  36. * DECLARE_BITMAP(context_map, IOMMU_MAX_CBS)
  37. * struct iommu_device iommu;
  38. */
  39. };
  40. struct __packed ubwcp_hw_meta_metadata {
  41. u64 uv_start_addr : 48; /* uv start address */
  42. u16 format : 16; /* format */
  43. u16 stride; /* image stride (bytes) */
  44. u16 stride_ubwcp; /* p010 stride for tp10 image (bytes) */
  45. u32 metadata_base_y; /* 24-bit page address */
  46. u32 metadata_base_uv; /* 24-bit page address */
  47. u16 buffer_y_offset; /* 4KB offset from meta_data_base_y */
  48. u16 buffer_uv_offset; /* 4KB offset from meta_data_base_y */
  49. u32 width_height; /* image width (bytes) */
  50. };
  51. void ubwcp_hw_version(void __iomem *base, u32 *major, u32 *minor);
  52. void ubwcp_hw_set_buf_desc(void __iomem *base, u64 desc_addr, u16 desc_stride);
  53. void ubwcp_hw_enable_range_check(void __iomem *base, u16 index);
  54. int ubwcp_hw_disable_range_check_with_flush(void __iomem *base, u16 index);
  55. void ubwcp_hw_set_range_check(void __iomem *base, u16 index, phys_addr_t pa, size_t size);
  56. u64 ubwcp_hw_interrupt_src_address(void __iomem *base, u16 interrupt);
  57. void ubwcp_hw_interrupt_clear(void __iomem *base, u16 interrupt);
  58. void ubwcp_hw_interrupt_enable(void __iomem *base, u16 interrupt, bool enable);
  59. void ubwcp_hw_power_on(void __iomem *pwr_ctrl, bool power_on);
  60. void ubwcp_hw_one_time_init(void __iomem *base);
  61. int ubwcp_hw_flush(void __iomem *base);
  62. void ubwcp_hw_trace_set(bool value);
  63. void ubwcp_hw_trace_get(bool *value);
  64. #endif /* __UBWCP_HW_H_ */