dp_power.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/pm_runtime.h>
  8. #include "dp_power.h"
  9. #include "dp_catalog.h"
  10. #include "dp_debug.h"
  11. #include "dp_pll.h"
  12. #define DP_CLIENT_NAME_SIZE 20
  13. #define XO_CLK_KHZ 19200
  14. struct dp_power_private {
  15. struct dp_parser *parser;
  16. struct dp_pll *pll;
  17. struct platform_device *pdev;
  18. struct clk *pixel_clk_rcg;
  19. struct clk *pixel_parent;
  20. struct clk *pixel1_clk_rcg;
  21. struct clk *xo_clk;
  22. struct dp_power dp_power;
  23. bool core_clks_on;
  24. bool link_clks_on;
  25. bool strm0_clks_on;
  26. bool strm1_clks_on;
  27. bool strm0_clks_parked;
  28. bool strm1_clks_parked;
  29. };
  30. static int dp_power_regulator_init(struct dp_power_private *power)
  31. {
  32. int rc = 0, i = 0, j = 0;
  33. struct platform_device *pdev;
  34. struct dp_parser *parser;
  35. parser = power->parser;
  36. pdev = power->pdev;
  37. for (i = DP_CORE_PM; !rc && (i < DP_MAX_PM); i++) {
  38. rc = msm_dss_get_vreg(&pdev->dev,
  39. parser->mp[i].vreg_config,
  40. parser->mp[i].num_vreg, 1);
  41. if (rc) {
  42. DP_ERR("failed to init vregs for %s\n",
  43. dp_parser_pm_name(i));
  44. for (j = i - 1; j >= DP_CORE_PM; j--) {
  45. msm_dss_get_vreg(&pdev->dev,
  46. parser->mp[j].vreg_config,
  47. parser->mp[j].num_vreg, 0);
  48. }
  49. goto error;
  50. }
  51. }
  52. error:
  53. return rc;
  54. }
  55. static void dp_power_regulator_deinit(struct dp_power_private *power)
  56. {
  57. int rc = 0, i = 0;
  58. struct platform_device *pdev;
  59. struct dp_parser *parser;
  60. parser = power->parser;
  61. pdev = power->pdev;
  62. for (i = DP_CORE_PM; (i < DP_MAX_PM); i++) {
  63. rc = msm_dss_get_vreg(&pdev->dev,
  64. parser->mp[i].vreg_config,
  65. parser->mp[i].num_vreg, 0);
  66. if (rc)
  67. DP_ERR("failed to deinit vregs for %s\n",
  68. dp_parser_pm_name(i));
  69. }
  70. }
  71. static void dp_power_phy_gdsc(struct dp_power *dp_power, bool on)
  72. {
  73. int rc = 0;
  74. if (IS_ERR_OR_NULL(dp_power->dp_phy_gdsc))
  75. return;
  76. if (on)
  77. rc = regulator_enable(dp_power->dp_phy_gdsc);
  78. else
  79. rc = regulator_disable(dp_power->dp_phy_gdsc);
  80. if (rc)
  81. DP_ERR("Fail to %s dp_phy_gdsc regulator ret =%d\n",
  82. on ? "enable" : "disable", rc);
  83. }
  84. static int dp_power_regulator_ctrl(struct dp_power_private *power, bool enable)
  85. {
  86. int rc = 0, i = 0, j = 0;
  87. struct dp_parser *parser;
  88. parser = power->parser;
  89. for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
  90. /*
  91. * The DP_PLL_PM regulator is controlled by dp_display based
  92. * on the link configuration.
  93. */
  94. if (i == DP_PLL_PM) {
  95. /* DP GDSC vote is needed for new chipsets, define gdsc phandle if needed */
  96. dp_power_phy_gdsc(&power->dp_power, enable);
  97. DP_DEBUG("skipping: '%s' vregs for %s\n",
  98. enable ? "enable" : "disable",
  99. dp_parser_pm_name(i));
  100. continue;
  101. }
  102. rc = msm_dss_enable_vreg(
  103. parser->mp[i].vreg_config,
  104. parser->mp[i].num_vreg, enable);
  105. if (rc) {
  106. DP_ERR("failed to '%s' vregs for %s\n",
  107. enable ? "enable" : "disable",
  108. dp_parser_pm_name(i));
  109. if (enable) {
  110. for (j = i-1; j >= DP_CORE_PM; j--) {
  111. msm_dss_enable_vreg(
  112. parser->mp[j].vreg_config,
  113. parser->mp[j].num_vreg, 0);
  114. }
  115. }
  116. goto error;
  117. }
  118. }
  119. error:
  120. return rc;
  121. }
  122. static int dp_power_pinctrl_set(struct dp_power_private *power, bool active)
  123. {
  124. int rc = -EFAULT;
  125. struct pinctrl_state *pin_state;
  126. struct dp_parser *parser;
  127. parser = power->parser;
  128. if (IS_ERR_OR_NULL(parser->pinctrl.pin))
  129. return 0;
  130. pin_state = active ? parser->pinctrl.state_active
  131. : parser->pinctrl.state_suspend;
  132. if (!IS_ERR_OR_NULL(pin_state)) {
  133. rc = pinctrl_select_state(parser->pinctrl.pin,
  134. pin_state);
  135. if (rc)
  136. DP_ERR("can not set %s pins\n",
  137. active ? "dp_active"
  138. : "dp_sleep");
  139. } else {
  140. DP_ERR("invalid '%s' pinstate\n",
  141. active ? "dp_active"
  142. : "dp_sleep");
  143. }
  144. return rc;
  145. }
  146. static void dp_power_clk_put(struct dp_power_private *power)
  147. {
  148. enum dp_pm_type module;
  149. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  150. struct dss_module_power *pm = &power->parser->mp[module];
  151. if (!pm->num_clk)
  152. continue;
  153. msm_dss_mmrm_deregister(&power->pdev->dev, pm);
  154. msm_dss_put_clk(pm->clk_config, pm->num_clk);
  155. }
  156. }
  157. static int dp_power_clk_init(struct dp_power_private *power, bool enable)
  158. {
  159. int rc = 0;
  160. struct device *dev;
  161. enum dp_pm_type module;
  162. dev = &power->pdev->dev;
  163. if (enable) {
  164. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  165. struct dss_module_power *pm =
  166. &power->parser->mp[module];
  167. if (!pm->num_clk)
  168. continue;
  169. rc = msm_dss_get_clk(dev, pm->clk_config, pm->num_clk);
  170. if (rc) {
  171. DP_ERR("failed to get %s clk. err=%d\n",
  172. dp_parser_pm_name(module), rc);
  173. goto exit;
  174. }
  175. }
  176. power->pixel_clk_rcg = clk_get(dev, "pixel_clk_rcg");
  177. if (IS_ERR(power->pixel_clk_rcg)) {
  178. DP_ERR("Unable to get DP pixel clk RCG: %ld\n",
  179. PTR_ERR(power->pixel_clk_rcg));
  180. rc = PTR_ERR(power->pixel_clk_rcg);
  181. power->pixel_clk_rcg = NULL;
  182. goto err_pixel_clk_rcg;
  183. }
  184. power->pixel_parent = clk_get(dev, "pixel_parent");
  185. if (IS_ERR(power->pixel_parent)) {
  186. DP_ERR("Unable to get DP pixel RCG parent: %d\n",
  187. PTR_ERR(power->pixel_parent));
  188. rc = PTR_ERR(power->pixel_parent);
  189. power->pixel_parent = NULL;
  190. goto err_pixel_parent;
  191. }
  192. power->xo_clk = clk_get(dev, "rpmh_cxo_clk");
  193. if (IS_ERR(power->xo_clk)) {
  194. DP_ERR("Unable to get XO clk: %d\n", PTR_ERR(power->xo_clk));
  195. rc = PTR_ERR(power->xo_clk);
  196. power->xo_clk = NULL;
  197. goto err_xo_clk;
  198. }
  199. if (power->parser->has_mst) {
  200. power->pixel1_clk_rcg = clk_get(dev, "pixel1_clk_rcg");
  201. if (IS_ERR(power->pixel1_clk_rcg)) {
  202. DP_ERR("Unable to get DP pixel1 clk RCG: %d\n",
  203. PTR_ERR(power->pixel1_clk_rcg));
  204. rc = PTR_ERR(power->pixel1_clk_rcg);
  205. power->pixel1_clk_rcg = NULL;
  206. goto err_pixel1_clk_rcg;
  207. }
  208. }
  209. } else {
  210. if (power->pixel1_clk_rcg)
  211. clk_put(power->pixel1_clk_rcg);
  212. if (power->pixel_parent)
  213. clk_put(power->pixel_parent);
  214. if (power->pixel_clk_rcg)
  215. clk_put(power->pixel_clk_rcg);
  216. dp_power_clk_put(power);
  217. }
  218. return rc;
  219. err_pixel1_clk_rcg:
  220. clk_put(power->xo_clk);
  221. err_xo_clk:
  222. clk_put(power->pixel_parent);
  223. err_pixel_parent:
  224. clk_put(power->pixel_clk_rcg);
  225. err_pixel_clk_rcg:
  226. dp_power_clk_put(power);
  227. exit:
  228. return rc;
  229. }
  230. static int dp_power_park_module(struct dp_power_private *power, enum dp_pm_type module)
  231. {
  232. struct dss_module_power *mp;
  233. struct clk *clk = NULL;
  234. int rc = 0;
  235. bool *parked;
  236. mp = &power->parser->mp[module];
  237. if (module == DP_STREAM0_PM) {
  238. clk = power->pixel_clk_rcg;
  239. parked = &power->strm0_clks_parked;
  240. } else if (module == DP_STREAM1_PM) {
  241. clk = power->pixel1_clk_rcg;
  242. parked = &power->strm1_clks_parked;
  243. } else {
  244. goto exit;
  245. }
  246. if (!clk) {
  247. DP_WARN("clk type %d not supported\n", module);
  248. rc = -EINVAL;
  249. goto exit;
  250. }
  251. if (!power->xo_clk) {
  252. rc = -EINVAL;
  253. goto exit;
  254. }
  255. if (*parked)
  256. goto exit;
  257. rc = clk_set_parent(clk, power->xo_clk);
  258. if (rc) {
  259. DP_ERR("unable to set xo parent on clk %d\n", module);
  260. goto exit;
  261. }
  262. mp->clk_config->rate = XO_CLK_KHZ;
  263. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  264. if (rc) {
  265. DP_ERR("failed to set clk rate.\n");
  266. goto exit;
  267. }
  268. *parked = true;
  269. exit:
  270. return rc;
  271. }
  272. static int dp_power_clk_set_rate(struct dp_power_private *power,
  273. enum dp_pm_type module, bool enable)
  274. {
  275. int rc = 0;
  276. struct dss_module_power *mp;
  277. if (!power) {
  278. DP_ERR("invalid power data\n");
  279. rc = -EINVAL;
  280. goto exit;
  281. }
  282. mp = &power->parser->mp[module];
  283. if (enable) {
  284. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  285. if (rc) {
  286. DP_ERR("failed to set clks rate.\n");
  287. goto exit;
  288. }
  289. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 1);
  290. if (rc) {
  291. DP_ERR("failed to enable clks\n");
  292. goto exit;
  293. }
  294. } else {
  295. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, 0);
  296. if (rc) {
  297. DP_ERR("failed to disable clks\n");
  298. goto exit;
  299. }
  300. dp_power_park_module(power, module);
  301. }
  302. exit:
  303. return rc;
  304. }
  305. static int dp_power_clk_enable(struct dp_power *dp_power,
  306. enum dp_pm_type pm_type, bool enable)
  307. {
  308. int rc = 0;
  309. struct dss_module_power *mp;
  310. struct dp_power_private *power;
  311. if (!dp_power) {
  312. DP_ERR("invalid power data\n");
  313. rc = -EINVAL;
  314. goto error;
  315. }
  316. power = container_of(dp_power, struct dp_power_private, dp_power);
  317. mp = &power->parser->mp[pm_type];
  318. if (pm_type >= DP_MAX_PM) {
  319. DP_ERR("unsupported power module: %s\n",
  320. dp_parser_pm_name(pm_type));
  321. return -EINVAL;
  322. }
  323. if (enable) {
  324. if (pm_type == DP_CORE_PM && power->core_clks_on) {
  325. DP_DEBUG("core clks already enabled\n");
  326. return 0;
  327. }
  328. if ((pm_type == DP_STREAM0_PM) && (power->strm0_clks_on)) {
  329. DP_DEBUG("strm0 clks already enabled\n");
  330. return 0;
  331. }
  332. if ((pm_type == DP_STREAM1_PM) && (power->strm1_clks_on)) {
  333. DP_DEBUG("strm1 clks already enabled\n");
  334. return 0;
  335. }
  336. if ((pm_type == DP_CTRL_PM) && (!power->core_clks_on)) {
  337. DP_DEBUG("Need to enable core clks before link clks\n");
  338. rc = dp_power_clk_set_rate(power, pm_type, enable);
  339. if (rc) {
  340. DP_ERR("failed to enable clks: %s. err=%d\n",
  341. dp_parser_pm_name(DP_CORE_PM), rc);
  342. goto error;
  343. } else {
  344. power->core_clks_on = true;
  345. }
  346. }
  347. if (pm_type == DP_LINK_PM && power->link_clks_on) {
  348. DP_DEBUG("links clks already enabled\n");
  349. return 0;
  350. }
  351. }
  352. rc = dp_power_clk_set_rate(power, pm_type, enable);
  353. if (rc) {
  354. DP_ERR("failed to '%s' clks for: %s. err=%d\n",
  355. enable ? "enable" : "disable",
  356. dp_parser_pm_name(pm_type), rc);
  357. goto error;
  358. }
  359. if (pm_type == DP_CORE_PM)
  360. power->core_clks_on = enable;
  361. else if (pm_type == DP_STREAM0_PM)
  362. power->strm0_clks_on = enable;
  363. else if (pm_type == DP_STREAM1_PM)
  364. power->strm1_clks_on = enable;
  365. else if (pm_type == DP_LINK_PM)
  366. power->link_clks_on = enable;
  367. if (pm_type == DP_STREAM0_PM)
  368. power->strm0_clks_parked = false;
  369. if (pm_type == DP_STREAM1_PM)
  370. power->strm1_clks_parked = false;
  371. /*
  372. * This log is printed only when user connects or disconnects
  373. * a DP cable. As this is a user-action and not a frequent
  374. * usecase, it is not going to flood the kernel logs. Also,
  375. * helpful in debugging the NOC issues.
  376. */
  377. DP_INFO("core:%s link:%s strm0:%s strm1:%s\n",
  378. power->core_clks_on ? "on" : "off",
  379. power->link_clks_on ? "on" : "off",
  380. power->strm0_clks_on ? "on" : "off",
  381. power->strm1_clks_on ? "on" : "off");
  382. error:
  383. return rc;
  384. }
  385. static bool dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type)
  386. {
  387. struct dp_power_private *power;
  388. if (!dp_power) {
  389. DP_ERR("invalid power data\n");
  390. return false;
  391. }
  392. power = container_of(dp_power, struct dp_power_private, dp_power);
  393. if (pm_type == DP_LINK_PM)
  394. return power->link_clks_on;
  395. else if (pm_type == DP_CORE_PM)
  396. return power->core_clks_on;
  397. else if (pm_type == DP_STREAM0_PM)
  398. return power->strm0_clks_on;
  399. else if (pm_type == DP_STREAM1_PM)
  400. return power->strm1_clks_on;
  401. else
  402. return false;
  403. }
  404. static int dp_power_request_gpios(struct dp_power_private *power)
  405. {
  406. int rc = 0, i;
  407. struct device *dev;
  408. struct dss_module_power *mp;
  409. static const char * const gpio_names[] = {
  410. "aux_enable", "aux_sel", "usbplug_cc",
  411. };
  412. if (!power) {
  413. DP_ERR("invalid power data\n");
  414. return -EINVAL;
  415. }
  416. dev = &power->pdev->dev;
  417. mp = &power->parser->mp[DP_CORE_PM];
  418. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  419. unsigned int gpio = mp->gpio_config[i].gpio;
  420. if (gpio_is_valid(gpio)) {
  421. rc = gpio_request(gpio, gpio_names[i]);
  422. if (rc) {
  423. DP_ERR("request %s gpio failed, rc=%d\n",
  424. gpio_names[i], rc);
  425. goto error;
  426. }
  427. }
  428. }
  429. return 0;
  430. error:
  431. for (i = 0; i < ARRAY_SIZE(gpio_names); i++) {
  432. unsigned int gpio = mp->gpio_config[i].gpio;
  433. if (gpio_is_valid(gpio))
  434. gpio_free(gpio);
  435. }
  436. return rc;
  437. }
  438. static bool dp_power_find_gpio(const char *gpio1, const char *gpio2)
  439. {
  440. return !!strnstr(gpio1, gpio2, strlen(gpio1));
  441. }
  442. static void dp_power_set_gpio(struct dp_power_private *power, bool flip)
  443. {
  444. int i;
  445. struct dss_module_power *mp = &power->parser->mp[DP_CORE_PM];
  446. struct dss_gpio *config = mp->gpio_config;
  447. for (i = 0; i < mp->num_gpio; i++) {
  448. if (dp_power_find_gpio(config->gpio_name, "aux-sel"))
  449. config->value = flip;
  450. if (gpio_is_valid(config->gpio)) {
  451. DP_DEBUG("gpio %s, value %d\n", config->gpio_name,
  452. config->value);
  453. if (dp_power_find_gpio(config->gpio_name, "aux-en") ||
  454. dp_power_find_gpio(config->gpio_name, "aux-sel"))
  455. gpio_direction_output(config->gpio,
  456. config->value);
  457. else
  458. gpio_set_value(config->gpio, config->value);
  459. }
  460. config++;
  461. }
  462. }
  463. static int dp_power_config_gpios(struct dp_power_private *power, bool flip,
  464. bool enable)
  465. {
  466. int rc = 0, i;
  467. struct dss_module_power *mp;
  468. struct dss_gpio *config;
  469. mp = &power->parser->mp[DP_CORE_PM];
  470. config = mp->gpio_config;
  471. if (enable) {
  472. rc = dp_power_request_gpios(power);
  473. if (rc) {
  474. DP_ERR("gpio request failed\n");
  475. return rc;
  476. }
  477. dp_power_set_gpio(power, flip);
  478. } else {
  479. for (i = 0; i < mp->num_gpio; i++) {
  480. if (gpio_is_valid(config[i].gpio)) {
  481. gpio_set_value(config[i].gpio, 0);
  482. gpio_free(config[i].gpio);
  483. }
  484. }
  485. }
  486. return 0;
  487. }
  488. static int dp_power_mmrm_init(struct dp_power *dp_power, struct sde_power_handle *phandle, void *dp,
  489. int (*dp_display_mmrm_callback)(struct mmrm_client_notifier_data *notifier_data))
  490. {
  491. int rc = 0;
  492. enum dp_pm_type module;
  493. struct dp_power_private *power = container_of(dp_power, struct dp_power_private, dp_power);
  494. struct device *dev = &power->pdev->dev;
  495. for (module = DP_CORE_PM; module < DP_MAX_PM; module++) {
  496. struct dss_module_power *pm = &power->parser->mp[module];
  497. if (!pm->num_clk)
  498. continue;
  499. rc = msm_dss_mmrm_register(dev, pm, dp_display_mmrm_callback,
  500. dp, &phandle->mmrm_enable);
  501. if (rc)
  502. DP_ERR("mmrm register failed rc=%d\n", rc);
  503. }
  504. return rc;
  505. }
  506. static int dp_power_client_init(struct dp_power *dp_power,
  507. struct sde_power_handle *phandle, struct drm_device *drm_dev)
  508. {
  509. int rc = 0;
  510. struct dp_power_private *power;
  511. if (!drm_dev) {
  512. DP_ERR("invalid drm_dev\n");
  513. return -EINVAL;
  514. }
  515. power = container_of(dp_power, struct dp_power_private, dp_power);
  516. rc = dp_power_regulator_init(power);
  517. if (rc) {
  518. DP_ERR("failed to init regulators\n");
  519. goto error_power;
  520. }
  521. rc = dp_power_clk_init(power, true);
  522. if (rc) {
  523. DP_ERR("failed to init clocks\n");
  524. goto error_clk;
  525. }
  526. dp_power->phandle = phandle;
  527. dp_power->drm_dev = drm_dev;
  528. return 0;
  529. error_clk:
  530. dp_power_regulator_deinit(power);
  531. error_power:
  532. return rc;
  533. }
  534. static void dp_power_client_deinit(struct dp_power *dp_power)
  535. {
  536. struct dp_power_private *power;
  537. if (!dp_power) {
  538. DP_ERR("invalid power data\n");
  539. return;
  540. }
  541. power = container_of(dp_power, struct dp_power_private, dp_power);
  542. dp_power_clk_init(power, false);
  543. dp_power_regulator_deinit(power);
  544. }
  545. static int dp_power_park_clocks(struct dp_power *dp_power)
  546. {
  547. int rc = 0;
  548. struct dp_power_private *power;
  549. if (!dp_power) {
  550. DP_ERR("invalid power data\n");
  551. return -EINVAL;
  552. }
  553. power = container_of(dp_power, struct dp_power_private, dp_power);
  554. rc = dp_power_park_module(power, DP_STREAM0_PM);
  555. if (rc) {
  556. DP_ERR("failed to park stream 0. err=%d\n", rc);
  557. goto error;
  558. }
  559. rc = dp_power_park_module(power, DP_STREAM1_PM);
  560. if (rc) {
  561. DP_ERR("failed to park stream 1. err=%d\n", rc);
  562. goto error;
  563. }
  564. error:
  565. return rc;
  566. }
  567. static int dp_power_set_pixel_clk_parent(struct dp_power *dp_power, u32 strm_id)
  568. {
  569. int rc = 0;
  570. struct dp_power_private *power;
  571. if (!dp_power || strm_id >= DP_STREAM_MAX) {
  572. DP_ERR("invalid power data. stream %d\n", strm_id);
  573. rc = -EINVAL;
  574. goto exit;
  575. }
  576. power = container_of(dp_power, struct dp_power_private, dp_power);
  577. if (strm_id == DP_STREAM_0) {
  578. if (power->pixel_clk_rcg && power->pixel_parent)
  579. rc = clk_set_parent(power->pixel_clk_rcg,
  580. power->pixel_parent);
  581. else
  582. DP_WARN("skipped for strm_id=%d\n", strm_id);
  583. } else if (strm_id == DP_STREAM_1) {
  584. if (power->pixel1_clk_rcg && power->pixel_parent)
  585. rc = clk_set_parent(power->pixel1_clk_rcg,
  586. power->pixel_parent);
  587. else
  588. DP_WARN("skipped for strm_id=%d\n", strm_id);
  589. }
  590. if (rc)
  591. DP_ERR("failed. strm_id=%d, rc=%d\n", strm_id, rc);
  592. exit:
  593. return rc;
  594. }
  595. static u64 dp_power_clk_get_rate(struct dp_power *dp_power, char *clk_name)
  596. {
  597. size_t i;
  598. enum dp_pm_type j;
  599. struct dss_module_power *mp;
  600. struct dp_power_private *power;
  601. bool clk_found = false;
  602. u64 rate = 0;
  603. if (!clk_name) {
  604. DP_ERR("invalid pointer for clk_name\n");
  605. return 0;
  606. }
  607. power = container_of(dp_power, struct dp_power_private, dp_power);
  608. mp = &dp_power->phandle->mp;
  609. for (i = 0; i < mp->num_clk; i++) {
  610. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  611. rate = clk_get_rate(mp->clk_config[i].clk);
  612. clk_found = true;
  613. break;
  614. }
  615. }
  616. for (j = DP_CORE_PM; j < DP_MAX_PM && !clk_found; j++) {
  617. mp = &power->parser->mp[j];
  618. for (i = 0; i < mp->num_clk; i++) {
  619. if (!strcmp(mp->clk_config[i].clk_name, clk_name)) {
  620. rate = clk_get_rate(mp->clk_config[i].clk);
  621. clk_found = true;
  622. break;
  623. }
  624. }
  625. }
  626. return rate;
  627. }
  628. static int dp_power_init(struct dp_power *dp_power, bool flip)
  629. {
  630. int rc = 0;
  631. struct dp_power_private *power;
  632. if (!dp_power) {
  633. DP_ERR("invalid power data\n");
  634. rc = -EINVAL;
  635. goto exit;
  636. }
  637. power = container_of(dp_power, struct dp_power_private, dp_power);
  638. rc = dp_power_regulator_ctrl(power, true);
  639. if (rc) {
  640. DP_ERR("failed to enable regulators\n");
  641. goto exit;
  642. }
  643. rc = dp_power_pinctrl_set(power, true);
  644. if (rc) {
  645. DP_ERR("failed to set pinctrl state\n");
  646. goto err_pinctrl;
  647. }
  648. rc = dp_power_config_gpios(power, flip, true);
  649. if (rc) {
  650. DP_ERR("failed to enable gpios\n");
  651. goto err_gpio;
  652. }
  653. rc = pm_runtime_resume_and_get(dp_power->drm_dev->dev);
  654. if (rc < 0) {
  655. DP_ERR("failed to enable power resource %d\n", rc);
  656. goto err_sde_power;
  657. }
  658. rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
  659. if (rc) {
  660. DP_ERR("failed to enable DP core clocks\n");
  661. goto err_clk;
  662. }
  663. return 0;
  664. err_clk:
  665. pm_runtime_put_sync(dp_power->drm_dev->dev);
  666. err_sde_power:
  667. dp_power_config_gpios(power, flip, false);
  668. err_gpio:
  669. dp_power_pinctrl_set(power, false);
  670. err_pinctrl:
  671. dp_power_regulator_ctrl(power, false);
  672. exit:
  673. return rc;
  674. }
  675. static int dp_power_deinit(struct dp_power *dp_power)
  676. {
  677. int rc = 0;
  678. struct dp_power_private *power;
  679. if (!dp_power) {
  680. DP_ERR("invalid power data\n");
  681. rc = -EINVAL;
  682. goto exit;
  683. }
  684. power = container_of(dp_power, struct dp_power_private, dp_power);
  685. if (power->link_clks_on)
  686. dp_power_clk_enable(dp_power, DP_LINK_PM, false);
  687. dp_power_clk_enable(dp_power, DP_CORE_PM, false);
  688. pm_runtime_put_sync(dp_power->drm_dev->dev);
  689. dp_power_config_gpios(power, false, false);
  690. dp_power_pinctrl_set(power, false);
  691. dp_power_regulator_ctrl(power, false);
  692. exit:
  693. return rc;
  694. }
  695. struct dp_power *dp_power_get(struct dp_parser *parser, struct dp_pll *pll)
  696. {
  697. int rc = 0;
  698. struct dp_power_private *power;
  699. struct dp_power *dp_power;
  700. struct device *dev;
  701. if (!parser || !pll) {
  702. DP_ERR("invalid input\n");
  703. rc = -EINVAL;
  704. goto error;
  705. }
  706. power = kzalloc(sizeof(*power), GFP_KERNEL);
  707. if (!power) {
  708. rc = -ENOMEM;
  709. goto error;
  710. }
  711. power->parser = parser;
  712. power->pll = pll;
  713. power->pdev = parser->pdev;
  714. dp_power = &power->dp_power;
  715. dev = &power->pdev->dev;
  716. dp_power->init = dp_power_init;
  717. dp_power->deinit = dp_power_deinit;
  718. dp_power->clk_enable = dp_power_clk_enable;
  719. dp_power->clk_status = dp_power_clk_status;
  720. dp_power->set_pixel_clk_parent = dp_power_set_pixel_clk_parent;
  721. dp_power->park_clocks = dp_power_park_clocks;
  722. dp_power->clk_get_rate = dp_power_clk_get_rate;
  723. dp_power->power_client_init = dp_power_client_init;
  724. dp_power->power_client_deinit = dp_power_client_deinit;
  725. dp_power->power_mmrm_init = dp_power_mmrm_init;
  726. dp_power->dp_phy_gdsc = devm_regulator_get(dev, "dp_phy_gdsc");
  727. if (IS_ERR(dp_power->dp_phy_gdsc)) {
  728. dp_power->dp_phy_gdsc = NULL;
  729. DP_DEBUG("Optional GDSC regulator is missing\n");
  730. }
  731. return dp_power;
  732. error:
  733. return ERR_PTR(rc);
  734. }
  735. void dp_power_put(struct dp_power *dp_power)
  736. {
  737. struct dp_power_private *power = NULL;
  738. if (!dp_power)
  739. return;
  740. power = container_of(dp_power, struct dp_power_private, dp_power);
  741. kfree(power);
  742. }