dp_catalog.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/iopoll.h>
  8. #include "dp_catalog.h"
  9. #include "dp_reg.h"
  10. #include "dp_debug.h"
  11. #include "dp_link.h"
  12. #define DP_GET_MSB(x) (x >> 8)
  13. #define DP_GET_LSB(x) (x & 0xff)
  14. #define DP_PHY_READY BIT(1)
  15. #define dp_catalog_get_priv(x) ({ \
  16. struct dp_catalog *dp_catalog; \
  17. dp_catalog = container_of(x, struct dp_catalog, x); \
  18. container_of(dp_catalog, struct dp_catalog_private, \
  19. dp_catalog); \
  20. })
  21. #define DP_INTERRUPT_STATUS1 \
  22. (DP_INTR_AUX_I2C_DONE| \
  23. DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
  24. DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \
  25. DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \
  26. DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR)
  27. #define DP_INTR_MASK1 (DP_INTERRUPT_STATUS1 << 2)
  28. #define DP_INTERRUPT_STATUS2 \
  29. (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \
  30. DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED)
  31. #define DP_INTR_MASK2 (DP_INTERRUPT_STATUS2 << 2)
  32. #define DP_INTERRUPT_STATUS5 \
  33. (DP_INTR_MST_DP0_VCPF_SENT | DP_INTR_MST_DP1_VCPF_SENT)
  34. #define DP_INTR_MASK5 (DP_INTERRUPT_STATUS5 << 2)
  35. #define DP_TPG_PATTERN_MAX 9
  36. #define DP_TPG_PATTERN_DEFAULT 8
  37. #define dp_catalog_fill_io(x) { \
  38. catalog->io.x = parser->get_io(parser, #x); \
  39. }
  40. #define dp_catalog_fill_io_buf(x) { \
  41. parser->get_io_buf(parser, #x); \
  42. }
  43. #define dp_read(x) ({ \
  44. catalog->read(catalog, io_data, x); \
  45. })
  46. #define dp_write(x, y) ({ \
  47. catalog->write(catalog, io_data, x, y); \
  48. })
  49. static u8 const vm_pre_emphasis[4][4] = {
  50. {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */
  51. {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */
  52. {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */
  53. {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
  54. };
  55. /* voltage swing, 0.2v and 1.0v are not support */
  56. static u8 const vm_voltage_swing[4][4] = {
  57. {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */
  58. {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */
  59. {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */
  60. {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */
  61. };
  62. static u8 const vm_pre_emphasis_hbr3_hbr2[4][4] = {
  63. {0x00, 0x0C, 0x15, 0x1A},
  64. {0x02, 0x0E, 0x16, 0xFF},
  65. {0x02, 0x11, 0xFF, 0xFF},
  66. {0x04, 0xFF, 0xFF, 0xFF}
  67. };
  68. static u8 const vm_voltage_swing_hbr3_hbr2[4][4] = {
  69. {0x02, 0x12, 0x16, 0x1A},
  70. {0x09, 0x19, 0x1F, 0xFF},
  71. {0x10, 0x1F, 0xFF, 0xFF},
  72. {0x1F, 0xFF, 0xFF, 0xFF}
  73. };
  74. static u8 const vm_pre_emphasis_hbr_rbr[4][4] = {
  75. {0x00, 0x0C, 0x14, 0x19},
  76. {0x00, 0x0B, 0x12, 0xFF},
  77. {0x00, 0x0B, 0xFF, 0xFF},
  78. {0x04, 0xFF, 0xFF, 0xFF}
  79. };
  80. static u8 const vm_voltage_swing_hbr_rbr[4][4] = {
  81. {0x08, 0x0F, 0x16, 0x1F},
  82. {0x11, 0x1E, 0x1F, 0xFF},
  83. {0x19, 0x1F, 0xFF, 0xFF},
  84. {0x1F, 0xFF, 0xFF, 0xFF}
  85. };
  86. enum dp_flush_bit {
  87. DP_PPS_FLUSH,
  88. DP_DHDR_FLUSH,
  89. };
  90. /* audio related catalog functions */
  91. struct dp_catalog_private {
  92. struct device *dev;
  93. struct dp_catalog_io io;
  94. struct dp_parser *parser;
  95. u32 (*read)(struct dp_catalog_private *catalog,
  96. struct dp_io_data *io_data, u32 offset);
  97. void (*write)(struct dp_catalog_private *catlog,
  98. struct dp_io_data *io_data, u32 offset, u32 data);
  99. u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
  100. struct dp_catalog dp_catalog;
  101. char exe_mode[SZ_4];
  102. u32 dp_core_version;
  103. u32 dp_phy_version;
  104. };
  105. static u32 dp_read_sw(struct dp_catalog_private *catalog,
  106. struct dp_io_data *io_data, u32 offset)
  107. {
  108. u32 data = 0;
  109. if (io_data->buf)
  110. memcpy(&data, io_data->buf + offset, sizeof(offset));
  111. return data;
  112. }
  113. static void dp_write_sw(struct dp_catalog_private *catalog,
  114. struct dp_io_data *io_data, u32 offset, u32 data)
  115. {
  116. if (io_data->buf)
  117. memcpy(io_data->buf + offset, &data, sizeof(data));
  118. }
  119. static u32 dp_read_hw(struct dp_catalog_private *catalog,
  120. struct dp_io_data *io_data, u32 offset)
  121. {
  122. u32 data = 0;
  123. data = readl_relaxed(io_data->io.base + offset);
  124. return data;
  125. }
  126. static void dp_write_hw(struct dp_catalog_private *catalog,
  127. struct dp_io_data *io_data, u32 offset, u32 data)
  128. {
  129. writel_relaxed(data, io_data->io.base + offset);
  130. }
  131. static u32 dp_read_sub_sw(struct dp_catalog *dp_catalog,
  132. struct dp_io_data *io_data, u32 offset)
  133. {
  134. struct dp_catalog_private *catalog = container_of(dp_catalog,
  135. struct dp_catalog_private, dp_catalog);
  136. return dp_read_sw(catalog, io_data, offset);
  137. }
  138. static void dp_write_sub_sw(struct dp_catalog *dp_catalog,
  139. struct dp_io_data *io_data, u32 offset, u32 data)
  140. {
  141. struct dp_catalog_private *catalog = container_of(dp_catalog,
  142. struct dp_catalog_private, dp_catalog);
  143. dp_write_sw(catalog, io_data, offset, data);
  144. }
  145. static u32 dp_read_sub_hw(struct dp_catalog *dp_catalog,
  146. struct dp_io_data *io_data, u32 offset)
  147. {
  148. struct dp_catalog_private *catalog = container_of(dp_catalog,
  149. struct dp_catalog_private, dp_catalog);
  150. return dp_read_hw(catalog, io_data, offset);
  151. }
  152. static void dp_write_sub_hw(struct dp_catalog *dp_catalog,
  153. struct dp_io_data *io_data, u32 offset, u32 data)
  154. {
  155. struct dp_catalog_private *catalog = container_of(dp_catalog,
  156. struct dp_catalog_private, dp_catalog);
  157. dp_write_hw(catalog, io_data, offset, data);
  158. }
  159. /* aux related catalog functions */
  160. static u32 dp_catalog_aux_read_data(struct dp_catalog_aux *aux)
  161. {
  162. struct dp_catalog_private *catalog;
  163. struct dp_io_data *io_data;
  164. if (!aux) {
  165. DP_ERR("invalid input\n");
  166. goto end;
  167. }
  168. catalog = dp_catalog_get_priv(aux);
  169. io_data = catalog->io.dp_aux;
  170. return dp_read(DP_AUX_DATA);
  171. end:
  172. return 0;
  173. }
  174. static int dp_catalog_aux_write_data(struct dp_catalog_aux *aux)
  175. {
  176. int rc = 0;
  177. struct dp_catalog_private *catalog;
  178. struct dp_io_data *io_data;
  179. if (!aux) {
  180. DP_ERR("invalid input\n");
  181. rc = -EINVAL;
  182. goto end;
  183. }
  184. catalog = dp_catalog_get_priv(aux);
  185. io_data = catalog->io.dp_aux;
  186. dp_write(DP_AUX_DATA, aux->data);
  187. end:
  188. return rc;
  189. }
  190. static int dp_catalog_aux_write_trans(struct dp_catalog_aux *aux)
  191. {
  192. int rc = 0;
  193. struct dp_catalog_private *catalog;
  194. struct dp_io_data *io_data;
  195. if (!aux) {
  196. DP_ERR("invalid input\n");
  197. rc = -EINVAL;
  198. goto end;
  199. }
  200. catalog = dp_catalog_get_priv(aux);
  201. io_data = catalog->io.dp_aux;
  202. dp_write(DP_AUX_TRANS_CTRL, aux->data);
  203. end:
  204. return rc;
  205. }
  206. static int dp_catalog_aux_clear_trans(struct dp_catalog_aux *aux, bool read)
  207. {
  208. int rc = 0;
  209. u32 data = 0;
  210. struct dp_catalog_private *catalog;
  211. struct dp_io_data *io_data;
  212. if (!aux) {
  213. DP_ERR("invalid input\n");
  214. rc = -EINVAL;
  215. goto end;
  216. }
  217. catalog = dp_catalog_get_priv(aux);
  218. io_data = catalog->io.dp_aux;
  219. if (read) {
  220. data = dp_read(DP_AUX_TRANS_CTRL);
  221. data &= ~BIT(9);
  222. dp_write(DP_AUX_TRANS_CTRL, data);
  223. } else {
  224. dp_write(DP_AUX_TRANS_CTRL, 0);
  225. }
  226. end:
  227. return rc;
  228. }
  229. static void dp_catalog_aux_clear_hw_interrupts(struct dp_catalog_aux *aux)
  230. {
  231. struct dp_catalog_private *catalog;
  232. struct dp_io_data *io_data;
  233. u32 data = 0;
  234. if (!aux) {
  235. DP_ERR("invalid input\n");
  236. return;
  237. }
  238. catalog = dp_catalog_get_priv(aux);
  239. io_data = catalog->io.dp_phy;
  240. data = dp_read(DP_PHY_AUX_INTERRUPT_STATUS);
  241. dp_write(DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f);
  242. wmb(); /* make sure 0x1f is written before next write */
  243. dp_write(DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f);
  244. wmb(); /* make sure 0x9f is written before next write */
  245. dp_write(DP_PHY_AUX_INTERRUPT_CLEAR, 0);
  246. wmb(); /* make sure register is cleared */
  247. }
  248. static void dp_catalog_aux_reset(struct dp_catalog_aux *aux)
  249. {
  250. u32 aux_ctrl;
  251. struct dp_catalog_private *catalog;
  252. struct dp_io_data *io_data;
  253. if (!aux) {
  254. DP_ERR("invalid input\n");
  255. return;
  256. }
  257. catalog = dp_catalog_get_priv(aux);
  258. io_data = catalog->io.dp_aux;
  259. aux_ctrl = dp_read(DP_AUX_CTRL);
  260. aux_ctrl |= BIT(1);
  261. dp_write(DP_AUX_CTRL, aux_ctrl);
  262. usleep_range(1000, 1010); /* h/w recommended delay */
  263. aux_ctrl &= ~BIT(1);
  264. dp_write(DP_AUX_CTRL, aux_ctrl);
  265. wmb(); /* make sure AUX reset is done here */
  266. }
  267. static void dp_catalog_aux_enable(struct dp_catalog_aux *aux, bool enable)
  268. {
  269. u32 aux_ctrl;
  270. struct dp_catalog_private *catalog;
  271. struct dp_io_data *io_data;
  272. if (!aux) {
  273. DP_ERR("invalid input\n");
  274. return;
  275. }
  276. catalog = dp_catalog_get_priv(aux);
  277. io_data = catalog->io.dp_aux;
  278. aux_ctrl = dp_read(DP_AUX_CTRL);
  279. if (enable) {
  280. aux_ctrl |= BIT(0);
  281. dp_write(DP_AUX_CTRL, aux_ctrl);
  282. wmb(); /* make sure AUX module is enabled */
  283. dp_write(DP_TIMEOUT_COUNT, 0xffff);
  284. dp_write(DP_AUX_LIMITS, 0xffff);
  285. } else {
  286. aux_ctrl &= ~BIT(0);
  287. dp_write(DP_AUX_CTRL, aux_ctrl);
  288. }
  289. }
  290. static void dp_catalog_aux_update_cfg(struct dp_catalog_aux *aux,
  291. struct dp_aux_cfg *cfg, enum dp_phy_aux_config_type type)
  292. {
  293. struct dp_catalog_private *catalog;
  294. u32 new_index = 0, current_index = 0;
  295. struct dp_io_data *io_data;
  296. if (!aux || !cfg || (type >= PHY_AUX_CFG_MAX)) {
  297. DP_ERR("invalid input\n");
  298. return;
  299. }
  300. catalog = dp_catalog_get_priv(aux);
  301. io_data = catalog->io.dp_phy;
  302. current_index = cfg[type].current_index;
  303. new_index = (current_index + 1) % cfg[type].cfg_cnt;
  304. DP_DEBUG("Updating %s from 0x%08x to 0x%08x\n",
  305. dp_phy_aux_config_type_to_string(type),
  306. cfg[type].lut[current_index], cfg[type].lut[new_index]);
  307. dp_write(cfg[type].offset, cfg[type].lut[new_index]);
  308. cfg[type].current_index = new_index;
  309. }
  310. static void dp_catalog_aux_setup(struct dp_catalog_aux *aux,
  311. struct dp_aux_cfg *cfg)
  312. {
  313. struct dp_catalog_private *catalog;
  314. struct dp_io_data *io_data;
  315. int i = 0;
  316. if (!aux || !cfg) {
  317. DP_ERR("invalid input\n");
  318. return;
  319. }
  320. catalog = dp_catalog_get_priv(aux);
  321. io_data = catalog->io.dp_phy;
  322. dp_write(DP_PHY_PD_CTL, 0x65);
  323. wmb(); /* make sure PD programming happened */
  324. /* Turn on BIAS current for PHY/PLL */
  325. io_data = catalog->io.dp_pll;
  326. dp_write(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1b);
  327. io_data = catalog->io.dp_phy;
  328. dp_write(DP_PHY_PD_CTL, 0x02);
  329. wmb(); /* make sure PD programming happened */
  330. dp_write(DP_PHY_PD_CTL, 0x7d);
  331. /* Turn on BIAS current for PHY/PLL */
  332. io_data = catalog->io.dp_pll;
  333. dp_write(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f);
  334. /* DP AUX CFG register programming */
  335. io_data = catalog->io.dp_phy;
  336. for (i = 0; i < PHY_AUX_CFG_MAX; i++)
  337. dp_write(cfg[i].offset, cfg[i].lut[cfg[i].current_index]);
  338. dp_write(DP_PHY_AUX_INTERRUPT_MASK, 0x1F);
  339. wmb(); /* make sure AUX configuration is done before enabling it */
  340. }
  341. static void dp_catalog_aux_get_irq(struct dp_catalog_aux *aux, bool cmd_busy)
  342. {
  343. u32 ack;
  344. struct dp_catalog_private *catalog;
  345. struct dp_io_data *io_data;
  346. if (!aux) {
  347. DP_ERR("invalid input\n");
  348. return;
  349. }
  350. catalog = dp_catalog_get_priv(aux);
  351. io_data = catalog->io.dp_ahb;
  352. aux->isr = dp_read(DP_INTR_STATUS);
  353. aux->isr &= ~DP_INTR_MASK1;
  354. ack = aux->isr & DP_INTERRUPT_STATUS1;
  355. ack <<= 1;
  356. ack |= DP_INTR_MASK1;
  357. dp_write(DP_INTR_STATUS, ack);
  358. }
  359. static bool dp_catalog_ctrl_wait_for_phy_ready(
  360. struct dp_catalog_private *catalog)
  361. {
  362. u32 phy_version;
  363. u32 reg, state;
  364. void __iomem *base = catalog->io.dp_phy->io.base;
  365. bool success = true;
  366. u32 const poll_sleep_us = 500;
  367. u32 const pll_timeout_us = 10000;
  368. phy_version = dp_catalog_get_dp_phy_version(&catalog->dp_catalog);
  369. if (phy_version >= 0x60000000) {
  370. reg = DP_PHY_STATUS_V600;
  371. } else {
  372. reg = DP_PHY_STATUS;
  373. }
  374. if (readl_poll_timeout_atomic((base + reg), state,
  375. ((state & DP_PHY_READY) > 0),
  376. poll_sleep_us, pll_timeout_us)) {
  377. DP_ERR("PHY status failed, status=%x\n", state);
  378. success = false;
  379. }
  380. return success;
  381. }
  382. /* controller related catalog functions */
  383. static int dp_catalog_ctrl_late_phy_init(struct dp_catalog_ctrl *ctrl,
  384. u8 lane_cnt, bool flipped)
  385. {
  386. int rc = 0;
  387. u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
  388. struct dp_catalog_private *catalog;
  389. struct dp_io_data *io_data;
  390. if (!ctrl) {
  391. DP_ERR("invalid input\n");
  392. return -EINVAL;
  393. }
  394. catalog = dp_catalog_get_priv(ctrl);
  395. switch (lane_cnt) {
  396. case 1:
  397. drvr0_en = flipped ? 0x13 : 0x10;
  398. bias0_en = flipped ? 0x3E : 0x15;
  399. drvr1_en = flipped ? 0x10 : 0x13;
  400. bias1_en = flipped ? 0x15 : 0x3E;
  401. break;
  402. case 2:
  403. drvr0_en = flipped ? 0x10 : 0x10;
  404. bias0_en = flipped ? 0x3F : 0x15;
  405. drvr1_en = flipped ? 0x10 : 0x10;
  406. bias1_en = flipped ? 0x15 : 0x3F;
  407. break;
  408. case 4:
  409. default:
  410. drvr0_en = 0x10;
  411. bias0_en = 0x3F;
  412. drvr1_en = 0x10;
  413. bias1_en = 0x3F;
  414. break;
  415. }
  416. io_data = catalog->io.dp_ln_tx0;
  417. dp_write(TXn_HIGHZ_DRVR_EN_V420, drvr0_en);
  418. dp_write(TXn_TRANSCEIVER_BIAS_EN_V420, bias0_en);
  419. io_data = catalog->io.dp_ln_tx1;
  420. dp_write(TXn_HIGHZ_DRVR_EN_V420, drvr1_en);
  421. dp_write(TXn_TRANSCEIVER_BIAS_EN_V420, bias1_en);
  422. io_data = catalog->io.dp_phy;
  423. dp_write(DP_PHY_CFG, 0x18);
  424. /* add hardware recommended delay */
  425. udelay(2000);
  426. dp_write(DP_PHY_CFG, 0x19);
  427. /*
  428. * Make sure all the register writes are completed before
  429. * doing any other operation
  430. */
  431. wmb();
  432. if (!dp_catalog_ctrl_wait_for_phy_ready(catalog)) {
  433. rc = -EINVAL;
  434. goto lock_err;
  435. }
  436. io_data = catalog->io.dp_ln_tx0;
  437. dp_write(TXn_TX_POL_INV_V420, 0x0a);
  438. io_data = catalog->io.dp_ln_tx1;
  439. dp_write(TXn_TX_POL_INV_V420, 0x0a);
  440. io_data = catalog->io.dp_ln_tx0;
  441. dp_write(TXn_TX_DRV_LVL_V420, 0x27);
  442. io_data = catalog->io.dp_ln_tx1;
  443. dp_write(TXn_TX_DRV_LVL_V420, 0x27);
  444. io_data = catalog->io.dp_ln_tx0;
  445. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  446. io_data = catalog->io.dp_ln_tx1;
  447. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  448. /* Make sure the PHY register writes are done */
  449. wmb();
  450. lock_err:
  451. return rc;
  452. }
  453. static u32 dp_catalog_ctrl_read_hdcp_status(struct dp_catalog_ctrl *ctrl)
  454. {
  455. struct dp_catalog_private *catalog;
  456. struct dp_io_data *io_data;
  457. if (!ctrl) {
  458. DP_ERR("invalid input\n");
  459. return -EINVAL;
  460. }
  461. catalog = dp_catalog_get_priv(ctrl);
  462. io_data = catalog->io.dp_ahb;
  463. return dp_read(DP_HDCP_STATUS);
  464. }
  465. static void dp_catalog_panel_sdp_update(struct dp_catalog_panel *panel)
  466. {
  467. struct dp_catalog_private *catalog;
  468. struct dp_io_data *io_data;
  469. u32 sdp_cfg3_off = 0;
  470. if (panel->stream_id >= DP_STREAM_MAX) {
  471. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  472. return;
  473. }
  474. if (panel->stream_id == DP_STREAM_1)
  475. sdp_cfg3_off = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3;
  476. catalog = dp_catalog_get_priv(panel);
  477. io_data = catalog->io.dp_link;
  478. dp_write(MMSS_DP_SDP_CFG3 + sdp_cfg3_off, 0x01);
  479. dp_write(MMSS_DP_SDP_CFG3 + sdp_cfg3_off, 0x00);
  480. }
  481. static void dp_catalog_panel_setup_vsif_infoframe_sdp(
  482. struct dp_catalog_panel *panel)
  483. {
  484. struct dp_catalog_private *catalog;
  485. struct drm_msm_ext_hdr_metadata *hdr;
  486. struct dp_io_data *io_data;
  487. u32 header, parity, data, mst_offset = 0;
  488. u8 buf[SZ_64], off = 0;
  489. if (panel->stream_id >= DP_STREAM_MAX) {
  490. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  491. return;
  492. }
  493. if (panel->stream_id == DP_STREAM_1)
  494. mst_offset = MMSS_DP1_VSCEXT_0 - MMSS_DP_VSCEXT_0;
  495. catalog = dp_catalog_get_priv(panel);
  496. hdr = &panel->hdr_meta;
  497. io_data = catalog->io.dp_link;
  498. /* HEADER BYTE 1 */
  499. header = panel->dhdr_vsif_sdp.HB1;
  500. parity = dp_header_get_parity(header);
  501. data = ((header << HEADER_BYTE_1_BIT)
  502. | (parity << PARITY_BYTE_1_BIT));
  503. dp_write(MMSS_DP_VSCEXT_0 + mst_offset, data);
  504. memcpy(buf + off, &data, sizeof(data));
  505. off += sizeof(data);
  506. /* HEADER BYTE 2 */
  507. header = panel->dhdr_vsif_sdp.HB2;
  508. parity = dp_header_get_parity(header);
  509. data = ((header << HEADER_BYTE_2_BIT)
  510. | (parity << PARITY_BYTE_2_BIT));
  511. dp_write(MMSS_DP_VSCEXT_1 + mst_offset, data);
  512. /* HEADER BYTE 3 */
  513. header = panel->dhdr_vsif_sdp.HB3;
  514. parity = dp_header_get_parity(header);
  515. data = ((header << HEADER_BYTE_3_BIT)
  516. | (parity << PARITY_BYTE_3_BIT));
  517. data |= dp_read(MMSS_DP_VSCEXT_1 + mst_offset);
  518. dp_write(MMSS_DP_VSCEXT_1 + mst_offset, data);
  519. memcpy(buf + off, &data, sizeof(data));
  520. off += sizeof(data);
  521. print_hex_dump_debug("[drm-dp] VSCEXT: ",
  522. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  523. }
  524. static void dp_catalog_panel_setup_hdr_infoframe_sdp(
  525. struct dp_catalog_panel *panel)
  526. {
  527. struct dp_catalog_private *catalog;
  528. struct drm_msm_ext_hdr_metadata *hdr;
  529. struct dp_io_data *io_data;
  530. u32 header, parity, data, mst_offset = 0;
  531. u8 buf[SZ_64], off = 0;
  532. u32 const version = 0x01;
  533. u32 const length = 0x1a;
  534. if (panel->stream_id >= DP_STREAM_MAX) {
  535. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  536. return;
  537. }
  538. if (panel->stream_id == DP_STREAM_1)
  539. mst_offset = MMSS_DP1_GENERIC2_0 - MMSS_DP_GENERIC2_0;
  540. catalog = dp_catalog_get_priv(panel);
  541. hdr = &panel->hdr_meta;
  542. io_data = catalog->io.dp_link;
  543. /* HEADER BYTE 1 */
  544. header = panel->shdr_if_sdp.HB1;
  545. parity = dp_header_get_parity(header);
  546. data = ((header << HEADER_BYTE_1_BIT)
  547. | (parity << PARITY_BYTE_1_BIT));
  548. dp_write(MMSS_DP_GENERIC2_0 + mst_offset,
  549. data);
  550. memcpy(buf + off, &data, sizeof(data));
  551. off += sizeof(data);
  552. /* HEADER BYTE 2 */
  553. header = panel->shdr_if_sdp.HB2;
  554. parity = dp_header_get_parity(header);
  555. data = ((header << HEADER_BYTE_2_BIT)
  556. | (parity << PARITY_BYTE_2_BIT));
  557. dp_write(MMSS_DP_GENERIC2_1 + mst_offset, data);
  558. /* HEADER BYTE 3 */
  559. header = panel->shdr_if_sdp.HB3;
  560. parity = dp_header_get_parity(header);
  561. data = ((header << HEADER_BYTE_3_BIT)
  562. | (parity << PARITY_BYTE_3_BIT));
  563. data |= dp_read(MMSS_DP_VSCEXT_1 + mst_offset);
  564. dp_write(MMSS_DP_GENERIC2_1 + mst_offset,
  565. data);
  566. memcpy(buf + off, &data, sizeof(data));
  567. off += sizeof(data);
  568. data = version;
  569. data |= length << 8;
  570. data |= hdr->eotf << 16;
  571. dp_write(MMSS_DP_GENERIC2_2 + mst_offset, data);
  572. memcpy(buf + off, &data, sizeof(data));
  573. off += sizeof(data);
  574. data = (DP_GET_LSB(hdr->display_primaries_x[0]) |
  575. (DP_GET_MSB(hdr->display_primaries_x[0]) << 8) |
  576. (DP_GET_LSB(hdr->display_primaries_y[0]) << 16) |
  577. (DP_GET_MSB(hdr->display_primaries_y[0]) << 24));
  578. dp_write(MMSS_DP_GENERIC2_3 + mst_offset, data);
  579. memcpy(buf + off, &data, sizeof(data));
  580. off += sizeof(data);
  581. data = (DP_GET_LSB(hdr->display_primaries_x[1]) |
  582. (DP_GET_MSB(hdr->display_primaries_x[1]) << 8) |
  583. (DP_GET_LSB(hdr->display_primaries_y[1]) << 16) |
  584. (DP_GET_MSB(hdr->display_primaries_y[1]) << 24));
  585. dp_write(MMSS_DP_GENERIC2_4 + mst_offset, data);
  586. memcpy(buf + off, &data, sizeof(data));
  587. off += sizeof(data);
  588. data = (DP_GET_LSB(hdr->display_primaries_x[2]) |
  589. (DP_GET_MSB(hdr->display_primaries_x[2]) << 8) |
  590. (DP_GET_LSB(hdr->display_primaries_y[2]) << 16) |
  591. (DP_GET_MSB(hdr->display_primaries_y[2]) << 24));
  592. dp_write(MMSS_DP_GENERIC2_5 + mst_offset, data);
  593. memcpy(buf + off, &data, sizeof(data));
  594. off += sizeof(data);
  595. data = (DP_GET_LSB(hdr->white_point_x) |
  596. (DP_GET_MSB(hdr->white_point_x) << 8) |
  597. (DP_GET_LSB(hdr->white_point_y) << 16) |
  598. (DP_GET_MSB(hdr->white_point_y) << 24));
  599. dp_write(MMSS_DP_GENERIC2_6 + mst_offset, data);
  600. memcpy(buf + off, &data, sizeof(data));
  601. off += sizeof(data);
  602. data = (DP_GET_LSB(hdr->max_luminance) |
  603. (DP_GET_MSB(hdr->max_luminance) << 8) |
  604. (DP_GET_LSB(hdr->min_luminance) << 16) |
  605. (DP_GET_MSB(hdr->min_luminance) << 24));
  606. dp_write(MMSS_DP_GENERIC2_7 + mst_offset, data);
  607. memcpy(buf + off, &data, sizeof(data));
  608. off += sizeof(data);
  609. data = (DP_GET_LSB(hdr->max_content_light_level) |
  610. (DP_GET_MSB(hdr->max_content_light_level) << 8) |
  611. (DP_GET_LSB(hdr->max_average_light_level) << 16) |
  612. (DP_GET_MSB(hdr->max_average_light_level) << 24));
  613. dp_write(MMSS_DP_GENERIC2_8 + mst_offset, data);
  614. memcpy(buf + off, &data, sizeof(data));
  615. off += sizeof(data);
  616. data = 0;
  617. dp_write(MMSS_DP_GENERIC2_9 + mst_offset, data);
  618. memcpy(buf + off, &data, sizeof(data));
  619. off += sizeof(data);
  620. print_hex_dump_debug("[drm-dp] HDR: ",
  621. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  622. }
  623. static void dp_catalog_panel_setup_vsc_sdp(struct dp_catalog_panel *panel)
  624. {
  625. struct dp_catalog_private *catalog;
  626. struct dp_io_data *io_data;
  627. u32 header, parity, data, mst_offset = 0;
  628. u8 off = 0;
  629. u8 buf[SZ_128];
  630. if (!panel) {
  631. DP_ERR("invalid input\n");
  632. return;
  633. }
  634. if (panel->stream_id >= DP_STREAM_MAX) {
  635. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  636. return;
  637. }
  638. if (panel->stream_id == DP_STREAM_1)
  639. mst_offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  640. catalog = dp_catalog_get_priv(panel);
  641. io_data = catalog->io.dp_link;
  642. /* HEADER BYTE 1 */
  643. header = panel->vsc_colorimetry.header.HB1;
  644. parity = dp_header_get_parity(header);
  645. data = ((header << HEADER_BYTE_1_BIT)
  646. | (parity << PARITY_BYTE_1_BIT));
  647. dp_write(MMSS_DP_GENERIC0_0 + mst_offset, data);
  648. memcpy(buf + off, &data, sizeof(data));
  649. off += sizeof(data);
  650. /* HEADER BYTE 2 */
  651. header = panel->vsc_colorimetry.header.HB2;
  652. parity = dp_header_get_parity(header);
  653. data = ((header << HEADER_BYTE_2_BIT)
  654. | (parity << PARITY_BYTE_2_BIT));
  655. dp_write(MMSS_DP_GENERIC0_1 + mst_offset, data);
  656. /* HEADER BYTE 3 */
  657. header = panel->vsc_colorimetry.header.HB3;
  658. parity = dp_header_get_parity(header);
  659. data = ((header << HEADER_BYTE_3_BIT)
  660. | (parity << PARITY_BYTE_3_BIT));
  661. data |= dp_read(MMSS_DP_GENERIC0_1 + mst_offset);
  662. dp_write(MMSS_DP_GENERIC0_1 + mst_offset, data);
  663. memcpy(buf + off, &data, sizeof(data));
  664. off += sizeof(data);
  665. data = 0;
  666. dp_write(MMSS_DP_GENERIC0_2 + mst_offset, data);
  667. memcpy(buf + off, &data, sizeof(data));
  668. off += sizeof(data);
  669. dp_write(MMSS_DP_GENERIC0_3 + mst_offset, data);
  670. memcpy(buf + off, &data, sizeof(data));
  671. off += sizeof(data);
  672. dp_write(MMSS_DP_GENERIC0_4 + mst_offset, data);
  673. memcpy(buf + off, &data, sizeof(data));
  674. off += sizeof(data);
  675. dp_write(MMSS_DP_GENERIC0_5 + mst_offset, data);
  676. memcpy(buf + off, &data, sizeof(data));
  677. off += sizeof(data);
  678. data = (panel->vsc_colorimetry.data[16] & 0xFF) |
  679. ((panel->vsc_colorimetry.data[17] & 0xFF) << 8) |
  680. ((panel->vsc_colorimetry.data[18] & 0x7) << 16);
  681. dp_write(MMSS_DP_GENERIC0_6 + mst_offset, data);
  682. memcpy(buf + off, &data, sizeof(data));
  683. off += sizeof(data);
  684. data = 0;
  685. dp_write(MMSS_DP_GENERIC0_7 + mst_offset, data);
  686. memcpy(buf + off, &data, sizeof(data));
  687. off += sizeof(data);
  688. dp_write(MMSS_DP_GENERIC0_8 + mst_offset, data);
  689. memcpy(buf + off, &data, sizeof(data));
  690. off += sizeof(data);
  691. dp_write(MMSS_DP_GENERIC0_9 + mst_offset, data);
  692. memcpy(buf + off, &data, sizeof(data));
  693. off += sizeof(data);
  694. print_hex_dump_debug("[drm-dp] VSC: ",
  695. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  696. }
  697. static void dp_catalog_panel_config_sdp(struct dp_catalog_panel *panel,
  698. bool en)
  699. {
  700. struct dp_catalog_private *catalog;
  701. struct dp_io_data *io_data;
  702. u32 cfg, cfg2;
  703. u32 sdp_cfg_off = 0;
  704. u32 sdp_cfg2_off = 0;
  705. if (panel->stream_id >= DP_STREAM_MAX) {
  706. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  707. return;
  708. }
  709. catalog = dp_catalog_get_priv(panel);
  710. io_data = catalog->io.dp_link;
  711. if (panel->stream_id == DP_STREAM_1) {
  712. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  713. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  714. }
  715. cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  716. cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  717. if (en) {
  718. /* GEN0_SDP_EN */
  719. cfg |= BIT(17);
  720. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  721. /* GENERIC0_SDPSIZE */
  722. cfg2 |= BIT(16);
  723. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  724. /* setup the GENERIC0 in case of en = true */
  725. dp_catalog_panel_setup_vsc_sdp(panel);
  726. } else {
  727. /* GEN0_SDP_EN */
  728. cfg &= ~BIT(17);
  729. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  730. /* GENERIC0_SDPSIZE */
  731. cfg2 &= ~BIT(16);
  732. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  733. }
  734. dp_catalog_panel_sdp_update(panel);
  735. }
  736. static void dp_catalog_panel_config_misc(struct dp_catalog_panel *panel)
  737. {
  738. struct dp_catalog_private *catalog;
  739. struct dp_io_data *io_data;
  740. u32 reg_offset = 0;
  741. if (!panel) {
  742. DP_ERR("invalid input\n");
  743. return;
  744. }
  745. if (panel->stream_id >= DP_STREAM_MAX) {
  746. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  747. return;
  748. }
  749. catalog = dp_catalog_get_priv(panel);
  750. io_data = catalog->io.dp_link;
  751. if (panel->stream_id == DP_STREAM_1)
  752. reg_offset = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  753. DP_DEBUG("misc settings = 0x%x\n", panel->misc_val);
  754. dp_write(DP_MISC1_MISC0 + reg_offset, panel->misc_val);
  755. }
  756. static int dp_catalog_panel_set_colorspace(struct dp_catalog_panel *panel,
  757. bool vsc_supported)
  758. {
  759. struct dp_catalog_private *catalog;
  760. struct dp_io_data *io_data;
  761. if (!panel) {
  762. DP_ERR("invalid input\n");
  763. return -EINVAL;
  764. }
  765. if (panel->stream_id >= DP_STREAM_MAX) {
  766. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  767. return -EINVAL;
  768. }
  769. catalog = dp_catalog_get_priv(panel);
  770. io_data = catalog->io.dp_link;
  771. if (vsc_supported) {
  772. dp_catalog_panel_setup_vsc_sdp(panel);
  773. dp_catalog_panel_sdp_update(panel);
  774. } else
  775. dp_catalog_panel_config_misc(panel);
  776. return 0;
  777. }
  778. static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en,
  779. u32 dhdr_max_pkts, bool flush)
  780. {
  781. struct dp_catalog_private *catalog;
  782. struct dp_io_data *io_data;
  783. u32 cfg, cfg2, cfg4, misc;
  784. u32 sdp_cfg_off = 0;
  785. u32 sdp_cfg2_off = 0;
  786. u32 sdp_cfg4_off = 0;
  787. u32 misc1_misc0_off = 0;
  788. if (!panel) {
  789. DP_ERR("invalid input\n");
  790. return;
  791. }
  792. if (panel->stream_id >= DP_STREAM_MAX) {
  793. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  794. return;
  795. }
  796. catalog = dp_catalog_get_priv(panel);
  797. io_data = catalog->io.dp_link;
  798. if (panel->stream_id == DP_STREAM_1) {
  799. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  800. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  801. sdp_cfg4_off = MMSS_DP1_SDP_CFG4 - MMSS_DP_SDP_CFG4;
  802. misc1_misc0_off = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  803. }
  804. cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  805. cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  806. misc = dp_read(DP_MISC1_MISC0 + misc1_misc0_off);
  807. if (en) {
  808. if (dhdr_max_pkts) {
  809. /* VSCEXT_SDP_EN */
  810. cfg |= BIT(16);
  811. /* DHDR_EN, DHDR_PACKET_LIMIT */
  812. cfg4 = (dhdr_max_pkts << 1) | BIT(0);
  813. dp_write(MMSS_DP_SDP_CFG4 + sdp_cfg4_off, cfg4);
  814. dp_catalog_panel_setup_vsif_infoframe_sdp(panel);
  815. }
  816. /* GEN2_SDP_EN */
  817. cfg |= BIT(19);
  818. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  819. /* GENERIC2_SDPSIZE */
  820. cfg2 |= BIT(20);
  821. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  822. dp_catalog_panel_setup_hdr_infoframe_sdp(panel);
  823. if (panel->hdr_meta.eotf)
  824. DP_DEBUG("Enabled\n");
  825. else
  826. DP_DEBUG("Reset\n");
  827. } else {
  828. /* VSCEXT_SDP_ENG */
  829. cfg &= ~BIT(16) & ~BIT(19);
  830. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  831. /* GENERIC0_SDPSIZE GENERIC2_SDPSIZE */
  832. cfg2 &= ~BIT(20);
  833. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  834. /* DHDR_EN, DHDR_PACKET_LIMIT */
  835. cfg4 = 0;
  836. dp_write(MMSS_DP_SDP_CFG4 + sdp_cfg4_off, cfg4);
  837. DP_DEBUG("Disabled\n");
  838. }
  839. if (flush) {
  840. DP_DEBUG("flushing HDR metadata\n");
  841. dp_catalog_panel_sdp_update(panel);
  842. }
  843. }
  844. static void dp_catalog_panel_update_transfer_unit(
  845. struct dp_catalog_panel *panel)
  846. {
  847. struct dp_catalog_private *catalog;
  848. struct dp_io_data *io_data;
  849. if (!panel || panel->stream_id >= DP_STREAM_MAX) {
  850. DP_ERR("invalid input\n");
  851. return;
  852. }
  853. catalog = dp_catalog_get_priv(panel);
  854. io_data = catalog->io.dp_link;
  855. dp_write(DP_VALID_BOUNDARY, panel->valid_boundary);
  856. dp_write(DP_TU, panel->dp_tu);
  857. dp_write(DP_VALID_BOUNDARY_2, panel->valid_boundary2);
  858. }
  859. static void dp_catalog_ctrl_state_ctrl(struct dp_catalog_ctrl *ctrl, u32 state)
  860. {
  861. struct dp_catalog_private *catalog;
  862. struct dp_io_data *io_data;
  863. if (!ctrl) {
  864. DP_ERR("invalid input\n");
  865. return;
  866. }
  867. catalog = dp_catalog_get_priv(ctrl);
  868. io_data = catalog->io.dp_link;
  869. dp_write(DP_STATE_CTRL, state);
  870. /* make sure to change the hw state */
  871. wmb();
  872. }
  873. static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt)
  874. {
  875. struct dp_catalog_private *catalog;
  876. struct dp_io_data *io_data;
  877. u32 cfg;
  878. if (!ctrl) {
  879. DP_ERR("invalid input\n");
  880. return;
  881. }
  882. catalog = dp_catalog_get_priv(ctrl);
  883. io_data = catalog->io.dp_link;
  884. cfg = dp_read(DP_CONFIGURATION_CTRL);
  885. /*
  886. * Reset ASSR (alternate scrambler seed reset) by resetting BIT(10).
  887. * ASSR should be set to disable for TPS4 link training pattern.
  888. * Forcing it to 0 as the power on reset value of register enables it.
  889. */
  890. cfg &= ~(BIT(4) | BIT(5) | BIT(10));
  891. cfg |= (ln_cnt - 1) << 4;
  892. dp_write(DP_CONFIGURATION_CTRL, cfg);
  893. cfg = dp_read(DP_MAINLINK_CTRL);
  894. cfg |= 0x02000000;
  895. dp_write(DP_MAINLINK_CTRL, cfg);
  896. DP_DEBUG("DP_MAINLINK_CTRL=0x%x\n", cfg);
  897. }
  898. static void dp_catalog_panel_config_ctrl(struct dp_catalog_panel *panel,
  899. u32 cfg)
  900. {
  901. struct dp_catalog_private *catalog;
  902. struct dp_io_data *io_data;
  903. u32 strm_reg_off = 0, mainlink_ctrl;
  904. if (!panel) {
  905. DP_ERR("invalid input\n");
  906. return;
  907. }
  908. if (panel->stream_id >= DP_STREAM_MAX) {
  909. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  910. return;
  911. }
  912. catalog = dp_catalog_get_priv(panel);
  913. io_data = catalog->io.dp_link;
  914. if (panel->stream_id == DP_STREAM_1)
  915. strm_reg_off = DP1_CONFIGURATION_CTRL - DP_CONFIGURATION_CTRL;
  916. DP_DEBUG("DP_CONFIGURATION_CTRL=0x%x\n", cfg);
  917. dp_write(DP_CONFIGURATION_CTRL + strm_reg_off, cfg);
  918. mainlink_ctrl = dp_read(DP_MAINLINK_CTRL);
  919. if (panel->stream_id == DP_STREAM_0)
  920. io_data = catalog->io.dp_p0;
  921. else if (panel->stream_id == DP_STREAM_1)
  922. io_data = catalog->io.dp_p1;
  923. if (mainlink_ctrl & BIT(8))
  924. dp_write(MMSS_DP_ASYNC_FIFO_CONFIG, 0x01);
  925. else
  926. dp_write(MMSS_DP_ASYNC_FIFO_CONFIG, 0x00);
  927. }
  928. static void dp_catalog_panel_config_dto(struct dp_catalog_panel *panel,
  929. bool ack)
  930. {
  931. struct dp_catalog_private *catalog;
  932. struct dp_io_data *io_data;
  933. u32 dsc_dto;
  934. if (!panel) {
  935. DP_ERR("invalid input\n");
  936. return;
  937. }
  938. if (panel->stream_id >= DP_STREAM_MAX) {
  939. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  940. return;
  941. }
  942. catalog = dp_catalog_get_priv(panel);
  943. io_data = catalog->io.dp_link;
  944. switch (panel->stream_id) {
  945. case DP_STREAM_0:
  946. io_data = catalog->io.dp_p0;
  947. break;
  948. case DP_STREAM_1:
  949. io_data = catalog->io.dp_p1;
  950. break;
  951. default:
  952. DP_ERR("invalid stream id\n");
  953. return;
  954. }
  955. dsc_dto = dp_read(MMSS_DP_DSC_DTO);
  956. if (ack)
  957. dsc_dto = BIT(1);
  958. else
  959. dsc_dto &= ~BIT(1);
  960. dp_write(MMSS_DP_DSC_DTO, dsc_dto);
  961. }
  962. static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl,
  963. bool flipped, char *lane_map)
  964. {
  965. struct dp_catalog_private *catalog;
  966. struct dp_io_data *io_data;
  967. if (!ctrl) {
  968. DP_ERR("invalid input\n");
  969. return;
  970. }
  971. catalog = dp_catalog_get_priv(ctrl);
  972. io_data = catalog->io.dp_link;
  973. dp_write(DP_LOGICAL2PHYSICAL_LANE_MAPPING, 0xe4);
  974. }
  975. static void dp_catalog_ctrl_lane_pnswap(struct dp_catalog_ctrl *ctrl,
  976. u8 ln_pnswap)
  977. {
  978. struct dp_catalog_private *catalog;
  979. struct dp_io_data *io_data;
  980. u32 cfg0, cfg1;
  981. catalog = dp_catalog_get_priv(ctrl);
  982. cfg0 = 0x0a;
  983. cfg1 = 0x0a;
  984. cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0;
  985. cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2;
  986. cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0;
  987. cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2;
  988. io_data = catalog->io.dp_ln_tx0;
  989. dp_write(TXn_TX_POL_INV, cfg0);
  990. io_data = catalog->io.dp_ln_tx1;
  991. dp_write(TXn_TX_POL_INV, cfg1);
  992. }
  993. static void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog_ctrl *ctrl,
  994. bool enable)
  995. {
  996. u32 mainlink_ctrl, reg;
  997. struct dp_catalog_private *catalog;
  998. struct dp_io_data *io_data;
  999. if (!ctrl) {
  1000. DP_ERR("invalid input\n");
  1001. return;
  1002. }
  1003. catalog = dp_catalog_get_priv(ctrl);
  1004. io_data = catalog->io.dp_link;
  1005. if (enable) {
  1006. reg = dp_read(DP_MAINLINK_CTRL);
  1007. mainlink_ctrl = reg & ~(0x03);
  1008. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  1009. wmb(); /* make sure mainlink is turned off before reset */
  1010. mainlink_ctrl = reg | 0x02;
  1011. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  1012. wmb(); /* make sure mainlink entered reset */
  1013. mainlink_ctrl = reg & ~(0x03);
  1014. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  1015. wmb(); /* make sure mainlink reset done */
  1016. mainlink_ctrl = reg | 0x01;
  1017. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  1018. wmb(); /* make sure mainlink turned on */
  1019. } else {
  1020. mainlink_ctrl = dp_read(DP_MAINLINK_CTRL);
  1021. mainlink_ctrl &= ~BIT(0);
  1022. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  1023. }
  1024. }
  1025. static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel,
  1026. u32 rate, u32 stream_rate_khz)
  1027. {
  1028. u32 pixel_m, pixel_n;
  1029. u32 mvid, nvid;
  1030. u32 const nvid_fixed = 0x8000;
  1031. u32 const link_rate_hbr2 = 540000;
  1032. u32 const link_rate_hbr3 = 810000;
  1033. struct dp_catalog_private *catalog;
  1034. struct dp_io_data *io_data;
  1035. u32 strm_reg_off = 0;
  1036. u32 mvid_reg_off = 0, nvid_reg_off = 0;
  1037. if (!panel) {
  1038. DP_ERR("invalid input\n");
  1039. return;
  1040. }
  1041. if (panel->stream_id >= DP_STREAM_MAX) {
  1042. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1043. return;
  1044. }
  1045. catalog = dp_catalog_get_priv(panel);
  1046. io_data = catalog->io.dp_mmss_cc;
  1047. if (panel->stream_id == DP_STREAM_1)
  1048. strm_reg_off = MMSS_DP_PIXEL1_M - MMSS_DP_PIXEL_M;
  1049. pixel_m = dp_read(MMSS_DP_PIXEL_M + strm_reg_off);
  1050. pixel_n = dp_read(MMSS_DP_PIXEL_N + strm_reg_off);
  1051. DP_DEBUG("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n);
  1052. mvid = (pixel_m & 0xFFFF) * 5;
  1053. nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);
  1054. if (nvid < nvid_fixed) {
  1055. u32 temp;
  1056. temp = (nvid_fixed / nvid) * nvid;
  1057. mvid = (nvid_fixed / nvid) * mvid;
  1058. nvid = temp;
  1059. }
  1060. DP_DEBUG("rate = %d\n", rate);
  1061. if (panel->widebus_en)
  1062. mvid <<= 1;
  1063. if (link_rate_hbr2 == rate)
  1064. nvid *= 2;
  1065. if (link_rate_hbr3 == rate)
  1066. nvid *= 3;
  1067. io_data = catalog->io.dp_link;
  1068. if (panel->stream_id == DP_STREAM_1) {
  1069. mvid_reg_off = DP1_SOFTWARE_MVID - DP_SOFTWARE_MVID;
  1070. nvid_reg_off = DP1_SOFTWARE_NVID - DP_SOFTWARE_NVID;
  1071. }
  1072. DP_DEBUG("mvid=0x%x, nvid=0x%x\n", mvid, nvid);
  1073. dp_write(DP_SOFTWARE_MVID + mvid_reg_off, mvid);
  1074. dp_write(DP_SOFTWARE_NVID + nvid_reg_off, nvid);
  1075. }
  1076. static void dp_catalog_ctrl_set_pattern(struct dp_catalog_ctrl *ctrl,
  1077. u32 pattern)
  1078. {
  1079. int bit, cnt = 10;
  1080. u32 data;
  1081. const u32 link_training_offset = 3;
  1082. struct dp_catalog_private *catalog;
  1083. struct dp_io_data *io_data;
  1084. if (!ctrl) {
  1085. DP_ERR("invalid input\n");
  1086. return;
  1087. }
  1088. catalog = dp_catalog_get_priv(ctrl);
  1089. io_data = catalog->io.dp_link;
  1090. switch (pattern) {
  1091. case DP_TRAINING_PATTERN_4:
  1092. bit = 3;
  1093. break;
  1094. case DP_TRAINING_PATTERN_3:
  1095. case DP_TRAINING_PATTERN_2:
  1096. case DP_TRAINING_PATTERN_1:
  1097. bit = pattern - 1;
  1098. break;
  1099. default:
  1100. DP_ERR("invalid pattern\n");
  1101. return;
  1102. }
  1103. DP_DEBUG("hw: bit=%d train=%d\n", bit, pattern);
  1104. dp_write(DP_STATE_CTRL, BIT(bit));
  1105. bit += link_training_offset;
  1106. while (cnt--) {
  1107. data = dp_read(DP_MAINLINK_READY);
  1108. if (data & BIT(bit))
  1109. break;
  1110. }
  1111. if (cnt == 0)
  1112. DP_ERR("set link_train=%d failed\n", pattern);
  1113. }
  1114. static void dp_catalog_ctrl_usb_reset(struct dp_catalog_ctrl *ctrl, bool flip)
  1115. {
  1116. struct dp_catalog_private *catalog;
  1117. struct dp_io_data *io_data;
  1118. if (!ctrl) {
  1119. DP_ERR("invalid input\n");
  1120. return;
  1121. }
  1122. catalog = dp_catalog_get_priv(ctrl);
  1123. io_data = catalog->io.usb3_dp_com;
  1124. DP_DEBUG("Program PHYMODE to DP only\n");
  1125. dp_write(USB3_DP_COM_RESET_OVRD_CTRL, 0x0a);
  1126. dp_write(USB3_DP_COM_PHY_MODE_CTRL, 0x02);
  1127. dp_write(USB3_DP_COM_SW_RESET, 0x01);
  1128. /* make sure usb3 com phy software reset is done */
  1129. wmb();
  1130. if (!flip) /* CC1 */
  1131. dp_write(USB3_DP_COM_TYPEC_CTRL, 0x02);
  1132. else /* CC2 */
  1133. dp_write(USB3_DP_COM_TYPEC_CTRL, 0x03);
  1134. dp_write(USB3_DP_COM_SWI_CTRL, 0x00);
  1135. dp_write(USB3_DP_COM_SW_RESET, 0x00);
  1136. /* make sure the software reset is done */
  1137. wmb();
  1138. dp_write(USB3_DP_COM_POWER_DOWN_CTRL, 0x01);
  1139. dp_write(USB3_DP_COM_RESET_OVRD_CTRL, 0x00);
  1140. /* make sure phy is brought out of reset */
  1141. wmb();
  1142. }
  1143. static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel, u32 pattern)
  1144. {
  1145. struct dp_catalog_private *catalog;
  1146. struct dp_io_data *io_data;
  1147. u32 reg;
  1148. if (!panel) {
  1149. DP_ERR("invalid input\n");
  1150. return;
  1151. }
  1152. if (panel->stream_id >= DP_STREAM_MAX) {
  1153. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1154. return;
  1155. }
  1156. catalog = dp_catalog_get_priv(panel);
  1157. if (panel->stream_id == DP_STREAM_0)
  1158. io_data = catalog->io.dp_p0;
  1159. else if (panel->stream_id == DP_STREAM_1)
  1160. io_data = catalog->io.dp_p1;
  1161. if (!pattern) {
  1162. dp_write(MMSS_DP_TPG_MAIN_CONTROL, 0x0);
  1163. dp_write(MMSS_DP_BIST_ENABLE, 0x0);
  1164. reg = dp_read(MMSS_DP_TIMING_ENGINE_EN);
  1165. reg &= ~0x1;
  1166. dp_write(MMSS_DP_TIMING_ENGINE_EN, reg);
  1167. wmb(); /* ensure Timing generator is turned off */
  1168. return;
  1169. }
  1170. if (pattern > DP_TPG_PATTERN_MAX)
  1171. pattern = DP_TPG_PATTERN_DEFAULT;
  1172. dp_write(MMSS_DP_INTF_HSYNC_CTL,
  1173. panel->hsync_ctl);
  1174. dp_write(MMSS_DP_INTF_VSYNC_PERIOD_F0,
  1175. panel->vsync_period * panel->hsync_period);
  1176. dp_write(MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0,
  1177. panel->v_sync_width * panel->hsync_period);
  1178. dp_write(MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
  1179. dp_write(MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0);
  1180. dp_write(MMSS_DP_INTF_DISPLAY_HCTL, panel->display_hctl);
  1181. dp_write(MMSS_DP_INTF_ACTIVE_HCTL, 0);
  1182. dp_write(MMSS_INTF_DISPLAY_V_START_F0, panel->display_v_start);
  1183. dp_write(MMSS_DP_INTF_DISPLAY_V_END_F0, panel->display_v_end);
  1184. dp_write(MMSS_INTF_DISPLAY_V_START_F1, 0);
  1185. dp_write(MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
  1186. dp_write(MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
  1187. dp_write(MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
  1188. dp_write(MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
  1189. dp_write(MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
  1190. dp_write(MMSS_DP_INTF_POLARITY_CTL, 0);
  1191. wmb(); /* ensure TPG registers are programmed */
  1192. dp_write(MMSS_DP_TPG_MAIN_CONTROL, (1 << pattern));
  1193. dp_write(MMSS_DP_TPG_VIDEO_CONFIG, 0x5);
  1194. wmb(); /* ensure TPG config is programmed */
  1195. dp_write(MMSS_DP_BIST_ENABLE, 0x1);
  1196. reg = dp_read(MMSS_DP_TIMING_ENGINE_EN);
  1197. reg |= 0x1;
  1198. dp_write(MMSS_DP_TIMING_ENGINE_EN, reg);
  1199. wmb(); /* ensure Timing generator is turned on */
  1200. }
  1201. static void dp_catalog_panel_dsc_cfg(struct dp_catalog_panel *panel)
  1202. {
  1203. struct dp_catalog_private *catalog;
  1204. struct dp_io_data *io_data;
  1205. u32 reg, offset;
  1206. int i;
  1207. if (!panel) {
  1208. DP_ERR("invalid input\n");
  1209. return;
  1210. }
  1211. if (panel->stream_id >= DP_STREAM_MAX) {
  1212. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1213. return;
  1214. }
  1215. catalog = dp_catalog_get_priv(panel);
  1216. if (panel->stream_id == DP_STREAM_0)
  1217. io_data = catalog->io.dp_p0;
  1218. else
  1219. io_data = catalog->io.dp_p1;
  1220. dp_write(MMSS_DP_DSC_DTO_COUNT, panel->dsc.dto_count);
  1221. reg = dp_read(MMSS_DP_DSC_DTO);
  1222. if (panel->dsc.dto_en) {
  1223. reg |= BIT(0);
  1224. reg |= BIT(3);
  1225. reg |= (panel->dsc.dto_n << 8);
  1226. reg |= (panel->dsc.dto_d << 16);
  1227. }
  1228. dp_write(MMSS_DP_DSC_DTO, reg);
  1229. io_data = catalog->io.dp_link;
  1230. if (panel->stream_id == DP_STREAM_0)
  1231. offset = 0;
  1232. else
  1233. offset = DP1_COMPRESSION_MODE_CTRL - DP_COMPRESSION_MODE_CTRL;
  1234. dp_write(DP_PPS_HB_0_3 + offset, 0x7F1000);
  1235. dp_write(DP_PPS_PB_0_3 + offset, 0xA22300);
  1236. for (i = 0; i < panel->dsc.parity_word_len; i++)
  1237. dp_write(DP_PPS_PB_4_7 + (i << 2) + offset,
  1238. panel->dsc.parity_word[i]);
  1239. for (i = 0; i < panel->dsc.pps_word_len; i++)
  1240. dp_write(DP_PPS_PPS_0_3 + (i << 2) + offset,
  1241. panel->dsc.pps_word[i]);
  1242. reg = 0;
  1243. if (panel->dsc.dsc_en) {
  1244. reg = BIT(0);
  1245. reg |= (panel->dsc.eol_byte_num << 3);
  1246. reg |= (panel->dsc.slice_per_pkt << 5);
  1247. reg |= (panel->dsc.bytes_per_pkt << 16);
  1248. reg |= (panel->dsc.be_in_lane << 10);
  1249. }
  1250. dp_write(DP_COMPRESSION_MODE_CTRL + offset, reg);
  1251. DP_DEBUG("compression:0x%x for stream:%d\n",
  1252. reg, panel->stream_id);
  1253. }
  1254. static void dp_catalog_panel_dp_flush(struct dp_catalog_panel *panel,
  1255. enum dp_flush_bit flush_bit)
  1256. {
  1257. struct dp_catalog_private *catalog;
  1258. struct dp_io_data *io_data;
  1259. u32 dp_flush, offset;
  1260. struct dp_dsc_cfg_data *dsc;
  1261. if (!panel) {
  1262. DP_ERR("invalid input\n");
  1263. return;
  1264. }
  1265. if (panel->stream_id >= DP_STREAM_MAX) {
  1266. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1267. return;
  1268. }
  1269. catalog = dp_catalog_get_priv(panel);
  1270. io_data = catalog->io.dp_link;
  1271. dsc = &panel->dsc;
  1272. if (panel->stream_id == DP_STREAM_0)
  1273. offset = 0;
  1274. else
  1275. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1276. dp_flush = dp_read(MMSS_DP_FLUSH + offset);
  1277. if ((flush_bit == DP_PPS_FLUSH) &&
  1278. dsc->continuous_pps)
  1279. dp_flush &= ~BIT(2);
  1280. dp_flush |= BIT(flush_bit);
  1281. dp_write(MMSS_DP_FLUSH + offset, dp_flush);
  1282. }
  1283. static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel)
  1284. {
  1285. dp_catalog_panel_dp_flush(panel, DP_PPS_FLUSH);
  1286. DP_DEBUG("pps flush for stream:%d\n", panel->stream_id);
  1287. }
  1288. static void dp_catalog_panel_dhdr_flush(struct dp_catalog_panel *panel)
  1289. {
  1290. dp_catalog_panel_dp_flush(panel, DP_DHDR_FLUSH);
  1291. DP_DEBUG("dhdr flush for stream:%d\n", panel->stream_id);
  1292. }
  1293. static bool dp_catalog_panel_dhdr_busy(struct dp_catalog_panel *panel)
  1294. {
  1295. struct dp_catalog_private *catalog;
  1296. struct dp_io_data *io_data;
  1297. u32 dp_flush, offset;
  1298. if (panel->stream_id >= DP_STREAM_MAX) {
  1299. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1300. return false;
  1301. }
  1302. catalog = dp_catalog_get_priv(panel);
  1303. io_data = catalog->io.dp_link;
  1304. if (panel->stream_id == DP_STREAM_0)
  1305. offset = 0;
  1306. else
  1307. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1308. dp_flush = dp_read(MMSS_DP_FLUSH + offset);
  1309. return dp_flush & BIT(DP_DHDR_FLUSH) ? true : false;
  1310. }
  1311. static void dp_catalog_ctrl_reset(struct dp_catalog_ctrl *ctrl)
  1312. {
  1313. u32 sw_reset;
  1314. struct dp_catalog_private *catalog;
  1315. struct dp_io_data *io_data;
  1316. if (!ctrl) {
  1317. DP_ERR("invalid input\n");
  1318. return;
  1319. }
  1320. catalog = dp_catalog_get_priv(ctrl);
  1321. io_data = catalog->io.dp_ahb;
  1322. sw_reset = dp_read(DP_SW_RESET);
  1323. sw_reset |= BIT(0);
  1324. dp_write(DP_SW_RESET, sw_reset);
  1325. usleep_range(1000, 1010); /* h/w recommended delay */
  1326. sw_reset &= ~BIT(0);
  1327. dp_write(DP_SW_RESET, sw_reset);
  1328. }
  1329. static bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog_ctrl *ctrl)
  1330. {
  1331. u32 data;
  1332. int cnt = 10;
  1333. struct dp_catalog_private *catalog;
  1334. struct dp_io_data *io_data;
  1335. if (!ctrl) {
  1336. DP_ERR("invalid input\n");
  1337. goto end;
  1338. }
  1339. catalog = dp_catalog_get_priv(ctrl);
  1340. io_data = catalog->io.dp_link;
  1341. while (--cnt) {
  1342. /* DP_MAINLINK_READY */
  1343. data = dp_read(DP_MAINLINK_READY);
  1344. if (data & BIT(0))
  1345. return true;
  1346. usleep_range(1000, 1010); /* 1ms wait before next reg read */
  1347. }
  1348. DP_ERR("mainlink not ready\n");
  1349. end:
  1350. return false;
  1351. }
  1352. static void dp_catalog_ctrl_enable_irq(struct dp_catalog_ctrl *ctrl,
  1353. bool enable)
  1354. {
  1355. struct dp_catalog_private *catalog;
  1356. struct dp_io_data *io_data;
  1357. if (!ctrl) {
  1358. DP_ERR("invalid input\n");
  1359. return;
  1360. }
  1361. catalog = dp_catalog_get_priv(ctrl);
  1362. io_data = catalog->io.dp_ahb;
  1363. if (enable) {
  1364. dp_write(DP_INTR_STATUS, DP_INTR_MASK1);
  1365. dp_write(DP_INTR_STATUS2, DP_INTR_MASK2);
  1366. dp_write(DP_INTR_STATUS5, DP_INTR_MASK5);
  1367. } else {
  1368. /* disable interrupts */
  1369. dp_write(DP_INTR_STATUS, 0x00);
  1370. dp_write(DP_INTR_STATUS2, 0x00);
  1371. dp_write(DP_INTR_STATUS5, 0x00);
  1372. wmb();
  1373. /* clear all pending interrupts */
  1374. dp_write(DP_INTR_STATUS, DP_INTERRUPT_STATUS1 << 1);
  1375. dp_write(DP_INTR_STATUS2, DP_INTERRUPT_STATUS2 << 1);
  1376. dp_write(DP_INTR_STATUS5, DP_INTERRUPT_STATUS5 << 1);
  1377. wmb();
  1378. }
  1379. }
  1380. static void dp_catalog_ctrl_get_interrupt(struct dp_catalog_ctrl *ctrl)
  1381. {
  1382. u32 ack = 0;
  1383. struct dp_catalog_private *catalog;
  1384. struct dp_io_data *io_data;
  1385. if (!ctrl) {
  1386. DP_ERR("invalid input\n");
  1387. return;
  1388. }
  1389. catalog = dp_catalog_get_priv(ctrl);
  1390. io_data = catalog->io.dp_ahb;
  1391. ctrl->isr = dp_read(DP_INTR_STATUS2);
  1392. ctrl->isr &= ~DP_INTR_MASK2;
  1393. ack = ctrl->isr & DP_INTERRUPT_STATUS2;
  1394. ack <<= 1;
  1395. ack |= DP_INTR_MASK2;
  1396. dp_write(DP_INTR_STATUS2, ack);
  1397. ctrl->isr5 = dp_read(DP_INTR_STATUS5);
  1398. ctrl->isr5 &= ~DP_INTR_MASK5;
  1399. ack = ctrl->isr5 & DP_INTERRUPT_STATUS5;
  1400. ack <<= 1;
  1401. ack |= DP_INTR_MASK5;
  1402. dp_write(DP_INTR_STATUS5, ack);
  1403. }
  1404. static void dp_catalog_ctrl_phy_reset(struct dp_catalog_ctrl *ctrl)
  1405. {
  1406. struct dp_catalog_private *catalog;
  1407. struct dp_io_data *io_data;
  1408. if (!ctrl) {
  1409. DP_ERR("invalid input\n");
  1410. return;
  1411. }
  1412. catalog = dp_catalog_get_priv(ctrl);
  1413. io_data = catalog->io.dp_ahb;
  1414. dp_write(DP_PHY_CTRL, 0x5); /* bit 0 & 2 */
  1415. usleep_range(1000, 1010); /* h/w recommended delay */
  1416. dp_write(DP_PHY_CTRL, 0x0);
  1417. wmb(); /* make sure PHY reset done */
  1418. }
  1419. static void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog_ctrl *ctrl,
  1420. bool flipped, u8 ln_cnt)
  1421. {
  1422. u32 info = 0x0;
  1423. struct dp_catalog_private *catalog;
  1424. struct dp_io_data *io_data;
  1425. u8 orientation = BIT(!!flipped);
  1426. if (!ctrl) {
  1427. DP_ERR("invalid input\n");
  1428. return;
  1429. }
  1430. catalog = dp_catalog_get_priv(ctrl);
  1431. io_data = catalog->io.dp_phy;
  1432. info |= (ln_cnt & 0x0F);
  1433. info |= ((orientation & 0x0F) << 4);
  1434. DP_DEBUG("Shared Info = 0x%x\n", info);
  1435. dp_write(DP_PHY_SPARE0, info);
  1436. }
  1437. static void dp_catalog_ctrl_update_vx_px(struct dp_catalog_ctrl *ctrl,
  1438. u8 v_level, u8 p_level, bool high)
  1439. {
  1440. struct dp_catalog_private *catalog;
  1441. struct dp_io_data *io_data;
  1442. u8 value0, value1;
  1443. u32 version;
  1444. if (!ctrl) {
  1445. DP_ERR("invalid input\n");
  1446. return;
  1447. }
  1448. catalog = dp_catalog_get_priv(ctrl);
  1449. DP_DEBUG("hw: v=%d p=%d\n", v_level, p_level);
  1450. io_data = catalog->io.dp_ahb;
  1451. version = dp_read(DP_HW_VERSION);
  1452. if (version == 0x10020004) {
  1453. if (high) {
  1454. value0 = vm_voltage_swing_hbr3_hbr2[v_level][p_level];
  1455. value1 = vm_pre_emphasis_hbr3_hbr2[v_level][p_level];
  1456. } else {
  1457. value0 = vm_voltage_swing_hbr_rbr[v_level][p_level];
  1458. value1 = vm_pre_emphasis_hbr_rbr[v_level][p_level];
  1459. }
  1460. } else {
  1461. value0 = vm_voltage_swing[v_level][p_level];
  1462. value1 = vm_pre_emphasis[v_level][p_level];
  1463. }
  1464. /* program default setting first */
  1465. io_data = catalog->io.dp_ln_tx0;
  1466. dp_write(TXn_TX_DRV_LVL, 0x2A);
  1467. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  1468. io_data = catalog->io.dp_ln_tx1;
  1469. dp_write(TXn_TX_DRV_LVL, 0x2A);
  1470. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  1471. /* Enable MUX to use Cursor values from these registers */
  1472. value0 |= BIT(5);
  1473. value1 |= BIT(5);
  1474. /* Configure host and panel only if both values are allowed */
  1475. if (value0 != 0xFF && value1 != 0xFF) {
  1476. io_data = catalog->io.dp_ln_tx0;
  1477. dp_write(TXn_TX_DRV_LVL, value0);
  1478. dp_write(TXn_TX_EMP_POST1_LVL, value1);
  1479. io_data = catalog->io.dp_ln_tx1;
  1480. dp_write(TXn_TX_DRV_LVL, value0);
  1481. dp_write(TXn_TX_EMP_POST1_LVL, value1);
  1482. DP_DEBUG("hw: vx_value=0x%x px_value=0x%x\n",
  1483. value0, value1);
  1484. } else {
  1485. DP_ERR("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n",
  1486. v_level, value0, p_level, value1);
  1487. }
  1488. }
  1489. static void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog_ctrl *ctrl,
  1490. u32 pattern)
  1491. {
  1492. struct dp_catalog_private *catalog;
  1493. u32 value = 0x0;
  1494. struct dp_io_data *io_data = NULL;
  1495. if (!ctrl) {
  1496. DP_ERR("invalid input\n");
  1497. return;
  1498. }
  1499. catalog = dp_catalog_get_priv(ctrl);
  1500. io_data = catalog->io.dp_link;
  1501. dp_write(DP_STATE_CTRL, 0x0);
  1502. switch (pattern) {
  1503. case DP_PHY_TEST_PATTERN_D10_2:
  1504. dp_write(DP_STATE_CTRL, 0x1);
  1505. break;
  1506. case DP_PHY_TEST_PATTERN_ERROR_COUNT:
  1507. value &= ~(1 << 16);
  1508. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1509. value |= 0xFC;
  1510. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1511. dp_write(DP_MAINLINK_LEVELS, 0x2);
  1512. dp_write(DP_STATE_CTRL, 0x10);
  1513. break;
  1514. case DP_PHY_TEST_PATTERN_PRBS7:
  1515. dp_write(DP_STATE_CTRL, 0x20);
  1516. break;
  1517. case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
  1518. dp_write(DP_STATE_CTRL, 0x40);
  1519. /* 00111110000011111000001111100000 */
  1520. dp_write(DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 0x3E0F83E0);
  1521. /* 00001111100000111110000011111000 */
  1522. dp_write(DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 0x0F83E0F8);
  1523. /* 1111100000111110 */
  1524. dp_write(DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E);
  1525. break;
  1526. case DP_PHY_TEST_PATTERN_CP2520:
  1527. value = dp_read(DP_MAINLINK_CTRL);
  1528. value &= ~BIT(4);
  1529. dp_write(DP_MAINLINK_CTRL, value);
  1530. value = BIT(16);
  1531. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1532. value |= 0xFC;
  1533. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1534. dp_write(DP_MAINLINK_LEVELS, 0x2);
  1535. dp_write(DP_STATE_CTRL, 0x10);
  1536. value = dp_read(DP_MAINLINK_CTRL);
  1537. value |= BIT(0);
  1538. dp_write(DP_MAINLINK_CTRL, value);
  1539. break;
  1540. case DP_PHY_TEST_PATTERN_CP2520_3:
  1541. dp_write(DP_MAINLINK_CTRL, 0x01);
  1542. dp_write(DP_STATE_CTRL, 0x8);
  1543. break;
  1544. default:
  1545. DP_DEBUG("No valid test pattern requested: 0x%x\n", pattern);
  1546. return;
  1547. }
  1548. /* Make sure the test pattern is programmed in the hardware */
  1549. wmb();
  1550. }
  1551. static u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog_ctrl *ctrl)
  1552. {
  1553. struct dp_catalog_private *catalog;
  1554. struct dp_io_data *io_data = NULL;
  1555. if (!ctrl) {
  1556. DP_ERR("invalid input\n");
  1557. return 0;
  1558. }
  1559. catalog = dp_catalog_get_priv(ctrl);
  1560. io_data = catalog->io.dp_link;
  1561. return dp_read(DP_MAINLINK_READY);
  1562. }
  1563. static void dp_catalog_ctrl_fec_config(struct dp_catalog_ctrl *ctrl,
  1564. bool enable)
  1565. {
  1566. struct dp_catalog_private *catalog;
  1567. struct dp_io_data *io_data = NULL;
  1568. u32 reg;
  1569. if (!ctrl) {
  1570. DP_ERR("invalid input\n");
  1571. return;
  1572. }
  1573. catalog = dp_catalog_get_priv(ctrl);
  1574. io_data = catalog->io.dp_link;
  1575. reg = dp_read(DP_MAINLINK_CTRL);
  1576. /*
  1577. * fec_en = BIT(12)
  1578. * fec_seq_mode = BIT(22)
  1579. * sde_flush = BIT(23) | BIT(24)
  1580. * fb_boundary_sel = BIT(25)
  1581. */
  1582. if (enable)
  1583. reg |= BIT(12) | BIT(22) | BIT(23) | BIT(24) | BIT(25);
  1584. else
  1585. reg &= ~BIT(12);
  1586. dp_write(DP_MAINLINK_CTRL, reg);
  1587. /* make sure mainlink configuration is updated with fec sequence */
  1588. wmb();
  1589. }
  1590. u32 dp_catalog_get_dp_core_version(struct dp_catalog *dp_catalog)
  1591. {
  1592. struct dp_catalog_private *catalog;
  1593. struct dp_io_data *io_data;
  1594. if (!dp_catalog) {
  1595. DP_ERR("invalid input\n");
  1596. return 0;
  1597. }
  1598. catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog);
  1599. if (catalog->dp_core_version)
  1600. return catalog->dp_core_version;
  1601. io_data = catalog->io.dp_ahb;
  1602. return dp_read(DP_HW_VERSION);
  1603. }
  1604. u32 dp_catalog_get_dp_phy_version(struct dp_catalog *dp_catalog)
  1605. {
  1606. struct dp_catalog_private *catalog;
  1607. struct dp_io_data *io_data;
  1608. if (!dp_catalog) {
  1609. DP_ERR("invalid input\n");
  1610. return 0;
  1611. }
  1612. catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog);
  1613. if (catalog->dp_phy_version)
  1614. return catalog->dp_phy_version;
  1615. io_data = catalog->io.dp_phy;
  1616. catalog->dp_phy_version = (dp_read(DP_PHY_REVISION_ID3) << 24) |
  1617. (dp_read(DP_PHY_REVISION_ID2) << 16) |
  1618. (dp_read(DP_PHY_REVISION_ID1) << 8) |
  1619. dp_read(DP_PHY_REVISION_ID0);
  1620. return catalog->dp_phy_version;
  1621. }
  1622. static int dp_catalog_reg_dump(struct dp_catalog *dp_catalog,
  1623. char *name, u8 **out_buf, u32 *out_buf_len)
  1624. {
  1625. int ret = 0;
  1626. u8 *buf;
  1627. u32 len;
  1628. struct dp_io_data *io_data;
  1629. struct dp_catalog_private *catalog;
  1630. struct dp_parser *parser;
  1631. if (!dp_catalog) {
  1632. DP_ERR("invalid input\n");
  1633. return -EINVAL;
  1634. }
  1635. catalog = container_of(dp_catalog, struct dp_catalog_private,
  1636. dp_catalog);
  1637. parser = catalog->parser;
  1638. parser->get_io_buf(parser, name);
  1639. io_data = parser->get_io(parser, name);
  1640. if (!io_data) {
  1641. DP_ERR("IO %s not found\n", name);
  1642. ret = -EINVAL;
  1643. goto end;
  1644. }
  1645. buf = io_data->buf;
  1646. len = io_data->io.len;
  1647. if (!buf || !len) {
  1648. DP_ERR("no buffer available\n");
  1649. ret = -ENOMEM;
  1650. goto end;
  1651. }
  1652. if (!strcmp(catalog->exe_mode, "hw") ||
  1653. !strcmp(catalog->exe_mode, "all")) {
  1654. u32 i, data;
  1655. u32 const rowsize = 4;
  1656. void __iomem *addr = io_data->io.base;
  1657. memset(buf, 0, len);
  1658. for (i = 0; i < len / rowsize; i++) {
  1659. data = readl_relaxed(addr);
  1660. memcpy(buf + (rowsize * i), &data, sizeof(u32));
  1661. addr += rowsize;
  1662. }
  1663. }
  1664. *out_buf = buf;
  1665. *out_buf_len = len;
  1666. end:
  1667. if (ret)
  1668. parser->clear_io_buf(parser);
  1669. return ret;
  1670. }
  1671. static void dp_catalog_ctrl_mst_config(struct dp_catalog_ctrl *ctrl,
  1672. bool enable)
  1673. {
  1674. struct dp_catalog_private *catalog;
  1675. struct dp_io_data *io_data = NULL;
  1676. u32 reg;
  1677. if (!ctrl) {
  1678. DP_ERR("invalid input\n");
  1679. return;
  1680. }
  1681. catalog = dp_catalog_get_priv(ctrl);
  1682. io_data = catalog->io.dp_link;
  1683. reg = dp_read(DP_MAINLINK_CTRL);
  1684. if (enable)
  1685. reg |= (0x04000100);
  1686. else
  1687. reg &= ~(0x04000100);
  1688. dp_write(DP_MAINLINK_CTRL, reg);
  1689. /* make sure mainlink MST configuration is updated */
  1690. wmb();
  1691. }
  1692. static void dp_catalog_ctrl_trigger_act(struct dp_catalog_ctrl *ctrl)
  1693. {
  1694. struct dp_catalog_private *catalog;
  1695. struct dp_io_data *io_data = NULL;
  1696. if (!ctrl) {
  1697. DP_ERR("invalid input\n");
  1698. return;
  1699. }
  1700. catalog = dp_catalog_get_priv(ctrl);
  1701. io_data = catalog->io.dp_link;
  1702. dp_write(DP_MST_ACT, 0x1);
  1703. /* make sure ACT signal is performed */
  1704. wmb();
  1705. }
  1706. static void dp_catalog_ctrl_read_act_complete_sts(struct dp_catalog_ctrl *ctrl,
  1707. bool *sts)
  1708. {
  1709. struct dp_catalog_private *catalog;
  1710. struct dp_io_data *io_data = NULL;
  1711. u32 reg;
  1712. if (!ctrl || !sts) {
  1713. DP_ERR("invalid input\n");
  1714. return;
  1715. }
  1716. *sts = false;
  1717. catalog = dp_catalog_get_priv(ctrl);
  1718. io_data = catalog->io.dp_link;
  1719. reg = dp_read(DP_MST_ACT);
  1720. if (!reg)
  1721. *sts = true;
  1722. }
  1723. static void dp_catalog_ctrl_channel_alloc(struct dp_catalog_ctrl *ctrl,
  1724. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1725. {
  1726. struct dp_catalog_private *catalog;
  1727. struct dp_io_data *io_data = NULL;
  1728. u32 i, slot_reg_1, slot_reg_2, slot;
  1729. u32 reg_off = 0;
  1730. int const num_slots_per_reg = 32;
  1731. if (!ctrl || ch >= DP_STREAM_MAX) {
  1732. DP_ERR("invalid input. ch %d\n", ch);
  1733. return;
  1734. }
  1735. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1736. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1737. DP_ERR("invalid slots start %d, tot %d\n",
  1738. ch_start_slot, tot_slot_cnt);
  1739. return;
  1740. }
  1741. catalog = dp_catalog_get_priv(ctrl);
  1742. io_data = catalog->io.dp_link;
  1743. DP_DEBUG("ch %d, start_slot %d, tot_slot %d\n",
  1744. ch, ch_start_slot, tot_slot_cnt);
  1745. if (ch == DP_STREAM_1)
  1746. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1747. slot_reg_1 = 0;
  1748. slot_reg_2 = 0;
  1749. if (ch_start_slot && tot_slot_cnt) {
  1750. ch_start_slot--;
  1751. for (i = 0; i < tot_slot_cnt; i++) {
  1752. if (ch_start_slot < num_slots_per_reg) {
  1753. slot_reg_1 |= BIT(ch_start_slot);
  1754. } else {
  1755. slot = ch_start_slot - num_slots_per_reg;
  1756. slot_reg_2 |= BIT(slot);
  1757. }
  1758. ch_start_slot++;
  1759. }
  1760. }
  1761. DP_DEBUG("ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1762. slot_reg_1, slot_reg_2);
  1763. dp_write(DP_DP0_TIMESLOT_1_32 + reg_off, slot_reg_1);
  1764. dp_write(DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2);
  1765. }
  1766. static void dp_catalog_ctrl_channel_dealloc(struct dp_catalog_ctrl *ctrl,
  1767. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1768. {
  1769. struct dp_catalog_private *catalog;
  1770. struct dp_io_data *io_data = NULL;
  1771. u32 i, slot_reg_1, slot_reg_2, slot;
  1772. u32 reg_off = 0;
  1773. if (!ctrl || ch >= DP_STREAM_MAX) {
  1774. DP_ERR("invalid input. ch %d\n", ch);
  1775. return;
  1776. }
  1777. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1778. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1779. DP_ERR("invalid slots start %d, tot %d\n",
  1780. ch_start_slot, tot_slot_cnt);
  1781. return;
  1782. }
  1783. catalog = dp_catalog_get_priv(ctrl);
  1784. io_data = catalog->io.dp_link;
  1785. DP_DEBUG("dealloc ch %d, start_slot %d, tot_slot %d\n",
  1786. ch, ch_start_slot, tot_slot_cnt);
  1787. if (ch == DP_STREAM_1)
  1788. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1789. slot_reg_1 = dp_read(DP_DP0_TIMESLOT_1_32 + reg_off);
  1790. slot_reg_2 = dp_read(DP_DP0_TIMESLOT_33_63 + reg_off);
  1791. ch_start_slot = ch_start_slot - 1;
  1792. for (i = 0; i < tot_slot_cnt; i++) {
  1793. if (ch_start_slot < 33) {
  1794. slot_reg_1 &= ~BIT(ch_start_slot);
  1795. } else {
  1796. slot = ch_start_slot - 33;
  1797. slot_reg_2 &= ~BIT(slot);
  1798. }
  1799. ch_start_slot++;
  1800. }
  1801. DP_DEBUG("dealloc ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1802. slot_reg_1, slot_reg_2);
  1803. dp_write(DP_DP0_TIMESLOT_1_32 + reg_off, slot_reg_1);
  1804. dp_write(DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2);
  1805. }
  1806. static void dp_catalog_ctrl_update_rg(struct dp_catalog_ctrl *ctrl, u32 ch,
  1807. u32 x_int, u32 y_frac_enum)
  1808. {
  1809. struct dp_catalog_private *catalog;
  1810. struct dp_io_data *io_data = NULL;
  1811. u32 rg, reg_off = 0;
  1812. if (!ctrl || ch >= DP_STREAM_MAX) {
  1813. DP_ERR("invalid input. ch %d\n", ch);
  1814. return;
  1815. }
  1816. catalog = dp_catalog_get_priv(ctrl);
  1817. io_data = catalog->io.dp_link;
  1818. rg = y_frac_enum;
  1819. rg |= (x_int << 16);
  1820. DP_DEBUG("ch: %d x_int:%d y_frac_enum:%d rg:%d\n", ch, x_int,
  1821. y_frac_enum, rg);
  1822. if (ch == DP_STREAM_1)
  1823. reg_off = DP_DP1_RG - DP_DP0_RG;
  1824. dp_write(DP_DP0_RG + reg_off, rg);
  1825. }
  1826. static void dp_catalog_ctrl_mainlink_levels(struct dp_catalog_ctrl *ctrl,
  1827. u8 lane_cnt)
  1828. {
  1829. struct dp_catalog_private *catalog;
  1830. struct dp_io_data *io_data;
  1831. u32 mainlink_levels, safe_to_exit_level = 14;
  1832. catalog = dp_catalog_get_priv(ctrl);
  1833. io_data = catalog->io.dp_link;
  1834. switch (lane_cnt) {
  1835. case 1:
  1836. safe_to_exit_level = 14;
  1837. break;
  1838. case 2:
  1839. safe_to_exit_level = 8;
  1840. break;
  1841. case 4:
  1842. safe_to_exit_level = 5;
  1843. break;
  1844. default:
  1845. DP_DEBUG("setting the default safe_to_exit_level = %u\n",
  1846. safe_to_exit_level);
  1847. break;
  1848. }
  1849. mainlink_levels = dp_read(DP_MAINLINK_LEVELS);
  1850. mainlink_levels &= 0xFE0;
  1851. mainlink_levels |= safe_to_exit_level;
  1852. DP_DEBUG("mainlink_level = 0x%x, safe_to_exit_level = 0x%x\n",
  1853. mainlink_levels, safe_to_exit_level);
  1854. dp_write(DP_MAINLINK_LEVELS, mainlink_levels);
  1855. }
  1856. /* panel related catalog functions */
  1857. static int dp_catalog_panel_timing_cfg(struct dp_catalog_panel *panel)
  1858. {
  1859. struct dp_catalog_private *catalog;
  1860. struct dp_io_data *io_data;
  1861. u32 offset = 0, reg;
  1862. if (!panel) {
  1863. DP_ERR("invalid input\n");
  1864. goto end;
  1865. }
  1866. if (panel->stream_id >= DP_STREAM_MAX) {
  1867. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1868. goto end;
  1869. }
  1870. catalog = dp_catalog_get_priv(panel);
  1871. io_data = catalog->io.dp_link;
  1872. if (panel->stream_id == DP_STREAM_1)
  1873. offset = DP1_TOTAL_HOR_VER - DP_TOTAL_HOR_VER;
  1874. dp_write(DP_TOTAL_HOR_VER + offset, panel->total);
  1875. dp_write(DP_START_HOR_VER_FROM_SYNC + offset, panel->sync_start);
  1876. dp_write(DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, panel->width_blanking);
  1877. dp_write(DP_ACTIVE_HOR_VER + offset, panel->dp_active);
  1878. if (panel->stream_id == DP_STREAM_0)
  1879. io_data = catalog->io.dp_p0;
  1880. else
  1881. io_data = catalog->io.dp_p1;
  1882. reg = dp_read(MMSS_DP_INTF_CONFIG);
  1883. if (panel->widebus_en)
  1884. reg |= BIT(4);
  1885. else
  1886. reg &= ~BIT(4);
  1887. dp_write(MMSS_DP_INTF_CONFIG, reg);
  1888. end:
  1889. return 0;
  1890. }
  1891. static void dp_catalog_hpd_config_hpd(struct dp_catalog_hpd *hpd, bool en)
  1892. {
  1893. struct dp_catalog_private *catalog;
  1894. struct dp_io_data *io_data;
  1895. if (!hpd) {
  1896. DP_ERR("invalid input\n");
  1897. return;
  1898. }
  1899. catalog = dp_catalog_get_priv(hpd);
  1900. io_data = catalog->io.dp_aux;
  1901. if (en) {
  1902. u32 reftimer = dp_read(DP_DP_HPD_REFTIMER);
  1903. /* Arm only the UNPLUG and HPD_IRQ interrupts */
  1904. dp_write(DP_DP_HPD_INT_ACK, 0xF);
  1905. dp_write(DP_DP_HPD_INT_MASK, 0xA);
  1906. /* Enable REFTIMER to count 1ms */
  1907. reftimer |= BIT(16);
  1908. dp_write(DP_DP_HPD_REFTIMER, reftimer);
  1909. /* Connect_time is 250us & disconnect_time is 2ms */
  1910. dp_write(DP_DP_HPD_EVENT_TIME_0, 0x3E800FA);
  1911. dp_write(DP_DP_HPD_EVENT_TIME_1, 0x1F407D0);
  1912. /* Enable HPD */
  1913. dp_write(DP_DP_HPD_CTRL, 0x1);
  1914. } else {
  1915. /* Disable HPD */
  1916. dp_write(DP_DP_HPD_CTRL, 0x0);
  1917. }
  1918. }
  1919. static u32 dp_catalog_hpd_get_interrupt(struct dp_catalog_hpd *hpd)
  1920. {
  1921. u32 isr = 0;
  1922. struct dp_catalog_private *catalog;
  1923. struct dp_io_data *io_data;
  1924. if (!hpd) {
  1925. DP_ERR("invalid input\n");
  1926. return isr;
  1927. }
  1928. catalog = dp_catalog_get_priv(hpd);
  1929. io_data = catalog->io.dp_aux;
  1930. isr = dp_read(DP_DP_HPD_INT_STATUS);
  1931. dp_write(DP_DP_HPD_INT_ACK, (isr & 0xf));
  1932. return isr;
  1933. }
  1934. static void dp_catalog_audio_init(struct dp_catalog_audio *audio)
  1935. {
  1936. struct dp_catalog_private *catalog;
  1937. static u32 sdp_map[][DP_AUDIO_SDP_HEADER_MAX] = {
  1938. {
  1939. MMSS_DP_AUDIO_STREAM_0,
  1940. MMSS_DP_AUDIO_STREAM_1,
  1941. MMSS_DP_AUDIO_STREAM_1,
  1942. },
  1943. {
  1944. MMSS_DP_AUDIO_TIMESTAMP_0,
  1945. MMSS_DP_AUDIO_TIMESTAMP_1,
  1946. MMSS_DP_AUDIO_TIMESTAMP_1,
  1947. },
  1948. {
  1949. MMSS_DP_AUDIO_INFOFRAME_0,
  1950. MMSS_DP_AUDIO_INFOFRAME_1,
  1951. MMSS_DP_AUDIO_INFOFRAME_1,
  1952. },
  1953. {
  1954. MMSS_DP_AUDIO_COPYMANAGEMENT_0,
  1955. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1956. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1957. },
  1958. {
  1959. MMSS_DP_AUDIO_ISRC_0,
  1960. MMSS_DP_AUDIO_ISRC_1,
  1961. MMSS_DP_AUDIO_ISRC_1,
  1962. },
  1963. };
  1964. if (!audio)
  1965. return;
  1966. catalog = dp_catalog_get_priv(audio);
  1967. catalog->audio_map = sdp_map;
  1968. }
  1969. static void dp_catalog_audio_config_sdp(struct dp_catalog_audio *audio)
  1970. {
  1971. struct dp_catalog_private *catalog;
  1972. struct dp_io_data *io_data;
  1973. u32 sdp_cfg = 0, sdp_cfg_off = 0;
  1974. u32 sdp_cfg2 = 0, sdp_cfg2_off = 0;
  1975. if (!audio)
  1976. return;
  1977. if (audio->stream_id >= DP_STREAM_MAX) {
  1978. DP_ERR("invalid stream id:%d\n", audio->stream_id);
  1979. return;
  1980. }
  1981. if (audio->stream_id == DP_STREAM_1) {
  1982. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  1983. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  1984. }
  1985. catalog = dp_catalog_get_priv(audio);
  1986. io_data = catalog->io.dp_link;
  1987. sdp_cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  1988. /* AUDIO_TIMESTAMP_SDP_EN */
  1989. sdp_cfg |= BIT(1);
  1990. /* AUDIO_STREAM_SDP_EN */
  1991. sdp_cfg |= BIT(2);
  1992. /* AUDIO_COPY_MANAGEMENT_SDP_EN */
  1993. sdp_cfg |= BIT(5);
  1994. /* AUDIO_ISRC_SDP_EN */
  1995. sdp_cfg |= BIT(6);
  1996. /* AUDIO_INFOFRAME_SDP_EN */
  1997. sdp_cfg |= BIT(20);
  1998. DP_DEBUG("sdp_cfg = 0x%x\n", sdp_cfg);
  1999. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, sdp_cfg);
  2000. sdp_cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg_off);
  2001. /* IFRM_REGSRC -> Do not use reg values */
  2002. sdp_cfg2 &= ~BIT(0);
  2003. /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */
  2004. sdp_cfg2 &= ~BIT(1);
  2005. DP_DEBUG("sdp_cfg2 = 0x%x\n", sdp_cfg2);
  2006. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg_off, sdp_cfg2);
  2007. }
  2008. static void dp_catalog_audio_get_header(struct dp_catalog_audio *audio)
  2009. {
  2010. struct dp_catalog_private *catalog;
  2011. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  2012. struct dp_io_data *io_data;
  2013. enum dp_catalog_audio_sdp_type sdp;
  2014. enum dp_catalog_audio_header_type header;
  2015. if (!audio)
  2016. return;
  2017. catalog = dp_catalog_get_priv(audio);
  2018. io_data = catalog->io.dp_link;
  2019. sdp_map = catalog->audio_map;
  2020. sdp = audio->sdp_type;
  2021. header = audio->sdp_header;
  2022. audio->data = dp_read(sdp_map[sdp][header]);
  2023. }
  2024. static void dp_catalog_audio_set_header(struct dp_catalog_audio *audio)
  2025. {
  2026. struct dp_catalog_private *catalog;
  2027. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  2028. struct dp_io_data *io_data;
  2029. enum dp_catalog_audio_sdp_type sdp;
  2030. enum dp_catalog_audio_header_type header;
  2031. u32 data;
  2032. if (!audio)
  2033. return;
  2034. catalog = dp_catalog_get_priv(audio);
  2035. io_data = catalog->io.dp_link;
  2036. sdp_map = catalog->audio_map;
  2037. sdp = audio->sdp_type;
  2038. header = audio->sdp_header;
  2039. data = audio->data;
  2040. dp_write(sdp_map[sdp][header], data);
  2041. }
  2042. static void dp_catalog_audio_config_acr(struct dp_catalog_audio *audio)
  2043. {
  2044. struct dp_catalog_private *catalog;
  2045. struct dp_io_data *io_data;
  2046. u32 acr_ctrl, select;
  2047. catalog = dp_catalog_get_priv(audio);
  2048. select = audio->data;
  2049. io_data = catalog->io.dp_link;
  2050. acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14);
  2051. DP_DEBUG("select = 0x%x, acr_ctrl = 0x%x\n", select, acr_ctrl);
  2052. dp_write(MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl);
  2053. }
  2054. static void dp_catalog_audio_enable(struct dp_catalog_audio *audio)
  2055. {
  2056. struct dp_catalog_private *catalog;
  2057. struct dp_io_data *io_data;
  2058. bool enable;
  2059. u32 audio_ctrl;
  2060. catalog = dp_catalog_get_priv(audio);
  2061. io_data = catalog->io.dp_link;
  2062. enable = !!audio->data;
  2063. audio_ctrl = dp_read(MMSS_DP_AUDIO_CFG);
  2064. if (enable)
  2065. audio_ctrl |= BIT(0);
  2066. else
  2067. audio_ctrl &= ~BIT(0);
  2068. DP_DEBUG("dp_audio_cfg = 0x%x\n", audio_ctrl);
  2069. dp_write(MMSS_DP_AUDIO_CFG, audio_ctrl);
  2070. /* make sure audio engine is disabled */
  2071. wmb();
  2072. }
  2073. static void dp_catalog_config_spd_header(struct dp_catalog_panel *panel)
  2074. {
  2075. struct dp_catalog_private *catalog;
  2076. struct dp_io_data *io_data;
  2077. u32 value, new_value, offset = 0;
  2078. u8 parity_byte;
  2079. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  2080. return;
  2081. catalog = dp_catalog_get_priv(panel);
  2082. io_data = catalog->io.dp_link;
  2083. if (panel->stream_id == DP_STREAM_1)
  2084. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  2085. /* Config header and parity byte 1 */
  2086. value = dp_read(MMSS_DP_GENERIC1_0 + offset);
  2087. new_value = 0x83;
  2088. parity_byte = dp_header_get_parity(new_value);
  2089. value |= ((new_value << HEADER_BYTE_1_BIT)
  2090. | (parity_byte << PARITY_BYTE_1_BIT));
  2091. DP_DEBUG("Header Byte 1: value = 0x%x, parity_byte = 0x%x\n",
  2092. value, parity_byte);
  2093. dp_write(MMSS_DP_GENERIC1_0 + offset, value);
  2094. /* Config header and parity byte 2 */
  2095. value = dp_read(MMSS_DP_GENERIC1_1 + offset);
  2096. new_value = 0x1b;
  2097. parity_byte = dp_header_get_parity(new_value);
  2098. value |= ((new_value << HEADER_BYTE_2_BIT)
  2099. | (parity_byte << PARITY_BYTE_2_BIT));
  2100. DP_DEBUG("Header Byte 2: value = 0x%x, parity_byte = 0x%x\n",
  2101. value, parity_byte);
  2102. dp_write(MMSS_DP_GENERIC1_1 + offset, value);
  2103. /* Config header and parity byte 3 */
  2104. value = dp_read(MMSS_DP_GENERIC1_1 + offset);
  2105. new_value = (0x0 | (0x12 << 2));
  2106. parity_byte = dp_header_get_parity(new_value);
  2107. value |= ((new_value << HEADER_BYTE_3_BIT)
  2108. | (parity_byte << PARITY_BYTE_3_BIT));
  2109. DP_DEBUG("Header Byte 3: value = 0x%x, parity_byte = 0x%x\n",
  2110. new_value, parity_byte);
  2111. dp_write(MMSS_DP_GENERIC1_1 + offset, value);
  2112. }
  2113. static void dp_catalog_panel_config_spd(struct dp_catalog_panel *panel)
  2114. {
  2115. struct dp_catalog_private *catalog;
  2116. struct dp_io_data *io_data;
  2117. u32 spd_cfg = 0, spd_cfg2 = 0;
  2118. u8 *vendor = NULL, *product = NULL;
  2119. u32 offset = 0;
  2120. u32 sdp_cfg_off = 0;
  2121. u32 sdp_cfg2_off = 0;
  2122. /*
  2123. * Source Device Information
  2124. * 00h unknown
  2125. * 01h Digital STB
  2126. * 02h DVD
  2127. * 03h D-VHS
  2128. * 04h HDD Video
  2129. * 05h DVC
  2130. * 06h DSC
  2131. * 07h Video CD
  2132. * 08h Game
  2133. * 09h PC general
  2134. * 0ah Bluray-Disc
  2135. * 0bh Super Audio CD
  2136. * 0ch HD DVD
  2137. * 0dh PMP
  2138. * 0eh-ffh reserved
  2139. */
  2140. u32 device_type = 0;
  2141. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  2142. return;
  2143. catalog = dp_catalog_get_priv(panel);
  2144. io_data = catalog->io.dp_link;
  2145. if (panel->stream_id == DP_STREAM_1)
  2146. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  2147. dp_catalog_config_spd_header(panel);
  2148. vendor = panel->spd_vendor_name;
  2149. product = panel->spd_product_description;
  2150. dp_write(MMSS_DP_GENERIC1_2 + offset,
  2151. ((vendor[0] & 0x7f) |
  2152. ((vendor[1] & 0x7f) << 8) |
  2153. ((vendor[2] & 0x7f) << 16) |
  2154. ((vendor[3] & 0x7f) << 24)));
  2155. dp_write(MMSS_DP_GENERIC1_3 + offset,
  2156. ((vendor[4] & 0x7f) |
  2157. ((vendor[5] & 0x7f) << 8) |
  2158. ((vendor[6] & 0x7f) << 16) |
  2159. ((vendor[7] & 0x7f) << 24)));
  2160. dp_write(MMSS_DP_GENERIC1_4 + offset,
  2161. ((product[0] & 0x7f) |
  2162. ((product[1] & 0x7f) << 8) |
  2163. ((product[2] & 0x7f) << 16) |
  2164. ((product[3] & 0x7f) << 24)));
  2165. dp_write(MMSS_DP_GENERIC1_5 + offset,
  2166. ((product[4] & 0x7f) |
  2167. ((product[5] & 0x7f) << 8) |
  2168. ((product[6] & 0x7f) << 16) |
  2169. ((product[7] & 0x7f) << 24)));
  2170. dp_write(MMSS_DP_GENERIC1_6 + offset,
  2171. ((product[8] & 0x7f) |
  2172. ((product[9] & 0x7f) << 8) |
  2173. ((product[10] & 0x7f) << 16) |
  2174. ((product[11] & 0x7f) << 24)));
  2175. dp_write(MMSS_DP_GENERIC1_7 + offset,
  2176. ((product[12] & 0x7f) |
  2177. ((product[13] & 0x7f) << 8) |
  2178. ((product[14] & 0x7f) << 16) |
  2179. ((product[15] & 0x7f) << 24)));
  2180. dp_write(MMSS_DP_GENERIC1_8 + offset, device_type);
  2181. dp_write(MMSS_DP_GENERIC1_9 + offset, 0x00);
  2182. if (panel->stream_id == DP_STREAM_1) {
  2183. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  2184. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  2185. }
  2186. spd_cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  2187. /* GENERIC1_SDP for SPD Infoframe */
  2188. spd_cfg |= BIT(18);
  2189. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, spd_cfg);
  2190. spd_cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  2191. /* 28 data bytes for SPD Infoframe with GENERIC1 set */
  2192. spd_cfg2 |= BIT(17);
  2193. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, spd_cfg2);
  2194. dp_catalog_panel_sdp_update(panel);
  2195. }
  2196. static void dp_catalog_get_io_buf(struct dp_catalog_private *catalog)
  2197. {
  2198. struct dp_parser *parser = catalog->parser;
  2199. dp_catalog_fill_io_buf(dp_ahb);
  2200. dp_catalog_fill_io_buf(dp_aux);
  2201. dp_catalog_fill_io_buf(dp_link);
  2202. dp_catalog_fill_io_buf(dp_p0);
  2203. dp_catalog_fill_io_buf(dp_phy);
  2204. dp_catalog_fill_io_buf(dp_ln_tx0);
  2205. dp_catalog_fill_io_buf(dp_ln_tx1);
  2206. dp_catalog_fill_io_buf(dp_pll);
  2207. dp_catalog_fill_io_buf(usb3_dp_com);
  2208. dp_catalog_fill_io_buf(dp_mmss_cc);
  2209. dp_catalog_fill_io_buf(hdcp_physical);
  2210. dp_catalog_fill_io_buf(dp_p1);
  2211. dp_catalog_fill_io_buf(dp_tcsr);
  2212. }
  2213. static void dp_catalog_get_io(struct dp_catalog_private *catalog)
  2214. {
  2215. struct dp_parser *parser = catalog->parser;
  2216. dp_catalog_fill_io(dp_ahb);
  2217. dp_catalog_fill_io(dp_aux);
  2218. dp_catalog_fill_io(dp_link);
  2219. dp_catalog_fill_io(dp_p0);
  2220. dp_catalog_fill_io(dp_phy);
  2221. dp_catalog_fill_io(dp_ln_tx0);
  2222. dp_catalog_fill_io(dp_ln_tx1);
  2223. dp_catalog_fill_io(dp_pll);
  2224. dp_catalog_fill_io(usb3_dp_com);
  2225. dp_catalog_fill_io(dp_mmss_cc);
  2226. dp_catalog_fill_io(hdcp_physical);
  2227. dp_catalog_fill_io(dp_p1);
  2228. dp_catalog_fill_io(dp_tcsr);
  2229. }
  2230. static void dp_catalog_set_exe_mode(struct dp_catalog *dp_catalog, char *mode)
  2231. {
  2232. struct dp_catalog_private *catalog;
  2233. if (!dp_catalog) {
  2234. DP_ERR("invalid input\n");
  2235. return;
  2236. }
  2237. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2238. dp_catalog);
  2239. strlcpy(catalog->exe_mode, mode, sizeof(catalog->exe_mode));
  2240. if (!strcmp(catalog->exe_mode, "hw"))
  2241. catalog->parser->clear_io_buf(catalog->parser);
  2242. else
  2243. dp_catalog_get_io_buf(catalog);
  2244. if (!strcmp(catalog->exe_mode, "hw") ||
  2245. !strcmp(catalog->exe_mode, "all")) {
  2246. catalog->read = dp_read_hw;
  2247. catalog->write = dp_write_hw;
  2248. dp_catalog->sub->read = dp_read_sub_hw;
  2249. dp_catalog->sub->write = dp_write_sub_hw;
  2250. } else {
  2251. catalog->read = dp_read_sw;
  2252. catalog->write = dp_write_sw;
  2253. dp_catalog->sub->read = dp_read_sub_sw;
  2254. dp_catalog->sub->write = dp_write_sub_sw;
  2255. }
  2256. }
  2257. static int dp_catalog_init(struct device *dev, struct dp_catalog *dp_catalog,
  2258. struct dp_parser *parser)
  2259. {
  2260. int rc = 0;
  2261. struct dp_catalog_private *catalog = container_of(dp_catalog,
  2262. struct dp_catalog_private, dp_catalog);
  2263. if (parser->hw_cfg.phy_version >= DP_PHY_VERSION_4_2_0)
  2264. dp_catalog->sub = dp_catalog_get_v420(dev, dp_catalog, &catalog->io);
  2265. else if (parser->hw_cfg.phy_version == DP_PHY_VERSION_2_0_0)
  2266. dp_catalog->sub = dp_catalog_get_v200(dev, dp_catalog, &catalog->io);
  2267. else
  2268. goto end;
  2269. if (IS_ERR(dp_catalog->sub)) {
  2270. rc = PTR_ERR(dp_catalog->sub);
  2271. dp_catalog->sub = NULL;
  2272. } else {
  2273. dp_catalog->sub->read = dp_read_sub_hw;
  2274. dp_catalog->sub->write = dp_write_sub_hw;
  2275. }
  2276. end:
  2277. return rc;
  2278. }
  2279. void dp_catalog_put(struct dp_catalog *dp_catalog)
  2280. {
  2281. struct dp_catalog_private *catalog;
  2282. if (!dp_catalog)
  2283. return;
  2284. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2285. dp_catalog);
  2286. if (dp_catalog->sub && dp_catalog->sub->put)
  2287. dp_catalog->sub->put(dp_catalog);
  2288. catalog->parser->clear_io_buf(catalog->parser);
  2289. devm_kfree(catalog->dev, catalog);
  2290. }
  2291. struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser)
  2292. {
  2293. int rc = 0;
  2294. struct dp_catalog *dp_catalog;
  2295. struct dp_catalog_private *catalog;
  2296. struct dp_catalog_aux aux = {
  2297. .read_data = dp_catalog_aux_read_data,
  2298. .write_data = dp_catalog_aux_write_data,
  2299. .write_trans = dp_catalog_aux_write_trans,
  2300. .clear_trans = dp_catalog_aux_clear_trans,
  2301. .reset = dp_catalog_aux_reset,
  2302. .update_aux_cfg = dp_catalog_aux_update_cfg,
  2303. .enable = dp_catalog_aux_enable,
  2304. .setup = dp_catalog_aux_setup,
  2305. .get_irq = dp_catalog_aux_get_irq,
  2306. .clear_hw_interrupts = dp_catalog_aux_clear_hw_interrupts,
  2307. };
  2308. struct dp_catalog_ctrl ctrl = {
  2309. .state_ctrl = dp_catalog_ctrl_state_ctrl,
  2310. .config_ctrl = dp_catalog_ctrl_config_ctrl,
  2311. .lane_mapping = dp_catalog_ctrl_lane_mapping,
  2312. .lane_pnswap = dp_catalog_ctrl_lane_pnswap,
  2313. .mainlink_ctrl = dp_catalog_ctrl_mainlink_ctrl,
  2314. .set_pattern = dp_catalog_ctrl_set_pattern,
  2315. .reset = dp_catalog_ctrl_reset,
  2316. .usb_reset = dp_catalog_ctrl_usb_reset,
  2317. .mainlink_ready = dp_catalog_ctrl_mainlink_ready,
  2318. .enable_irq = dp_catalog_ctrl_enable_irq,
  2319. .phy_reset = dp_catalog_ctrl_phy_reset,
  2320. .phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg,
  2321. .update_vx_px = dp_catalog_ctrl_update_vx_px,
  2322. .get_interrupt = dp_catalog_ctrl_get_interrupt,
  2323. .read_hdcp_status = dp_catalog_ctrl_read_hdcp_status,
  2324. .send_phy_pattern = dp_catalog_ctrl_send_phy_pattern,
  2325. .read_phy_pattern = dp_catalog_ctrl_read_phy_pattern,
  2326. .mst_config = dp_catalog_ctrl_mst_config,
  2327. .trigger_act = dp_catalog_ctrl_trigger_act,
  2328. .read_act_complete_sts = dp_catalog_ctrl_read_act_complete_sts,
  2329. .channel_alloc = dp_catalog_ctrl_channel_alloc,
  2330. .update_rg = dp_catalog_ctrl_update_rg,
  2331. .channel_dealloc = dp_catalog_ctrl_channel_dealloc,
  2332. .fec_config = dp_catalog_ctrl_fec_config,
  2333. .mainlink_levels = dp_catalog_ctrl_mainlink_levels,
  2334. .late_phy_init = dp_catalog_ctrl_late_phy_init,
  2335. };
  2336. struct dp_catalog_hpd hpd = {
  2337. .config_hpd = dp_catalog_hpd_config_hpd,
  2338. .get_interrupt = dp_catalog_hpd_get_interrupt,
  2339. };
  2340. struct dp_catalog_audio audio = {
  2341. .init = dp_catalog_audio_init,
  2342. .config_acr = dp_catalog_audio_config_acr,
  2343. .enable = dp_catalog_audio_enable,
  2344. .config_sdp = dp_catalog_audio_config_sdp,
  2345. .set_header = dp_catalog_audio_set_header,
  2346. .get_header = dp_catalog_audio_get_header,
  2347. };
  2348. struct dp_catalog_panel panel = {
  2349. .timing_cfg = dp_catalog_panel_timing_cfg,
  2350. .config_hdr = dp_catalog_panel_config_hdr,
  2351. .config_sdp = dp_catalog_panel_config_sdp,
  2352. .tpg_config = dp_catalog_panel_tpg_cfg,
  2353. .config_spd = dp_catalog_panel_config_spd,
  2354. .config_misc = dp_catalog_panel_config_misc,
  2355. .set_colorspace = dp_catalog_panel_set_colorspace,
  2356. .config_msa = dp_catalog_panel_config_msa,
  2357. .update_transfer_unit = dp_catalog_panel_update_transfer_unit,
  2358. .config_ctrl = dp_catalog_panel_config_ctrl,
  2359. .config_dto = dp_catalog_panel_config_dto,
  2360. .dsc_cfg = dp_catalog_panel_dsc_cfg,
  2361. .pps_flush = dp_catalog_panel_pps_flush,
  2362. .dhdr_flush = dp_catalog_panel_dhdr_flush,
  2363. .dhdr_busy = dp_catalog_panel_dhdr_busy,
  2364. };
  2365. if (!dev || !parser) {
  2366. DP_ERR("invalid input\n");
  2367. rc = -EINVAL;
  2368. goto error;
  2369. }
  2370. catalog = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL);
  2371. if (!catalog) {
  2372. rc = -ENOMEM;
  2373. goto error;
  2374. }
  2375. catalog->dev = dev;
  2376. catalog->parser = parser;
  2377. catalog->read = dp_read_hw;
  2378. catalog->write = dp_write_hw;
  2379. dp_catalog_get_io(catalog);
  2380. strlcpy(catalog->exe_mode, "hw", sizeof(catalog->exe_mode));
  2381. dp_catalog = &catalog->dp_catalog;
  2382. dp_catalog->aux = aux;
  2383. dp_catalog->ctrl = ctrl;
  2384. dp_catalog->hpd = hpd;
  2385. dp_catalog->audio = audio;
  2386. dp_catalog->panel = panel;
  2387. rc = dp_catalog_init(dev, dp_catalog, parser);
  2388. if (rc) {
  2389. dp_catalog_put(dp_catalog);
  2390. goto error;
  2391. }
  2392. dp_catalog->set_exe_mode = dp_catalog_set_exe_mode;
  2393. dp_catalog->get_reg_dump = dp_catalog_reg_dump;
  2394. return dp_catalog;
  2395. error:
  2396. return ERR_PTR(rc);
  2397. }