dp_aux.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/soc/qcom/fsa4480-i2c.h>
  7. #include <linux/delay.h>
  8. #include "dp_aux.h"
  9. #include "dp_hpd.h"
  10. #include "dp_debug.h"
  11. #define DP_AUX_ENUM_STR(x) #x
  12. #define DP_AUX_IPC_NUM_PAGES 10
  13. #define DP_AUX_DEBUG(dp_aux, fmt, ...) \
  14. do { \
  15. if (dp_aux) \
  16. ipc_log_string(dp_aux->ipc_log_context, "[d][%-4d]"fmt,\
  17. current->pid, ##__VA_ARGS__); \
  18. DP_DEBUG_V(fmt, ##__VA_ARGS__); \
  19. } while (0)
  20. #define DP_AUX_WARN(dp_aux, fmt, ...) \
  21. do { \
  22. if (dp_aux) \
  23. ipc_log_string(dp_aux->ipc_log_context, "[w][%-4d]"fmt,\
  24. current->pid, ##__VA_ARGS__); \
  25. DP_WARN_V(fmt, ##__VA_ARGS__); \
  26. } while (0)
  27. #define DP_AUX_ERR(dp_aux, fmt, ...) \
  28. do { \
  29. if (dp_aux) \
  30. ipc_log_string(dp_aux->ipc_log_context, "[e][%-4d]"fmt,\
  31. current->pid, ##__VA_ARGS__); \
  32. DP_ERR_V(fmt, ##__VA_ARGS__); \
  33. } while (0)
  34. enum {
  35. DP_AUX_DATA_INDEX_WRITE = BIT(31),
  36. };
  37. struct dp_aux_private {
  38. struct device *dev;
  39. struct dp_aux dp_aux;
  40. struct dp_catalog_aux *catalog;
  41. struct dp_aux_cfg *cfg;
  42. struct device_node *aux_switch_node;
  43. struct mutex mutex;
  44. struct completion comp;
  45. struct drm_dp_aux drm_aux;
  46. struct dp_aux_bridge *aux_bridge;
  47. struct dp_aux_bridge *sim_bridge;
  48. bool bridge_in_transfer;
  49. bool sim_in_transfer;
  50. bool cmd_busy;
  51. bool native;
  52. bool read;
  53. bool no_send_addr;
  54. bool no_send_stop;
  55. bool enabled;
  56. u32 offset;
  57. u32 segment;
  58. u32 aux_error_num;
  59. u32 retry_cnt;
  60. atomic_t aborted;
  61. };
  62. #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG)
  63. static void dp_aux_hex_dump(struct drm_dp_aux *drm_aux,
  64. struct drm_dp_aux_msg *msg)
  65. {
  66. char prefix[64];
  67. int i, linelen, remaining = msg->size;
  68. const int rowsize = 16;
  69. u8 linebuf[64];
  70. struct dp_aux_private *aux = container_of(drm_aux,
  71. struct dp_aux_private, drm_aux);
  72. struct dp_aux *dp_aux = &aux->dp_aux;
  73. snprintf(prefix, sizeof(prefix), "%s %s %4xh(%2zu): ",
  74. (msg->request & DP_AUX_I2C_MOT) ? "I2C" : "NAT",
  75. (msg->request & DP_AUX_I2C_READ) ? "RD" : "WR",
  76. msg->address, msg->size);
  77. for (i = 0; i < msg->size; i += rowsize) {
  78. linelen = min(remaining, rowsize);
  79. remaining -= rowsize;
  80. hex_dump_to_buffer(msg->buffer + i, linelen, rowsize, 1,
  81. linebuf, sizeof(linebuf), false);
  82. if (msg->size == 1 && msg->address == 0)
  83. DP_DEBUG_V("%s%s\n", prefix, linebuf);
  84. else
  85. DP_AUX_DEBUG(dp_aux, "%s%s\n", prefix, linebuf);
  86. }
  87. }
  88. #else
  89. static void dp_aux_hex_dump(struct drm_dp_aux *drm_aux,
  90. struct drm_dp_aux_msg *msg)
  91. {
  92. }
  93. #endif /* CONFIG_DYNAMIC_DEBUG */
  94. static char *dp_aux_get_error(u32 aux_error)
  95. {
  96. switch (aux_error) {
  97. case DP_AUX_ERR_NONE:
  98. return DP_AUX_ENUM_STR(DP_AUX_ERR_NONE);
  99. case DP_AUX_ERR_ADDR:
  100. return DP_AUX_ENUM_STR(DP_AUX_ERR_ADDR);
  101. case DP_AUX_ERR_TOUT:
  102. return DP_AUX_ENUM_STR(DP_AUX_ERR_TOUT);
  103. case DP_AUX_ERR_NACK:
  104. return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK);
  105. case DP_AUX_ERR_DEFER:
  106. return DP_AUX_ENUM_STR(DP_AUX_ERR_DEFER);
  107. case DP_AUX_ERR_NACK_DEFER:
  108. return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK_DEFER);
  109. default:
  110. return "unknown";
  111. }
  112. }
  113. static u32 dp_aux_write(struct dp_aux_private *aux,
  114. struct drm_dp_aux_msg *msg)
  115. {
  116. u32 data[4], reg, len;
  117. u8 *msgdata = msg->buffer;
  118. int const aux_cmd_fifo_len = 128;
  119. int i = 0;
  120. struct dp_aux *dp_aux = &aux->dp_aux;
  121. if (aux->read)
  122. len = 4;
  123. else
  124. len = msg->size + 4;
  125. /*
  126. * cmd fifo only has depth of 144 bytes
  127. * limit buf length to 128 bytes here
  128. */
  129. if (len > aux_cmd_fifo_len) {
  130. DP_AUX_ERR(dp_aux, "buf len error\n");
  131. return 0;
  132. }
  133. /* Pack cmd and write to HW */
  134. data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
  135. if (aux->read)
  136. data[0] |= BIT(4); /* R/W */
  137. data[1] = (msg->address >> 8) & 0xff; /* addr[15:8] */
  138. data[2] = msg->address & 0xff; /* addr[7:0] */
  139. data[3] = (msg->size - 1) & 0xff; /* len[7:0] */
  140. for (i = 0; i < len; i++) {
  141. reg = (i < 4) ? data[i] : msgdata[i - 4];
  142. reg = ((reg) << 8) & 0x0000ff00; /* index = 0, write */
  143. if (i == 0)
  144. reg |= DP_AUX_DATA_INDEX_WRITE;
  145. aux->catalog->data = reg;
  146. aux->catalog->write_data(aux->catalog);
  147. }
  148. aux->catalog->clear_trans(aux->catalog, false);
  149. aux->catalog->clear_hw_interrupts(aux->catalog);
  150. reg = 0; /* Transaction number == 1 */
  151. if (!aux->native) { /* i2c */
  152. reg |= BIT(8);
  153. if (aux->no_send_addr)
  154. reg |= BIT(10);
  155. if (aux->no_send_stop)
  156. reg |= BIT(11);
  157. }
  158. reg |= BIT(9);
  159. aux->catalog->data = reg;
  160. aux->catalog->write_trans(aux->catalog);
  161. return len;
  162. }
  163. static int dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
  164. struct drm_dp_aux_msg *msg)
  165. {
  166. u32 ret = 0, len = 0, timeout;
  167. int const aux_timeout_ms = HZ/4;
  168. struct dp_aux *dp_aux = &aux->dp_aux;
  169. reinit_completion(&aux->comp);
  170. len = dp_aux_write(aux, msg);
  171. if (len == 0) {
  172. DP_AUX_ERR(dp_aux, "DP AUX write failed\n");
  173. return -EINVAL;
  174. }
  175. timeout = wait_for_completion_timeout(&aux->comp, aux_timeout_ms);
  176. if (!timeout) {
  177. DP_AUX_ERR(dp_aux, "aux %s timeout\n", (aux->read ? "read" : "write"));
  178. return -ETIMEDOUT;
  179. }
  180. if (aux->aux_error_num == DP_AUX_ERR_NONE) {
  181. ret = len;
  182. } else {
  183. pr_err_ratelimited("aux err: %s\n",
  184. dp_aux_get_error(aux->aux_error_num));
  185. ret = -EINVAL;
  186. }
  187. return ret;
  188. }
  189. static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
  190. struct drm_dp_aux_msg *msg)
  191. {
  192. u32 data;
  193. u8 *dp;
  194. u32 i, actual_i;
  195. u32 len = msg->size;
  196. struct dp_aux *dp_aux = &aux->dp_aux;
  197. aux->catalog->clear_trans(aux->catalog, true);
  198. data = 0;
  199. data |= DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */
  200. data |= BIT(0); /* read */
  201. aux->catalog->data = data;
  202. aux->catalog->write_data(aux->catalog);
  203. dp = msg->buffer;
  204. /* discard first byte */
  205. data = aux->catalog->read_data(aux->catalog);
  206. for (i = 0; i < len; i++) {
  207. data = aux->catalog->read_data(aux->catalog);
  208. *dp++ = (u8)((data >> 8) & 0xff);
  209. actual_i = (data >> 16) & 0xFF;
  210. if (i != actual_i)
  211. DP_AUX_WARN(dp_aux, "Index mismatch: expected %d, found %d\n",
  212. i, actual_i);
  213. }
  214. }
  215. static void dp_aux_native_handler(struct dp_aux_private *aux)
  216. {
  217. u32 isr = aux->catalog->isr;
  218. if (isr & DP_INTR_AUX_I2C_DONE)
  219. aux->aux_error_num = DP_AUX_ERR_NONE;
  220. else if (isr & DP_INTR_WRONG_ADDR)
  221. aux->aux_error_num = DP_AUX_ERR_ADDR;
  222. else if (isr & DP_INTR_TIMEOUT)
  223. aux->aux_error_num = DP_AUX_ERR_TOUT;
  224. if (isr & DP_INTR_NACK_DEFER)
  225. aux->aux_error_num = DP_AUX_ERR_NACK;
  226. if (isr & DP_INTR_AUX_ERROR) {
  227. aux->aux_error_num = DP_AUX_ERR_PHY;
  228. aux->catalog->clear_hw_interrupts(aux->catalog);
  229. }
  230. complete(&aux->comp);
  231. }
  232. static void dp_aux_i2c_handler(struct dp_aux_private *aux)
  233. {
  234. u32 isr = aux->catalog->isr;
  235. if (isr & DP_INTR_AUX_I2C_DONE) {
  236. if (isr & (DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER))
  237. aux->aux_error_num = DP_AUX_ERR_NACK;
  238. else
  239. aux->aux_error_num = DP_AUX_ERR_NONE;
  240. } else {
  241. if (isr & DP_INTR_WRONG_ADDR)
  242. aux->aux_error_num = DP_AUX_ERR_ADDR;
  243. else if (isr & DP_INTR_TIMEOUT)
  244. aux->aux_error_num = DP_AUX_ERR_TOUT;
  245. if (isr & DP_INTR_NACK_DEFER)
  246. aux->aux_error_num = DP_AUX_ERR_NACK_DEFER;
  247. if (isr & DP_INTR_I2C_NACK)
  248. aux->aux_error_num = DP_AUX_ERR_NACK;
  249. if (isr & DP_INTR_I2C_DEFER)
  250. aux->aux_error_num = DP_AUX_ERR_DEFER;
  251. if (isr & DP_INTR_AUX_ERROR) {
  252. aux->aux_error_num = DP_AUX_ERR_PHY;
  253. aux->catalog->clear_hw_interrupts(aux->catalog);
  254. }
  255. }
  256. complete(&aux->comp);
  257. }
  258. static void dp_aux_isr(struct dp_aux *dp_aux)
  259. {
  260. struct dp_aux_private *aux;
  261. if (!dp_aux) {
  262. DP_AUX_ERR(dp_aux, "invalid input\n");
  263. return;
  264. }
  265. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  266. aux->catalog->get_irq(aux->catalog, aux->cmd_busy);
  267. if (!aux->cmd_busy)
  268. return;
  269. if (aux->native)
  270. dp_aux_native_handler(aux);
  271. else
  272. dp_aux_i2c_handler(aux);
  273. }
  274. static void dp_aux_reconfig(struct dp_aux *dp_aux)
  275. {
  276. struct dp_aux_private *aux;
  277. if (!dp_aux) {
  278. DP_AUX_ERR(dp_aux, "invalid input\n");
  279. return;
  280. }
  281. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  282. aux->catalog->update_aux_cfg(aux->catalog,
  283. aux->cfg, PHY_AUX_CFG1);
  284. aux->catalog->reset(aux->catalog);
  285. }
  286. static void dp_aux_abort_transaction(struct dp_aux *dp_aux, bool abort)
  287. {
  288. struct dp_aux_private *aux;
  289. if (!dp_aux) {
  290. DP_AUX_ERR(dp_aux, "invalid input\n");
  291. return;
  292. }
  293. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  294. atomic_set(&aux->aborted, abort);
  295. }
  296. static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux,
  297. struct drm_dp_aux_msg *input_msg)
  298. {
  299. u32 const edid_address = 0x50;
  300. u32 const segment_address = 0x30;
  301. bool i2c_read = input_msg->request &
  302. (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
  303. u8 *data = NULL;
  304. if (aux->native || i2c_read || ((input_msg->address != edid_address) &&
  305. (input_msg->address != segment_address)))
  306. return;
  307. data = input_msg->buffer;
  308. if (input_msg->address == segment_address)
  309. aux->segment = *data;
  310. else
  311. aux->offset = *data;
  312. }
  313. /**
  314. * dp_aux_transfer_helper() - helper function for EDID read transactions
  315. *
  316. * @aux: DP AUX private structure
  317. * @input_msg: input message from DRM upstream APIs
  318. * @send_seg: send the seg to sink
  319. *
  320. * return: void
  321. *
  322. * This helper function is used to fix EDID reads for non-compliant
  323. * sinks that do not handle the i2c middle-of-transaction flag correctly.
  324. */
  325. static void dp_aux_transfer_helper(struct dp_aux_private *aux,
  326. struct drm_dp_aux_msg *input_msg, bool send_seg)
  327. {
  328. struct drm_dp_aux_msg helper_msg;
  329. u32 const message_size = 0x10;
  330. u32 const segment_address = 0x30;
  331. u32 const edid_block_length = 0x80;
  332. bool i2c_mot = input_msg->request & DP_AUX_I2C_MOT;
  333. bool i2c_read = input_msg->request &
  334. (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
  335. if (!i2c_mot || !i2c_read || (input_msg->size == 0))
  336. return;
  337. /*
  338. * Sending the segment value and EDID offset will be performed
  339. * from the DRM upstream EDID driver for each block. Avoid
  340. * duplicate AUX transactions related to this while reading the
  341. * first 16 bytes of each block.
  342. */
  343. if (!(aux->offset % edid_block_length) || !send_seg)
  344. goto end;
  345. aux->read = false;
  346. aux->cmd_busy = true;
  347. aux->no_send_addr = true;
  348. aux->no_send_stop = true;
  349. /*
  350. * Send the segment address for i2c reads for segment > 0 and for which
  351. * the middle-of-transaction flag is set. This is required to support
  352. * EDID reads of more than 2 blocks as the segment address is reset to 0
  353. * since we are overriding the middle-of-transaction flag for read
  354. * transactions.
  355. */
  356. if (aux->segment) {
  357. memset(&helper_msg, 0, sizeof(helper_msg));
  358. helper_msg.address = segment_address;
  359. helper_msg.buffer = &aux->segment;
  360. helper_msg.size = 1;
  361. dp_aux_cmd_fifo_tx(aux, &helper_msg);
  362. }
  363. /*
  364. * Send the offset address for every i2c read in which the
  365. * middle-of-transaction flag is set. This will ensure that the sink
  366. * will update its read pointer and return the correct portion of the
  367. * EDID buffer in the subsequent i2c read trasntion triggered in the
  368. * native AUX transfer function.
  369. */
  370. memset(&helper_msg, 0, sizeof(helper_msg));
  371. helper_msg.address = input_msg->address;
  372. helper_msg.buffer = &aux->offset;
  373. helper_msg.size = 1;
  374. dp_aux_cmd_fifo_tx(aux, &helper_msg);
  375. end:
  376. aux->offset += message_size;
  377. if (aux->offset == 0x80 || aux->offset == 0x100)
  378. aux->segment = 0x0; /* reset segment at end of block */
  379. }
  380. static int dp_aux_transfer_ready(struct dp_aux_private *aux,
  381. struct drm_dp_aux_msg *msg, bool send_seg)
  382. {
  383. int ret = 0;
  384. int const aux_cmd_native_max = 16;
  385. int const aux_cmd_i2c_max = 128;
  386. struct dp_aux *dp_aux = &aux->dp_aux;
  387. if (atomic_read(&aux->aborted)) {
  388. ret = -ETIMEDOUT;
  389. goto error;
  390. }
  391. aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
  392. /* Ignore address only message */
  393. if ((msg->size == 0) || (msg->buffer == NULL)) {
  394. msg->reply = aux->native ?
  395. DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
  396. goto error;
  397. }
  398. /* msg sanity check */
  399. if ((aux->native && (msg->size > aux_cmd_native_max)) ||
  400. (msg->size > aux_cmd_i2c_max)) {
  401. DP_AUX_ERR(dp_aux, "%s: invalid msg: size(%zu), request(%x)\n",
  402. __func__, msg->size, msg->request);
  403. ret = -EINVAL;
  404. goto error;
  405. }
  406. dp_aux_update_offset_and_segment(aux, msg);
  407. dp_aux_transfer_helper(aux, msg, send_seg);
  408. aux->read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
  409. if (aux->read) {
  410. aux->no_send_addr = true;
  411. aux->no_send_stop = false;
  412. } else {
  413. aux->no_send_addr = true;
  414. aux->no_send_stop = true;
  415. }
  416. aux->cmd_busy = true;
  417. error:
  418. return ret;
  419. }
  420. static inline bool dp_aux_is_sideband_msg(u32 address, size_t size)
  421. {
  422. return (address >= 0x1000 && address + size < 0x1800) ||
  423. (address >= 0x2000 && address + size < 0x2200);
  424. }
  425. /*
  426. * This function does the real job to process an AUX transaction.
  427. * It will call aux_reset() function to reset the AUX channel,
  428. * if the waiting is timeout.
  429. */
  430. static ssize_t dp_aux_transfer(struct drm_dp_aux *drm_aux,
  431. struct drm_dp_aux_msg *msg)
  432. {
  433. ssize_t ret;
  434. int const retry_count = 5;
  435. struct dp_aux_private *aux = container_of(drm_aux,
  436. struct dp_aux_private, drm_aux);
  437. mutex_lock(&aux->mutex);
  438. ret = dp_aux_transfer_ready(aux, msg, true);
  439. if (ret)
  440. goto unlock_exit;
  441. if (!aux->cmd_busy) {
  442. ret = msg->size;
  443. goto unlock_exit;
  444. }
  445. ret = dp_aux_cmd_fifo_tx(aux, msg);
  446. if ((ret < 0) && !atomic_read(&aux->aborted)) {
  447. aux->retry_cnt++;
  448. if (!(aux->retry_cnt % retry_count))
  449. aux->catalog->update_aux_cfg(aux->catalog,
  450. aux->cfg, PHY_AUX_CFG1);
  451. aux->catalog->reset(aux->catalog);
  452. goto unlock_exit;
  453. } else if (ret < 0) {
  454. goto unlock_exit;
  455. }
  456. if (aux->aux_error_num == DP_AUX_ERR_NONE) {
  457. if (aux->read)
  458. dp_aux_cmd_fifo_rx(aux, msg);
  459. dp_aux_hex_dump(drm_aux, msg);
  460. msg->reply = aux->native ?
  461. DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
  462. } else {
  463. /* Reply defer to retry */
  464. msg->reply = aux->native ?
  465. DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
  466. }
  467. /* Return requested size for success or retry */
  468. ret = msg->size;
  469. aux->retry_cnt = 0;
  470. unlock_exit:
  471. aux->cmd_busy = false;
  472. mutex_unlock(&aux->mutex);
  473. return ret;
  474. }
  475. static ssize_t dp_aux_bridge_transfer(struct drm_dp_aux *drm_aux,
  476. struct drm_dp_aux_msg *msg)
  477. {
  478. struct dp_aux_private *aux = container_of(drm_aux,
  479. struct dp_aux_private, drm_aux);
  480. ssize_t size;
  481. if (aux->bridge_in_transfer) {
  482. size = dp_aux_transfer(drm_aux, msg);
  483. } else {
  484. aux->bridge_in_transfer = true;
  485. size = aux->aux_bridge->transfer(aux->aux_bridge,
  486. drm_aux, msg);
  487. aux->bridge_in_transfer = false;
  488. dp_aux_hex_dump(drm_aux, msg);
  489. }
  490. return size;
  491. }
  492. static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux,
  493. struct drm_dp_aux_msg *msg)
  494. {
  495. struct dp_aux_private *aux = container_of(drm_aux,
  496. struct dp_aux_private, drm_aux);
  497. ssize_t size;
  498. int aborted;
  499. mutex_lock(&aux->mutex);
  500. aborted = atomic_read(&aux->aborted);
  501. mutex_unlock(&aux->mutex);
  502. if (aborted) {
  503. size = -ETIMEDOUT;
  504. goto end;
  505. }
  506. if (aux->sim_in_transfer) {
  507. if (aux->aux_bridge && aux->aux_bridge->transfer)
  508. size = dp_aux_bridge_transfer(drm_aux, msg);
  509. else
  510. size = dp_aux_transfer(drm_aux, msg);
  511. } else {
  512. aux->sim_in_transfer = true;
  513. size = aux->sim_bridge->transfer(aux->sim_bridge,
  514. drm_aux, msg);
  515. aux->sim_in_transfer = false;
  516. dp_aux_hex_dump(drm_aux, msg);
  517. }
  518. end:
  519. return size;
  520. }
  521. static void dp_aux_reset_phy_config_indices(struct dp_aux_cfg *aux_cfg)
  522. {
  523. int i = 0;
  524. for (i = 0; i < PHY_AUX_CFG_MAX; i++)
  525. aux_cfg[i].current_index = 0;
  526. }
  527. static void dp_aux_init(struct dp_aux *dp_aux, struct dp_aux_cfg *aux_cfg)
  528. {
  529. struct dp_aux_private *aux;
  530. if (!dp_aux || !aux_cfg) {
  531. DP_AUX_ERR(dp_aux, "invalid input\n");
  532. return;
  533. }
  534. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  535. if (aux->enabled)
  536. return;
  537. dp_aux->ipc_log_context = ipc_log_context_create(DP_AUX_IPC_NUM_PAGES, "drm_dp_aux", 0);
  538. if (!dp_aux->ipc_log_context)
  539. DP_AUX_WARN(dp_aux, "Error in creating dp_aux_ipc_log context\n");
  540. dp_aux_reset_phy_config_indices(aux_cfg);
  541. aux->catalog->setup(aux->catalog, aux_cfg);
  542. aux->catalog->reset(aux->catalog);
  543. aux->catalog->enable(aux->catalog, true);
  544. atomic_set(&aux->aborted, 0);
  545. aux->retry_cnt = 0;
  546. aux->enabled = true;
  547. }
  548. static void dp_aux_deinit(struct dp_aux *dp_aux)
  549. {
  550. struct dp_aux_private *aux;
  551. if (!dp_aux) {
  552. DP_AUX_ERR(dp_aux, "invalid input\n");
  553. return;
  554. }
  555. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  556. if (!aux->enabled)
  557. return;
  558. if (dp_aux->ipc_log_context) {
  559. ipc_log_context_destroy(dp_aux->ipc_log_context);
  560. dp_aux->ipc_log_context = NULL;
  561. }
  562. atomic_set(&aux->aborted, 1);
  563. aux->catalog->enable(aux->catalog, false);
  564. aux->enabled = false;
  565. }
  566. static int dp_aux_register(struct dp_aux *dp_aux, struct drm_device *drm_dev)
  567. {
  568. struct dp_aux_private *aux;
  569. int ret = 0;
  570. if (!dp_aux) {
  571. DP_AUX_ERR(dp_aux, "invalid input\n");
  572. ret = -EINVAL;
  573. goto exit;
  574. }
  575. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  576. aux->drm_aux.name = "sde_dp_aux";
  577. aux->drm_aux.dev = aux->dev;
  578. aux->drm_aux.transfer = dp_aux_transfer;
  579. #if (KERNEL_VERSION(5, 15, 0) <= LINUX_VERSION_CODE)
  580. aux->drm_aux.drm_dev = drm_dev;
  581. #endif
  582. atomic_set(&aux->aborted, 1);
  583. ret = drm_dp_aux_register(&aux->drm_aux);
  584. if (ret) {
  585. DP_AUX_ERR(dp_aux, "%s: failed to register drm aux: %d\n", __func__, ret);
  586. goto exit;
  587. }
  588. dp_aux->drm_aux = &aux->drm_aux;
  589. /* if bridge is defined, override transfer function */
  590. if (aux->aux_bridge && aux->aux_bridge->transfer)
  591. aux->drm_aux.transfer = dp_aux_bridge_transfer;
  592. exit:
  593. return ret;
  594. }
  595. static void dp_aux_deregister(struct dp_aux *dp_aux)
  596. {
  597. struct dp_aux_private *aux;
  598. if (!dp_aux) {
  599. DP_AUX_ERR(dp_aux, "invalid input\n");
  600. return;
  601. }
  602. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  603. drm_dp_aux_unregister(&aux->drm_aux);
  604. }
  605. static void dp_aux_set_sim_mode(struct dp_aux *dp_aux,
  606. struct dp_aux_bridge *sim_bridge)
  607. {
  608. struct dp_aux_private *aux;
  609. if (!dp_aux) {
  610. DP_AUX_ERR(dp_aux, "invalid input\n");
  611. return;
  612. }
  613. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  614. mutex_lock(&aux->mutex);
  615. aux->sim_bridge = sim_bridge;
  616. if (sim_bridge) {
  617. atomic_set(&aux->aborted, 0);
  618. aux->drm_aux.transfer = dp_aux_transfer_debug;
  619. } else if (aux->aux_bridge && aux->aux_bridge->transfer) {
  620. aux->drm_aux.transfer = dp_aux_bridge_transfer;
  621. } else {
  622. aux->drm_aux.transfer = dp_aux_transfer;
  623. }
  624. mutex_unlock(&aux->mutex);
  625. }
  626. static int dp_aux_configure_aux_switch(struct dp_aux *dp_aux,
  627. bool enable, int orientation)
  628. {
  629. struct dp_aux_private *aux;
  630. int rc = 0;
  631. enum fsa_function event = FSA_USBC_DISPLAYPORT_DISCONNECTED;
  632. if (!dp_aux) {
  633. DP_AUX_ERR(dp_aux, "invalid input\n");
  634. rc = -EINVAL;
  635. goto end;
  636. }
  637. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  638. if (!aux->aux_switch_node) {
  639. DP_AUX_DEBUG(dp_aux, "undefined fsa4480 handle\n");
  640. rc = -EINVAL;
  641. goto end;
  642. }
  643. if (enable) {
  644. switch (orientation) {
  645. case ORIENTATION_CC1:
  646. event = FSA_USBC_ORIENTATION_CC1;
  647. break;
  648. case ORIENTATION_CC2:
  649. event = FSA_USBC_ORIENTATION_CC2;
  650. break;
  651. default:
  652. DP_AUX_ERR(dp_aux, "invalid orientation\n");
  653. rc = -EINVAL;
  654. goto end;
  655. }
  656. }
  657. DP_AUX_DEBUG(dp_aux, "enable=%d, orientation=%d, event=%d\n",
  658. enable, orientation, event);
  659. rc = fsa4480_switch_event(aux->aux_switch_node, event);
  660. if (rc)
  661. DP_AUX_ERR(dp_aux, "failed to configure fsa4480 i2c device (%d)\n", rc);
  662. end:
  663. return rc;
  664. }
  665. struct dp_aux *dp_aux_get(struct device *dev, struct dp_catalog_aux *catalog,
  666. struct dp_parser *parser, struct device_node *aux_switch,
  667. struct dp_aux_bridge *aux_bridge)
  668. {
  669. int rc = 0;
  670. struct dp_aux_private *aux;
  671. struct dp_aux *dp_aux = NULL;
  672. if (!catalog || !parser) {
  673. DP_AUX_ERR(dp_aux, "invalid input\n");
  674. rc = -ENODEV;
  675. goto error;
  676. }
  677. aux = devm_kzalloc(dev, sizeof(*aux), GFP_KERNEL);
  678. if (!aux) {
  679. rc = -ENOMEM;
  680. goto error;
  681. }
  682. init_completion(&aux->comp);
  683. aux->cmd_busy = false;
  684. mutex_init(&aux->mutex);
  685. aux->dev = dev;
  686. aux->catalog = catalog;
  687. aux->cfg = parser->aux_cfg;
  688. aux->aux_switch_node = aux_switch;
  689. aux->aux_bridge = aux_bridge;
  690. dp_aux = &aux->dp_aux;
  691. aux->retry_cnt = 0;
  692. dp_aux->isr = dp_aux_isr;
  693. dp_aux->init = dp_aux_init;
  694. dp_aux->deinit = dp_aux_deinit;
  695. dp_aux->drm_aux_register = dp_aux_register;
  696. dp_aux->drm_aux_deregister = dp_aux_deregister;
  697. dp_aux->reconfig = dp_aux_reconfig;
  698. dp_aux->abort = dp_aux_abort_transaction;
  699. dp_aux->set_sim_mode = dp_aux_set_sim_mode;
  700. dp_aux->aux_switch = dp_aux_configure_aux_switch;
  701. return dp_aux;
  702. error:
  703. return ERR_PTR(rc);
  704. }
  705. void dp_aux_put(struct dp_aux *dp_aux)
  706. {
  707. struct dp_aux_private *aux;
  708. if (!dp_aux)
  709. return;
  710. aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
  711. mutex_destroy(&aux->mutex);
  712. devm_kfree(aux->dev, aux);
  713. }