sde_plane.c 139 KB

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  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/debugfs.h>
  21. #include <linux/dma-buf.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/msm_drm_pp.h>
  24. #include <linux/version.h>
  25. #include "msm_prop.h"
  26. #include "msm_drv.h"
  27. #include "sde_kms.h"
  28. #include "sde_fence.h"
  29. #include "sde_formats.h"
  30. #include "sde_hw_sspp.h"
  31. #include "sde_hw_catalog_format.h"
  32. #include "sde_trace.h"
  33. #include "sde_crtc.h"
  34. #include "sde_vbif.h"
  35. #include "sde_plane.h"
  36. #include "sde_color_processing.h"
  37. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  40. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  41. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  42. #define PHASE_STEP_SHIFT 21
  43. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  44. #define PHASE_RESIDUAL 15
  45. #define SHARP_STRENGTH_DEFAULT 32
  46. #define SHARP_EDGE_THR_DEFAULT 112
  47. #define SHARP_SMOOTH_THR_DEFAULT 8
  48. #define SHARP_NOISE_THR_DEFAULT 2
  49. #define SDE_NAME_SIZE 12
  50. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  51. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  52. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  53. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  54. /**
  55. * enum sde_plane_qos - Different qos configurations for each pipe
  56. *
  57. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  58. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  59. * this configuration is mutually exclusive from VBLANK_CTRL.
  60. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  61. */
  62. enum sde_plane_qos {
  63. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  64. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  65. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  66. };
  67. struct sde_plane {
  68. struct drm_plane base;
  69. struct mutex lock;
  70. enum sde_sspp pipe;
  71. uint64_t features; /* capabilities from catalog */
  72. uint32_t perf_features; /* perf capabilities from catalog */
  73. uint32_t nformats;
  74. uint32_t formats[64];
  75. struct sde_hw_pipe *pipe_hw;
  76. struct sde_hw_pipe_cfg pipe_cfg;
  77. struct sde_hw_sharp_cfg sharp_cfg;
  78. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  79. uint32_t color_fill;
  80. bool is_error;
  81. bool is_rt_pipe;
  82. enum sde_wb_usage_type wb_usage_type;
  83. bool is_virtual;
  84. struct list_head mplane_list;
  85. struct sde_mdss_cfg *catalog;
  86. bool revalidate;
  87. bool xin_halt_forced_clk;
  88. struct sde_csc_cfg csc_cfg;
  89. struct sde_csc_cfg *csc_usr_ptr;
  90. struct sde_csc_cfg *csc_ptr;
  91. struct sde_hw_scaler3_cfg scaler3_cfg;
  92. struct sde_hw_pixel_ext pixel_ext;
  93. const struct sde_sspp_sub_blks *pipe_sblk;
  94. char pipe_name[SDE_NAME_SIZE];
  95. struct msm_property_info property_info;
  96. struct msm_property_data property_data[PLANE_PROP_COUNT];
  97. struct drm_property_blob *blob_info;
  98. struct drm_property_blob *blob_rot_caps;
  99. /* debugfs related stuff */
  100. struct dentry *debugfs_root;
  101. bool debugfs_default_scale;
  102. };
  103. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  104. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  105. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  106. {
  107. struct msm_drm_private *priv;
  108. if (!plane || !plane->dev)
  109. return NULL;
  110. priv = plane->dev->dev_private;
  111. if (!priv)
  112. return NULL;
  113. return to_sde_kms(priv->kms);
  114. }
  115. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  116. {
  117. struct drm_plane_state *pstate = NULL;
  118. struct drm_crtc *drm_crtc = NULL;
  119. struct sde_crtc *sde_crtc = NULL;
  120. struct sde_crtc_mixer *mixer = NULL;
  121. struct sde_hw_ctl *ctl = NULL;
  122. if (!plane) {
  123. DRM_ERROR("Invalid plane %pK\n", plane);
  124. return NULL;
  125. }
  126. pstate = plane->state;
  127. if (!pstate) {
  128. DRM_ERROR("Invalid plane state %pK\n", pstate);
  129. return NULL;
  130. }
  131. drm_crtc = pstate->crtc;
  132. if (!drm_crtc) {
  133. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  134. return NULL;
  135. }
  136. sde_crtc = to_sde_crtc(drm_crtc);
  137. if (!sde_crtc) {
  138. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  139. return NULL;
  140. }
  141. /* it will always return the first mixer and single CTL */
  142. mixer = sde_crtc->mixers;
  143. if (!mixer) {
  144. DRM_ERROR("invalid mixer %pK\n", mixer);
  145. return NULL;
  146. }
  147. ctl = mixer->hw_ctl;
  148. if (!mixer) {
  149. DRM_ERROR("invalid ctl %pK\n", ctl);
  150. return NULL;
  151. }
  152. return ctl;
  153. }
  154. static bool sde_plane_enabled(const struct drm_plane_state *state)
  155. {
  156. return state && state->fb && state->crtc;
  157. }
  158. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  159. {
  160. struct sde_plane *psde;
  161. if (!plane)
  162. return false;
  163. psde = to_sde_plane(plane);
  164. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  165. }
  166. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  167. enum sde_sspp_multirect_index rect_mode, bool enable)
  168. {
  169. struct sde_plane *psde;
  170. if (!plane)
  171. return;
  172. psde = to_sde_plane(plane);
  173. if (psde->pipe_hw->ops.set_src_split_order)
  174. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  175. rect_mode, enable);
  176. }
  177. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  178. {
  179. struct sde_plane *psde;
  180. struct sde_kms *sde_kms;
  181. struct msm_drm_private *priv;
  182. if (!plane || !plane->dev) {
  183. SDE_ERROR("invalid plane\n");
  184. return;
  185. }
  186. priv = plane->dev->dev_private;
  187. if (!priv || !priv->kms) {
  188. SDE_ERROR("invalid KMS reference\n");
  189. return;
  190. }
  191. sde_kms = to_sde_kms(priv->kms);
  192. psde = to_sde_plane(plane);
  193. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm);
  194. }
  195. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  196. struct drm_crtc *crtc,
  197. struct drm_framebuffer *fb)
  198. {
  199. struct sde_plane *psde;
  200. const struct sde_format *fmt = NULL;
  201. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, ds_lut_index;
  202. struct sde_perf_cfg *perf;
  203. struct sde_plane_state *pstate;
  204. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  205. bool inline_rot = false, landscape = false;
  206. struct drm_display_mode *mode;
  207. u32 fl_require0 = 0;
  208. if (!plane || !fb) {
  209. SDE_ERROR("invalid arguments\n");
  210. return;
  211. }
  212. psde = to_sde_plane(plane);
  213. pstate = to_sde_plane_state(plane->state);
  214. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  215. SDE_ERROR("invalid arguments\n");
  216. return;
  217. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  218. return;
  219. }
  220. mode = &crtc->state->adjusted_mode;
  221. landscape = mode->hdisplay > mode->vdisplay ? true : false;
  222. frame_rate = drm_mode_vrefresh(&crtc->mode);
  223. perf = &psde->catalog->perf;
  224. qos_count = perf->qos_refresh_count;
  225. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  226. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  227. (fps_index == qos_count - 1))
  228. break;
  229. fps_index++;
  230. }
  231. if (psde->is_rt_pipe) {
  232. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  233. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  234. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  235. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  236. else if (inline_rot)
  237. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  238. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  239. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  240. else
  241. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  242. } else {
  243. lut_index = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  244. SDE_QOS_LUT_USAGE_OFFLINE_WB : SDE_QOS_LUT_USAGE_NRT;
  245. }
  246. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  247. if (psde->scaler3_cfg.enable)
  248. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  249. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_CREQ_LUT_TYPE_MAX);
  250. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  251. ds_lut_index = lut_index * SDE_DANGER_SAFE_LUT_TYPE_MAX;
  252. if (landscape) {
  253. if (psde->catalog->qos_target_time_ns && sde_crtc->line_time_in_ns)
  254. fl_require0 = psde->catalog->qos_target_time_ns /
  255. (sde_crtc->line_time_in_ns * 2);
  256. if (!fl_require0 || fl_require0 < 4.5)
  257. ds_lut_index += SDE_DANGER_SAFE_LUT_TYPE_LANDSCAPE;
  258. }
  259. ds_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_DANGER_SAFE_LUT_TYPE_MAX);
  260. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[ds_lut_index];
  261. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[ds_lut_index];
  262. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0,
  263. (fmt) ? fmt->fetch_mode : 0, psde->pipe_qos_cfg.danger_lut,
  264. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut);
  265. SDE_DEBUG("plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d lut[0x%x,0x%x 0x%llx] rt:%d type:%d\n",
  266. plane->base.id, psde->pipe - SSPP_VIG0,
  267. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  268. fmt ? fmt->fetch_mode : -1, psde->pipe_qos_cfg.danger_lut,
  269. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut,
  270. psde->is_rt_pipe, psde->wb_usage_type);
  271. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  272. }
  273. /**
  274. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  275. * @plane: Pointer to drm plane
  276. * @enable: true to enable QoS control
  277. * @flags: QoS control mode (enum sde_plane_qos)
  278. */
  279. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  280. bool enable, u32 flags)
  281. {
  282. struct sde_plane *psde;
  283. if (!plane) {
  284. SDE_ERROR("invalid arguments\n");
  285. return;
  286. }
  287. psde = to_sde_plane(plane);
  288. if (!psde->pipe_hw || !psde->pipe_sblk) {
  289. SDE_ERROR("invalid arguments\n");
  290. return;
  291. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  292. return;
  293. }
  294. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  295. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  296. psde->pipe_qos_cfg.danger_vblank =
  297. psde->pipe_sblk->danger_vblank;
  298. psde->pipe_qos_cfg.vblank_en = enable;
  299. }
  300. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  301. /* this feature overrules previous VBLANK_CTRL */
  302. psde->pipe_qos_cfg.vblank_en = false;
  303. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  304. psde->pipe_qos_cfg.danger_vblank = 0;
  305. }
  306. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  307. psde->pipe_qos_cfg.danger_safe_en = enable;
  308. if (!psde->is_rt_pipe) {
  309. psde->pipe_qos_cfg.vblank_en = false;
  310. psde->pipe_qos_cfg.danger_safe_en = false;
  311. }
  312. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  313. plane->base.id,
  314. psde->pipe - SSPP_VIG0,
  315. psde->pipe_qos_cfg.danger_safe_en,
  316. psde->pipe_qos_cfg.vblank_en,
  317. psde->pipe_qos_cfg.creq_vblank,
  318. psde->pipe_qos_cfg.danger_vblank,
  319. psde->is_rt_pipe);
  320. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  321. &psde->pipe_qos_cfg);
  322. }
  323. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  324. {
  325. struct sde_plane *psde;
  326. if (!plane)
  327. return;
  328. psde = to_sde_plane(plane);
  329. psde->revalidate = enable;
  330. }
  331. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  332. {
  333. struct sde_plane *psde;
  334. int rc;
  335. if (!plane) {
  336. SDE_ERROR("invalid arguments\n");
  337. return -EINVAL;
  338. }
  339. psde = to_sde_plane(plane);
  340. if (!psde->is_rt_pipe)
  341. goto end;
  342. rc = pm_runtime_resume_and_get(plane->dev->dev);
  343. if (rc < 0) {
  344. SDE_ERROR("failed to enable power resource %d\n", rc);
  345. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  346. return rc;
  347. }
  348. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  349. pm_runtime_put_sync(plane->dev->dev);
  350. end:
  351. return 0;
  352. }
  353. /**
  354. * _sde_plane_set_ot_limit - set OT limit for the given plane
  355. * @plane: Pointer to drm plane
  356. * @crtc: Pointer to drm crtc
  357. */
  358. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  359. struct drm_crtc *crtc)
  360. {
  361. struct sde_plane *psde;
  362. struct sde_vbif_set_ot_params ot_params;
  363. struct msm_drm_private *priv;
  364. struct sde_kms *sde_kms;
  365. if (!plane || !plane->dev || !crtc) {
  366. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  367. !plane, !crtc);
  368. return;
  369. }
  370. priv = plane->dev->dev_private;
  371. if (!priv || !priv->kms) {
  372. SDE_ERROR("invalid KMS reference\n");
  373. return;
  374. }
  375. sde_kms = to_sde_kms(priv->kms);
  376. psde = to_sde_plane(plane);
  377. if (!psde->pipe_hw) {
  378. SDE_ERROR("invalid pipe reference\n");
  379. return;
  380. }
  381. memset(&ot_params, 0, sizeof(ot_params));
  382. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  383. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  384. ot_params.width = psde->pipe_cfg.src_rect.w;
  385. ot_params.height = psde->pipe_cfg.src_rect.h;
  386. ot_params.is_wfd = ((psde->is_rt_pipe)
  387. || (psde->wb_usage_type == WB_USAGE_OFFLINE_WB)) ? false : true;
  388. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  389. ot_params.vbif_idx = VBIF_RT;
  390. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  391. ot_params.rd = true;
  392. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  393. }
  394. /**
  395. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  396. * @plane: Pointer to drm plane
  397. */
  398. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  399. {
  400. struct sde_plane *psde;
  401. struct sde_vbif_set_qos_params qos_params;
  402. struct msm_drm_private *priv;
  403. struct sde_kms *sde_kms;
  404. if (!plane || !plane->dev) {
  405. SDE_ERROR("invalid arguments\n");
  406. return;
  407. }
  408. priv = plane->dev->dev_private;
  409. if (!priv || !priv->kms) {
  410. SDE_ERROR("invalid KMS reference\n");
  411. return;
  412. }
  413. sde_kms = to_sde_kms(priv->kms);
  414. psde = to_sde_plane(plane);
  415. if (!psde->pipe_hw) {
  416. SDE_ERROR("invalid pipe reference\n");
  417. return;
  418. }
  419. memset(&qos_params, 0, sizeof(qos_params));
  420. qos_params.vbif_idx = VBIF_RT;
  421. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  422. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  423. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  424. if (psde->is_rt_pipe)
  425. qos_params.client_type = VBIF_RT_CLIENT;
  426. else
  427. qos_params.client_type = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  428. VBIF_OFFLINE_WB_CLIENT : VBIF_NRT_CLIENT;
  429. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  430. plane->base.id, qos_params.num,
  431. qos_params.vbif_idx,
  432. qos_params.xin_id, qos_params.client_type,
  433. qos_params.clk_ctrl);
  434. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  435. }
  436. /**
  437. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  438. * @plane: Pointer to drm plane
  439. * @pstate: Pointer to sde plane state
  440. */
  441. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  442. struct sde_plane_state *pstate)
  443. {
  444. struct sde_plane *psde;
  445. struct sde_hw_pipe_ts_cfg cfg;
  446. struct msm_drm_private *priv;
  447. struct sde_kms *sde_kms;
  448. if (!plane || !plane->dev) {
  449. SDE_ERROR("invalid arguments");
  450. return;
  451. }
  452. priv = plane->dev->dev_private;
  453. if (!priv || !priv->kms) {
  454. SDE_ERROR("invalid KMS reference\n");
  455. return;
  456. }
  457. sde_kms = to_sde_kms(priv->kms);
  458. psde = to_sde_plane(plane);
  459. if (!psde->pipe_hw) {
  460. SDE_ERROR("invalid pipe reference\n");
  461. return;
  462. }
  463. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  464. return;
  465. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  466. memset(&cfg, 0, sizeof(cfg));
  467. cfg.size = sde_plane_get_property(pstate,
  468. PLANE_PROP_PREFILL_SIZE);
  469. cfg.time = sde_plane_get_property(pstate,
  470. PLANE_PROP_PREFILL_TIME);
  471. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  472. plane->base.id, cfg.size, cfg.time);
  473. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  474. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  475. pstate->multirect_index);
  476. }
  477. /* helper to update a state's input fence pointer from the property */
  478. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  479. struct sde_plane_state *pstate, uint64_t fd)
  480. {
  481. if (!psde || !pstate) {
  482. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  483. !psde, !pstate);
  484. return;
  485. }
  486. /* clear previous reference */
  487. if (pstate->input_fence)
  488. sde_sync_put(pstate->input_fence);
  489. /* get fence pointer for later */
  490. if (fd == 0)
  491. pstate->input_fence = NULL;
  492. else
  493. pstate->input_fence = sde_sync_get(fd);
  494. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  495. }
  496. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  497. {
  498. struct sde_plane *psde;
  499. struct sde_plane_state *pstate;
  500. uint32_t prefix;
  501. void *input_fence;
  502. int ret = -EINVAL;
  503. signed long rc;
  504. if (!plane) {
  505. SDE_ERROR("invalid plane\n");
  506. } else if (!plane->state) {
  507. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  508. } else {
  509. psde = to_sde_plane(plane);
  510. pstate = to_sde_plane_state(plane->state);
  511. input_fence = pstate->input_fence;
  512. if (input_fence) {
  513. prefix = sde_sync_get_name_prefix(input_fence);
  514. rc = sde_sync_wait(input_fence, wait_ms);
  515. switch (rc) {
  516. case 0:
  517. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  518. wait_ms, prefix, sde_plane_get_property(pstate,
  519. PLANE_PROP_INPUT_FENCE));
  520. psde->is_error = true;
  521. sde_kms_timeline_status(plane->dev);
  522. ret = -ETIMEDOUT;
  523. break;
  524. case -ERESTARTSYS:
  525. SDE_ERROR_PLANE(psde,
  526. "%ums wait interrupted on %08X\n",
  527. wait_ms, prefix);
  528. psde->is_error = true;
  529. ret = -ERESTARTSYS;
  530. break;
  531. case -EINVAL:
  532. SDE_ERROR_PLANE(psde,
  533. "invalid fence param for %08X\n",
  534. prefix);
  535. psde->is_error = true;
  536. ret = -EINVAL;
  537. break;
  538. case -EBADF:
  539. SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
  540. plane->base.id,
  541. sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
  542. psde->is_error = true;
  543. ret = 0;
  544. break;
  545. default:
  546. SDE_DEBUG_PLANE(psde, "signaled\n");
  547. ret = 0;
  548. break;
  549. }
  550. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  551. } else {
  552. ret = 0;
  553. }
  554. }
  555. return ret;
  556. }
  557. /**
  558. * _sde_plane_get_aspace: gets the address space based on the
  559. * fb_translation mode property
  560. */
  561. static int _sde_plane_get_aspace(
  562. struct sde_plane *psde,
  563. struct sde_plane_state *pstate,
  564. struct msm_gem_address_space **aspace)
  565. {
  566. struct sde_kms *kms;
  567. int mode;
  568. if (!psde || !pstate || !aspace) {
  569. SDE_ERROR("invalid parameters\n");
  570. return -EINVAL;
  571. }
  572. kms = _sde_plane_get_kms(&psde->base);
  573. if (!kms) {
  574. SDE_ERROR("invalid kms\n");
  575. return -EINVAL;
  576. }
  577. mode = sde_plane_get_property(pstate,
  578. PLANE_PROP_FB_TRANSLATION_MODE);
  579. switch (mode) {
  580. case SDE_DRM_FB_NON_SEC:
  581. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  582. if (!aspace)
  583. return -EINVAL;
  584. break;
  585. case SDE_DRM_FB_SEC:
  586. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  587. if (!aspace)
  588. return -EINVAL;
  589. break;
  590. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  591. case SDE_DRM_FB_SEC_DIR_TRANS:
  592. *aspace = NULL;
  593. break;
  594. default:
  595. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  596. return -EFAULT;
  597. }
  598. return 0;
  599. }
  600. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  601. struct sde_plane_state *pstate,
  602. struct sde_hw_pipe_cfg *pipe_cfg,
  603. struct drm_framebuffer *fb)
  604. {
  605. struct sde_plane *psde;
  606. struct msm_gem_address_space *aspace = NULL;
  607. int ret, mode;
  608. bool secure = false;
  609. if (!plane || !pstate || !pipe_cfg || !fb) {
  610. SDE_ERROR(
  611. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  612. !plane, !pstate, !pipe_cfg, !fb);
  613. return;
  614. }
  615. psde = to_sde_plane(plane);
  616. if (!psde->pipe_hw) {
  617. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  618. return;
  619. }
  620. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  621. if (ret) {
  622. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  623. return;
  624. }
  625. /*
  626. * framebuffer prepare is deferred for prepare_fb calls that
  627. * happen during the transition from secure to non-secure.
  628. * Handle the prepare at this point for such cases. This can be
  629. * expected for one or two frames during the transition.
  630. */
  631. if (aspace && pstate->defer_prepare_fb) {
  632. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  633. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  634. if (ret) {
  635. SDE_ERROR_PLANE(psde,
  636. "failed to prepare framebuffer %d\n", ret);
  637. return;
  638. }
  639. pstate->defer_prepare_fb = false;
  640. }
  641. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  642. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  643. secure = true;
  644. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  645. if (ret == -EAGAIN)
  646. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  647. else if (ret) {
  648. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  649. /*
  650. * Force solid fill color on error. This is to prevent
  651. * smmu faults during secure session transition.
  652. */
  653. psde->is_error = true;
  654. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  655. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  656. pipe_cfg->layout.width,
  657. pipe_cfg->layout.height,
  658. pipe_cfg->layout.plane_addr[0],
  659. pipe_cfg->layout.plane_size[0],
  660. pipe_cfg->layout.plane_addr[1],
  661. pipe_cfg->layout.plane_size[1],
  662. pipe_cfg->layout.plane_addr[2],
  663. pipe_cfg->layout.plane_size[2],
  664. pipe_cfg->layout.plane_addr[3],
  665. pipe_cfg->layout.plane_size[3],
  666. pstate->multirect_index,
  667. secure);
  668. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  669. pstate->multirect_index);
  670. }
  671. }
  672. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  673. struct sde_plane_state *pstate)
  674. {
  675. struct sde_hw_scaler3_cfg *cfg;
  676. int ret = 0;
  677. if (!psde || !pstate) {
  678. SDE_ERROR("invalid args\n");
  679. return -EINVAL;
  680. }
  681. cfg = &psde->scaler3_cfg;
  682. cfg->dir_lut = msm_property_get_blob(
  683. &psde->property_info,
  684. &pstate->property_state, &cfg->dir_len,
  685. PLANE_PROP_SCALER_LUT_ED);
  686. cfg->cir_lut = msm_property_get_blob(
  687. &psde->property_info,
  688. &pstate->property_state, &cfg->cir_len,
  689. PLANE_PROP_SCALER_LUT_CIR);
  690. cfg->sep_lut = msm_property_get_blob(
  691. &psde->property_info,
  692. &pstate->property_state, &cfg->sep_len,
  693. PLANE_PROP_SCALER_LUT_SEP);
  694. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  695. ret = -ENODATA;
  696. return ret;
  697. }
  698. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  699. struct sde_plane_state *pstate)
  700. {
  701. struct sde_hw_scaler3_cfg *cfg;
  702. cfg = &psde->scaler3_cfg;
  703. cfg->sep_lut = msm_property_get_blob(
  704. &psde->property_info,
  705. &pstate->property_state, &cfg->sep_len,
  706. PLANE_PROP_SCALER_LUT_SEP);
  707. return cfg->sep_lut ? 0 : -ENODATA;
  708. }
  709. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  710. struct sde_plane_state *pstate, const struct sde_format *fmt,
  711. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  712. {
  713. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  714. struct sde_hw_scaler3_cfg *scale_cfg;
  715. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  716. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  717. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  718. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  719. chroma_subsmpl_h, chroma_subsmpl_v);
  720. return;
  721. }
  722. scale_cfg = &psde->scaler3_cfg;
  723. src_w = psde->pipe_cfg.src_rect.w;
  724. src_h = psde->pipe_cfg.src_rect.h;
  725. dst_w = psde->pipe_cfg.dst_rect.w;
  726. dst_h = psde->pipe_cfg.dst_rect.h;
  727. memset(scale_cfg, 0, sizeof(*scale_cfg));
  728. memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  729. /*
  730. * For inline rotation cases, scaler config is post-rotation,
  731. * so swap the dimensions here. However, pixel extension will
  732. * need pre-rotation settings, this will be corrected below
  733. * when calculating pixel extension settings.
  734. */
  735. if (inline_rotation)
  736. swap(src_w, src_h);
  737. decimated = DECIMATED_DIMENSION(src_w,
  738. psde->pipe_cfg.horz_decimation);
  739. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  740. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  741. decimated = DECIMATED_DIMENSION(src_h,
  742. psde->pipe_cfg.vert_decimation);
  743. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  744. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  745. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  746. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  747. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  748. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  749. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  750. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  751. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  752. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  753. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  754. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  755. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  756. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  757. for (i = 0; i < SDE_MAX_PLANES; i++) {
  758. /*
  759. * For inline rotation cases with pre-downscaling enabled
  760. * set x pre-downscale value if required. Only x direction
  761. * is currently supported. Use src_h as values have been swapped
  762. * and x direction corresponds to height value.
  763. */
  764. src_h_pre_down = src_h;
  765. if (pre_down_supported && inline_rotation) {
  766. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  767. src_h_pre_down = src_h / 2;
  768. }
  769. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  770. psde->pipe_cfg.horz_decimation);
  771. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  772. psde->pipe_cfg.vert_decimation);
  773. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  774. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  775. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  776. }
  777. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  778. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  779. /* For pixel extension we need the pre-rotated orientation */
  780. if (inline_rotation) {
  781. psde->pixel_ext.num_ext_pxls_top[i] =
  782. scale_cfg->src_width[i];
  783. psde->pixel_ext.num_ext_pxls_left[i] =
  784. scale_cfg->src_height[i];
  785. } else {
  786. psde->pixel_ext.num_ext_pxls_top[i] =
  787. scale_cfg->src_height[i];
  788. psde->pixel_ext.num_ext_pxls_left[i] =
  789. scale_cfg->src_width[i];
  790. }
  791. }
  792. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  793. && (src_w == dst_w) && !inline_rotation) ||
  794. pstate->multirect_mode)
  795. return;
  796. SDE_DEBUG_PLANE(psde,
  797. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  798. src_w, src_h, dst_w, dst_h,
  799. chroma_subsmpl_v, chroma_subsmpl_h,
  800. fmt->base.pixel_format);
  801. scale_cfg->dst_width = dst_w;
  802. scale_cfg->dst_height = dst_h;
  803. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  804. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  805. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  806. scale_cfg->lut_flag = 0;
  807. scale_cfg->blend_cfg = 1;
  808. scale_cfg->enable = 1;
  809. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  810. }
  811. /**
  812. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  813. * @psde: Pointer to SDE plane object
  814. * @src: Source size
  815. * @dst: Destination size
  816. * @phase_steps: Pointer to output array for phase steps
  817. * @filter: Pointer to output array for filter type
  818. * @fmt: Pointer to format definition
  819. * @chroma_subsampling: Subsampling amount for chroma channel
  820. *
  821. * Returns: 0 on success
  822. */
  823. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  824. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  825. enum sde_hw_filter *filter, const struct sde_format *fmt,
  826. uint32_t chroma_subsampling)
  827. {
  828. if (!psde || !phase_steps || !filter || !fmt) {
  829. SDE_ERROR(
  830. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  831. !psde, !phase_steps, !filter, !fmt);
  832. return -EINVAL;
  833. }
  834. /* calculate phase steps, leave init phase as zero */
  835. phase_steps[SDE_SSPP_COMP_0] =
  836. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  837. phase_steps[SDE_SSPP_COMP_1_2] =
  838. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  839. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  840. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  841. /* calculate scaler config, if necessary */
  842. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  843. filter[SDE_SSPP_COMP_3] =
  844. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  845. SDE_SCALE_FILTER_PCMN;
  846. if (SDE_FORMAT_IS_YUV(fmt)) {
  847. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  848. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  849. } else {
  850. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  851. filter[SDE_SSPP_COMP_1_2] =
  852. SDE_SCALE_FILTER_NEAREST;
  853. }
  854. } else {
  855. /* disable scaler */
  856. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  857. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  858. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  859. }
  860. return 0;
  861. }
  862. /**
  863. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  864. * @psde: Pointer to SDE plane object
  865. * @src: Source size
  866. * @dst: Destination size
  867. * @decimated_src: Source size after decimation, if any
  868. * @phase_steps: Pointer to output array for phase steps
  869. * @out_src: Output array for pixel extension values
  870. * @out_edge1: Output array for pixel extension first edge
  871. * @out_edge2: Output array for pixel extension second edge
  872. * @filter: Pointer to array for filter type
  873. * @fmt: Pointer to format definition
  874. * @chroma_subsampling: Subsampling amount for chroma channel
  875. * @post_compare: Whether to chroma subsampled source size for comparisions
  876. */
  877. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  878. uint32_t src, uint32_t dst, uint32_t decimated_src,
  879. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  880. int *out_edge2, enum sde_hw_filter *filter,
  881. const struct sde_format *fmt, uint32_t chroma_subsampling,
  882. bool post_compare)
  883. {
  884. int64_t edge1, edge2, caf;
  885. uint32_t src_work;
  886. int i, tmp;
  887. if (psde && phase_steps && out_src && out_edge1 &&
  888. out_edge2 && filter && fmt) {
  889. /* handle CAF for YUV formats */
  890. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  891. caf = PHASE_STEP_UNIT_SCALE;
  892. else
  893. caf = 0;
  894. for (i = 0; i < SDE_MAX_PLANES; i++) {
  895. src_work = decimated_src;
  896. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  897. src_work /= chroma_subsampling;
  898. if (post_compare)
  899. src = src_work;
  900. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  901. /* unity */
  902. edge1 = 0;
  903. edge2 = 0;
  904. } else if (dst >= src) {
  905. /* upscale */
  906. edge1 = (1 << PHASE_RESIDUAL);
  907. edge1 -= caf;
  908. edge2 = (1 << PHASE_RESIDUAL);
  909. edge2 += (dst - 1) * *(phase_steps + i);
  910. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  911. edge2 += caf;
  912. edge2 = -(edge2);
  913. } else {
  914. /* downscale */
  915. edge1 = 0;
  916. edge2 = (dst - 1) * *(phase_steps + i);
  917. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  918. edge2 += *(phase_steps + i);
  919. edge2 = -(edge2);
  920. }
  921. /* only enable CAF for luma plane */
  922. caf = 0;
  923. /* populate output arrays */
  924. *(out_src + i) = src_work;
  925. /* edge updates taken from __pxl_extn_helper */
  926. if (edge1 >= 0) {
  927. tmp = (uint32_t)edge1;
  928. tmp >>= PHASE_STEP_SHIFT;
  929. *(out_edge1 + i) = -tmp;
  930. } else {
  931. tmp = (uint32_t)(-edge1);
  932. *(out_edge1 + i) =
  933. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  934. PHASE_STEP_SHIFT;
  935. }
  936. if (edge2 >= 0) {
  937. tmp = (uint32_t)edge2;
  938. tmp >>= PHASE_STEP_SHIFT;
  939. *(out_edge2 + i) = -tmp;
  940. } else {
  941. tmp = (uint32_t)(-edge2);
  942. *(out_edge2 + i) =
  943. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  944. PHASE_STEP_SHIFT;
  945. }
  946. }
  947. }
  948. }
  949. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  950. {
  951. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  952. {
  953. /* S15.16 format */
  954. 0x00012A00, 0x00000000, 0x00019880,
  955. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  956. 0x00012A00, 0x00020480, 0x00000000,
  957. },
  958. /* signed bias */
  959. { 0xfff0, 0xff80, 0xff80,},
  960. { 0x0, 0x0, 0x0,},
  961. /* unsigned clamp */
  962. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  963. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  964. };
  965. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  966. {
  967. /* S15.16 format */
  968. 0x00012A00, 0x00000000, 0x00019880,
  969. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  970. 0x00012A00, 0x00020480, 0x00000000,
  971. },
  972. /* signed bias */
  973. { 0xffc0, 0xfe00, 0xfe00,},
  974. { 0x0, 0x0, 0x0,},
  975. /* unsigned clamp */
  976. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  977. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  978. };
  979. if (!psde) {
  980. SDE_ERROR("invalid plane\n");
  981. return;
  982. }
  983. /* revert to kernel default if override not available */
  984. if (psde->csc_usr_ptr)
  985. psde->csc_ptr = psde->csc_usr_ptr;
  986. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  987. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  988. else
  989. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  990. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  991. psde->csc_ptr->csc_mv[0],
  992. psde->csc_ptr->csc_mv[1],
  993. psde->csc_ptr->csc_mv[2]);
  994. }
  995. static void sde_color_process_plane_setup(struct drm_plane *plane)
  996. {
  997. struct sde_plane *psde;
  998. struct sde_plane_state *pstate;
  999. uint32_t hue, saturation, value, contrast;
  1000. struct drm_msm_memcol *memcol = NULL;
  1001. struct drm_msm_3d_gamut *vig_gamut = NULL;
  1002. struct drm_msm_igc_lut *igc = NULL;
  1003. struct drm_msm_pgc_lut *gc = NULL;
  1004. size_t memcol_sz = 0, size = 0;
  1005. struct sde_hw_cp_cfg hw_cfg = {};
  1006. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1007. bool fp16_igc, fp16_unmult;
  1008. struct drm_msm_fp16_gc *fp16_gc = NULL;
  1009. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1010. psde = to_sde_plane(plane);
  1011. pstate = to_sde_plane_state(plane->state);
  1012. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1013. if (psde->pipe_hw->ops.setup_pa_hue)
  1014. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1015. saturation = (uint32_t) sde_plane_get_property(pstate,
  1016. PLANE_PROP_SATURATION_ADJUST);
  1017. if (psde->pipe_hw->ops.setup_pa_sat)
  1018. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1019. value = (uint32_t) sde_plane_get_property(pstate,
  1020. PLANE_PROP_VALUE_ADJUST);
  1021. if (psde->pipe_hw->ops.setup_pa_val)
  1022. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1023. contrast = (uint32_t) sde_plane_get_property(pstate,
  1024. PLANE_PROP_CONTRAST_ADJUST);
  1025. if (psde->pipe_hw->ops.setup_pa_cont)
  1026. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1027. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1028. /* Skin memory color setup */
  1029. memcol = msm_property_get_blob(&psde->property_info,
  1030. &pstate->property_state,
  1031. &memcol_sz,
  1032. PLANE_PROP_SKIN_COLOR);
  1033. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1034. MEMCOLOR_SKIN, memcol);
  1035. /* Sky memory color setup */
  1036. memcol = msm_property_get_blob(&psde->property_info,
  1037. &pstate->property_state,
  1038. &memcol_sz,
  1039. PLANE_PROP_SKY_COLOR);
  1040. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1041. MEMCOLOR_SKY, memcol);
  1042. /* Foliage memory color setup */
  1043. memcol = msm_property_get_blob(&psde->property_info,
  1044. &pstate->property_state,
  1045. &memcol_sz,
  1046. PLANE_PROP_FOLIAGE_COLOR);
  1047. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1048. MEMCOLOR_FOLIAGE, memcol);
  1049. }
  1050. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1051. psde->pipe_hw->ops.setup_vig_gamut) {
  1052. vig_gamut = msm_property_get_blob(&psde->property_info,
  1053. &pstate->property_state,
  1054. &size,
  1055. PLANE_PROP_VIG_GAMUT);
  1056. hw_cfg.last_feature = 0;
  1057. hw_cfg.ctl = ctl;
  1058. hw_cfg.len = size;
  1059. hw_cfg.payload = vig_gamut;
  1060. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1061. }
  1062. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1063. psde->pipe_hw->ops.setup_vig_igc) {
  1064. igc = msm_property_get_blob(&psde->property_info,
  1065. &pstate->property_state,
  1066. &size,
  1067. PLANE_PROP_VIG_IGC);
  1068. hw_cfg.last_feature = 0;
  1069. hw_cfg.ctl = ctl;
  1070. hw_cfg.len = size;
  1071. hw_cfg.payload = igc;
  1072. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1073. }
  1074. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1075. psde->pipe_hw->ops.setup_dma_igc) {
  1076. igc = msm_property_get_blob(&psde->property_info,
  1077. &pstate->property_state,
  1078. &size,
  1079. PLANE_PROP_DMA_IGC);
  1080. hw_cfg.last_feature = 0;
  1081. hw_cfg.ctl = ctl;
  1082. hw_cfg.len = size;
  1083. hw_cfg.payload = igc;
  1084. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1085. pstate->multirect_index);
  1086. }
  1087. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1088. psde->pipe_hw->ops.setup_dma_gc) {
  1089. gc = msm_property_get_blob(&psde->property_info,
  1090. &pstate->property_state,
  1091. &size,
  1092. PLANE_PROP_DMA_GC);
  1093. hw_cfg.last_feature = 0;
  1094. hw_cfg.ctl = ctl;
  1095. hw_cfg.len = size;
  1096. hw_cfg.payload = gc;
  1097. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1098. pstate->multirect_index);
  1099. }
  1100. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1101. psde->pipe_hw->ops.setup_fp16_igc) {
  1102. fp16_igc = !!sde_plane_get_property(pstate,
  1103. PLANE_PROP_FP16_IGC);
  1104. hw_cfg.last_feature = 0;
  1105. hw_cfg.ctl = ctl;
  1106. hw_cfg.len = sizeof(bool);
  1107. hw_cfg.payload = &fp16_igc;
  1108. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1109. pstate->multirect_index, &hw_cfg);
  1110. }
  1111. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1112. psde->pipe_hw->ops.setup_fp16_gc) {
  1113. fp16_gc = msm_property_get_blob(&psde->property_info,
  1114. &pstate->property_state,
  1115. &size,
  1116. PLANE_PROP_FP16_GC);
  1117. hw_cfg.last_feature = 0;
  1118. hw_cfg.ctl = ctl;
  1119. hw_cfg.len = size;
  1120. hw_cfg.payload = fp16_gc;
  1121. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1122. pstate->multirect_index, &hw_cfg);
  1123. }
  1124. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1125. psde->pipe_hw->ops.setup_fp16_csc) {
  1126. fp16_csc = msm_property_get_blob(&psde->property_info,
  1127. &pstate->property_state,
  1128. &size,
  1129. PLANE_PROP_FP16_CSC);
  1130. hw_cfg.last_feature = 0;
  1131. hw_cfg.ctl = ctl;
  1132. hw_cfg.len = size;
  1133. hw_cfg.payload = fp16_csc;
  1134. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1135. pstate->multirect_index, &hw_cfg);
  1136. }
  1137. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1138. psde->pipe_hw->ops.setup_fp16_unmult) {
  1139. fp16_unmult = !!sde_plane_get_property(pstate,
  1140. PLANE_PROP_FP16_UNMULT);
  1141. hw_cfg.last_feature = 0;
  1142. hw_cfg.ctl = ctl;
  1143. hw_cfg.len = sizeof(bool);
  1144. hw_cfg.payload = &fp16_unmult;
  1145. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1146. pstate->multirect_index, &hw_cfg);
  1147. }
  1148. }
  1149. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1150. struct sde_plane_state *pstate,
  1151. const struct sde_format *fmt, bool color_fill)
  1152. {
  1153. struct sde_hw_pixel_ext *pe;
  1154. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1155. const struct drm_format_info *info = NULL;
  1156. if (!psde || !fmt || !pstate) {
  1157. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1158. !psde, !fmt, !pstate);
  1159. return;
  1160. }
  1161. memcpy(&psde->scaler3_cfg, &pstate->scaler3_cfg,
  1162. sizeof(psde->scaler3_cfg));
  1163. memcpy(&psde->pixel_ext, &pstate->pixel_ext,
  1164. sizeof(psde->pixel_ext));
  1165. info = drm_format_info(fmt->base.pixel_format);
  1166. pe = &psde->pixel_ext;
  1167. psde->pipe_cfg.horz_decimation =
  1168. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1169. psde->pipe_cfg.vert_decimation =
  1170. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1171. /* don't chroma subsample if decimating */
  1172. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1173. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1174. /* update scaler */
  1175. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1176. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1177. int rc = -EINVAL;
  1178. if (!color_fill && !psde->debugfs_default_scale)
  1179. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1180. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1181. _sde_plane_setup_scaler3_lut(psde, pstate);
  1182. if (rc || pstate->scaler_check_state !=
  1183. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1184. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1185. pstate->scaler_check_state,
  1186. psde->debugfs_default_scale, rc,
  1187. psde->pipe_cfg.src_rect.w,
  1188. psde->pipe_cfg.src_rect.h,
  1189. psde->pipe_cfg.dst_rect.w,
  1190. psde->pipe_cfg.dst_rect.h,
  1191. pstate->multirect_mode);
  1192. /* calculate default config for QSEED3 */
  1193. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1194. chroma_subsmpl_h, chroma_subsmpl_v);
  1195. }
  1196. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1197. color_fill || psde->debugfs_default_scale) {
  1198. uint32_t deci_dim, i;
  1199. /* calculate default configuration for QSEED2 */
  1200. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1201. SDE_DEBUG_PLANE(psde, "default config\n");
  1202. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1203. psde->pipe_cfg.horz_decimation);
  1204. _sde_plane_setup_scaler2(psde,
  1205. deci_dim,
  1206. psde->pipe_cfg.dst_rect.w,
  1207. pe->phase_step_x,
  1208. pe->horz_filter, fmt, chroma_subsmpl_h);
  1209. if (SDE_FORMAT_IS_YUV(fmt))
  1210. deci_dim &= ~0x1;
  1211. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1212. psde->pipe_cfg.dst_rect.w, deci_dim,
  1213. pe->phase_step_x,
  1214. pe->roi_w,
  1215. pe->num_ext_pxls_left,
  1216. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1217. chroma_subsmpl_h, 0);
  1218. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1219. psde->pipe_cfg.vert_decimation);
  1220. _sde_plane_setup_scaler2(psde,
  1221. deci_dim,
  1222. psde->pipe_cfg.dst_rect.h,
  1223. pe->phase_step_y,
  1224. pe->vert_filter, fmt, chroma_subsmpl_v);
  1225. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1226. psde->pipe_cfg.dst_rect.h, deci_dim,
  1227. pe->phase_step_y,
  1228. pe->roi_h,
  1229. pe->num_ext_pxls_top,
  1230. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1231. chroma_subsmpl_v, 1);
  1232. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1233. if (pe->num_ext_pxls_left[i] >= 0)
  1234. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1235. else
  1236. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1237. if (pe->num_ext_pxls_right[i] >= 0)
  1238. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1239. else
  1240. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1241. if (pe->num_ext_pxls_top[i] >= 0)
  1242. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1243. else
  1244. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1245. if (pe->num_ext_pxls_btm[i] >= 0)
  1246. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1247. else
  1248. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1249. }
  1250. }
  1251. if (psde->pipe_hw->ops.setup_pre_downscale)
  1252. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1253. &pstate->pre_down);
  1254. }
  1255. /**
  1256. * _sde_plane_color_fill - enables color fill on plane
  1257. * @psde: Pointer to SDE plane object
  1258. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1259. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1260. * Returns: 0 on success
  1261. */
  1262. static int _sde_plane_color_fill(struct sde_plane *psde,
  1263. uint32_t color, uint32_t alpha)
  1264. {
  1265. const struct sde_format *fmt;
  1266. const struct drm_plane *plane;
  1267. struct sde_plane_state *pstate;
  1268. bool blend_enable = true;
  1269. if (!psde || !psde->base.state) {
  1270. SDE_ERROR("invalid plane\n");
  1271. return -EINVAL;
  1272. }
  1273. if (!psde->pipe_hw) {
  1274. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1275. return -EINVAL;
  1276. }
  1277. plane = &psde->base;
  1278. pstate = to_sde_plane_state(plane->state);
  1279. SDE_DEBUG_PLANE(psde, "\n");
  1280. /*
  1281. * select fill format to match user property expectation,
  1282. * h/w only supports RGB variants
  1283. */
  1284. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1285. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1286. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1287. /* update sspp */
  1288. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1289. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1290. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1291. pstate->multirect_index);
  1292. /* override scaler/decimation if solid fill */
  1293. psde->pipe_cfg.src_rect.x = 0;
  1294. psde->pipe_cfg.src_rect.y = 0;
  1295. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1296. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1297. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1298. if (psde->pipe_hw->ops.setup_format)
  1299. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1300. fmt, blend_enable,
  1301. SDE_SSPP_SOLID_FILL,
  1302. pstate->multirect_index);
  1303. if (psde->pipe_hw->ops.setup_rects)
  1304. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1305. &psde->pipe_cfg,
  1306. pstate->multirect_index);
  1307. if (psde->pipe_hw->ops.setup_pe)
  1308. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1309. &psde->pixel_ext);
  1310. if (psde->pipe_hw->ops.setup_scaler &&
  1311. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1312. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1313. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1314. &psde->pipe_cfg, &psde->pixel_ext,
  1315. &psde->scaler3_cfg);
  1316. }
  1317. }
  1318. return 0;
  1319. }
  1320. /**
  1321. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1322. * @plane: Pointer to drm plane
  1323. * @state: Pointer to drm plane state to be validated
  1324. * return: 0 if success; error code otherwise
  1325. */
  1326. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1327. struct drm_plane_state *state)
  1328. {
  1329. struct sde_plane *psde;
  1330. struct sde_plane_state *pstate, *old_pstate;
  1331. int ret = 0;
  1332. u32 rotation;
  1333. if (!plane || !state) {
  1334. SDE_ERROR("invalid plane/state\n");
  1335. return -EINVAL;
  1336. }
  1337. psde = to_sde_plane(plane);
  1338. pstate = to_sde_plane_state(state);
  1339. old_pstate = to_sde_plane_state(plane->state);
  1340. /* check inline rotation and simplify the transform */
  1341. rotation = drm_rotation_simplify(
  1342. state->rotation,
  1343. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1344. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1345. if ((rotation & DRM_MODE_ROTATE_180) ||
  1346. (rotation & DRM_MODE_ROTATE_270)) {
  1347. SDE_ERROR_PLANE(psde,
  1348. "invalid rotation transform must be simplified 0x%x\n",
  1349. rotation);
  1350. ret = -EINVAL;
  1351. goto exit;
  1352. }
  1353. if (rotation & DRM_MODE_ROTATE_90) {
  1354. struct msm_drm_private *priv = plane->dev->dev_private;
  1355. struct sde_kms *sde_kms;
  1356. const struct msm_format *msm_fmt;
  1357. const struct sde_format *fmt;
  1358. struct sde_rect src;
  1359. bool q16_data = true;
  1360. POPULATE_RECT(&src, state->src_x, state->src_y,
  1361. state->src_w, state->src_h, q16_data);
  1362. /*
  1363. * DRM framework expects rotation flag in counter-clockwise
  1364. * direction and the HW expects in clockwise direction.
  1365. * Flip the flags to match with HW.
  1366. */
  1367. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1368. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1369. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1370. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1371. !psde->pipe_sblk->in_rot_maxheight ||
  1372. !psde->pipe_sblk->in_rot_format_list ||
  1373. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1374. SDE_ERROR_PLANE(psde,
  1375. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1376. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1377. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1378. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1379. !psde->pipe_sblk->in_rot_format_list,
  1380. !psde->pipe_sblk->in_rot_maxheight,
  1381. psde->features);
  1382. ret = -EINVAL;
  1383. goto exit;
  1384. }
  1385. /* check for valid height */
  1386. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1387. SDE_ERROR_PLANE(psde,
  1388. "invalid height for inline rot:%d max:%d\n",
  1389. src.h, psde->pipe_sblk->in_rot_maxheight);
  1390. ret = -EINVAL;
  1391. goto exit;
  1392. }
  1393. if (!sde_plane_enabled(state))
  1394. goto exit;
  1395. /* check for valid formats supported by inline rot */
  1396. sde_kms = to_sde_kms(priv->kms);
  1397. msm_fmt = msm_framebuffer_format(state->fb);
  1398. fmt = to_sde_format(msm_fmt);
  1399. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1400. psde->pipe_sblk->in_rot_format_list);
  1401. }
  1402. exit:
  1403. pstate->rotation = rotation;
  1404. return ret;
  1405. }
  1406. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1407. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1408. {
  1409. struct sde_plane *psde;
  1410. struct msm_drm_private *priv;
  1411. struct sde_vbif_set_xin_halt_params halt_params;
  1412. if (!plane || !plane->dev) {
  1413. SDE_ERROR("invalid arguments\n");
  1414. return false;
  1415. }
  1416. psde = to_sde_plane(plane);
  1417. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1418. SDE_ERROR("invalid pipe reference\n");
  1419. return false;
  1420. }
  1421. priv = plane->dev->dev_private;
  1422. if (!priv || !priv->kms) {
  1423. SDE_ERROR("invalid KMS reference\n");
  1424. return false;
  1425. }
  1426. memset(&halt_params, 0, sizeof(halt_params));
  1427. halt_params.vbif_idx = VBIF_RT;
  1428. halt_params.xin_id = xin_id;
  1429. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1430. halt_params.forced_on = halt_forced_clk;
  1431. halt_params.enable = enable;
  1432. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1433. }
  1434. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1435. {
  1436. struct sde_plane *psde;
  1437. if (!plane) {
  1438. SDE_ERROR("invalid plane\n");
  1439. return;
  1440. }
  1441. psde = to_sde_plane(plane);
  1442. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1443. SDE_ERROR("invalid pipe reference\n");
  1444. return;
  1445. }
  1446. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1447. psde->xin_halt_forced_clk =
  1448. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1449. psde->xin_halt_forced_clk, enable);
  1450. }
  1451. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1452. struct drm_crtc *crtc)
  1453. {
  1454. struct sde_plane *psde;
  1455. if (!plane || !crtc) {
  1456. SDE_ERROR("invalid plane/crtc\n");
  1457. return;
  1458. }
  1459. psde = to_sde_plane(plane);
  1460. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1461. return;
  1462. /* do all VBIF programming for the sec-ui allowed SSPP */
  1463. _sde_plane_set_qos_remap(plane);
  1464. _sde_plane_set_ot_limit(plane, crtc);
  1465. }
  1466. /**
  1467. * sde_plane_rot_install_properties - install plane rotator properties
  1468. * @plane: Pointer to drm plane
  1469. * @catalog: Pointer to mdss configuration
  1470. * return: none
  1471. */
  1472. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1473. struct sde_mdss_cfg *catalog)
  1474. {
  1475. struct sde_plane *psde = to_sde_plane(plane);
  1476. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1477. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1478. int ret = 0;
  1479. if (!plane || !psde) {
  1480. SDE_ERROR("invalid plane\n");
  1481. return;
  1482. } else if (!catalog) {
  1483. SDE_ERROR("invalid catalog\n");
  1484. return;
  1485. }
  1486. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1487. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1488. ret = drm_plane_create_rotation_property(plane,
  1489. DRM_MODE_ROTATE_0, supported_rotations);
  1490. if (ret) {
  1491. DRM_ERROR("create rotation property failed: %d\n", ret);
  1492. return;
  1493. }
  1494. }
  1495. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1496. {
  1497. struct sde_plane_state *pstate;
  1498. if (!drm_state)
  1499. return;
  1500. pstate = to_sde_plane_state(drm_state);
  1501. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1502. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1503. }
  1504. /**
  1505. * multi_rect validate API allows to validate only R0 and R1 RECT
  1506. * passing for each plane. Client of this API must not pass multiple
  1507. * plane which are not sharing same XIN client. Such calls will fail
  1508. * even though kernel client is passing valid multirect configuration.
  1509. */
  1510. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1511. {
  1512. struct sde_plane_state *pstate[R_MAX];
  1513. const struct drm_plane_state *drm_state[R_MAX];
  1514. struct sde_rect src[R_MAX], dst[R_MAX];
  1515. struct sde_plane *sde_plane[R_MAX];
  1516. const struct sde_format *fmt[R_MAX];
  1517. int xin_id[R_MAX];
  1518. bool q16_data = true;
  1519. int i, j, buffer_lines, width_threshold[R_MAX];
  1520. unsigned int max_tile_height = 1;
  1521. bool parallel_fetch_qualified = true;
  1522. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1523. const struct msm_format *msm_fmt;
  1524. bool const_alpha_enable = true;
  1525. for (i = 0; i < R_MAX; i++) {
  1526. drm_state[i] = i ? plane->r1 : plane->r0;
  1527. if (!drm_state[i]) {
  1528. SDE_ERROR("drm plane state is NULL\n");
  1529. return -EINVAL;
  1530. }
  1531. pstate[i] = to_sde_plane_state(drm_state[i]);
  1532. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1533. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1534. for (j = 0; j < i; j++) {
  1535. if (xin_id[i] != xin_id[j]) {
  1536. SDE_ERROR_PLANE(sde_plane[i],
  1537. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1538. j, xin_id[j], i, xin_id[i]);
  1539. return -EINVAL;
  1540. }
  1541. }
  1542. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1543. if (!msm_fmt) {
  1544. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1545. return -EINVAL;
  1546. }
  1547. fmt[i] = to_sde_format(msm_fmt);
  1548. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1549. (fmt[i]->tile_height > max_tile_height))
  1550. max_tile_height = fmt[i]->tile_height;
  1551. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1552. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1553. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1554. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1555. drm_state[i]->crtc_h, !q16_data);
  1556. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1557. SDE_ERROR_PLANE(sde_plane[i],
  1558. "scaling is not supported in multirect mode\n");
  1559. return -EINVAL;
  1560. }
  1561. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1562. SDE_ERROR_PLANE(sde_plane[i],
  1563. "inline rotation is not supported in mulirect mode\n");
  1564. return -EINVAL;
  1565. }
  1566. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1567. SDE_ERROR_PLANE(sde_plane[i],
  1568. "Unsupported format for multirect mode\n");
  1569. return -EINVAL;
  1570. }
  1571. /**
  1572. * SSPP PD_MEM is split half - one for each RECT.
  1573. * Tiled formats need 5 lines of buffering while fetching
  1574. * whereas linear formats need only 2 lines.
  1575. * So we cannot support more than half of the supported SSPP
  1576. * width for tiled formats.
  1577. */
  1578. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1579. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1580. width_threshold[i] /= 2;
  1581. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1582. parallel_fetch_qualified = false;
  1583. if (sde_plane[i]->is_virtual)
  1584. mode = sde_plane_get_property(pstate[i],
  1585. PLANE_PROP_MULTIRECT_MODE);
  1586. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1587. const_alpha_enable = false;
  1588. }
  1589. buffer_lines = 2 * max_tile_height;
  1590. /**
  1591. * fallback to driver mode selection logic if client is using
  1592. * multirect plane without setting property.
  1593. *
  1594. * validate multirect mode configuration based on rectangle
  1595. */
  1596. switch (mode) {
  1597. case SDE_SSPP_MULTIRECT_NONE:
  1598. if (parallel_fetch_qualified)
  1599. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1600. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1601. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1602. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1603. else
  1604. SDE_ERROR(
  1605. "planes(%d - %d) multirect mode selection fail\n",
  1606. drm_state[R0]->plane->base.id,
  1607. drm_state[R1]->plane->base.id);
  1608. break;
  1609. case SDE_SSPP_MULTIRECT_PARALLEL:
  1610. if (!parallel_fetch_qualified) {
  1611. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1612. drm_state[R0]->plane->base.id,
  1613. width_threshold[R0], src[R0].w);
  1614. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1615. drm_state[R1]->plane->base.id,
  1616. width_threshold[R1], src[R1].w);
  1617. SDE_ERROR("parallel fetch not qualified\n");
  1618. mode = SDE_SSPP_MULTIRECT_NONE;
  1619. }
  1620. break;
  1621. case SDE_SSPP_MULTIRECT_TIME_MX:
  1622. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1623. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1624. SDE_ERROR(
  1625. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1626. buffer_lines, drm_state[R0]->plane->base.id,
  1627. dst[R0].y, dst[R0].h);
  1628. SDE_ERROR(
  1629. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1630. buffer_lines, drm_state[R1]->plane->base.id,
  1631. dst[R1].y, dst[R1].h);
  1632. SDE_ERROR("time multiplexed fetch not qualified\n");
  1633. mode = SDE_SSPP_MULTIRECT_NONE;
  1634. }
  1635. break;
  1636. default:
  1637. SDE_ERROR("bad mode:%d selection\n", mode);
  1638. mode = SDE_SSPP_MULTIRECT_NONE;
  1639. break;
  1640. }
  1641. for (i = 0; i < R_MAX; i++) {
  1642. pstate[i]->multirect_mode = mode;
  1643. pstate[i]->const_alpha_en = const_alpha_enable;
  1644. }
  1645. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1646. return -EINVAL;
  1647. if (sde_plane[R0]->is_virtual) {
  1648. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1649. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1650. } else {
  1651. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1652. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1653. }
  1654. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1655. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1656. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1657. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1658. return 0;
  1659. }
  1660. /**
  1661. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1662. * @plane: Pointer to drm plane structure
  1663. * @ctl: Pointer to hardware control driver
  1664. * @set: set if true else clear
  1665. */
  1666. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1667. bool set)
  1668. {
  1669. if (!plane || !ctl) {
  1670. SDE_ERROR("invalid parameters\n");
  1671. return;
  1672. }
  1673. if (!ctl->ops.update_bitmask_sspp) {
  1674. SDE_ERROR("invalid ops\n");
  1675. return;
  1676. }
  1677. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1678. }
  1679. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1680. struct drm_plane_state *new_state)
  1681. {
  1682. struct drm_framebuffer *fb = new_state->fb;
  1683. struct sde_plane *psde = to_sde_plane(plane);
  1684. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1685. struct sde_hw_fmt_layout layout;
  1686. struct msm_gem_address_space *aspace;
  1687. int ret;
  1688. if (!fb)
  1689. return 0;
  1690. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1691. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1692. if (ret) {
  1693. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1694. return ret;
  1695. }
  1696. /* cache aspace */
  1697. pstate->aspace = aspace;
  1698. /*
  1699. * when transitioning from secure to non-secure,
  1700. * plane->prepare_fb happens before the commit. In such case,
  1701. * defer the prepare_fb and handled it late, during the commit
  1702. * after attaching the domains as part of the transition
  1703. */
  1704. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1705. true : false;
  1706. if (pstate->defer_prepare_fb) {
  1707. SDE_EVT32(DRMID(plane), psde->pipe);
  1708. SDE_DEBUG_PLANE(psde,
  1709. "domain not attached, prepare_fb handled later\n");
  1710. return 0;
  1711. }
  1712. if (pstate->aspace && fb) {
  1713. ret = msm_framebuffer_prepare(fb,
  1714. pstate->aspace);
  1715. if (ret) {
  1716. SDE_ERROR("failed to prepare framebuffer\n");
  1717. return ret;
  1718. }
  1719. }
  1720. /* validate framebuffer layout before commit */
  1721. ret = sde_format_populate_layout(pstate->aspace,
  1722. fb, &layout);
  1723. if (ret) {
  1724. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1725. return ret;
  1726. }
  1727. return 0;
  1728. }
  1729. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1730. struct drm_plane_state *old_state)
  1731. {
  1732. struct sde_plane *psde = to_sde_plane(plane);
  1733. struct sde_plane_state *old_pstate;
  1734. if (!old_state || !old_state->fb || !plane)
  1735. return;
  1736. old_pstate = to_sde_plane_state(old_state);
  1737. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1738. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1739. }
  1740. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1741. struct drm_plane_state *state,
  1742. struct drm_plane_state *old_state)
  1743. {
  1744. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1745. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1746. struct drm_framebuffer *fb, *old_fb;
  1747. /* no need to check it again */
  1748. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1749. return;
  1750. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1751. || psde->is_error) {
  1752. SDE_DEBUG_PLANE(psde,
  1753. "enabling/disabling full modeset required\n");
  1754. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1755. } else if (to_sde_plane_state(old_state)->pending) {
  1756. SDE_DEBUG_PLANE(psde, "still pending\n");
  1757. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1758. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1759. pstate->multirect_mode != old_pstate->multirect_mode) {
  1760. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1761. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1762. } else if (state->src_w != old_state->src_w ||
  1763. state->src_h != old_state->src_h ||
  1764. state->src_x != old_state->src_x ||
  1765. state->src_y != old_state->src_y) {
  1766. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1767. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1768. } else if (state->crtc_w != old_state->crtc_w ||
  1769. state->crtc_h != old_state->crtc_h ||
  1770. state->crtc_x != old_state->crtc_x ||
  1771. state->crtc_y != old_state->crtc_y) {
  1772. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1773. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1774. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1775. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1776. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1777. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1778. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1779. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1780. } else if (pstate->rotation != old_pstate->rotation) {
  1781. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1782. pstate->rotation, old_pstate->rotation);
  1783. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1784. }
  1785. fb = state->fb;
  1786. old_fb = old_state->fb;
  1787. if (!fb || !old_fb) {
  1788. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1789. } else if ((fb->format->format != old_fb->format->format) ||
  1790. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1791. SDE_DEBUG_PLANE(psde, "format change\n");
  1792. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1793. } else {
  1794. uint64_t new_mod = fb->modifier;
  1795. uint64_t old_mod = old_fb->modifier;
  1796. uint32_t *new_pitches = fb->pitches;
  1797. uint32_t *old_pitches = old_fb->pitches;
  1798. uint32_t *new_offset = fb->offsets;
  1799. uint32_t *old_offset = old_fb->offsets;
  1800. int i;
  1801. if (new_mod != old_mod) {
  1802. SDE_DEBUG_PLANE(psde,
  1803. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1804. new_mod, old_mod);
  1805. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1806. SDE_PLANE_DIRTY_RECTS;
  1807. }
  1808. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1809. if (new_pitches[i] != old_pitches[i]) {
  1810. SDE_DEBUG_PLANE(psde,
  1811. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1812. i, old_pitches[i], new_pitches[i]);
  1813. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1814. break;
  1815. }
  1816. }
  1817. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1818. if (new_offset[i] != old_offset[i]) {
  1819. SDE_DEBUG_PLANE(psde,
  1820. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1821. i, old_offset[i], new_offset[i]);
  1822. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1823. SDE_PLANE_DIRTY_RECTS;
  1824. break;
  1825. }
  1826. }
  1827. }
  1828. }
  1829. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1830. unsigned long base_addr, u32 size)
  1831. {
  1832. int ret = -EINVAL;
  1833. u32 addr;
  1834. struct sde_plane *psde = to_sde_plane(plane);
  1835. if (!psde || !base_addr || !size) {
  1836. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1837. return ret;
  1838. }
  1839. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1840. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1841. is_sde_plane_virtual(plane));
  1842. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1843. ret = 0;
  1844. }
  1845. return ret;
  1846. }
  1847. static inline bool _sde_plane_is_pre_downscale_enabled(
  1848. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1849. {
  1850. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1851. }
  1852. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1853. struct sde_plane_state *pstate,
  1854. const struct sde_format *fmt,
  1855. uint32_t img_w, uint32_t img_h,
  1856. uint32_t src_w, uint32_t src_h,
  1857. uint32_t deci_w, uint32_t deci_h)
  1858. {
  1859. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1860. bool pre_down_en;
  1861. int i;
  1862. if (!psde || !pstate || !fmt) {
  1863. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1864. return -EINVAL;
  1865. }
  1866. if (psde->debugfs_default_scale ||
  1867. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1868. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1869. return 0;
  1870. pd_cfg = &pstate->pre_down;
  1871. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1872. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1873. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1874. uint32_t hor_req_pixels, hor_fetch_pixels;
  1875. uint32_t vert_req_pixels, vert_fetch_pixels;
  1876. uint32_t src_w_tmp, src_h_tmp;
  1877. uint32_t scaler_w, scaler_h;
  1878. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1879. bool rot;
  1880. /* re-use color plane 1's config for plane 2 */
  1881. if (i == 2)
  1882. continue;
  1883. if (pre_down_en) {
  1884. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1885. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1886. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1887. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1888. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1889. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1890. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1891. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1892. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1893. i, pre_down_ratio_x, pre_down_ratio_y);
  1894. }
  1895. src_w_tmp = src_w;
  1896. src_h_tmp = src_h;
  1897. /*
  1898. * For chroma plane, width is half for the following sub sampled
  1899. * formats. Except in case of decimation, where hardware avoids
  1900. * 1 line of decimation instead of downsampling.
  1901. */
  1902. if (i == 1) {
  1903. if (!deci_w &&
  1904. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1905. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1906. src_w_tmp >>= 1;
  1907. if (!deci_h &&
  1908. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1909. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1910. src_h_tmp >>= 1;
  1911. }
  1912. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1913. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1914. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1915. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1916. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1917. deci_w);
  1918. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1919. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1920. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1921. deci_h);
  1922. if ((hor_req_pixels != hor_fetch_pixels) ||
  1923. (hor_fetch_pixels > img_w) ||
  1924. (vert_req_pixels != vert_fetch_pixels) ||
  1925. (vert_fetch_pixels > img_h)) {
  1926. SDE_ERROR_PLANE(psde,
  1927. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1928. hor_req_pixels, vert_req_pixels,
  1929. hor_fetch_pixels, vert_fetch_pixels,
  1930. img_w, img_h);
  1931. return -EINVAL;
  1932. }
  1933. /*
  1934. * swap the scaler src width & height for inline-rotation 90
  1935. * comparison with Pixel-Extension, as PE is based on
  1936. * pre-rotation and QSEED is based on post-rotation
  1937. */
  1938. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1939. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1940. : pstate->scaler3_cfg.src_width[i];
  1941. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1942. : pstate->scaler3_cfg.src_height[i];
  1943. /*
  1944. * Alpha plane can only be scaled using bilinear or pixel
  1945. * repeat/drop, src_width and src_height are only specified
  1946. * for Y and UV plane
  1947. */
  1948. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1949. vert_req_pixels / pre_down_ratio_y !=
  1950. scaler_h)) {
  1951. SDE_ERROR_PLANE(psde,
  1952. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1953. i, pstate->pixel_ext.roi_w[i],
  1954. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1955. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1956. return -EINVAL;
  1957. }
  1958. /*
  1959. * SSPP fetch , unpack output and QSEED3 input lines need
  1960. * to match for Y plane
  1961. */
  1962. if (i == 0 &&
  1963. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1964. BIT(SDE_DRM_DEINTERLACE)) &&
  1965. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1966. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1967. SDE_ERROR_PLANE(psde,
  1968. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1969. i, pstate->pixel_ext.roi_w[i],
  1970. pstate->pixel_ext.roi_h[i],
  1971. pstate->scaler3_cfg.src_width[i],
  1972. pstate->scaler3_cfg.src_height[i],
  1973. src_w, src_h);
  1974. return -EINVAL;
  1975. }
  1976. }
  1977. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1978. return 0;
  1979. }
  1980. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1981. {
  1982. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1983. }
  1984. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1985. struct sde_plane_state *pstate, struct sde_rect *dst,
  1986. u32 src_w, u32 src_h)
  1987. {
  1988. int ret = 0;
  1989. u32 min_ratio_numer, min_ratio_denom;
  1990. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1991. bool pd_x;
  1992. bool pd_y;
  1993. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1994. return ret;
  1995. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1996. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1997. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1998. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1999. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  2000. SDE_ERROR_PLANE(psde,
  2001. "hw does not support pre-downscale X: 0x%x\n",
  2002. psde->features);
  2003. ret = -EINVAL;
  2004. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2005. SDE_ERROR_PLANE(psde,
  2006. "hw does not support pre-downscale Y: 0x%x\n",
  2007. psde->features);
  2008. ret = -EINVAL;
  2009. } else if (!min_ratio_numer || !min_ratio_denom) {
  2010. SDE_ERROR_PLANE(psde,
  2011. "min downscale ratio not set! %u / %u\n",
  2012. min_ratio_numer, min_ratio_denom);
  2013. ret = -EINVAL;
  2014. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2015. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2016. min_ratio_denom))) {
  2017. SDE_ERROR_PLANE(psde,
  2018. "failed min downscale-x check %u->%u, %u/%u\n",
  2019. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2020. ret = -EINVAL;
  2021. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2022. min_ratio_denom))) {
  2023. SDE_ERROR_PLANE(psde,
  2024. "failed min downscale-y check %u->%u, %u/%u\n",
  2025. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2026. ret = -EINVAL;
  2027. }
  2028. return ret;
  2029. }
  2030. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2031. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2032. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2033. u32 *max_numer_h, u32 *max_denom_h)
  2034. {
  2035. bool rotated, has_predown, default_scale;
  2036. const struct sde_sspp_sub_blks *sblk;
  2037. struct sde_hw_inline_pre_downscale_cfg *pd = NULL;
  2038. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2039. sblk = psde->pipe_sblk;
  2040. *max_numer_w = sblk->maxdwnscale;
  2041. *max_denom_w = 1;
  2042. *max_numer_h = sblk->maxdwnscale;
  2043. *max_denom_h = 1;
  2044. has_predown = _sde_plane_has_pre_downscale(psde);
  2045. if (has_predown)
  2046. pd = &pstate->pre_down;
  2047. default_scale = psde->debugfs_default_scale ||
  2048. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2049. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2050. /**
  2051. * Inline rotation has different max vertical downscaling limits since
  2052. * the source-width becomes the scaler's pre-downscaled source-height.
  2053. **/
  2054. if (rotated) {
  2055. if (pd != NULL && rt_client && has_predown) {
  2056. if (default_scale)
  2057. pd->pre_downscale_x_0 = (src_h >
  2058. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2059. *max_numer_h = pd->pre_downscale_x_0 ?
  2060. sblk->in_rot_maxdwnscale_rt_num :
  2061. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2062. *max_denom_h = pd->pre_downscale_x_0 ?
  2063. sblk->in_rot_maxdwnscale_rt_denom :
  2064. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2065. } else if (rt_client) {
  2066. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2067. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2068. } else {
  2069. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2070. }
  2071. }
  2072. }
  2073. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2074. struct sde_plane *psde, const struct sde_format *fmt,
  2075. struct sde_plane_state *pstate, struct sde_rect *src,
  2076. struct sde_rect *dst, u32 width, u32 height)
  2077. {
  2078. int ret = 0;
  2079. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2080. uint32_t scaler_src_w, scaler_src_h;
  2081. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2082. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2083. uint32_t max_upscale, max_linewidth;
  2084. bool inline_rotation, rt_client;
  2085. struct drm_crtc *crtc;
  2086. struct drm_crtc_state *new_cstate;
  2087. const struct sde_sspp_sub_blks *sblk;
  2088. if (!state || !state->state || !state->crtc) {
  2089. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2090. return -EINVAL;
  2091. }
  2092. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2093. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2094. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2095. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2096. /* with inline rotator, the source of the scaler is post-rotated */
  2097. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2098. if (inline_rotation) {
  2099. scaler_src_w = src_deci_h;
  2100. scaler_src_h = src_deci_w;
  2101. } else {
  2102. scaler_src_w = src_deci_w;
  2103. scaler_src_h = src_deci_h;
  2104. }
  2105. sblk = psde->pipe_sblk;
  2106. max_upscale = sblk->maxupscale;
  2107. if (inline_rotation)
  2108. max_linewidth = sblk->in_rot_maxheight;
  2109. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2110. max_linewidth = sblk->scaling_linewidth;
  2111. else
  2112. max_linewidth = sblk->maxlinewidth;
  2113. crtc = state->crtc;
  2114. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2115. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2116. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2117. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2118. &max_downscale_num_h, &max_downscale_denom_h);
  2119. /* decimation validation */
  2120. if ((deci_w || deci_h)
  2121. && ((deci_w > sblk->maxhdeciexp)
  2122. || (deci_h > sblk->maxvdeciexp))) {
  2123. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2124. ret = -EINVAL;
  2125. } else if ((deci_w || deci_h)
  2126. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2127. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2128. ret = -EINVAL;
  2129. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2130. ((src->w != dst->w) || (src->h != dst->h))) {
  2131. SDE_ERROR_PLANE(psde,
  2132. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2133. src->w, src->h, dst->w, dst->h);
  2134. ret = -EINVAL;
  2135. /* check scaler source width */
  2136. } else if (scaler_src_w > max_linewidth) {
  2137. SDE_ERROR_PLANE(psde,
  2138. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2139. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2140. ret = -E2BIG;
  2141. /* check max scaler capability */
  2142. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2143. ((scaler_src_h * max_upscale) < dst->h) ||
  2144. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2145. < scaler_src_w) ||
  2146. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2147. < scaler_src_h)) {
  2148. SDE_ERROR_PLANE(psde,
  2149. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2150. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2151. inline_rotation, max_downscale_num_w,
  2152. max_downscale_denom_w, max_downscale_num_h,
  2153. max_downscale_denom_h);
  2154. ret = -E2BIG;
  2155. /* check inline pre-downscale support */
  2156. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2157. pstate, dst, src_deci_w, src_deci_h)) {
  2158. ret = -EINVAL;
  2159. /* QSEED validation */
  2160. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2161. width, height, src->w, src->h,
  2162. deci_w, deci_h)) {
  2163. ret = -EINVAL;
  2164. }
  2165. return ret;
  2166. }
  2167. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2168. struct sde_plane_state *pstate, struct sde_rect *src,
  2169. const struct sde_format *fmt, int ret)
  2170. {
  2171. /* check excl rect configs */
  2172. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2173. struct sde_rect intersect;
  2174. /*
  2175. * Check exclusion rect against src rect.
  2176. * it must intersect with source rect.
  2177. */
  2178. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2179. if (intersect.w != pstate->excl_rect.w ||
  2180. intersect.h != pstate->excl_rect.h ||
  2181. SDE_FORMAT_IS_YUV(fmt)) {
  2182. SDE_ERROR_PLANE(psde,
  2183. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2184. pstate->excl_rect.x, pstate->excl_rect.y,
  2185. pstate->excl_rect.w, pstate->excl_rect.h,
  2186. src->x, src->y, src->w, src->h,
  2187. (char *)&fmt->base.pixel_format);
  2188. ret = -EINVAL;
  2189. }
  2190. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2191. pstate->excl_rect.x, pstate->excl_rect.y,
  2192. pstate->excl_rect.w, pstate->excl_rect.h);
  2193. }
  2194. return ret;
  2195. }
  2196. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2197. struct drm_plane_state *state)
  2198. {
  2199. struct sde_kms *sde_kms;
  2200. struct sde_splash_display *splash_display;
  2201. int i;
  2202. sde_kms = _sde_plane_get_kms(&psde->base);
  2203. if (!sde_kms || !state->crtc)
  2204. return 0;
  2205. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2206. splash_display = &sde_kms->splash_data.splash_display[i];
  2207. if (splash_display && splash_display->cont_splash_enabled &&
  2208. splash_display->encoder &&
  2209. state->crtc != splash_display->encoder->crtc) {
  2210. struct sde_sspp_index_info *pipe_info = &splash_display->pipe_info;
  2211. if (test_bit(psde->pipe, pipe_info->pipes) ||
  2212. test_bit(psde->pipe, pipe_info->virt_pipes)) {
  2213. SDE_ERROR_PLANE(psde, "pipe:%d used in cont-splash on crtc:%d\n",
  2214. psde->pipe,
  2215. splash_display->encoder->crtc->base.id);
  2216. return -EINVAL;
  2217. }
  2218. }
  2219. }
  2220. return 0;
  2221. }
  2222. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2223. const struct sde_format *fmt,
  2224. struct sde_rect src, struct sde_rect dst,
  2225. u32 width, u32 height)
  2226. {
  2227. int ret = 0;
  2228. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2229. if (SDE_FORMAT_IS_YUV(fmt) &&
  2230. (!(psde->features & SDE_SSPP_SCALER) ||
  2231. !(psde->features & (BIT(SDE_SSPP_CSC)
  2232. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2233. SDE_ERROR_PLANE(psde,
  2234. "plane doesn't have scaler/csc for yuv\n");
  2235. ret = -EINVAL;
  2236. /* check src bounds */
  2237. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2238. src.w < min_src_size || src.h < min_src_size ||
  2239. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2240. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2241. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2242. src.x, src.y, src.w, src.h);
  2243. ret = -E2BIG;
  2244. /* valid yuv image */
  2245. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2246. (src.w & 0x1) || (src.h & 0x1))) {
  2247. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2248. src.x, src.y, src.w, src.h);
  2249. ret = -EINVAL;
  2250. /* min dst support */
  2251. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2252. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2253. dst.x, dst.y, dst.w, dst.h);
  2254. ret = -EINVAL;
  2255. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2256. !psde->catalog->ubwc_rev) {
  2257. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2258. ret = -EINVAL;
  2259. }
  2260. return ret;
  2261. }
  2262. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2263. struct drm_plane_state *state)
  2264. {
  2265. int ret = 0;
  2266. struct sde_plane *psde;
  2267. struct sde_plane_state *pstate;
  2268. const struct msm_format *msm_fmt;
  2269. const struct sde_format *fmt;
  2270. struct sde_rect src, dst;
  2271. bool q16_data = true;
  2272. struct drm_framebuffer *fb;
  2273. u32 width;
  2274. u32 height;
  2275. psde = to_sde_plane(plane);
  2276. pstate = to_sde_plane_state(state);
  2277. if (!psde->pipe_sblk) {
  2278. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2279. return -EINVAL;
  2280. }
  2281. /* src values are in Q16 fixed point, convert to integer */
  2282. POPULATE_RECT(&src, state->src_x, state->src_y,
  2283. state->src_w, state->src_h, q16_data);
  2284. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2285. state->crtc_h, !q16_data);
  2286. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2287. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2288. if (!sde_plane_enabled(state))
  2289. goto modeset_update;
  2290. fb = state->fb;
  2291. width = fb ? state->fb->width : 0x0;
  2292. height = fb ? state->fb->height : 0x0;
  2293. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2294. plane->base.id,
  2295. pstate->rotation,
  2296. width, height,
  2297. fb ? (char *) &state->fb->format->format : 0x0,
  2298. fb ? state->fb->modifier : 0x0);
  2299. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2300. state->src_w >> 16, state->src_h >> 16,
  2301. state->src_x >> 16, state->src_y >> 16,
  2302. state->crtc_w, state->crtc_h,
  2303. state->crtc_x, state->crtc_y);
  2304. msm_fmt = msm_framebuffer_format(fb);
  2305. fmt = to_sde_format(msm_fmt);
  2306. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2307. height);
  2308. if (ret)
  2309. return ret;
  2310. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2311. &src, &dst, width, height);
  2312. if (ret)
  2313. return ret;
  2314. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2315. &src, fmt, ret);
  2316. if (ret)
  2317. return ret;
  2318. ret = _sde_plane_validate_shared_crtc(psde, state);
  2319. if (ret)
  2320. return ret;
  2321. pstate->const_alpha_en = fmt->alpha_enable &&
  2322. (SDE_DRM_BLEND_OP_OPAQUE !=
  2323. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2324. (pstate->stage != SDE_STAGE_0);
  2325. modeset_update:
  2326. if (!ret)
  2327. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2328. state, plane->state);
  2329. return ret;
  2330. }
  2331. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2332. static int sde_plane_atomic_check(struct drm_plane *plane,
  2333. struct drm_atomic_state *atomic_state)
  2334. #else
  2335. static int sde_plane_atomic_check(struct drm_plane *plane,
  2336. struct drm_plane_state *state)
  2337. #endif
  2338. {
  2339. int ret = 0;
  2340. struct sde_plane *psde;
  2341. struct sde_plane_state *pstate;
  2342. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2343. struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, plane);
  2344. #endif
  2345. if (!plane || !state) {
  2346. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2347. !plane, !state);
  2348. ret = -EINVAL;
  2349. goto exit;
  2350. }
  2351. psde = to_sde_plane(plane);
  2352. pstate = to_sde_plane_state(state);
  2353. SDE_DEBUG_PLANE(psde, "\n");
  2354. ret = sde_plane_rot_atomic_check(plane, state);
  2355. if (ret)
  2356. goto exit;
  2357. ret = sde_plane_sspp_atomic_check(plane, state);
  2358. exit:
  2359. return ret;
  2360. }
  2361. void sde_plane_flush(struct drm_plane *plane)
  2362. {
  2363. struct sde_plane *psde;
  2364. struct sde_plane_state *pstate;
  2365. if (!plane || !plane->state) {
  2366. SDE_ERROR("invalid plane\n");
  2367. return;
  2368. }
  2369. psde = to_sde_plane(plane);
  2370. pstate = to_sde_plane_state(plane->state);
  2371. /*
  2372. * These updates have to be done immediately before the plane flush
  2373. * timing, and may not be moved to the atomic_update/mode_set functions.
  2374. */
  2375. if (psde->is_error)
  2376. /* force white frame with 100% alpha pipe output on error */
  2377. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2378. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2379. /* force 100% alpha */
  2380. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2381. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2382. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2383. /* flag h/w flush complete */
  2384. if (plane->state)
  2385. pstate->pending = false;
  2386. }
  2387. /**
  2388. * sde_plane_set_error: enable/disable error condition
  2389. * @plane: pointer to drm_plane structure
  2390. */
  2391. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2392. {
  2393. struct sde_plane *psde;
  2394. if (!plane)
  2395. return;
  2396. psde = to_sde_plane(plane);
  2397. psde->is_error = error;
  2398. }
  2399. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2400. struct sde_plane_state *pstate)
  2401. {
  2402. struct drm_plane_state *state = psde->base.state;
  2403. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2404. struct sde_hw_pipe_sc_cfg *cfg = &pstate->sc_cfg;
  2405. bool prev_rd_en = cfg->rd_en;
  2406. u32 fb_cache_flag, fb_cache_type;
  2407. msm_framebuffer_get_cache_hint(state->fb, &fb_cache_flag, &fb_cache_type);
  2408. cfg->rd_en = false;
  2409. cfg->rd_scid = 0x0;
  2410. cfg->flags = SYS_CACHE_EN_FLAG | SYS_CACHE_SCID;
  2411. cfg->type = SDE_SYS_CACHE_NONE;
  2412. if ((sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
  2413. && ((pstate->static_cache_state == CACHE_STATE_FRAME_WRITE)
  2414. || (pstate->static_cache_state == CACHE_STATE_FRAME_READ))) {
  2415. cfg->rd_en = true;
  2416. cfg->rd_scid = sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2417. cfg->rd_noallocate = (pstate->static_cache_state == CACHE_STATE_FRAME_READ);
  2418. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2419. cfg->type = SDE_SYS_CACHE_DISP;
  2420. } else if ((sc_cfg[fb_cache_type].has_sys_cache)
  2421. && (fb_cache_flag & MSM_FB_CACHE_WRITE_EN)) {
  2422. cfg->rd_en = true;
  2423. cfg->rd_scid = sc_cfg[fb_cache_type].llcc_scid;
  2424. cfg->rd_noallocate = true;
  2425. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2426. cfg->type = fb_cache_type;
  2427. msm_framebuffer_set_cache_hint(state->fb, MSM_FB_CACHE_READ_EN, fb_cache_type);
  2428. }
  2429. if (!cfg->rd_en && !prev_rd_en)
  2430. return;
  2431. SDE_EVT32(DRMID(&psde->base), cfg->rd_scid, cfg->rd_en, cfg->rd_noallocate, cfg->flags,
  2432. fb_cache_flag, fb_cache_type);
  2433. psde->pipe_hw->ops.setup_sys_cache(psde->pipe_hw, cfg);
  2434. }
  2435. void sde_plane_static_img_control(struct drm_plane *plane,
  2436. enum sde_sys_cache_state state)
  2437. {
  2438. struct sde_plane *psde;
  2439. struct sde_plane_state *pstate;
  2440. if (!plane || !plane->state) {
  2441. SDE_ERROR("invalid plane\n");
  2442. return;
  2443. }
  2444. psde = to_sde_plane(plane);
  2445. pstate = to_sde_plane_state(plane->state);
  2446. pstate->static_cache_state = state;
  2447. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2448. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2449. }
  2450. static void _sde_plane_map_prop_to_dirty_bits(void)
  2451. {
  2452. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2453. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2454. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2455. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2456. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2457. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2458. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2459. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2460. plane_prop_array[PLANE_PROP_ZPOS] =
  2461. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2462. plane_prop_array[PLANE_PROP_UBWC_STATS_ROI] =
  2463. SDE_PLANE_DIRTY_RECTS;
  2464. plane_prop_array[PLANE_PROP_CSC_V1] =
  2465. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2466. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2467. SDE_PLANE_DIRTY_FORMAT;
  2468. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2469. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2470. SDE_PLANE_DIRTY_ALL;
  2471. /* no special action required */
  2472. plane_prop_array[PLANE_PROP_INFO] =
  2473. plane_prop_array[PLANE_PROP_ALPHA] =
  2474. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2475. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2476. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2477. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2478. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2479. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2480. SDE_PLANE_DIRTY_PERF;
  2481. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2482. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2483. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2484. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2485. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2486. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2487. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2488. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2489. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2490. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2491. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2492. SDE_PLANE_DIRTY_ALL;
  2493. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2494. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2495. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2496. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2497. }
  2498. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2499. struct sde_rect *src, struct sde_rect *dst)
  2500. {
  2501. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2502. u32 downscale = (src->h * 1000)/dst->h;
  2503. return (downscale > max_downscale) ? false : true;
  2504. }
  2505. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2506. struct sde_plane *psde, struct sde_plane_state *pstate,
  2507. struct sde_rect *src, struct sde_rect *dst)
  2508. {
  2509. struct sde_hw_pipe_uidle_cfg cfg;
  2510. u32 line_time = sde_crtc_get_line_time(crtc);
  2511. u32 fal1_target_idle_time_ns =
  2512. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2513. u32 fal10_target_idle_time_ns =
  2514. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2515. u32 fal10_threshold =
  2516. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2517. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2518. fal1_target_idle_time_ns) {
  2519. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2520. cfg.fal10_threshold = fal10_threshold;
  2521. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2522. cfg.fal1_threshold = min(1 +
  2523. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2524. psde->catalog->uidle_cfg.fal1_max_threshold);
  2525. cfg.fal_allowed_threshold = fal10_threshold +
  2526. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2527. cfg.fill_level_scale = 0;
  2528. /*
  2529. * if uidle fill scale is supported, determing the scale value
  2530. * and adjust fal10 thresholds to their scaled values.
  2531. * fal1 thresholds and fal_allowed are not scaled.
  2532. */
  2533. if (psde->pipe_hw->ops.setup_uidle_fill_scale) {
  2534. u32 fl_require0 = psde->catalog->qos_target_time_ns / line_time * 2;
  2535. u32 fl_require = max(fal10_threshold * 1000, fl_require0);
  2536. u32 fl_scale = fl_require / fal10_threshold;
  2537. u32 fal10_threshold_noscale;
  2538. cfg.fill_level_scale = (fl_scale <= 1) ? 0 : (32 / fl_scale);
  2539. if (cfg.fill_level_scale) {
  2540. fal10_threshold_noscale = fal10_threshold *
  2541. 32/cfg.fill_level_scale;
  2542. cfg.fal_allowed_threshold = fal10_threshold_noscale +
  2543. (fal10_target_idle_time_ns * 1000 / line_time * 2) / 1000;
  2544. }
  2545. }
  2546. } else {
  2547. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2548. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2549. fal1_target_idle_time_ns);
  2550. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2551. }
  2552. SDE_DEBUG_PLANE(psde,
  2553. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d fill_scale=%d\n",
  2554. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2555. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2556. cfg.fill_level_scale);
  2557. SDE_DEBUG_PLANE(psde,
  2558. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2559. line_time, fal1_target_idle_time_ns,
  2560. fal10_target_idle_time_ns,
  2561. psde->catalog->uidle_cfg.max_dwnscale);
  2562. SDE_EVT32_VERBOSE(cfg.enable,
  2563. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2564. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2565. cfg.fill_level_scale, psde->catalog->uidle_cfg.max_dwnscale);
  2566. if (psde->pipe_hw->ops.setup_uidle_fill_scale)
  2567. psde->pipe_hw->ops.setup_uidle_fill_scale(psde->pipe_hw, &cfg);
  2568. psde->pipe_hw->ops.setup_uidle(
  2569. psde->pipe_hw, &cfg,
  2570. pstate->multirect_index);
  2571. }
  2572. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2573. struct sde_plane_state *pstate)
  2574. {
  2575. bool enable = false;
  2576. int mode = sde_plane_get_property(pstate,
  2577. PLANE_PROP_FB_TRANSLATION_MODE);
  2578. if ((mode == SDE_DRM_FB_SEC) ||
  2579. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2580. enable = true;
  2581. /* update secure session flag */
  2582. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2583. pstate->multirect_index,
  2584. enable);
  2585. }
  2586. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2587. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2588. {
  2589. const struct sde_format *fmt;
  2590. const struct msm_format *msm_fmt;
  2591. struct sde_plane *psde;
  2592. struct drm_plane_state *state;
  2593. struct sde_plane_state *pstate;
  2594. struct sde_rect src, dst;
  2595. const struct sde_rect *crtc_roi;
  2596. bool q16_data = true;
  2597. int idx;
  2598. psde = to_sde_plane(plane);
  2599. state = plane->state;
  2600. pstate = to_sde_plane_state(state);
  2601. msm_fmt = msm_framebuffer_format(fb);
  2602. if (!msm_fmt) {
  2603. SDE_ERROR("crtc%d plane%d: null format\n",
  2604. DRMID(crtc), DRMID(plane));
  2605. return;
  2606. }
  2607. fmt = to_sde_format(msm_fmt);
  2608. POPULATE_RECT(&src, state->src_x, state->src_y,
  2609. state->src_w, state->src_h, q16_data);
  2610. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2611. state->crtc_w, state->crtc_h, !q16_data);
  2612. SDE_DEBUG_PLANE(psde,
  2613. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2614. fb->base.id, src.x, src.y, src.w, src.h,
  2615. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2616. (char *)&fmt->base.pixel_format,
  2617. SDE_FORMAT_IS_UBWC(fmt));
  2618. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2619. BIT(SDE_DRM_DEINTERLACE)) {
  2620. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2621. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2622. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2623. src.h /= 2;
  2624. src.y = DIV_ROUND_UP(src.y, 2);
  2625. src.y &= ~0x1;
  2626. }
  2627. /*
  2628. * adjust layer mixer position of the sspp in the presence
  2629. * of a partial update to the active lm origin
  2630. */
  2631. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2632. dst.x -= crtc_roi->x;
  2633. dst.y -= crtc_roi->y;
  2634. /* check for UIDLE */
  2635. if (psde->pipe_hw->ops.setup_uidle)
  2636. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2637. psde->pipe_cfg.src_rect = src;
  2638. psde->pipe_cfg.dst_rect = dst;
  2639. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2640. /* check for color fill */
  2641. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2642. PLANE_PROP_COLOR_FILL);
  2643. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2644. /* skip remaining processing on color fill */
  2645. pstate->dirty = 0x0;
  2646. } else if (psde->pipe_hw->ops.setup_rects) {
  2647. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2648. &psde->pipe_cfg,
  2649. pstate->multirect_index);
  2650. }
  2651. if (psde->pipe_hw->ops.setup_pe &&
  2652. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2653. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2654. &psde->pixel_ext);
  2655. /**
  2656. * when programmed in multirect mode, scalar block will be
  2657. * bypassed. Still we need to update alpha and bitwidth
  2658. * ONLY for RECT0
  2659. */
  2660. if (psde->pipe_hw->ops.setup_scaler &&
  2661. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2662. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2663. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2664. &psde->pipe_cfg, &psde->pixel_ext,
  2665. &psde->scaler3_cfg);
  2666. }
  2667. /* update excl rect */
  2668. if (psde->pipe_hw->ops.setup_excl_rect)
  2669. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2670. &pstate->excl_rect,
  2671. pstate->multirect_index);
  2672. /* enable multirect config of corresponding rect */
  2673. if (psde->pipe_hw->ops.update_multirect)
  2674. psde->pipe_hw->ops.update_multirect(
  2675. psde->pipe_hw,
  2676. true,
  2677. pstate->multirect_index,
  2678. pstate->multirect_mode);
  2679. }
  2680. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2681. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2682. {
  2683. uint32_t src_flags = 0;
  2684. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2685. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2686. src_flags |= SDE_SSPP_FLIP_LR;
  2687. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2688. src_flags |= SDE_SSPP_FLIP_UD;
  2689. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2690. src_flags |= SDE_SSPP_ROT_90;
  2691. /* update format */
  2692. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2693. pstate->const_alpha_en, src_flags,
  2694. pstate->multirect_index);
  2695. if (psde->pipe_hw->ops.setup_cdp) {
  2696. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2697. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2698. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2699. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2700. cdp_cfg->ubwc_meta_enable =
  2701. SDE_FORMAT_IS_UBWC(fmt);
  2702. cdp_cfg->tile_amortize_enable =
  2703. SDE_FORMAT_IS_UBWC(fmt) ||
  2704. SDE_FORMAT_IS_TILE(fmt);
  2705. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2706. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2707. pstate->multirect_index);
  2708. }
  2709. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2710. /* update csc */
  2711. if (SDE_FORMAT_IS_YUV(fmt))
  2712. _sde_plane_setup_csc(psde);
  2713. else
  2714. psde->csc_ptr = 0;
  2715. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2716. uint32_t pma_mode = 0;
  2717. if (fmt->alpha_enable)
  2718. pma_mode = (uint32_t) sde_plane_get_property(
  2719. pstate, PLANE_PROP_INVERSE_PMA);
  2720. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2721. pstate->multirect_index, pma_mode);
  2722. }
  2723. if (psde->pipe_hw->ops.setup_dgm_csc)
  2724. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2725. pstate->multirect_index, psde->csc_usr_ptr);
  2726. if (psde->pipe_hw->ops.set_ubwc_stats_roi) {
  2727. if (SDE_FORMAT_IS_UBWC(fmt) && !SDE_FORMAT_IS_YUV(fmt))
  2728. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2729. pstate->multirect_index, &pstate->ubwc_stats_roi);
  2730. else
  2731. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2732. pstate->multirect_index, NULL);
  2733. }
  2734. }
  2735. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2736. {
  2737. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2738. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2739. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2740. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2741. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2742. &psde->sharp_cfg);
  2743. }
  2744. static void _sde_plane_update_properties(struct drm_plane *plane,
  2745. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2746. {
  2747. uint32_t nplanes;
  2748. const struct msm_format *msm_fmt;
  2749. const struct sde_format *fmt;
  2750. struct sde_plane *psde;
  2751. struct drm_plane_state *state;
  2752. struct sde_plane_state *pstate;
  2753. psde = to_sde_plane(plane);
  2754. state = plane->state;
  2755. pstate = to_sde_plane_state(state);
  2756. if (!pstate) {
  2757. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2758. return;
  2759. }
  2760. msm_fmt = msm_framebuffer_format(fb);
  2761. if (!msm_fmt) {
  2762. SDE_ERROR("crtc%d plane%d: null format\n",
  2763. DRMID(crtc), DRMID(plane));
  2764. return;
  2765. }
  2766. fmt = to_sde_format(msm_fmt);
  2767. nplanes = fmt->num_planes;
  2768. /* update secure session flag */
  2769. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2770. _sde_plane_update_secure_session(psde, pstate);
  2771. /* update roi config */
  2772. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2773. _sde_plane_update_roi_config(plane, crtc, fb);
  2774. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2775. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2776. psde->pipe_hw->ops.setup_format)
  2777. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2778. sde_color_process_plane_setup(plane);
  2779. /* update sharpening */
  2780. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2781. psde->pipe_hw->ops.setup_sharpening)
  2782. _sde_plane_update_sharpening(psde);
  2783. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2784. SDE_PLANE_DIRTY_FORMAT))
  2785. _sde_plane_set_qos_lut(plane, crtc, fb);
  2786. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2787. _sde_plane_set_ot_limit(plane, crtc);
  2788. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2789. _sde_plane_set_ts_prefill(plane, pstate);
  2790. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2791. _sde_plane_set_qos_remap(plane);
  2792. /* clear dirty */
  2793. pstate->dirty = 0x0;
  2794. }
  2795. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2796. struct drm_plane_state *old_state)
  2797. {
  2798. struct sde_plane *psde;
  2799. struct drm_plane_state *state;
  2800. struct sde_plane_state *pstate;
  2801. struct sde_plane_state *old_pstate;
  2802. struct drm_crtc *crtc;
  2803. struct drm_framebuffer *fb;
  2804. int idx;
  2805. int dirty_prop_flag;
  2806. bool is_rt;
  2807. if (!plane) {
  2808. SDE_ERROR("invalid plane\n");
  2809. return -EINVAL;
  2810. } else if (!plane->state) {
  2811. SDE_ERROR("invalid plane state\n");
  2812. return -EINVAL;
  2813. } else if (!old_state) {
  2814. SDE_ERROR("invalid old state\n");
  2815. return -EINVAL;
  2816. }
  2817. psde = to_sde_plane(plane);
  2818. state = plane->state;
  2819. pstate = to_sde_plane_state(state);
  2820. old_pstate = to_sde_plane_state(old_state);
  2821. crtc = state->crtc;
  2822. fb = state->fb;
  2823. if (!crtc || !fb) {
  2824. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2825. !crtc, !fb);
  2826. return -EINVAL;
  2827. }
  2828. SDE_DEBUG(
  2829. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2830. plane->base.id,
  2831. state->fb->width, state->fb->height,
  2832. (char *) &state->fb->format->format,
  2833. state->fb->modifier,
  2834. state->src_w >> 16, state->src_h >> 16,
  2835. state->src_x >> 16, state->src_y >> 16,
  2836. pstate->rotation,
  2837. state->crtc_w, state->crtc_h,
  2838. state->crtc_x, state->crtc_y);
  2839. /* force reprogramming of all the parameters, if the flag is set */
  2840. if (psde->revalidate) {
  2841. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2842. plane->base.id);
  2843. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2844. psde->revalidate = false;
  2845. }
  2846. /* determine what needs to be refreshed */
  2847. mutex_lock(&psde->property_info.property_lock);
  2848. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2849. &pstate->property_state)) >= 0) {
  2850. dirty_prop_flag = plane_prop_array[idx];
  2851. pstate->dirty |= dirty_prop_flag;
  2852. }
  2853. mutex_unlock(&psde->property_info.property_lock);
  2854. /**
  2855. * since plane_atomic_check is invoked before crtc_atomic_check
  2856. * in the commit sequence, all the parameters for updating the
  2857. * plane dirty flag will not be available during
  2858. * plane_atomic_check as some features params are updated
  2859. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2860. * before sspp update.
  2861. */
  2862. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2863. old_state);
  2864. /* re-program the output rects always if partial update roi changed */
  2865. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2866. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2867. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2868. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2869. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2870. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2871. if (is_rt != psde->is_rt_pipe || crtc->state->mode_changed) {
  2872. psde->is_rt_pipe = is_rt;
  2873. psde->wb_usage_type = psde->is_rt_pipe ? 0 : sde_crtc_get_wb_usage_type(crtc);
  2874. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2875. }
  2876. /* early out if nothing dirty */
  2877. if (!pstate->dirty)
  2878. return 0;
  2879. pstate->pending = true;
  2880. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2881. _sde_plane_update_properties(plane, crtc, fb);
  2882. return 0;
  2883. }
  2884. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2885. struct drm_plane_state *old_state)
  2886. {
  2887. struct sde_plane *psde;
  2888. struct drm_plane_state *state;
  2889. struct sde_plane_state *pstate;
  2890. u32 multirect_index = SDE_SSPP_RECT_0;
  2891. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  2892. u32 blend_type;
  2893. if (!plane) {
  2894. SDE_ERROR("invalid plane\n");
  2895. return;
  2896. } else if (!plane->state) {
  2897. SDE_ERROR("invalid plane state\n");
  2898. return;
  2899. } else if (!old_state) {
  2900. SDE_ERROR("invalid old state\n");
  2901. return;
  2902. }
  2903. psde = to_sde_plane(plane);
  2904. state = plane->state;
  2905. pstate = to_sde_plane_state(state);
  2906. blend_type = sde_plane_get_property(pstate,
  2907. PLANE_PROP_BLEND_OP);
  2908. /* some of the color features are dependent on plane with skip blend.
  2909. * if skip blend plane is being disabled, we need to disable color properties.
  2910. */
  2911. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  2912. skip_blend_plane.valid_plane = false;
  2913. skip_blend_plane.plane = SSPP_NONE;
  2914. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  2915. sde_crtc_disable_cp_features(old_state->crtc);
  2916. }
  2917. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2918. pstate->multirect_mode);
  2919. pstate->pending = true;
  2920. if (is_sde_plane_virtual(plane))
  2921. multirect_index = SDE_SSPP_RECT_1;
  2922. /* disable multirect config of corresponding rect */
  2923. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2924. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2925. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2926. }
  2927. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2928. static void _sde_plane_atomic_update(struct drm_plane *plane,
  2929. struct drm_plane_state *old_state)
  2930. #else
  2931. static void sde_plane_atomic_update(struct drm_plane *plane,
  2932. struct drm_plane_state *old_state)
  2933. #endif
  2934. {
  2935. struct sde_plane *psde;
  2936. struct drm_plane_state *state;
  2937. if (!plane) {
  2938. SDE_ERROR("invalid plane\n");
  2939. return;
  2940. } else if (!plane->state) {
  2941. SDE_ERROR("invalid plane state\n");
  2942. return;
  2943. }
  2944. psde = to_sde_plane(plane);
  2945. psde->is_error = false;
  2946. state = plane->state;
  2947. SDE_DEBUG_PLANE(psde, "\n");
  2948. if (!sde_plane_enabled(state)) {
  2949. _sde_plane_atomic_disable(plane, old_state);
  2950. } else {
  2951. int ret;
  2952. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2953. /* atomic_check should have ensured that this doesn't fail */
  2954. WARN_ON(ret < 0);
  2955. }
  2956. }
  2957. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2958. static void sde_plane_atomic_update(struct drm_plane *plane,
  2959. struct drm_atomic_state *atomic_state)
  2960. {
  2961. struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(atomic_state, plane);
  2962. _sde_plane_atomic_update(plane, old_state);
  2963. }
  2964. #endif
  2965. void sde_plane_restore(struct drm_plane *plane)
  2966. {
  2967. struct sde_plane *psde;
  2968. if (!plane || !plane->state) {
  2969. SDE_ERROR("invalid plane\n");
  2970. return;
  2971. }
  2972. psde = to_sde_plane(plane);
  2973. /*
  2974. * Revalidate is only true here if idle PC occurred and
  2975. * there is no plane state update in current commit cycle.
  2976. */
  2977. if (!psde->revalidate)
  2978. return;
  2979. SDE_DEBUG_PLANE(psde, "\n");
  2980. /* last plane state is same as current state */
  2981. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2982. _sde_plane_atomic_update(plane, plane->state);
  2983. #else
  2984. sde_plane_atomic_update(plane, plane->state);
  2985. #endif
  2986. }
  2987. bool sde_plane_is_cache_required(struct drm_plane *plane,
  2988. enum sde_sys_cache_type type)
  2989. {
  2990. struct sde_plane_state *pstate;
  2991. if (!plane || !plane->state) {
  2992. SDE_ERROR("invalid plane\n");
  2993. return false;
  2994. }
  2995. pstate = to_sde_plane_state(plane->state);
  2996. /* check if llcc is required for the plane */
  2997. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  2998. return true;
  2999. else
  3000. return false;
  3001. }
  3002. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  3003. {
  3004. char feature_name[256];
  3005. if (psde->pipe_sblk->maxhdeciexp) {
  3006. msm_property_install_range(&psde->property_info,
  3007. "h_decimate", 0x0, 0,
  3008. psde->pipe_sblk->maxhdeciexp, 0,
  3009. PLANE_PROP_H_DECIMATE);
  3010. }
  3011. if (psde->pipe_sblk->maxvdeciexp) {
  3012. msm_property_install_range(&psde->property_info,
  3013. "v_decimate", 0x0, 0,
  3014. psde->pipe_sblk->maxvdeciexp, 0,
  3015. PLANE_PROP_V_DECIMATE);
  3016. }
  3017. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  3018. msm_property_install_range(
  3019. &psde->property_info, "scaler_v2",
  3020. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3021. msm_property_install_blob(&psde->property_info,
  3022. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  3023. msm_property_install_blob(&psde->property_info,
  3024. "lut_cir", 0,
  3025. PLANE_PROP_SCALER_LUT_CIR);
  3026. msm_property_install_blob(&psde->property_info,
  3027. "lut_sep", 0,
  3028. PLANE_PROP_SCALER_LUT_SEP);
  3029. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  3030. msm_property_install_range(
  3031. &psde->property_info, "scaler_v2",
  3032. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3033. msm_property_install_blob(&psde->property_info,
  3034. "lut_sep", 0,
  3035. PLANE_PROP_SCALER_LUT_SEP);
  3036. } else if (psde->features & SDE_SSPP_SCALER) {
  3037. msm_property_install_range(
  3038. &psde->property_info, "scaler_v1", 0x0,
  3039. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  3040. }
  3041. if (psde->features & BIT(SDE_SSPP_CSC) ||
  3042. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  3043. msm_property_install_volatile_range(
  3044. &psde->property_info, "csc_v1", 0x0,
  3045. 0, ~0, 0, PLANE_PROP_CSC_V1);
  3046. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  3047. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3048. "SDE_SSPP_HUE_V",
  3049. psde->pipe_sblk->hsic_blk.version >> 16);
  3050. msm_property_install_range(&psde->property_info,
  3051. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3052. PLANE_PROP_HUE_ADJUST);
  3053. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3054. "SDE_SSPP_SATURATION_V",
  3055. psde->pipe_sblk->hsic_blk.version >> 16);
  3056. msm_property_install_range(&psde->property_info,
  3057. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3058. PLANE_PROP_SATURATION_ADJUST);
  3059. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3060. "SDE_SSPP_VALUE_V",
  3061. psde->pipe_sblk->hsic_blk.version >> 16);
  3062. msm_property_install_range(&psde->property_info,
  3063. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3064. PLANE_PROP_VALUE_ADJUST);
  3065. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3066. "SDE_SSPP_CONTRAST_V",
  3067. psde->pipe_sblk->hsic_blk.version >> 16);
  3068. msm_property_install_range(&psde->property_info,
  3069. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3070. PLANE_PROP_CONTRAST_ADJUST);
  3071. }
  3072. }
  3073. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3074. struct sde_kms_info *info)
  3075. {
  3076. char feature_name[256];
  3077. bool is_master = !psde->is_virtual;
  3078. if ((is_master &&
  3079. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3080. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3081. msm_property_install_range(&psde->property_info,
  3082. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3083. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3084. }
  3085. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3086. msm_property_install_volatile_range(
  3087. &psde->property_info, "csc_dma_v1", 0x0,
  3088. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3089. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3090. }
  3091. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3092. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3093. "SDE_SSPP_SKIN_COLOR_V",
  3094. psde->pipe_sblk->memcolor_blk.version >> 16);
  3095. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3096. PLANE_PROP_SKIN_COLOR);
  3097. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3098. "SDE_SSPP_SKY_COLOR_V",
  3099. psde->pipe_sblk->memcolor_blk.version >> 16);
  3100. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3101. PLANE_PROP_SKY_COLOR);
  3102. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3103. "SDE_SSPP_FOLIAGE_COLOR_V",
  3104. psde->pipe_sblk->memcolor_blk.version >> 16);
  3105. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3106. PLANE_PROP_FOLIAGE_COLOR);
  3107. }
  3108. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3109. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3110. "SDE_VIG_3D_LUT_GAMUT_V",
  3111. psde->pipe_sblk->gamut_blk.version >> 16);
  3112. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3113. PLANE_PROP_VIG_GAMUT);
  3114. }
  3115. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3116. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3117. "SDE_VIG_1D_LUT_IGC_V",
  3118. psde->pipe_sblk->igc_blk[0].version >> 16);
  3119. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3120. PLANE_PROP_VIG_IGC);
  3121. }
  3122. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3123. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3124. "SDE_DGM_1D_LUT_IGC_V",
  3125. psde->pipe_sblk->igc_blk[0].version >> 16);
  3126. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3127. PLANE_PROP_DMA_IGC);
  3128. }
  3129. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3130. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3131. "SDE_DGM_1D_LUT_GC_V",
  3132. psde->pipe_sblk->gc_blk[0].version >> 16);
  3133. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3134. PLANE_PROP_DMA_GC);
  3135. }
  3136. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3137. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3138. "SDE_SSPP_FP16_IGC_V",
  3139. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3140. msm_property_install_range(&psde->property_info, feature_name,
  3141. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3142. }
  3143. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3144. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3145. "SDE_SSPP_FP16_GC_V",
  3146. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3147. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3148. PLANE_PROP_FP16_GC);
  3149. }
  3150. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3151. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3152. "SDE_SSPP_FP16_CSC_V",
  3153. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3154. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3155. PLANE_PROP_FP16_CSC);
  3156. }
  3157. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3158. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3159. "SDE_SSPP_FP16_UNMULT_V",
  3160. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3161. msm_property_install_range(&psde->property_info, feature_name,
  3162. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3163. }
  3164. }
  3165. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3166. u32 master_plane_id, struct sde_kms_info *info,
  3167. struct sde_mdss_cfg *catalog)
  3168. {
  3169. bool is_master = !psde->is_virtual;
  3170. const struct sde_format_extended *format_list;
  3171. u32 index;
  3172. int pipe_id;
  3173. if (is_master) {
  3174. format_list = psde->pipe_sblk->format_list;
  3175. } else {
  3176. format_list = psde->pipe_sblk->virt_format_list;
  3177. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3178. master_plane_id);
  3179. }
  3180. if (format_list) {
  3181. sde_kms_info_start(info, "pixel_formats");
  3182. while (format_list->fourcc_format) {
  3183. sde_kms_info_append_format(info,
  3184. format_list->fourcc_format,
  3185. format_list->modifier);
  3186. ++format_list;
  3187. }
  3188. sde_kms_info_stop(info);
  3189. }
  3190. if (psde->pipe_hw && catalog->qseed_hw_rev)
  3191. sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
  3192. sde_kms_info_add_keyint(info, "max_linewidth",
  3193. psde->pipe_sblk->maxlinewidth);
  3194. sde_kms_info_add_keyint(info, "max_upscale",
  3195. psde->pipe_sblk->maxupscale);
  3196. sde_kms_info_add_keyint(info, "max_downscale",
  3197. psde->pipe_sblk->maxdwnscale);
  3198. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3199. psde->pipe_sblk->maxhdeciexp);
  3200. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3201. psde->pipe_sblk->maxvdeciexp);
  3202. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3203. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3204. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3205. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3206. if (SDE_SSPP_VALID_VIG(psde->pipe))
  3207. pipe_id = psde->pipe - SSPP_VIG0;
  3208. else if (SDE_SSPP_VALID_DMA(psde->pipe))
  3209. pipe_id = psde->pipe - SSPP_DMA0;
  3210. else
  3211. pipe_id = -1;
  3212. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3213. index = (master_plane_id == 0) ? 0 : 1;
  3214. if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
  3215. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3216. sde_kms_info_add_keyint(info, "demura_block", index);
  3217. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3218. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3219. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3220. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3221. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3222. const struct sde_format_extended *inline_rot_fmt_list;
  3223. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3224. catalog->true_inline_rot_rev);
  3225. sde_kms_info_add_keyint(info,
  3226. "true_inline_dwnscale_rt",
  3227. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3228. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3229. sde_kms_info_add_keyint(info,
  3230. "true_inline_dwnscale_rt_numerator",
  3231. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3232. sde_kms_info_add_keyint(info,
  3233. "true_inline_dwnscale_rt_denominator",
  3234. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3235. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3236. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3237. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3238. psde->pipe_sblk->in_rot_maxheight);
  3239. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3240. if (inline_rot_fmt_list) {
  3241. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3242. while (inline_rot_fmt_list->fourcc_format) {
  3243. sde_kms_info_append_format(info,
  3244. inline_rot_fmt_list->fourcc_format,
  3245. inline_rot_fmt_list->modifier);
  3246. ++inline_rot_fmt_list;
  3247. }
  3248. sde_kms_info_stop(info);
  3249. }
  3250. }
  3251. }
  3252. /* helper to install properties which are common to planes and crtcs */
  3253. static void _sde_plane_install_properties(struct drm_plane *plane,
  3254. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3255. {
  3256. static const struct drm_prop_enum_list e_blend_op[] = {
  3257. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3258. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3259. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3260. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3261. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3262. };
  3263. static const struct drm_prop_enum_list e_src_config[] = {
  3264. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3265. };
  3266. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3267. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3268. {SDE_DRM_FB_SEC, "sec"},
  3269. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3270. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3271. };
  3272. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3273. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3274. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3275. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3276. };
  3277. struct sde_kms_info *info;
  3278. struct sde_plane *psde = to_sde_plane(plane);
  3279. bool is_master;
  3280. int zpos_max = 255;
  3281. int zpos_def = 0;
  3282. if (!plane || !psde) {
  3283. SDE_ERROR("invalid plane\n");
  3284. return;
  3285. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3286. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3287. !psde->pipe_hw, !psde->pipe_sblk);
  3288. return;
  3289. } else if (!catalog) {
  3290. SDE_ERROR("invalid catalog\n");
  3291. return;
  3292. }
  3293. psde->catalog = catalog;
  3294. is_master = !psde->is_virtual;
  3295. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3296. if (!info) {
  3297. SDE_ERROR("failed to allocate info memory\n");
  3298. return;
  3299. }
  3300. if (sde_is_custom_client()) {
  3301. if (catalog->mixer_count &&
  3302. catalog->mixer[0].sblk->maxblendstages) {
  3303. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3304. if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
  3305. (zpos_max > SDE_STAGE_MAX - 1))
  3306. zpos_max = SDE_STAGE_MAX - 1;
  3307. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3308. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3309. }
  3310. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3311. /* reserve zpos == 0 for primary planes */
  3312. zpos_def = drm_plane_index(plane) + 1;
  3313. }
  3314. msm_property_install_range(&psde->property_info, "zpos",
  3315. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3316. msm_property_install_range(&psde->property_info, "alpha",
  3317. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3318. /* linux default file descriptor range on each process */
  3319. msm_property_install_range(&psde->property_info, "input_fence",
  3320. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3321. if (is_master)
  3322. _sde_plane_install_master_only_properties(psde);
  3323. else
  3324. msm_property_install_enum(&psde->property_info,
  3325. "multirect_mode", 0x0, 0, e_multirect_mode,
  3326. ARRAY_SIZE(e_multirect_mode), 0,
  3327. PLANE_PROP_MULTIRECT_MODE);
  3328. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3329. msm_property_install_volatile_range(&psde->property_info,
  3330. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3331. sde_plane_rot_install_properties(plane, catalog);
  3332. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3333. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3334. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3335. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3336. PLANE_PROP_SRC_CONFIG);
  3337. if (psde->pipe_hw->ops.setup_solidfill)
  3338. msm_property_install_range(&psde->property_info, "color_fill",
  3339. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3340. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3341. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3342. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3343. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3344. msm_property_install_blob(&psde->property_info, "capabilities",
  3345. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3346. sde_kms_info_reset(info);
  3347. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3348. catalog);
  3349. _sde_plane_install_colorproc_properties(psde, info);
  3350. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3351. info->data, SDE_KMS_INFO_DATALEN(info),
  3352. PLANE_PROP_INFO);
  3353. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3354. 0x0, 0, e_fb_translation_mode,
  3355. ARRAY_SIZE(e_fb_translation_mode), 0,
  3356. PLANE_PROP_FB_TRANSLATION_MODE);
  3357. if (psde->pipe_hw->ops.set_ubwc_stats_roi)
  3358. msm_property_install_range(&psde->property_info, "ubwc_stats_roi",
  3359. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_UBWC_STATS_ROI);
  3360. kfree(info);
  3361. }
  3362. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3363. void __user *usr_ptr)
  3364. {
  3365. struct sde_drm_csc_v1 csc_v1;
  3366. int i;
  3367. if (!psde) {
  3368. SDE_ERROR("invalid plane\n");
  3369. return;
  3370. }
  3371. psde->csc_usr_ptr = NULL;
  3372. if (!usr_ptr) {
  3373. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3374. return;
  3375. }
  3376. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3377. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3378. return;
  3379. }
  3380. /* populate from user space */
  3381. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3382. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3383. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3384. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3385. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3386. }
  3387. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3388. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3389. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3390. }
  3391. psde->csc_usr_ptr = &psde->csc_cfg;
  3392. }
  3393. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3394. struct sde_plane_state *pstate, void __user *usr)
  3395. {
  3396. struct sde_drm_scaler_v1 scale_v1;
  3397. struct sde_hw_pixel_ext *pe;
  3398. int i;
  3399. if (!psde || !pstate) {
  3400. SDE_ERROR("invalid argument(s)\n");
  3401. return;
  3402. }
  3403. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3404. if (!usr) {
  3405. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3406. return;
  3407. }
  3408. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3409. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3410. return;
  3411. }
  3412. /* force property to be dirty, even if the pointer didn't change */
  3413. msm_property_set_dirty(&psde->property_info,
  3414. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3415. /* populate from user space */
  3416. pe = &pstate->pixel_ext;
  3417. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3418. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3419. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3420. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3421. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3422. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3423. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3424. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3425. }
  3426. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3427. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3428. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3429. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3430. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3431. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3432. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3433. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3434. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3435. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3436. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3437. }
  3438. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3439. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3440. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3441. }
  3442. static void _sde_plane_clear_predownscale_settings(
  3443. struct sde_plane_state *pstate)
  3444. {
  3445. pstate->pre_down.pre_downscale_x_0 = 0;
  3446. pstate->pre_down.pre_downscale_x_1 = 0;
  3447. pstate->pre_down.pre_downscale_y_0 = 0;
  3448. pstate->pre_down.pre_downscale_y_1 = 0;
  3449. }
  3450. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3451. struct sde_plane_state *pstate, void __user *usr)
  3452. {
  3453. struct sde_drm_scaler_v2 scale_v2;
  3454. struct sde_hw_pixel_ext *pe;
  3455. int i;
  3456. struct sde_hw_scaler3_cfg *cfg;
  3457. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3458. if (!psde || !pstate) {
  3459. SDE_ERROR("invalid argument(s)\n");
  3460. return;
  3461. }
  3462. cfg = &pstate->scaler3_cfg;
  3463. pd_cfg = &pstate->pre_down;
  3464. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3465. if (!usr) {
  3466. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3467. cfg->enable = 0;
  3468. _sde_plane_clear_predownscale_settings(pstate);
  3469. goto end;
  3470. }
  3471. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3472. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3473. return;
  3474. }
  3475. /* detach/ignore user data if 'disabled' */
  3476. if (!scale_v2.enable) {
  3477. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3478. cfg->enable = 0;
  3479. _sde_plane_clear_predownscale_settings(pstate);
  3480. goto end;
  3481. }
  3482. /* populate from user space */
  3483. sde_set_scaler_v2(cfg, &scale_v2);
  3484. if (_sde_plane_has_pre_downscale(psde)) {
  3485. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3486. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3487. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3488. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3489. }
  3490. pe = &pstate->pixel_ext;
  3491. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3492. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3493. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3494. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3495. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3496. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3497. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3498. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3499. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3500. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3501. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3502. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3503. }
  3504. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3505. end:
  3506. /* force property to be dirty, even if the pointer didn't change */
  3507. msm_property_set_dirty(&psde->property_info,
  3508. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3509. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3510. cfg->src_width[0], cfg->src_height[0],
  3511. cfg->dst_width, cfg->dst_height);
  3512. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3513. }
  3514. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3515. struct sde_plane_state *pstate, void __user *usr_ptr)
  3516. {
  3517. struct drm_clip_rect excl_rect_v1;
  3518. if (!psde || !pstate) {
  3519. SDE_ERROR("invalid argument(s)\n");
  3520. return;
  3521. }
  3522. if (!usr_ptr) {
  3523. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3524. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3525. return;
  3526. }
  3527. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3528. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3529. return;
  3530. }
  3531. /* populate from user space */
  3532. pstate->excl_rect.x = excl_rect_v1.x1;
  3533. pstate->excl_rect.y = excl_rect_v1.y1;
  3534. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3535. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3536. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3537. pstate->excl_rect.x, pstate->excl_rect.y,
  3538. pstate->excl_rect.w, pstate->excl_rect.h);
  3539. }
  3540. static void _sde_plane_set_ubwc_stats_roi(struct sde_plane *psde,
  3541. struct sde_plane_state *pstate, uint64_t roi)
  3542. {
  3543. uint16_t y0, y1;
  3544. if (!psde || !pstate) {
  3545. SDE_ERROR("invalid argument(s)\n");
  3546. return;
  3547. }
  3548. y0 = roi & 0xFFFF;
  3549. y1 = (roi >> 0x10) & 0xFFFF;
  3550. if (y0 > psde->pipe_cfg.src_rect.h || y1 > psde->pipe_cfg.src_rect.h) {
  3551. SDE_ERROR_PLANE(psde, "invalid ubwc roi y0 0x%x, y1 0x%x, src height 0x%x",
  3552. y0, y1, psde->pipe_cfg.src_rect.h);
  3553. y0 = 0;
  3554. y1 = 0;
  3555. }
  3556. pstate->ubwc_stats_roi.y_coord0 = y0;
  3557. pstate->ubwc_stats_roi.y_coord1 = y1;
  3558. }
  3559. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3560. struct drm_plane_state *state, struct drm_property *property,
  3561. uint64_t val)
  3562. {
  3563. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3564. struct sde_plane_state *pstate;
  3565. int idx, ret = -EINVAL;
  3566. SDE_DEBUG_PLANE(psde, "\n");
  3567. if (!plane) {
  3568. SDE_ERROR("invalid plane\n");
  3569. } else if (!state) {
  3570. SDE_ERROR_PLANE(psde, "invalid state\n");
  3571. } else {
  3572. pstate = to_sde_plane_state(state);
  3573. ret = msm_property_atomic_set(&psde->property_info,
  3574. &pstate->property_state, property, val);
  3575. if (!ret) {
  3576. idx = msm_property_index(&psde->property_info,
  3577. property);
  3578. switch (idx) {
  3579. case PLANE_PROP_INPUT_FENCE:
  3580. _sde_plane_set_input_fence(psde, pstate, val);
  3581. break;
  3582. case PLANE_PROP_CSC_V1:
  3583. case PLANE_PROP_CSC_DMA_V1:
  3584. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3585. break;
  3586. case PLANE_PROP_SCALER_V1:
  3587. _sde_plane_set_scaler_v1(psde, pstate,
  3588. (void *)(uintptr_t)val);
  3589. break;
  3590. case PLANE_PROP_SCALER_V2:
  3591. _sde_plane_set_scaler_v2(psde, pstate,
  3592. (void *)(uintptr_t)val);
  3593. break;
  3594. case PLANE_PROP_EXCL_RECT_V1:
  3595. _sde_plane_set_excl_rect_v1(psde, pstate,
  3596. (void *)(uintptr_t)val);
  3597. break;
  3598. case PLANE_PROP_UBWC_STATS_ROI:
  3599. _sde_plane_set_ubwc_stats_roi(psde, pstate, val);
  3600. break;
  3601. default:
  3602. /* nothing to do */
  3603. break;
  3604. }
  3605. }
  3606. }
  3607. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3608. property->name, property->base.id, val, ret);
  3609. return ret;
  3610. }
  3611. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3612. const struct drm_plane_state *state,
  3613. struct drm_property *property, uint64_t *val)
  3614. {
  3615. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3616. struct sde_plane_state *pstate;
  3617. int ret = -EINVAL;
  3618. if (!plane) {
  3619. SDE_ERROR("invalid plane\n");
  3620. } else if (!state) {
  3621. SDE_ERROR("invalid state\n");
  3622. } else {
  3623. SDE_DEBUG_PLANE(psde, "\n");
  3624. pstate = to_sde_plane_state(state);
  3625. ret = msm_property_atomic_get(&psde->property_info,
  3626. &pstate->property_state, property, val);
  3627. }
  3628. return ret;
  3629. }
  3630. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3631. struct drm_plane_state *plane_state)
  3632. {
  3633. struct sde_plane *psde;
  3634. struct sde_plane_state *pstate;
  3635. struct drm_property *drm_prop;
  3636. enum msm_mdp_plane_property prop_idx;
  3637. if (!plane || !plane_state) {
  3638. SDE_ERROR("invalid params\n");
  3639. return -EINVAL;
  3640. }
  3641. psde = to_sde_plane(plane);
  3642. pstate = to_sde_plane_state(plane_state);
  3643. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3644. uint64_t val = pstate->property_values[prop_idx].value;
  3645. uint64_t def;
  3646. int ret;
  3647. drm_prop = msm_property_index_to_drm_property(
  3648. &psde->property_info, prop_idx);
  3649. if (!drm_prop) {
  3650. /* not all props will be installed, based on caps */
  3651. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3652. prop_idx);
  3653. continue;
  3654. }
  3655. def = msm_property_get_default(&psde->property_info, prop_idx);
  3656. if (val == def)
  3657. continue;
  3658. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3659. drm_prop->name, prop_idx, val, def);
  3660. ret = sde_plane_atomic_set_property(plane, plane_state,
  3661. drm_prop, def);
  3662. if (ret) {
  3663. SDE_ERROR_PLANE(psde,
  3664. "set property failed, idx %d ret %d\n",
  3665. prop_idx, ret);
  3666. continue;
  3667. }
  3668. }
  3669. return 0;
  3670. }
  3671. static void sde_plane_destroy(struct drm_plane *plane)
  3672. {
  3673. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3674. SDE_DEBUG_PLANE(psde, "\n");
  3675. if (psde) {
  3676. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3677. if (psde->blob_info)
  3678. drm_property_blob_put(psde->blob_info);
  3679. msm_property_destroy(&psde->property_info);
  3680. mutex_destroy(&psde->lock);
  3681. /* this will destroy the states as well */
  3682. drm_plane_cleanup(plane);
  3683. if (psde->pipe_hw)
  3684. sde_hw_sspp_destroy(psde->pipe_hw);
  3685. kfree(psde);
  3686. }
  3687. }
  3688. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3689. {
  3690. struct sde_plane_state *pstate;
  3691. if (!state) {
  3692. SDE_ERROR("invalid arg state %d\n", !state);
  3693. return;
  3694. }
  3695. pstate = to_sde_plane_state(state);
  3696. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3697. SDE_DRM_FB_SEC) {
  3698. /* remove ref count for frame buffers */
  3699. if (state->fb) {
  3700. drm_framebuffer_put(state->fb);
  3701. state->fb = NULL;
  3702. }
  3703. }
  3704. }
  3705. static void sde_plane_destroy_state(struct drm_plane *plane,
  3706. struct drm_plane_state *state)
  3707. {
  3708. struct sde_plane *psde;
  3709. struct sde_plane_state *pstate;
  3710. if (!plane || !state) {
  3711. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3712. !plane, !state);
  3713. return;
  3714. }
  3715. psde = to_sde_plane(plane);
  3716. pstate = to_sde_plane_state(state);
  3717. SDE_DEBUG_PLANE(psde, "\n");
  3718. /* remove ref count for frame buffers */
  3719. if (state->fb)
  3720. drm_framebuffer_put(state->fb);
  3721. /* remove ref count for fence */
  3722. if (pstate->input_fence)
  3723. sde_sync_put(pstate->input_fence);
  3724. pstate->input_fence = 0;
  3725. /* destroy value helper */
  3726. msm_property_destroy_state(&psde->property_info, pstate,
  3727. &pstate->property_state);
  3728. }
  3729. static struct drm_plane_state *
  3730. sde_plane_duplicate_state(struct drm_plane *plane)
  3731. {
  3732. struct sde_plane *psde;
  3733. struct sde_plane_state *pstate;
  3734. struct sde_plane_state *old_state;
  3735. struct drm_property *drm_prop;
  3736. uint64_t input_fence_default;
  3737. if (!plane) {
  3738. SDE_ERROR("invalid plane\n");
  3739. return NULL;
  3740. } else if (!plane->state) {
  3741. SDE_ERROR("invalid plane state\n");
  3742. return NULL;
  3743. }
  3744. old_state = to_sde_plane_state(plane->state);
  3745. psde = to_sde_plane(plane);
  3746. if (old_state->cont_splash_populated) {
  3747. plane->state->crtc = NULL;
  3748. old_state->cont_splash_populated = false;
  3749. }
  3750. pstate = msm_property_alloc_state(&psde->property_info);
  3751. if (!pstate) {
  3752. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3753. return NULL;
  3754. }
  3755. SDE_DEBUG_PLANE(psde, "\n");
  3756. /* duplicate value helper */
  3757. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3758. &pstate->property_state, pstate->property_values);
  3759. /* clear out any input fence */
  3760. pstate->input_fence = 0;
  3761. input_fence_default = msm_property_get_default(
  3762. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3763. drm_prop = msm_property_index_to_drm_property(
  3764. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3765. if (msm_property_atomic_set(&psde->property_info,
  3766. &pstate->property_state, drm_prop,
  3767. input_fence_default))
  3768. SDE_DEBUG_PLANE(psde,
  3769. "error clearing duplicated input fence\n");
  3770. pstate->dirty = 0x0;
  3771. pstate->pending = false;
  3772. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3773. /* reset layout offset */
  3774. if (pstate->layout_offset) {
  3775. if (pstate->layout_offset > 0)
  3776. pstate->base.crtc_x += pstate->layout_offset;
  3777. pstate->layout = SDE_LAYOUT_NONE;
  3778. pstate->layout_offset = 0;
  3779. }
  3780. return &pstate->base;
  3781. }
  3782. static void sde_plane_reset(struct drm_plane *plane)
  3783. {
  3784. struct sde_plane *psde;
  3785. struct sde_plane_state *pstate;
  3786. if (!plane) {
  3787. SDE_ERROR("invalid plane\n");
  3788. return;
  3789. }
  3790. psde = to_sde_plane(plane);
  3791. SDE_DEBUG_PLANE(psde, "\n");
  3792. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3793. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3794. return;
  3795. }
  3796. /* remove previous state, if present */
  3797. if (plane->state) {
  3798. sde_plane_destroy_state(plane, plane->state);
  3799. plane->state = 0;
  3800. }
  3801. pstate = msm_property_alloc_state(&psde->property_info);
  3802. if (!pstate) {
  3803. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3804. return;
  3805. }
  3806. /* reset value helper */
  3807. msm_property_reset_state(&psde->property_info, pstate,
  3808. &pstate->property_state,
  3809. pstate->property_values);
  3810. pstate->base.plane = plane;
  3811. plane->state = &pstate->base;
  3812. }
  3813. void sde_plane_get_frame_data(struct drm_plane *plane,
  3814. struct sde_drm_plane_frame_data *data)
  3815. {
  3816. struct sde_plane *psde;
  3817. struct sde_plane_state *pstate;
  3818. struct sde_drm_ubwc_stats_data *ubwc_stats;
  3819. if (!plane) {
  3820. SDE_ERROR("invalid plane\n");
  3821. return;
  3822. }
  3823. psde = to_sde_plane(plane);
  3824. pstate = to_sde_plane_state(plane->state);
  3825. ubwc_stats = &data->ubwc_stats;
  3826. data->plane_id = DRMID(plane);
  3827. if (psde->pipe_hw->ops.get_ubwc_stats_data) {
  3828. memcpy(&ubwc_stats->roi, &pstate->ubwc_stats_roi,
  3829. sizeof(struct sde_drm_ubwc_stats_roi));
  3830. psde->pipe_hw->ops.get_ubwc_stats_data(psde->pipe_hw,
  3831. pstate->multirect_index, ubwc_stats);
  3832. }
  3833. if (psde->pipe_hw->ops.get_ubwc_error)
  3834. ubwc_stats->error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  3835. pstate->multirect_index);
  3836. if (psde->pipe_hw->ops.clear_ubwc_error && ubwc_stats->error)
  3837. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  3838. if (psde->pipe_hw->ops.get_meta_error)
  3839. ubwc_stats->meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  3840. pstate->multirect_index);
  3841. if (psde->pipe_hw->ops.clear_meta_error && ubwc_stats->meta_error)
  3842. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  3843. if (ubwc_stats->error || ubwc_stats->meta_error) {
  3844. SDE_EVT32(DRMID(plane), ubwc_stats->error, ubwc_stats->meta_error,
  3845. SDE_EVTLOG_ERROR);
  3846. SDE_DEBUG_PLANE(psde, "plane%d ubwc_error %d meta_error %d\n",
  3847. ubwc_stats->error, ubwc_stats->meta_error);
  3848. }
  3849. }
  3850. #if IS_ENABLED(CONFIG_DEBUG_FS)
  3851. static ssize_t _sde_plane_danger_read(struct file *file,
  3852. char __user *buff, size_t count, loff_t *ppos)
  3853. {
  3854. struct sde_kms *kms = file->private_data;
  3855. struct sde_mdss_cfg *cfg = kms->catalog;
  3856. int len = 0;
  3857. char buf[40] = {'\0'};
  3858. if (!cfg)
  3859. return -ENODEV;
  3860. if (*ppos)
  3861. return 0; /* the end */
  3862. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3863. if (len < 0 || len >= sizeof(buf))
  3864. return 0;
  3865. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3866. return -EFAULT;
  3867. *ppos += len; /* increase offset */
  3868. return len;
  3869. }
  3870. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3871. {
  3872. struct drm_plane *plane;
  3873. drm_for_each_plane(plane, kms->dev) {
  3874. if (plane->fb && plane->state) {
  3875. sde_plane_danger_signal_ctrl(plane, enable);
  3876. SDE_DEBUG("plane:%d img:%dx%d ",
  3877. plane->base.id, plane->fb->width,
  3878. plane->fb->height);
  3879. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3880. plane->state->src_x >> 16,
  3881. plane->state->src_y >> 16,
  3882. plane->state->src_w >> 16,
  3883. plane->state->src_h >> 16,
  3884. plane->state->crtc_x, plane->state->crtc_y,
  3885. plane->state->crtc_w, plane->state->crtc_h);
  3886. } else {
  3887. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3888. }
  3889. }
  3890. }
  3891. static ssize_t _sde_plane_danger_write(struct file *file,
  3892. const char __user *user_buf, size_t count, loff_t *ppos)
  3893. {
  3894. struct sde_kms *kms = file->private_data;
  3895. struct sde_mdss_cfg *cfg = kms->catalog;
  3896. int disable_panic;
  3897. char buf[10];
  3898. if (!cfg)
  3899. return -EFAULT;
  3900. if (count >= sizeof(buf))
  3901. return -EFAULT;
  3902. if (copy_from_user(buf, user_buf, count))
  3903. return -EFAULT;
  3904. buf[count] = 0; /* end of string */
  3905. if (kstrtoint(buf, 0, &disable_panic))
  3906. return -EFAULT;
  3907. if (disable_panic) {
  3908. /* Disable panic signal for all active pipes */
  3909. SDE_DEBUG("Disabling danger:\n");
  3910. _sde_plane_set_danger_state(kms, false);
  3911. kms->has_danger_ctrl = false;
  3912. } else {
  3913. /* Enable panic signal for all active pipes */
  3914. SDE_DEBUG("Enabling danger:\n");
  3915. kms->has_danger_ctrl = true;
  3916. _sde_plane_set_danger_state(kms, true);
  3917. }
  3918. return count;
  3919. }
  3920. static const struct file_operations sde_plane_danger_enable = {
  3921. .open = simple_open,
  3922. .read = _sde_plane_danger_read,
  3923. .write = _sde_plane_danger_write,
  3924. };
  3925. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3926. {
  3927. struct sde_plane *psde;
  3928. struct sde_kms *kms;
  3929. struct msm_drm_private *priv;
  3930. const struct sde_sspp_sub_blks *sblk = 0;
  3931. const struct sde_sspp_cfg *cfg = 0;
  3932. if (!plane || !plane->dev) {
  3933. SDE_ERROR("invalid arguments\n");
  3934. return -EINVAL;
  3935. }
  3936. priv = plane->dev->dev_private;
  3937. if (!priv || !priv->kms) {
  3938. SDE_ERROR("invalid KMS reference\n");
  3939. return -EINVAL;
  3940. }
  3941. kms = to_sde_kms(priv->kms);
  3942. psde = to_sde_plane(plane);
  3943. if (psde && psde->pipe_hw)
  3944. cfg = psde->pipe_hw->cap;
  3945. if (cfg)
  3946. sblk = cfg->sblk;
  3947. if (!sblk)
  3948. return 0;
  3949. /* create overall sub-directory for the pipe */
  3950. psde->debugfs_root =
  3951. debugfs_create_dir(psde->pipe_name,
  3952. plane->dev->primary->debugfs_root);
  3953. if (!psde->debugfs_root)
  3954. return -ENOMEM;
  3955. /* don't error check these */
  3956. debugfs_create_x64("features", 0400,
  3957. psde->debugfs_root, &psde->features);
  3958. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3959. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3960. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3961. debugfs_create_bool("default_scaling",
  3962. 0600,
  3963. psde->debugfs_root,
  3964. &psde->debugfs_default_scale);
  3965. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3966. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3967. 0600,
  3968. psde->debugfs_root,
  3969. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3970. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3971. 0600,
  3972. psde->debugfs_root,
  3973. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3974. debugfs_create_u32("in_rot_max_downscale_nrt",
  3975. 0600,
  3976. psde->debugfs_root,
  3977. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3978. debugfs_create_u32("in_rot_max_height",
  3979. 0600,
  3980. psde->debugfs_root,
  3981. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3982. }
  3983. debugfs_create_u32("xin_id",
  3984. 0400,
  3985. psde->debugfs_root,
  3986. (u32 *) &cfg->xin_id);
  3987. debugfs_create_x32("creq_vblank",
  3988. 0600,
  3989. psde->debugfs_root,
  3990. (u32 *) &sblk->creq_vblank);
  3991. debugfs_create_x32("danger_vblank",
  3992. 0600,
  3993. psde->debugfs_root,
  3994. (u32 *) &sblk->danger_vblank);
  3995. debugfs_create_file("disable_danger",
  3996. 0600,
  3997. psde->debugfs_root,
  3998. kms, &sde_plane_danger_enable);
  3999. return 0;
  4000. }
  4001. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4002. {
  4003. struct sde_plane *psde;
  4004. if (!plane)
  4005. return;
  4006. psde = to_sde_plane(plane);
  4007. debugfs_remove_recursive(psde->debugfs_root);
  4008. }
  4009. #else
  4010. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4011. {
  4012. return 0;
  4013. }
  4014. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4015. {
  4016. }
  4017. #endif /* CONFIG_DEBUG_FS */
  4018. static int sde_plane_late_register(struct drm_plane *plane)
  4019. {
  4020. return _sde_plane_init_debugfs(plane);
  4021. }
  4022. static void sde_plane_early_unregister(struct drm_plane *plane)
  4023. {
  4024. _sde_plane_destroy_debugfs(plane);
  4025. }
  4026. static const struct drm_plane_funcs sde_plane_funcs = {
  4027. .update_plane = drm_atomic_helper_update_plane,
  4028. .disable_plane = drm_atomic_helper_disable_plane,
  4029. .destroy = sde_plane_destroy,
  4030. .atomic_set_property = sde_plane_atomic_set_property,
  4031. .atomic_get_property = sde_plane_atomic_get_property,
  4032. .reset = sde_plane_reset,
  4033. .atomic_duplicate_state = sde_plane_duplicate_state,
  4034. .atomic_destroy_state = sde_plane_destroy_state,
  4035. .late_register = sde_plane_late_register,
  4036. .early_unregister = sde_plane_early_unregister,
  4037. };
  4038. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  4039. .prepare_fb = sde_plane_prepare_fb,
  4040. .cleanup_fb = sde_plane_cleanup_fb,
  4041. .atomic_check = sde_plane_atomic_check,
  4042. .atomic_update = sde_plane_atomic_update,
  4043. };
  4044. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  4045. {
  4046. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  4047. }
  4048. bool is_sde_plane_virtual(struct drm_plane *plane)
  4049. {
  4050. return plane ? to_sde_plane(plane)->is_virtual : false;
  4051. }
  4052. /* initialize plane */
  4053. struct drm_plane *sde_plane_init(struct drm_device *dev,
  4054. uint32_t pipe, bool primary_plane,
  4055. unsigned long possible_crtcs, u32 master_plane_id)
  4056. {
  4057. struct drm_plane *plane = NULL, *master_plane = NULL;
  4058. const struct sde_format_extended *format_list;
  4059. struct sde_plane *psde;
  4060. struct msm_drm_private *priv;
  4061. struct sde_kms *kms;
  4062. enum drm_plane_type type;
  4063. struct sde_vbif_clk_client clk_client;
  4064. int ret = -EINVAL;
  4065. if (!dev) {
  4066. SDE_ERROR("[%u]device is NULL\n", pipe);
  4067. goto exit;
  4068. }
  4069. priv = dev->dev_private;
  4070. if (!priv) {
  4071. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4072. goto exit;
  4073. }
  4074. if (!priv->kms) {
  4075. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4076. goto exit;
  4077. }
  4078. kms = to_sde_kms(priv->kms);
  4079. if (!kms->catalog) {
  4080. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4081. goto exit;
  4082. }
  4083. /* create and zero local structure */
  4084. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4085. if (!psde) {
  4086. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4087. ret = -ENOMEM;
  4088. goto exit;
  4089. }
  4090. /* cache local stuff for later */
  4091. plane = &psde->base;
  4092. psde->pipe = pipe;
  4093. psde->is_virtual = (master_plane_id != 0);
  4094. INIT_LIST_HEAD(&psde->mplane_list);
  4095. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4096. if (master_plane) {
  4097. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4098. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4099. }
  4100. /* initialize underlying h/w driver */
  4101. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog, psde->is_virtual,
  4102. &clk_client);
  4103. if (IS_ERR(psde->pipe_hw)) {
  4104. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4105. ret = PTR_ERR(psde->pipe_hw);
  4106. goto clean_plane;
  4107. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4108. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4109. goto clean_sspp;
  4110. }
  4111. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, kms->catalog->features)) {
  4112. ret = sde_vbif_clk_register(kms, &clk_client);
  4113. if (ret) {
  4114. SDE_ERROR("failed to register vbif client %d\n",
  4115. clk_client.clk_ctrl);
  4116. goto clean_sspp;
  4117. }
  4118. }
  4119. /* cache features mask for later */
  4120. psde->features = psde->pipe_hw->cap->features_ext;
  4121. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4122. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4123. if (!psde->pipe_sblk) {
  4124. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4125. goto clean_sspp;
  4126. }
  4127. if (psde->is_virtual)
  4128. format_list = psde->pipe_sblk->virt_format_list;
  4129. else
  4130. format_list = psde->pipe_sblk->format_list;
  4131. psde->nformats = sde_populate_formats(format_list,
  4132. psde->formats,
  4133. 0,
  4134. ARRAY_SIZE(psde->formats));
  4135. if (!psde->nformats) {
  4136. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4137. goto clean_sspp;
  4138. }
  4139. if (primary_plane)
  4140. type = DRM_PLANE_TYPE_PRIMARY;
  4141. else
  4142. type = DRM_PLANE_TYPE_OVERLAY;
  4143. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4144. psde->formats, psde->nformats,
  4145. NULL, type, NULL);
  4146. if (ret)
  4147. goto clean_sspp;
  4148. /* Populate static array of plane property flags */
  4149. _sde_plane_map_prop_to_dirty_bits();
  4150. /* success! finalize initialization */
  4151. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4152. msm_property_init(&psde->property_info, &plane->base, dev,
  4153. priv->plane_property, psde->property_data,
  4154. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4155. sizeof(struct sde_plane_state));
  4156. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4157. /* save user friendly pipe name for later */
  4158. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4159. mutex_init(&psde->lock);
  4160. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4161. pipe, plane->base.id, master_plane_id);
  4162. return plane;
  4163. clean_sspp:
  4164. if (psde && psde->pipe_hw)
  4165. sde_hw_sspp_destroy(psde->pipe_hw);
  4166. clean_plane:
  4167. kfree(psde);
  4168. exit:
  4169. return ERR_PTR(ret);
  4170. }
  4171. void sde_plane_add_data_to_minidump_va(struct drm_plane *plane)
  4172. {
  4173. struct sde_plane *sde_plane;
  4174. struct sde_plane_state *pstate;
  4175. sde_plane = to_sde_plane(plane);
  4176. pstate = to_sde_plane_state(plane->state);
  4177. sde_mini_dump_add_va_region("sde_plane", sizeof(*sde_plane), sde_plane);
  4178. sde_mini_dump_add_va_region("plane_state", sizeof(*pstate), pstate);
  4179. }