sde_kms.c 89 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/dma-buf.h>
  25. #include <linux/memblock.h>
  26. #include <drm/drm_atomic_uapi.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "msm_drv.h"
  29. #include "msm_mmu.h"
  30. #include "msm_gem.h"
  31. #include "dsi_display.h"
  32. #include "dsi_drm.h"
  33. #include "sde_wb.h"
  34. #include "dp_display.h"
  35. #include "dp_drm.h"
  36. #include "dp_mst_drm.h"
  37. #include "sde_kms.h"
  38. #include "sde_core_irq.h"
  39. #include "sde_formats.h"
  40. #include "sde_hw_vbif.h"
  41. #include "sde_vbif.h"
  42. #include "sde_encoder.h"
  43. #include "sde_plane.h"
  44. #include "sde_crtc.h"
  45. #include "sde_reg_dma.h"
  46. #include "sde_connector.h"
  47. #include <linux/qcom_scm.h>
  48. #include "soc/qcom/secure_buffer.h"
  49. #include <linux/qtee_shmbridge.h>
  50. #define CREATE_TRACE_POINTS
  51. #include "sde_trace.h"
  52. /* defines for secure channel call */
  53. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  54. #define MDP_DEVICE_ID 0x1A
  55. static const char * const iommu_ports[] = {
  56. "mdp_0",
  57. };
  58. /**
  59. * Controls size of event log buffer. Specified as a power of 2.
  60. */
  61. #define SDE_EVTLOG_SIZE 1024
  62. /*
  63. * To enable overall DRM driver logging
  64. * # echo 0x2 > /sys/module/drm/parameters/debug
  65. *
  66. * To enable DRM driver h/w logging
  67. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  68. *
  69. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  70. */
  71. #define SDE_DEBUGFS_DIR "msm_sde"
  72. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  73. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  74. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  75. /**
  76. * sdecustom - enable certain driver customizations for sde clients
  77. * Enabling this modifies the standard DRM behavior slightly and assumes
  78. * that the clients have specific knowledge about the modifications that
  79. * are involved, so don't enable this unless you know what you're doing.
  80. *
  81. * Parts of the driver that are affected by this setting may be located by
  82. * searching for invocations of the 'sde_is_custom_client()' function.
  83. *
  84. * This is disabled by default.
  85. */
  86. static bool sdecustom = true;
  87. module_param(sdecustom, bool, 0400);
  88. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  89. static int sde_kms_hw_init(struct msm_kms *kms);
  90. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  91. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  92. static int _sde_kms_register_events(struct msm_kms *kms,
  93. struct drm_mode_object *obj, u32 event, bool en);
  94. bool sde_is_custom_client(void)
  95. {
  96. return sdecustom;
  97. }
  98. #ifdef CONFIG_DEBUG_FS
  99. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  100. {
  101. struct msm_drm_private *priv;
  102. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  103. return NULL;
  104. priv = sde_kms->dev->dev_private;
  105. return priv->debug_root;
  106. }
  107. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  108. {
  109. void *p;
  110. int rc;
  111. void *debugfs_root;
  112. p = sde_hw_util_get_log_mask_ptr();
  113. if (!sde_kms || !p)
  114. return -EINVAL;
  115. debugfs_root = sde_debugfs_get_root(sde_kms);
  116. if (!debugfs_root)
  117. return -EINVAL;
  118. /* allow debugfs_root to be NULL */
  119. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  120. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  121. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  122. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  123. if (rc) {
  124. SDE_ERROR("failed to init perf %d\n", rc);
  125. return rc;
  126. }
  127. if (sde_kms->catalog->qdss_count)
  128. debugfs_create_u32("qdss", 0600, debugfs_root,
  129. (u32 *)&sde_kms->qdss_enabled);
  130. return 0;
  131. }
  132. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  133. {
  134. /* don't need to NULL check debugfs_root */
  135. if (sde_kms) {
  136. sde_debugfs_vbif_destroy(sde_kms);
  137. sde_debugfs_core_irq_destroy(sde_kms);
  138. }
  139. }
  140. #else
  141. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  142. {
  143. return 0;
  144. }
  145. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  146. {
  147. }
  148. #endif
  149. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  150. {
  151. int ret = 0;
  152. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  153. ret = sde_crtc_vblank(crtc, true);
  154. SDE_ATRACE_END("sde_kms_enable_vblank");
  155. return ret;
  156. }
  157. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  158. {
  159. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  160. sde_crtc_vblank(crtc, false);
  161. SDE_ATRACE_END("sde_kms_disable_vblank");
  162. }
  163. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  164. struct drm_crtc *crtc)
  165. {
  166. struct drm_encoder *encoder;
  167. struct drm_device *dev;
  168. int ret;
  169. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  170. SDE_ERROR("invalid params\n");
  171. return;
  172. }
  173. if (!crtc->state->enable) {
  174. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  175. return;
  176. }
  177. if (!crtc->state->active) {
  178. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  179. return;
  180. }
  181. dev = crtc->dev;
  182. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  183. if (encoder->crtc != crtc)
  184. continue;
  185. /*
  186. * Video Mode - Wait for VSYNC
  187. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  188. * complete
  189. */
  190. SDE_EVT32_VERBOSE(DRMID(crtc));
  191. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  192. if (ret && ret != -EWOULDBLOCK) {
  193. SDE_ERROR(
  194. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  195. crtc->base.id, encoder->base.id, ret);
  196. break;
  197. }
  198. }
  199. }
  200. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  201. struct drm_crtc *crtc, bool enable)
  202. {
  203. struct drm_device *dev;
  204. struct msm_drm_private *priv;
  205. struct sde_mdss_cfg *sde_cfg;
  206. struct drm_plane *plane;
  207. int i, ret;
  208. dev = sde_kms->dev;
  209. priv = dev->dev_private;
  210. sde_cfg = sde_kms->catalog;
  211. ret = sde_vbif_halt_xin_mask(sde_kms,
  212. sde_cfg->sui_block_xin_mask, enable);
  213. if (ret) {
  214. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  215. return ret;
  216. }
  217. if (enable) {
  218. for (i = 0; i < priv->num_planes; i++) {
  219. plane = priv->planes[i];
  220. sde_plane_secure_ctrl_xin_client(plane, crtc);
  221. }
  222. }
  223. return 0;
  224. }
  225. /**
  226. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  227. * @sde_kms: Pointer to sde_kms struct
  228. * @vimd: switch the stage 2 translation to this VMID
  229. */
  230. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  231. {
  232. struct drm_device *dev;
  233. uint32_t num_sids;
  234. uint32_t *sec_sid;
  235. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  236. int ret = 0, i;
  237. struct qtee_shm shm;
  238. bool qtee_en = qtee_shmbridge_is_enabled();
  239. phys_addr_t mem_addr;
  240. u64 mem_size;
  241. dev = sde_kms->dev;
  242. num_sids = sde_cfg->sec_sid_mask_count;
  243. if (!num_sids) {
  244. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  245. return -EINVAL;
  246. }
  247. if (qtee_en) {
  248. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  249. &shm);
  250. if (ret)
  251. return -ENOMEM;
  252. sec_sid = (uint32_t *) shm.vaddr;
  253. mem_addr = shm.paddr;
  254. mem_size = shm.size;
  255. } else {
  256. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  257. if (!sec_sid)
  258. return -ENOMEM;
  259. mem_addr = virt_to_phys(sec_sid);
  260. mem_size = sizeof(uint32_t) * num_sids;
  261. }
  262. for (i = 0; i < num_sids; i++) {
  263. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  264. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  265. }
  266. dma_map_single(dev->dev, sec_sid, num_sids *sizeof(uint32_t),
  267. DMA_TO_DEVICE);
  268. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  269. vmid, num_sids, qtee_en);
  270. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  271. mem_size, vmid);
  272. if (ret)
  273. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  274. vmid, ret);
  275. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  276. vmid, qtee_en, num_sids, ret);
  277. if (qtee_en)
  278. qtee_shmbridge_free_shm(&shm);
  279. else
  280. kfree(sec_sid);
  281. return ret;
  282. }
  283. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  284. {
  285. u32 ret;
  286. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  287. return 0;
  288. /* detach_all_contexts */
  289. ret = sde_kms_mmu_detach(sde_kms, false);
  290. if (ret) {
  291. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  292. goto mmu_error;
  293. }
  294. ret = _sde_kms_scm_call(sde_kms, vmid);
  295. if (ret) {
  296. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  297. goto scm_error;
  298. }
  299. return 0;
  300. scm_error:
  301. sde_kms_mmu_attach(sde_kms, false);
  302. mmu_error:
  303. atomic_dec(&sde_kms->detach_all_cb);
  304. return ret;
  305. }
  306. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  307. u32 old_vmid)
  308. {
  309. u32 ret;
  310. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  311. return 0;
  312. ret = _sde_kms_scm_call(sde_kms, vmid);
  313. if (ret) {
  314. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  315. goto scm_error;
  316. }
  317. /* attach_all_contexts */
  318. ret = sde_kms_mmu_attach(sde_kms, false);
  319. if (ret) {
  320. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  321. goto mmu_error;
  322. }
  323. return 0;
  324. mmu_error:
  325. _sde_kms_scm_call(sde_kms, old_vmid);
  326. scm_error:
  327. atomic_inc(&sde_kms->detach_all_cb);
  328. return ret;
  329. }
  330. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  331. {
  332. u32 ret;
  333. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  334. return 0;
  335. /* detach secure_context */
  336. ret = sde_kms_mmu_detach(sde_kms, true);
  337. if (ret) {
  338. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  339. goto mmu_error;
  340. }
  341. ret = _sde_kms_scm_call(sde_kms, vmid);
  342. if (ret) {
  343. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  344. goto scm_error;
  345. }
  346. return 0;
  347. scm_error:
  348. sde_kms_mmu_attach(sde_kms, true);
  349. mmu_error:
  350. atomic_dec(&sde_kms->detach_sec_cb);
  351. return ret;
  352. }
  353. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  354. u32 old_vmid)
  355. {
  356. u32 ret;
  357. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  358. return 0;
  359. ret = _sde_kms_scm_call(sde_kms, vmid);
  360. if (ret) {
  361. goto scm_error;
  362. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  363. }
  364. ret = sde_kms_mmu_attach(sde_kms, true);
  365. if (ret) {
  366. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  367. goto mmu_error;
  368. }
  369. return 0;
  370. mmu_error:
  371. _sde_kms_scm_call(sde_kms, old_vmid);
  372. scm_error:
  373. atomic_inc(&sde_kms->detach_sec_cb);
  374. return ret;
  375. }
  376. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  377. struct drm_crtc *crtc, bool enable)
  378. {
  379. int ret;
  380. if (enable) {
  381. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  382. if (ret < 0) {
  383. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  384. return ret;
  385. }
  386. sde_crtc_misr_setup(crtc, true, 1);
  387. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  388. if (ret) {
  389. sde_crtc_misr_setup(crtc, false, 0);
  390. pm_runtime_put_sync(sde_kms->dev->dev);
  391. return ret;
  392. }
  393. } else {
  394. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  395. sde_crtc_misr_setup(crtc, false, 0);
  396. pm_runtime_put_sync(sde_kms->dev->dev);
  397. }
  398. return 0;
  399. }
  400. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  401. bool post_commit)
  402. {
  403. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  404. int old_smmu_state = smmu_state->state;
  405. int ret = 0;
  406. u32 vmid;
  407. if (!sde_kms || !crtc) {
  408. SDE_ERROR("invalid argument(s)\n");
  409. return -EINVAL;
  410. }
  411. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  412. post_commit, smmu_state->sui_misr_state,
  413. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  414. if ((!smmu_state->transition_type) ||
  415. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  416. /* Bail out */
  417. return 0;
  418. /* enable sui misr if requested, before the transition */
  419. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  420. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  421. if (ret) {
  422. smmu_state->sui_misr_state = NONE;
  423. goto end;
  424. }
  425. }
  426. mutex_lock(&sde_kms->secure_transition_lock);
  427. switch (smmu_state->state) {
  428. case DETACH_ALL_REQ:
  429. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  430. if (!ret)
  431. smmu_state->state = DETACHED;
  432. break;
  433. case ATTACH_ALL_REQ:
  434. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  435. VMID_CP_SEC_DISPLAY);
  436. if (!ret) {
  437. smmu_state->state = ATTACHED;
  438. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  439. }
  440. break;
  441. case DETACH_SEC_REQ:
  442. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  443. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  444. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  445. if (!ret)
  446. smmu_state->state = DETACHED_SEC;
  447. break;
  448. case ATTACH_SEC_REQ:
  449. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  450. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  451. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  452. if (!ret) {
  453. smmu_state->state = ATTACHED;
  454. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  455. }
  456. break;
  457. default:
  458. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  459. DRMID(crtc), smmu_state->state,
  460. smmu_state->transition_type);
  461. ret = -EINVAL;
  462. break;
  463. }
  464. mutex_unlock(&sde_kms->secure_transition_lock);
  465. /* disable sui misr if requested, after the transition */
  466. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  467. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  468. if (ret)
  469. goto end;
  470. }
  471. end:
  472. smmu_state->transition_error = false;
  473. if (ret) {
  474. smmu_state->transition_error = true;
  475. SDE_ERROR(
  476. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  477. DRMID(crtc), old_smmu_state, smmu_state->state,
  478. smmu_state->secure_level, ret);
  479. smmu_state->state = smmu_state->prev_state;
  480. smmu_state->secure_level = smmu_state->prev_secure_level;
  481. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  482. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  483. }
  484. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  485. DRMID(crtc), old_smmu_state, smmu_state->state,
  486. smmu_state->secure_level, ret);
  487. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  488. smmu_state->transition_type,
  489. smmu_state->transition_error,
  490. smmu_state->secure_level, smmu_state->prev_secure_level,
  491. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  492. smmu_state->sui_misr_state = NONE;
  493. smmu_state->transition_type = NONE;
  494. return ret;
  495. }
  496. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  497. struct drm_atomic_state *state)
  498. {
  499. struct drm_crtc *crtc;
  500. struct drm_crtc_state *old_crtc_state;
  501. struct drm_plane *plane;
  502. struct drm_plane_state *plane_state;
  503. struct sde_kms *sde_kms = to_sde_kms(kms);
  504. struct drm_device *dev = sde_kms->dev;
  505. int i, ops = 0, ret = 0;
  506. bool old_valid_fb = false;
  507. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  508. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  509. if (!crtc->state || !crtc->state->active)
  510. continue;
  511. /*
  512. * It is safe to assume only one active crtc,
  513. * and compatible translation modes on the
  514. * planes staged on this crtc.
  515. * otherwise validation would have failed.
  516. * For this CRTC,
  517. */
  518. /*
  519. * 1. Check if old state on the CRTC has planes
  520. * staged with valid fbs
  521. */
  522. for_each_old_plane_in_state(state, plane, plane_state, i) {
  523. if (!plane_state->crtc)
  524. continue;
  525. if (plane_state->fb) {
  526. old_valid_fb = true;
  527. break;
  528. }
  529. }
  530. /*
  531. * 2.Get the operations needed to be performed before
  532. * secure transition can be initiated.
  533. */
  534. ops = sde_crtc_get_secure_transition_ops(crtc,
  535. old_crtc_state, old_valid_fb);
  536. if (ops < 0) {
  537. SDE_ERROR("invalid secure operations %x\n", ops);
  538. return ops;
  539. }
  540. if (!ops) {
  541. smmu_state->transition_error = false;
  542. goto no_ops;
  543. }
  544. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  545. crtc->base.id, ops, crtc->state);
  546. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  547. /* 3. Perform operations needed for secure transition */
  548. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  549. SDE_DEBUG("wait_for_transfer_done\n");
  550. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  551. }
  552. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  553. SDE_DEBUG("cleanup planes\n");
  554. drm_atomic_helper_cleanup_planes(dev, state);
  555. }
  556. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  557. SDE_DEBUG("secure ctrl\n");
  558. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  559. }
  560. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  561. SDE_DEBUG("prepare planes %d",
  562. crtc->state->plane_mask);
  563. drm_atomic_crtc_for_each_plane(plane,
  564. crtc) {
  565. const struct drm_plane_helper_funcs *funcs;
  566. plane_state = plane->state;
  567. funcs = plane->helper_private;
  568. SDE_DEBUG("psde:%d FB[%u]\n",
  569. plane->base.id,
  570. plane->fb->base.id);
  571. if (!funcs)
  572. continue;
  573. if (funcs->prepare_fb(plane, plane_state)) {
  574. ret = funcs->prepare_fb(plane,
  575. plane_state);
  576. if (ret)
  577. return ret;
  578. }
  579. }
  580. }
  581. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  582. SDE_DEBUG("secure operations completed\n");
  583. }
  584. no_ops:
  585. return 0;
  586. }
  587. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  588. unsigned int splash_buffer_size,
  589. unsigned int ramdump_base,
  590. unsigned int ramdump_buffer_size)
  591. {
  592. unsigned long pfn_start, pfn_end, pfn_idx;
  593. int ret = 0;
  594. if (!mem_addr || !splash_buffer_size) {
  595. SDE_ERROR("invalid params\n");
  596. return -EINVAL;
  597. }
  598. /* leave ramdump memory only if base address matches */
  599. if (ramdump_base == mem_addr &&
  600. ramdump_buffer_size <= splash_buffer_size) {
  601. mem_addr += ramdump_buffer_size;
  602. splash_buffer_size -= ramdump_buffer_size;
  603. }
  604. pfn_start = mem_addr >> PAGE_SHIFT;
  605. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  606. ret = memblock_free(mem_addr, splash_buffer_size);
  607. if (ret) {
  608. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  609. return ret;
  610. }
  611. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  612. free_reserved_page(pfn_to_page(pfn_idx));
  613. return ret;
  614. }
  615. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  616. struct sde_splash_mem *splash)
  617. {
  618. struct msm_mmu *mmu = NULL;
  619. int ret = 0;
  620. if (!sde_kms->aspace[0]) {
  621. SDE_ERROR("aspace not found for sde kms node\n");
  622. return -EINVAL;
  623. }
  624. mmu = sde_kms->aspace[0]->mmu;
  625. if (!mmu) {
  626. SDE_ERROR("mmu not found for aspace\n");
  627. return -EINVAL;
  628. }
  629. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  630. SDE_ERROR("invalid input params for map\n");
  631. return -EINVAL;
  632. }
  633. if (!splash->ref_cnt) {
  634. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  635. splash->splash_buf_base,
  636. splash->splash_buf_size,
  637. IOMMU_READ | IOMMU_NOEXEC);
  638. if (ret)
  639. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  640. }
  641. splash->ref_cnt++;
  642. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  643. splash->splash_buf_base,
  644. splash->splash_buf_size,
  645. splash->ref_cnt);
  646. return ret;
  647. }
  648. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  649. {
  650. int i = 0;
  651. int ret = 0;
  652. if (!sde_kms)
  653. return -EINVAL;
  654. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  655. ret = _sde_kms_splash_mem_get(sde_kms,
  656. sde_kms->splash_data.splash_display[i].splash);
  657. if (ret)
  658. return ret;
  659. }
  660. return ret;
  661. }
  662. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  663. struct sde_splash_mem *splash)
  664. {
  665. struct msm_mmu *mmu = NULL;
  666. int rc = 0;
  667. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  668. SDE_ERROR("invalid params\n");
  669. return -EINVAL;
  670. }
  671. mmu = sde_kms->aspace[0]->mmu;
  672. if (!splash || !splash->ref_cnt ||
  673. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  674. return -EINVAL;
  675. splash->ref_cnt--;
  676. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  677. splash->splash_buf_base, splash->ref_cnt);
  678. if (!splash->ref_cnt) {
  679. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  680. splash->splash_buf_size);
  681. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  682. splash->splash_buf_size, splash->ramdump_base,
  683. splash->ramdump_size);
  684. splash->splash_buf_base = 0;
  685. splash->splash_buf_size = 0;
  686. }
  687. return rc;
  688. }
  689. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  690. {
  691. int i = 0;
  692. int ret = 0;
  693. if (!sde_kms)
  694. return -EINVAL;
  695. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  696. ret = _sde_kms_splash_mem_put(sde_kms,
  697. sde_kms->splash_data.splash_display[i].splash);
  698. if (ret)
  699. return ret;
  700. }
  701. return ret;
  702. }
  703. static void sde_kms_prepare_commit(struct msm_kms *kms,
  704. struct drm_atomic_state *state)
  705. {
  706. struct sde_kms *sde_kms;
  707. struct msm_drm_private *priv;
  708. struct drm_device *dev;
  709. struct drm_encoder *encoder;
  710. struct drm_crtc *crtc;
  711. struct drm_crtc_state *crtc_state;
  712. int i, rc;
  713. if (!kms)
  714. return;
  715. sde_kms = to_sde_kms(kms);
  716. dev = sde_kms->dev;
  717. if (!dev || !dev->dev_private)
  718. return;
  719. priv = dev->dev_private;
  720. SDE_ATRACE_BEGIN("prepare_commit");
  721. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  722. if (rc < 0) {
  723. SDE_ERROR("failed to enable power resources %d\n", rc);
  724. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  725. goto end;
  726. }
  727. if (sde_kms->first_kickoff) {
  728. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  729. sde_kms->first_kickoff = false;
  730. }
  731. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  732. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  733. head) {
  734. if (encoder->crtc != crtc)
  735. continue;
  736. sde_encoder_prepare_commit(encoder);
  737. }
  738. }
  739. /*
  740. * NOTE: for secure use cases we want to apply the new HW
  741. * configuration only after completing preparation for secure
  742. * transitions prepare below if any transtions is required.
  743. */
  744. sde_kms_prepare_secure_transition(kms, state);
  745. end:
  746. SDE_ATRACE_END("prepare_commit");
  747. }
  748. static void sde_kms_commit(struct msm_kms *kms,
  749. struct drm_atomic_state *old_state)
  750. {
  751. struct sde_kms *sde_kms;
  752. struct drm_crtc *crtc;
  753. struct drm_crtc_state *old_crtc_state;
  754. int i;
  755. if (!kms || !old_state)
  756. return;
  757. sde_kms = to_sde_kms(kms);
  758. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  759. SDE_ERROR("power resource is not enabled\n");
  760. return;
  761. }
  762. SDE_ATRACE_BEGIN("sde_kms_commit");
  763. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  764. if (crtc->state->active) {
  765. SDE_EVT32(DRMID(crtc));
  766. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  767. }
  768. }
  769. SDE_ATRACE_END("sde_kms_commit");
  770. }
  771. static void _sde_kms_free_splash_region(struct sde_kms *sde_kms,
  772. struct sde_splash_display *splash_display)
  773. {
  774. if (!sde_kms || !splash_display ||
  775. !sde_kms->splash_data.num_splash_displays)
  776. return;
  777. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  778. sde_kms->splash_data.num_splash_displays--;
  779. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  780. sde_kms->splash_data.num_splash_displays);
  781. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  782. }
  783. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  784. struct drm_crtc *crtc)
  785. {
  786. struct msm_drm_private *priv;
  787. struct sde_splash_display *splash_display;
  788. int i;
  789. if (!sde_kms || !crtc)
  790. return;
  791. priv = sde_kms->dev->dev_private;
  792. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  793. return;
  794. SDE_EVT32(DRMID(crtc), crtc->state->active,
  795. sde_kms->splash_data.num_splash_displays);
  796. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  797. splash_display = &sde_kms->splash_data.splash_display[i];
  798. if (splash_display->encoder &&
  799. crtc == splash_display->encoder->crtc)
  800. break;
  801. }
  802. if (i >= MAX_DSI_DISPLAYS)
  803. return;
  804. if (splash_display->cont_splash_enabled) {
  805. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  806. splash_display, false);
  807. _sde_kms_free_splash_region(sde_kms, splash_display);
  808. }
  809. /* remove the votes if all displays are done with splash */
  810. if (!sde_kms->splash_data.num_splash_displays) {
  811. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  812. sde_power_data_bus_set_quota(&priv->phandle, i,
  813. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  814. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  815. pm_runtime_put_sync(sde_kms->dev->dev);
  816. }
  817. }
  818. static void sde_kms_complete_commit(struct msm_kms *kms,
  819. struct drm_atomic_state *old_state)
  820. {
  821. struct sde_kms *sde_kms;
  822. struct msm_drm_private *priv;
  823. struct drm_crtc *crtc;
  824. struct drm_crtc_state *old_crtc_state;
  825. struct drm_connector *connector;
  826. struct drm_connector_state *old_conn_state;
  827. struct msm_display_conn_params params;
  828. int i, rc = 0;
  829. if (!kms || !old_state)
  830. return;
  831. sde_kms = to_sde_kms(kms);
  832. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  833. return;
  834. priv = sde_kms->dev->dev_private;
  835. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  836. SDE_ERROR("power resource is not enabled\n");
  837. return;
  838. }
  839. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  840. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  841. sde_crtc_complete_commit(crtc, old_crtc_state);
  842. /* complete secure transitions if any */
  843. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  844. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  845. }
  846. for_each_old_connector_in_state(old_state, connector,
  847. old_conn_state, i) {
  848. struct sde_connector *c_conn;
  849. c_conn = to_sde_connector(connector);
  850. if (!c_conn->ops.post_kickoff)
  851. continue;
  852. memset(&params, 0, sizeof(params));
  853. sde_connector_complete_qsync_commit(connector, &params);
  854. rc = c_conn->ops.post_kickoff(connector, &params);
  855. if (rc) {
  856. pr_err("Connector Post kickoff failed rc=%d\n",
  857. rc);
  858. }
  859. }
  860. pm_runtime_put_sync(sde_kms->dev->dev);
  861. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  862. _sde_kms_release_splash_resource(sde_kms, crtc);
  863. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  864. SDE_ATRACE_END("sde_kms_complete_commit");
  865. }
  866. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  867. struct drm_crtc *crtc)
  868. {
  869. struct drm_encoder *encoder;
  870. struct drm_device *dev;
  871. int ret;
  872. if (!kms || !crtc || !crtc->state) {
  873. SDE_ERROR("invalid params\n");
  874. return;
  875. }
  876. dev = crtc->dev;
  877. if (!crtc->state->enable) {
  878. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  879. return;
  880. }
  881. if (!crtc->state->active) {
  882. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  883. return;
  884. }
  885. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  886. SDE_ERROR("power resource is not enabled\n");
  887. return;
  888. }
  889. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  890. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  891. if (encoder->crtc != crtc)
  892. continue;
  893. /*
  894. * Wait for post-flush if necessary to delay before
  895. * plane_cleanup. For example, wait for vsync in case of video
  896. * mode panels. This may be a no-op for command mode panels.
  897. */
  898. SDE_EVT32_VERBOSE(DRMID(crtc));
  899. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  900. if (ret && ret != -EWOULDBLOCK) {
  901. SDE_ERROR("wait for commit done returned %d\n", ret);
  902. sde_crtc_request_frame_reset(crtc);
  903. break;
  904. }
  905. sde_crtc_complete_flip(crtc, NULL);
  906. }
  907. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  908. }
  909. static void sde_kms_prepare_fence(struct msm_kms *kms,
  910. struct drm_atomic_state *old_state)
  911. {
  912. struct drm_crtc *crtc;
  913. struct drm_crtc_state *old_crtc_state;
  914. int i, rc;
  915. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  916. SDE_ERROR("invalid argument(s)\n");
  917. return;
  918. }
  919. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  920. retry:
  921. /* attempt to acquire ww mutex for connection */
  922. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  923. old_state->acquire_ctx);
  924. if (rc == -EDEADLK) {
  925. drm_modeset_backoff(old_state->acquire_ctx);
  926. goto retry;
  927. }
  928. /* old_state actually contains updated crtc pointers */
  929. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  930. if (crtc->state->active || crtc->state->active_changed)
  931. sde_crtc_prepare_commit(crtc, old_crtc_state);
  932. }
  933. SDE_ATRACE_END("sde_kms_prepare_fence");
  934. }
  935. /**
  936. * _sde_kms_get_displays - query for underlying display handles and cache them
  937. * @sde_kms: Pointer to sde kms structure
  938. * Returns: Zero on success
  939. */
  940. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  941. {
  942. int rc = -ENOMEM;
  943. if (!sde_kms) {
  944. SDE_ERROR("invalid sde kms\n");
  945. return -EINVAL;
  946. }
  947. /* dsi */
  948. sde_kms->dsi_displays = NULL;
  949. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  950. if (sde_kms->dsi_display_count) {
  951. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  952. sizeof(void *),
  953. GFP_KERNEL);
  954. if (!sde_kms->dsi_displays) {
  955. SDE_ERROR("failed to allocate dsi displays\n");
  956. goto exit_deinit_dsi;
  957. }
  958. sde_kms->dsi_display_count =
  959. dsi_display_get_active_displays(sde_kms->dsi_displays,
  960. sde_kms->dsi_display_count);
  961. }
  962. /* wb */
  963. sde_kms->wb_displays = NULL;
  964. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  965. if (sde_kms->wb_display_count) {
  966. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  967. sizeof(void *),
  968. GFP_KERNEL);
  969. if (!sde_kms->wb_displays) {
  970. SDE_ERROR("failed to allocate wb displays\n");
  971. goto exit_deinit_wb;
  972. }
  973. sde_kms->wb_display_count =
  974. wb_display_get_displays(sde_kms->wb_displays,
  975. sde_kms->wb_display_count);
  976. }
  977. /* dp */
  978. sde_kms->dp_displays = NULL;
  979. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  980. if (sde_kms->dp_display_count) {
  981. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  982. sizeof(void *), GFP_KERNEL);
  983. if (!sde_kms->dp_displays) {
  984. SDE_ERROR("failed to allocate dp displays\n");
  985. goto exit_deinit_dp;
  986. }
  987. sde_kms->dp_display_count =
  988. dp_display_get_displays(sde_kms->dp_displays,
  989. sde_kms->dp_display_count);
  990. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  991. }
  992. return 0;
  993. exit_deinit_dp:
  994. kfree(sde_kms->dp_displays);
  995. sde_kms->dp_stream_count = 0;
  996. sde_kms->dp_display_count = 0;
  997. sde_kms->dp_displays = NULL;
  998. exit_deinit_wb:
  999. kfree(sde_kms->wb_displays);
  1000. sde_kms->wb_display_count = 0;
  1001. sde_kms->wb_displays = NULL;
  1002. exit_deinit_dsi:
  1003. kfree(sde_kms->dsi_displays);
  1004. sde_kms->dsi_display_count = 0;
  1005. sde_kms->dsi_displays = NULL;
  1006. return rc;
  1007. }
  1008. /**
  1009. * _sde_kms_release_displays - release cache of underlying display handles
  1010. * @sde_kms: Pointer to sde kms structure
  1011. */
  1012. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1013. {
  1014. if (!sde_kms) {
  1015. SDE_ERROR("invalid sde kms\n");
  1016. return;
  1017. }
  1018. kfree(sde_kms->wb_displays);
  1019. sde_kms->wb_displays = NULL;
  1020. sde_kms->wb_display_count = 0;
  1021. kfree(sde_kms->dsi_displays);
  1022. sde_kms->dsi_displays = NULL;
  1023. sde_kms->dsi_display_count = 0;
  1024. }
  1025. /**
  1026. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1027. * for underlying displays
  1028. * @dev: Pointer to drm device structure
  1029. * @priv: Pointer to private drm device data
  1030. * @sde_kms: Pointer to sde kms structure
  1031. * Returns: Zero on success
  1032. */
  1033. static int _sde_kms_setup_displays(struct drm_device *dev,
  1034. struct msm_drm_private *priv,
  1035. struct sde_kms *sde_kms)
  1036. {
  1037. static const struct sde_connector_ops dsi_ops = {
  1038. .set_info_blob = dsi_conn_set_info_blob,
  1039. .detect = dsi_conn_detect,
  1040. .get_modes = dsi_connector_get_modes,
  1041. .pre_destroy = dsi_connector_put_modes,
  1042. .mode_valid = dsi_conn_mode_valid,
  1043. .get_info = dsi_display_get_info,
  1044. .set_backlight = dsi_display_set_backlight,
  1045. .soft_reset = dsi_display_soft_reset,
  1046. .pre_kickoff = dsi_conn_pre_kickoff,
  1047. .clk_ctrl = dsi_display_clk_ctrl,
  1048. .set_power = dsi_display_set_power,
  1049. .get_mode_info = dsi_conn_get_mode_info,
  1050. .get_dst_format = dsi_display_get_dst_format,
  1051. .post_kickoff = dsi_conn_post_kickoff,
  1052. .check_status = dsi_display_check_status,
  1053. .enable_event = dsi_conn_enable_event,
  1054. .cmd_transfer = dsi_display_cmd_transfer,
  1055. .cont_splash_config = dsi_display_cont_splash_config,
  1056. .get_panel_vfp = dsi_display_get_panel_vfp,
  1057. .get_default_lms = dsi_display_get_default_lms,
  1058. };
  1059. static const struct sde_connector_ops wb_ops = {
  1060. .post_init = sde_wb_connector_post_init,
  1061. .set_info_blob = sde_wb_connector_set_info_blob,
  1062. .detect = sde_wb_connector_detect,
  1063. .get_modes = sde_wb_connector_get_modes,
  1064. .set_property = sde_wb_connector_set_property,
  1065. .get_info = sde_wb_get_info,
  1066. .soft_reset = NULL,
  1067. .get_mode_info = sde_wb_get_mode_info,
  1068. .get_dst_format = NULL,
  1069. .check_status = NULL,
  1070. .cmd_transfer = NULL,
  1071. .cont_splash_config = NULL,
  1072. .get_panel_vfp = NULL,
  1073. };
  1074. static const struct sde_connector_ops dp_ops = {
  1075. .post_init = dp_connector_post_init,
  1076. .detect = dp_connector_detect,
  1077. .get_modes = dp_connector_get_modes,
  1078. .atomic_check = dp_connector_atomic_check,
  1079. .mode_valid = dp_connector_mode_valid,
  1080. .get_info = dp_connector_get_info,
  1081. .get_mode_info = dp_connector_get_mode_info,
  1082. .post_open = dp_connector_post_open,
  1083. .check_status = NULL,
  1084. .set_colorspace = dp_connector_set_colorspace,
  1085. .config_hdr = dp_connector_config_hdr,
  1086. .cmd_transfer = NULL,
  1087. .cont_splash_config = NULL,
  1088. .get_panel_vfp = NULL,
  1089. .update_pps = dp_connector_update_pps,
  1090. };
  1091. struct msm_display_info info;
  1092. struct drm_encoder *encoder;
  1093. void *display, *connector;
  1094. int i, max_encoders;
  1095. int rc = 0;
  1096. if (!dev || !priv || !sde_kms) {
  1097. SDE_ERROR("invalid argument(s)\n");
  1098. return -EINVAL;
  1099. }
  1100. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1101. sde_kms->dp_display_count +
  1102. sde_kms->dp_stream_count;
  1103. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1104. max_encoders = ARRAY_SIZE(priv->encoders);
  1105. SDE_ERROR("capping number of displays to %d", max_encoders);
  1106. }
  1107. /* wb */
  1108. for (i = 0; i < sde_kms->wb_display_count &&
  1109. priv->num_encoders < max_encoders; ++i) {
  1110. display = sde_kms->wb_displays[i];
  1111. encoder = NULL;
  1112. memset(&info, 0x0, sizeof(info));
  1113. rc = sde_wb_get_info(NULL, &info, display);
  1114. if (rc) {
  1115. SDE_ERROR("wb get_info %d failed\n", i);
  1116. continue;
  1117. }
  1118. encoder = sde_encoder_init(dev, &info);
  1119. if (IS_ERR_OR_NULL(encoder)) {
  1120. SDE_ERROR("encoder init failed for wb %d\n", i);
  1121. continue;
  1122. }
  1123. rc = sde_wb_drm_init(display, encoder);
  1124. if (rc) {
  1125. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1126. sde_encoder_destroy(encoder);
  1127. continue;
  1128. }
  1129. connector = sde_connector_init(dev,
  1130. encoder,
  1131. 0,
  1132. display,
  1133. &wb_ops,
  1134. DRM_CONNECTOR_POLL_HPD,
  1135. DRM_MODE_CONNECTOR_VIRTUAL);
  1136. if (connector) {
  1137. priv->encoders[priv->num_encoders++] = encoder;
  1138. priv->connectors[priv->num_connectors++] = connector;
  1139. } else {
  1140. SDE_ERROR("wb %d connector init failed\n", i);
  1141. sde_wb_drm_deinit(display);
  1142. sde_encoder_destroy(encoder);
  1143. }
  1144. }
  1145. /* dsi */
  1146. for (i = 0; i < sde_kms->dsi_display_count &&
  1147. priv->num_encoders < max_encoders; ++i) {
  1148. display = sde_kms->dsi_displays[i];
  1149. encoder = NULL;
  1150. memset(&info, 0x0, sizeof(info));
  1151. rc = dsi_display_get_info(NULL, &info, display);
  1152. if (rc) {
  1153. SDE_ERROR("dsi get_info %d failed\n", i);
  1154. continue;
  1155. }
  1156. encoder = sde_encoder_init(dev, &info);
  1157. if (IS_ERR_OR_NULL(encoder)) {
  1158. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1159. continue;
  1160. }
  1161. rc = dsi_display_drm_bridge_init(display, encoder);
  1162. if (rc) {
  1163. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1164. sde_encoder_destroy(encoder);
  1165. continue;
  1166. }
  1167. connector = sde_connector_init(dev,
  1168. encoder,
  1169. dsi_display_get_drm_panel(display),
  1170. display,
  1171. &dsi_ops,
  1172. DRM_CONNECTOR_POLL_HPD,
  1173. DRM_MODE_CONNECTOR_DSI);
  1174. if (connector) {
  1175. priv->encoders[priv->num_encoders++] = encoder;
  1176. priv->connectors[priv->num_connectors++] = connector;
  1177. } else {
  1178. SDE_ERROR("dsi %d connector init failed\n", i);
  1179. dsi_display_drm_bridge_deinit(display);
  1180. sde_encoder_destroy(encoder);
  1181. continue;
  1182. }
  1183. rc = dsi_display_drm_ext_bridge_init(display,
  1184. encoder, connector);
  1185. if (rc) {
  1186. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1187. dsi_display_drm_bridge_deinit(display);
  1188. sde_connector_destroy(connector);
  1189. sde_encoder_destroy(encoder);
  1190. }
  1191. }
  1192. /* dp */
  1193. for (i = 0; i < sde_kms->dp_display_count &&
  1194. priv->num_encoders < max_encoders; ++i) {
  1195. int idx;
  1196. display = sde_kms->dp_displays[i];
  1197. encoder = NULL;
  1198. memset(&info, 0x0, sizeof(info));
  1199. rc = dp_connector_get_info(NULL, &info, display);
  1200. if (rc) {
  1201. SDE_ERROR("dp get_info %d failed\n", i);
  1202. continue;
  1203. }
  1204. encoder = sde_encoder_init(dev, &info);
  1205. if (IS_ERR_OR_NULL(encoder)) {
  1206. SDE_ERROR("dp encoder init failed %d\n", i);
  1207. continue;
  1208. }
  1209. rc = dp_drm_bridge_init(display, encoder);
  1210. if (rc) {
  1211. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1212. sde_encoder_destroy(encoder);
  1213. continue;
  1214. }
  1215. connector = sde_connector_init(dev,
  1216. encoder,
  1217. NULL,
  1218. display,
  1219. &dp_ops,
  1220. DRM_CONNECTOR_POLL_HPD,
  1221. DRM_MODE_CONNECTOR_DisplayPort);
  1222. if (connector) {
  1223. priv->encoders[priv->num_encoders++] = encoder;
  1224. priv->connectors[priv->num_connectors++] = connector;
  1225. } else {
  1226. SDE_ERROR("dp %d connector init failed\n", i);
  1227. dp_drm_bridge_deinit(display);
  1228. sde_encoder_destroy(encoder);
  1229. }
  1230. /* update display cap to MST_MODE for DP MST encoders */
  1231. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1232. for (idx = 0; idx < sde_kms->dp_stream_count; idx++) {
  1233. info.h_tile_instance[0] = idx;
  1234. encoder = sde_encoder_init(dev, &info);
  1235. if (IS_ERR_OR_NULL(encoder)) {
  1236. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1237. continue;
  1238. }
  1239. rc = dp_mst_drm_bridge_init(display, encoder);
  1240. if (rc) {
  1241. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1242. i, rc);
  1243. sde_encoder_destroy(encoder);
  1244. continue;
  1245. }
  1246. priv->encoders[priv->num_encoders++] = encoder;
  1247. }
  1248. }
  1249. return 0;
  1250. }
  1251. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1252. {
  1253. struct msm_drm_private *priv;
  1254. int i;
  1255. if (!sde_kms) {
  1256. SDE_ERROR("invalid sde_kms\n");
  1257. return;
  1258. } else if (!sde_kms->dev) {
  1259. SDE_ERROR("invalid dev\n");
  1260. return;
  1261. } else if (!sde_kms->dev->dev_private) {
  1262. SDE_ERROR("invalid dev_private\n");
  1263. return;
  1264. }
  1265. priv = sde_kms->dev->dev_private;
  1266. for (i = 0; i < priv->num_crtcs; i++)
  1267. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1268. priv->num_crtcs = 0;
  1269. for (i = 0; i < priv->num_planes; i++)
  1270. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1271. priv->num_planes = 0;
  1272. for (i = 0; i < priv->num_connectors; i++)
  1273. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1274. priv->num_connectors = 0;
  1275. for (i = 0; i < priv->num_encoders; i++)
  1276. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1277. priv->num_encoders = 0;
  1278. _sde_kms_release_displays(sde_kms);
  1279. }
  1280. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1281. {
  1282. struct drm_device *dev;
  1283. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1284. struct drm_crtc *crtc;
  1285. struct msm_drm_private *priv;
  1286. struct sde_mdss_cfg *catalog;
  1287. int primary_planes_idx = 0, i, ret;
  1288. int max_crtc_count;
  1289. u32 sspp_id[MAX_PLANES];
  1290. u32 master_plane_id[MAX_PLANES];
  1291. u32 num_virt_planes = 0;
  1292. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1293. SDE_ERROR("invalid sde_kms\n");
  1294. return -EINVAL;
  1295. }
  1296. dev = sde_kms->dev;
  1297. priv = dev->dev_private;
  1298. catalog = sde_kms->catalog;
  1299. ret = sde_core_irq_domain_add(sde_kms);
  1300. if (ret)
  1301. goto fail_irq;
  1302. /*
  1303. * Query for underlying display drivers, and create connectors,
  1304. * bridges and encoders for them.
  1305. */
  1306. if (!_sde_kms_get_displays(sde_kms))
  1307. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1308. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1309. /* Create the planes */
  1310. for (i = 0; i < catalog->sspp_count; i++) {
  1311. bool primary = true;
  1312. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1313. || primary_planes_idx >= max_crtc_count)
  1314. primary = false;
  1315. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1316. (1UL << max_crtc_count) - 1, 0);
  1317. if (IS_ERR(plane)) {
  1318. SDE_ERROR("sde_plane_init failed\n");
  1319. ret = PTR_ERR(plane);
  1320. goto fail;
  1321. }
  1322. priv->planes[priv->num_planes++] = plane;
  1323. if (primary)
  1324. primary_planes[primary_planes_idx++] = plane;
  1325. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1326. sde_is_custom_client()) {
  1327. int priority =
  1328. catalog->sspp[i].sblk->smart_dma_priority;
  1329. sspp_id[priority - 1] = catalog->sspp[i].id;
  1330. master_plane_id[priority - 1] = plane->base.id;
  1331. num_virt_planes++;
  1332. }
  1333. }
  1334. /* Initialize smart DMA virtual planes */
  1335. for (i = 0; i < num_virt_planes; i++) {
  1336. plane = sde_plane_init(dev, sspp_id[i], false,
  1337. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1338. if (IS_ERR(plane)) {
  1339. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1340. ret = PTR_ERR(plane);
  1341. goto fail;
  1342. }
  1343. priv->planes[priv->num_planes++] = plane;
  1344. }
  1345. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1346. /* Create one CRTC per encoder */
  1347. for (i = 0; i < max_crtc_count; i++) {
  1348. crtc = sde_crtc_init(dev, primary_planes[i]);
  1349. if (IS_ERR(crtc)) {
  1350. ret = PTR_ERR(crtc);
  1351. goto fail;
  1352. }
  1353. priv->crtcs[priv->num_crtcs++] = crtc;
  1354. }
  1355. if (sde_is_custom_client()) {
  1356. /* All CRTCs are compatible with all planes */
  1357. for (i = 0; i < priv->num_planes; i++)
  1358. priv->planes[i]->possible_crtcs =
  1359. (1 << priv->num_crtcs) - 1;
  1360. }
  1361. /* All CRTCs are compatible with all encoders */
  1362. for (i = 0; i < priv->num_encoders; i++)
  1363. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1364. return 0;
  1365. fail:
  1366. _sde_kms_drm_obj_destroy(sde_kms);
  1367. fail_irq:
  1368. sde_core_irq_domain_fini(sde_kms);
  1369. return ret;
  1370. }
  1371. /**
  1372. * sde_kms_timeline_status - provides current timeline status
  1373. * This API should be called without mode config lock.
  1374. * @dev: Pointer to drm device
  1375. */
  1376. void sde_kms_timeline_status(struct drm_device *dev)
  1377. {
  1378. struct drm_crtc *crtc;
  1379. struct drm_connector *conn;
  1380. struct drm_connector_list_iter conn_iter;
  1381. if (!dev) {
  1382. SDE_ERROR("invalid drm device node\n");
  1383. return;
  1384. }
  1385. drm_for_each_crtc(crtc, dev)
  1386. sde_crtc_timeline_status(crtc);
  1387. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1388. /*
  1389. *Probably locked from last close dumping status anyway
  1390. */
  1391. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1392. drm_connector_list_iter_begin(dev, &conn_iter);
  1393. drm_for_each_connector_iter(conn, &conn_iter)
  1394. sde_conn_timeline_status(conn);
  1395. drm_connector_list_iter_end(&conn_iter);
  1396. return;
  1397. }
  1398. mutex_lock(&dev->mode_config.mutex);
  1399. drm_connector_list_iter_begin(dev, &conn_iter);
  1400. drm_for_each_connector_iter(conn, &conn_iter)
  1401. sde_conn_timeline_status(conn);
  1402. drm_connector_list_iter_end(&conn_iter);
  1403. mutex_unlock(&dev->mode_config.mutex);
  1404. }
  1405. static int sde_kms_postinit(struct msm_kms *kms)
  1406. {
  1407. struct sde_kms *sde_kms = to_sde_kms(kms);
  1408. struct drm_device *dev;
  1409. struct drm_crtc *crtc;
  1410. int rc;
  1411. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1412. SDE_ERROR("invalid sde_kms\n");
  1413. return -EINVAL;
  1414. }
  1415. dev = sde_kms->dev;
  1416. rc = _sde_debugfs_init(sde_kms);
  1417. if (rc)
  1418. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1419. drm_for_each_crtc(crtc, dev)
  1420. sde_crtc_post_init(dev, crtc);
  1421. return rc;
  1422. }
  1423. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1424. struct drm_encoder *encoder)
  1425. {
  1426. return rate;
  1427. }
  1428. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1429. struct platform_device *pdev)
  1430. {
  1431. struct drm_device *dev;
  1432. struct msm_drm_private *priv;
  1433. int i;
  1434. if (!sde_kms || !pdev)
  1435. return;
  1436. dev = sde_kms->dev;
  1437. if (!dev)
  1438. return;
  1439. priv = dev->dev_private;
  1440. if (!priv)
  1441. return;
  1442. if (sde_kms->genpd_init) {
  1443. sde_kms->genpd_init = false;
  1444. pm_genpd_remove(&sde_kms->genpd);
  1445. of_genpd_del_provider(pdev->dev.of_node);
  1446. }
  1447. if (sde_kms->hw_intr)
  1448. sde_hw_intr_destroy(sde_kms->hw_intr);
  1449. sde_kms->hw_intr = NULL;
  1450. if (sde_kms->power_event)
  1451. sde_power_handle_unregister_event(
  1452. &priv->phandle, sde_kms->power_event);
  1453. _sde_kms_release_displays(sde_kms);
  1454. _sde_kms_unmap_all_splash_regions(sde_kms);
  1455. /* safe to call these more than once during shutdown */
  1456. _sde_debugfs_destroy(sde_kms);
  1457. _sde_kms_mmu_destroy(sde_kms);
  1458. if (sde_kms->catalog) {
  1459. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1460. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1461. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1462. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1463. }
  1464. }
  1465. if (sde_kms->rm_init)
  1466. sde_rm_destroy(&sde_kms->rm);
  1467. sde_kms->rm_init = false;
  1468. if (sde_kms->catalog)
  1469. sde_hw_catalog_deinit(sde_kms->catalog);
  1470. sde_kms->catalog = NULL;
  1471. if (sde_kms->sid)
  1472. msm_iounmap(pdev, sde_kms->sid);
  1473. sde_kms->sid = NULL;
  1474. if (sde_kms->reg_dma)
  1475. msm_iounmap(pdev, sde_kms->reg_dma);
  1476. sde_kms->reg_dma = NULL;
  1477. if (sde_kms->vbif[VBIF_NRT])
  1478. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1479. sde_kms->vbif[VBIF_NRT] = NULL;
  1480. if (sde_kms->vbif[VBIF_RT])
  1481. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1482. sde_kms->vbif[VBIF_RT] = NULL;
  1483. if (sde_kms->mmio)
  1484. msm_iounmap(pdev, sde_kms->mmio);
  1485. sde_kms->mmio = NULL;
  1486. sde_reg_dma_deinit();
  1487. }
  1488. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1489. {
  1490. int i;
  1491. if (!sde_kms)
  1492. return -EINVAL;
  1493. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1494. struct msm_mmu *mmu;
  1495. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1496. if (!aspace)
  1497. continue;
  1498. mmu = sde_kms->aspace[i]->mmu;
  1499. if (secure_only &&
  1500. !aspace->mmu->funcs->is_domain_secure(mmu))
  1501. continue;
  1502. /* cleanup aspace before detaching */
  1503. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1504. SDE_DEBUG("Detaching domain:%d\n", i);
  1505. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1506. ARRAY_SIZE(iommu_ports));
  1507. aspace->domain_attached = false;
  1508. }
  1509. return 0;
  1510. }
  1511. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1512. {
  1513. int i;
  1514. if (!sde_kms)
  1515. return -EINVAL;
  1516. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1517. struct msm_mmu *mmu;
  1518. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1519. if (!aspace)
  1520. continue;
  1521. mmu = sde_kms->aspace[i]->mmu;
  1522. if (secure_only &&
  1523. !aspace->mmu->funcs->is_domain_secure(mmu))
  1524. continue;
  1525. SDE_DEBUG("Attaching domain:%d\n", i);
  1526. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1527. ARRAY_SIZE(iommu_ports));
  1528. aspace->domain_attached = true;
  1529. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1530. }
  1531. return 0;
  1532. }
  1533. static void sde_kms_destroy(struct msm_kms *kms)
  1534. {
  1535. struct sde_kms *sde_kms;
  1536. struct drm_device *dev;
  1537. if (!kms) {
  1538. SDE_ERROR("invalid kms\n");
  1539. return;
  1540. }
  1541. sde_kms = to_sde_kms(kms);
  1542. dev = sde_kms->dev;
  1543. if (!dev || !dev->dev) {
  1544. SDE_ERROR("invalid device\n");
  1545. return;
  1546. }
  1547. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1548. kfree(sde_kms);
  1549. }
  1550. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1551. struct drm_atomic_state *state)
  1552. {
  1553. struct drm_device *dev = sde_kms->dev;
  1554. struct drm_plane *plane;
  1555. struct drm_plane_state *plane_state;
  1556. struct drm_crtc *crtc;
  1557. struct drm_crtc_state *crtc_state;
  1558. struct drm_connector *conn;
  1559. struct drm_connector_state *conn_state;
  1560. struct drm_connector_list_iter conn_iter;
  1561. int ret = 0;
  1562. drm_for_each_plane(plane, dev) {
  1563. plane_state = drm_atomic_get_plane_state(state, plane);
  1564. if (IS_ERR(plane_state)) {
  1565. ret = PTR_ERR(plane_state);
  1566. SDE_ERROR("error %d getting plane %d state\n",
  1567. ret, DRMID(plane));
  1568. return ret;
  1569. }
  1570. ret = sde_plane_helper_reset_custom_properties(plane,
  1571. plane_state);
  1572. if (ret) {
  1573. SDE_ERROR("error %d resetting plane props %d\n",
  1574. ret, DRMID(plane));
  1575. return ret;
  1576. }
  1577. }
  1578. drm_for_each_crtc(crtc, dev) {
  1579. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1580. if (IS_ERR(crtc_state)) {
  1581. ret = PTR_ERR(crtc_state);
  1582. SDE_ERROR("error %d getting crtc %d state\n",
  1583. ret, DRMID(crtc));
  1584. return ret;
  1585. }
  1586. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1587. if (ret) {
  1588. SDE_ERROR("error %d resetting crtc props %d\n",
  1589. ret, DRMID(crtc));
  1590. return ret;
  1591. }
  1592. }
  1593. drm_connector_list_iter_begin(dev, &conn_iter);
  1594. drm_for_each_connector_iter(conn, &conn_iter) {
  1595. conn_state = drm_atomic_get_connector_state(state, conn);
  1596. if (IS_ERR(conn_state)) {
  1597. ret = PTR_ERR(conn_state);
  1598. SDE_ERROR("error %d getting connector %d state\n",
  1599. ret, DRMID(conn));
  1600. return ret;
  1601. }
  1602. ret = sde_connector_helper_reset_custom_properties(conn,
  1603. conn_state);
  1604. if (ret) {
  1605. SDE_ERROR("error %d resetting connector props %d\n",
  1606. ret, DRMID(conn));
  1607. return ret;
  1608. }
  1609. }
  1610. drm_connector_list_iter_end(&conn_iter);
  1611. return ret;
  1612. }
  1613. static void sde_kms_lastclose(struct msm_kms *kms)
  1614. {
  1615. struct sde_kms *sde_kms;
  1616. struct drm_device *dev;
  1617. struct drm_atomic_state *state;
  1618. struct drm_modeset_acquire_ctx ctx;
  1619. int ret;
  1620. if (!kms) {
  1621. SDE_ERROR("invalid argument\n");
  1622. return;
  1623. }
  1624. sde_kms = to_sde_kms(kms);
  1625. dev = sde_kms->dev;
  1626. drm_modeset_acquire_init(&ctx, 0);
  1627. state = drm_atomic_state_alloc(dev);
  1628. if (!state) {
  1629. ret = -ENOMEM;
  1630. goto out_ctx;
  1631. }
  1632. state->acquire_ctx = &ctx;
  1633. retry:
  1634. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1635. if (ret)
  1636. goto out_state;
  1637. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1638. if (ret)
  1639. goto out_state;
  1640. ret = drm_atomic_commit(state);
  1641. out_state:
  1642. if (ret == -EDEADLK)
  1643. goto backoff;
  1644. drm_atomic_state_put(state);
  1645. out_ctx:
  1646. drm_modeset_drop_locks(&ctx);
  1647. drm_modeset_acquire_fini(&ctx);
  1648. if (ret)
  1649. SDE_ERROR("kms lastclose failed: %d\n", ret);
  1650. return;
  1651. backoff:
  1652. drm_atomic_state_clear(state);
  1653. drm_modeset_backoff(&ctx);
  1654. goto retry;
  1655. }
  1656. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  1657. struct drm_atomic_state *state)
  1658. {
  1659. struct sde_kms *sde_kms;
  1660. struct drm_device *dev;
  1661. struct drm_crtc *crtc;
  1662. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  1663. struct drm_crtc_state *crtc_state;
  1664. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  1665. bool sec_session = false, global_sec_session = false;
  1666. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  1667. int i;
  1668. if (!kms || !state) {
  1669. return -EINVAL;
  1670. SDE_ERROR("invalid arguments\n");
  1671. }
  1672. sde_kms = to_sde_kms(kms);
  1673. dev = sde_kms->dev;
  1674. /* iterate state object for active secure/non-secure crtc */
  1675. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  1676. if (!crtc_state->active)
  1677. continue;
  1678. active_crtc_cnt++;
  1679. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  1680. &fb_sec, &fb_sec_dir);
  1681. if (fb_sec_dir)
  1682. sec_session = true;
  1683. cur_crtc = crtc;
  1684. }
  1685. /* iterate global list for active and secure/non-secure crtc */
  1686. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1687. if (!crtc->state->active)
  1688. continue;
  1689. global_active_crtc_cnt++;
  1690. /* update only when crtc is not the same as current crtc */
  1691. if (crtc != cur_crtc) {
  1692. fb_ns = fb_sec = fb_sec_dir = 0;
  1693. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  1694. &fb_sec, &fb_sec_dir);
  1695. if (fb_sec_dir)
  1696. global_sec_session = true;
  1697. global_crtc = crtc;
  1698. }
  1699. }
  1700. if (!global_sec_session && !sec_session)
  1701. return 0;
  1702. /*
  1703. * - fail crtc commit, if secure-camera/secure-ui session is
  1704. * in-progress in any other display
  1705. * - fail secure-camera/secure-ui crtc commit, if any other display
  1706. * session is in-progress
  1707. */
  1708. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  1709. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  1710. SDE_ERROR(
  1711. "crtc%d secure check failed global_active:%d active:%d\n",
  1712. cur_crtc ? cur_crtc->base.id : -1,
  1713. global_active_crtc_cnt, active_crtc_cnt);
  1714. return -EPERM;
  1715. /*
  1716. * As only one crtc is allowed during secure session, the crtc
  1717. * in this commit should match with the global crtc
  1718. */
  1719. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  1720. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  1721. cur_crtc->base.id, sec_session,
  1722. global_crtc->base.id, global_sec_session);
  1723. return -EPERM;
  1724. }
  1725. return 0;
  1726. }
  1727. static int sde_kms_atomic_check(struct msm_kms *kms,
  1728. struct drm_atomic_state *state)
  1729. {
  1730. struct sde_kms *sde_kms;
  1731. struct drm_device *dev;
  1732. int ret;
  1733. if (!kms || !state)
  1734. return -EINVAL;
  1735. sde_kms = to_sde_kms(kms);
  1736. dev = sde_kms->dev;
  1737. SDE_ATRACE_BEGIN("atomic_check");
  1738. if (sde_kms_is_suspend_blocked(dev)) {
  1739. SDE_DEBUG("suspended, skip atomic_check\n");
  1740. ret = -EBUSY;
  1741. goto end;
  1742. }
  1743. ret = drm_atomic_helper_check(dev, state);
  1744. if (ret)
  1745. goto end;
  1746. /*
  1747. * Check if any secure transition(moving CRTC between secure and
  1748. * non-secure state and vice-versa) is allowed or not. when moving
  1749. * to secure state, planes with fb_mode set to dir_translated only can
  1750. * be staged on the CRTC, and only one CRTC can be active during
  1751. * Secure state
  1752. */
  1753. ret = sde_kms_check_secure_transition(kms, state);
  1754. end:
  1755. SDE_ATRACE_END("atomic_check");
  1756. return ret;
  1757. }
  1758. static struct msm_gem_address_space*
  1759. _sde_kms_get_address_space(struct msm_kms *kms,
  1760. unsigned int domain)
  1761. {
  1762. struct sde_kms *sde_kms;
  1763. if (!kms) {
  1764. SDE_ERROR("invalid kms\n");
  1765. return NULL;
  1766. }
  1767. sde_kms = to_sde_kms(kms);
  1768. if (!sde_kms) {
  1769. SDE_ERROR("invalid sde_kms\n");
  1770. return NULL;
  1771. }
  1772. if (domain >= MSM_SMMU_DOMAIN_MAX)
  1773. return NULL;
  1774. return (sde_kms->aspace[domain] &&
  1775. sde_kms->aspace[domain]->domain_attached) ?
  1776. sde_kms->aspace[domain] : NULL;
  1777. }
  1778. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  1779. unsigned int domain)
  1780. {
  1781. struct msm_gem_address_space *aspace =
  1782. _sde_kms_get_address_space(kms, domain);
  1783. return (aspace && aspace->domain_attached) ?
  1784. msm_gem_get_aspace_device(aspace) : NULL;
  1785. }
  1786. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  1787. {
  1788. struct drm_device *dev = NULL;
  1789. struct sde_kms *sde_kms = NULL;
  1790. struct drm_connector *connector = NULL;
  1791. struct drm_connector_list_iter conn_iter;
  1792. struct sde_connector *sde_conn = NULL;
  1793. if (!kms) {
  1794. SDE_ERROR("invalid kms\n");
  1795. return;
  1796. }
  1797. sde_kms = to_sde_kms(kms);
  1798. dev = sde_kms->dev;
  1799. if (!dev) {
  1800. SDE_ERROR("invalid device\n");
  1801. return;
  1802. }
  1803. if (!dev->mode_config.poll_enabled)
  1804. return;
  1805. mutex_lock(&dev->mode_config.mutex);
  1806. drm_connector_list_iter_begin(dev, &conn_iter);
  1807. drm_for_each_connector_iter(connector, &conn_iter) {
  1808. /* Only handle HPD capable connectors. */
  1809. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  1810. continue;
  1811. sde_conn = to_sde_connector(connector);
  1812. if (sde_conn->ops.post_open)
  1813. sde_conn->ops.post_open(&sde_conn->base,
  1814. sde_conn->display);
  1815. }
  1816. drm_connector_list_iter_end(&conn_iter);
  1817. mutex_unlock(&dev->mode_config.mutex);
  1818. }
  1819. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  1820. struct sde_splash_display *splash_display,
  1821. struct drm_crtc *crtc)
  1822. {
  1823. struct msm_drm_private *priv;
  1824. struct drm_plane *plane;
  1825. struct sde_splash_mem *splash;
  1826. enum sde_sspp plane_id;
  1827. bool is_virtual;
  1828. int i, j;
  1829. if (!sde_kms || !splash_display || !crtc) {
  1830. SDE_ERROR("invalid input args\n");
  1831. return -EINVAL;
  1832. }
  1833. priv = sde_kms->dev->dev_private;
  1834. for (i = 0; i < priv->num_planes; i++) {
  1835. plane = priv->planes[i];
  1836. plane_id = sde_plane_pipe(plane);
  1837. is_virtual = is_sde_plane_virtual(plane);
  1838. splash = splash_display->splash;
  1839. for (j = 0; j < splash_display->pipe_cnt; j++) {
  1840. if ((plane_id != splash_display->pipes[j].sspp) ||
  1841. (splash_display->pipes[j].is_virtual
  1842. != is_virtual))
  1843. continue;
  1844. if (splash && sde_plane_validate_src_addr(plane,
  1845. splash->splash_buf_base,
  1846. splash->splash_buf_size)) {
  1847. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  1848. plane_id, crtc->base.id);
  1849. }
  1850. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  1851. crtc->base.id, plane_id, is_virtual);
  1852. }
  1853. }
  1854. return 0;
  1855. }
  1856. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  1857. {
  1858. void *display;
  1859. struct dsi_display *dsi_display;
  1860. struct msm_display_info info;
  1861. struct drm_encoder *encoder = NULL;
  1862. struct drm_crtc *crtc = NULL;
  1863. int i, rc = 0;
  1864. struct drm_display_mode *drm_mode = NULL;
  1865. struct drm_device *dev;
  1866. struct msm_drm_private *priv;
  1867. struct sde_kms *sde_kms;
  1868. struct drm_connector_list_iter conn_iter;
  1869. struct drm_connector *connector = NULL;
  1870. struct sde_connector *sde_conn = NULL;
  1871. struct sde_splash_display *splash_display;
  1872. if (!kms) {
  1873. SDE_ERROR("invalid kms\n");
  1874. return -EINVAL;
  1875. }
  1876. sde_kms = to_sde_kms(kms);
  1877. dev = sde_kms->dev;
  1878. if (!dev) {
  1879. SDE_ERROR("invalid device\n");
  1880. return -EINVAL;
  1881. }
  1882. if (!sde_kms->splash_data.num_splash_regions ||
  1883. !sde_kms->splash_data.num_splash_displays) {
  1884. DRM_INFO("cont_splash feature not enabled\n");
  1885. return rc;
  1886. }
  1887. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  1888. sde_kms->splash_data.num_splash_displays,
  1889. sde_kms->dsi_display_count);
  1890. /* dsi */
  1891. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  1892. display = sde_kms->dsi_displays[i];
  1893. dsi_display = (struct dsi_display *)display;
  1894. splash_display = &sde_kms->splash_data.splash_display[i];
  1895. if (!splash_display->cont_splash_enabled) {
  1896. SDE_DEBUG("display->name = %s splash not enabled\n",
  1897. dsi_display->name);
  1898. continue;
  1899. }
  1900. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  1901. if (dsi_display->bridge->base.encoder) {
  1902. encoder = dsi_display->bridge->base.encoder;
  1903. SDE_DEBUG("encoder name = %s\n", encoder->name);
  1904. }
  1905. memset(&info, 0x0, sizeof(info));
  1906. rc = dsi_display_get_info(NULL, &info, display);
  1907. if (rc) {
  1908. SDE_ERROR("dsi get_info %d failed\n", i);
  1909. encoder = NULL;
  1910. continue;
  1911. }
  1912. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  1913. ((info.is_connected) ? "true" : "false"),
  1914. info.display_type);
  1915. if (!encoder) {
  1916. SDE_ERROR("encoder not initialized\n");
  1917. return -EINVAL;
  1918. }
  1919. priv = sde_kms->dev->dev_private;
  1920. encoder->crtc = priv->crtcs[i];
  1921. crtc = encoder->crtc;
  1922. splash_display->encoder = encoder;
  1923. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  1924. i, crtc->base.id, encoder->base.id);
  1925. mutex_lock(&dev->mode_config.mutex);
  1926. drm_connector_list_iter_begin(dev, &conn_iter);
  1927. drm_for_each_connector_iter(connector, &conn_iter) {
  1928. /**
  1929. * SDE_KMS doesn't attach more than one encoder to
  1930. * a DSI connector. So it is safe to check only with
  1931. * the first encoder entry. Revisit this logic if we
  1932. * ever have to support continuous splash for
  1933. * external displays in MST configuration.
  1934. */
  1935. if (connector->encoder_ids[0] == encoder->base.id)
  1936. break;
  1937. }
  1938. drm_connector_list_iter_end(&conn_iter);
  1939. if (!connector) {
  1940. SDE_ERROR("connector not initialized\n");
  1941. mutex_unlock(&dev->mode_config.mutex);
  1942. return -EINVAL;
  1943. }
  1944. if (connector->funcs->fill_modes) {
  1945. connector->funcs->fill_modes(connector,
  1946. dev->mode_config.max_width,
  1947. dev->mode_config.max_height);
  1948. } else {
  1949. SDE_ERROR("fill_modes api not defined\n");
  1950. mutex_unlock(&dev->mode_config.mutex);
  1951. return -EINVAL;
  1952. }
  1953. mutex_unlock(&dev->mode_config.mutex);
  1954. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  1955. /* currently consider modes[0] as the preferred mode */
  1956. drm_mode = list_first_entry(&connector->modes,
  1957. struct drm_display_mode, head);
  1958. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  1959. drm_mode->name, drm_mode->type,
  1960. drm_mode->flags);
  1961. /* Update CRTC drm structure */
  1962. crtc->state->active = true;
  1963. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  1964. if (rc) {
  1965. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  1966. return rc;
  1967. }
  1968. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  1969. drm_mode_copy(&crtc->mode, drm_mode);
  1970. /* Update encoder structure */
  1971. sde_encoder_update_caps_for_cont_splash(encoder,
  1972. splash_display, true);
  1973. sde_crtc_update_cont_splash_settings(crtc);
  1974. sde_conn = to_sde_connector(connector);
  1975. if (sde_conn && sde_conn->ops.cont_splash_config)
  1976. sde_conn->ops.cont_splash_config(sde_conn->display);
  1977. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  1978. splash_display, crtc);
  1979. if (rc) {
  1980. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  1981. return rc;
  1982. }
  1983. }
  1984. return rc;
  1985. }
  1986. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  1987. {
  1988. struct sde_kms *sde_kms;
  1989. if (!kms) {
  1990. SDE_ERROR("invalid kms\n");
  1991. return false;
  1992. }
  1993. sde_kms = to_sde_kms(kms);
  1994. return sde_kms->splash_data.num_splash_displays;
  1995. }
  1996. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  1997. const struct drm_display_mode *mode,
  1998. const struct msm_resource_caps_info *res, u32 *num_lm)
  1999. {
  2000. struct sde_kms *sde_kms;
  2001. s64 mode_clock_hz = 0;
  2002. s64 max_mdp_clock_hz = 0;
  2003. s64 mdp_fudge_factor = 0;
  2004. s64 temp = 0;
  2005. s64 htotal_fp = 0;
  2006. s64 vtotal_fp = 0;
  2007. s64 vrefresh_fp = 0;
  2008. if (!num_lm) {
  2009. SDE_ERROR("invalid num_lm pointer\n");
  2010. return -EINVAL;
  2011. }
  2012. *num_lm = 1;
  2013. if (!kms || !mode || !res) {
  2014. SDE_ERROR("invalid input args\n");
  2015. return -EINVAL;
  2016. }
  2017. sde_kms = to_sde_kms(kms);
  2018. max_mdp_clock_hz = drm_fixp_from_fraction(
  2019. sde_kms->perf.max_core_clk_rate, 1);
  2020. mdp_fudge_factor = drm_fixp_from_fraction(105, 100); /* 1.05 */
  2021. htotal_fp = drm_fixp_from_fraction(mode->htotal, 1);
  2022. vtotal_fp = drm_fixp_from_fraction(mode->vtotal, 1);
  2023. vrefresh_fp = drm_fixp_from_fraction(mode->vrefresh, 1);
  2024. temp = drm_fixp_mul(htotal_fp, vtotal_fp);
  2025. temp = drm_fixp_mul(temp, vrefresh_fp);
  2026. mode_clock_hz = drm_fixp_mul(temp, mdp_fudge_factor);
  2027. if (mode_clock_hz > max_mdp_clock_hz ||
  2028. mode->hdisplay > res->max_mixer_width) {
  2029. *num_lm = 2;
  2030. if ((mode_clock_hz >> 1) > max_mdp_clock_hz) {
  2031. SDE_DEBUG("[%s] clock %d exceeds max_mdp_clk %d\n",
  2032. mode->name, mode_clock_hz,
  2033. max_mdp_clock_hz);
  2034. return -EINVAL;
  2035. }
  2036. }
  2037. SDE_DEBUG("[%s] h=%d, v=%d, fps=%d, max_mdp_clk_hz=%llu, num_lm=%d\n",
  2038. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2039. sde_kms->perf.max_core_clk_rate, *num_lm);
  2040. return 0;
  2041. }
  2042. static void _sde_kms_null_commit(struct drm_device *dev,
  2043. struct drm_encoder *enc)
  2044. {
  2045. struct drm_modeset_acquire_ctx ctx;
  2046. struct drm_connector *conn = NULL;
  2047. struct drm_connector *tmp_conn = NULL;
  2048. struct drm_connector_list_iter conn_iter;
  2049. struct drm_atomic_state *state = NULL;
  2050. struct drm_crtc_state *crtc_state = NULL;
  2051. struct drm_connector_state *conn_state = NULL;
  2052. int retry_cnt = 0;
  2053. int ret = 0;
  2054. drm_modeset_acquire_init(&ctx, 0);
  2055. retry:
  2056. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2057. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2058. drm_modeset_backoff(&ctx);
  2059. retry_cnt++;
  2060. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2061. goto retry;
  2062. } else if (WARN_ON(ret)) {
  2063. goto end;
  2064. }
  2065. state = drm_atomic_state_alloc(dev);
  2066. if (!state) {
  2067. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2068. goto end;
  2069. }
  2070. state->acquire_ctx = &ctx;
  2071. drm_connector_list_iter_begin(dev, &conn_iter);
  2072. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2073. if (enc == tmp_conn->state->best_encoder) {
  2074. conn = tmp_conn;
  2075. break;
  2076. }
  2077. }
  2078. drm_connector_list_iter_end(&conn_iter);
  2079. if (!conn) {
  2080. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2081. goto end;
  2082. }
  2083. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2084. conn_state = drm_atomic_get_connector_state(state, conn);
  2085. if (IS_ERR(conn_state)) {
  2086. SDE_ERROR("error %d getting connector %d state\n",
  2087. ret, DRMID(conn));
  2088. goto end;
  2089. }
  2090. crtc_state->active = true;
  2091. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2092. if (ret)
  2093. SDE_ERROR("error %d setting the crtc\n", ret);
  2094. ret = drm_atomic_commit(state);
  2095. if (ret)
  2096. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2097. end:
  2098. if (state)
  2099. drm_atomic_state_put(state);
  2100. drm_modeset_drop_locks(&ctx);
  2101. drm_modeset_acquire_fini(&ctx);
  2102. }
  2103. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2104. struct device *dev)
  2105. {
  2106. int i, ret;
  2107. struct drm_device *ddev = dev_get_drvdata(dev);
  2108. struct drm_connector *conn;
  2109. struct drm_connector_list_iter conn_iter;
  2110. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2111. drm_connector_list_iter_begin(ddev, &conn_iter);
  2112. drm_for_each_connector_iter(conn, &conn_iter) {
  2113. uint64_t lp;
  2114. lp = sde_connector_get_lp(conn);
  2115. if (lp != SDE_MODE_DPMS_LP2)
  2116. continue;
  2117. ret = sde_encoder_wait_for_event(conn->encoder,
  2118. MSM_ENC_TX_COMPLETE);
  2119. if (ret && ret != -EWOULDBLOCK)
  2120. SDE_ERROR(
  2121. "[conn: %d] wait for commit done returned %d\n",
  2122. conn->base.id, ret);
  2123. else if (!ret)
  2124. sde_encoder_idle_request(conn->encoder);
  2125. }
  2126. drm_connector_list_iter_end(&conn_iter);
  2127. for (i = 0; i < priv->num_crtcs; i++) {
  2128. if (priv->disp_thread[i].thread)
  2129. kthread_flush_worker(
  2130. &priv->disp_thread[i].worker);
  2131. if (priv->event_thread[i].thread)
  2132. kthread_flush_worker(
  2133. &priv->event_thread[i].worker);
  2134. }
  2135. kthread_flush_worker(&priv->pp_event_worker);
  2136. }
  2137. static int sde_kms_pm_suspend(struct device *dev)
  2138. {
  2139. struct drm_device *ddev;
  2140. struct drm_modeset_acquire_ctx ctx;
  2141. struct drm_connector *conn;
  2142. struct drm_encoder *enc;
  2143. struct drm_connector_list_iter conn_iter;
  2144. struct drm_atomic_state *state = NULL;
  2145. struct sde_kms *sde_kms;
  2146. int ret = 0, num_crtcs = 0;
  2147. if (!dev)
  2148. return -EINVAL;
  2149. ddev = dev_get_drvdata(dev);
  2150. if (!ddev || !ddev_to_msm_kms(ddev))
  2151. return -EINVAL;
  2152. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2153. SDE_EVT32(0);
  2154. /* disable hot-plug polling */
  2155. drm_kms_helper_poll_disable(ddev);
  2156. /* if a display stuck in CS trigger a null commit to complete handoff */
  2157. drm_for_each_encoder(enc, ddev) {
  2158. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2159. _sde_kms_null_commit(ddev, enc);
  2160. }
  2161. /* acquire modeset lock(s) */
  2162. drm_modeset_acquire_init(&ctx, 0);
  2163. retry:
  2164. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2165. if (ret)
  2166. goto unlock;
  2167. /* save current state for resume */
  2168. if (sde_kms->suspend_state)
  2169. drm_atomic_state_put(sde_kms->suspend_state);
  2170. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2171. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2172. ret = PTR_ERR(sde_kms->suspend_state);
  2173. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2174. sde_kms->suspend_state = NULL;
  2175. goto unlock;
  2176. }
  2177. /* create atomic state to disable all CRTCs */
  2178. state = drm_atomic_state_alloc(ddev);
  2179. if (!state) {
  2180. ret = -ENOMEM;
  2181. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2182. goto unlock;
  2183. }
  2184. state->acquire_ctx = &ctx;
  2185. drm_connector_list_iter_begin(ddev, &conn_iter);
  2186. drm_for_each_connector_iter(conn, &conn_iter) {
  2187. struct drm_crtc_state *crtc_state;
  2188. uint64_t lp;
  2189. if (!conn->state || !conn->state->crtc ||
  2190. conn->dpms != DRM_MODE_DPMS_ON)
  2191. continue;
  2192. lp = sde_connector_get_lp(conn);
  2193. if (lp == SDE_MODE_DPMS_LP1) {
  2194. /* transition LP1->LP2 on pm suspend */
  2195. ret = sde_connector_set_property_for_commit(conn, state,
  2196. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2197. if (ret) {
  2198. DRM_ERROR("failed to set lp2 for conn %d\n",
  2199. conn->base.id);
  2200. drm_connector_list_iter_end(&conn_iter);
  2201. goto unlock;
  2202. }
  2203. }
  2204. if (lp != SDE_MODE_DPMS_LP2) {
  2205. /* force CRTC to be inactive */
  2206. crtc_state = drm_atomic_get_crtc_state(state,
  2207. conn->state->crtc);
  2208. if (IS_ERR_OR_NULL(crtc_state)) {
  2209. DRM_ERROR("failed to get crtc %d state\n",
  2210. conn->state->crtc->base.id);
  2211. drm_connector_list_iter_end(&conn_iter);
  2212. goto unlock;
  2213. }
  2214. if (lp != SDE_MODE_DPMS_LP1)
  2215. crtc_state->active = false;
  2216. ++num_crtcs;
  2217. }
  2218. }
  2219. drm_connector_list_iter_end(&conn_iter);
  2220. /* check for nothing to do */
  2221. if (num_crtcs == 0) {
  2222. DRM_DEBUG("all crtcs are already in the off state\n");
  2223. sde_kms->suspend_block = true;
  2224. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2225. goto unlock;
  2226. }
  2227. /* commit the "disable all" state */
  2228. ret = drm_atomic_commit(state);
  2229. if (ret < 0) {
  2230. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2231. goto unlock;
  2232. }
  2233. sde_kms->suspend_block = true;
  2234. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2235. unlock:
  2236. if (state) {
  2237. drm_atomic_state_put(state);
  2238. state = NULL;
  2239. }
  2240. if (ret == -EDEADLK) {
  2241. drm_modeset_backoff(&ctx);
  2242. goto retry;
  2243. }
  2244. drm_modeset_drop_locks(&ctx);
  2245. drm_modeset_acquire_fini(&ctx);
  2246. /*
  2247. * pm runtime driver avoids multiple runtime_suspend API call by
  2248. * checking runtime_status. However, this call helps when there is a
  2249. * race condition between pm_suspend call and doze_suspend/power_off
  2250. * commit. It removes the extra vote from suspend and adds it back
  2251. * later to allow power collapse during pm_suspend call
  2252. */
  2253. pm_runtime_put_sync(dev);
  2254. pm_runtime_get_noresume(dev);
  2255. return ret;
  2256. }
  2257. static int sde_kms_pm_resume(struct device *dev)
  2258. {
  2259. struct drm_device *ddev;
  2260. struct sde_kms *sde_kms;
  2261. struct drm_modeset_acquire_ctx ctx;
  2262. int ret, i;
  2263. if (!dev)
  2264. return -EINVAL;
  2265. ddev = dev_get_drvdata(dev);
  2266. if (!ddev || !ddev_to_msm_kms(ddev))
  2267. return -EINVAL;
  2268. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2269. SDE_EVT32(sde_kms->suspend_state != NULL);
  2270. drm_mode_config_reset(ddev);
  2271. drm_modeset_acquire_init(&ctx, 0);
  2272. retry:
  2273. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2274. if (ret == -EDEADLK) {
  2275. drm_modeset_backoff(&ctx);
  2276. goto retry;
  2277. } else if (WARN_ON(ret)) {
  2278. goto end;
  2279. }
  2280. sde_kms->suspend_block = false;
  2281. if (sde_kms->suspend_state) {
  2282. sde_kms->suspend_state->acquire_ctx = &ctx;
  2283. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2284. ret = drm_atomic_helper_commit_duplicated_state(
  2285. sde_kms->suspend_state, &ctx);
  2286. if (ret != -EDEADLK)
  2287. break;
  2288. drm_modeset_backoff(&ctx);
  2289. }
  2290. if (ret < 0)
  2291. DRM_ERROR("failed to restore state, %d\n", ret);
  2292. drm_atomic_state_put(sde_kms->suspend_state);
  2293. sde_kms->suspend_state = NULL;
  2294. }
  2295. end:
  2296. drm_modeset_drop_locks(&ctx);
  2297. drm_modeset_acquire_fini(&ctx);
  2298. /* enable hot-plug polling */
  2299. drm_kms_helper_poll_enable(ddev);
  2300. return 0;
  2301. }
  2302. static const struct msm_kms_funcs kms_funcs = {
  2303. .hw_init = sde_kms_hw_init,
  2304. .postinit = sde_kms_postinit,
  2305. .irq_preinstall = sde_irq_preinstall,
  2306. .irq_postinstall = sde_irq_postinstall,
  2307. .irq_uninstall = sde_irq_uninstall,
  2308. .irq = sde_irq,
  2309. .lastclose = sde_kms_lastclose,
  2310. .prepare_fence = sde_kms_prepare_fence,
  2311. .prepare_commit = sde_kms_prepare_commit,
  2312. .commit = sde_kms_commit,
  2313. .complete_commit = sde_kms_complete_commit,
  2314. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2315. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2316. .enable_vblank = sde_kms_enable_vblank,
  2317. .disable_vblank = sde_kms_disable_vblank,
  2318. .check_modified_format = sde_format_check_modified_format,
  2319. .atomic_check = sde_kms_atomic_check,
  2320. .get_format = sde_get_msm_format,
  2321. .round_pixclk = sde_kms_round_pixclk,
  2322. .pm_suspend = sde_kms_pm_suspend,
  2323. .pm_resume = sde_kms_pm_resume,
  2324. .destroy = sde_kms_destroy,
  2325. .cont_splash_config = sde_kms_cont_splash_config,
  2326. .register_events = _sde_kms_register_events,
  2327. .get_address_space = _sde_kms_get_address_space,
  2328. .get_address_space_device = _sde_kms_get_address_space_device,
  2329. .postopen = _sde_kms_post_open,
  2330. .check_for_splash = sde_kms_check_for_splash,
  2331. .get_mixer_count = sde_kms_get_mixer_count,
  2332. };
  2333. /* the caller api needs to turn on clock before calling it */
  2334. static inline void _sde_kms_core_hw_rev_init(struct sde_kms *sde_kms)
  2335. {
  2336. sde_kms->core_rev = readl_relaxed(sde_kms->mmio + 0x0);
  2337. }
  2338. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2339. {
  2340. int i;
  2341. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2342. if (!sde_kms->aspace[i])
  2343. continue;
  2344. msm_gem_address_space_put(sde_kms->aspace[i]);
  2345. sde_kms->aspace[i] = NULL;
  2346. }
  2347. return 0;
  2348. }
  2349. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2350. {
  2351. struct msm_mmu *mmu;
  2352. int i, ret;
  2353. int early_map = 0;
  2354. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  2355. return -EINVAL;
  2356. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2357. struct msm_gem_address_space *aspace;
  2358. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2359. if (IS_ERR(mmu)) {
  2360. ret = PTR_ERR(mmu);
  2361. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2362. i, ret);
  2363. continue;
  2364. }
  2365. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2366. mmu, "sde");
  2367. if (IS_ERR(aspace)) {
  2368. ret = PTR_ERR(aspace);
  2369. goto fail;
  2370. }
  2371. sde_kms->aspace[i] = aspace;
  2372. aspace->domain_attached = true;
  2373. /* Mapping splash memory block */
  2374. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2375. sde_kms->splash_data.num_splash_regions) {
  2376. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2377. if (ret) {
  2378. SDE_ERROR("failed to map ret:%d\n", ret);
  2379. goto fail;
  2380. }
  2381. }
  2382. /*
  2383. * disable early-map which would have been enabled during
  2384. * bootup by smmu through the device-tree hint for cont-spash
  2385. */
  2386. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2387. &early_map);
  2388. if (ret) {
  2389. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2390. ret, early_map);
  2391. goto early_map_fail;
  2392. }
  2393. }
  2394. return 0;
  2395. early_map_fail:
  2396. _sde_kms_unmap_all_splash_regions(sde_kms);
  2397. fail:
  2398. mmu->funcs->destroy(mmu);
  2399. _sde_kms_mmu_destroy(sde_kms);
  2400. return ret;
  2401. }
  2402. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2403. {
  2404. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2405. return;
  2406. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2407. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2408. sde_kms->catalog);
  2409. if (sde_kms->sid)
  2410. sde_hw_sid_rotator_set(sde_kms->hw_sid);
  2411. }
  2412. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2413. {
  2414. struct sde_vbif_set_qos_params qos_params;
  2415. struct sde_mdss_cfg *catalog;
  2416. if (!sde_kms->catalog)
  2417. return;
  2418. catalog = sde_kms->catalog;
  2419. memset(&qos_params, 0, sizeof(qos_params));
  2420. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2421. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2422. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2423. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2424. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2425. }
  2426. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  2427. {
  2428. struct sde_hw_uidle *uidle;
  2429. if (!sde_kms) {
  2430. SDE_ERROR("invalid kms\n");
  2431. return -EINVAL;
  2432. }
  2433. uidle = sde_kms->hw_uidle;
  2434. if (uidle && uidle->ops.active_override_enable)
  2435. uidle->ops.active_override_enable(uidle, enable);
  2436. return 0;
  2437. }
  2438. static void sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  2439. {
  2440. struct device *cpu_dev;
  2441. int cpu = 0;
  2442. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2443. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2444. return;
  2445. }
  2446. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2447. cpu_dev = get_cpu_device(cpu);
  2448. if (!cpu_dev) {
  2449. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2450. cpu);
  2451. continue;
  2452. }
  2453. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2454. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  2455. sde_kms->catalog->perf.cpu_dma_latency);
  2456. else
  2457. dev_pm_qos_add_request(cpu_dev,
  2458. &sde_kms->pm_qos_irq_req[cpu],
  2459. DEV_PM_QOS_RESUME_LATENCY,
  2460. sde_kms->catalog->perf.cpu_dma_latency);
  2461. }
  2462. }
  2463. static void sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  2464. {
  2465. struct device *cpu_dev;
  2466. int cpu = 0;
  2467. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2468. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2469. return;
  2470. }
  2471. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2472. cpu_dev = get_cpu_device(cpu);
  2473. if (!cpu_dev) {
  2474. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2475. cpu);
  2476. continue;
  2477. }
  2478. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2479. dev_pm_qos_remove_request(
  2480. &sde_kms->pm_qos_irq_req[cpu]);
  2481. }
  2482. }
  2483. static void sde_kms_irq_affinity_notify(
  2484. struct irq_affinity_notify *affinity_notify,
  2485. const cpumask_t *mask)
  2486. {
  2487. struct msm_drm_private *priv;
  2488. struct sde_kms *sde_kms = container_of(affinity_notify,
  2489. struct sde_kms, affinity_notify);
  2490. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  2491. return;
  2492. priv = sde_kms->dev->dev_private;
  2493. mutex_lock(&priv->phandle.phandle_lock);
  2494. // save irq cpu mask
  2495. sde_kms->irq_cpu_mask = *mask;
  2496. // request vote with updated irq cpu mask
  2497. if (sde_kms->irq_enabled)
  2498. sde_kms_update_pm_qos_irq_request(sde_kms);
  2499. mutex_unlock(&priv->phandle.phandle_lock);
  2500. }
  2501. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  2502. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  2503. {
  2504. struct sde_kms *sde_kms = usr;
  2505. struct msm_kms *msm_kms;
  2506. msm_kms = &sde_kms->base;
  2507. if (!sde_kms)
  2508. return;
  2509. SDE_DEBUG("event_type:%d\n", event_type);
  2510. SDE_EVT32_VERBOSE(event_type);
  2511. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  2512. sde_irq_update(msm_kms, true);
  2513. sde_vbif_init_memtypes(sde_kms);
  2514. sde_kms_init_shared_hw(sde_kms);
  2515. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  2516. sde_kms->first_kickoff = true;
  2517. sde_kms_update_pm_qos_irq_request(sde_kms);
  2518. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  2519. sde_kms_remove_pm_qos_irq_request(sde_kms);
  2520. sde_irq_update(msm_kms, false);
  2521. sde_kms->first_kickoff = false;
  2522. _sde_kms_active_override(sde_kms, true);
  2523. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  2524. sde_vbif_axi_halt_request(sde_kms);
  2525. }
  2526. }
  2527. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  2528. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  2529. {
  2530. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2531. int rc = -EINVAL;
  2532. SDE_DEBUG("\n");
  2533. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2534. if (rc > 0)
  2535. rc = 0;
  2536. SDE_EVT32(rc, genpd->device_count);
  2537. return rc;
  2538. }
  2539. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  2540. {
  2541. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2542. SDE_DEBUG("\n");
  2543. pm_runtime_put_sync(sde_kms->dev->dev);
  2544. SDE_EVT32(genpd->device_count);
  2545. return 0;
  2546. }
  2547. static int _sde_kms_get_splash_data(struct sde_splash_data *data)
  2548. {
  2549. int i = 0;
  2550. int ret = 0;
  2551. struct device_node *parent, *node, *node1;
  2552. struct resource r, r1;
  2553. const char *node_name = "cont_splash_region";
  2554. struct sde_splash_mem *mem;
  2555. bool share_splash_mem = false;
  2556. int num_displays, num_regions;
  2557. struct sde_splash_display *splash_display;
  2558. if (!data)
  2559. return -EINVAL;
  2560. memset(data, 0, sizeof(*data));
  2561. parent = of_find_node_by_path("/reserved-memory");
  2562. if (!parent) {
  2563. SDE_ERROR("failed to find reserved-memory node\n");
  2564. return -EINVAL;
  2565. }
  2566. node = of_find_node_by_name(parent, node_name);
  2567. if (!node) {
  2568. SDE_DEBUG("failed to find node %s\n", node_name);
  2569. return -EINVAL;
  2570. }
  2571. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  2572. if (!node1)
  2573. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  2574. /**
  2575. * Support sharing a single splash memory for all the built in displays
  2576. * and also independent splash region per displays. Incase of
  2577. * independent splash region for each connected display, dtsi node of
  2578. * cont_splash_region should be collection of all memory regions
  2579. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  2580. */
  2581. num_displays = dsi_display_get_num_of_displays();
  2582. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  2583. data->num_splash_displays = num_displays;
  2584. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  2585. if (num_displays > num_regions) {
  2586. share_splash_mem = true;
  2587. pr_info(":%d displays share same splash buf\n", num_displays);
  2588. }
  2589. for (i = 0; i < num_displays; i++) {
  2590. splash_display = &data->splash_display[i];
  2591. if (!i || !share_splash_mem) {
  2592. if (of_address_to_resource(node, i, &r)) {
  2593. SDE_ERROR("invalid data for:%s\n", node_name);
  2594. return -EINVAL;
  2595. }
  2596. mem = &data->splash_mem[i];
  2597. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  2598. SDE_DEBUG("failed to find ramdump memory\n");
  2599. mem->ramdump_base = 0;
  2600. mem->ramdump_size = 0;
  2601. } else {
  2602. mem->ramdump_base = (unsigned long)r1.start;
  2603. mem->ramdump_size = (r1.end - r1.start) + 1;
  2604. }
  2605. mem->splash_buf_base = (unsigned long)r.start;
  2606. mem->splash_buf_size = (r.end - r.start) + 1;
  2607. mem->ref_cnt = 0;
  2608. splash_display->splash = mem;
  2609. data->num_splash_regions++;
  2610. } else {
  2611. data->splash_display[i].splash = &data->splash_mem[0];
  2612. }
  2613. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  2614. splash_display->splash->splash_buf_base,
  2615. splash_display->splash->splash_buf_size);
  2616. }
  2617. return ret;
  2618. }
  2619. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  2620. struct platform_device *platformdev)
  2621. {
  2622. int rc = -EINVAL;
  2623. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  2624. if (IS_ERR(sde_kms->mmio)) {
  2625. rc = PTR_ERR(sde_kms->mmio);
  2626. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  2627. sde_kms->mmio = NULL;
  2628. goto error;
  2629. }
  2630. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  2631. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  2632. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  2633. sde_kms->mmio_len);
  2634. if (rc)
  2635. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  2636. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  2637. "vbif_phys");
  2638. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  2639. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  2640. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  2641. sde_kms->vbif[VBIF_RT] = NULL;
  2642. goto error;
  2643. }
  2644. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  2645. "vbif_phys");
  2646. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  2647. sde_kms->vbif_len[VBIF_RT]);
  2648. if (rc)
  2649. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  2650. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  2651. "vbif_nrt_phys");
  2652. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  2653. sde_kms->vbif[VBIF_NRT] = NULL;
  2654. SDE_DEBUG("VBIF NRT is not defined");
  2655. } else {
  2656. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  2657. "vbif_nrt_phys");
  2658. rc = sde_dbg_reg_register_base("vbif_nrt",
  2659. sde_kms->vbif[VBIF_NRT],
  2660. sde_kms->vbif_len[VBIF_NRT]);
  2661. if (rc)
  2662. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  2663. rc);
  2664. }
  2665. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  2666. "regdma_phys");
  2667. if (IS_ERR(sde_kms->reg_dma)) {
  2668. sde_kms->reg_dma = NULL;
  2669. SDE_DEBUG("REG_DMA is not defined");
  2670. } else {
  2671. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  2672. "regdma_phys");
  2673. rc = sde_dbg_reg_register_base("reg_dma",
  2674. sde_kms->reg_dma,
  2675. sde_kms->reg_dma_len);
  2676. if (rc)
  2677. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  2678. rc);
  2679. }
  2680. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  2681. "sid_phys");
  2682. if (IS_ERR(sde_kms->sid)) {
  2683. SDE_DEBUG("sid register is not defined: %d\n", rc);
  2684. sde_kms->sid = NULL;
  2685. } else {
  2686. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  2687. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  2688. sde_kms->sid_len);
  2689. if (rc)
  2690. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  2691. }
  2692. error:
  2693. return rc;
  2694. }
  2695. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  2696. struct sde_kms *sde_kms)
  2697. {
  2698. int rc = 0;
  2699. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  2700. sde_kms->genpd.name = dev->unique;
  2701. sde_kms->genpd.power_off = sde_kms_pd_disable;
  2702. sde_kms->genpd.power_on = sde_kms_pd_enable;
  2703. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  2704. if (rc < 0) {
  2705. SDE_ERROR("failed to init genpd provider %s: %d\n",
  2706. sde_kms->genpd.name, rc);
  2707. return rc;
  2708. }
  2709. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  2710. &sde_kms->genpd);
  2711. if (rc < 0) {
  2712. SDE_ERROR("failed to add genpd provider %s: %d\n",
  2713. sde_kms->genpd.name, rc);
  2714. pm_genpd_remove(&sde_kms->genpd);
  2715. return rc;
  2716. }
  2717. sde_kms->genpd_init = true;
  2718. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  2719. }
  2720. return rc;
  2721. }
  2722. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  2723. struct drm_device *dev,
  2724. struct msm_drm_private *priv)
  2725. {
  2726. struct sde_rm *rm = NULL;
  2727. int i, rc = -EINVAL;
  2728. _sde_kms_core_hw_rev_init(sde_kms);
  2729. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  2730. sde_kms->catalog = sde_hw_catalog_init(dev, sde_kms->core_rev);
  2731. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  2732. rc = PTR_ERR(sde_kms->catalog);
  2733. if (!sde_kms->catalog)
  2734. rc = -EINVAL;
  2735. SDE_ERROR("catalog init failed: %d\n", rc);
  2736. sde_kms->catalog = NULL;
  2737. goto power_error;
  2738. }
  2739. /* initialize power domain if defined */
  2740. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  2741. if (rc) {
  2742. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  2743. goto genpd_err;
  2744. }
  2745. rc = _sde_kms_mmu_init(sde_kms);
  2746. if (rc) {
  2747. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  2748. goto power_error;
  2749. }
  2750. /* Initialize reg dma block which is a singleton */
  2751. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  2752. sde_kms->dev);
  2753. if (rc) {
  2754. SDE_ERROR("failed: reg dma init failed\n");
  2755. goto power_error;
  2756. }
  2757. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  2758. rm = &sde_kms->rm;
  2759. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  2760. sde_kms->dev);
  2761. if (rc) {
  2762. SDE_ERROR("rm init failed: %d\n", rc);
  2763. goto power_error;
  2764. }
  2765. sde_kms->rm_init = true;
  2766. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  2767. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  2768. rc = PTR_ERR(sde_kms->hw_intr);
  2769. SDE_ERROR("hw_intr init failed: %d\n", rc);
  2770. sde_kms->hw_intr = NULL;
  2771. goto hw_intr_init_err;
  2772. }
  2773. /*
  2774. * Attempt continuous splash handoff only if reserved
  2775. * splash memory is found & release resources on any error
  2776. * in finding display hw config in splash
  2777. */
  2778. if (sde_kms->splash_data.num_splash_regions) {
  2779. struct sde_splash_display *display;
  2780. int ret, display_count =
  2781. sde_kms->splash_data.num_splash_displays;
  2782. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  2783. &sde_kms->splash_data, sde_kms->catalog);
  2784. for (i = 0; i < display_count; i++) {
  2785. display = &sde_kms->splash_data.splash_display[i];
  2786. /*
  2787. * free splash region on resource init failure and
  2788. * cont-splash disabled case
  2789. */
  2790. if (!display->cont_splash_enabled || ret)
  2791. _sde_kms_free_splash_region(sde_kms, display);
  2792. }
  2793. }
  2794. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  2795. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  2796. rc = PTR_ERR(sde_kms->hw_mdp);
  2797. if (!sde_kms->hw_mdp)
  2798. rc = -EINVAL;
  2799. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  2800. sde_kms->hw_mdp = NULL;
  2801. goto power_error;
  2802. }
  2803. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  2804. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  2805. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  2806. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  2807. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  2808. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  2809. if (!sde_kms->hw_vbif[vbif_idx])
  2810. rc = -EINVAL;
  2811. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  2812. sde_kms->hw_vbif[vbif_idx] = NULL;
  2813. goto power_error;
  2814. }
  2815. }
  2816. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  2817. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  2818. sde_kms->mmio_len, sde_kms->catalog);
  2819. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  2820. rc = PTR_ERR(sde_kms->hw_uidle);
  2821. if (!sde_kms->hw_uidle)
  2822. rc = -EINVAL;
  2823. /* uidle is optional, so do not make it a fatal error */
  2824. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  2825. sde_kms->hw_uidle = NULL;
  2826. rc = 0;
  2827. }
  2828. } else {
  2829. sde_kms->hw_uidle = NULL;
  2830. }
  2831. if (sde_kms->sid) {
  2832. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  2833. sde_kms->sid_len, sde_kms->catalog);
  2834. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  2835. rc = PTR_ERR(sde_kms->hw_sid);
  2836. SDE_ERROR("failed to init sid %ld\n", rc);
  2837. sde_kms->hw_sid = NULL;
  2838. goto power_error;
  2839. }
  2840. }
  2841. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  2842. &priv->phandle, "core_clk");
  2843. if (rc) {
  2844. SDE_ERROR("failed to init perf %d\n", rc);
  2845. goto perf_err;
  2846. }
  2847. /*
  2848. * _sde_kms_drm_obj_init should create the DRM related objects
  2849. * i.e. CRTCs, planes, encoders, connectors and so forth
  2850. */
  2851. rc = _sde_kms_drm_obj_init(sde_kms);
  2852. if (rc) {
  2853. SDE_ERROR("modeset init failed: %d\n", rc);
  2854. goto drm_obj_init_err;
  2855. }
  2856. return 0;
  2857. genpd_err:
  2858. drm_obj_init_err:
  2859. sde_core_perf_destroy(&sde_kms->perf);
  2860. hw_intr_init_err:
  2861. perf_err:
  2862. power_error:
  2863. return rc;
  2864. }
  2865. static int sde_kms_hw_init(struct msm_kms *kms)
  2866. {
  2867. struct sde_kms *sde_kms;
  2868. struct drm_device *dev;
  2869. struct msm_drm_private *priv;
  2870. struct platform_device *platformdev;
  2871. int i, irq_num, rc = -EINVAL;
  2872. if (!kms) {
  2873. SDE_ERROR("invalid kms\n");
  2874. goto end;
  2875. }
  2876. sde_kms = to_sde_kms(kms);
  2877. dev = sde_kms->dev;
  2878. if (!dev || !dev->dev) {
  2879. SDE_ERROR("invalid device\n");
  2880. goto end;
  2881. }
  2882. platformdev = to_platform_device(dev->dev);
  2883. priv = dev->dev_private;
  2884. if (!priv) {
  2885. SDE_ERROR("invalid private data\n");
  2886. goto end;
  2887. }
  2888. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  2889. if (rc)
  2890. goto error;
  2891. rc = _sde_kms_get_splash_data(&sde_kms->splash_data);
  2892. if (rc)
  2893. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  2894. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2895. if (rc < 0) {
  2896. SDE_ERROR("resource enable failed: %d\n", rc);
  2897. goto error;
  2898. }
  2899. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  2900. if (rc)
  2901. goto hw_init_err;
  2902. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  2903. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  2904. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  2905. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  2906. mutex_init(&sde_kms->secure_transition_lock);
  2907. atomic_set(&sde_kms->detach_sec_cb, 0);
  2908. atomic_set(&sde_kms->detach_all_cb, 0);
  2909. /*
  2910. * Support format modifiers for compression etc.
  2911. */
  2912. dev->mode_config.allow_fb_modifiers = true;
  2913. /*
  2914. * Handle (re)initializations during power enable
  2915. */
  2916. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  2917. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  2918. SDE_POWER_EVENT_POST_ENABLE |
  2919. SDE_POWER_EVENT_PRE_DISABLE,
  2920. sde_kms_handle_power_event, sde_kms, "kms");
  2921. if (sde_kms->splash_data.num_splash_displays) {
  2922. SDE_DEBUG("Skipping MDP Resources disable\n");
  2923. } else {
  2924. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  2925. sde_power_data_bus_set_quota(&priv->phandle, i,
  2926. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  2927. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  2928. pm_runtime_put_sync(sde_kms->dev->dev);
  2929. }
  2930. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  2931. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  2932. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  2933. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  2934. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  2935. return 0;
  2936. hw_init_err:
  2937. pm_runtime_put_sync(sde_kms->dev->dev);
  2938. error:
  2939. _sde_kms_hw_destroy(sde_kms, platformdev);
  2940. end:
  2941. return rc;
  2942. }
  2943. struct msm_kms *sde_kms_init(struct drm_device *dev)
  2944. {
  2945. struct msm_drm_private *priv;
  2946. struct sde_kms *sde_kms;
  2947. if (!dev || !dev->dev_private) {
  2948. SDE_ERROR("drm device node invalid\n");
  2949. return ERR_PTR(-EINVAL);
  2950. }
  2951. priv = dev->dev_private;
  2952. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  2953. if (!sde_kms) {
  2954. SDE_ERROR("failed to allocate sde kms\n");
  2955. return ERR_PTR(-ENOMEM);
  2956. }
  2957. msm_kms_init(&sde_kms->base, &kms_funcs);
  2958. sde_kms->dev = dev;
  2959. return &sde_kms->base;
  2960. }
  2961. static int _sde_kms_register_events(struct msm_kms *kms,
  2962. struct drm_mode_object *obj, u32 event, bool en)
  2963. {
  2964. int ret = 0;
  2965. struct drm_crtc *crtc = NULL;
  2966. struct drm_connector *conn = NULL;
  2967. struct sde_kms *sde_kms = NULL;
  2968. if (!kms || !obj) {
  2969. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  2970. return -EINVAL;
  2971. }
  2972. sde_kms = to_sde_kms(kms);
  2973. switch (obj->type) {
  2974. case DRM_MODE_OBJECT_CRTC:
  2975. crtc = obj_to_crtc(obj);
  2976. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  2977. break;
  2978. case DRM_MODE_OBJECT_CONNECTOR:
  2979. conn = obj_to_connector(obj);
  2980. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  2981. en);
  2982. break;
  2983. }
  2984. return ret;
  2985. }
  2986. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  2987. {
  2988. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  2989. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  2990. }