wcd939x.c 164 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <linux/stringify.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include <soc/soundwire.h>
  18. #include <linux/regmap.h>
  19. #include <sound/soc.h>
  20. #include <sound/soc-dapm.h>
  21. #include <asoc/wcdcal-hwdep.h>
  22. #include <asoc/msm-cdc-pinctrl.h>
  23. #include <asoc/msm-cdc-supply.h>
  24. #include <asoc/wcd-mbhc-v2-api.h>
  25. #include <bindings/audio-codec-port-types.h>
  26. #include <linux/qti-regmap-debugfs.h>
  27. #include "wcd939x-registers.h"
  28. #include "wcd939x.h"
  29. #include "internal.h"
  30. #include "asoc/bolero-slave-internal.h"
  31. #include "wcd939x-reg-masks.h"
  32. #include "wcd939x-reg-shifts.h"
  33. #if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
  34. #include <linux/soc/qcom/wcd939x-i2c.h>
  35. #endif
  36. #define NUM_SWRS_DT_PARAMS 5
  37. #define WCD939X_VARIANT_ENTRY_SIZE 32
  38. #define WCD939X_VERSION_ENTRY_SIZE 32
  39. #define ADC_MODE_VAL_HIFI 0x01
  40. #define ADC_MODE_VAL_LO_HIF 0x02
  41. #define ADC_MODE_VAL_NORMAL 0x03
  42. #define ADC_MODE_VAL_LP 0x05
  43. #define ADC_MODE_VAL_ULP1 0x09
  44. #define ADC_MODE_VAL_ULP2 0x0B
  45. #define HPH_IMPEDANCE_2VPK_MODE_OHMS 260
  46. #define XTALK_L_CH_NUM 0
  47. #define XTALK_R_CH_NUM 1
  48. #define NUM_ATTEMPTS 5
  49. #define COMP_MAX_COEFF 25
  50. #define HPH_MODE_MAX 4
  51. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  52. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  53. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  54. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  55. #define WCD939X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  56. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  57. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  58. SNDRV_PCM_RATE_384000)
  59. /* Fractional Rates */
  60. #define WCD939X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  61. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  62. #define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  63. SNDRV_PCM_FMTBIT_S24_LE |\
  64. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  65. #define REG_FIELD_VALUE(register_name, field_name, value) \
  66. WCD939X_##register_name, FIELD_MASK(register_name, field_name), \
  67. value << FIELD_SHIFT(register_name, field_name)
  68. #define WCD939X_COMP_OFFSET \
  69. (WCD939X_R_BASE - WCD939X_COMPANDER_HPHL_BASE)
  70. #define WCD939X_XTALK_OFFSET \
  71. (WCD939X_HPHR_RX_PATH_SEC0 - WCD939X_HPHL_RX_PATH_SEC0)
  72. enum {
  73. CODEC_TX = 0,
  74. CODEC_RX,
  75. };
  76. enum {
  77. WCD_ADC1 = 0,
  78. WCD_ADC2,
  79. WCD_ADC3,
  80. WCD_ADC4,
  81. ALLOW_BUCK_DISABLE,
  82. HPH_COMP_DELAY,
  83. HPH_PA_DELAY,
  84. AMIC2_BCS_ENABLE,
  85. WCD_SUPPLIES_LPM_MODE,
  86. WCD_ADC1_MODE,
  87. WCD_ADC2_MODE,
  88. WCD_ADC3_MODE,
  89. WCD_ADC4_MODE,
  90. };
  91. enum {
  92. ADC_MODE_INVALID = 0,
  93. ADC_MODE_HIFI,
  94. ADC_MODE_LO_HIF,
  95. ADC_MODE_NORMAL,
  96. ADC_MODE_LP,
  97. ADC_MODE_ULP1,
  98. ADC_MODE_ULP2,
  99. };
  100. enum {
  101. SUPPLY_LEVEL_2VPK,
  102. REGULATOR_MODE_2VPK,
  103. SET_HPH_GAIN_2VPK,
  104. };
  105. static u8 tx_mode_bit[] = {
  106. [ADC_MODE_INVALID] = 0x00,
  107. [ADC_MODE_HIFI] = 0x01,
  108. [ADC_MODE_LO_HIF] = 0x02,
  109. [ADC_MODE_NORMAL] = 0x04,
  110. [ADC_MODE_LP] = 0x08,
  111. [ADC_MODE_ULP1] = 0x10,
  112. [ADC_MODE_ULP2] = 0x20,
  113. };
  114. extern const u8 wcd939x_reg_access[WCD939X_NUM_REGISTERS];
  115. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(hph_analog_gain, 600, -3000);
  116. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  117. /* Will be set by reading the registers during bind()*/
  118. static int wcd939x_version = WCD939X_VERSION_2_0;
  119. static int wcd939x_handle_post_irq(void *data);
  120. static int wcd939x_reset(struct device *dev);
  121. static int wcd939x_reset_low(struct device *dev);
  122. static int wcd939x_get_adc_mode(int val);
  123. static void wcd939x_config_2Vpk_mode(struct snd_soc_component *component,
  124. struct wcd939x_priv *wcd939x, int mode_2vpk);
  125. static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = {
  126. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  127. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  128. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  129. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  130. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10),
  131. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20),
  132. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40),
  133. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80),
  134. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01),
  135. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02),
  136. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04),
  137. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  138. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  139. REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80),
  140. REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  141. REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  142. REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  143. };
  144. static struct regmap_irq_chip wcd939x_regmap_irq_chip = {
  145. .name = "wcd939x",
  146. .irqs = wcd939x_irqs,
  147. .num_irqs = ARRAY_SIZE(wcd939x_irqs),
  148. .num_regs = 3,
  149. .status_base = WCD939X_INTR_STATUS_0,
  150. .mask_base = WCD939X_INTR_MASK_0,
  151. .type_base = WCD939X_INTR_LEVEL_0,
  152. .ack_base = WCD939X_INTR_CLEAR_0,
  153. .use_ack = 1,
  154. .runtime_pm = false,
  155. .handle_post_irq = wcd939x_handle_post_irq,
  156. .irq_drv_data = NULL,
  157. };
  158. static bool wcd939x_readable_register(struct device *dev, unsigned int reg)
  159. {
  160. if (reg <= WCD939X_BASE + 1)
  161. return 0;
  162. if (reg >= WCD939X_FLYBACK_NEW_CTRL_2 && reg <= WCD939X_FLYBACK_NEW_CTRL_4) {
  163. if (wcd939x_version == WCD939X_VERSION_1_0)
  164. return 0;
  165. }
  166. return wcd939x_reg_access[WCD939X_REG(reg)] & RD_REG;
  167. }
  168. static int wcd939x_handle_post_irq(void *data)
  169. {
  170. struct wcd939x_priv *wcd939x = data;
  171. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  172. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_0, &sts1);
  173. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_1, &sts2);
  174. regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_2, &sts3);
  175. wcd939x->tx_swr_dev->slave_irq_pending =
  176. ((sts1 || sts2 || sts3) ? true : false);
  177. return IRQ_HANDLED;
  178. }
  179. static int wcd939x_hph_compander_get(struct snd_kcontrol *kcontrol,
  180. struct snd_ctl_elem_value *ucontrol)
  181. {
  182. struct snd_soc_component *component =
  183. snd_soc_kcontrol_component(kcontrol);
  184. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  185. int compander = ((struct soc_multi_mixer_control *)
  186. kcontrol->private_value)->shift;
  187. ucontrol->value.integer.value[0] = wcd939x->compander_enabled[compander];
  188. return 0;
  189. }
  190. static int wcd939x_hph_compander_put(struct snd_kcontrol *kcontrol,
  191. struct snd_ctl_elem_value *ucontrol)
  192. {
  193. struct snd_soc_component *component =
  194. snd_soc_kcontrol_component(kcontrol);
  195. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  196. int compander = ((struct soc_multi_mixer_control *)
  197. kcontrol->private_value)->shift;
  198. int value = ucontrol->value.integer.value[0];
  199. if (value < WCD939X_HPH_MAX && value >= 0)
  200. wcd939x->compander_enabled[compander] = value;
  201. else {
  202. dev_err(component->dev, "%s: Invalid comp value = %d\n", __func__, value);
  203. return -EINVAL;
  204. }
  205. dev_dbg(component->dev, "%s: Compander %d value %d\n",
  206. __func__, wcd939x->compander_enabled[compander], value);
  207. return 0;
  208. }
  209. static int wcd939x_hph_xtalk_put(struct snd_kcontrol *kcontrol,
  210. struct snd_ctl_elem_value *ucontrol)
  211. {
  212. struct snd_soc_component *component =
  213. snd_soc_kcontrol_component(kcontrol);
  214. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  215. int xtalk = ((struct soc_multi_mixer_control *)
  216. kcontrol->private_value)->shift;
  217. int value = ucontrol->value.integer.value[0];
  218. if (value < WCD939X_HPH_MAX && value >= 0)
  219. wcd939x->xtalk_enabled[xtalk] = value;
  220. else {
  221. dev_err(component->dev, "%s: Invalid xtalk value = %d\n", __func__, value);
  222. return -EINVAL;
  223. }
  224. dev_dbg(component->dev, "%s: xtalk %d value %d\n",
  225. __func__, wcd939x->xtalk_enabled[xtalk], value);
  226. return 0;
  227. }
  228. static int wcd939x_hph_xtalk_get(struct snd_kcontrol *kcontrol,
  229. struct snd_ctl_elem_value *ucontrol)
  230. {
  231. struct snd_soc_component *component =
  232. snd_soc_kcontrol_component(kcontrol);
  233. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  234. int xtalk = ((struct soc_multi_mixer_control *)
  235. kcontrol->private_value)->shift;
  236. ucontrol->value.integer.value[0] = wcd939x->xtalk_enabled[xtalk];
  237. return 0;
  238. }
  239. static int wcd939x_hph_pcm_enable_put(struct snd_kcontrol *kcontrol,
  240. struct snd_ctl_elem_value *ucontrol)
  241. {
  242. struct snd_soc_component *component =
  243. snd_soc_kcontrol_component(kcontrol);
  244. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  245. wcd939x->hph_pcm_enabled = ucontrol->value.integer.value[0];
  246. dev_dbg(component->dev, "%s: pcm enabled %d \n",
  247. __func__, wcd939x->hph_pcm_enabled);
  248. return 0;
  249. }
  250. static int wcd939x_hph_pcm_enable_get(struct snd_kcontrol *kcontrol,
  251. struct snd_ctl_elem_value *ucontrol)
  252. {
  253. struct snd_soc_component *component =
  254. snd_soc_kcontrol_component(kcontrol);
  255. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  256. ucontrol->value.integer.value[0] = wcd939x->hph_pcm_enabled;
  257. return 0;
  258. }
  259. static int wcd939x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  260. {
  261. int ret = 0;
  262. int bank = 0;
  263. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  264. if (ret)
  265. return -EINVAL;
  266. return ((bank & 0x40) ? 1: 0);
  267. }
  268. static int wcd939x_get_clk_rate(int mode)
  269. {
  270. int rate;
  271. switch (mode) {
  272. case ADC_MODE_ULP2:
  273. rate = SWR_CLK_RATE_0P6MHZ;
  274. break;
  275. case ADC_MODE_ULP1:
  276. rate = SWR_CLK_RATE_1P2MHZ;
  277. break;
  278. case ADC_MODE_LP:
  279. rate = SWR_CLK_RATE_4P8MHZ;
  280. break;
  281. case ADC_MODE_NORMAL:
  282. case ADC_MODE_LO_HIF:
  283. case ADC_MODE_HIFI:
  284. case ADC_MODE_INVALID:
  285. default:
  286. rate = SWR_CLK_RATE_9P6MHZ;
  287. break;
  288. }
  289. return rate;
  290. }
  291. static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component,
  292. int rate, int bank)
  293. {
  294. u8 mask = (bank ? 0xF0 : 0x0F);
  295. u8 val = 0;
  296. switch (rate) {
  297. case SWR_CLK_RATE_0P6MHZ:
  298. val = (bank ? 0x60 : 0x06);
  299. break;
  300. case SWR_CLK_RATE_1P2MHZ:
  301. val = (bank ? 0x50 : 0x05);
  302. break;
  303. case SWR_CLK_RATE_2P4MHZ:
  304. val = (bank ? 0x30 : 0x03);
  305. break;
  306. case SWR_CLK_RATE_4P8MHZ:
  307. val = (bank ? 0x10 : 0x01);
  308. break;
  309. case SWR_CLK_RATE_9P6MHZ:
  310. default:
  311. val = 0x00;
  312. break;
  313. }
  314. snd_soc_component_update_bits(component,
  315. WCD939X_SWR_TX_CLK_RATE,
  316. mask, val);
  317. return 0;
  318. }
  319. static int wcd939x_init_reg(struct snd_soc_component *component)
  320. {
  321. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  322. snd_soc_component_update_bits(component,
  323. REG_FIELD_VALUE(BIAS, ANALOG_BIAS_EN, 0x01));
  324. snd_soc_component_update_bits(component,
  325. REG_FIELD_VALUE(BIAS, PRECHRG_EN, 0x01));
  326. /* 10 msec delay as per HW requirement */
  327. usleep_range(10000, 10010);
  328. snd_soc_component_update_bits(component,
  329. REG_FIELD_VALUE(BIAS, PRECHRG_EN, 0x00));
  330. snd_soc_component_update_bits(component,
  331. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x15));
  332. snd_soc_component_update_bits(component,
  333. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x15));
  334. snd_soc_component_update_bits(component,
  335. REG_FIELD_VALUE(CDC_DMIC_CTL, CLK_SCALE_EN, 0x01));
  336. snd_soc_component_update_bits(component,
  337. REG_FIELD_VALUE(TXFE_ICTRL_STG2CASC_ULP, ICTRL_SCBIAS_ULP0P6M, 0x1));
  338. snd_soc_component_update_bits(component,
  339. REG_FIELD_VALUE(TXFE_ICTRL_STG2CASC_ULP, ICTRL_STG2CASC_ULP, 0x4));
  340. snd_soc_component_update_bits(component,
  341. REG_FIELD_VALUE(TXFE_ICTRL_STG2MAIN_ULP, ICTRL_STG2MAIN_ULP, 0x08));
  342. snd_soc_component_update_bits(component,
  343. REG_FIELD_VALUE(TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  344. snd_soc_component_update_bits(component,
  345. REG_FIELD_VALUE(MICB2_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  346. snd_soc_component_update_bits(component,
  347. REG_FIELD_VALUE(MICB3_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  348. snd_soc_component_update_bits(component,
  349. REG_FIELD_VALUE(MICB4_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
  350. snd_soc_component_update_bits(component,
  351. REG_FIELD_VALUE(TEST_BLK_EN2, TXFE2_MBHC_CLKRST_EN, 0x00));
  352. if (of_find_property(component->card->dev->of_node, "qcom,wcd-disable-legacy-surge", NULL)) {
  353. snd_soc_component_update_bits(component,
  354. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHL, 0x00));
  355. snd_soc_component_update_bits(component,
  356. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHR, 0x00));
  357. }
  358. else {
  359. snd_soc_component_update_bits(component,
  360. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHL, 0x01));
  361. snd_soc_component_update_bits(component,
  362. REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHR, 0x01));
  363. }
  364. snd_soc_component_update_bits(component,
  365. REG_FIELD_VALUE(HPH_OCP_CTL, OCP_FSM_EN, 0x01));
  366. snd_soc_component_update_bits(component,
  367. REG_FIELD_VALUE(HPH_OCP_CTL, SCD_OP_EN, 0x01));
  368. if (wcd939x->version != WCD939X_VERSION_2_0)
  369. snd_soc_component_write(component, WCD939X_CFG0, 0x05);
  370. /*
  371. * Disable 1M pull-up by default during boot by writing 0b1 to bit[7].
  372. * This gets re-enabled when headset is inserted.
  373. */
  374. snd_soc_component_update_bits(component, WCD939X_ZDET_BIAS_CTL, 0x80, 0x80);
  375. return 0;
  376. }
  377. static int wcd939x_set_port_params(struct snd_soc_component *component,
  378. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  379. u8 *ch_mask, u32 *ch_rate,
  380. u8 *port_type, u8 path)
  381. {
  382. int i, j;
  383. u8 num_ports = 0;
  384. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  385. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  386. switch (path) {
  387. case CODEC_RX:
  388. map = &wcd939x->rx_port_mapping;
  389. num_ports = wcd939x->num_rx_ports;
  390. break;
  391. case CODEC_TX:
  392. map = &wcd939x->tx_port_mapping;
  393. num_ports = wcd939x->num_tx_ports;
  394. break;
  395. default:
  396. dev_err_ratelimited(component->dev, "%s Invalid path selected %u\n",
  397. __func__, path);
  398. return -EINVAL;
  399. }
  400. for (i = 0; i <= num_ports; i++) {
  401. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  402. if ((*map)[i][j].slave_port_type == slv_prt_type)
  403. goto found;
  404. }
  405. }
  406. found:
  407. if (i > num_ports || j == MAX_CH_PER_PORT) {
  408. dev_err_ratelimited(component->dev, "%s Failed to find slave port for type %u\n",
  409. __func__, slv_prt_type);
  410. return -EINVAL;
  411. }
  412. *port_id = i;
  413. *num_ch = (*map)[i][j].num_ch;
  414. *ch_mask = (*map)[i][j].ch_mask;
  415. *ch_rate = (*map)[i][j].ch_rate;
  416. *port_type = (*map)[i][j].master_port_type;
  417. return 0;
  418. }
  419. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  420. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  421. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  422. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  423. static int wcd939x_parse_port_params(struct device *dev,
  424. char *prop, u8 path)
  425. {
  426. u32 *dt_array, map_size, max_uc;
  427. int ret = 0;
  428. u32 cnt = 0;
  429. u32 i, j;
  430. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  431. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  432. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  433. switch (path) {
  434. case CODEC_TX:
  435. map = &wcd939x->tx_port_params;
  436. map_uc = &wcd939x->swr_tx_port_params;
  437. break;
  438. default:
  439. ret = -EINVAL;
  440. goto err_port_map;
  441. }
  442. if (!of_find_property(dev->of_node, prop,
  443. &map_size)) {
  444. dev_err(dev, "missing port mapping prop %s\n", prop);
  445. ret = -EINVAL;
  446. goto err_port_map;
  447. }
  448. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  449. if (max_uc != SWR_UC_MAX) {
  450. dev_err(dev, "%s: port params not provided for all usecases\n",
  451. __func__);
  452. ret = -EINVAL;
  453. goto err_port_map;
  454. }
  455. dt_array = kzalloc(map_size, GFP_KERNEL);
  456. if (!dt_array) {
  457. ret = -ENOMEM;
  458. goto err_alloc;
  459. }
  460. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  461. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  462. if (ret) {
  463. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  464. __func__, prop);
  465. goto err_pdata_fail;
  466. }
  467. for (i = 0; i < max_uc; i++) {
  468. for (j = 0; j < SWR_NUM_PORTS; j++) {
  469. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  470. (*map)[i][j].offset1 = dt_array[cnt];
  471. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  472. }
  473. (*map_uc)[i].pp = &(*map)[i][0];
  474. }
  475. kfree(dt_array);
  476. return 0;
  477. err_pdata_fail:
  478. kfree(dt_array);
  479. err_alloc:
  480. err_port_map:
  481. return ret;
  482. }
  483. static int wcd939x_parse_port_mapping(struct device *dev,
  484. char *prop, u8 path)
  485. {
  486. u32 *dt_array, map_size, map_length;
  487. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  488. u32 slave_port_type, master_port_type;
  489. u32 i, ch_iter = 0;
  490. int ret = 0;
  491. u8 *num_ports = NULL;
  492. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  493. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  494. switch (path) {
  495. case CODEC_RX:
  496. map = &wcd939x->rx_port_mapping;
  497. num_ports = &wcd939x->num_rx_ports;
  498. break;
  499. case CODEC_TX:
  500. map = &wcd939x->tx_port_mapping;
  501. num_ports = &wcd939x->num_tx_ports;
  502. break;
  503. default:
  504. dev_err(dev, "%s Invalid path selected %u\n",
  505. __func__, path);
  506. return -EINVAL;
  507. }
  508. if (!of_find_property(dev->of_node, prop,
  509. &map_size)) {
  510. dev_err(dev, "missing port mapping prop %s\n", prop);
  511. ret = -EINVAL;
  512. goto err_port_map;
  513. }
  514. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  515. dt_array = kzalloc(map_size, GFP_KERNEL);
  516. if (!dt_array) {
  517. ret = -ENOMEM;
  518. goto err_alloc;
  519. }
  520. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  521. NUM_SWRS_DT_PARAMS * map_length);
  522. if (ret) {
  523. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  524. __func__, prop);
  525. goto err_pdata_fail;
  526. }
  527. for (i = 0; i < map_length; i++) {
  528. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  529. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  530. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  531. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  532. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  533. if (port_num != old_port_num)
  534. ch_iter = 0;
  535. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  536. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  537. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  538. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  539. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  540. old_port_num = port_num;
  541. }
  542. *num_ports = port_num;
  543. kfree(dt_array);
  544. return 0;
  545. err_pdata_fail:
  546. kfree(dt_array);
  547. err_alloc:
  548. err_port_map:
  549. return ret;
  550. }
  551. static int wcd939x_tx_connect_port(struct snd_soc_component *component,
  552. u8 slv_port_type, int clk_rate,
  553. u8 enable)
  554. {
  555. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  556. u8 port_id, num_ch, ch_mask;
  557. u8 ch_type = 0;
  558. u32 ch_rate;
  559. int slave_ch_idx;
  560. u8 num_port = 1;
  561. int ret = 0;
  562. ret = wcd939x_set_port_params(component, slv_port_type, &port_id,
  563. &num_ch, &ch_mask, &ch_rate,
  564. &ch_type, CODEC_TX);
  565. if (ret)
  566. return ret;
  567. if (clk_rate)
  568. ch_rate = clk_rate;
  569. slave_ch_idx = wcd939x_slave_get_slave_ch_val(slv_port_type);
  570. if (slave_ch_idx != -EINVAL)
  571. ch_type = wcd939x->tx_master_ch_map[slave_ch_idx];
  572. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  573. __func__, slave_ch_idx, ch_type);
  574. if (enable)
  575. ret = swr_connect_port(wcd939x->tx_swr_dev, &port_id,
  576. num_port, &ch_mask, &ch_rate,
  577. &num_ch, &ch_type);
  578. else
  579. ret = swr_disconnect_port(wcd939x->tx_swr_dev, &port_id,
  580. num_port, &ch_mask, &ch_type);
  581. return ret;
  582. }
  583. static int wcd939x_rx_connect_port(struct snd_soc_component *component,
  584. u8 slv_port_type, u8 enable)
  585. {
  586. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  587. u8 port_id, num_ch, ch_mask, port_type;
  588. u32 ch_rate;
  589. u8 num_port = 1;
  590. int ret = 0;
  591. ret = wcd939x_set_port_params(component, slv_port_type, &port_id,
  592. &num_ch, &ch_mask, &ch_rate,
  593. &port_type, CODEC_RX);
  594. if (ret)
  595. return ret;
  596. if (enable)
  597. ret = swr_connect_port(wcd939x->rx_swr_dev, &port_id,
  598. num_port, &ch_mask, &ch_rate,
  599. &num_ch, &port_type);
  600. else
  601. ret = swr_disconnect_port(wcd939x->rx_swr_dev, &port_id,
  602. num_port, &ch_mask, &port_type);
  603. return ret;
  604. }
  605. static int wcd939x_rx_clk_enable(struct snd_soc_component *component, int rx_num)
  606. {
  607. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  608. dev_dbg(component->dev, "%s rx_clk_cnt: %d\n", __func__, wcd939x->rx_clk_cnt);
  609. if (wcd939x->rx_clk_cnt == 0) {
  610. snd_soc_component_update_bits(component,
  611. REG_FIELD_VALUE(RX_SUPPLIES, RX_BIAS_ENABLE, 0x01));
  612. /*Analog path clock controls*/
  613. snd_soc_component_update_bits(component,
  614. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_CLK_EN, 0x01));
  615. snd_soc_component_update_bits(component,
  616. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV2_CLK_EN, 0x01));
  617. snd_soc_component_update_bits(component,
  618. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV4_CLK_EN, 0x01));
  619. /*Digital path clock controls*/
  620. snd_soc_component_update_bits(component,
  621. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x01));
  622. snd_soc_component_update_bits(component,
  623. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD1_CLK_EN, 0x01));
  624. snd_soc_component_update_bits(component,
  625. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD2_CLK_EN, 0x01));
  626. }
  627. wcd939x->rx_clk_cnt++;
  628. return 0;
  629. }
  630. static int wcd939x_rx_clk_disable(struct snd_soc_component *component)
  631. {
  632. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  633. dev_dbg(component->dev, "%s rx_clk_cnt: %d\n", __func__, wcd939x->rx_clk_cnt);
  634. if (wcd939x->rx_clk_cnt == 0)
  635. return 0;
  636. wcd939x->rx_clk_cnt--;
  637. if (wcd939x->rx_clk_cnt == 0) {
  638. snd_soc_component_update_bits(component,
  639. REG_FIELD_VALUE(RX_SUPPLIES, VNEG_EN, 0x00));
  640. snd_soc_component_update_bits(component,
  641. REG_FIELD_VALUE(RX_SUPPLIES, VPOS_EN, 0x00));
  642. snd_soc_component_update_bits(component,
  643. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD2_CLK_EN, 0x00));
  644. snd_soc_component_update_bits(component,
  645. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD1_CLK_EN, 0x00));
  646. snd_soc_component_update_bits(component,
  647. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x00));
  648. snd_soc_component_update_bits(component,
  649. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV4_CLK_EN, 0x00));
  650. snd_soc_component_update_bits(component,
  651. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV2_CLK_EN, 0x00));
  652. snd_soc_component_update_bits(component,
  653. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_CLK_EN, 0x00));
  654. snd_soc_component_update_bits(component,
  655. REG_FIELD_VALUE(RX_SUPPLIES, RX_BIAS_ENABLE, 0x00));
  656. }
  657. return 0;
  658. }
  659. /*
  660. * wcd939x_soc_get_mbhc: get wcd939x_mbhc handle of corresponding component
  661. * @component: handle to snd_soc_component *
  662. *
  663. * return wcd939x_mbhc handle or error code in case of failure
  664. */
  665. struct wcd939x_mbhc *wcd939x_soc_get_mbhc(struct snd_soc_component *component)
  666. {
  667. struct wcd939x_priv *wcd939x;
  668. if (!component) {
  669. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  670. return NULL;
  671. }
  672. wcd939x = snd_soc_component_get_drvdata(component);
  673. if (!wcd939x) {
  674. pr_err_ratelimited("%s: wcd939x is NULL\n", __func__);
  675. return NULL;
  676. }
  677. return wcd939x->mbhc;
  678. }
  679. EXPORT_SYMBOL(wcd939x_soc_get_mbhc);
  680. static int wcd939x_config_power_mode(struct snd_soc_component *component,
  681. int event, int index, int mode)
  682. {
  683. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  684. switch (event) {
  685. case SND_SOC_DAPM_PRE_PMU:
  686. if (mode == CLS_H_ULP) {
  687. snd_soc_component_update_bits(component,
  688. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFP_IOUT_CTL, 0x1));
  689. snd_soc_component_update_bits(component,
  690. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFN_IOUT_CTL, 0x1));
  691. if (wcd939x->compander_enabled[index]) {
  692. if (index == WCD939X_HPHL) {
  693. snd_soc_component_update_bits(component,
  694. REG_FIELD_VALUE(CTL12, ZONE3_RMS, 0x21));
  695. snd_soc_component_update_bits(component,
  696. REG_FIELD_VALUE(CTL13, ZONE4_RMS, 0x30));
  697. snd_soc_component_update_bits(component,
  698. REG_FIELD_VALUE(CTL14, ZONE5_RMS, 0x3F));
  699. snd_soc_component_update_bits(component,
  700. REG_FIELD_VALUE(CTL15, ZONE6_RMS, 0x48));
  701. snd_soc_component_update_bits(component,
  702. REG_FIELD_VALUE(CTL17, PATH_GAIN, 0x0C));
  703. } else if (index == WCD939X_HPHR) {
  704. snd_soc_component_update_bits(component,
  705. REG_FIELD_VALUE(R_CTL12, ZONE3_RMS, 0x21));
  706. snd_soc_component_update_bits(component,
  707. REG_FIELD_VALUE(R_CTL13, ZONE4_RMS, 0x30));
  708. snd_soc_component_update_bits(component,
  709. REG_FIELD_VALUE(R_CTL14, ZONE5_RMS, 0x3F));
  710. snd_soc_component_update_bits(component,
  711. REG_FIELD_VALUE(R_CTL15, ZONE6_RMS, 0x48));
  712. snd_soc_component_update_bits(component,
  713. REG_FIELD_VALUE(R_CTL17, PATH_GAIN, 0x0C));
  714. }
  715. }
  716. } else {
  717. if (wcd939x->compander_enabled[index]) {
  718. if (index == WCD939X_HPHL) {
  719. snd_soc_component_update_bits(component,
  720. REG_FIELD_VALUE(CTL12, ZONE3_RMS, 0x1E));
  721. snd_soc_component_update_bits(component,
  722. REG_FIELD_VALUE(CTL13, ZONE4_RMS, 0x2A));
  723. snd_soc_component_update_bits(component,
  724. REG_FIELD_VALUE(CTL14, ZONE5_RMS, 0x36));
  725. snd_soc_component_update_bits(component,
  726. REG_FIELD_VALUE(CTL15, ZONE6_RMS, 0x3C));
  727. snd_soc_component_update_bits(component,
  728. REG_FIELD_VALUE(CTL17, PATH_GAIN, 0x00));
  729. } else if (index == WCD939X_HPHR) {
  730. snd_soc_component_update_bits(component,
  731. REG_FIELD_VALUE(R_CTL12, ZONE3_RMS, 0x1E));
  732. snd_soc_component_update_bits(component,
  733. REG_FIELD_VALUE(R_CTL13, ZONE4_RMS, 0x2A));
  734. snd_soc_component_update_bits(component,
  735. REG_FIELD_VALUE(R_CTL14, ZONE5_RMS, 0x36));
  736. snd_soc_component_update_bits(component,
  737. REG_FIELD_VALUE(R_CTL15, ZONE6_RMS, 0x3C));
  738. snd_soc_component_update_bits(component,
  739. REG_FIELD_VALUE(R_CTL17, PATH_GAIN, 0x00));
  740. }
  741. }
  742. }
  743. break;
  744. case SND_SOC_DAPM_POST_PMD:
  745. if (mode == CLS_H_ULP) {
  746. snd_soc_component_update_bits(component,
  747. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFN_IOUT_CTL, 0x0));
  748. snd_soc_component_update_bits(component,
  749. REG_FIELD_VALUE(REFBUFF_UHQA_CTL, REFBUFP_IOUT_CTL, 0x0));
  750. }
  751. break;
  752. }
  753. return 0;
  754. }
  755. static int wcd939x_get_usbss_hph_power_mode(int hph_mode)
  756. {
  757. switch (hph_mode) {
  758. case CLS_H_HIFI:
  759. case CLS_H_LOHIFI:
  760. return 0x4;
  761. default:
  762. /* set default mode to ULP */
  763. return 0x2;
  764. }
  765. }
  766. static int wcd939x_enable_hph_pcm_index(struct snd_soc_component *component,
  767. int event, int hph)
  768. {
  769. struct wcd939x_priv *wcd939x = NULL;
  770. if (!component) {
  771. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  772. return -EINVAL;
  773. }
  774. wcd939x = snd_soc_component_get_drvdata(component);
  775. if (!wcd939x->hph_pcm_enabled)
  776. return 0;
  777. switch (event) {
  778. case SND_SOC_DAPM_POST_PMU:
  779. if (hph == WCD939X_HPHL) {
  780. if (wcd939x->rx_clk_config == RX_CLK_11P2896MHZ)
  781. snd_soc_component_update_bits(component,
  782. REG_FIELD_VALUE(HPHL_RX_PATH_CFG1,
  783. RX_DC_DROOP_COEFF_SEL, 0x2));
  784. else if (wcd939x->rx_clk_config == RX_CLK_9P6MHZ)
  785. snd_soc_component_update_bits(component,
  786. REG_FIELD_VALUE(HPHL_RX_PATH_CFG1,
  787. RX_DC_DROOP_COEFF_SEL, 0x3));
  788. snd_soc_component_update_bits(component,
  789. REG_FIELD_VALUE(HPHL_RX_PATH_CFG0,
  790. DLY_ZN_EN, 0x1));
  791. snd_soc_component_update_bits(component,
  792. REG_FIELD_VALUE(HPHL_RX_PATH_CFG0,
  793. INT_EN, 0x3));
  794. } else if (hph == WCD939X_HPHR) {
  795. if (wcd939x->rx_clk_config == RX_CLK_11P2896MHZ)
  796. snd_soc_component_update_bits(component,
  797. REG_FIELD_VALUE(HPHR_RX_PATH_CFG1,
  798. RX_DC_DROOP_COEFF_SEL, 0x2));
  799. else if (wcd939x->rx_clk_config == RX_CLK_9P6MHZ)
  800. snd_soc_component_update_bits(component,
  801. REG_FIELD_VALUE(HPHR_RX_PATH_CFG1,
  802. RX_DC_DROOP_COEFF_SEL, 0x3));
  803. snd_soc_component_update_bits(component,
  804. REG_FIELD_VALUE(HPHR_RX_PATH_CFG0,
  805. DLY_ZN_EN, 0x1));
  806. snd_soc_component_update_bits(component,
  807. REG_FIELD_VALUE(HPHR_RX_PATH_CFG0,
  808. INT_EN, 0x3));
  809. }
  810. break;
  811. case SND_SOC_DAPM_POST_PMD:
  812. break;
  813. }
  814. return 0;
  815. }
  816. static int wcd939x_config_compander(struct snd_soc_component *component,
  817. int event, int compander_indx)
  818. {
  819. u16 comp_ctl7_reg = 0, comp_ctl0_reg = 0;
  820. u16 comp_en_mask_val = 0, gain_source_sel = 0;
  821. struct wcd939x_priv *wcd939x;
  822. if (compander_indx >= WCD939X_HPH_MAX || compander_indx < 0) {
  823. pr_err_ratelimited("%s: Invalid compander value: %d\n",
  824. __func__, compander_indx);
  825. return -EINVAL;
  826. }
  827. if (!component) {
  828. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  829. return -EINVAL;
  830. }
  831. wcd939x = snd_soc_component_get_drvdata(component);
  832. if (!wcd939x->hph_pcm_enabled)
  833. return 0;
  834. dev_dbg(component->dev, "%s compander_index = %d\n", __func__, compander_indx);
  835. if (!wcd939x->compander_enabled[compander_indx]) {
  836. if (SND_SOC_DAPM_EVENT_ON(event))
  837. gain_source_sel = 0x01;
  838. else
  839. gain_source_sel = 0x00;
  840. if (compander_indx == WCD939X_HPHL) {
  841. snd_soc_component_update_bits(component,
  842. REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, gain_source_sel));
  843. } else if (compander_indx == WCD939X_HPHR) {
  844. snd_soc_component_update_bits(component,
  845. REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, gain_source_sel));
  846. }
  847. wcd939x_config_2Vpk_mode(component, wcd939x, SET_HPH_GAIN_2VPK);
  848. return 0;
  849. }
  850. if (compander_indx == WCD939X_HPHL)
  851. comp_en_mask_val = 1 << 1;
  852. else if (compander_indx == WCD939X_HPHR)
  853. comp_en_mask_val = 1 << 0;
  854. else
  855. return 0;
  856. comp_ctl0_reg = WCD939X_CTL0 + (compander_indx * WCD939X_COMP_OFFSET);
  857. comp_ctl7_reg = WCD939X_CTL7 + (compander_indx * WCD939X_COMP_OFFSET);
  858. if (SND_SOC_DAPM_EVENT_ON(event)) {
  859. snd_soc_component_update_bits(component,
  860. comp_ctl7_reg, 0x1E, 0x00);
  861. /* Enable compander clock*/
  862. snd_soc_component_update_bits(component,
  863. comp_ctl0_reg , 0x01, 0x01);
  864. /* 250us sleep required as per HW Sequence */
  865. usleep_range(250, 260);
  866. snd_soc_component_update_bits(component,
  867. comp_ctl0_reg, 0x02, 0x02);
  868. snd_soc_component_update_bits(component,
  869. comp_ctl0_reg, 0x02, 0x00);
  870. /* Enable compander*/
  871. snd_soc_component_update_bits(component,
  872. WCD939X_CDC_COMP_CTL_0, comp_en_mask_val, comp_en_mask_val);
  873. } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
  874. snd_soc_component_update_bits(component,
  875. WCD939X_CDC_COMP_CTL_0, comp_en_mask_val, 0x00);
  876. snd_soc_component_update_bits(component,
  877. comp_ctl0_reg , 0x01, 0x00);
  878. if (compander_indx == WCD939X_HPHL)
  879. snd_soc_component_update_bits(component,
  880. REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, 0x0));
  881. if (compander_indx == WCD939X_HPHR)
  882. snd_soc_component_update_bits(component,
  883. REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, 0x0));
  884. }
  885. return 0;
  886. }
  887. static int wcd939x_config_xtalk(struct snd_soc_component *component,
  888. int event, int xtalk_indx)
  889. {
  890. u16 xtalk_sec0 = 0, xtalk_sec1 = 0, xtalk_sec2 = 0, xtalk_sec3 = 0;
  891. struct wcd939x_priv *wcd939x = NULL;
  892. struct wcd939x_pdata *pdata = NULL;
  893. if (!component) {
  894. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  895. return -EINVAL;
  896. }
  897. wcd939x = snd_soc_component_get_drvdata(component);
  898. if (!wcd939x->xtalk_enabled[xtalk_indx])
  899. return 0;
  900. pdata = dev_get_platdata(wcd939x->dev);
  901. dev_dbg(component->dev, "%s xtalk_indx = %d event = %d\n",
  902. __func__, xtalk_indx, event);
  903. switch(event) {
  904. case SND_SOC_DAPM_PRE_PMU:
  905. xtalk_sec0 = WCD939X_HPHL_RX_PATH_SEC0 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  906. xtalk_sec1 = WCD939X_HPHL_RX_PATH_SEC1 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  907. xtalk_sec2 = WCD939X_HPHL_RX_PATH_SEC2 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  908. xtalk_sec3 = WCD939X_HPHL_RX_PATH_SEC3 + (xtalk_indx * WCD939X_XTALK_OFFSET);
  909. /* Write scale and alpha based on channel */
  910. if (xtalk_indx == XTALK_L_CH_NUM) {
  911. snd_soc_component_update_bits(component, xtalk_sec1, 0xFF,
  912. pdata->usbcss_hs.alpha_l);
  913. snd_soc_component_update_bits(component, xtalk_sec0, 0x1F,
  914. pdata->usbcss_hs.scale_l);
  915. } else if (xtalk_indx == XTALK_R_CH_NUM) {
  916. snd_soc_component_update_bits(component, xtalk_sec1, 0xFF,
  917. pdata->usbcss_hs.alpha_r);
  918. snd_soc_component_update_bits(component, xtalk_sec0, 0x1F,
  919. pdata->usbcss_hs.scale_r);
  920. } else {
  921. snd_soc_component_update_bits(component, xtalk_sec1, 0xFF, MIN_XTALK_ALPHA);
  922. snd_soc_component_update_bits(component, xtalk_sec0, 0x1F, MAX_XTALK_SCALE);
  923. }
  924. dev_dbg(component->dev, "%s Scale = 0x%x, Alpha = 0x%x\n", __func__,
  925. snd_soc_component_read(component, xtalk_sec0),
  926. snd_soc_component_read(component, xtalk_sec1));
  927. snd_soc_component_update_bits(component, xtalk_sec3, 0xFF, 0x4F);
  928. snd_soc_component_update_bits(component, xtalk_sec2, 0x1F, 0x11);
  929. break;
  930. case SND_SOC_DAPM_POST_PMU:
  931. /* enable xtalk for L and R channels*/
  932. snd_soc_component_update_bits(component, WCD939X_RX_PATH_CFG2,
  933. 0x0F, 0x0F);
  934. break;
  935. case SND_SOC_DAPM_POST_PMD:
  936. /* Disable Xtalk for L and R channels*/
  937. snd_soc_component_update_bits(component, WCD939X_RX_PATH_CFG2,
  938. 0x00, 0x00);
  939. break;
  940. }
  941. return 0;
  942. }
  943. static int wcd939x_rx3_mux(struct snd_soc_dapm_widget *w,
  944. struct snd_kcontrol *kcontrol, int event)
  945. {
  946. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  947. dev_dbg(component->dev, "%s event: %d wshift: %d wname: %s\n",
  948. __func__, event, w->shift, w->name);
  949. switch (event) {
  950. case SND_SOC_DAPM_PRE_PMU:
  951. wcd939x_rx_clk_enable(component, w->shift);
  952. break;
  953. case SND_SOC_DAPM_POST_PMD:
  954. wcd939x_rx_clk_disable(component);
  955. break;
  956. }
  957. return 0;
  958. }
  959. static int wcd939x_rx_mux(struct snd_soc_dapm_widget *w,
  960. struct snd_kcontrol *kcontrol,
  961. int event)
  962. {
  963. int hph_mode = 0;
  964. struct wcd939x_priv *wcd939x = NULL;
  965. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  966. wcd939x = snd_soc_component_get_drvdata(component);
  967. hph_mode = wcd939x->hph_mode;
  968. dev_dbg(component->dev, "%s event: %d wshift: %d wname: %s\n",
  969. __func__, event, w->shift, w->name);
  970. switch (event) {
  971. case SND_SOC_DAPM_PRE_PMU:
  972. wcd939x_rx_clk_enable(component, w->shift);
  973. if (wcd939x->hph_pcm_enabled)
  974. wcd939x_config_power_mode(component, event, w->shift, hph_mode);
  975. wcd939x_config_compander(component, event, w->shift);
  976. wcd939x_config_xtalk(component, event, w->shift);
  977. break;
  978. case SND_SOC_DAPM_POST_PMU:
  979. wcd939x_config_xtalk(component, event, w->shift);
  980. /*TBD: need to revisit , for both L & R we are updating, but in QCRG only once*/
  981. if (wcd939x->hph_pcm_enabled) {
  982. if (hph_mode == CLS_H_HIFI || hph_mode == CLS_AB_HIFI)
  983. snd_soc_component_update_bits(component,
  984. REG_FIELD_VALUE(TOP_CFG0, HPH_DAC_RATE_SEL, 0x1));
  985. else
  986. snd_soc_component_update_bits(component,
  987. REG_FIELD_VALUE(TOP_CFG0, HPH_DAC_RATE_SEL, 0x0));
  988. }
  989. wcd939x_enable_hph_pcm_index(component, event, w->shift);
  990. break;
  991. case SND_SOC_DAPM_POST_PMD:
  992. wcd939x_config_xtalk(component, event, w->shift);
  993. wcd939x_config_compander(component, event, w->shift);
  994. if (wcd939x->hph_pcm_enabled)
  995. wcd939x_config_power_mode(component, event, w->shift, hph_mode);
  996. wcd939x_rx_clk_disable(component);
  997. break;
  998. }
  999. return 0;
  1000. }
  1001. static void wcd939x_config_2Vpk_mode(struct snd_soc_component *component,
  1002. struct wcd939x_priv *wcd939x, int mode_2vpk)
  1003. {
  1004. uint32_t zl = 0, zr = 0;
  1005. int rc;
  1006. if (!wcd939x->in_2Vpk_mode)
  1007. return;
  1008. rc = wcd_mbhc_get_impedance(&wcd939x->mbhc->wcd_mbhc, &zl, &zr);
  1009. if (rc) {
  1010. dev_err_ratelimited(component->dev, "%s: Unable to get impedance for 2Vpk mode", __func__);
  1011. return;
  1012. }
  1013. switch (mode_2vpk) {
  1014. case SUPPLY_LEVEL_2VPK:
  1015. snd_soc_component_update_bits(component,
  1016. REG_FIELD_VALUE(PA_GAIN_CTL_L, RX_SUPPLY_LEVEL, 0x01));
  1017. if (zl < HPH_IMPEDANCE_2VPK_MODE_OHMS)
  1018. snd_soc_component_update_bits(component,
  1019. REG_FIELD_VALUE(PA_GAIN_CTL_L, EN_HPHPA_2VPK, 0x00));
  1020. else
  1021. snd_soc_component_update_bits(component,
  1022. REG_FIELD_VALUE(PA_GAIN_CTL_L, EN_HPHPA_2VPK, 0x01));
  1023. break;
  1024. case REGULATOR_MODE_2VPK:
  1025. if (zl >= HPH_IMPEDANCE_2VPK_MODE_OHMS) {
  1026. snd_soc_component_update_bits(component,
  1027. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1028. snd_soc_component_update_bits(component, WCD939X_FLYBACK_TEST_CTL,
  1029. 0x0F, 0x02);
  1030. } else {
  1031. snd_soc_component_update_bits(component, WCD939X_FLYBACK_TEST_CTL,
  1032. 0x0F, 0x0D);
  1033. }
  1034. break;
  1035. case SET_HPH_GAIN_2VPK:
  1036. if (zl >= HPH_IMPEDANCE_2VPK_MODE_OHMS) {
  1037. snd_soc_component_update_bits(component, WCD939X_PA_GAIN_CTL_L, 0x1F, 0x02);
  1038. snd_soc_component_update_bits(component, WCD939X_PA_GAIN_CTL_R, 0x1F, 0x02);
  1039. }
  1040. break;
  1041. }
  1042. }
  1043. static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1044. struct snd_kcontrol *kcontrol,
  1045. int event)
  1046. {
  1047. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1048. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1049. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1050. w->name, event);
  1051. switch (event) {
  1052. case SND_SOC_DAPM_PRE_PMU:
  1053. if (!wcd939x->hph_pcm_enabled)
  1054. snd_soc_component_update_bits(component,
  1055. REG_FIELD_VALUE(RDAC_CLK_CTL1, OPAMP_CHOP_CLK_EN, 0x00));
  1056. wcd939x_config_2Vpk_mode(component, wcd939x, SUPPLY_LEVEL_2VPK);
  1057. snd_soc_component_update_bits(component,
  1058. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHL_RX_EN, 0x01));
  1059. break;
  1060. case SND_SOC_DAPM_POST_PMU:
  1061. snd_soc_component_update_bits(component,
  1062. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x1D));
  1063. if (!wcd939x->hph_pcm_enabled) {
  1064. if (wcd939x->comp1_enable) {
  1065. snd_soc_component_update_bits(component,
  1066. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x01));
  1067. /* 5msec compander delay as per HW requirement */
  1068. if (!wcd939x->comp2_enable ||
  1069. (snd_soc_component_read(component,
  1070. WCD939X_CDC_COMP_CTL_0) & 0x01))
  1071. usleep_range(5000, 5010);
  1072. snd_soc_component_update_bits(component,
  1073. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1074. } else {
  1075. snd_soc_component_update_bits(component,
  1076. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x00));
  1077. snd_soc_component_update_bits(component,
  1078. REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, 0x01));
  1079. }
  1080. }
  1081. if (wcd939x->hph_pcm_enabled) {
  1082. snd_soc_component_update_bits(component,
  1083. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1084. snd_soc_component_write(component, WCD939X_VNEG_CTRL_1, 0xEB);
  1085. if (wcd939x->hph_mode == CLS_H_LOHIFI)
  1086. snd_soc_component_write(component,
  1087. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x52);
  1088. else
  1089. snd_soc_component_write(component,
  1090. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x64);
  1091. }
  1092. break;
  1093. case SND_SOC_DAPM_POST_PMD:
  1094. snd_soc_component_update_bits(component,
  1095. REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x01));
  1096. snd_soc_component_update_bits(component,
  1097. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHL_RX_EN, 0x00));
  1098. break;
  1099. }
  1100. return 0;
  1101. }
  1102. static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1103. struct snd_kcontrol *kcontrol,
  1104. int event)
  1105. {
  1106. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1107. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1108. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1109. w->name, event);
  1110. switch (event) {
  1111. case SND_SOC_DAPM_PRE_PMU:
  1112. if (!wcd939x->hph_pcm_enabled)
  1113. snd_soc_component_update_bits(component,
  1114. REG_FIELD_VALUE(RDAC_CLK_CTL1, OPAMP_CHOP_CLK_EN, 0x00));
  1115. wcd939x_config_2Vpk_mode(component, wcd939x, SUPPLY_LEVEL_2VPK);
  1116. snd_soc_component_update_bits(component,
  1117. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHR_RX_EN, 0x01));
  1118. break;
  1119. case SND_SOC_DAPM_POST_PMU:
  1120. snd_soc_component_update_bits(component,
  1121. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x1D));
  1122. if (!wcd939x->hph_pcm_enabled) {
  1123. if (wcd939x->comp1_enable) {
  1124. snd_soc_component_update_bits(component,
  1125. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHR_COMP_EN, 0x01));
  1126. /* 5msec compander delay as per HW requirement */
  1127. if (!wcd939x->comp2_enable ||
  1128. (snd_soc_component_read(component,
  1129. WCD939X_CDC_COMP_CTL_0) & 0x02))
  1130. usleep_range(5000, 5010);
  1131. snd_soc_component_update_bits(component,
  1132. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
  1133. } else {
  1134. snd_soc_component_update_bits(component,
  1135. REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHR_COMP_EN, 0x00));
  1136. snd_soc_component_update_bits(component,
  1137. REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, 0x01));
  1138. }
  1139. }
  1140. if (wcd939x->hph_pcm_enabled) {
  1141. snd_soc_component_write(component, WCD939X_VNEG_CTRL_1, 0xEB);
  1142. if (wcd939x->hph_mode == CLS_H_LOHIFI)
  1143. snd_soc_component_write(component,
  1144. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x52);
  1145. else
  1146. snd_soc_component_write(component,
  1147. WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x64);
  1148. }
  1149. break;
  1150. case SND_SOC_DAPM_POST_PMD:
  1151. snd_soc_component_update_bits(component,
  1152. REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x01));
  1153. snd_soc_component_update_bits(component,
  1154. REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHR_RX_EN, 0x00));
  1155. break;
  1156. }
  1157. return 0;
  1158. }
  1159. static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1160. struct snd_kcontrol *kcontrol,
  1161. int event)
  1162. {
  1163. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1164. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1165. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1166. w->name, event);
  1167. switch (event) {
  1168. case SND_SOC_DAPM_PRE_PMU:
  1169. snd_soc_component_update_bits(component,
  1170. REG_FIELD_VALUE(CDC_EAR_GAIN_CTL, EAR_EN, 0x01));
  1171. snd_soc_component_update_bits(component,
  1172. REG_FIELD_VALUE(EAR_DAC_CON, DAC_SAMPLE_EDGE_SEL, 0x00));
  1173. /* 5 msec delay as per HW requirement */
  1174. usleep_range(5000, 5010);
  1175. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1176. WCD_CLSH_EVENT_PRE_DAC,
  1177. WCD_CLSH_STATE_EAR,
  1178. CLS_AB_HIFI);
  1179. snd_soc_component_update_bits(component,
  1180. REG_FIELD_VALUE(VNEG_CTRL_4, ILIM_SEL, 0xD));
  1181. break;
  1182. case SND_SOC_DAPM_POST_PMD:
  1183. snd_soc_component_update_bits(component,
  1184. REG_FIELD_VALUE(EAR_DAC_CON, DAC_SAMPLE_EDGE_SEL, 0x01));
  1185. break;
  1186. };
  1187. return 0;
  1188. }
  1189. static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1190. struct snd_kcontrol *kcontrol,
  1191. int event)
  1192. {
  1193. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1194. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1195. int ret = 0;
  1196. int hph_mode = wcd939x->hph_mode;
  1197. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1198. w->name, event);
  1199. switch (event) {
  1200. case SND_SOC_DAPM_PRE_PMU:
  1201. if (wcd939x->ldoh)
  1202. snd_soc_component_update_bits(component,
  1203. REG_FIELD_VALUE(MODE, LDOH_EN, 0x01));
  1204. if (wcd939x->update_wcd_event)
  1205. wcd939x->update_wcd_event(wcd939x->handle,
  1206. SLV_BOLERO_EVT_RX_MUTE,
  1207. (WCD_RX2 << 0x10 | 0x1));
  1208. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1209. wcd939x->rx_swr_dev->dev_num,
  1210. true);
  1211. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1212. WCD_CLSH_EVENT_PRE_DAC,
  1213. WCD_CLSH_STATE_HPHR,
  1214. hph_mode);
  1215. wcd939x_config_2Vpk_mode(component, wcd939x, REGULATOR_MODE_2VPK);
  1216. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  1217. hph_mode == CLS_H_ULP) {
  1218. if (!wcd939x->hph_pcm_enabled)
  1219. snd_soc_component_update_bits(component,
  1220. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x01));
  1221. }
  1222. /* update Mode for LOHIFI */
  1223. if (hph_mode == CLS_H_LOHIFI) {
  1224. snd_soc_component_update_bits(component,
  1225. REG_FIELD_VALUE(HPH, PWR_LEVEL, 0x00));
  1226. }
  1227. /* update USBSS power mode for AATC */
  1228. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog)
  1229. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE,
  1230. wcd939x_get_usbss_hph_power_mode(hph_mode));
  1231. snd_soc_component_update_bits(component,
  1232. REG_FIELD_VALUE(VNEG_CTRL_4, ILIM_SEL, 0xD));
  1233. snd_soc_component_update_bits(component,
  1234. REG_FIELD_VALUE(HPH, HPHR_REF_ENABLE, 0x01));
  1235. if ((snd_soc_component_read(component, WCD939X_HPH) & 0x30) == 0x30)
  1236. usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
  1237. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1238. if (!wcd939x->hph_pcm_enabled)
  1239. snd_soc_component_update_bits(component,
  1240. REG_FIELD_VALUE(PDM_WD_CTL1, PDM_WD_EN, 0x03));
  1241. break;
  1242. case SND_SOC_DAPM_POST_PMU:
  1243. /*
  1244. * 7ms sleep is required if compander is enabled as per
  1245. * HW requirement. If compander is disabled, then
  1246. * 20ms delay is required.
  1247. */
  1248. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1249. if (!wcd939x->comp2_enable)
  1250. usleep_range(20000, 20100);
  1251. else
  1252. usleep_range(7000, 7100);
  1253. if (hph_mode == CLS_H_LP ||
  1254. hph_mode == CLS_H_LOHIFI ||
  1255. hph_mode == CLS_H_ULP)
  1256. if (!wcd939x->hph_pcm_enabled)
  1257. snd_soc_component_update_bits(component,
  1258. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x00));
  1259. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1260. }
  1261. snd_soc_component_update_bits(component,
  1262. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x01));
  1263. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1264. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1265. snd_soc_component_update_bits(component,
  1266. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1267. if (wcd939x->update_wcd_event)
  1268. wcd939x->update_wcd_event(wcd939x->handle,
  1269. SLV_BOLERO_EVT_RX_MUTE,
  1270. (WCD_RX2 << 0x10));
  1271. /*Enable PDM INT for PDM data path only*/
  1272. if (!wcd939x->hph_pcm_enabled)
  1273. wcd_enable_irq(&wcd939x->irq_info,
  1274. WCD939X_IRQ_HPHR_PDM_WD_INT);
  1275. break;
  1276. case SND_SOC_DAPM_PRE_PMD:
  1277. if (wcd939x->update_wcd_event)
  1278. wcd939x->update_wcd_event(wcd939x->handle,
  1279. SLV_BOLERO_EVT_RX_MUTE,
  1280. (WCD_RX2 << 0x10 | 0x1));
  1281. wcd_disable_irq(&wcd939x->irq_info,
  1282. WCD939X_IRQ_HPHR_PDM_WD_INT);
  1283. if (wcd939x->update_wcd_event && wcd939x->comp2_enable)
  1284. wcd939x->update_wcd_event(wcd939x->handle,
  1285. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1286. (WCD_RX2 << 0x10));
  1287. /*
  1288. * 7ms sleep is required if compander is enabled as per
  1289. * HW requirement. If compander is disabled, then
  1290. * 20ms delay is required.
  1291. */
  1292. if (!wcd939x->comp2_enable)
  1293. usleep_range(20000, 20100);
  1294. else
  1295. usleep_range(7000, 7100);
  1296. snd_soc_component_update_bits(component,
  1297. REG_FIELD_VALUE(HPH, HPHR_ENABLE, 0x00));
  1298. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1299. WCD_EVENT_PRE_HPHR_PA_OFF,
  1300. &wcd939x->mbhc->wcd_mbhc);
  1301. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1302. break;
  1303. case SND_SOC_DAPM_POST_PMD:
  1304. /*
  1305. * 7ms sleep is required if compander is enabled as per
  1306. * HW requirement. If compander is disabled, then
  1307. * 20ms delay is required.
  1308. */
  1309. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1310. if (!wcd939x->comp2_enable)
  1311. usleep_range(20000, 20100);
  1312. else
  1313. usleep_range(7000, 7100);
  1314. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1315. }
  1316. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1317. WCD_EVENT_POST_HPHR_PA_OFF,
  1318. &wcd939x->mbhc->wcd_mbhc);
  1319. snd_soc_component_update_bits(component,
  1320. REG_FIELD_VALUE(HPH, HPHR_REF_ENABLE, 0x00));
  1321. snd_soc_component_update_bits(component,
  1322. REG_FIELD_VALUE(PDM_WD_CTL1, PDM_WD_EN, 0x00));
  1323. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog &&
  1324. !(snd_soc_component_read(component, WCD939X_HPH) & 0XC0))
  1325. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE, 1);
  1326. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1327. WCD_CLSH_EVENT_POST_PA,
  1328. WCD_CLSH_STATE_HPHR,
  1329. hph_mode);
  1330. if (wcd939x->ldoh)
  1331. snd_soc_component_update_bits(component,
  1332. REG_FIELD_VALUE(MODE, LDOH_EN, 0x00));
  1333. break;
  1334. };
  1335. return ret;
  1336. }
  1337. static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1338. struct snd_kcontrol *kcontrol,
  1339. int event)
  1340. {
  1341. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1342. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1343. int ret = 0;
  1344. int hph_mode = wcd939x->hph_mode;
  1345. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1346. w->name, event);
  1347. switch (event) {
  1348. case SND_SOC_DAPM_PRE_PMU:
  1349. if (wcd939x->ldoh)
  1350. snd_soc_component_update_bits(component,
  1351. REG_FIELD_VALUE(MODE, LDOH_EN, 0x01));
  1352. if (wcd939x->update_wcd_event)
  1353. wcd939x->update_wcd_event(wcd939x->handle,
  1354. SLV_BOLERO_EVT_RX_MUTE,
  1355. (WCD_RX1 << 0x10 | 0x01));
  1356. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1357. wcd939x->rx_swr_dev->dev_num,
  1358. true);
  1359. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1360. WCD_CLSH_EVENT_PRE_DAC,
  1361. WCD_CLSH_STATE_HPHL,
  1362. hph_mode);
  1363. wcd939x_config_2Vpk_mode(component, wcd939x, REGULATOR_MODE_2VPK);
  1364. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  1365. hph_mode == CLS_H_ULP) {
  1366. if (!wcd939x->hph_pcm_enabled)
  1367. snd_soc_component_update_bits(component,
  1368. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x01));
  1369. }
  1370. /* update Mode for LOHIFI */
  1371. if (hph_mode == CLS_H_LOHIFI) {
  1372. snd_soc_component_update_bits(component,
  1373. REG_FIELD_VALUE(HPH, PWR_LEVEL, 0x00));
  1374. }
  1375. /* update USBSS power mode for AATC */
  1376. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog)
  1377. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE,
  1378. wcd939x_get_usbss_hph_power_mode(hph_mode));
  1379. snd_soc_component_update_bits(component,
  1380. REG_FIELD_VALUE(VNEG_CTRL_4, ILIM_SEL, 0xD));
  1381. snd_soc_component_update_bits(component,
  1382. REG_FIELD_VALUE(HPH, HPHL_REF_ENABLE, 0x01));
  1383. if ((snd_soc_component_read(component, WCD939X_HPH) & 0x30) == 0x30)
  1384. usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
  1385. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1386. if (!wcd939x->hph_pcm_enabled)
  1387. snd_soc_component_update_bits(component,
  1388. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x03));
  1389. break;
  1390. case SND_SOC_DAPM_POST_PMU:
  1391. /*
  1392. * 7ms sleep is required if compander is enabled as per
  1393. * HW requirement. If compander is disabled, then
  1394. * 20ms delay is required.
  1395. */
  1396. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1397. if (!wcd939x->comp1_enable)
  1398. usleep_range(20000, 20100);
  1399. else
  1400. usleep_range(7000, 7100);
  1401. if (hph_mode == CLS_H_LP ||
  1402. hph_mode == CLS_H_LOHIFI ||
  1403. hph_mode == CLS_H_ULP)
  1404. if (!wcd939x->hph_pcm_enabled)
  1405. snd_soc_component_update_bits(component,
  1406. REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x00));
  1407. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1408. }
  1409. snd_soc_component_update_bits(component,
  1410. REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x01));
  1411. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1412. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1413. snd_soc_component_update_bits(component,
  1414. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1415. if (wcd939x->update_wcd_event)
  1416. wcd939x->update_wcd_event(wcd939x->handle,
  1417. SLV_BOLERO_EVT_RX_MUTE,
  1418. (WCD_RX1 << 0x10));
  1419. /*Enable PDM INT for PDM data path only*/
  1420. if (!wcd939x->hph_pcm_enabled)
  1421. wcd_enable_irq(&wcd939x->irq_info,
  1422. WCD939X_IRQ_HPHL_PDM_WD_INT);
  1423. break;
  1424. case SND_SOC_DAPM_PRE_PMD:
  1425. if (wcd939x->update_wcd_event)
  1426. wcd939x->update_wcd_event(wcd939x->handle,
  1427. SLV_BOLERO_EVT_RX_MUTE,
  1428. (WCD_RX1 << 0x10 | 0x1));
  1429. wcd_disable_irq(&wcd939x->irq_info,
  1430. WCD939X_IRQ_HPHL_PDM_WD_INT);
  1431. if (wcd939x->update_wcd_event && wcd939x->comp1_enable)
  1432. wcd939x->update_wcd_event(wcd939x->handle,
  1433. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1434. (WCD_RX1 << 0x10));
  1435. /*
  1436. * 7ms sleep is required if compander is enabled as per
  1437. * HW requirement. If compander is disabled, then
  1438. * 20ms delay is required.
  1439. */
  1440. if (!wcd939x->comp1_enable)
  1441. usleep_range(20000, 20100);
  1442. else
  1443. usleep_range(7000, 7100);
  1444. snd_soc_component_update_bits(component,
  1445. REG_FIELD_VALUE(HPH, HPHL_ENABLE, 0x00));
  1446. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1447. WCD_EVENT_PRE_HPHL_PA_OFF,
  1448. &wcd939x->mbhc->wcd_mbhc);
  1449. set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1450. break;
  1451. case SND_SOC_DAPM_POST_PMD:
  1452. /*
  1453. * 7ms sleep is required if compander is enabled as per
  1454. * HW requirement. If compander is disabled, then
  1455. * 20ms delay is required.
  1456. */
  1457. if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
  1458. if (!wcd939x->comp1_enable)
  1459. usleep_range(21000, 21100);
  1460. else
  1461. usleep_range(7000, 7100);
  1462. clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
  1463. }
  1464. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  1465. WCD_EVENT_POST_HPHL_PA_OFF,
  1466. &wcd939x->mbhc->wcd_mbhc);
  1467. snd_soc_component_update_bits(component,
  1468. REG_FIELD_VALUE(HPH, HPHL_REF_ENABLE, 0x00));
  1469. snd_soc_component_update_bits(component,
  1470. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x00));
  1471. if (wcd939x->mbhc->wcd_mbhc.mbhc_cfg->enable_usbc_analog &&
  1472. !(snd_soc_component_read(component, WCD939X_HPH) & 0XC0))
  1473. wcd_usbss_audio_config(NULL, WCD_USBSS_CONFIG_TYPE_POWER_MODE, 1);
  1474. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1475. WCD_CLSH_EVENT_POST_PA,
  1476. WCD_CLSH_STATE_HPHL,
  1477. hph_mode);
  1478. if (wcd939x->ldoh)
  1479. snd_soc_component_update_bits(component,
  1480. REG_FIELD_VALUE(MODE, LDOH_EN, 0x00));
  1481. break;
  1482. };
  1483. return ret;
  1484. }
  1485. static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1486. struct snd_kcontrol *kcontrol,
  1487. int event)
  1488. {
  1489. struct snd_soc_component *component =
  1490. snd_soc_dapm_to_component(w->dapm);
  1491. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1492. int ret = 0;
  1493. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1494. w->name, event);
  1495. switch (event) {
  1496. case SND_SOC_DAPM_PRE_PMU:
  1497. ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
  1498. wcd939x->rx_swr_dev->dev_num,
  1499. true);
  1500. /*
  1501. * Enable watchdog interrupt for HPHL
  1502. */
  1503. snd_soc_component_update_bits(component,
  1504. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x03));
  1505. /* For EAR, use CLASS_AB regulator mode */
  1506. snd_soc_component_update_bits(component,
  1507. REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
  1508. snd_soc_component_update_bits(component,
  1509. REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x01));
  1510. break;
  1511. case SND_SOC_DAPM_POST_PMU:
  1512. /* 6 msec delay as per HW requirement */
  1513. usleep_range(6000, 6010);
  1514. if (wcd939x->update_wcd_event)
  1515. wcd939x->update_wcd_event(wcd939x->handle,
  1516. SLV_BOLERO_EVT_RX_MUTE,
  1517. (WCD_RX3 << 0x10));
  1518. wcd_enable_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT);
  1519. break;
  1520. case SND_SOC_DAPM_PRE_PMD:
  1521. wcd_disable_irq(&wcd939x->irq_info,
  1522. WCD939X_IRQ_EAR_PDM_WD_INT);
  1523. if (wcd939x->update_wcd_event)
  1524. wcd939x->update_wcd_event(wcd939x->handle,
  1525. SLV_BOLERO_EVT_RX_MUTE,
  1526. (WCD_RX3 << 0x10 | 0x1));
  1527. break;
  1528. case SND_SOC_DAPM_POST_PMD:
  1529. snd_soc_component_update_bits(component,
  1530. REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x00));
  1531. /* 7 msec delay as per HW requirement */
  1532. usleep_range(7000, 7010);
  1533. snd_soc_component_update_bits(component,
  1534. REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x00));
  1535. wcd_cls_h_fsm(component, &wcd939x->clsh_info,
  1536. WCD_CLSH_EVENT_POST_PA,
  1537. WCD_CLSH_STATE_EAR,
  1538. CLS_AB_HIFI);
  1539. break;
  1540. };
  1541. return ret;
  1542. }
  1543. static int wcd939x_clsh_dummy(struct snd_soc_dapm_widget *w,
  1544. struct snd_kcontrol *kcontrol,
  1545. int event)
  1546. {
  1547. struct snd_soc_component *component =
  1548. snd_soc_dapm_to_component(w->dapm);
  1549. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1550. int ret = 0;
  1551. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1552. w->name, event);
  1553. if (SND_SOC_DAPM_EVENT_OFF(event))
  1554. ret = swr_slvdev_datapath_control(
  1555. wcd939x->rx_swr_dev,
  1556. wcd939x->rx_swr_dev->dev_num,
  1557. false);
  1558. return ret;
  1559. }
  1560. static int wcd939x_enable_clsh(struct snd_soc_dapm_widget *w,
  1561. struct snd_kcontrol *kcontrol,
  1562. int event)
  1563. {
  1564. struct snd_soc_component *component =
  1565. snd_soc_dapm_to_component(w->dapm);
  1566. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1567. int mode = wcd939x->hph_mode;
  1568. int ret = 0;
  1569. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1570. w->name, event);
  1571. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1572. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1573. wcd939x_rx_connect_port(component, CLSH,
  1574. SND_SOC_DAPM_EVENT_ON(event));
  1575. }
  1576. if (SND_SOC_DAPM_EVENT_OFF(event))
  1577. ret = swr_slvdev_datapath_control(
  1578. wcd939x->rx_swr_dev,
  1579. wcd939x->rx_swr_dev->dev_num,
  1580. false);
  1581. return ret;
  1582. }
  1583. static int wcd939x_enable_rx1(struct snd_soc_dapm_widget *w,
  1584. struct snd_kcontrol *kcontrol,
  1585. int event)
  1586. {
  1587. struct snd_soc_component *component =
  1588. snd_soc_dapm_to_component(w->dapm);
  1589. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1590. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1591. w->name, event);
  1592. switch (event) {
  1593. case SND_SOC_DAPM_PRE_PMU:
  1594. if (wcd939x->hph_pcm_enabled)
  1595. wcd939x_rx_connect_port(component, HIFI_PCM_L, true);
  1596. else {
  1597. wcd939x_rx_connect_port(component, HPH_L, true);
  1598. if (wcd939x->comp1_enable)
  1599. wcd939x_rx_connect_port(component, COMP_L, true);
  1600. }
  1601. break;
  1602. case SND_SOC_DAPM_POST_PMD:
  1603. if (wcd939x->hph_pcm_enabled)
  1604. wcd939x_rx_connect_port(component, HIFI_PCM_L, false);
  1605. else {
  1606. wcd939x_rx_connect_port(component, HPH_L, false);
  1607. if (wcd939x->comp1_enable)
  1608. wcd939x_rx_connect_port(component, COMP_L, false);
  1609. }
  1610. break;
  1611. };
  1612. return 0;
  1613. }
  1614. static int wcd939x_enable_rx2(struct snd_soc_dapm_widget *w,
  1615. struct snd_kcontrol *kcontrol, int event)
  1616. {
  1617. struct snd_soc_component *component =
  1618. snd_soc_dapm_to_component(w->dapm);
  1619. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1620. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1621. w->name, event);
  1622. switch (event) {
  1623. case SND_SOC_DAPM_PRE_PMU:
  1624. if (wcd939x->hph_pcm_enabled)
  1625. wcd939x_rx_connect_port(component, HIFI_PCM_R, true);
  1626. else {
  1627. wcd939x_rx_connect_port(component, HPH_R, true);
  1628. if (wcd939x->comp2_enable)
  1629. wcd939x_rx_connect_port(component, COMP_R, true);
  1630. }
  1631. break;
  1632. case SND_SOC_DAPM_POST_PMD:
  1633. if (wcd939x->hph_pcm_enabled)
  1634. wcd939x_rx_connect_port(component, HIFI_PCM_R, false);
  1635. else {
  1636. wcd939x_rx_connect_port(component, HPH_R, false);
  1637. if (wcd939x->comp2_enable)
  1638. wcd939x_rx_connect_port(component, COMP_R, false);
  1639. }
  1640. break;
  1641. };
  1642. return 0;
  1643. }
  1644. static int wcd939x_enable_rx3(struct snd_soc_dapm_widget *w,
  1645. struct snd_kcontrol *kcontrol,
  1646. int event)
  1647. {
  1648. struct snd_soc_component *component =
  1649. snd_soc_dapm_to_component(w->dapm);
  1650. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1651. w->name, event);
  1652. switch (event) {
  1653. case SND_SOC_DAPM_PRE_PMU:
  1654. wcd939x_rx_connect_port(component, LO, true);
  1655. break;
  1656. case SND_SOC_DAPM_POST_PMD:
  1657. wcd939x_rx_connect_port(component, LO, false);
  1658. /* 6 msec delay as per HW requirement */
  1659. usleep_range(6000, 6010);
  1660. break;
  1661. }
  1662. return 0;
  1663. }
  1664. static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1665. struct snd_kcontrol *kcontrol,
  1666. int event)
  1667. {
  1668. struct snd_soc_component *component =
  1669. snd_soc_dapm_to_component(w->dapm);
  1670. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1671. u16 dmic_clk_reg, dmic_clk_en_reg;
  1672. s32 *dmic_clk_cnt;
  1673. u8 dmic_ctl_shift = 0;
  1674. u8 dmic_clk_shift = 0;
  1675. u8 dmic_clk_mask = 0;
  1676. u16 dmic2_left_en = 0;
  1677. int ret = 0;
  1678. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1679. w->name, event);
  1680. switch (w->shift) {
  1681. case 0:
  1682. case 1:
  1683. dmic_clk_cnt = &(wcd939x->dmic_0_1_clk_cnt);
  1684. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_1_2;
  1685. dmic_clk_en_reg = WCD939X_CDC_DMIC1_CTL;
  1686. dmic_clk_mask = 0x0F;
  1687. dmic_clk_shift = 0x00;
  1688. dmic_ctl_shift = 0x00;
  1689. break;
  1690. case 2:
  1691. dmic2_left_en = WCD939X_CDC_DMIC2_CTL;
  1692. fallthrough;
  1693. case 3:
  1694. dmic_clk_cnt = &(wcd939x->dmic_2_3_clk_cnt);
  1695. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_1_2;
  1696. dmic_clk_en_reg = WCD939X_CDC_DMIC2_CTL;
  1697. dmic_clk_mask = 0xF0;
  1698. dmic_clk_shift = 0x04;
  1699. dmic_ctl_shift = 0x01;
  1700. break;
  1701. case 4:
  1702. case 5:
  1703. dmic_clk_cnt = &(wcd939x->dmic_4_5_clk_cnt);
  1704. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_3_4;
  1705. dmic_clk_en_reg = WCD939X_CDC_DMIC3_CTL;
  1706. dmic_clk_mask = 0x0F;
  1707. dmic_clk_shift = 0x00;
  1708. dmic_ctl_shift = 0x02;
  1709. break;
  1710. case 6:
  1711. case 7:
  1712. dmic_clk_cnt = &(wcd939x->dmic_6_7_clk_cnt);
  1713. dmic_clk_reg = WCD939X_CDC_DMIC_RATE_3_4;
  1714. dmic_clk_en_reg = WCD939X_CDC_DMIC4_CTL;
  1715. dmic_clk_mask = 0xF0;
  1716. dmic_clk_shift = 0x04;
  1717. dmic_ctl_shift = 0x03;
  1718. break;
  1719. default:
  1720. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  1721. __func__);
  1722. return -EINVAL;
  1723. };
  1724. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1725. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1726. switch (event) {
  1727. case SND_SOC_DAPM_PRE_PMU:
  1728. snd_soc_component_update_bits(component,
  1729. WCD939X_CDC_AMIC_CTL,
  1730. (0x01 << dmic_ctl_shift), 0x00);
  1731. /* 250us sleep as per HW requirement */
  1732. usleep_range(250, 260);
  1733. if (dmic2_left_en)
  1734. snd_soc_component_update_bits(component,
  1735. dmic2_left_en, 0x80, 0x80);
  1736. /* Setting DMIC clock rate to 2.4MHz */
  1737. snd_soc_component_update_bits(component,
  1738. dmic_clk_reg, dmic_clk_mask,
  1739. (0x03 << dmic_clk_shift));
  1740. snd_soc_component_update_bits(component,
  1741. dmic_clk_en_reg, 0x08, 0x08);
  1742. /* enable clock scaling */
  1743. snd_soc_component_update_bits(component,
  1744. REG_FIELD_VALUE(CDC_DMIC_CTL, CLK_SCALE_EN, 0x01));
  1745. snd_soc_component_update_bits(component,
  1746. REG_FIELD_VALUE(CDC_DMIC_CTL, DMIC_DIV_BAK_EN, 0x01));
  1747. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  1748. wcd939x->tx_swr_dev->dev_num,
  1749. true);
  1750. break;
  1751. case SND_SOC_DAPM_POST_PMD:
  1752. wcd939x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1753. false);
  1754. snd_soc_component_update_bits(component,
  1755. WCD939X_CDC_AMIC_CTL,
  1756. (0x01 << dmic_ctl_shift),
  1757. (0x01 << dmic_ctl_shift));
  1758. if (dmic2_left_en)
  1759. snd_soc_component_update_bits(component,
  1760. dmic2_left_en, 0x80, 0x00);
  1761. snd_soc_component_update_bits(component,
  1762. dmic_clk_en_reg, 0x08, 0x00);
  1763. break;
  1764. };
  1765. return ret;
  1766. }
  1767. /*
  1768. * wcd939x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1769. * @micb_mv: micbias in mv
  1770. *
  1771. * return register value converted
  1772. */
  1773. int wcd939x_get_micb_vout_ctl_val(u32 micb_mv)
  1774. {
  1775. /* min micbias voltage is 1V and maximum is 2.85V */
  1776. if (micb_mv < 1000 || micb_mv > 2850) {
  1777. pr_err_ratelimited("%s: unsupported micbias voltage\n", __func__);
  1778. return -EINVAL;
  1779. }
  1780. return (micb_mv - 1000) / 50;
  1781. }
  1782. EXPORT_SYMBOL(wcd939x_get_micb_vout_ctl_val);
  1783. /*
  1784. * wcd939x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1785. * @component: handle to snd_soc_component *
  1786. * @req_volt: micbias voltage to be set
  1787. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1788. *
  1789. * return 0 if adjustment is success or error code in case of failure
  1790. */
  1791. int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1792. int req_volt, int micb_num)
  1793. {
  1794. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1795. int cur_vout_ctl, req_vout_ctl;
  1796. int micb_reg, micb_val, micb_en;
  1797. int ret = 0;
  1798. switch (micb_num) {
  1799. case MIC_BIAS_1:
  1800. micb_reg = WCD939X_MICB1;
  1801. break;
  1802. case MIC_BIAS_2:
  1803. micb_reg = WCD939X_MICB2;
  1804. break;
  1805. case MIC_BIAS_3:
  1806. micb_reg = WCD939X_MICB3;
  1807. break;
  1808. case MIC_BIAS_4:
  1809. micb_reg = WCD939X_MICB4;
  1810. break;
  1811. default:
  1812. return -EINVAL;
  1813. }
  1814. mutex_lock(&wcd939x->micb_lock);
  1815. /*
  1816. * If requested micbias voltage is same as current micbias
  1817. * voltage, then just return. Otherwise, adjust voltage as
  1818. * per requested value. If micbias is already enabled, then
  1819. * to avoid slow micbias ramp-up or down enable pull-up
  1820. * momentarily, change the micbias value and then re-enable
  1821. * micbias.
  1822. */
  1823. micb_val = snd_soc_component_read(component, micb_reg);
  1824. micb_en = (micb_val & 0xC0) >> 6;
  1825. cur_vout_ctl = micb_val & 0x3F;
  1826. req_vout_ctl = wcd939x_get_micb_vout_ctl_val(req_volt);
  1827. if (req_vout_ctl < 0) {
  1828. ret = -EINVAL;
  1829. goto exit;
  1830. }
  1831. if (cur_vout_ctl == req_vout_ctl) {
  1832. ret = 0;
  1833. goto exit;
  1834. }
  1835. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1836. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1837. req_volt, micb_en);
  1838. if (micb_en == 0x1)
  1839. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1840. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1841. if (micb_en == 0x1) {
  1842. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1843. /*
  1844. * Add 2ms delay as per HW requirement after enabling
  1845. * micbias
  1846. */
  1847. usleep_range(2000, 2100);
  1848. }
  1849. exit:
  1850. mutex_unlock(&wcd939x->micb_lock);
  1851. return ret;
  1852. }
  1853. EXPORT_SYMBOL(wcd939x_mbhc_micb_adjust_voltage);
  1854. static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1855. struct snd_kcontrol *kcontrol,
  1856. int event)
  1857. {
  1858. struct snd_soc_component *component =
  1859. snd_soc_dapm_to_component(w->dapm);
  1860. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  1861. int ret = 0;
  1862. int bank = 0;
  1863. u8 mode = 0;
  1864. int i = 0;
  1865. int rate = 0;
  1866. bank = (wcd939x_swr_slv_get_current_bank(wcd939x->tx_swr_dev,
  1867. wcd939x->tx_swr_dev->dev_num) ? 0 : 1);
  1868. /* power mode is applicable only to analog mics */
  1869. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1870. /* Get channel rate */
  1871. rate = wcd939x_get_clk_rate(wcd939x->tx_mode[w->shift - ADC1]);
  1872. }
  1873. switch (event) {
  1874. case SND_SOC_DAPM_PRE_PMU:
  1875. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1876. if (w->shift == ADC2 &&
  1877. (((snd_soc_component_read(component, WCD939X_TX_CH12_MUX) &
  1878. 0x38) >> 3) == 0x2)) {
  1879. if (!wcd939x->bcs_dis) {
  1880. wcd939x_tx_connect_port(component, MBHC,
  1881. SWR_CLK_RATE_4P8MHZ, true);
  1882. set_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask);
  1883. }
  1884. }
  1885. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1886. set_bit(w->shift - ADC1, &wcd939x->status_mask);
  1887. wcd939x_tx_connect_port(component, w->shift, rate,
  1888. true);
  1889. } else {
  1890. wcd939x_tx_connect_port(component, w->shift,
  1891. SWR_CLK_RATE_2P4MHZ, true);
  1892. }
  1893. break;
  1894. case SND_SOC_DAPM_POST_PMD:
  1895. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1896. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1897. clear_bit(WCD_ADC1, &wcd939x->status_mask);
  1898. clear_bit(WCD_ADC1_MODE, &wcd939x->status_mask);
  1899. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1900. clear_bit(WCD_ADC2, &wcd939x->status_mask);
  1901. clear_bit(WCD_ADC2_MODE, &wcd939x->status_mask);
  1902. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1903. clear_bit(WCD_ADC3, &wcd939x->status_mask);
  1904. clear_bit(WCD_ADC3_MODE, &wcd939x->status_mask);
  1905. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1906. clear_bit(WCD_ADC4, &wcd939x->status_mask);
  1907. clear_bit(WCD_ADC4_MODE, &wcd939x->status_mask);
  1908. }
  1909. }
  1910. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1911. if (test_bit(WCD_ADC1, &wcd939x->status_mask) ||
  1912. test_bit(WCD_ADC1_MODE, &wcd939x->status_mask))
  1913. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
  1914. if (test_bit(WCD_ADC2, &wcd939x->status_mask) ||
  1915. test_bit(WCD_ADC2_MODE, &wcd939x->status_mask))
  1916. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
  1917. if (test_bit(WCD_ADC3, &wcd939x->status_mask) ||
  1918. test_bit(WCD_ADC3_MODE, &wcd939x->status_mask))
  1919. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
  1920. if (test_bit(WCD_ADC4, &wcd939x->status_mask) ||
  1921. test_bit(WCD_ADC4_MODE, &wcd939x->status_mask))
  1922. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
  1923. if (mode != 0) {
  1924. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1925. if (mode & (1 << i)) {
  1926. i++;
  1927. break;
  1928. }
  1929. }
  1930. }
  1931. rate = wcd939x_get_clk_rate(i);
  1932. if (wcd939x->adc_count) {
  1933. rate = (wcd939x->adc_count * rate);
  1934. if (rate > SWR_CLK_RATE_9P6MHZ)
  1935. rate = SWR_CLK_RATE_9P6MHZ;
  1936. }
  1937. wcd939x_set_swr_clk_rate(component, rate, bank);
  1938. }
  1939. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  1940. wcd939x->tx_swr_dev->dev_num,
  1941. false);
  1942. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1943. wcd939x_set_swr_clk_rate(component, rate, !bank);
  1944. break;
  1945. };
  1946. return ret;
  1947. }
  1948. static int wcd939x_get_adc_mode(int val)
  1949. {
  1950. int ret = 0;
  1951. switch (val) {
  1952. case ADC_MODE_INVALID:
  1953. ret = ADC_MODE_VAL_NORMAL;
  1954. break;
  1955. case ADC_MODE_HIFI:
  1956. ret = ADC_MODE_VAL_HIFI;
  1957. break;
  1958. case ADC_MODE_LO_HIF:
  1959. ret = ADC_MODE_VAL_LO_HIF;
  1960. break;
  1961. case ADC_MODE_NORMAL:
  1962. ret = ADC_MODE_VAL_NORMAL;
  1963. break;
  1964. case ADC_MODE_LP:
  1965. ret = ADC_MODE_VAL_LP;
  1966. break;
  1967. case ADC_MODE_ULP1:
  1968. ret = ADC_MODE_VAL_ULP1;
  1969. break;
  1970. case ADC_MODE_ULP2:
  1971. ret = ADC_MODE_VAL_ULP2;
  1972. break;
  1973. default:
  1974. ret = -EINVAL;
  1975. pr_err_ratelimited("%s: invalid ADC mode value %d\n", __func__, val);
  1976. break;
  1977. }
  1978. return ret;
  1979. }
  1980. int wcd939x_tx_channel_config(struct snd_soc_component *component,
  1981. int channel, int mode)
  1982. {
  1983. int reg = WCD939X_TX_CH2, mask = 0, val = 0;
  1984. int ret = 0;
  1985. switch (channel) {
  1986. case 0:
  1987. reg = WCD939X_TX_CH2;
  1988. mask = 0x40;
  1989. break;
  1990. case 1:
  1991. reg = WCD939X_TX_CH2;
  1992. mask = 0x20;
  1993. break;
  1994. case 2:
  1995. reg = WCD939X_TX_CH4;
  1996. mask = 0x40;
  1997. break;
  1998. case 3:
  1999. reg = WCD939X_TX_CH4;
  2000. mask = 0x20;
  2001. break;
  2002. default:
  2003. pr_err_ratelimited("%s: Invalid channel num %d\n", __func__, channel);
  2004. ret = -EINVAL;
  2005. break;
  2006. }
  2007. if (!mode)
  2008. val = 0x00;
  2009. else
  2010. val = mask;
  2011. if (!ret)
  2012. snd_soc_component_update_bits(component, reg, mask, val);
  2013. return ret;
  2014. }
  2015. static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  2016. struct snd_kcontrol *kcontrol,
  2017. int event){
  2018. struct snd_soc_component *component =
  2019. snd_soc_dapm_to_component(w->dapm);
  2020. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2021. int clk_rate = 0, ret = 0;
  2022. int mode = 0, i = 0, bank = 0;
  2023. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2024. w->name, event);
  2025. bank = (wcd939x_swr_slv_get_current_bank(wcd939x->tx_swr_dev,
  2026. wcd939x->tx_swr_dev->dev_num) ? 0 : 1);
  2027. switch (event) {
  2028. case SND_SOC_DAPM_PRE_PMU:
  2029. wcd939x->adc_count++;
  2030. if (test_bit(WCD_ADC1, &wcd939x->status_mask) ||
  2031. test_bit(WCD_ADC1_MODE, &wcd939x->status_mask))
  2032. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
  2033. if (test_bit(WCD_ADC2, &wcd939x->status_mask) ||
  2034. test_bit(WCD_ADC2_MODE, &wcd939x->status_mask))
  2035. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
  2036. if (test_bit(WCD_ADC3, &wcd939x->status_mask) ||
  2037. test_bit(WCD_ADC3_MODE, &wcd939x->status_mask))
  2038. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
  2039. if (test_bit(WCD_ADC4, &wcd939x->status_mask) ||
  2040. test_bit(WCD_ADC4_MODE, &wcd939x->status_mask))
  2041. mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
  2042. if (mode != 0) {
  2043. for (i = 0; i < ADC_MODE_ULP2; i++) {
  2044. if (mode & (1 << i)) {
  2045. i++;
  2046. break;
  2047. }
  2048. }
  2049. }
  2050. clk_rate = wcd939x_get_clk_rate(i);
  2051. /* clk_rate depends on number of paths getting enabled */
  2052. clk_rate = (wcd939x->adc_count * clk_rate);
  2053. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  2054. clk_rate = SWR_CLK_RATE_9P6MHZ;
  2055. wcd939x_set_swr_clk_rate(component, clk_rate, bank);
  2056. ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
  2057. wcd939x->tx_swr_dev->dev_num,
  2058. true);
  2059. wcd939x_set_swr_clk_rate(component, clk_rate, !bank);
  2060. break;
  2061. case SND_SOC_DAPM_POST_PMD:
  2062. wcd939x->adc_count--;
  2063. if (wcd939x->adc_count < 0)
  2064. wcd939x->adc_count = 0;
  2065. wcd939x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  2066. if (w->shift + ADC1 == ADC2 &&
  2067. test_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask)) {
  2068. wcd939x_tx_connect_port(component, MBHC, 0,
  2069. false);
  2070. clear_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask);
  2071. }
  2072. break;
  2073. };
  2074. return ret;
  2075. }
  2076. void wcd939x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  2077. bool bcs_disable)
  2078. {
  2079. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2080. if (wcd939x->update_wcd_event) {
  2081. if (bcs_disable)
  2082. wcd939x->update_wcd_event(wcd939x->handle,
  2083. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  2084. else
  2085. wcd939x->update_wcd_event(wcd939x->handle,
  2086. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  2087. }
  2088. }
  2089. static int wcd939x_enable_req(struct snd_soc_dapm_widget *w,
  2090. struct snd_kcontrol *kcontrol, int event)
  2091. {
  2092. struct snd_soc_component *component =
  2093. snd_soc_dapm_to_component(w->dapm);
  2094. struct wcd939x_priv *wcd939x =
  2095. snd_soc_component_get_drvdata(component);
  2096. int ret = 0;
  2097. u8 mode = 0;
  2098. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2099. w->name, event);
  2100. switch (event) {
  2101. case SND_SOC_DAPM_PRE_PMU:
  2102. snd_soc_component_update_bits(component,
  2103. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_CLK_EN, 0x01));
  2104. snd_soc_component_update_bits(component,
  2105. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x01));
  2106. snd_soc_component_update_bits(component,
  2107. REG_FIELD_VALUE(CDC_REQ_CTL, FS_RATE_4P8, 0x01));
  2108. snd_soc_component_update_bits(component,
  2109. REG_FIELD_VALUE(CDC_REQ_CTL, NO_NOTCH, 0x00));
  2110. ret = wcd939x_tx_channel_config(component, w->shift, 1);
  2111. mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]);
  2112. if (mode < 0) {
  2113. dev_info_ratelimited(component->dev,
  2114. "%s: invalid mode, setting to normal mode\n",
  2115. __func__);
  2116. mode = ADC_MODE_VAL_NORMAL;
  2117. }
  2118. switch (w->shift) {
  2119. case 0:
  2120. snd_soc_component_update_bits(component,
  2121. WCD939X_CDC_TX_ANA_MODE_0_1, 0x0F,
  2122. mode);
  2123. snd_soc_component_update_bits(component,
  2124. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD0_CLK_EN, 0x01));
  2125. break;
  2126. case 1:
  2127. snd_soc_component_update_bits(component,
  2128. WCD939X_CDC_TX_ANA_MODE_0_1, 0xF0,
  2129. mode << 4);
  2130. snd_soc_component_update_bits(component,
  2131. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD1_CLK_EN, 0x01));
  2132. break;
  2133. case 2:
  2134. snd_soc_component_update_bits(component,
  2135. WCD939X_CDC_TX_ANA_MODE_2_3, 0x0F,
  2136. mode);
  2137. snd_soc_component_update_bits(component,
  2138. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD2_CLK_EN, 0x01));
  2139. break;
  2140. case 3:
  2141. snd_soc_component_update_bits(component,
  2142. WCD939X_CDC_TX_ANA_MODE_2_3, 0xF0,
  2143. mode << 4);
  2144. snd_soc_component_update_bits(component,
  2145. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD3_CLK_EN, 0x01));
  2146. break;
  2147. default:
  2148. break;
  2149. }
  2150. ret |= wcd939x_tx_channel_config(component, w->shift, 0);
  2151. break;
  2152. case SND_SOC_DAPM_POST_PMD:
  2153. switch (w->shift) {
  2154. case 0:
  2155. snd_soc_component_update_bits(component,
  2156. REG_FIELD_VALUE(CDC_TX_ANA_MODE_0_1, TXD0_MODE, 0x00));
  2157. snd_soc_component_update_bits(component,
  2158. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD0_CLK_EN, 0x00));
  2159. break;
  2160. case 1:
  2161. snd_soc_component_update_bits(component,
  2162. REG_FIELD_VALUE(CDC_TX_ANA_MODE_0_1, TXD1_MODE, 0x00));
  2163. snd_soc_component_update_bits(component,
  2164. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD1_CLK_EN, 0x00));
  2165. break;
  2166. case 2:
  2167. snd_soc_component_update_bits(component,
  2168. REG_FIELD_VALUE(CDC_TX_ANA_MODE_2_3, TXD2_MODE, 0x00));
  2169. snd_soc_component_update_bits(component,
  2170. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD2_CLK_EN, 0x00));
  2171. break;
  2172. case 3:
  2173. snd_soc_component_update_bits(component,
  2174. REG_FIELD_VALUE(CDC_TX_ANA_MODE_2_3, TXD3_MODE, 0x00));
  2175. snd_soc_component_update_bits(component,
  2176. REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD3_CLK_EN, 0x00));
  2177. break;
  2178. default:
  2179. break;
  2180. }
  2181. if (wcd939x->adc_count == 0) {
  2182. snd_soc_component_update_bits(component,
  2183. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x00));
  2184. snd_soc_component_update_bits(component,
  2185. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_CLK_EN, 0x00));
  2186. }
  2187. break;
  2188. };
  2189. return ret;
  2190. }
  2191. int wcd939x_micbias_control(struct snd_soc_component *component,
  2192. int micb_num, int req, bool is_dapm)
  2193. {
  2194. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2195. int micb_index = micb_num - 1;
  2196. u16 micb_reg;
  2197. int pre_off_event = 0, post_off_event = 0;
  2198. int post_on_event = 0, post_dapm_off = 0;
  2199. int post_dapm_on = 0;
  2200. int ret = 0;
  2201. if ((micb_index < 0) || (micb_index > WCD939X_MAX_MICBIAS - 1)) {
  2202. dev_err_ratelimited(component->dev,
  2203. "%s: Invalid micbias index, micb_ind:%d\n",
  2204. __func__, micb_index);
  2205. return -EINVAL;
  2206. }
  2207. if (NULL == wcd939x) {
  2208. dev_err_ratelimited(component->dev,
  2209. "%s: wcd939x private data is NULL\n", __func__);
  2210. return -EINVAL;
  2211. }
  2212. switch (micb_num) {
  2213. case MIC_BIAS_1:
  2214. micb_reg = WCD939X_MICB1;
  2215. break;
  2216. case MIC_BIAS_2:
  2217. micb_reg = WCD939X_MICB2;
  2218. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  2219. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  2220. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  2221. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  2222. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  2223. break;
  2224. case MIC_BIAS_3:
  2225. micb_reg = WCD939X_MICB3;
  2226. break;
  2227. case MIC_BIAS_4:
  2228. micb_reg = WCD939X_MICB4;
  2229. break;
  2230. default:
  2231. dev_err_ratelimited(component->dev, "%s: Invalid micbias number: %d\n",
  2232. __func__, micb_num);
  2233. return -EINVAL;
  2234. };
  2235. mutex_lock(&wcd939x->micb_lock);
  2236. switch (req) {
  2237. case MICB_PULLUP_ENABLE:
  2238. if (!wcd939x->dev_up) {
  2239. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2240. __func__, req);
  2241. ret = -ENODEV;
  2242. goto done;
  2243. }
  2244. wcd939x->pullup_ref[micb_index]++;
  2245. if ((wcd939x->pullup_ref[micb_index] == 1) &&
  2246. (wcd939x->micb_ref[micb_index] == 0))
  2247. snd_soc_component_update_bits(component, micb_reg,
  2248. 0xC0, 0x80);
  2249. break;
  2250. case MICB_PULLUP_DISABLE:
  2251. if (wcd939x->pullup_ref[micb_index] > 0)
  2252. wcd939x->pullup_ref[micb_index]--;
  2253. if (!wcd939x->dev_up) {
  2254. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2255. __func__, req);
  2256. ret = -ENODEV;
  2257. goto done;
  2258. }
  2259. if ((wcd939x->pullup_ref[micb_index] == 0) &&
  2260. (wcd939x->micb_ref[micb_index] == 0))
  2261. snd_soc_component_update_bits(component, micb_reg,
  2262. 0xC0, 0x00);
  2263. break;
  2264. case MICB_ENABLE:
  2265. if (!wcd939x->dev_up) {
  2266. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2267. __func__, req);
  2268. ret = -ENODEV;
  2269. goto done;
  2270. }
  2271. wcd939x->micb_ref[micb_index]++;
  2272. if (wcd939x->micb_ref[micb_index] == 1) {
  2273. snd_soc_component_update_bits(component,
  2274. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD3_CLK_EN, 0x01));
  2275. snd_soc_component_update_bits(component,
  2276. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD2_CLK_EN, 0x01));
  2277. snd_soc_component_update_bits(component,
  2278. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD1_CLK_EN, 0x01));
  2279. snd_soc_component_update_bits(component,
  2280. REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD0_CLK_EN, 0x01));
  2281. snd_soc_component_update_bits(component,
  2282. REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x01));
  2283. snd_soc_component_update_bits(component,
  2284. REG_FIELD_VALUE(CDC_ANA_TX_CLK_CTL, ANA_TXSCBIAS_CLK_EN, 0x01));
  2285. snd_soc_component_update_bits(component,
  2286. REG_FIELD_VALUE(TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2287. snd_soc_component_update_bits(component,
  2288. REG_FIELD_VALUE(MICB2_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2289. snd_soc_component_update_bits(component,
  2290. REG_FIELD_VALUE(MICB3_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2291. snd_soc_component_update_bits(component,
  2292. REG_FIELD_VALUE(MICB4_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
  2293. snd_soc_component_update_bits(component,
  2294. micb_reg, 0xC0, 0x40);
  2295. if (post_on_event)
  2296. blocking_notifier_call_chain(
  2297. &wcd939x->mbhc->notifier,
  2298. post_on_event,
  2299. &wcd939x->mbhc->wcd_mbhc);
  2300. }
  2301. if (is_dapm && post_dapm_on && wcd939x->mbhc)
  2302. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  2303. post_dapm_on,
  2304. &wcd939x->mbhc->wcd_mbhc);
  2305. break;
  2306. case MICB_DISABLE:
  2307. if (wcd939x->micb_ref[micb_index] > 0)
  2308. wcd939x->micb_ref[micb_index]--;
  2309. if (!wcd939x->dev_up) {
  2310. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  2311. __func__, req);
  2312. ret = -ENODEV;
  2313. goto done;
  2314. }
  2315. if ((wcd939x->micb_ref[micb_index] == 0) &&
  2316. (wcd939x->pullup_ref[micb_index] > 0))
  2317. snd_soc_component_update_bits(component, micb_reg,
  2318. 0xC0, 0x80);
  2319. else if ((wcd939x->micb_ref[micb_index] == 0) &&
  2320. (wcd939x->pullup_ref[micb_index] == 0)) {
  2321. if (pre_off_event && wcd939x->mbhc)
  2322. blocking_notifier_call_chain(
  2323. &wcd939x->mbhc->notifier,
  2324. pre_off_event,
  2325. &wcd939x->mbhc->wcd_mbhc);
  2326. snd_soc_component_update_bits(component, micb_reg,
  2327. 0xC0, 0x00);
  2328. if (post_off_event && wcd939x->mbhc)
  2329. blocking_notifier_call_chain(
  2330. &wcd939x->mbhc->notifier,
  2331. post_off_event,
  2332. &wcd939x->mbhc->wcd_mbhc);
  2333. }
  2334. if (is_dapm && post_dapm_off && wcd939x->mbhc)
  2335. blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
  2336. post_dapm_off,
  2337. &wcd939x->mbhc->wcd_mbhc);
  2338. break;
  2339. };
  2340. dev_dbg(component->dev,
  2341. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  2342. __func__, micb_num, wcd939x->micb_ref[micb_index],
  2343. wcd939x->pullup_ref[micb_index]);
  2344. done:
  2345. mutex_unlock(&wcd939x->micb_lock);
  2346. return ret;
  2347. }
  2348. EXPORT_SYMBOL(wcd939x_micbias_control);
  2349. static int wcd939x_get_logical_addr(struct swr_device *swr_dev)
  2350. {
  2351. int ret = 0;
  2352. uint8_t devnum = 0;
  2353. int num_retry = NUM_ATTEMPTS;
  2354. do {
  2355. /* retry after 1ms */
  2356. usleep_range(1000, 1010);
  2357. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  2358. } while (ret && --num_retry);
  2359. if (ret)
  2360. dev_err_ratelimited(&swr_dev->dev,
  2361. "%s get devnum %d for dev addr %llx failed\n",
  2362. __func__, devnum, swr_dev->addr);
  2363. swr_dev->dev_num = devnum;
  2364. return 0;
  2365. }
  2366. static bool get_usbc_hs_status(struct snd_soc_component *component,
  2367. struct wcd_mbhc_config *mbhc_cfg)
  2368. {
  2369. if (mbhc_cfg->enable_usbc_analog) {
  2370. if (!(snd_soc_component_read(component, WCD939X_MBHC_MECH)
  2371. & 0x20))
  2372. return true;
  2373. }
  2374. return false;
  2375. }
  2376. int wcd939x_swr_dmic_register_notifier(struct snd_soc_component *component,
  2377. struct notifier_block *nblock,
  2378. bool enable)
  2379. {
  2380. struct wcd939x_priv *wcd939x_priv;
  2381. if(NULL == component) {
  2382. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2383. return -EINVAL;
  2384. }
  2385. wcd939x_priv = snd_soc_component_get_drvdata(component);
  2386. wcd939x_priv->notify_swr_dmic = enable;
  2387. if (enable)
  2388. return blocking_notifier_chain_register(&wcd939x_priv->notifier,
  2389. nblock);
  2390. else
  2391. return blocking_notifier_chain_unregister(
  2392. &wcd939x_priv->notifier, nblock);
  2393. }
  2394. EXPORT_SYMBOL(wcd939x_swr_dmic_register_notifier);
  2395. static int wcd939x_event_notify(struct notifier_block *block,
  2396. unsigned long val,
  2397. void *data)
  2398. {
  2399. u16 event = (val & 0xffff);
  2400. int ret = 0;
  2401. int rx_clk_type;
  2402. struct wcd939x_priv *wcd939x = dev_get_drvdata((struct device *)data);
  2403. struct snd_soc_component *component = wcd939x->component;
  2404. struct wcd_mbhc *mbhc;
  2405. switch (event) {
  2406. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2407. if (test_bit(WCD_ADC1, &wcd939x->status_mask)) {
  2408. snd_soc_component_update_bits(component,
  2409. REG_FIELD_VALUE(TX_CH2, HPF1_INIT, 0x00));
  2410. set_bit(WCD_ADC1_MODE, &wcd939x->status_mask);
  2411. clear_bit(WCD_ADC1, &wcd939x->status_mask);
  2412. }
  2413. if (test_bit(WCD_ADC2, &wcd939x->status_mask)) {
  2414. snd_soc_component_update_bits(component,
  2415. REG_FIELD_VALUE(TX_CH2, HPF2_INIT, 0x00));
  2416. set_bit(WCD_ADC2_MODE, &wcd939x->status_mask);
  2417. clear_bit(WCD_ADC2, &wcd939x->status_mask);
  2418. }
  2419. if (test_bit(WCD_ADC3, &wcd939x->status_mask)) {
  2420. snd_soc_component_update_bits(component,
  2421. REG_FIELD_VALUE(TX_CH4, HPF3_INIT, 0x00));
  2422. set_bit(WCD_ADC3_MODE, &wcd939x->status_mask);
  2423. clear_bit(WCD_ADC3, &wcd939x->status_mask);
  2424. }
  2425. if (test_bit(WCD_ADC4, &wcd939x->status_mask)) {
  2426. snd_soc_component_update_bits(component,
  2427. REG_FIELD_VALUE(TX_CH4, HPF4_INIT, 0x00));
  2428. set_bit(WCD_ADC4_MODE, &wcd939x->status_mask);
  2429. clear_bit(WCD_ADC4, &wcd939x->status_mask);
  2430. }
  2431. break;
  2432. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2433. snd_soc_component_update_bits(component,
  2434. REG_FIELD_VALUE(HPH, HPHL_ENABLE, 0x00));
  2435. snd_soc_component_update_bits(component,
  2436. REG_FIELD_VALUE(HPH, HPHR_ENABLE , 0x00));
  2437. snd_soc_component_update_bits(component,
  2438. REG_FIELD_VALUE(EAR, ENABLE, 0x00));
  2439. break;
  2440. case BOLERO_SLV_EVT_SSR_DOWN:
  2441. wcd939x->dev_up = false;
  2442. if(wcd939x->notify_swr_dmic)
  2443. blocking_notifier_call_chain(&wcd939x->notifier,
  2444. WCD939X_EVT_SSR_DOWN,
  2445. NULL);
  2446. wcd939x->mbhc->wcd_mbhc.deinit_in_progress = true;
  2447. mbhc = &wcd939x->mbhc->wcd_mbhc;
  2448. wcd939x->usbc_hs_status = get_usbc_hs_status(component,
  2449. mbhc->mbhc_cfg);
  2450. wcd939x_mbhc_ssr_down(wcd939x->mbhc, component);
  2451. wcd939x_reset_low(wcd939x->dev);
  2452. break;
  2453. case BOLERO_SLV_EVT_SSR_UP:
  2454. wcd939x_reset(wcd939x->dev);
  2455. /* allow reset to take effect */
  2456. usleep_range(10000, 10010);
  2457. wcd939x_get_logical_addr(wcd939x->tx_swr_dev);
  2458. wcd939x_get_logical_addr(wcd939x->rx_swr_dev);
  2459. wcd939x_init_reg(component);
  2460. regcache_mark_dirty(wcd939x->regmap);
  2461. regcache_sync(wcd939x->regmap);
  2462. /* Initialize MBHC module */
  2463. mbhc = &wcd939x->mbhc->wcd_mbhc;
  2464. ret = wcd939x_mbhc_post_ssr_init(wcd939x->mbhc, component);
  2465. if (ret) {
  2466. dev_err_ratelimited(component->dev, "%s: mbhc initialization failed\n",
  2467. __func__);
  2468. } else {
  2469. wcd939x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2470. }
  2471. wcd939x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2472. wcd939x->dev_up = true;
  2473. if(wcd939x->notify_swr_dmic)
  2474. blocking_notifier_call_chain(&wcd939x->notifier,
  2475. WCD939X_EVT_SSR_UP,
  2476. NULL);
  2477. if (wcd939x->usbc_hs_status)
  2478. mdelay(500);
  2479. break;
  2480. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2481. snd_soc_component_update_bits(component,
  2482. WCD939X_TOP_CLK_CFG, 0x06,
  2483. ((val >> 0x10) << 0x01));
  2484. rx_clk_type = (val >> 0x10);
  2485. switch(rx_clk_type) {
  2486. case RX_CLK_12P288MHZ:
  2487. wcd939x->rx_clk_config = RX_CLK_12P288MHZ;
  2488. break;
  2489. case RX_CLK_11P2896MHZ:
  2490. wcd939x->rx_clk_config = RX_CLK_11P2896MHZ;
  2491. break;
  2492. default:
  2493. wcd939x->rx_clk_config = RX_CLK_9P6MHZ;
  2494. break;
  2495. }
  2496. dev_dbg(component->dev, "%s: rx clk config %d\n", __func__, wcd939x->rx_clk_config);
  2497. break;
  2498. default:
  2499. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2500. break;
  2501. }
  2502. return 0;
  2503. }
  2504. static int __wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2505. int event)
  2506. {
  2507. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2508. int micb_num;
  2509. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2510. __func__, w->name, event);
  2511. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2512. micb_num = MIC_BIAS_1;
  2513. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2514. micb_num = MIC_BIAS_2;
  2515. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2516. micb_num = MIC_BIAS_3;
  2517. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2518. micb_num = MIC_BIAS_4;
  2519. else
  2520. return -EINVAL;
  2521. switch (event) {
  2522. case SND_SOC_DAPM_PRE_PMU:
  2523. wcd939x_micbias_control(component, micb_num,
  2524. MICB_ENABLE, true);
  2525. break;
  2526. case SND_SOC_DAPM_POST_PMU:
  2527. /* 1 msec delay as per HW requirement */
  2528. usleep_range(1000, 1100);
  2529. break;
  2530. case SND_SOC_DAPM_POST_PMD:
  2531. wcd939x_micbias_control(component, micb_num,
  2532. MICB_DISABLE, true);
  2533. break;
  2534. };
  2535. return 0;
  2536. }
  2537. static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2538. struct snd_kcontrol *kcontrol,
  2539. int event)
  2540. {
  2541. return __wcd939x_codec_enable_micbias(w, event);
  2542. }
  2543. static int __wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2544. int event)
  2545. {
  2546. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2547. int micb_num;
  2548. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2549. __func__, w->name, event);
  2550. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2551. micb_num = MIC_BIAS_1;
  2552. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2553. micb_num = MIC_BIAS_2;
  2554. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2555. micb_num = MIC_BIAS_3;
  2556. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2557. micb_num = MIC_BIAS_4;
  2558. else
  2559. return -EINVAL;
  2560. switch (event) {
  2561. case SND_SOC_DAPM_PRE_PMU:
  2562. wcd939x_micbias_control(component, micb_num,
  2563. MICB_PULLUP_ENABLE, true);
  2564. break;
  2565. case SND_SOC_DAPM_POST_PMU:
  2566. /* 1 msec delay as per HW requirement */
  2567. usleep_range(1000, 1100);
  2568. break;
  2569. case SND_SOC_DAPM_POST_PMD:
  2570. wcd939x_micbias_control(component, micb_num,
  2571. MICB_PULLUP_DISABLE, true);
  2572. break;
  2573. };
  2574. return 0;
  2575. }
  2576. static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2577. struct snd_kcontrol *kcontrol,
  2578. int event)
  2579. {
  2580. return __wcd939x_codec_enable_micbias_pullup(w, event);
  2581. }
  2582. static int wcd939x_wakeup(void *handle, bool enable)
  2583. {
  2584. struct wcd939x_priv *priv;
  2585. int ret = 0;
  2586. if (!handle) {
  2587. pr_err_ratelimited("%s: NULL handle\n", __func__);
  2588. return -EINVAL;
  2589. }
  2590. priv = (struct wcd939x_priv *)handle;
  2591. if (!priv->tx_swr_dev) {
  2592. pr_err_ratelimited("%s: tx swr dev is NULL\n", __func__);
  2593. return -EINVAL;
  2594. }
  2595. mutex_lock(&priv->wakeup_lock);
  2596. if (enable)
  2597. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2598. else
  2599. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2600. mutex_unlock(&priv->wakeup_lock);
  2601. return ret;
  2602. }
  2603. static int wcd939x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2604. struct snd_kcontrol *kcontrol,
  2605. int event)
  2606. {
  2607. int ret = 0;
  2608. struct snd_soc_component *component =
  2609. snd_soc_dapm_to_component(w->dapm);
  2610. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2611. switch (event) {
  2612. case SND_SOC_DAPM_PRE_PMU:
  2613. wcd939x_wakeup(wcd939x, true);
  2614. ret = __wcd939x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2615. wcd939x_wakeup(wcd939x, false);
  2616. break;
  2617. case SND_SOC_DAPM_POST_PMD:
  2618. wcd939x_wakeup(wcd939x, true);
  2619. ret = __wcd939x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2620. wcd939x_wakeup(wcd939x, false);
  2621. break;
  2622. }
  2623. return ret;
  2624. }
  2625. static int wcd939x_enable_micbias(struct wcd939x_priv *wcd939x,
  2626. int micb_num, int req)
  2627. {
  2628. int micb_index = micb_num - 1;
  2629. u16 micb_reg;
  2630. if (NULL == wcd939x) {
  2631. pr_err_ratelimited("%s: wcd939x private data is NULL\n", __func__);
  2632. return -EINVAL;
  2633. }
  2634. switch (micb_num) {
  2635. case MIC_BIAS_1:
  2636. micb_reg = WCD939X_MICB1;
  2637. break;
  2638. case MIC_BIAS_2:
  2639. micb_reg = WCD939X_MICB2;
  2640. break;
  2641. case MIC_BIAS_3:
  2642. micb_reg = WCD939X_MICB3;
  2643. break;
  2644. case MIC_BIAS_4:
  2645. micb_reg = WCD939X_MICB4;
  2646. break;
  2647. default:
  2648. pr_err_ratelimited("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2649. return -EINVAL;
  2650. };
  2651. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2652. __func__, req, micb_num, wcd939x->micb_ref[micb_index],
  2653. wcd939x->pullup_ref[micb_index]);
  2654. mutex_lock(&wcd939x->micb_lock);
  2655. switch (req) {
  2656. case MICB_ENABLE:
  2657. wcd939x->micb_ref[micb_index]++;
  2658. if (wcd939x->micb_ref[micb_index] == 1) {
  2659. regmap_update_bits(wcd939x->regmap,
  2660. WCD939X_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2661. regmap_update_bits(wcd939x->regmap,
  2662. WCD939X_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2663. regmap_update_bits(wcd939x->regmap,
  2664. WCD939X_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2665. regmap_update_bits(wcd939x->regmap,
  2666. WCD939X_TEST_CTL_2, 0x01, 0x01);
  2667. regmap_update_bits(wcd939x->regmap,
  2668. WCD939X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2669. regmap_update_bits(wcd939x->regmap,
  2670. WCD939X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2671. regmap_update_bits(wcd939x->regmap,
  2672. WCD939X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2673. regmap_update_bits(wcd939x->regmap,
  2674. micb_reg, 0xC0, 0x40);
  2675. regmap_update_bits(wcd939x->regmap, micb_reg, 0x3F, 0x10);
  2676. }
  2677. break;
  2678. case MICB_PULLUP_ENABLE:
  2679. wcd939x->pullup_ref[micb_index]++;
  2680. if ((wcd939x->pullup_ref[micb_index] == 1) &&
  2681. (wcd939x->micb_ref[micb_index] == 0))
  2682. regmap_update_bits(wcd939x->regmap, micb_reg,
  2683. 0xC0, 0x80);
  2684. break;
  2685. case MICB_PULLUP_DISABLE:
  2686. if (wcd939x->pullup_ref[micb_index] > 0)
  2687. wcd939x->pullup_ref[micb_index]--;
  2688. if ((wcd939x->pullup_ref[micb_index] == 0) &&
  2689. (wcd939x->micb_ref[micb_index] == 0))
  2690. regmap_update_bits(wcd939x->regmap, micb_reg,
  2691. 0xC0, 0x00);
  2692. break;
  2693. case MICB_DISABLE:
  2694. if (wcd939x->micb_ref[micb_index] > 0)
  2695. wcd939x->micb_ref[micb_index]--;
  2696. if ((wcd939x->micb_ref[micb_index] == 0) &&
  2697. (wcd939x->pullup_ref[micb_index] > 0))
  2698. regmap_update_bits(wcd939x->regmap, micb_reg,
  2699. 0xC0, 0x80);
  2700. else if ((wcd939x->micb_ref[micb_index] == 0) &&
  2701. (wcd939x->pullup_ref[micb_index] == 0))
  2702. regmap_update_bits(wcd939x->regmap, micb_reg,
  2703. 0xC0, 0x00);
  2704. break;
  2705. };
  2706. mutex_unlock(&wcd939x->micb_lock);
  2707. return 0;
  2708. }
  2709. int wcd939x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2710. int event, int micb_num)
  2711. {
  2712. struct wcd939x_priv *wcd939x_priv = NULL;
  2713. int ret = 0;
  2714. int micb_index = micb_num - 1;
  2715. if(NULL == component) {
  2716. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2717. return -EINVAL;
  2718. }
  2719. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2720. pr_err_ratelimited("%s: invalid event: %d\n", __func__, event);
  2721. return -EINVAL;
  2722. }
  2723. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2724. pr_err_ratelimited("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2725. return -EINVAL;
  2726. }
  2727. wcd939x_priv = snd_soc_component_get_drvdata(component);
  2728. if (!wcd939x_priv->dev_up) {
  2729. if ((wcd939x_priv->pullup_ref[micb_index] > 0) &&
  2730. (event == SND_SOC_DAPM_POST_PMD)) {
  2731. wcd939x_priv->pullup_ref[micb_index]--;
  2732. ret = -ENODEV;
  2733. goto done;
  2734. }
  2735. }
  2736. switch (event) {
  2737. case SND_SOC_DAPM_PRE_PMU:
  2738. wcd939x_wakeup(wcd939x_priv, true);
  2739. wcd939x_enable_micbias(wcd939x_priv, micb_num, MICB_PULLUP_ENABLE);
  2740. wcd939x_wakeup(wcd939x_priv, false);
  2741. break;
  2742. case SND_SOC_DAPM_POST_PMD:
  2743. wcd939x_wakeup(wcd939x_priv, true);
  2744. wcd939x_enable_micbias(wcd939x_priv, micb_num, MICB_PULLUP_DISABLE);
  2745. wcd939x_wakeup(wcd939x_priv, false);
  2746. break;
  2747. }
  2748. done:
  2749. return ret;
  2750. }
  2751. EXPORT_SYMBOL(wcd939x_codec_force_enable_micbias_v2);
  2752. static inline int wcd939x_tx_path_get(const char *wname,
  2753. unsigned int *path_num)
  2754. {
  2755. int ret = 0;
  2756. char *widget_name = NULL;
  2757. char *w_name = NULL;
  2758. char *path_num_char = NULL;
  2759. char *path_name = NULL;
  2760. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2761. if (!widget_name)
  2762. return -EINVAL;
  2763. w_name = widget_name;
  2764. path_name = strsep(&widget_name, " ");
  2765. if (!path_name) {
  2766. pr_err_ratelimited("%s: Invalid widget name = %s\n",
  2767. __func__, widget_name);
  2768. ret = -EINVAL;
  2769. goto err;
  2770. }
  2771. path_num_char = strpbrk(path_name, "0123");
  2772. if (!path_num_char) {
  2773. pr_err_ratelimited("%s: tx path index not found\n",
  2774. __func__);
  2775. ret = -EINVAL;
  2776. goto err;
  2777. }
  2778. ret = kstrtouint(path_num_char, 10, path_num);
  2779. if (ret < 0)
  2780. pr_err_ratelimited("%s: Invalid tx path = %s\n",
  2781. __func__, w_name);
  2782. err:
  2783. kfree(w_name);
  2784. return ret;
  2785. }
  2786. static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2787. struct snd_ctl_elem_value *ucontrol)
  2788. {
  2789. struct snd_soc_component *component =
  2790. snd_soc_kcontrol_component(kcontrol);
  2791. struct wcd939x_priv *wcd939x = NULL;
  2792. int ret = 0;
  2793. unsigned int path = 0;
  2794. if (!component)
  2795. return -EINVAL;
  2796. wcd939x = snd_soc_component_get_drvdata(component);
  2797. if (!wcd939x)
  2798. return -EINVAL;
  2799. ret = wcd939x_tx_path_get(kcontrol->id.name, &path);
  2800. if (ret < 0)
  2801. return ret;
  2802. ucontrol->value.integer.value[0] = wcd939x->tx_mode[path];
  2803. return 0;
  2804. }
  2805. static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2806. struct snd_ctl_elem_value *ucontrol)
  2807. {
  2808. struct snd_soc_component *component =
  2809. snd_soc_kcontrol_component(kcontrol);
  2810. struct wcd939x_priv *wcd939x = NULL;
  2811. u32 mode_val;
  2812. unsigned int path = 0;
  2813. int ret = 0;
  2814. if (!component)
  2815. return -EINVAL;
  2816. wcd939x = snd_soc_component_get_drvdata(component);
  2817. if (!wcd939x)
  2818. return -EINVAL;
  2819. ret = wcd939x_tx_path_get(kcontrol->id.name, &path);
  2820. if (ret)
  2821. return ret;
  2822. mode_val = ucontrol->value.enumerated.item[0];
  2823. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2824. wcd939x->tx_mode[path] = mode_val;
  2825. return 0;
  2826. }
  2827. static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2828. struct snd_ctl_elem_value *ucontrol)
  2829. {
  2830. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2831. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2832. ucontrol->value.integer.value[0] = wcd939x->hph_mode;
  2833. return 0;
  2834. }
  2835. static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2836. struct snd_ctl_elem_value *ucontrol)
  2837. {
  2838. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2839. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2840. u32 mode_val;
  2841. mode_val = ucontrol->value.enumerated.item[0];
  2842. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2843. if (wcd939x->variant == WCD9390) {
  2844. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2845. dev_info_ratelimited(component->dev,
  2846. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2847. __func__);
  2848. mode_val = CLS_H_ULP;
  2849. }
  2850. }
  2851. if (mode_val == CLS_H_NORMAL) {
  2852. dev_info_ratelimited(component->dev,
  2853. "%s:Invalid HPH Mode, default to class_AB\n",
  2854. __func__);
  2855. mode_val = CLS_H_ULP;
  2856. }
  2857. wcd939x->hph_mode = mode_val;
  2858. return 0;
  2859. }
  2860. static int wcd939x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2861. struct snd_ctl_elem_value *ucontrol)
  2862. {
  2863. u8 ear_pa_gain = 0;
  2864. struct snd_soc_component *component =
  2865. snd_soc_kcontrol_component(kcontrol);
  2866. ear_pa_gain = snd_soc_component_read(component,
  2867. WCD939X_EAR_COMPANDER_CTL);
  2868. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2869. ucontrol->value.integer.value[0] = ear_pa_gain;
  2870. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2871. ear_pa_gain);
  2872. return 0;
  2873. }
  2874. static int wcd939x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2875. struct snd_ctl_elem_value *ucontrol)
  2876. {
  2877. u8 ear_pa_gain = 0;
  2878. struct snd_soc_component *component =
  2879. snd_soc_kcontrol_component(kcontrol);
  2880. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2881. __func__, ucontrol->value.integer.value[0]);
  2882. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2883. snd_soc_component_update_bits(component,
  2884. WCD939X_EAR_COMPANDER_CTL,
  2885. 0x7C, ear_pa_gain);
  2886. return 0;
  2887. }
  2888. /* wcd939x_codec_get_dev_num - returns swr device number
  2889. * @component: Codec instance
  2890. *
  2891. * Return: swr device number on success or negative error
  2892. * code on failure.
  2893. */
  2894. int wcd939x_codec_get_dev_num(struct snd_soc_component *component)
  2895. {
  2896. struct wcd939x_priv *wcd939x;
  2897. if (!component)
  2898. return -EINVAL;
  2899. wcd939x = snd_soc_component_get_drvdata(component);
  2900. if (!wcd939x || !wcd939x->rx_swr_dev) {
  2901. pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
  2902. return -EINVAL;
  2903. }
  2904. return wcd939x->rx_swr_dev->dev_num;
  2905. }
  2906. EXPORT_SYMBOL(wcd939x_codec_get_dev_num);
  2907. static int wcd939x_get_compander(struct snd_kcontrol *kcontrol,
  2908. struct snd_ctl_elem_value *ucontrol)
  2909. {
  2910. struct snd_soc_component *component =
  2911. snd_soc_kcontrol_component(kcontrol);
  2912. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2913. bool hphr;
  2914. struct soc_multi_mixer_control *mc;
  2915. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2916. hphr = mc->shift;
  2917. ucontrol->value.integer.value[0] = hphr ? wcd939x->comp2_enable :
  2918. wcd939x->comp1_enable;
  2919. return 0;
  2920. }
  2921. static int wcd939x_set_compander(struct snd_kcontrol *kcontrol,
  2922. struct snd_ctl_elem_value *ucontrol)
  2923. {
  2924. struct snd_soc_component *component =
  2925. snd_soc_kcontrol_component(kcontrol);
  2926. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2927. int value = ucontrol->value.integer.value[0];
  2928. bool hphr;
  2929. struct soc_multi_mixer_control *mc;
  2930. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2931. hphr = mc->shift;
  2932. if (hphr)
  2933. wcd939x->comp2_enable = value;
  2934. else
  2935. wcd939x->comp1_enable = value;
  2936. return 0;
  2937. }
  2938. static int wcd939x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2939. struct snd_kcontrol *kcontrol,
  2940. int event)
  2941. {
  2942. struct snd_soc_component *component =
  2943. snd_soc_dapm_to_component(w->dapm);
  2944. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2945. struct wcd939x_pdata *pdata = NULL;
  2946. int ret = 0;
  2947. pdata = dev_get_platdata(wcd939x->dev);
  2948. if (!pdata) {
  2949. dev_err_ratelimited(component->dev, "%s: pdata is NULL\n", __func__);
  2950. return -EINVAL;
  2951. }
  2952. if (!msm_cdc_is_ondemand_supply(wcd939x->dev,
  2953. wcd939x->supplies,
  2954. pdata->regulator,
  2955. pdata->num_supplies,
  2956. "cdc-vdd-buck"))
  2957. return 0;
  2958. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2959. w->name, event);
  2960. switch (event) {
  2961. case SND_SOC_DAPM_PRE_PMU:
  2962. if (test_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask)) {
  2963. dev_dbg(component->dev,
  2964. "%s: buck already in enabled state\n",
  2965. __func__);
  2966. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2967. return 0;
  2968. }
  2969. ret = msm_cdc_enable_ondemand_supply(wcd939x->dev,
  2970. wcd939x->supplies,
  2971. pdata->regulator,
  2972. pdata->num_supplies,
  2973. "cdc-vdd-buck");
  2974. if (ret == -EINVAL) {
  2975. dev_err_ratelimited(component->dev, "%s: vdd buck is not enabled\n",
  2976. __func__);
  2977. return ret;
  2978. }
  2979. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2980. /*
  2981. * 200us sleep is required after LDO is enabled as per
  2982. * HW requirement
  2983. */
  2984. usleep_range(200, 250);
  2985. break;
  2986. case SND_SOC_DAPM_POST_PMD:
  2987. set_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  2988. break;
  2989. }
  2990. return 0;
  2991. }
  2992. static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol,
  2993. struct snd_ctl_elem_value *ucontrol)
  2994. {
  2995. struct snd_soc_component *component =
  2996. snd_soc_kcontrol_component(kcontrol);
  2997. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  2998. ucontrol->value.integer.value[0] = wcd939x->ldoh;
  2999. return 0;
  3000. }
  3001. static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol,
  3002. struct snd_ctl_elem_value *ucontrol)
  3003. {
  3004. struct snd_soc_component *component =
  3005. snd_soc_kcontrol_component(kcontrol);
  3006. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3007. wcd939x->ldoh = ucontrol->value.integer.value[0];
  3008. return 0;
  3009. }
  3010. const char * const tx_master_ch_text[] = {
  3011. "ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
  3012. "SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
  3013. "SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
  3014. "SWRM_TX3_CH4", "SWRM_PCM_IN",
  3015. };
  3016. const struct soc_enum tx_master_ch_enum =
  3017. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  3018. tx_master_ch_text);
  3019. static void wcd939x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  3020. {
  3021. u8 ch_type = 0;
  3022. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  3023. ch_type = ADC1;
  3024. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  3025. ch_type = ADC2;
  3026. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  3027. ch_type = ADC3;
  3028. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  3029. ch_type = ADC4;
  3030. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  3031. ch_type = DMIC0;
  3032. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  3033. ch_type = DMIC1;
  3034. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  3035. ch_type = MBHC;
  3036. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  3037. ch_type = DMIC2;
  3038. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  3039. ch_type = DMIC3;
  3040. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  3041. ch_type = DMIC4;
  3042. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  3043. ch_type = DMIC5;
  3044. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  3045. ch_type = DMIC6;
  3046. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  3047. ch_type = DMIC7;
  3048. else
  3049. pr_err_ratelimited("%s: port name: %s is not listed\n", __func__, wname);
  3050. if (ch_type)
  3051. *ch_idx = wcd939x_slave_get_slave_ch_val(ch_type);
  3052. else
  3053. *ch_idx = -EINVAL;
  3054. }
  3055. static int wcd939x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  3056. struct snd_ctl_elem_value *ucontrol)
  3057. {
  3058. struct snd_soc_component *component =
  3059. snd_soc_kcontrol_component(kcontrol);
  3060. struct wcd939x_priv *wcd939x = NULL;
  3061. int slave_ch_idx = -EINVAL;
  3062. if (component == NULL)
  3063. return -EINVAL;
  3064. wcd939x = snd_soc_component_get_drvdata(component);
  3065. if (wcd939x == NULL)
  3066. return -EINVAL;
  3067. wcd939x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  3068. if (slave_ch_idx < 0 || slave_ch_idx >= WCD939X_MAX_SLAVE_CH_TYPES)
  3069. return -EINVAL;
  3070. ucontrol->value.integer.value[0] = wcd939x_slave_get_master_ch_val(
  3071. wcd939x->tx_master_ch_map[slave_ch_idx]);
  3072. return 0;
  3073. }
  3074. static int wcd939x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  3075. struct snd_ctl_elem_value *ucontrol)
  3076. {
  3077. struct snd_soc_component *component =
  3078. snd_soc_kcontrol_component(kcontrol);
  3079. struct wcd939x_priv *wcd939x = NULL;
  3080. int slave_ch_idx = -EINVAL, idx = 0;
  3081. if (component == NULL)
  3082. return -EINVAL;
  3083. wcd939x = snd_soc_component_get_drvdata(component);
  3084. if (wcd939x == NULL)
  3085. return -EINVAL;
  3086. wcd939x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  3087. if (slave_ch_idx < 0 || slave_ch_idx >= WCD939X_MAX_SLAVE_CH_TYPES)
  3088. return -EINVAL;
  3089. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  3090. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  3091. __func__, ucontrol->value.enumerated.item[0]);
  3092. idx = ucontrol->value.enumerated.item[0];
  3093. if (idx < 0 || idx >= ARRAY_SIZE(swr_master_ch_map))
  3094. return -EINVAL;
  3095. wcd939x->tx_master_ch_map[slave_ch_idx] = wcd939x_slave_get_master_ch(idx);
  3096. return 0;
  3097. }
  3098. static int wcd939x_bcs_get(struct snd_kcontrol *kcontrol,
  3099. struct snd_ctl_elem_value *ucontrol)
  3100. {
  3101. struct snd_soc_component *component =
  3102. snd_soc_kcontrol_component(kcontrol);
  3103. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3104. ucontrol->value.integer.value[0] = wcd939x->bcs_dis;
  3105. return 0;
  3106. }
  3107. static int wcd939x_bcs_put(struct snd_kcontrol *kcontrol,
  3108. struct snd_ctl_elem_value *ucontrol)
  3109. {
  3110. struct snd_soc_component *component =
  3111. snd_soc_kcontrol_component(kcontrol);
  3112. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3113. wcd939x->bcs_dis = ucontrol->value.integer.value[0];
  3114. return 0;
  3115. }
  3116. static const char * const tx_mode_mux_text_wcd9390[] = {
  3117. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  3118. };
  3119. static const struct soc_enum tx_mode_mux_enum_wcd9390 =
  3120. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9390),
  3121. tx_mode_mux_text_wcd9390);
  3122. static const char * const tx_mode_mux_text[] = {
  3123. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  3124. "ADC_ULP1", "ADC_ULP2",
  3125. };
  3126. static const struct soc_enum tx_mode_mux_enum =
  3127. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  3128. tx_mode_mux_text);
  3129. static const char * const rx_hph_mode_mux_text_wcd9390[] = {
  3130. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  3131. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  3132. "CLS_AB_LOHIFI",
  3133. };
  3134. static const char * const wcd939x_ear_pa_gain_text[] = {
  3135. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  3136. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  3137. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  3138. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  3139. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  3140. };
  3141. static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 =
  3142. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390),
  3143. rx_hph_mode_mux_text_wcd9390);
  3144. static SOC_ENUM_SINGLE_EXT_DECL(wcd939x_ear_pa_gain_enum,
  3145. wcd939x_ear_pa_gain_text);
  3146. static const char * const rx_hph_mode_mux_text[] = {
  3147. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  3148. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  3149. };
  3150. static const struct soc_enum rx_hph_mode_mux_enum =
  3151. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  3152. rx_hph_mode_mux_text);
  3153. static const struct snd_kcontrol_new wcd9390_snd_controls[] = {
  3154. SOC_ENUM_EXT("EAR PA GAIN", wcd939x_ear_pa_gain_enum,
  3155. wcd939x_ear_pa_gain_get, wcd939x_ear_pa_gain_put),
  3156. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390,
  3157. wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
  3158. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9390,
  3159. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3160. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9390,
  3161. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3162. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9390,
  3163. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3164. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9390,
  3165. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3166. };
  3167. static const struct snd_kcontrol_new wcd9395_snd_controls[] = {
  3168. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  3169. wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
  3170. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  3171. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3172. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  3173. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3174. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  3175. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3176. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  3177. wcd939x_tx_mode_get, wcd939x_tx_mode_put),
  3178. };
  3179. static const struct snd_kcontrol_new wcd939x_snd_controls[] = {
  3180. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  3181. wcd939x_get_compander, wcd939x_set_compander),
  3182. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  3183. wcd939x_get_compander, wcd939x_set_compander),
  3184. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  3185. wcd939x_ldoh_get, wcd939x_ldoh_put),
  3186. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  3187. wcd939x_bcs_get, wcd939x_bcs_put),
  3188. SOC_SINGLE_TLV("HPHL Volume", WCD939X_PA_GAIN_CTL_L, 0, 0x18, 0, hph_analog_gain),
  3189. SOC_SINGLE_TLV("HPHR Volume", WCD939X_PA_GAIN_CTL_R, 0, 0x18, 0, hph_analog_gain),
  3190. SOC_SINGLE_TLV("ADC1 Volume", WCD939X_TX_CH1, 0, 20, 0,
  3191. analog_gain),
  3192. SOC_SINGLE_TLV("ADC2 Volume", WCD939X_TX_CH2, 0, 20, 0,
  3193. analog_gain),
  3194. SOC_SINGLE_TLV("ADC3 Volume", WCD939X_TX_CH3, 0, 20, 0,
  3195. analog_gain),
  3196. SOC_SINGLE_TLV("ADC4 Volume", WCD939X_TX_CH4, 0, 20, 0,
  3197. analog_gain),
  3198. SOC_SINGLE_EXT("HPHL Compander", SND_SOC_NOPM, WCD939X_HPHL, 1, 0,
  3199. wcd939x_hph_compander_get, wcd939x_hph_compander_put),
  3200. SOC_SINGLE_EXT("HPHR Compander", SND_SOC_NOPM, WCD939X_HPHR, 1, 0,
  3201. wcd939x_hph_compander_get, wcd939x_hph_compander_put),
  3202. SOC_SINGLE_EXT("HPHL XTALK", SND_SOC_NOPM, WCD939X_HPHL, 1, 0,
  3203. wcd939x_hph_xtalk_get, wcd939x_hph_xtalk_put),
  3204. SOC_SINGLE_EXT("HPHR XTALK", SND_SOC_NOPM, WCD939X_HPHR, 1, 0,
  3205. wcd939x_hph_xtalk_get, wcd939x_hph_xtalk_put),
  3206. SOC_SINGLE_EXT("HPH PCM Enable", SND_SOC_NOPM, 0, 1, 0,
  3207. wcd939x_hph_pcm_enable_get, wcd939x_hph_pcm_enable_put),
  3208. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  3209. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3210. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  3211. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3212. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  3213. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3214. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  3215. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3216. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  3217. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3218. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  3219. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3220. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  3221. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3222. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  3223. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3224. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  3225. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3226. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  3227. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3228. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  3229. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3230. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  3231. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3232. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  3233. wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
  3234. };
  3235. static const struct snd_kcontrol_new adc1_switch[] = {
  3236. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3237. };
  3238. static const struct snd_kcontrol_new adc2_switch[] = {
  3239. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3240. };
  3241. static const struct snd_kcontrol_new adc3_switch[] = {
  3242. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3243. };
  3244. static const struct snd_kcontrol_new adc4_switch[] = {
  3245. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3246. };
  3247. static const struct snd_kcontrol_new amic1_switch[] = {
  3248. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3249. };
  3250. static const struct snd_kcontrol_new amic2_switch[] = {
  3251. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3252. };
  3253. static const struct snd_kcontrol_new amic3_switch[] = {
  3254. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3255. };
  3256. static const struct snd_kcontrol_new amic4_switch[] = {
  3257. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3258. };
  3259. static const struct snd_kcontrol_new amic5_switch[] = {
  3260. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3261. };
  3262. static const struct snd_kcontrol_new va_amic1_switch[] = {
  3263. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3264. };
  3265. static const struct snd_kcontrol_new va_amic2_switch[] = {
  3266. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3267. };
  3268. static const struct snd_kcontrol_new va_amic3_switch[] = {
  3269. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3270. };
  3271. static const struct snd_kcontrol_new va_amic4_switch[] = {
  3272. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3273. };
  3274. static const struct snd_kcontrol_new va_amic5_switch[] = {
  3275. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3276. };
  3277. static const struct snd_kcontrol_new dmic1_switch[] = {
  3278. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3279. };
  3280. static const struct snd_kcontrol_new dmic2_switch[] = {
  3281. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3282. };
  3283. static const struct snd_kcontrol_new dmic3_switch[] = {
  3284. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3285. };
  3286. static const struct snd_kcontrol_new dmic4_switch[] = {
  3287. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3288. };
  3289. static const struct snd_kcontrol_new dmic5_switch[] = {
  3290. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3291. };
  3292. static const struct snd_kcontrol_new dmic6_switch[] = {
  3293. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3294. };
  3295. static const struct snd_kcontrol_new dmic7_switch[] = {
  3296. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3297. };
  3298. static const struct snd_kcontrol_new dmic8_switch[] = {
  3299. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3300. };
  3301. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  3302. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3303. };
  3304. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  3305. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3306. };
  3307. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  3308. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  3309. };
  3310. static const char * const adc1_mux_text[] = {
  3311. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5"
  3312. };
  3313. static const struct soc_enum adc1_enum =
  3314. SOC_ENUM_SINGLE(WCD939X_TX_CH12_MUX, WCD939X_TX_CH12_MUX_CH1_SEL_SHIFT,
  3315. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  3316. static const struct snd_kcontrol_new tx_adc1_mux =
  3317. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  3318. static const char * const adc2_mux_text[] = {
  3319. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5"
  3320. };
  3321. static const struct soc_enum adc2_enum =
  3322. SOC_ENUM_SINGLE(WCD939X_TX_CH12_MUX, WCD939X_TX_CH12_MUX_CH2_SEL_SHIFT,
  3323. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  3324. static const struct snd_kcontrol_new tx_adc2_mux =
  3325. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  3326. static const char * const adc3_mux_text[] = {
  3327. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5"
  3328. };
  3329. static const struct soc_enum adc3_enum =
  3330. SOC_ENUM_SINGLE(WCD939X_TX_CH34_MUX, WCD939X_TX_CH34_MUX_CH3_SEL_SHIFT,
  3331. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  3332. static const struct snd_kcontrol_new tx_adc3_mux =
  3333. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  3334. static const char * const adc4_mux_text[] = {
  3335. "CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5"
  3336. };
  3337. static const struct soc_enum adc4_enum =
  3338. SOC_ENUM_SINGLE(WCD939X_TX_CH34_MUX, WCD939X_TX_CH34_MUX_CH4_SEL_SHIFT,
  3339. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  3340. static const struct snd_kcontrol_new tx_adc4_mux =
  3341. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  3342. static const char * const rdac3_mux_text[] = {
  3343. "RX3", "RX1"
  3344. };
  3345. static const struct soc_enum rdac3_enum =
  3346. SOC_ENUM_SINGLE(WCD939X_CDC_EAR_PATH_CTL, 0,
  3347. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  3348. static const struct snd_kcontrol_new rx_rdac3_mux =
  3349. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  3350. static const char * const rx1_mux_text[] = {
  3351. "ZERO", "RX1 MUX"
  3352. };
  3353. static const struct soc_enum rx1_enum =
  3354. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx1_mux_text);
  3355. static const struct snd_kcontrol_new rx1_mux =
  3356. SOC_DAPM_ENUM("RX1 MUX Mux", rx1_enum);
  3357. static const char * const rx2_mux_text[] = {
  3358. "ZERO", "RX2 MUX"
  3359. };
  3360. static const struct soc_enum rx2_enum =
  3361. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx2_mux_text);
  3362. static const struct snd_kcontrol_new rx2_mux =
  3363. SOC_DAPM_ENUM("RX2 MUX Mux", rx2_enum);
  3364. static const char * const rx3_mux_text[] = {
  3365. "ZERO", "RX3 MUX"
  3366. };
  3367. static const struct soc_enum rx3_enum =
  3368. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 0, rx3_mux_text);
  3369. static const struct snd_kcontrol_new rx3_mux =
  3370. SOC_DAPM_ENUM("RX3 MUX Mux", rx3_enum);
  3371. static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = {
  3372. /*input widgets*/
  3373. SND_SOC_DAPM_INPUT("AMIC1"),
  3374. SND_SOC_DAPM_INPUT("AMIC2"),
  3375. SND_SOC_DAPM_INPUT("AMIC3"),
  3376. SND_SOC_DAPM_INPUT("AMIC4"),
  3377. SND_SOC_DAPM_INPUT("AMIC5"),
  3378. SND_SOC_DAPM_INPUT("VA AMIC1"),
  3379. SND_SOC_DAPM_INPUT("VA AMIC2"),
  3380. SND_SOC_DAPM_INPUT("VA AMIC3"),
  3381. SND_SOC_DAPM_INPUT("VA AMIC4"),
  3382. SND_SOC_DAPM_INPUT("VA AMIC5"),
  3383. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  3384. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  3385. SND_SOC_DAPM_INPUT("IN3_EAR"),
  3386. /*
  3387. * These dummy widgets are null connected to WCD939x dapm input and
  3388. * output widgets which are not actual path endpoints. This ensures
  3389. * dapm doesnt set these dapm input and output widgets as endpoints.
  3390. */
  3391. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  3392. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  3393. /*tx widgets*/
  3394. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  3395. wcd939x_codec_enable_adc,
  3396. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3397. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  3398. wcd939x_codec_enable_adc,
  3399. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3400. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  3401. wcd939x_codec_enable_adc,
  3402. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3403. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  3404. wcd939x_codec_enable_adc,
  3405. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3406. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  3407. wcd939x_codec_enable_dmic,
  3408. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3409. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  3410. wcd939x_codec_enable_dmic,
  3411. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3412. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  3413. wcd939x_codec_enable_dmic,
  3414. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3415. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  3416. wcd939x_codec_enable_dmic,
  3417. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3418. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  3419. wcd939x_codec_enable_dmic,
  3420. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3421. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  3422. wcd939x_codec_enable_dmic,
  3423. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3424. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  3425. wcd939x_codec_enable_dmic,
  3426. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3427. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  3428. wcd939x_codec_enable_dmic,
  3429. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3430. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  3431. NULL, 0, wcd939x_enable_req,
  3432. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3433. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  3434. NULL, 0, wcd939x_enable_req,
  3435. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3436. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  3437. NULL, 0, wcd939x_enable_req,
  3438. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3439. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  3440. NULL, 0, wcd939x_enable_req,
  3441. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3442. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3443. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3444. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3445. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3446. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3447. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3448. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3449. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3450. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3451. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3452. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3453. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3454. SND_SOC_DAPM_MIXER_E("AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3455. amic5_switch, ARRAY_SIZE(amic5_switch), NULL,
  3456. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3457. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3458. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3459. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3460. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3461. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3462. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3463. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3464. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3465. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3466. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3467. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3468. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3469. SND_SOC_DAPM_MIXER_E("VA_AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3470. va_amic5_switch, ARRAY_SIZE(va_amic5_switch), NULL,
  3471. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3472. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  3473. &tx_adc1_mux),
  3474. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3475. &tx_adc2_mux),
  3476. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3477. &tx_adc3_mux),
  3478. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  3479. &tx_adc4_mux),
  3480. /*tx mixers*/
  3481. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  3482. adc1_switch, ARRAY_SIZE(adc1_switch),
  3483. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3484. SND_SOC_DAPM_POST_PMD),
  3485. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  3486. adc2_switch, ARRAY_SIZE(adc2_switch),
  3487. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3488. SND_SOC_DAPM_POST_PMD),
  3489. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  3490. ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl,
  3491. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3492. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  3493. ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl,
  3494. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3495. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3496. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3497. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3498. SND_SOC_DAPM_POST_PMD),
  3499. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3500. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3501. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3502. SND_SOC_DAPM_POST_PMD),
  3503. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3504. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3505. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3506. SND_SOC_DAPM_POST_PMD),
  3507. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3508. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3509. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3510. SND_SOC_DAPM_POST_PMD),
  3511. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3512. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3513. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3514. SND_SOC_DAPM_POST_PMD),
  3515. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3516. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3517. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3518. SND_SOC_DAPM_POST_PMD),
  3519. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  3520. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  3521. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3522. SND_SOC_DAPM_POST_PMD),
  3523. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  3524. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  3525. wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3526. SND_SOC_DAPM_POST_PMD),
  3527. /* micbias widgets*/
  3528. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3529. wcd939x_codec_enable_micbias,
  3530. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3531. SND_SOC_DAPM_POST_PMD),
  3532. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3533. wcd939x_codec_enable_micbias,
  3534. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3535. SND_SOC_DAPM_POST_PMD),
  3536. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3537. wcd939x_codec_enable_micbias,
  3538. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3539. SND_SOC_DAPM_POST_PMD),
  3540. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3541. wcd939x_codec_enable_micbias,
  3542. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3543. SND_SOC_DAPM_POST_PMD),
  3544. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  3545. wcd939x_codec_force_enable_micbias,
  3546. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3547. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  3548. wcd939x_codec_force_enable_micbias,
  3549. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3550. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  3551. wcd939x_codec_force_enable_micbias,
  3552. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3553. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  3554. wcd939x_codec_force_enable_micbias,
  3555. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3556. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3557. wcd939x_codec_enable_vdd_buck,
  3558. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3559. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3560. wcd939x_enable_clsh,
  3561. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3562. SND_SOC_DAPM_SUPPLY_S("CLS_H_DUMMY", 1, SND_SOC_NOPM, 0, 0,
  3563. wcd939x_clsh_dummy, SND_SOC_DAPM_POST_PMD),
  3564. /*rx widgets*/
  3565. SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_EAR, 7, 0, NULL, 0,
  3566. wcd939x_codec_enable_ear_pa,
  3567. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3568. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3569. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_HPH, 7, 0, NULL, 0,
  3570. wcd939x_codec_enable_hphl_pa,
  3571. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3572. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3573. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_HPH, 6, 0, NULL, 0,
  3574. wcd939x_codec_enable_hphr_pa,
  3575. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3576. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3577. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3578. wcd939x_codec_hphl_dac_event,
  3579. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3580. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3581. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3582. wcd939x_codec_hphr_dac_event,
  3583. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3584. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3585. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3586. wcd939x_codec_ear_dac_event,
  3587. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3588. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3589. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3590. SND_SOC_DAPM_MUX_E("RX1 MUX", SND_SOC_NOPM, WCD_RX1, 0, &rx1_mux,
  3591. wcd939x_rx_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU
  3592. | SND_SOC_DAPM_POST_PMD),
  3593. SND_SOC_DAPM_MUX_E("RX2 MUX", SND_SOC_NOPM, WCD_RX2, 0, &rx2_mux,
  3594. wcd939x_rx_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU
  3595. | SND_SOC_DAPM_POST_PMD),
  3596. SND_SOC_DAPM_MUX_E("RX3 MUX", SND_SOC_NOPM, WCD_RX3, 0, &rx3_mux,
  3597. wcd939x_rx3_mux, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3598. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3599. wcd939x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3600. SND_SOC_DAPM_POST_PMD),
  3601. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3602. wcd939x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3603. SND_SOC_DAPM_POST_PMD),
  3604. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3605. wcd939x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3606. SND_SOC_DAPM_POST_PMD),
  3607. /* rx mixer widgets*/
  3608. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3609. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3610. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3611. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3612. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3613. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3614. /*output widgets tx*/
  3615. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3616. /*output widgets rx*/
  3617. SND_SOC_DAPM_OUTPUT("EAR"),
  3618. SND_SOC_DAPM_OUTPUT("HPHL"),
  3619. SND_SOC_DAPM_OUTPUT("HPHR"),
  3620. /* micbias pull up widgets*/
  3621. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3622. wcd939x_codec_enable_micbias_pullup,
  3623. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3624. SND_SOC_DAPM_POST_PMD),
  3625. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3626. wcd939x_codec_enable_micbias_pullup,
  3627. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3628. SND_SOC_DAPM_POST_PMD),
  3629. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3630. wcd939x_codec_enable_micbias_pullup,
  3631. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3632. SND_SOC_DAPM_POST_PMD),
  3633. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3634. wcd939x_codec_enable_micbias_pullup,
  3635. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3636. SND_SOC_DAPM_POST_PMD),
  3637. };
  3638. static const struct snd_soc_dapm_route wcd939x_audio_map[] = {
  3639. /*ADC-1 (channel-1)*/
  3640. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3641. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3642. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3643. {"ADC1 REQ", NULL, "ADC1"},
  3644. {"ADC1", NULL, "ADC1 MUX"},
  3645. {"ADC1 MUX", "CH1_AMIC1", "AMIC1_MIXER"},
  3646. {"ADC1 MUX", "CH1_AMIC2", "AMIC2_MIXER"},
  3647. {"ADC1 MUX", "CH1_AMIC3", "AMIC3_MIXER"},
  3648. {"ADC1 MUX", "CH1_AMIC4", "AMIC4_MIXER"},
  3649. {"ADC1 MUX", "CH1_AMIC5", "AMIC5_MIXER"},
  3650. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3651. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3652. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3653. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3654. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3655. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3656. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3657. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3658. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3659. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3660. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3661. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3662. {"AMIC5_MIXER", "Switch", "AMIC5"},
  3663. {"AMIC5_MIXER", NULL, "VA_AMIC5_MIXER"},
  3664. {"VA_AMIC5_MIXER", "Switch", "VA AMIC5"},
  3665. /*ADC-2 (channel-2)*/
  3666. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3667. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3668. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3669. {"ADC2 REQ", NULL, "ADC2"},
  3670. {"ADC2", NULL, "ADC2 MUX"},
  3671. {"ADC2 MUX", "CH2_AMIC1", "AMIC1_MIXER"},
  3672. {"ADC2 MUX", "CH2_AMIC2", "AMIC2_MIXER"},
  3673. {"ADC2 MUX", "CH2_AMIC3", "AMIC3_MIXER"},
  3674. {"ADC2 MUX", "CH2_AMIC4", "AMIC4_MIXER"},
  3675. {"ADC2 MUX", "CH2_AMIC5", "AMIC5_MIXER"},
  3676. /*ADC-3 (channel-3)*/
  3677. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3678. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3679. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3680. {"ADC3 REQ", NULL, "ADC3"},
  3681. {"ADC3", NULL, "ADC3 MUX"},
  3682. {"ADC3 MUX", "CH3_AMIC1", "AMIC1_MIXER"},
  3683. {"ADC3 MUX", "CH3_AMIC3", "AMIC3_MIXER"},
  3684. {"ADC3 MUX", "CH3_AMIC4", "AMIC4_MIXER"},
  3685. {"ADC3 MUX", "CH3_AMIC5", "AMIC5_MIXER"},
  3686. /*ADC-4 (channel-4)*/
  3687. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3688. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3689. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3690. {"ADC4 REQ", NULL, "ADC4"},
  3691. {"ADC4", NULL, "ADC4 MUX"},
  3692. {"ADC4 MUX", "CH4_AMIC1", "AMIC1_MIXER"},
  3693. {"ADC4 MUX", "CH4_AMIC3", "AMIC3_MIXER"},
  3694. {"ADC4 MUX", "CH4_AMIC4", "AMIC4_MIXER"},
  3695. {"ADC4 MUX", "CH4_AMIC5", "AMIC5_MIXER"},
  3696. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3697. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3698. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3699. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3700. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3701. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3702. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3703. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3704. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3705. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3706. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3707. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3708. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3709. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3710. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3711. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3712. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3713. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3714. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3715. {"RX1 MUX", NULL, "IN1_HPHL"},
  3716. {"RX1", NULL, "RX1 MUX"},
  3717. {"RDAC1", NULL, "RX1"},
  3718. {"HPHL_RDAC", "Switch", "RDAC1"},
  3719. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3720. {"HPHL", NULL, "HPHL PGA"},
  3721. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3722. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3723. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3724. {"RX2 MUX", NULL, "IN2_HPHR"},
  3725. {"RX2", NULL, "RX2 MUX"},
  3726. {"RDAC2", NULL, "RX2"},
  3727. {"HPHR_RDAC", "Switch", "RDAC2"},
  3728. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3729. {"HPHR", NULL, "HPHR PGA"},
  3730. {"IN3_EAR", NULL, "WCD_RX_DUMMY"},
  3731. {"IN3_EAR", NULL, "VDD_BUCK"},
  3732. {"IN3_EAR", NULL, "CLS_H_DUMMY"},
  3733. {"RX3 MUX", NULL, "IN3_EAR"},
  3734. {"RX3", NULL, "RX3 MUX"},
  3735. {"RDAC3_MUX", "RX3", "RX3"},
  3736. {"RDAC3_MUX", "RX1", "RX1"},
  3737. {"RDAC3", NULL, "RDAC3_MUX"},
  3738. {"EAR_RDAC", "Switch", "RDAC3"},
  3739. {"EAR PGA", NULL, "EAR_RDAC"},
  3740. {"EAR", NULL, "EAR PGA"},
  3741. };
  3742. static ssize_t wcd939x_version_read(struct snd_info_entry *entry,
  3743. void *file_private_data,
  3744. struct file *file,
  3745. char __user *buf, size_t count,
  3746. loff_t pos)
  3747. {
  3748. struct wcd939x_priv *priv;
  3749. char buffer[WCD939X_VERSION_ENTRY_SIZE];
  3750. int len = 0;
  3751. priv = (struct wcd939x_priv *) entry->private_data;
  3752. if (!priv) {
  3753. pr_err_ratelimited("%s: wcd939x priv is null\n", __func__);
  3754. return -EINVAL;
  3755. }
  3756. switch (priv->version) {
  3757. case WCD939X_VERSION_1_0:
  3758. case WCD939X_VERSION_1_1:
  3759. len = snprintf(buffer, sizeof(buffer), "WCD939X_1_0\n");
  3760. break;
  3761. case WCD939X_VERSION_2_0:
  3762. len = snprintf(buffer, sizeof(buffer), "WCD939X_2_0\n");
  3763. break;
  3764. default:
  3765. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3766. }
  3767. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3768. }
  3769. static struct snd_info_entry_ops wcd939x_info_ops = {
  3770. .read = wcd939x_version_read,
  3771. };
  3772. static ssize_t wcd939x_variant_read(struct snd_info_entry *entry,
  3773. void *file_private_data,
  3774. struct file *file,
  3775. char __user *buf, size_t count,
  3776. loff_t pos)
  3777. {
  3778. struct wcd939x_priv *priv;
  3779. char buffer[WCD939X_VARIANT_ENTRY_SIZE];
  3780. int len = 0;
  3781. priv = (struct wcd939x_priv *) entry->private_data;
  3782. if (!priv) {
  3783. pr_err_ratelimited("%s: wcd939x priv is null\n", __func__);
  3784. return -EINVAL;
  3785. }
  3786. switch (priv->variant) {
  3787. case WCD9390:
  3788. len = snprintf(buffer, sizeof(buffer), "WCD9390\n");
  3789. break;
  3790. case WCD9395:
  3791. len = snprintf(buffer, sizeof(buffer), "WCD9395\n");
  3792. break;
  3793. default:
  3794. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3795. }
  3796. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3797. }
  3798. static struct snd_info_entry_ops wcd939x_variant_ops = {
  3799. .read = wcd939x_variant_read,
  3800. };
  3801. /*
  3802. * wcd939x_get_codec_variant
  3803. * @component: component instance
  3804. *
  3805. * Return: codec variant or -EINVAL in error.
  3806. */
  3807. int wcd939x_get_codec_variant(struct snd_soc_component *component)
  3808. {
  3809. struct wcd939x_priv *priv = NULL;
  3810. if (!component)
  3811. return -EINVAL;
  3812. priv = snd_soc_component_get_drvdata(component);
  3813. if (!priv) {
  3814. dev_err(component->dev,
  3815. "%s:wcd939x not probed\n", __func__);
  3816. return 0;
  3817. }
  3818. return priv->variant;
  3819. }
  3820. EXPORT_SYMBOL(wcd939x_get_codec_variant);
  3821. /*
  3822. * wcd939x_info_create_codec_entry - creates wcd939x module
  3823. * @codec_root: The parent directory
  3824. * @component: component instance
  3825. *
  3826. * Creates wcd939x module, variant and version entry under the given
  3827. * parent directory.
  3828. *
  3829. * Return: 0 on success or negative error code on failure.
  3830. */
  3831. int wcd939x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3832. struct snd_soc_component *component)
  3833. {
  3834. struct snd_info_entry *version_entry;
  3835. struct snd_info_entry *variant_entry;
  3836. struct wcd939x_priv *priv;
  3837. struct snd_soc_card *card;
  3838. if (!codec_root || !component)
  3839. return -EINVAL;
  3840. priv = snd_soc_component_get_drvdata(component);
  3841. if (priv->entry) {
  3842. dev_dbg(priv->dev,
  3843. "%s:wcd939x module already created\n", __func__);
  3844. return 0;
  3845. }
  3846. card = component->card;
  3847. priv->entry = snd_info_create_module_entry(codec_root->module,
  3848. "wcd939x", codec_root);
  3849. if (!priv->entry) {
  3850. dev_dbg(component->dev, "%s: failed to create wcd939x entry\n",
  3851. __func__);
  3852. return -ENOMEM;
  3853. }
  3854. priv->entry->mode = S_IFDIR | 0555;
  3855. if (snd_info_register(priv->entry) < 0) {
  3856. snd_info_free_entry(priv->entry);
  3857. return -ENOMEM;
  3858. }
  3859. version_entry = snd_info_create_card_entry(card->snd_card,
  3860. "version",
  3861. priv->entry);
  3862. if (!version_entry) {
  3863. dev_dbg(component->dev, "%s: failed to create wcd939x version entry\n",
  3864. __func__);
  3865. snd_info_free_entry(priv->entry);
  3866. return -ENOMEM;
  3867. }
  3868. version_entry->private_data = priv;
  3869. version_entry->size = WCD939X_VERSION_ENTRY_SIZE;
  3870. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3871. version_entry->c.ops = &wcd939x_info_ops;
  3872. if (snd_info_register(version_entry) < 0) {
  3873. snd_info_free_entry(version_entry);
  3874. snd_info_free_entry(priv->entry);
  3875. return -ENOMEM;
  3876. }
  3877. priv->version_entry = version_entry;
  3878. variant_entry = snd_info_create_card_entry(card->snd_card,
  3879. "variant",
  3880. priv->entry);
  3881. if (!variant_entry) {
  3882. dev_dbg(component->dev, "%s: failed to create wcd939x variant entry\n",
  3883. __func__);
  3884. snd_info_free_entry(version_entry);
  3885. snd_info_free_entry(priv->entry);
  3886. return -ENOMEM;
  3887. }
  3888. variant_entry->private_data = priv;
  3889. variant_entry->size = WCD939X_VARIANT_ENTRY_SIZE;
  3890. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3891. variant_entry->c.ops = &wcd939x_variant_ops;
  3892. if (snd_info_register(variant_entry) < 0) {
  3893. snd_info_free_entry(variant_entry);
  3894. snd_info_free_entry(version_entry);
  3895. snd_info_free_entry(priv->entry);
  3896. return -ENOMEM;
  3897. }
  3898. priv->variant_entry = variant_entry;
  3899. return 0;
  3900. }
  3901. EXPORT_SYMBOL(wcd939x_info_create_codec_entry);
  3902. static int wcd939x_set_micbias_data(struct wcd939x_priv *wcd939x,
  3903. struct wcd939x_pdata *pdata)
  3904. {
  3905. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3906. int rc = 0;
  3907. if (!pdata) {
  3908. dev_err(wcd939x->dev, "%s: NULL pdata\n", __func__);
  3909. return -ENODEV;
  3910. }
  3911. /* set micbias voltage */
  3912. vout_ctl_1 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3913. vout_ctl_2 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3914. vout_ctl_3 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3915. vout_ctl_4 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3916. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3917. vout_ctl_4 < 0) {
  3918. rc = -EINVAL;
  3919. goto done;
  3920. }
  3921. regmap_update_bits(wcd939x->regmap, WCD939X_MICB1, 0x3F,
  3922. vout_ctl_1);
  3923. regmap_update_bits(wcd939x->regmap, WCD939X_MICB2, 0x3F,
  3924. vout_ctl_2);
  3925. regmap_update_bits(wcd939x->regmap, WCD939X_MICB3, 0x3F,
  3926. vout_ctl_3);
  3927. regmap_update_bits(wcd939x->regmap, WCD939X_MICB4, 0x3F,
  3928. vout_ctl_4);
  3929. done:
  3930. return rc;
  3931. }
  3932. static int wcd939x_soc_codec_probe(struct snd_soc_component *component)
  3933. {
  3934. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  3935. struct snd_soc_dapm_context *dapm =
  3936. snd_soc_component_get_dapm(component);
  3937. int ret = -EINVAL;
  3938. dev_info(component->dev, "%s()\n", __func__);
  3939. wcd939x = snd_soc_component_get_drvdata(component);
  3940. if (!wcd939x)
  3941. return -EINVAL;
  3942. wcd939x->component = component;
  3943. snd_soc_component_init_regmap(component, wcd939x->regmap);
  3944. devm_regmap_qti_debugfs_register(&wcd939x->tx_swr_dev->dev, wcd939x->regmap);
  3945. /*Harmonium contains only one variant i.e wcd9395*/
  3946. wcd939x->variant = WCD9395;
  3947. /* Check device tree to see if 2Vpk flag is enabled, this value should not be changed */
  3948. wcd939x->in_2Vpk_mode = of_find_property(wcd939x->dev->of_node,
  3949. "qcom,hph-2p15v-mode", NULL) != NULL;
  3950. wcd939x->fw_data = devm_kzalloc(component->dev,
  3951. sizeof(*(wcd939x->fw_data)),
  3952. GFP_KERNEL);
  3953. if (!wcd939x->fw_data) {
  3954. dev_err(component->dev, "Failed to allocate fw_data\n");
  3955. ret = -ENOMEM;
  3956. goto err;
  3957. }
  3958. set_bit(WCD9XXX_MBHC_CAL, wcd939x->fw_data->cal_bit);
  3959. ret = wcd_cal_create_hwdep(wcd939x->fw_data,
  3960. WCD9XXX_CODEC_HWDEP_NODE, component);
  3961. if (ret < 0) {
  3962. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3963. goto err_hwdep;
  3964. }
  3965. ret = wcd939x_mbhc_init(&wcd939x->mbhc, component, wcd939x->fw_data);
  3966. if (ret) {
  3967. pr_err("%s: mbhc initialization failed\n", __func__);
  3968. goto err_hwdep;
  3969. }
  3970. snd_soc_dapm_ignore_suspend(dapm, "WCD939X_AIF Playback");
  3971. snd_soc_dapm_ignore_suspend(dapm, "WCD939X_AIF Capture");
  3972. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3973. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3974. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3975. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3976. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3977. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3978. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3979. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3980. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3981. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC5");
  3982. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3983. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3984. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3985. snd_soc_dapm_ignore_suspend(dapm, "IN3_EAR");
  3986. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3987. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3988. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3989. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3990. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3991. snd_soc_dapm_sync(dapm);
  3992. wcd_cls_h_init(&wcd939x->clsh_info);
  3993. wcd939x_init_reg(component);
  3994. if (wcd939x->variant == WCD9390) {
  3995. ret = snd_soc_add_component_controls(component, wcd9390_snd_controls,
  3996. ARRAY_SIZE(wcd9390_snd_controls));
  3997. if (ret < 0) {
  3998. dev_err(component->dev,
  3999. "%s: Failed to add snd ctrls for variant: %d\n",
  4000. __func__, wcd939x->variant);
  4001. goto err_hwdep;
  4002. }
  4003. }
  4004. if (wcd939x->variant == WCD9395) {
  4005. ret = snd_soc_add_component_controls(component, wcd9395_snd_controls,
  4006. ARRAY_SIZE(wcd9395_snd_controls));
  4007. if (ret < 0) {
  4008. dev_err(component->dev,
  4009. "%s: Failed to add snd ctrls for variant: %d\n",
  4010. __func__, wcd939x->variant);
  4011. goto err_hwdep;
  4012. }
  4013. }
  4014. /* Register event notifier */
  4015. wcd939x->nblock.notifier_call = wcd939x_event_notify;
  4016. if (wcd939x->register_notifier) {
  4017. ret = wcd939x->register_notifier(wcd939x->handle,
  4018. &wcd939x->nblock,
  4019. true);
  4020. if (ret) {
  4021. dev_err(component->dev,
  4022. "%s: Failed to register notifier %d\n",
  4023. __func__, ret);
  4024. return ret;
  4025. }
  4026. }
  4027. return ret;
  4028. err_hwdep:
  4029. wcd939x->fw_data = NULL;
  4030. err:
  4031. return ret;
  4032. }
  4033. static void wcd939x_soc_codec_remove(struct snd_soc_component *component)
  4034. {
  4035. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  4036. if (!wcd939x) {
  4037. dev_err(component->dev, "%s: wcd939x is already NULL\n",
  4038. __func__);
  4039. return;
  4040. }
  4041. if (wcd939x->register_notifier)
  4042. wcd939x->register_notifier(wcd939x->handle,
  4043. &wcd939x->nblock,
  4044. false);
  4045. }
  4046. static int wcd939x_soc_codec_suspend(struct snd_soc_component *component)
  4047. {
  4048. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  4049. if (!wcd939x)
  4050. return 0;
  4051. wcd939x->dapm_bias_off = true;
  4052. return 0;
  4053. }
  4054. static int wcd939x_soc_codec_resume(struct snd_soc_component *component)
  4055. {
  4056. struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
  4057. if (!wcd939x)
  4058. return 0;
  4059. wcd939x->dapm_bias_off = false;
  4060. return 0;
  4061. }
  4062. static struct snd_soc_component_driver soc_codec_dev_wcd939x = {
  4063. .name = WCD939X_DRV_NAME,
  4064. .probe = wcd939x_soc_codec_probe,
  4065. .remove = wcd939x_soc_codec_remove,
  4066. .controls = wcd939x_snd_controls,
  4067. .num_controls = ARRAY_SIZE(wcd939x_snd_controls),
  4068. .dapm_widgets = wcd939x_dapm_widgets,
  4069. .num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets),
  4070. .dapm_routes = wcd939x_audio_map,
  4071. .num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map),
  4072. .suspend = wcd939x_soc_codec_suspend,
  4073. .resume = wcd939x_soc_codec_resume,
  4074. };
  4075. static int wcd939x_reset(struct device *dev)
  4076. {
  4077. struct wcd939x_priv *wcd939x = NULL;
  4078. int rc = 0;
  4079. int value = 0;
  4080. if (!dev)
  4081. return -ENODEV;
  4082. wcd939x = dev_get_drvdata(dev);
  4083. if (!wcd939x)
  4084. return -EINVAL;
  4085. if (!wcd939x->rst_np) {
  4086. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  4087. __func__);
  4088. return -EINVAL;
  4089. }
  4090. value = msm_cdc_pinctrl_get_state(wcd939x->rst_np);
  4091. if (value > 0)
  4092. return 0;
  4093. rc = msm_cdc_pinctrl_select_sleep_state(wcd939x->rst_np);
  4094. if (rc) {
  4095. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  4096. __func__);
  4097. return rc;
  4098. }
  4099. /* 20us sleep required after pulling the reset gpio to LOW */
  4100. usleep_range(20, 30);
  4101. rc = msm_cdc_pinctrl_select_active_state(wcd939x->rst_np);
  4102. if (rc) {
  4103. dev_err_ratelimited(dev, "%s: wcd active state request fail!\n",
  4104. __func__);
  4105. return rc;
  4106. }
  4107. /* 20us sleep required after pulling the reset gpio to HIGH */
  4108. usleep_range(20, 30);
  4109. return rc;
  4110. }
  4111. static int wcd939x_read_of_property_u32(struct device *dev, const char *name,
  4112. u32 *val)
  4113. {
  4114. int rc = 0;
  4115. rc = of_property_read_u32(dev->of_node, name, val);
  4116. if (rc)
  4117. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  4118. __func__, name, dev->of_node->full_name);
  4119. return rc;
  4120. }
  4121. static int wcd939x_read_of_property_s32(struct device *dev, const char *name,
  4122. s32 *val)
  4123. {
  4124. int rc = 0;
  4125. rc = of_property_read_s32(dev->of_node, name, val);
  4126. if (rc)
  4127. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  4128. __func__, name, dev->of_node->full_name);
  4129. return rc;
  4130. }
  4131. static void wcd939x_dt_parse_micbias_info(struct device *dev,
  4132. struct wcd939x_micbias_setting *mb)
  4133. {
  4134. u32 prop_val = 0;
  4135. int rc = 0;
  4136. /* MB1 */
  4137. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  4138. NULL)) {
  4139. rc = wcd939x_read_of_property_u32(dev,
  4140. "qcom,cdc-micbias1-mv",
  4141. &prop_val);
  4142. if (!rc)
  4143. mb->micb1_mv = prop_val;
  4144. } else {
  4145. dev_info(dev, "%s: Micbias1 DT property not found\n",
  4146. __func__);
  4147. }
  4148. /* MB2 */
  4149. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  4150. NULL)) {
  4151. rc = wcd939x_read_of_property_u32(dev,
  4152. "qcom,cdc-micbias2-mv",
  4153. &prop_val);
  4154. if (!rc)
  4155. mb->micb2_mv = prop_val;
  4156. } else {
  4157. dev_info(dev, "%s: Micbias2 DT property not found\n",
  4158. __func__);
  4159. }
  4160. /* MB3 */
  4161. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  4162. NULL)) {
  4163. rc = wcd939x_read_of_property_u32(dev,
  4164. "qcom,cdc-micbias3-mv",
  4165. &prop_val);
  4166. if (!rc)
  4167. mb->micb3_mv = prop_val;
  4168. } else {
  4169. dev_info(dev, "%s: Micbias3 DT property not found\n",
  4170. __func__);
  4171. }
  4172. /* MB4 */
  4173. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  4174. NULL)) {
  4175. rc = wcd939x_read_of_property_u32(dev,
  4176. "qcom,cdc-micbias4-mv",
  4177. &prop_val);
  4178. if (!rc)
  4179. mb->micb4_mv = prop_val;
  4180. } else {
  4181. dev_info(dev, "%s: Micbias4 DT property not found\n",
  4182. __func__);
  4183. }
  4184. }
  4185. static void init_usbcss_hs_params(struct wcd939x_usbcss_hs_params *usbcss_hs)
  4186. {
  4187. usbcss_hs->r_gnd_sbu1_int_fet_mohms = 145;
  4188. usbcss_hs->r_gnd_sbu2_int_fet_mohms = 185;
  4189. usbcss_hs->r_gnd_ext_fet_customer_mohms = 0;
  4190. usbcss_hs->r_gnd_ext_fet_mohms = 0; /* to be computed during MBHC zdet */
  4191. usbcss_hs->r_gnd_par_route1_mohms = 5;
  4192. usbcss_hs->r_gnd_par_route2_mohms = 330;
  4193. usbcss_hs->r_gnd_par_tot_mohms = 0;
  4194. usbcss_hs->r_gnd_sbu1_res_tot_mohms = 0;
  4195. usbcss_hs->r_gnd_sbu2_res_tot_mohms = 0;
  4196. usbcss_hs->r_conn_par_load_pos_mohms = 7550;
  4197. usbcss_hs->r_aud_int_fet_l_mohms = 303;
  4198. usbcss_hs->r_aud_int_fet_r_mohms = 275;
  4199. usbcss_hs->r_aud_ext_fet_l_mohms = 0; /* to be computed during MBHC zdet */
  4200. usbcss_hs->r_aud_ext_fet_r_mohms = 0; /* to be computed during MBHC zdet */
  4201. usbcss_hs->r_aud_res_tot_l_mohms = 0;
  4202. usbcss_hs->r_aud_res_tot_r_mohms = 0;
  4203. usbcss_hs->r_surge_mohms = 272;
  4204. usbcss_hs->r_load_eff_l_mohms = 0; /* to be computed during MBHC zdet */
  4205. usbcss_hs->r_load_eff_r_mohms = 0; /* to be computed during MBHC zdet */
  4206. usbcss_hs->r3 = 1;
  4207. usbcss_hs->r4 = 330;
  4208. usbcss_hs->r5 = 5;
  4209. usbcss_hs->r6 = 1;
  4210. usbcss_hs->r7 = 5;
  4211. usbcss_hs->k_aud_times_100 = 13;
  4212. usbcss_hs->k_gnd_times_100 = 13;
  4213. usbcss_hs->aud_tap_offset = 0;
  4214. usbcss_hs->gnd_tap_offset = 0;
  4215. usbcss_hs->scale_l = MAX_XTALK_SCALE;
  4216. usbcss_hs->alpha_l = MIN_XTALK_ALPHA;
  4217. usbcss_hs->scale_r = MAX_XTALK_SCALE;
  4218. usbcss_hs->alpha_r = MIN_XTALK_ALPHA;
  4219. usbcss_hs->xtalk_config = XTALK_NONE;
  4220. }
  4221. static void parse_xtalk_param(struct device *dev, u32 default_val, u32 *prop_val_p,
  4222. char *prop)
  4223. {
  4224. int rc = 0;
  4225. if (of_find_property(dev->of_node, prop, NULL)) {
  4226. rc = wcd939x_read_of_property_u32(dev, prop, prop_val_p);
  4227. if ((!rc) && (*prop_val_p <= MAX_USBCSS_HS_IMPEDANCE_MOHMS) && (*prop_val_p > 0))
  4228. return;
  4229. *prop_val_p = default_val;
  4230. dev_dbg(dev, "%s: %s OOB. Default value of %d will be used.\n", __func__, prop,
  4231. default_val);
  4232. } else {
  4233. *prop_val_p = default_val;
  4234. dev_dbg(dev, "%s: %s property not found. Default value of %d will be used.\n",
  4235. __func__, prop, default_val);
  4236. }
  4237. }
  4238. static void wcd939x_dt_parse_usbcss_hs_info(struct device *dev,
  4239. struct wcd939x_usbcss_hs_params *usbcss_hs)
  4240. {
  4241. u32 prop_val = 0;
  4242. s32 prop_val_signed = 0;
  4243. int rc = 0;
  4244. /* Default values for parameters */
  4245. init_usbcss_hs_params(usbcss_hs);
  4246. /* xtalk_config: Determine type of crosstalk: none (0), digital (1), or analog (2) */
  4247. if (of_find_property(dev->of_node, "qcom,usbcss-hs-xtalk-config", NULL)) {
  4248. rc = wcd939x_read_of_property_u32(dev, "qcom,usbcss-hs-xtalk-config", &prop_val);
  4249. if ((!rc) && (prop_val == XTALK_NONE || prop_val == XTALK_DIGITAL
  4250. || prop_val == XTALK_ANALOG)) {
  4251. usbcss_hs->xtalk_config = (enum xtalk_mode) prop_val;
  4252. } else
  4253. dev_dbg(dev, "%s: %s OOB. Default value of %s used.\n",
  4254. __func__, "qcom,usbcss-hs-xtalk-config", "XTALK_NONE");
  4255. } else
  4256. dev_dbg(dev, "%s: %s property not found. Default value of %s used.\n",
  4257. __func__, "qcom,usbcss-hs-xtalk-config", "XTALK_NONE");
  4258. /* k values for linearizer */
  4259. if (of_find_property(dev->of_node, "qcom,usbcss-hs-lin-k-aud", NULL)) {
  4260. rc = wcd939x_read_of_property_s32(dev, "qcom,usbcss-hs-lin-k-aud",
  4261. &prop_val);
  4262. if ((!rc) && (prop_val <= MAX_K_TIMES_100) && (prop_val >= MIN_K_TIMES_100))
  4263. usbcss_hs->k_aud_times_100 = prop_val;
  4264. dev_dbg(dev, "%s: %s OOB. Default value of %d will be used.\n",
  4265. __func__, "qcom,usbcss-hs-lin-k-aud",
  4266. usbcss_hs->k_aud_times_100);
  4267. } else {
  4268. dev_dbg(dev, "%s: %s property not found. Default value of %d will be used.\n",
  4269. __func__, "qcom,usbcss-hs-lin-k-aud",
  4270. usbcss_hs->k_aud_times_100);
  4271. }
  4272. if (of_find_property(dev->of_node, "qcom,usbcss-hs-lin-k-gnd", NULL)) {
  4273. rc = wcd939x_read_of_property_s32(dev, "qcom,usbcss-hs-lin-k-gnd",
  4274. &prop_val_signed);
  4275. if ((!rc) && (prop_val_signed <= MAX_K_TIMES_100) &&
  4276. (prop_val_signed >= MIN_K_TIMES_100))
  4277. usbcss_hs->k_gnd_times_100 = prop_val_signed;
  4278. dev_dbg(dev, "%s: %s OOB. Default value of %d will be used.\n",
  4279. __func__, "qcom,usbcss-hs-lin-k-gnd",
  4280. usbcss_hs->k_gnd_times_100);
  4281. } else {
  4282. dev_dbg(dev, "%s: %s property not found. Default value of %d will be used.\n",
  4283. __func__, "qcom,usbcss-hs-lin-k-gnd",
  4284. usbcss_hs->k_gnd_times_100);
  4285. }
  4286. /* r_gnd_ext_fet_customer_mohms */
  4287. parse_xtalk_param(dev, usbcss_hs->r_gnd_ext_fet_customer_mohms, &prop_val,
  4288. "qcom,usbcss-hs-rdson");
  4289. usbcss_hs->r_gnd_ext_fet_customer_mohms = prop_val;
  4290. /* r_conn_par_load_pos_mohm */
  4291. parse_xtalk_param(dev, usbcss_hs->r_conn_par_load_pos_mohms, &prop_val,
  4292. "qcom,usbcss-hs-r2");
  4293. usbcss_hs->r_conn_par_load_pos_mohms = prop_val;
  4294. /* r3 */
  4295. parse_xtalk_param(dev, usbcss_hs->r3, &prop_val,
  4296. "qcom,usbcss-hs-r3");
  4297. usbcss_hs->r3 = prop_val;
  4298. /* r4 */
  4299. parse_xtalk_param(dev, usbcss_hs->r4, &prop_val,
  4300. "qcom,usbcss-hs-r4");
  4301. usbcss_hs->r4 = prop_val;
  4302. /* r_gnd_par_route1_mohms and r_gnd_par_route2_mohms */
  4303. if (usbcss_hs->xtalk_config == XTALK_ANALOG) {
  4304. parse_xtalk_param(dev, usbcss_hs->r5, &prop_val,
  4305. "qcom,usbcss-hs-r5");
  4306. usbcss_hs->r5 = prop_val;
  4307. usbcss_hs->r_gnd_par_route1_mohms = usbcss_hs->r5 + usbcss_hs->r4;
  4308. usbcss_hs->r_gnd_par_route2_mohms = 125;
  4309. } else if (usbcss_hs->xtalk_config == XTALK_DIGITAL) {
  4310. parse_xtalk_param(dev, usbcss_hs->r6, &prop_val,
  4311. "qcom,usbcss-hs-r6");
  4312. usbcss_hs->r6 = prop_val;
  4313. usbcss_hs->r_gnd_par_route2_mohms = usbcss_hs->r6 + usbcss_hs->r4;
  4314. parse_xtalk_param(dev, usbcss_hs->r_gnd_par_route1_mohms, &prop_val,
  4315. "qcom,usbcss-hs-r7");
  4316. usbcss_hs->r7 = prop_val;
  4317. usbcss_hs->r_gnd_par_route1_mohms = prop_val;
  4318. }
  4319. /* Compute total resistances */
  4320. usbcss_hs->r_gnd_par_tot_mohms = usbcss_hs->r_gnd_par_route1_mohms +
  4321. usbcss_hs->r_gnd_par_route2_mohms;
  4322. usbcss_hs->r_gnd_sbu1_res_tot_mohms = get_r_gnd_res_tot_mohms(
  4323. usbcss_hs->r_gnd_sbu1_int_fet_mohms,
  4324. usbcss_hs->r_gnd_ext_fet_mohms,
  4325. usbcss_hs->r_gnd_par_tot_mohms);
  4326. usbcss_hs->r_gnd_sbu2_res_tot_mohms = get_r_gnd_res_tot_mohms(
  4327. usbcss_hs->r_gnd_sbu2_int_fet_mohms,
  4328. usbcss_hs->r_gnd_ext_fet_mohms,
  4329. usbcss_hs->r_gnd_par_tot_mohms);
  4330. usbcss_hs->r_aud_res_tot_l_mohms = get_r_aud_res_tot_mohms(
  4331. usbcss_hs->r_aud_int_fet_l_mohms,
  4332. usbcss_hs->r_aud_ext_fet_l_mohms);
  4333. usbcss_hs->r_aud_res_tot_r_mohms = get_r_aud_res_tot_mohms(
  4334. usbcss_hs->r_aud_int_fet_r_mohms,
  4335. usbcss_hs->r_aud_ext_fet_r_mohms);
  4336. /* Set linearizer calibration codes to be sourced from SW */
  4337. wcd_usbss_linearizer_rdac_cal_code_select(LINEARIZER_SOURCE_SW);
  4338. }
  4339. static int wcd939x_reset_low(struct device *dev)
  4340. {
  4341. struct wcd939x_priv *wcd939x = NULL;
  4342. int rc = 0;
  4343. if (!dev)
  4344. return -ENODEV;
  4345. wcd939x = dev_get_drvdata(dev);
  4346. if (!wcd939x)
  4347. return -EINVAL;
  4348. if (!wcd939x->rst_np) {
  4349. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  4350. __func__);
  4351. return -EINVAL;
  4352. }
  4353. rc = msm_cdc_pinctrl_select_sleep_state(wcd939x->rst_np);
  4354. if (rc) {
  4355. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  4356. __func__);
  4357. return rc;
  4358. }
  4359. /* 20us sleep required after pulling the reset gpio to LOW */
  4360. usleep_range(20, 30);
  4361. return rc;
  4362. }
  4363. struct wcd939x_pdata *wcd939x_populate_dt_data(struct device *dev)
  4364. {
  4365. struct wcd939x_pdata *pdata = NULL;
  4366. pdata = devm_kzalloc(dev, sizeof(struct wcd939x_pdata),
  4367. GFP_KERNEL);
  4368. if (!pdata)
  4369. return NULL;
  4370. pdata->rst_np = of_parse_phandle(dev->of_node,
  4371. "qcom,wcd-rst-gpio-node", 0);
  4372. if (!pdata->rst_np) {
  4373. dev_err_ratelimited(dev, "%s: Looking up %s property in node %s failed\n",
  4374. __func__, "qcom,wcd-rst-gpio-node",
  4375. dev->of_node->full_name);
  4376. return NULL;
  4377. }
  4378. /* Parse power supplies */
  4379. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  4380. &pdata->num_supplies);
  4381. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  4382. dev_err_ratelimited(dev, "%s: no power supplies defined for codec\n",
  4383. __func__);
  4384. return NULL;
  4385. }
  4386. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  4387. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  4388. wcd939x_dt_parse_micbias_info(dev, &pdata->micbias);
  4389. wcd939x_dt_parse_usbcss_hs_info(dev, &pdata->usbcss_hs);
  4390. return pdata;
  4391. }
  4392. static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data)
  4393. {
  4394. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  4395. __func__, irq);
  4396. return IRQ_HANDLED;
  4397. }
  4398. static struct snd_soc_dai_driver wcd939x_dai[] = {
  4399. {
  4400. .name = "wcd939x_cdc",
  4401. .playback = {
  4402. .stream_name = "WCD939X_AIF Playback",
  4403. .rates = WCD939X_RATES | WCD939X_FRAC_RATES,
  4404. .formats = WCD939X_FORMATS,
  4405. .rate_max = 384000,
  4406. .rate_min = 8000,
  4407. .channels_min = 1,
  4408. .channels_max = 4,
  4409. },
  4410. .capture = {
  4411. .stream_name = "WCD939X_AIF Capture",
  4412. .rates = WCD939X_RATES | WCD939X_FRAC_RATES,
  4413. .formats = WCD939X_FORMATS,
  4414. .rate_max = 384000,
  4415. .rate_min = 8000,
  4416. .channels_min = 1,
  4417. .channels_max = 4,
  4418. },
  4419. },
  4420. };
  4421. static const struct reg_default reg_def_1_1[] = {
  4422. {WCD939X_VBG_FINE_ADJ, 0xA5},
  4423. {WCD939X_FLYBACK_NEW_CTRL_2, 0x0},
  4424. {WCD939X_FLYBACK_NEW_CTRL_3, 0x0},
  4425. {WCD939X_FLYBACK_NEW_CTRL_4, 0x44},
  4426. {WCD939X_PA_GAIN_CTL_R, 0x80},
  4427. };
  4428. static const struct reg_default reg_def_2_0[] = {
  4429. {WCD939X_INTR_MASK_2, 0x3E},
  4430. };
  4431. static const char *version_to_str(u32 version)
  4432. {
  4433. switch (version) {
  4434. case WCD939X_VERSION_1_0:
  4435. return __stringify(WCD939X_1_0);
  4436. case WCD939X_VERSION_1_1:
  4437. return __stringify(WCD939X_1_1);
  4438. case WCD939X_VERSION_2_0:
  4439. return __stringify(WCD939X_2_0);
  4440. }
  4441. return NULL;
  4442. }
  4443. static void wcd939x_update_regmap_cache(struct wcd939x_priv *wcd939x)
  4444. {
  4445. if (wcd939x->version == WCD939X_VERSION_1_0)
  4446. return;
  4447. if (wcd939x->version >= WCD939X_VERSION_1_1) {
  4448. for (int i = 0; i < ARRAY_SIZE(reg_def_1_1); ++i)
  4449. regmap_write(wcd939x->regmap, reg_def_1_1[i].reg, reg_def_1_1[i].def);
  4450. }
  4451. if (wcd939x->version == WCD939X_VERSION_2_0) {
  4452. for (int i = 0; i < ARRAY_SIZE(reg_def_2_0); ++i)
  4453. regmap_write(wcd939x->regmap, reg_def_2_0[i].reg, reg_def_2_0[i].def);
  4454. }
  4455. }
  4456. static int wcd939x_bind(struct device *dev)
  4457. {
  4458. int ret = 0, i = 0, val = 0;
  4459. struct wcd939x_pdata *pdata = dev_get_platdata(dev);
  4460. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  4461. u8 id1 = 0, status1 = 0;
  4462. /*
  4463. * Add 5msec delay to provide sufficient time for
  4464. * soundwire auto enumeration of slave devices as
  4465. * as per HW requirement.
  4466. */
  4467. usleep_range(5000, 5010);
  4468. ret = component_bind_all(dev, wcd939x);
  4469. if (ret) {
  4470. dev_err_ratelimited(dev, "%s: Slave bind failed, ret = %d\n",
  4471. __func__, ret);
  4472. return ret;
  4473. }
  4474. wcd939x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  4475. if (!wcd939x->rx_swr_dev) {
  4476. dev_err_ratelimited(dev, "%s: Could not find RX swr slave device\n",
  4477. __func__);
  4478. ret = -ENODEV;
  4479. goto err;
  4480. }
  4481. wcd939x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  4482. if (!wcd939x->tx_swr_dev) {
  4483. dev_err_ratelimited(dev, "%s: Could not find TX swr slave device\n",
  4484. __func__);
  4485. ret = -ENODEV;
  4486. goto err;
  4487. }
  4488. swr_init_port_params(wcd939x->tx_swr_dev, SWR_NUM_PORTS,
  4489. wcd939x->swr_tx_port_params);
  4490. /* Check WCD9395 version */
  4491. swr_read(wcd939x->tx_swr_dev, wcd939x->tx_swr_dev->dev_num,
  4492. WCD939X_CHIP_ID1, &id1, 1);
  4493. swr_read(wcd939x->tx_swr_dev, wcd939x->tx_swr_dev->dev_num,
  4494. WCD939X_STATUS_REG_1, &status1, 1);
  4495. if (id1 == 0)
  4496. wcd939x->version = ((status1 & 0x3) ? WCD939X_VERSION_1_1 : WCD939X_VERSION_1_0);
  4497. else if (id1 == 1)
  4498. wcd939x->version = WCD939X_VERSION_2_0;
  4499. wcd939x_version = wcd939x->version;
  4500. dev_info(dev, "%s: wcd9395 version: %s\n", __func__,
  4501. version_to_str(wcd939x->version));
  4502. wcd939x_regmap_config.readable_reg = wcd939x_readable_register;
  4503. wcd939x->regmap = devm_regmap_init_swr(wcd939x->tx_swr_dev,
  4504. &wcd939x_regmap_config);
  4505. if (!wcd939x->regmap) {
  4506. dev_err_ratelimited(dev, "%s: Regmap init failed\n",
  4507. __func__);
  4508. goto err;
  4509. }
  4510. #if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
  4511. regmap_read(wcd939x->regmap, WCD939X_EFUSE_REG_17, &val);
  4512. if (wcd939x_version == WCD939X_VERSION_2_0 && val < 3)
  4513. wcd_usbss_update_default_trim();
  4514. #endif
  4515. wcd939x_update_regmap_cache(wcd939x);
  4516. /* Set all interupts as edge triggered */
  4517. for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++)
  4518. regmap_write(wcd939x->regmap,
  4519. (WCD939X_INTR_LEVEL_0 + i), 0);
  4520. wcd939x_regmap_irq_chip.irq_drv_data = wcd939x;
  4521. wcd939x->irq_info.wcd_regmap_irq_chip = &wcd939x_regmap_irq_chip;
  4522. wcd939x->irq_info.codec_name = "WCD939X";
  4523. wcd939x->irq_info.regmap = wcd939x->regmap;
  4524. wcd939x->irq_info.dev = dev;
  4525. ret = wcd_irq_init(&wcd939x->irq_info, &wcd939x->virq);
  4526. if (ret) {
  4527. dev_err_ratelimited(wcd939x->dev, "%s: IRQ init failed: %d\n",
  4528. __func__, ret);
  4529. goto err;
  4530. }
  4531. wcd939x->tx_swr_dev->slave_irq = wcd939x->virq;
  4532. ret = wcd939x_set_micbias_data(wcd939x, pdata);
  4533. if (ret < 0) {
  4534. dev_err_ratelimited(dev, "%s: bad micbias pdata\n", __func__);
  4535. goto err_irq;
  4536. }
  4537. /* Request for watchdog interrupt */
  4538. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT,
  4539. "HPHR PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4540. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT,
  4541. "HPHL PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4542. wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT,
  4543. "EAR PDM WD INT", wcd939x_wd_handle_irq, NULL);
  4544. /* Disable watchdog interrupt for HPH and EAR */
  4545. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT);
  4546. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT);
  4547. wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT);
  4548. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x,
  4549. wcd939x_dai, ARRAY_SIZE(wcd939x_dai));
  4550. if (ret) {
  4551. dev_err_ratelimited(dev, "%s: Codec registration failed\n",
  4552. __func__);
  4553. goto err_irq;
  4554. }
  4555. wcd939x->dev_up = true;
  4556. return ret;
  4557. err_irq:
  4558. wcd_irq_exit(&wcd939x->irq_info, wcd939x->virq);
  4559. err:
  4560. component_unbind_all(dev, wcd939x);
  4561. return ret;
  4562. }
  4563. static void wcd939x_unbind(struct device *dev)
  4564. {
  4565. struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
  4566. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT, NULL);
  4567. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT, NULL);
  4568. wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT, NULL);
  4569. wcd_irq_exit(&wcd939x->irq_info, wcd939x->virq);
  4570. snd_soc_unregister_component(dev);
  4571. component_unbind_all(dev, wcd939x);
  4572. }
  4573. static const struct of_device_id wcd939x_dt_match[] = {
  4574. { .compatible = "qcom,wcd939x-codec", .data = "wcd939x"},
  4575. {}
  4576. };
  4577. static const struct component_master_ops wcd939x_comp_ops = {
  4578. .bind = wcd939x_bind,
  4579. .unbind = wcd939x_unbind,
  4580. };
  4581. static int wcd939x_compare_of(struct device *dev, void *data)
  4582. {
  4583. return dev->of_node == data;
  4584. }
  4585. static void wcd939x_release_of(struct device *dev, void *data)
  4586. {
  4587. of_node_put(data);
  4588. }
  4589. static int wcd939x_add_slave_components(struct device *dev,
  4590. struct component_match **matchptr)
  4591. {
  4592. struct device_node *np, *rx_node, *tx_node;
  4593. np = dev->of_node;
  4594. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  4595. if (!rx_node) {
  4596. dev_err_ratelimited(dev, "%s: Rx-slave node not defined\n", __func__);
  4597. return -ENODEV;
  4598. }
  4599. of_node_get(rx_node);
  4600. component_match_add_release(dev, matchptr,
  4601. wcd939x_release_of,
  4602. wcd939x_compare_of,
  4603. rx_node);
  4604. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  4605. if (!tx_node) {
  4606. dev_err_ratelimited(dev, "%s: Tx-slave node not defined\n", __func__);
  4607. return -ENODEV;
  4608. }
  4609. of_node_get(tx_node);
  4610. component_match_add_release(dev, matchptr,
  4611. wcd939x_release_of,
  4612. wcd939x_compare_of,
  4613. tx_node);
  4614. return 0;
  4615. }
  4616. static int wcd939x_probe(struct platform_device *pdev)
  4617. {
  4618. struct component_match *match = NULL;
  4619. struct wcd939x_priv *wcd939x = NULL;
  4620. struct wcd939x_pdata *pdata = NULL;
  4621. struct wcd_ctrl_platform_data *plat_data = NULL;
  4622. struct device *dev = &pdev->dev;
  4623. int ret;
  4624. wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv),
  4625. GFP_KERNEL);
  4626. if (!wcd939x)
  4627. return -ENOMEM;
  4628. dev_set_drvdata(dev, wcd939x);
  4629. wcd939x->dev = dev;
  4630. pdata = wcd939x_populate_dt_data(dev);
  4631. if (!pdata) {
  4632. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  4633. return -EINVAL;
  4634. }
  4635. dev->platform_data = pdata;
  4636. wcd939x->rst_np = pdata->rst_np;
  4637. ret = msm_cdc_init_supplies(dev, &wcd939x->supplies,
  4638. pdata->regulator, pdata->num_supplies);
  4639. if (!wcd939x->supplies) {
  4640. dev_err(dev, "%s: Cannot init wcd supplies\n",
  4641. __func__);
  4642. return ret;
  4643. }
  4644. plat_data = dev_get_platdata(dev->parent);
  4645. if (!plat_data) {
  4646. dev_err(dev, "%s: platform data from parent is NULL\n",
  4647. __func__);
  4648. return -EINVAL;
  4649. }
  4650. wcd939x->handle = (void *)plat_data->handle;
  4651. if (!wcd939x->handle) {
  4652. dev_err(dev, "%s: handle is NULL\n", __func__);
  4653. return -EINVAL;
  4654. }
  4655. wcd939x->update_wcd_event = plat_data->update_wcd_event;
  4656. if (!wcd939x->update_wcd_event) {
  4657. dev_err(dev, "%s: update_wcd_event api is null!\n",
  4658. __func__);
  4659. return -EINVAL;
  4660. }
  4661. wcd939x->register_notifier = plat_data->register_notifier;
  4662. if (!wcd939x->register_notifier) {
  4663. dev_err(dev, "%s: register_notifier api is null!\n",
  4664. __func__);
  4665. return -EINVAL;
  4666. }
  4667. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd939x->supplies,
  4668. pdata->regulator,
  4669. pdata->num_supplies);
  4670. if (ret) {
  4671. dev_err(dev, "%s: wcd static supply enable failed!\n",
  4672. __func__);
  4673. return ret;
  4674. }
  4675. if (msm_cdc_is_ondemand_supply(wcd939x->dev, wcd939x->supplies,
  4676. pdata->regulator, pdata->num_supplies, "cdc-vdd-px")) {
  4677. ret = msm_cdc_enable_ondemand_supply(wcd939x->dev,
  4678. wcd939x->supplies, pdata->regulator,
  4679. pdata->num_supplies, "cdc-vdd-px");
  4680. if (ret) {
  4681. dev_err(dev, "%s: vdd px supply enable failed!\n",
  4682. __func__);
  4683. return ret;
  4684. }
  4685. }
  4686. ret = wcd939x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  4687. CODEC_RX);
  4688. ret |= wcd939x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  4689. CODEC_TX);
  4690. if (ret) {
  4691. dev_err(dev, "Failed to read port mapping\n");
  4692. goto err;
  4693. }
  4694. ret = wcd939x_parse_port_params(dev, "qcom,swr-tx-port-params",
  4695. CODEC_TX);
  4696. if (ret) {
  4697. dev_err(dev, "Failed to read port params\n");
  4698. goto err;
  4699. }
  4700. mutex_init(&wcd939x->wakeup_lock);
  4701. mutex_init(&wcd939x->micb_lock);
  4702. ret = wcd939x_add_slave_components(dev, &match);
  4703. if (ret)
  4704. goto err_lock_init;
  4705. wcd939x_reset(dev);
  4706. wcd939x->wakeup = wcd939x_wakeup;
  4707. return component_master_add_with_match(dev,
  4708. &wcd939x_comp_ops, match);
  4709. err_lock_init:
  4710. mutex_destroy(&wcd939x->micb_lock);
  4711. mutex_destroy(&wcd939x->wakeup_lock);
  4712. err:
  4713. return ret;
  4714. }
  4715. static int wcd939x_remove(struct platform_device *pdev)
  4716. {
  4717. struct wcd939x_priv *wcd939x = NULL;
  4718. wcd939x = platform_get_drvdata(pdev);
  4719. component_master_del(&pdev->dev, &wcd939x_comp_ops);
  4720. mutex_destroy(&wcd939x->micb_lock);
  4721. mutex_destroy(&wcd939x->wakeup_lock);
  4722. dev_set_drvdata(&pdev->dev, NULL);
  4723. return 0;
  4724. }
  4725. #ifdef CONFIG_PM_SLEEP
  4726. static int wcd939x_suspend(struct device *dev)
  4727. {
  4728. struct wcd939x_priv *wcd939x = NULL;
  4729. int ret = 0;
  4730. struct wcd939x_pdata *pdata = NULL;
  4731. if (!dev)
  4732. return -ENODEV;
  4733. wcd939x = dev_get_drvdata(dev);
  4734. if (!wcd939x)
  4735. return -EINVAL;
  4736. pdata = dev_get_platdata(wcd939x->dev);
  4737. if (!pdata) {
  4738. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4739. return -EINVAL;
  4740. }
  4741. if (test_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask)) {
  4742. ret = msm_cdc_disable_ondemand_supply(wcd939x->dev,
  4743. wcd939x->supplies,
  4744. pdata->regulator,
  4745. pdata->num_supplies,
  4746. "cdc-vdd-buck");
  4747. if (ret == -EINVAL) {
  4748. dev_err_ratelimited(dev, "%s: vdd buck is not disabled\n",
  4749. __func__);
  4750. return 0;
  4751. }
  4752. clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
  4753. }
  4754. if (wcd939x->dapm_bias_off ||
  4755. (wcd939x->component &&
  4756. (snd_soc_component_get_bias_level(wcd939x->component) ==
  4757. SND_SOC_BIAS_OFF))) {
  4758. msm_cdc_set_supplies_lpm_mode(wcd939x->dev,
  4759. wcd939x->supplies,
  4760. pdata->regulator,
  4761. pdata->num_supplies,
  4762. true);
  4763. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask);
  4764. if (msm_cdc_is_ondemand_supply(wcd939x->dev, wcd939x->supplies, pdata->regulator,
  4765. pdata->num_supplies, "cdc-vdd-px")) {
  4766. if (msm_cdc_supply_supports_retention_mode(wcd939x->dev, wcd939x->supplies,
  4767. pdata->regulator, pdata->num_supplies, "cdc-vdd-px") &&
  4768. msm_cdc_check_supply_vote(wcd939x->dev, wcd939x->supplies,
  4769. pdata->regulator, pdata->num_supplies, "cdc-vdd-px")) {
  4770. ret = msm_cdc_disable_ondemand_supply(wcd939x->dev,
  4771. wcd939x->supplies, pdata->regulator,
  4772. pdata->num_supplies, "cdc-vdd-px");
  4773. if (ret) {
  4774. dev_dbg(dev, "%s: vdd px supply suspend failed!\n",
  4775. __func__);
  4776. }
  4777. }
  4778. }
  4779. }
  4780. return 0;
  4781. }
  4782. static int wcd939x_resume(struct device *dev)
  4783. {
  4784. int ret = 0;
  4785. struct wcd939x_priv *wcd939x = NULL;
  4786. struct wcd939x_pdata *pdata = NULL;
  4787. if (!dev)
  4788. return -ENODEV;
  4789. wcd939x = dev_get_drvdata(dev);
  4790. if (!wcd939x)
  4791. return -EINVAL;
  4792. pdata = dev_get_platdata(wcd939x->dev);
  4793. if (!pdata) {
  4794. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4795. return -EINVAL;
  4796. }
  4797. if (msm_cdc_is_ondemand_supply(wcd939x->dev, wcd939x->supplies, pdata->regulator,
  4798. pdata->num_supplies, "cdc-vdd-px")) {
  4799. if (msm_cdc_supply_supports_retention_mode(wcd939x->dev, wcd939x->supplies,
  4800. pdata->regulator, pdata->num_supplies, "cdc-vdd-px") &&
  4801. !msm_cdc_check_supply_vote(wcd939x->dev, wcd939x->supplies,
  4802. pdata->regulator, pdata->num_supplies, "cdc-vdd-px")) {
  4803. ret = msm_cdc_enable_ondemand_supply(wcd939x->dev, wcd939x->supplies,
  4804. pdata->regulator, pdata->num_supplies, "cdc-vdd-px");
  4805. if (ret) {
  4806. dev_dbg(dev, "%s: vdd px supply resume failed!\n",
  4807. __func__);
  4808. }
  4809. }
  4810. }
  4811. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask)) {
  4812. msm_cdc_set_supplies_lpm_mode(wcd939x->dev,
  4813. wcd939x->supplies,
  4814. pdata->regulator,
  4815. pdata->num_supplies,
  4816. false);
  4817. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask);
  4818. }
  4819. return 0;
  4820. }
  4821. static const struct dev_pm_ops wcd939x_dev_pm_ops = {
  4822. .suspend_late = wcd939x_suspend,
  4823. .resume_early = wcd939x_resume,
  4824. };
  4825. #endif
  4826. static struct platform_driver wcd939x_codec_driver = {
  4827. .probe = wcd939x_probe,
  4828. .remove = wcd939x_remove,
  4829. .driver = {
  4830. .name = "wcd939x_codec",
  4831. .owner = THIS_MODULE,
  4832. .of_match_table = of_match_ptr(wcd939x_dt_match),
  4833. #ifdef CONFIG_PM_SLEEP
  4834. .pm = &wcd939x_dev_pm_ops,
  4835. #endif
  4836. .suppress_bind_attrs = true,
  4837. },
  4838. };
  4839. module_platform_driver(wcd939x_codec_driver);
  4840. MODULE_DESCRIPTION("WCD939X Codec driver");
  4841. MODULE_LICENSE("GPL v2");