dsi_phy.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/of_device.h>
  6. #include <linux/err.h>
  7. #include <linux/regulator/consumer.h>
  8. #include <linux/clk.h>
  9. #include <linux/list.h>
  10. #include "msm_drv.h"
  11. #include "msm_kms.h"
  12. #include "dsi_phy.h"
  13. #include "dsi_phy_hw.h"
  14. #include "dsi_clk.h"
  15. #include "dsi_pwr.h"
  16. #include "dsi_catalog.h"
  17. #include "sde_dbg.h"
  18. #define DSI_PHY_DEFAULT_LABEL "MDSS PHY CTRL"
  19. #define BITS_PER_BYTE 8
  20. struct dsi_phy_list_item {
  21. struct msm_dsi_phy *phy;
  22. struct list_head list;
  23. };
  24. static LIST_HEAD(dsi_phy_list);
  25. static DEFINE_MUTEX(dsi_phy_list_lock);
  26. static const struct dsi_ver_spec_info dsi_phy_v0_0_hpm = {
  27. .version = DSI_PHY_VERSION_0_0_HPM,
  28. .lane_cfg_count = 4,
  29. .strength_cfg_count = 2,
  30. .regulator_cfg_count = 1,
  31. .timing_cfg_count = 8,
  32. };
  33. static const struct dsi_ver_spec_info dsi_phy_v0_0_lpm = {
  34. .version = DSI_PHY_VERSION_0_0_LPM,
  35. .lane_cfg_count = 4,
  36. .strength_cfg_count = 2,
  37. .regulator_cfg_count = 1,
  38. .timing_cfg_count = 8,
  39. };
  40. static const struct dsi_ver_spec_info dsi_phy_v1_0 = {
  41. .version = DSI_PHY_VERSION_1_0,
  42. .lane_cfg_count = 4,
  43. .strength_cfg_count = 2,
  44. .regulator_cfg_count = 1,
  45. .timing_cfg_count = 8,
  46. };
  47. static const struct dsi_ver_spec_info dsi_phy_v2_0 = {
  48. .version = DSI_PHY_VERSION_2_0,
  49. .lane_cfg_count = 4,
  50. .strength_cfg_count = 2,
  51. .regulator_cfg_count = 1,
  52. .timing_cfg_count = 8,
  53. };
  54. static const struct dsi_ver_spec_info dsi_phy_v3_0 = {
  55. .version = DSI_PHY_VERSION_3_0,
  56. .lane_cfg_count = 4,
  57. .strength_cfg_count = 2,
  58. .regulator_cfg_count = 0,
  59. .timing_cfg_count = 12,
  60. };
  61. static const struct dsi_ver_spec_info dsi_phy_v4_0 = {
  62. .version = DSI_PHY_VERSION_4_0,
  63. .lane_cfg_count = 4,
  64. .strength_cfg_count = 2,
  65. .regulator_cfg_count = 0,
  66. .timing_cfg_count = 14,
  67. };
  68. static const struct dsi_ver_spec_info dsi_phy_v4_1 = {
  69. .version = DSI_PHY_VERSION_4_1,
  70. .lane_cfg_count = 4,
  71. .strength_cfg_count = 2,
  72. .regulator_cfg_count = 0,
  73. .timing_cfg_count = 14,
  74. };
  75. static const struct of_device_id msm_dsi_phy_of_match[] = {
  76. { .compatible = "qcom,dsi-phy-v0.0-hpm",
  77. .data = &dsi_phy_v0_0_hpm,},
  78. { .compatible = "qcom,dsi-phy-v0.0-lpm",
  79. .data = &dsi_phy_v0_0_lpm,},
  80. { .compatible = "qcom,dsi-phy-v1.0",
  81. .data = &dsi_phy_v1_0,},
  82. { .compatible = "qcom,dsi-phy-v2.0",
  83. .data = &dsi_phy_v2_0,},
  84. { .compatible = "qcom,dsi-phy-v3.0",
  85. .data = &dsi_phy_v3_0,},
  86. { .compatible = "qcom,dsi-phy-v4.0",
  87. .data = &dsi_phy_v4_0,},
  88. { .compatible = "qcom,dsi-phy-v4.1",
  89. .data = &dsi_phy_v4_1,},
  90. {}
  91. };
  92. static int dsi_phy_regmap_init(struct platform_device *pdev,
  93. struct msm_dsi_phy *phy)
  94. {
  95. int rc = 0;
  96. void __iomem *ptr;
  97. ptr = msm_ioremap(pdev, "dsi_phy", phy->name);
  98. if (IS_ERR(ptr)) {
  99. rc = PTR_ERR(ptr);
  100. return rc;
  101. }
  102. phy->hw.base = ptr;
  103. ptr = msm_ioremap(pdev, "dyn_refresh_base", phy->name);
  104. phy->hw.dyn_pll_base = ptr;
  105. DSI_PHY_DBG(phy, "map dsi_phy registers to %pK\n", phy->hw.base);
  106. switch (phy->ver_info->version) {
  107. case DSI_PHY_VERSION_2_0:
  108. ptr = msm_ioremap(pdev, "phy_clamp_base", phy->name);
  109. if (IS_ERR(ptr))
  110. phy->hw.phy_clamp_base = NULL;
  111. else
  112. phy->hw.phy_clamp_base = ptr;
  113. break;
  114. default:
  115. break;
  116. }
  117. return rc;
  118. }
  119. static int dsi_phy_regmap_deinit(struct msm_dsi_phy *phy)
  120. {
  121. DSI_PHY_DBG(phy, "unmap registers\n");
  122. return 0;
  123. }
  124. static int dsi_phy_supplies_init(struct platform_device *pdev,
  125. struct msm_dsi_phy *phy)
  126. {
  127. int rc = 0;
  128. int i = 0;
  129. struct dsi_regulator_info *regs;
  130. struct regulator *vreg = NULL;
  131. regs = &phy->pwr_info.digital;
  132. regs->vregs = devm_kzalloc(&pdev->dev, sizeof(struct dsi_vreg),
  133. GFP_KERNEL);
  134. if (!regs->vregs)
  135. goto error;
  136. regs->count = 1;
  137. snprintf(regs->vregs->vreg_name,
  138. ARRAY_SIZE(regs->vregs[i].vreg_name),
  139. "%s", "gdsc");
  140. rc = dsi_pwr_get_dt_vreg_data(&pdev->dev,
  141. &phy->pwr_info.phy_pwr,
  142. "qcom,phy-supply-entries");
  143. if (rc) {
  144. DSI_PHY_ERR(phy, "failed to get host power supplies, rc = %d\n",
  145. rc);
  146. goto error_digital;
  147. }
  148. regs = &phy->pwr_info.digital;
  149. for (i = 0; i < regs->count; i++) {
  150. vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
  151. rc = PTR_RET(vreg);
  152. if (rc) {
  153. DSI_PHY_ERR(phy, "failed to get %s regulator\n",
  154. regs->vregs[i].vreg_name);
  155. goto error_host_pwr;
  156. }
  157. regs->vregs[i].vreg = vreg;
  158. }
  159. regs = &phy->pwr_info.phy_pwr;
  160. for (i = 0; i < regs->count; i++) {
  161. vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
  162. rc = PTR_RET(vreg);
  163. if (rc) {
  164. DSI_PHY_ERR(phy, "failed to get %s regulator\n",
  165. regs->vregs[i].vreg_name);
  166. for (--i; i >= 0; i--)
  167. devm_regulator_put(regs->vregs[i].vreg);
  168. goto error_digital_put;
  169. }
  170. regs->vregs[i].vreg = vreg;
  171. }
  172. return rc;
  173. error_digital_put:
  174. regs = &phy->pwr_info.digital;
  175. for (i = 0; i < regs->count; i++)
  176. devm_regulator_put(regs->vregs[i].vreg);
  177. error_host_pwr:
  178. devm_kfree(&pdev->dev, phy->pwr_info.phy_pwr.vregs);
  179. phy->pwr_info.phy_pwr.vregs = NULL;
  180. phy->pwr_info.phy_pwr.count = 0;
  181. error_digital:
  182. devm_kfree(&pdev->dev, phy->pwr_info.digital.vregs);
  183. phy->pwr_info.digital.vregs = NULL;
  184. phy->pwr_info.digital.count = 0;
  185. error:
  186. return rc;
  187. }
  188. static int dsi_phy_supplies_deinit(struct msm_dsi_phy *phy)
  189. {
  190. int i = 0;
  191. int rc = 0;
  192. struct dsi_regulator_info *regs;
  193. regs = &phy->pwr_info.digital;
  194. for (i = 0; i < regs->count; i++) {
  195. if (!regs->vregs[i].vreg)
  196. DSI_PHY_ERR(phy, "vreg is NULL, should not reach here\n");
  197. else
  198. devm_regulator_put(regs->vregs[i].vreg);
  199. }
  200. regs = &phy->pwr_info.phy_pwr;
  201. for (i = 0; i < regs->count; i++) {
  202. if (!regs->vregs[i].vreg)
  203. DSI_PHY_ERR(phy, "vreg is NULL, should not reach here\n");
  204. else
  205. devm_regulator_put(regs->vregs[i].vreg);
  206. }
  207. if (phy->pwr_info.phy_pwr.vregs) {
  208. devm_kfree(&phy->pdev->dev, phy->pwr_info.phy_pwr.vregs);
  209. phy->pwr_info.phy_pwr.vregs = NULL;
  210. phy->pwr_info.phy_pwr.count = 0;
  211. }
  212. if (phy->pwr_info.digital.vregs) {
  213. devm_kfree(&phy->pdev->dev, phy->pwr_info.digital.vregs);
  214. phy->pwr_info.digital.vregs = NULL;
  215. phy->pwr_info.digital.count = 0;
  216. }
  217. return rc;
  218. }
  219. static int dsi_phy_parse_dt_per_lane_cfgs(struct platform_device *pdev,
  220. struct dsi_phy_per_lane_cfgs *cfg,
  221. char *property)
  222. {
  223. int rc = 0, i = 0, j = 0;
  224. const u8 *data;
  225. u32 len = 0;
  226. data = of_get_property(pdev->dev.of_node, property, &len);
  227. if (!data) {
  228. DSI_ERR("Unable to read Phy %s settings\n", property);
  229. return -EINVAL;
  230. }
  231. if (len != DSI_LANE_MAX * cfg->count_per_lane) {
  232. DSI_ERR("incorrect phy %s settings, exp=%d, act=%d\n",
  233. property, (DSI_LANE_MAX * cfg->count_per_lane), len);
  234. return -EINVAL;
  235. }
  236. for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
  237. for (j = 0; j < cfg->count_per_lane; j++) {
  238. cfg->lane[i][j] = *data;
  239. data++;
  240. }
  241. }
  242. return rc;
  243. }
  244. static int dsi_phy_settings_init(struct platform_device *pdev,
  245. struct msm_dsi_phy *phy)
  246. {
  247. int rc = 0;
  248. struct dsi_phy_per_lane_cfgs *lane = &phy->cfg.lanecfg;
  249. struct dsi_phy_per_lane_cfgs *strength = &phy->cfg.strength;
  250. struct dsi_phy_per_lane_cfgs *timing = &phy->cfg.timing;
  251. struct dsi_phy_per_lane_cfgs *regs = &phy->cfg.regulators;
  252. lane->count_per_lane = phy->ver_info->lane_cfg_count;
  253. rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, lane,
  254. "qcom,platform-lane-config");
  255. if (rc) {
  256. DSI_PHY_ERR(phy, "failed to parse lane cfgs, rc=%d\n", rc);
  257. goto err;
  258. }
  259. strength->count_per_lane = phy->ver_info->strength_cfg_count;
  260. rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, strength,
  261. "qcom,platform-strength-ctrl");
  262. if (rc) {
  263. DSI_PHY_ERR(phy, "failed to parse lane cfgs, rc=%d\n", rc);
  264. goto err;
  265. }
  266. regs->count_per_lane = phy->ver_info->regulator_cfg_count;
  267. if (regs->count_per_lane > 0) {
  268. rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, regs,
  269. "qcom,platform-regulator-settings");
  270. if (rc) {
  271. DSI_PHY_ERR(phy, "failed to parse lane cfgs, rc=%d\n",
  272. rc);
  273. goto err;
  274. }
  275. }
  276. /* Actual timing values are dependent on panel */
  277. timing->count_per_lane = phy->ver_info->timing_cfg_count;
  278. phy->allow_phy_power_off = of_property_read_bool(pdev->dev.of_node,
  279. "qcom,panel-allow-phy-poweroff");
  280. of_property_read_u32(pdev->dev.of_node,
  281. "qcom,dsi-phy-regulator-min-datarate-bps",
  282. &phy->regulator_min_datarate_bps);
  283. phy->cfg.force_clk_lane_hs = of_property_read_bool(pdev->dev.of_node,
  284. "qcom,panel-force-clock-lane-hs");
  285. return 0;
  286. err:
  287. lane->count_per_lane = 0;
  288. strength->count_per_lane = 0;
  289. regs->count_per_lane = 0;
  290. timing->count_per_lane = 0;
  291. return rc;
  292. }
  293. static int dsi_phy_settings_deinit(struct msm_dsi_phy *phy)
  294. {
  295. memset(&phy->cfg.lanecfg, 0x0, sizeof(phy->cfg.lanecfg));
  296. memset(&phy->cfg.strength, 0x0, sizeof(phy->cfg.strength));
  297. memset(&phy->cfg.timing, 0x0, sizeof(phy->cfg.timing));
  298. memset(&phy->cfg.regulators, 0x0, sizeof(phy->cfg.regulators));
  299. return 0;
  300. }
  301. static int dsi_phy_driver_probe(struct platform_device *pdev)
  302. {
  303. struct msm_dsi_phy *dsi_phy;
  304. struct dsi_phy_list_item *item;
  305. const struct of_device_id *id;
  306. const struct dsi_ver_spec_info *ver_info;
  307. int rc = 0;
  308. u32 index = 0;
  309. if (!pdev || !pdev->dev.of_node) {
  310. DSI_ERR("pdev not found\n");
  311. return -ENODEV;
  312. }
  313. id = of_match_node(msm_dsi_phy_of_match, pdev->dev.of_node);
  314. if (!id)
  315. return -ENODEV;
  316. ver_info = id->data;
  317. item = devm_kzalloc(&pdev->dev, sizeof(*item), GFP_KERNEL);
  318. if (!item)
  319. return -ENOMEM;
  320. dsi_phy = devm_kzalloc(&pdev->dev, sizeof(*dsi_phy), GFP_KERNEL);
  321. if (!dsi_phy) {
  322. devm_kfree(&pdev->dev, item);
  323. return -ENOMEM;
  324. }
  325. rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &index);
  326. if (rc) {
  327. DSI_PHY_DBG(dsi_phy, "cell index not set, default to 0\n");
  328. index = 0;
  329. }
  330. dsi_phy->index = index;
  331. dsi_phy->name = of_get_property(pdev->dev.of_node, "label", NULL);
  332. if (!dsi_phy->name)
  333. dsi_phy->name = DSI_PHY_DEFAULT_LABEL;
  334. DSI_PHY_DBG(dsi_phy, "Probing device\n");
  335. dsi_phy->ver_info = ver_info;
  336. rc = dsi_phy_regmap_init(pdev, dsi_phy);
  337. if (rc) {
  338. DSI_PHY_ERR(dsi_phy, "Failed to parse register information, rc=%d\n",
  339. rc);
  340. goto fail;
  341. }
  342. rc = dsi_phy_supplies_init(pdev, dsi_phy);
  343. if (rc) {
  344. DSI_PHY_ERR(dsi_phy, "failed to parse voltage supplies, rc = %d\n",
  345. rc);
  346. goto fail_regmap;
  347. }
  348. rc = dsi_catalog_phy_setup(&dsi_phy->hw, ver_info->version,
  349. dsi_phy->index);
  350. if (rc) {
  351. DSI_PHY_ERR(dsi_phy, "Catalog does not support version (%d)\n",
  352. ver_info->version);
  353. goto fail_supplies;
  354. }
  355. rc = dsi_phy_settings_init(pdev, dsi_phy);
  356. if (rc) {
  357. DSI_PHY_ERR(dsi_phy, "Failed to parse phy setting, rc=%d\n",
  358. rc);
  359. goto fail_supplies;
  360. }
  361. item->phy = dsi_phy;
  362. mutex_lock(&dsi_phy_list_lock);
  363. list_add(&item->list, &dsi_phy_list);
  364. mutex_unlock(&dsi_phy_list_lock);
  365. mutex_init(&dsi_phy->phy_lock);
  366. /** TODO: initialize debugfs */
  367. dsi_phy->pdev = pdev;
  368. platform_set_drvdata(pdev, dsi_phy);
  369. DSI_PHY_INFO(dsi_phy, "Probe successful\n");
  370. return 0;
  371. fail_supplies:
  372. (void)dsi_phy_supplies_deinit(dsi_phy);
  373. fail_regmap:
  374. (void)dsi_phy_regmap_deinit(dsi_phy);
  375. fail:
  376. devm_kfree(&pdev->dev, dsi_phy);
  377. devm_kfree(&pdev->dev, item);
  378. return rc;
  379. }
  380. static int dsi_phy_driver_remove(struct platform_device *pdev)
  381. {
  382. int rc = 0;
  383. struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
  384. struct list_head *pos, *tmp;
  385. if (!pdev || !phy) {
  386. DSI_PHY_ERR(phy, "Invalid device\n");
  387. return -EINVAL;
  388. }
  389. mutex_lock(&dsi_phy_list_lock);
  390. list_for_each_safe(pos, tmp, &dsi_phy_list) {
  391. struct dsi_phy_list_item *n;
  392. n = list_entry(pos, struct dsi_phy_list_item, list);
  393. if (n->phy == phy) {
  394. list_del(&n->list);
  395. devm_kfree(&pdev->dev, n);
  396. break;
  397. }
  398. }
  399. mutex_unlock(&dsi_phy_list_lock);
  400. mutex_lock(&phy->phy_lock);
  401. rc = dsi_phy_settings_deinit(phy);
  402. if (rc)
  403. DSI_PHY_ERR(phy, "failed to deinitialize phy settings, rc=%d\n",
  404. rc);
  405. rc = dsi_phy_supplies_deinit(phy);
  406. if (rc)
  407. DSI_PHY_ERR(phy, "failed to deinitialize voltage supplies, rc=%d\n",
  408. rc);
  409. rc = dsi_phy_regmap_deinit(phy);
  410. if (rc)
  411. DSI_PHY_ERR(phy, "failed to deinitialize regmap, rc=%d\n", rc);
  412. mutex_unlock(&phy->phy_lock);
  413. mutex_destroy(&phy->phy_lock);
  414. devm_kfree(&pdev->dev, phy);
  415. platform_set_drvdata(pdev, NULL);
  416. return 0;
  417. }
  418. static struct platform_driver dsi_phy_platform_driver = {
  419. .probe = dsi_phy_driver_probe,
  420. .remove = dsi_phy_driver_remove,
  421. .driver = {
  422. .name = "dsi_phy",
  423. .of_match_table = msm_dsi_phy_of_match,
  424. },
  425. };
  426. static void dsi_phy_enable_hw(struct msm_dsi_phy *phy)
  427. {
  428. if (phy->hw.ops.regulator_enable)
  429. phy->hw.ops.regulator_enable(&phy->hw, &phy->cfg.regulators);
  430. if (phy->hw.ops.enable)
  431. phy->hw.ops.enable(&phy->hw, &phy->cfg);
  432. }
  433. static void dsi_phy_disable_hw(struct msm_dsi_phy *phy)
  434. {
  435. if (phy->hw.ops.disable)
  436. phy->hw.ops.disable(&phy->hw, &phy->cfg);
  437. if (phy->hw.ops.regulator_disable)
  438. phy->hw.ops.regulator_disable(&phy->hw);
  439. }
  440. /**
  441. * dsi_phy_get() - get a dsi phy handle from device node
  442. * @of_node: device node for dsi phy controller
  443. *
  444. * Gets the DSI PHY handle for the corresponding of_node. The ref count is
  445. * incremented to one all subsequents get will fail until the original client
  446. * calls a put.
  447. *
  448. * Return: DSI PHY handle or an error code.
  449. */
  450. struct msm_dsi_phy *dsi_phy_get(struct device_node *of_node)
  451. {
  452. struct list_head *pos, *tmp;
  453. struct msm_dsi_phy *phy = NULL;
  454. mutex_lock(&dsi_phy_list_lock);
  455. list_for_each_safe(pos, tmp, &dsi_phy_list) {
  456. struct dsi_phy_list_item *n;
  457. n = list_entry(pos, struct dsi_phy_list_item, list);
  458. if (n->phy->pdev->dev.of_node == of_node) {
  459. phy = n->phy;
  460. break;
  461. }
  462. }
  463. mutex_unlock(&dsi_phy_list_lock);
  464. if (!phy) {
  465. DSI_PHY_ERR(phy, "Device with of node not found\n");
  466. phy = ERR_PTR(-EPROBE_DEFER);
  467. return phy;
  468. }
  469. mutex_lock(&phy->phy_lock);
  470. if (phy->refcount > 0) {
  471. DSI_PHY_ERR(phy, "Device under use\n");
  472. phy = ERR_PTR(-EINVAL);
  473. } else {
  474. phy->refcount++;
  475. }
  476. mutex_unlock(&phy->phy_lock);
  477. return phy;
  478. }
  479. /**
  480. * dsi_phy_put() - release dsi phy handle
  481. * @dsi_phy: DSI PHY handle.
  482. *
  483. * Release the DSI PHY hardware. Driver will clean up all resources and puts
  484. * back the DSI PHY into reset state.
  485. */
  486. void dsi_phy_put(struct msm_dsi_phy *dsi_phy)
  487. {
  488. mutex_lock(&dsi_phy->phy_lock);
  489. if (dsi_phy->refcount == 0)
  490. DSI_PHY_ERR(dsi_phy, "Unbalanced %s call\n", __func__);
  491. else
  492. dsi_phy->refcount--;
  493. mutex_unlock(&dsi_phy->phy_lock);
  494. }
  495. /**
  496. * dsi_phy_drv_init() - initialize dsi phy driver
  497. * @dsi_phy: DSI PHY handle.
  498. *
  499. * Initializes DSI PHY driver. Should be called after dsi_phy_get().
  500. *
  501. * Return: error code.
  502. */
  503. int dsi_phy_drv_init(struct msm_dsi_phy *dsi_phy)
  504. {
  505. char dbg_name[DSI_DEBUG_NAME_LEN];
  506. snprintf(dbg_name, DSI_DEBUG_NAME_LEN, "dsi%d_phy", dsi_phy->index);
  507. sde_dbg_reg_register_base(dbg_name, dsi_phy->hw.base,
  508. msm_iomap_size(dsi_phy->pdev, "dsi_phy"));
  509. return 0;
  510. }
  511. /**
  512. * dsi_phy_drv_deinit() - de-initialize dsi phy driver
  513. * @dsi_phy: DSI PHY handle.
  514. *
  515. * Release all resources acquired by dsi_phy_drv_init().
  516. *
  517. * Return: error code.
  518. */
  519. int dsi_phy_drv_deinit(struct msm_dsi_phy *dsi_phy)
  520. {
  521. return 0;
  522. }
  523. int dsi_phy_clk_cb_register(struct msm_dsi_phy *dsi_phy,
  524. struct clk_ctrl_cb *clk_cb)
  525. {
  526. if (!dsi_phy || !clk_cb) {
  527. DSI_PHY_ERR(dsi_phy, "Invalid params\n");
  528. return -EINVAL;
  529. }
  530. dsi_phy->clk_cb.priv = clk_cb->priv;
  531. dsi_phy->clk_cb.dsi_clk_cb = clk_cb->dsi_clk_cb;
  532. return 0;
  533. }
  534. /**
  535. * dsi_phy_validate_mode() - validate a display mode
  536. * @dsi_phy: DSI PHY handle.
  537. * @mode: Mode information.
  538. *
  539. * Validation will fail if the mode cannot be supported by the PHY driver or
  540. * hardware.
  541. *
  542. * Return: error code.
  543. */
  544. int dsi_phy_validate_mode(struct msm_dsi_phy *dsi_phy,
  545. struct dsi_mode_info *mode)
  546. {
  547. int rc = 0;
  548. if (!dsi_phy || !mode) {
  549. DSI_PHY_ERR(dsi_phy, "Invalid params\n");
  550. return -EINVAL;
  551. }
  552. DSI_PHY_DBG(dsi_phy, "Skipping validation\n");
  553. return rc;
  554. }
  555. /**
  556. * dsi_phy_set_power_state() - enable/disable dsi phy power supplies
  557. * @dsi_phy: DSI PHY handle.
  558. * @enable: Boolean flag to enable/disable.
  559. *
  560. * Return: error code.
  561. */
  562. int dsi_phy_set_power_state(struct msm_dsi_phy *dsi_phy, bool enable)
  563. {
  564. int rc = 0;
  565. if (!dsi_phy) {
  566. DSI_PHY_ERR(dsi_phy, "Invalid params\n");
  567. return -EINVAL;
  568. }
  569. mutex_lock(&dsi_phy->phy_lock);
  570. if (enable == dsi_phy->power_state) {
  571. DSI_PHY_ERR(dsi_phy, "No state change\n");
  572. goto error;
  573. }
  574. if (enable) {
  575. rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.digital, true);
  576. if (rc) {
  577. DSI_PHY_ERR(dsi_phy, "failed to enable digital regulator\n");
  578. goto error;
  579. }
  580. if (dsi_phy->dsi_phy_state == DSI_PHY_ENGINE_OFF &&
  581. dsi_phy->regulator_required) {
  582. rc = dsi_pwr_enable_regulator(
  583. &dsi_phy->pwr_info.phy_pwr, true);
  584. if (rc) {
  585. DSI_PHY_ERR(dsi_phy, "failed to enable phy power\n");
  586. (void)dsi_pwr_enable_regulator(
  587. &dsi_phy->pwr_info.digital, false);
  588. goto error;
  589. }
  590. }
  591. } else {
  592. if (dsi_phy->dsi_phy_state == DSI_PHY_ENGINE_OFF &&
  593. dsi_phy->regulator_required) {
  594. rc = dsi_pwr_enable_regulator(
  595. &dsi_phy->pwr_info.phy_pwr, false);
  596. if (rc) {
  597. DSI_PHY_ERR(dsi_phy, "failed to enable digital regulator\n");
  598. goto error;
  599. }
  600. }
  601. rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.digital,
  602. false);
  603. if (rc) {
  604. DSI_PHY_ERR(dsi_phy, "failed to enable phy power\n");
  605. goto error;
  606. }
  607. }
  608. dsi_phy->power_state = enable;
  609. error:
  610. mutex_unlock(&dsi_phy->phy_lock);
  611. return rc;
  612. }
  613. static int dsi_phy_enable_ulps(struct msm_dsi_phy *phy,
  614. struct dsi_host_config *config, bool clamp_enabled)
  615. {
  616. int rc = 0;
  617. u32 lanes = 0;
  618. u32 ulps_lanes;
  619. lanes = config->common_config.data_lanes;
  620. lanes |= DSI_CLOCK_LANE;
  621. /*
  622. * If DSI clamps are enabled, it means that the DSI lanes are
  623. * already in idle state. Checking for lanes to be in idle state
  624. * should be skipped during ULPS entry programming while coming
  625. * out of idle screen.
  626. */
  627. if (!clamp_enabled) {
  628. rc = phy->hw.ops.ulps_ops.wait_for_lane_idle(&phy->hw, lanes);
  629. if (rc) {
  630. DSI_PHY_ERR(phy, "lanes not entering idle, skip ULPS\n");
  631. return rc;
  632. }
  633. }
  634. phy->hw.ops.ulps_ops.ulps_request(&phy->hw, &phy->cfg, lanes);
  635. ulps_lanes = phy->hw.ops.ulps_ops.get_lanes_in_ulps(&phy->hw);
  636. if (!phy->hw.ops.ulps_ops.is_lanes_in_ulps(lanes, ulps_lanes)) {
  637. DSI_PHY_ERR(phy, "Failed to enter ULPS, request=0x%x, actual=0x%x\n",
  638. lanes, ulps_lanes);
  639. rc = -EIO;
  640. }
  641. return rc;
  642. }
  643. static int dsi_phy_disable_ulps(struct msm_dsi_phy *phy,
  644. struct dsi_host_config *config)
  645. {
  646. u32 ulps_lanes, lanes = 0;
  647. lanes = config->common_config.data_lanes;
  648. lanes |= DSI_CLOCK_LANE;
  649. ulps_lanes = phy->hw.ops.ulps_ops.get_lanes_in_ulps(&phy->hw);
  650. if (!phy->hw.ops.ulps_ops.is_lanes_in_ulps(lanes, ulps_lanes)) {
  651. DSI_PHY_ERR(phy, "Mismatch in ULPS: lanes:%d, ulps_lanes:%d\n",
  652. lanes, ulps_lanes);
  653. return -EIO;
  654. }
  655. phy->hw.ops.ulps_ops.ulps_exit(&phy->hw, &phy->cfg, lanes);
  656. ulps_lanes = phy->hw.ops.ulps_ops.get_lanes_in_ulps(&phy->hw);
  657. if (phy->hw.ops.ulps_ops.is_lanes_in_ulps(lanes, ulps_lanes)) {
  658. DSI_PHY_ERR(phy, "Lanes (0x%x) stuck in ULPS\n", ulps_lanes);
  659. return -EIO;
  660. }
  661. return 0;
  662. }
  663. void dsi_phy_toggle_resync_fifo(struct msm_dsi_phy *phy)
  664. {
  665. if (!phy)
  666. return;
  667. if (!phy->hw.ops.toggle_resync_fifo)
  668. return;
  669. phy->hw.ops.toggle_resync_fifo(&phy->hw);
  670. }
  671. void dsi_phy_reset_clk_en_sel(struct msm_dsi_phy *phy)
  672. {
  673. if (!phy)
  674. return;
  675. if (!phy->hw.ops.reset_clk_en_sel)
  676. return;
  677. phy->hw.ops.reset_clk_en_sel(&phy->hw);
  678. }
  679. int dsi_phy_set_ulps(struct msm_dsi_phy *phy, struct dsi_host_config *config,
  680. bool enable, bool clamp_enabled)
  681. {
  682. int rc = 0;
  683. if (!phy) {
  684. DSI_PHY_ERR(phy, "Invalid params\n");
  685. return DSI_PHY_ULPS_ERROR;
  686. }
  687. if (!phy->hw.ops.ulps_ops.ulps_request ||
  688. !phy->hw.ops.ulps_ops.ulps_exit ||
  689. !phy->hw.ops.ulps_ops.get_lanes_in_ulps ||
  690. !phy->hw.ops.ulps_ops.is_lanes_in_ulps ||
  691. !phy->hw.ops.ulps_ops.wait_for_lane_idle) {
  692. DSI_PHY_DBG(phy, "DSI PHY ULPS ops not present\n");
  693. return DSI_PHY_ULPS_NOT_HANDLED;
  694. }
  695. mutex_lock(&phy->phy_lock);
  696. if (enable)
  697. rc = dsi_phy_enable_ulps(phy, config, clamp_enabled);
  698. else
  699. rc = dsi_phy_disable_ulps(phy, config);
  700. if (rc) {
  701. DSI_PHY_ERR(phy, "Ulps state change(%d) failed, rc=%d\n",
  702. enable, rc);
  703. rc = DSI_PHY_ULPS_ERROR;
  704. goto error;
  705. }
  706. DSI_PHY_DBG(phy, "ULPS state = %d\n", enable);
  707. error:
  708. mutex_unlock(&phy->phy_lock);
  709. return rc;
  710. }
  711. /**
  712. * dsi_phy_enable() - enable DSI PHY hardware
  713. * @dsi_phy: DSI PHY handle.
  714. * @config: DSI host configuration.
  715. * @pll_source: Source PLL for PHY clock.
  716. * @skip_validation: Validation will not be performed on parameters.
  717. * @is_cont_splash_enabled: check whether continuous splash enabled.
  718. *
  719. * Validates and enables DSI PHY.
  720. *
  721. * Return: error code.
  722. */
  723. int dsi_phy_enable(struct msm_dsi_phy *phy,
  724. struct dsi_host_config *config,
  725. enum dsi_phy_pll_source pll_source,
  726. bool skip_validation,
  727. bool is_cont_splash_enabled)
  728. {
  729. int rc = 0;
  730. if (!phy || !config) {
  731. DSI_PHY_ERR(phy, "Invalid params\n");
  732. return -EINVAL;
  733. }
  734. mutex_lock(&phy->phy_lock);
  735. if (!skip_validation)
  736. DSI_PHY_DBG(phy, "TODO: perform validation\n");
  737. memcpy(&phy->mode, &config->video_timing, sizeof(phy->mode));
  738. memcpy(&phy->cfg.lane_map, &config->lane_map, sizeof(config->lane_map));
  739. phy->data_lanes = config->common_config.data_lanes;
  740. phy->dst_format = config->common_config.dst_format;
  741. phy->cfg.pll_source = pll_source;
  742. phy->cfg.bit_clk_rate_hz = config->bit_clk_rate_hz;
  743. /**
  744. * If PHY timing parameters are not present in panel dtsi file,
  745. * then calculate them in the driver
  746. */
  747. if (!phy->cfg.is_phy_timing_present)
  748. rc = phy->hw.ops.calculate_timing_params(&phy->hw,
  749. &phy->mode,
  750. &config->common_config,
  751. &phy->cfg.timing, false);
  752. if (rc) {
  753. DSI_PHY_ERR(phy, "failed to set timing, rc=%d\n", rc);
  754. goto error;
  755. }
  756. if (!is_cont_splash_enabled) {
  757. dsi_phy_enable_hw(phy);
  758. DSI_PHY_DBG(phy, "cont splash not enabled, phy enable required\n");
  759. }
  760. phy->dsi_phy_state = DSI_PHY_ENGINE_ON;
  761. error:
  762. mutex_unlock(&phy->phy_lock);
  763. return rc;
  764. }
  765. /* update dsi phy timings for dynamic clk switch use case */
  766. int dsi_phy_update_phy_timings(struct msm_dsi_phy *phy,
  767. struct dsi_host_config *config)
  768. {
  769. int rc = 0;
  770. if (!phy || !config) {
  771. DSI_PHY_ERR(phy, "invalid argument\n");
  772. return -EINVAL;
  773. }
  774. memcpy(&phy->mode, &config->video_timing, sizeof(phy->mode));
  775. rc = phy->hw.ops.calculate_timing_params(&phy->hw, &phy->mode,
  776. &config->common_config,
  777. &phy->cfg.timing, true);
  778. if (rc)
  779. DSI_PHY_ERR(phy, "failed to calculate phy timings %d\n", rc);
  780. return rc;
  781. }
  782. int dsi_phy_lane_reset(struct msm_dsi_phy *phy)
  783. {
  784. int ret = 0;
  785. if (!phy)
  786. return ret;
  787. mutex_lock(&phy->phy_lock);
  788. if (phy->hw.ops.phy_lane_reset)
  789. ret = phy->hw.ops.phy_lane_reset(&phy->hw);
  790. mutex_unlock(&phy->phy_lock);
  791. return ret;
  792. }
  793. /**
  794. * dsi_phy_disable() - disable DSI PHY hardware.
  795. * @phy: DSI PHY handle.
  796. *
  797. * Return: error code.
  798. */
  799. int dsi_phy_disable(struct msm_dsi_phy *phy)
  800. {
  801. int rc = 0;
  802. if (!phy) {
  803. DSI_PHY_ERR(phy, "Invalid params\n");
  804. return -EINVAL;
  805. }
  806. mutex_lock(&phy->phy_lock);
  807. dsi_phy_disable_hw(phy);
  808. phy->dsi_phy_state = DSI_PHY_ENGINE_OFF;
  809. mutex_unlock(&phy->phy_lock);
  810. return rc;
  811. }
  812. /**
  813. * dsi_phy_set_clamp_state() - configure clamps for DSI lanes
  814. * @phy: DSI PHY handle.
  815. * @enable: boolean to specify clamp enable/disable.
  816. *
  817. * Return: error code.
  818. */
  819. int dsi_phy_set_clamp_state(struct msm_dsi_phy *phy, bool enable)
  820. {
  821. if (!phy)
  822. return -EINVAL;
  823. DSI_PHY_DBG(phy, "enable=%d\n", enable);
  824. if (phy->hw.ops.clamp_ctrl)
  825. phy->hw.ops.clamp_ctrl(&phy->hw, enable);
  826. return 0;
  827. }
  828. /**
  829. * dsi_phy_idle_ctrl() - enable/disable DSI PHY during idle screen
  830. * @phy: DSI PHY handle
  831. * @enable: boolean to specify PHY enable/disable.
  832. *
  833. * Return: error code.
  834. */
  835. int dsi_phy_idle_ctrl(struct msm_dsi_phy *phy, bool enable)
  836. {
  837. if (!phy) {
  838. DSI_PHY_ERR(phy, "Invalid params\n");
  839. return -EINVAL;
  840. }
  841. DSI_PHY_DBG(phy, "enable=%d\n", enable);
  842. mutex_lock(&phy->phy_lock);
  843. if (enable) {
  844. if (phy->hw.ops.phy_idle_on)
  845. phy->hw.ops.phy_idle_on(&phy->hw, &phy->cfg);
  846. if (phy->hw.ops.regulator_enable)
  847. phy->hw.ops.regulator_enable(&phy->hw,
  848. &phy->cfg.regulators);
  849. if (phy->hw.ops.enable)
  850. phy->hw.ops.enable(&phy->hw, &phy->cfg);
  851. phy->dsi_phy_state = DSI_PHY_ENGINE_ON;
  852. } else {
  853. phy->dsi_phy_state = DSI_PHY_ENGINE_OFF;
  854. if (phy->hw.ops.disable)
  855. phy->hw.ops.disable(&phy->hw, &phy->cfg);
  856. if (phy->hw.ops.phy_idle_off)
  857. phy->hw.ops.phy_idle_off(&phy->hw);
  858. }
  859. mutex_unlock(&phy->phy_lock);
  860. return 0;
  861. }
  862. /**
  863. * dsi_phy_set_clk_freq() - set DSI PHY clock frequency setting
  864. * @phy: DSI PHY handle
  865. * @clk_freq: link clock frequency
  866. *
  867. * Return: error code.
  868. */
  869. int dsi_phy_set_clk_freq(struct msm_dsi_phy *phy,
  870. struct link_clk_freq *clk_freq)
  871. {
  872. if (!phy || !clk_freq) {
  873. DSI_PHY_ERR(phy, "Invalid params\n");
  874. return -EINVAL;
  875. }
  876. phy->regulator_required = clk_freq->byte_clk_rate >
  877. (phy->regulator_min_datarate_bps / BITS_PER_BYTE);
  878. /*
  879. * DSI PLL needs 0p9 LDO1A for Powering DSI PLL block.
  880. * PLL driver can vote for this regulator in PLL driver file, but for
  881. * the usecase where we come out of idle(static screen), if PLL and
  882. * PHY vote for regulator ,there will be performance delays as both
  883. * votes go through RPM to enable regulators.
  884. */
  885. phy->regulator_required = true;
  886. DSI_PHY_DBG(phy, "lane_datarate=%u min_datarate=%u required=%d\n",
  887. clk_freq->byte_clk_rate * BITS_PER_BYTE,
  888. phy->regulator_min_datarate_bps,
  889. phy->regulator_required);
  890. return 0;
  891. }
  892. /**
  893. * dsi_phy_set_timing_params() - timing parameters for the panel
  894. * @phy: DSI PHY handle
  895. * @timing: array holding timing params.
  896. * @size: size of the array.
  897. * @commit: boolean to indicate if programming PHY HW registers is
  898. * required
  899. *
  900. * When PHY timing calculator is not implemented, this array will be used to
  901. * pass PHY timing information.
  902. *
  903. * Return: error code.
  904. */
  905. int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
  906. u32 *timing, u32 size, bool commit)
  907. {
  908. int rc = 0;
  909. if (!phy || !timing || !size) {
  910. DSI_PHY_ERR(phy, "Invalid params\n");
  911. return -EINVAL;
  912. }
  913. mutex_lock(&phy->phy_lock);
  914. if (phy->hw.ops.phy_timing_val)
  915. rc = phy->hw.ops.phy_timing_val(&phy->cfg.timing, timing, size);
  916. if (!rc)
  917. phy->cfg.is_phy_timing_present = true;
  918. if (phy->hw.ops.commit_phy_timing && commit)
  919. phy->hw.ops.commit_phy_timing(&phy->hw, &phy->cfg.timing);
  920. mutex_unlock(&phy->phy_lock);
  921. return rc;
  922. }
  923. /**
  924. * dsi_phy_conv_phy_to_logical_lane() - Convert physical to logical lane
  925. * @lane_map: logical lane
  926. * @phy_lane: physical lane
  927. *
  928. * Return: Error code on failure. Lane number on success.
  929. */
  930. int dsi_phy_conv_phy_to_logical_lane(
  931. struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane)
  932. {
  933. int i = 0;
  934. if (phy_lane > DSI_PHYSICAL_LANE_3)
  935. return -EINVAL;
  936. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) {
  937. if (lane_map->lane_map_v2[i] == phy_lane)
  938. break;
  939. }
  940. return i;
  941. }
  942. /**
  943. * dsi_phy_conv_logical_to_phy_lane() - Convert logical to physical lane
  944. * @lane_map: physical lane
  945. * @lane: logical lane
  946. *
  947. * Return: Error code on failure. Lane number on success.
  948. */
  949. int dsi_phy_conv_logical_to_phy_lane(
  950. struct dsi_lane_map *lane_map, enum dsi_logical_lane lane)
  951. {
  952. int i = 0;
  953. if (lane > (DSI_LANE_MAX - 1))
  954. return -EINVAL;
  955. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) {
  956. if (BIT(i) == lane_map->lane_map_v2[lane])
  957. break;
  958. }
  959. return i;
  960. }
  961. /**
  962. * dsi_phy_config_dynamic_refresh() - Configure dynamic refresh registers
  963. * @phy: DSI PHY handle
  964. * @delay: pipe delays for dynamic refresh
  965. * @is_master: Boolean to indicate if for master or slave.
  966. */
  967. void dsi_phy_config_dynamic_refresh(struct msm_dsi_phy *phy,
  968. struct dsi_dyn_clk_delay *delay,
  969. bool is_master)
  970. {
  971. struct dsi_phy_cfg *cfg;
  972. if (!phy)
  973. return;
  974. mutex_lock(&phy->phy_lock);
  975. cfg = &phy->cfg;
  976. if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_config)
  977. phy->hw.ops.dyn_refresh_ops.dyn_refresh_config(&phy->hw, cfg,
  978. is_master);
  979. if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_pipe_delay)
  980. phy->hw.ops.dyn_refresh_ops.dyn_refresh_pipe_delay(
  981. &phy->hw, delay);
  982. mutex_unlock(&phy->phy_lock);
  983. }
  984. /**
  985. * dsi_phy_dynamic_refresh_trigger() - trigger dynamic refresh
  986. * @phy: DSI PHY handle
  987. * @is_master: Boolean to indicate if for master or slave.
  988. */
  989. void dsi_phy_dynamic_refresh_trigger(struct msm_dsi_phy *phy, bool is_master)
  990. {
  991. u32 off;
  992. if (!phy)
  993. return;
  994. mutex_lock(&phy->phy_lock);
  995. /*
  996. * program PLL_SWI_INTF_SEL and SW_TRIGGER bit only for
  997. * master and program SYNC_MODE bit only for slave.
  998. */
  999. if (is_master)
  1000. off = BIT(DYN_REFRESH_INTF_SEL) | BIT(DYN_REFRESH_SWI_CTRL) |
  1001. BIT(DYN_REFRESH_SW_TRIGGER);
  1002. else
  1003. off = BIT(DYN_REFRESH_SYNC_MODE) | BIT(DYN_REFRESH_SWI_CTRL);
  1004. if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper)
  1005. phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper(&phy->hw, off);
  1006. mutex_unlock(&phy->phy_lock);
  1007. }
  1008. /**
  1009. * dsi_phy_cache_phy_timings - cache the phy timings calculated as part of
  1010. * dynamic refresh.
  1011. * @phy: DSI PHY Handle.
  1012. * @dst: Pointer to cache location.
  1013. * @size: Number of phy lane settings.
  1014. */
  1015. int dsi_phy_dyn_refresh_cache_phy_timings(struct msm_dsi_phy *phy, u32 *dst,
  1016. u32 size)
  1017. {
  1018. int rc = 0;
  1019. if (!phy || !dst || !size)
  1020. return -EINVAL;
  1021. if (phy->hw.ops.dyn_refresh_ops.cache_phy_timings)
  1022. rc = phy->hw.ops.dyn_refresh_ops.cache_phy_timings(
  1023. &phy->cfg.timing, dst, size);
  1024. if (rc)
  1025. DSI_PHY_ERR(phy, "failed to cache phy timings %d\n", rc);
  1026. return rc;
  1027. }
  1028. /**
  1029. * dsi_phy_dynamic_refresh_clear() - clear dynamic refresh config
  1030. * @phy: DSI PHY handle
  1031. */
  1032. void dsi_phy_dynamic_refresh_clear(struct msm_dsi_phy *phy)
  1033. {
  1034. if (!phy)
  1035. return;
  1036. mutex_lock(&phy->phy_lock);
  1037. if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper)
  1038. phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper(&phy->hw, 0);
  1039. mutex_unlock(&phy->phy_lock);
  1040. }
  1041. /**
  1042. * dsi_phy_set_continuous_clk() - set/unset force clock lane HS request
  1043. * @phy: DSI PHY handle
  1044. * @enable: variable to control continuous clock
  1045. */
  1046. void dsi_phy_set_continuous_clk(struct msm_dsi_phy *phy, bool enable)
  1047. {
  1048. if (!phy)
  1049. return;
  1050. mutex_lock(&phy->phy_lock);
  1051. if (phy->hw.ops.set_continuous_clk)
  1052. phy->hw.ops.set_continuous_clk(&phy->hw, enable);
  1053. else
  1054. DSI_PHY_WARN(phy, "set_continuous_clk ops not present\n");
  1055. mutex_unlock(&phy->phy_lock);
  1056. }
  1057. void dsi_phy_drv_register(void)
  1058. {
  1059. platform_driver_register(&dsi_phy_platform_driver);
  1060. }
  1061. void dsi_phy_drv_unregister(void)
  1062. {
  1063. platform_driver_unregister(&dsi_phy_platform_driver);
  1064. }