sde_plane.c 130 KB

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  1. /*
  2. * Copyright (C) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/debugfs.h>
  20. #include <linux/dma-buf.h>
  21. #include <drm/sde_drm.h>
  22. #include <drm/msm_drm_pp.h>
  23. #include "msm_prop.h"
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include "sde_fence.h"
  27. #include "sde_formats.h"
  28. #include "sde_hw_sspp.h"
  29. #include "sde_hw_catalog_format.h"
  30. #include "sde_trace.h"
  31. #include "sde_crtc.h"
  32. #include "sde_vbif.h"
  33. #include "sde_plane.h"
  34. #include "sde_color_processing.h"
  35. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  36. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  37. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  40. #define PHASE_STEP_SHIFT 21
  41. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  42. #define PHASE_RESIDUAL 15
  43. #define SHARP_STRENGTH_DEFAULT 32
  44. #define SHARP_EDGE_THR_DEFAULT 112
  45. #define SHARP_SMOOTH_THR_DEFAULT 8
  46. #define SHARP_NOISE_THR_DEFAULT 2
  47. #define SDE_NAME_SIZE 12
  48. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  49. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  50. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  51. /* multirect rect index */
  52. enum {
  53. R0,
  54. R1,
  55. R_MAX
  56. };
  57. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  58. #define DEFAULT_REFRESH_RATE 60
  59. /**
  60. * enum sde_plane_qos - Different qos configurations for each pipe
  61. *
  62. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  63. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  64. * this configuration is mutually exclusive from VBLANK_CTRL.
  65. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  66. */
  67. enum sde_plane_qos {
  68. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  69. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  70. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  71. };
  72. /*
  73. * struct sde_plane - local sde plane structure
  74. * @aspace: address space pointer
  75. * @csc_cfg: Decoded user configuration for csc
  76. * @csc_usr_ptr: Points to csc_cfg if valid user config available
  77. * @csc_ptr: Points to sde_csc_cfg structure to use for current
  78. * @mplane_list: List of multirect planes of the same pipe
  79. * @catalog: Points to sde catalog structure
  80. * @revalidate: force revalidation of all the plane properties
  81. * @xin_halt_forced_clk: whether or not clocks were forced on for xin halt
  82. * @blob_rot_caps: Pointer to rotator capability blob
  83. */
  84. struct sde_plane {
  85. struct drm_plane base;
  86. struct mutex lock;
  87. enum sde_sspp pipe;
  88. uint32_t features; /* capabilities from catalog */
  89. uint32_t perf_features; /* perf capabilities from catalog */
  90. uint32_t nformats;
  91. uint32_t formats[64];
  92. struct sde_hw_pipe *pipe_hw;
  93. struct sde_hw_pipe_cfg pipe_cfg;
  94. struct sde_hw_sharp_cfg sharp_cfg;
  95. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  96. uint32_t color_fill;
  97. bool is_error;
  98. bool is_rt_pipe;
  99. bool is_virtual;
  100. struct list_head mplane_list;
  101. struct sde_mdss_cfg *catalog;
  102. bool revalidate;
  103. bool xin_halt_forced_clk;
  104. struct sde_csc_cfg csc_cfg;
  105. struct sde_csc_cfg *csc_usr_ptr;
  106. struct sde_csc_cfg *csc_ptr;
  107. const struct sde_sspp_sub_blks *pipe_sblk;
  108. char pipe_name[SDE_NAME_SIZE];
  109. struct msm_property_info property_info;
  110. struct msm_property_data property_data[PLANE_PROP_COUNT];
  111. struct drm_property_blob *blob_info;
  112. struct drm_property_blob *blob_rot_caps;
  113. /* debugfs related stuff */
  114. struct dentry *debugfs_root;
  115. bool debugfs_default_scale;
  116. };
  117. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  118. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  119. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  120. {
  121. struct msm_drm_private *priv;
  122. if (!plane || !plane->dev)
  123. return NULL;
  124. priv = plane->dev->dev_private;
  125. if (!priv)
  126. return NULL;
  127. return to_sde_kms(priv->kms);
  128. }
  129. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  130. {
  131. struct drm_plane_state *pstate = NULL;
  132. struct drm_crtc *drm_crtc = NULL;
  133. struct sde_crtc *sde_crtc = NULL;
  134. struct sde_crtc_mixer *mixer = NULL;
  135. struct sde_hw_ctl *ctl = NULL;
  136. if (!plane) {
  137. DRM_ERROR("Invalid plane %pK\n", plane);
  138. return NULL;
  139. }
  140. pstate = plane->state;
  141. if (!pstate) {
  142. DRM_ERROR("Invalid plane state %pK\n", pstate);
  143. return NULL;
  144. }
  145. drm_crtc = pstate->crtc;
  146. if (!drm_crtc) {
  147. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  148. return NULL;
  149. }
  150. sde_crtc = to_sde_crtc(drm_crtc);
  151. if (!sde_crtc) {
  152. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  153. return NULL;
  154. }
  155. /* it will always return the first mixer and single CTL */
  156. mixer = sde_crtc->mixers;
  157. if (!mixer) {
  158. DRM_ERROR("invalid mixer %pK\n", mixer);
  159. return NULL;
  160. }
  161. ctl = mixer->hw_ctl;
  162. if (!mixer) {
  163. DRM_ERROR("invalid ctl %pK\n", ctl);
  164. return NULL;
  165. }
  166. return ctl;
  167. }
  168. static bool sde_plane_enabled(const struct drm_plane_state *state)
  169. {
  170. return state && state->fb && state->crtc;
  171. }
  172. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  173. {
  174. struct sde_plane *psde;
  175. if (!plane)
  176. return false;
  177. psde = to_sde_plane(plane);
  178. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  179. }
  180. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  181. enum sde_sspp_multirect_index rect_mode, bool enable)
  182. {
  183. struct sde_plane *psde;
  184. if (!plane)
  185. return;
  186. psde = to_sde_plane(plane);
  187. if (psde->pipe_hw->ops.set_src_split_order)
  188. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  189. rect_mode, enable);
  190. }
  191. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  192. {
  193. struct sde_plane *psde;
  194. struct sde_kms *sde_kms;
  195. struct msm_drm_private *priv;
  196. if (!plane || !plane->dev) {
  197. SDE_ERROR("invalid plane %d\n");
  198. return;
  199. }
  200. priv = plane->dev->dev_private;
  201. if (!priv || !priv->kms) {
  202. SDE_ERROR("invalid KMS reference\n");
  203. return;
  204. }
  205. sde_kms = to_sde_kms(priv->kms);
  206. psde = to_sde_plane(plane);
  207. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm);
  208. }
  209. /**
  210. * _sde_plane_set_qos_lut - set danger, safe and creq LUT of the given plane
  211. * @plane: Pointer to drm plane
  212. * @crtc: Pointer to drm crtc to find refresh rate on mode
  213. * @fb: Pointer to framebuffer associated with the given plane
  214. */
  215. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  216. struct drm_crtc *crtc,
  217. struct drm_framebuffer *fb)
  218. {
  219. struct sde_plane *psde;
  220. const struct sde_format *fmt = NULL;
  221. u32 frame_rate, qos_count, fps_index = 0, lut_index, index;
  222. struct sde_perf_cfg *perf;
  223. struct sde_plane_state *pstate;
  224. if (!plane || !fb) {
  225. SDE_ERROR("invalid arguments\n");
  226. return;
  227. }
  228. psde = to_sde_plane(plane);
  229. pstate = to_sde_plane_state(plane->state);
  230. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  231. SDE_ERROR("invalid arguments\n");
  232. return;
  233. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  234. return;
  235. }
  236. frame_rate = crtc->mode.vrefresh;
  237. perf = &psde->catalog->perf;
  238. qos_count = perf->qos_refresh_count;
  239. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  240. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  241. (fps_index == qos_count - 1))
  242. break;
  243. fps_index++;
  244. }
  245. if (!psde->is_rt_pipe) {
  246. lut_index = SDE_QOS_LUT_USAGE_NRT;
  247. } else {
  248. fmt = sde_get_sde_format_ext(
  249. fb->format->format,
  250. fb->modifier);
  251. if (fmt && SDE_FORMAT_IS_LINEAR(fmt) &&
  252. pstate->scaler3_cfg.enable)
  253. lut_index = SDE_QOS_LUT_USAGE_LINEAR_QSEED;
  254. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  255. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  256. else if (pstate->scaler3_cfg.enable)
  257. lut_index = SDE_QOS_LUT_USAGE_MACROTILE_QSEED;
  258. else
  259. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  260. }
  261. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  262. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[index];
  263. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[index];
  264. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[index];
  265. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
  266. (fmt) ? fmt->base.pixel_format : 0,
  267. (fmt) ? fmt->fetch_mode : 0,
  268. psde->pipe_qos_cfg.danger_lut,
  269. psde->pipe_qos_cfg.safe_lut,
  270. psde->pipe_qos_cfg.creq_lut);
  271. SDE_DEBUG(
  272. "plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  273. plane->base.id,
  274. psde->pipe - SSPP_VIG0,
  275. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  276. fmt ? fmt->fetch_mode : -1,
  277. psde->pipe_qos_cfg.danger_lut,
  278. psde->pipe_qos_cfg.safe_lut,
  279. psde->pipe_qos_cfg.creq_lut);
  280. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  281. }
  282. /**
  283. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  284. * @plane: Pointer to drm plane
  285. * @enable: true to enable QoS control
  286. * @flags: QoS control mode (enum sde_plane_qos)
  287. */
  288. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  289. bool enable, u32 flags)
  290. {
  291. struct sde_plane *psde;
  292. if (!plane) {
  293. SDE_ERROR("invalid arguments\n");
  294. return;
  295. }
  296. psde = to_sde_plane(plane);
  297. if (!psde->pipe_hw || !psde->pipe_sblk) {
  298. SDE_ERROR("invalid arguments\n");
  299. return;
  300. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  301. return;
  302. }
  303. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  304. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  305. psde->pipe_qos_cfg.danger_vblank =
  306. psde->pipe_sblk->danger_vblank;
  307. psde->pipe_qos_cfg.vblank_en = enable;
  308. }
  309. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  310. /* this feature overrules previous VBLANK_CTRL */
  311. psde->pipe_qos_cfg.vblank_en = false;
  312. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  313. }
  314. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  315. psde->pipe_qos_cfg.danger_safe_en = enable;
  316. if (!psde->is_rt_pipe) {
  317. psde->pipe_qos_cfg.vblank_en = false;
  318. psde->pipe_qos_cfg.danger_safe_en = false;
  319. }
  320. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  321. plane->base.id,
  322. psde->pipe - SSPP_VIG0,
  323. psde->pipe_qos_cfg.danger_safe_en,
  324. psde->pipe_qos_cfg.vblank_en,
  325. psde->pipe_qos_cfg.creq_vblank,
  326. psde->pipe_qos_cfg.danger_vblank,
  327. psde->is_rt_pipe);
  328. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  329. &psde->pipe_qos_cfg);
  330. }
  331. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  332. {
  333. struct sde_plane *psde;
  334. if (!plane)
  335. return;
  336. psde = to_sde_plane(plane);
  337. psde->revalidate = enable;
  338. }
  339. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  340. {
  341. struct sde_plane *psde;
  342. int rc;
  343. if (!plane) {
  344. SDE_ERROR("invalid arguments\n");
  345. return -EINVAL;
  346. }
  347. psde = to_sde_plane(plane);
  348. if (!psde->is_rt_pipe)
  349. goto end;
  350. rc = pm_runtime_get_sync(plane->dev->dev);
  351. if (rc < 0) {
  352. SDE_ERROR("failed to enable power resource %d\n", rc);
  353. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  354. return rc;
  355. }
  356. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  357. pm_runtime_put_sync(plane->dev->dev);
  358. end:
  359. return 0;
  360. }
  361. /**
  362. * _sde_plane_set_ot_limit - set OT limit for the given plane
  363. * @plane: Pointer to drm plane
  364. * @crtc: Pointer to drm crtc
  365. */
  366. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  367. struct drm_crtc *crtc)
  368. {
  369. struct sde_plane *psde;
  370. struct sde_vbif_set_ot_params ot_params;
  371. struct msm_drm_private *priv;
  372. struct sde_kms *sde_kms;
  373. if (!plane || !plane->dev || !crtc) {
  374. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  375. !plane, !crtc);
  376. return;
  377. }
  378. priv = plane->dev->dev_private;
  379. if (!priv || !priv->kms) {
  380. SDE_ERROR("invalid KMS reference\n");
  381. return;
  382. }
  383. sde_kms = to_sde_kms(priv->kms);
  384. psde = to_sde_plane(plane);
  385. if (!psde->pipe_hw) {
  386. SDE_ERROR("invalid pipe reference\n");
  387. return;
  388. }
  389. memset(&ot_params, 0, sizeof(ot_params));
  390. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  391. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  392. ot_params.width = psde->pipe_cfg.src_rect.w;
  393. ot_params.height = psde->pipe_cfg.src_rect.h;
  394. ot_params.is_wfd = !psde->is_rt_pipe;
  395. ot_params.frame_rate = crtc->mode.vrefresh;
  396. ot_params.vbif_idx = VBIF_RT;
  397. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  398. ot_params.rd = true;
  399. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  400. }
  401. /**
  402. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  403. * @plane: Pointer to drm plane
  404. */
  405. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  406. {
  407. struct sde_plane *psde;
  408. struct sde_vbif_set_qos_params qos_params;
  409. struct msm_drm_private *priv;
  410. struct sde_kms *sde_kms;
  411. if (!plane || !plane->dev) {
  412. SDE_ERROR("invalid arguments\n");
  413. return;
  414. }
  415. priv = plane->dev->dev_private;
  416. if (!priv || !priv->kms) {
  417. SDE_ERROR("invalid KMS reference\n");
  418. return;
  419. }
  420. sde_kms = to_sde_kms(priv->kms);
  421. psde = to_sde_plane(plane);
  422. if (!psde->pipe_hw) {
  423. SDE_ERROR("invalid pipe reference\n");
  424. return;
  425. }
  426. memset(&qos_params, 0, sizeof(qos_params));
  427. qos_params.vbif_idx = VBIF_RT;
  428. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  429. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  430. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  431. qos_params.client_type = psde->is_rt_pipe ?
  432. VBIF_RT_CLIENT : VBIF_NRT_CLIENT;
  433. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  434. plane->base.id, qos_params.num,
  435. qos_params.vbif_idx,
  436. qos_params.xin_id, qos_params.client_type,
  437. qos_params.clk_ctrl);
  438. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  439. }
  440. /**
  441. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  442. * @plane: Pointer to drm plane
  443. * @pstate: Pointer to sde plane state
  444. */
  445. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  446. struct sde_plane_state *pstate)
  447. {
  448. struct sde_plane *psde;
  449. struct sde_hw_pipe_ts_cfg cfg;
  450. struct msm_drm_private *priv;
  451. struct sde_kms *sde_kms;
  452. if (!plane || !plane->dev) {
  453. SDE_ERROR("invalid arguments");
  454. return;
  455. }
  456. priv = plane->dev->dev_private;
  457. if (!priv || !priv->kms) {
  458. SDE_ERROR("invalid KMS reference\n");
  459. return;
  460. }
  461. sde_kms = to_sde_kms(priv->kms);
  462. psde = to_sde_plane(plane);
  463. if (!psde->pipe_hw) {
  464. SDE_ERROR("invalid pipe reference\n");
  465. return;
  466. }
  467. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  468. return;
  469. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  470. memset(&cfg, 0, sizeof(cfg));
  471. cfg.size = sde_plane_get_property(pstate,
  472. PLANE_PROP_PREFILL_SIZE);
  473. cfg.time = sde_plane_get_property(pstate,
  474. PLANE_PROP_PREFILL_TIME);
  475. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  476. plane->base.id, cfg.size, cfg.time);
  477. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  478. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  479. pstate->multirect_index);
  480. }
  481. /* helper to update a state's input fence pointer from the property */
  482. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  483. struct sde_plane_state *pstate, uint64_t fd)
  484. {
  485. if (!psde || !pstate) {
  486. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  487. !psde, !pstate);
  488. return;
  489. }
  490. /* clear previous reference */
  491. if (pstate->input_fence)
  492. sde_sync_put(pstate->input_fence);
  493. /* get fence pointer for later */
  494. if (fd == 0)
  495. pstate->input_fence = NULL;
  496. else
  497. pstate->input_fence = sde_sync_get(fd);
  498. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  499. }
  500. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  501. {
  502. struct sde_plane *psde;
  503. struct sde_plane_state *pstate;
  504. uint32_t prefix;
  505. void *input_fence;
  506. int ret = -EINVAL;
  507. signed long rc;
  508. if (!plane) {
  509. SDE_ERROR("invalid plane\n");
  510. } else if (!plane->state) {
  511. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  512. } else {
  513. psde = to_sde_plane(plane);
  514. pstate = to_sde_plane_state(plane->state);
  515. input_fence = pstate->input_fence;
  516. if (input_fence) {
  517. prefix = sde_sync_get_name_prefix(input_fence);
  518. rc = sde_sync_wait(input_fence, wait_ms);
  519. switch (rc) {
  520. case 0:
  521. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %d\n",
  522. wait_ms, prefix, sde_plane_get_property(pstate,
  523. PLANE_PROP_INPUT_FENCE));
  524. psde->is_error = true;
  525. sde_kms_timeline_status(plane->dev);
  526. ret = -ETIMEDOUT;
  527. break;
  528. case -ERESTARTSYS:
  529. SDE_ERROR_PLANE(psde,
  530. "%ums wait interrupted on %08X\n",
  531. wait_ms, prefix);
  532. psde->is_error = true;
  533. ret = -ERESTARTSYS;
  534. break;
  535. case -EINVAL:
  536. SDE_ERROR_PLANE(psde,
  537. "invalid fence param for %08X\n",
  538. prefix);
  539. psde->is_error = true;
  540. ret = -EINVAL;
  541. break;
  542. default:
  543. SDE_DEBUG_PLANE(psde, "signaled\n");
  544. ret = 0;
  545. break;
  546. }
  547. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  548. } else {
  549. ret = 0;
  550. }
  551. }
  552. return ret;
  553. }
  554. /**
  555. * _sde_plane_get_aspace: gets the address space based on the
  556. * fb_translation mode property
  557. */
  558. static int _sde_plane_get_aspace(
  559. struct sde_plane *psde,
  560. struct sde_plane_state *pstate,
  561. struct msm_gem_address_space **aspace)
  562. {
  563. struct sde_kms *kms;
  564. int mode;
  565. if (!psde || !pstate || !aspace) {
  566. SDE_ERROR("invalid parameters\n");
  567. return -EINVAL;
  568. }
  569. kms = _sde_plane_get_kms(&psde->base);
  570. if (!kms) {
  571. SDE_ERROR("invalid kms\n");
  572. return -EINVAL;
  573. }
  574. mode = sde_plane_get_property(pstate,
  575. PLANE_PROP_FB_TRANSLATION_MODE);
  576. switch (mode) {
  577. case SDE_DRM_FB_NON_SEC:
  578. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  579. if (!aspace)
  580. return -EINVAL;
  581. break;
  582. case SDE_DRM_FB_SEC:
  583. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  584. if (!aspace)
  585. return -EINVAL;
  586. break;
  587. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  588. case SDE_DRM_FB_SEC_DIR_TRANS:
  589. *aspace = NULL;
  590. break;
  591. default:
  592. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  593. return -EFAULT;
  594. }
  595. return 0;
  596. }
  597. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  598. struct sde_plane_state *pstate,
  599. struct sde_hw_pipe_cfg *pipe_cfg,
  600. struct drm_framebuffer *fb)
  601. {
  602. struct sde_plane *psde;
  603. struct msm_gem_address_space *aspace = NULL;
  604. int ret, mode;
  605. bool secure = false;
  606. if (!plane || !pstate || !pipe_cfg || !fb) {
  607. SDE_ERROR(
  608. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  609. !plane, !pstate, !pipe_cfg, !fb);
  610. return;
  611. }
  612. psde = to_sde_plane(plane);
  613. if (!psde->pipe_hw) {
  614. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  615. return;
  616. }
  617. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  618. if (ret) {
  619. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  620. return;
  621. }
  622. /*
  623. * framebuffer prepare is deferred for prepare_fb calls that
  624. * happen during the transition from secure to non-secure.
  625. * Handle the prepare at this point for such cases. This can be
  626. * expected for one or two frames during the transition.
  627. */
  628. if (aspace && pstate->defer_prepare_fb) {
  629. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  630. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  631. if (ret) {
  632. SDE_ERROR_PLANE(psde,
  633. "failed to prepare framebuffer %d\n", ret);
  634. return;
  635. }
  636. pstate->defer_prepare_fb = false;
  637. }
  638. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  639. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  640. secure = true;
  641. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  642. if (ret == -EAGAIN)
  643. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  644. else if (ret) {
  645. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  646. /*
  647. * Force solid fill color on error. This is to prevent
  648. * smmu faults during secure session transition.
  649. */
  650. psde->is_error = true;
  651. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  652. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  653. pipe_cfg->layout.width,
  654. pipe_cfg->layout.height,
  655. pipe_cfg->layout.plane_addr[0],
  656. pipe_cfg->layout.plane_size[0],
  657. pipe_cfg->layout.plane_addr[1],
  658. pipe_cfg->layout.plane_size[1],
  659. pipe_cfg->layout.plane_addr[2],
  660. pipe_cfg->layout.plane_size[2],
  661. pipe_cfg->layout.plane_addr[3],
  662. pipe_cfg->layout.plane_size[3],
  663. pstate->multirect_index,
  664. secure);
  665. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  666. pstate->multirect_index);
  667. }
  668. }
  669. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  670. struct sde_plane_state *pstate)
  671. {
  672. struct sde_hw_scaler3_cfg *cfg;
  673. int ret = 0;
  674. if (!psde || !pstate) {
  675. SDE_ERROR("invalid args\n");
  676. return -EINVAL;
  677. }
  678. cfg = &pstate->scaler3_cfg;
  679. cfg->dir_lut = msm_property_get_blob(
  680. &psde->property_info,
  681. &pstate->property_state, &cfg->dir_len,
  682. PLANE_PROP_SCALER_LUT_ED);
  683. cfg->cir_lut = msm_property_get_blob(
  684. &psde->property_info,
  685. &pstate->property_state, &cfg->cir_len,
  686. PLANE_PROP_SCALER_LUT_CIR);
  687. cfg->sep_lut = msm_property_get_blob(
  688. &psde->property_info,
  689. &pstate->property_state, &cfg->sep_len,
  690. PLANE_PROP_SCALER_LUT_SEP);
  691. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  692. ret = -ENODATA;
  693. return ret;
  694. }
  695. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  696. struct sde_plane_state *pstate)
  697. {
  698. struct sde_hw_scaler3_cfg *cfg;
  699. cfg = &pstate->scaler3_cfg;
  700. cfg->sep_lut = msm_property_get_blob(
  701. &psde->property_info,
  702. &pstate->property_state, &cfg->sep_len,
  703. PLANE_PROP_SCALER_LUT_SEP);
  704. return cfg->sep_lut ? 0 : -ENODATA;
  705. }
  706. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  707. struct sde_plane_state *pstate, const struct sde_format *fmt,
  708. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  709. {
  710. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  711. struct sde_hw_scaler3_cfg *scale_cfg;
  712. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  713. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  714. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  715. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  716. chroma_subsmpl_h, chroma_subsmpl_v);
  717. return;
  718. }
  719. scale_cfg = &pstate->scaler3_cfg;
  720. src_w = psde->pipe_cfg.src_rect.w;
  721. src_h = psde->pipe_cfg.src_rect.h;
  722. dst_w = psde->pipe_cfg.dst_rect.w;
  723. dst_h = psde->pipe_cfg.dst_rect.h;
  724. memset(scale_cfg, 0, sizeof(*scale_cfg));
  725. memset(&pstate->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  726. /*
  727. * For inline rotation cases, scaler config is post-rotation,
  728. * so swap the dimensions here. However, pixel extension will
  729. * need pre-rotation settings, this will be corrected below
  730. * when calculating pixel extension settings.
  731. */
  732. if (inline_rotation)
  733. swap(src_w, src_h);
  734. decimated = DECIMATED_DIMENSION(src_w,
  735. psde->pipe_cfg.horz_decimation);
  736. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  737. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  738. decimated = DECIMATED_DIMENSION(src_h,
  739. psde->pipe_cfg.vert_decimation);
  740. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  741. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  742. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  743. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  744. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  745. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  746. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  747. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  748. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  749. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  750. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  751. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  752. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  753. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  754. for (i = 0; i < SDE_MAX_PLANES; i++) {
  755. /*
  756. * For inline rotation cases with pre-downscaling enabled
  757. * set x pre-downscale value if required. Only x direction
  758. * is currently supported. Use src_h as values have been swapped
  759. * and x direction corresponds to height value.
  760. */
  761. src_h_pre_down = src_h;
  762. if (pre_down_supported && inline_rotation) {
  763. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  764. src_h_pre_down = src_h / 2;
  765. }
  766. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  767. psde->pipe_cfg.horz_decimation);
  768. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  769. psde->pipe_cfg.vert_decimation);
  770. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  771. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  772. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  773. }
  774. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  775. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  776. /* For pixel extension we need the pre-rotated orientation */
  777. if (inline_rotation) {
  778. pstate->pixel_ext.num_ext_pxls_top[i] =
  779. scale_cfg->src_width[i];
  780. pstate->pixel_ext.num_ext_pxls_left[i] =
  781. scale_cfg->src_height[i];
  782. } else {
  783. pstate->pixel_ext.num_ext_pxls_top[i] =
  784. scale_cfg->src_height[i];
  785. pstate->pixel_ext.num_ext_pxls_left[i] =
  786. scale_cfg->src_width[i];
  787. }
  788. }
  789. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  790. && (src_w == dst_w) && !inline_rotation) ||
  791. pstate->multirect_mode)
  792. return;
  793. SDE_DEBUG_PLANE(psde,
  794. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  795. src_w, src_h, dst_w, dst_h,
  796. chroma_subsmpl_v, chroma_subsmpl_h,
  797. fmt->base.pixel_format);
  798. scale_cfg->dst_width = dst_w;
  799. scale_cfg->dst_height = dst_h;
  800. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  801. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  802. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  803. scale_cfg->lut_flag = 0;
  804. scale_cfg->blend_cfg = 1;
  805. scale_cfg->enable = 1;
  806. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  807. }
  808. /**
  809. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  810. * @psde: Pointer to SDE plane object
  811. * @src: Source size
  812. * @dst: Destination size
  813. * @phase_steps: Pointer to output array for phase steps
  814. * @filter: Pointer to output array for filter type
  815. * @fmt: Pointer to format definition
  816. * @chroma_subsampling: Subsampling amount for chroma channel
  817. *
  818. * Returns: 0 on success
  819. */
  820. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  821. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  822. enum sde_hw_filter *filter, const struct sde_format *fmt,
  823. uint32_t chroma_subsampling)
  824. {
  825. if (!psde || !phase_steps || !filter || !fmt) {
  826. SDE_ERROR(
  827. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  828. !psde, !phase_steps, !filter, !fmt);
  829. return -EINVAL;
  830. }
  831. /* calculate phase steps, leave init phase as zero */
  832. phase_steps[SDE_SSPP_COMP_0] =
  833. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  834. phase_steps[SDE_SSPP_COMP_1_2] =
  835. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  836. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  837. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  838. /* calculate scaler config, if necessary */
  839. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  840. filter[SDE_SSPP_COMP_3] =
  841. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  842. SDE_SCALE_FILTER_PCMN;
  843. if (SDE_FORMAT_IS_YUV(fmt)) {
  844. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  845. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  846. } else {
  847. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  848. filter[SDE_SSPP_COMP_1_2] =
  849. SDE_SCALE_FILTER_NEAREST;
  850. }
  851. } else {
  852. /* disable scaler */
  853. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  854. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  855. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  856. }
  857. return 0;
  858. }
  859. /**
  860. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  861. * @psde: Pointer to SDE plane object
  862. * @src: Source size
  863. * @dst: Destination size
  864. * @decimated_src: Source size after decimation, if any
  865. * @phase_steps: Pointer to output array for phase steps
  866. * @out_src: Output array for pixel extension values
  867. * @out_edge1: Output array for pixel extension first edge
  868. * @out_edge2: Output array for pixel extension second edge
  869. * @filter: Pointer to array for filter type
  870. * @fmt: Pointer to format definition
  871. * @chroma_subsampling: Subsampling amount for chroma channel
  872. * @post_compare: Whether to chroma subsampled source size for comparisions
  873. */
  874. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  875. uint32_t src, uint32_t dst, uint32_t decimated_src,
  876. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  877. int *out_edge2, enum sde_hw_filter *filter,
  878. const struct sde_format *fmt, uint32_t chroma_subsampling,
  879. bool post_compare)
  880. {
  881. int64_t edge1, edge2, caf;
  882. uint32_t src_work;
  883. int i, tmp;
  884. if (psde && phase_steps && out_src && out_edge1 &&
  885. out_edge2 && filter && fmt) {
  886. /* handle CAF for YUV formats */
  887. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  888. caf = PHASE_STEP_UNIT_SCALE;
  889. else
  890. caf = 0;
  891. for (i = 0; i < SDE_MAX_PLANES; i++) {
  892. src_work = decimated_src;
  893. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  894. src_work /= chroma_subsampling;
  895. if (post_compare)
  896. src = src_work;
  897. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  898. /* unity */
  899. edge1 = 0;
  900. edge2 = 0;
  901. } else if (dst >= src) {
  902. /* upscale */
  903. edge1 = (1 << PHASE_RESIDUAL);
  904. edge1 -= caf;
  905. edge2 = (1 << PHASE_RESIDUAL);
  906. edge2 += (dst - 1) * *(phase_steps + i);
  907. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  908. edge2 += caf;
  909. edge2 = -(edge2);
  910. } else {
  911. /* downscale */
  912. edge1 = 0;
  913. edge2 = (dst - 1) * *(phase_steps + i);
  914. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  915. edge2 += *(phase_steps + i);
  916. edge2 = -(edge2);
  917. }
  918. /* only enable CAF for luma plane */
  919. caf = 0;
  920. /* populate output arrays */
  921. *(out_src + i) = src_work;
  922. /* edge updates taken from __pxl_extn_helper */
  923. if (edge1 >= 0) {
  924. tmp = (uint32_t)edge1;
  925. tmp >>= PHASE_STEP_SHIFT;
  926. *(out_edge1 + i) = -tmp;
  927. } else {
  928. tmp = (uint32_t)(-edge1);
  929. *(out_edge1 + i) =
  930. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  931. PHASE_STEP_SHIFT;
  932. }
  933. if (edge2 >= 0) {
  934. tmp = (uint32_t)edge2;
  935. tmp >>= PHASE_STEP_SHIFT;
  936. *(out_edge2 + i) = -tmp;
  937. } else {
  938. tmp = (uint32_t)(-edge2);
  939. *(out_edge2 + i) =
  940. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  941. PHASE_STEP_SHIFT;
  942. }
  943. }
  944. }
  945. }
  946. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  947. {
  948. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  949. {
  950. /* S15.16 format */
  951. 0x00012A00, 0x00000000, 0x00019880,
  952. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  953. 0x00012A00, 0x00020480, 0x00000000,
  954. },
  955. /* signed bias */
  956. { 0xfff0, 0xff80, 0xff80,},
  957. { 0x0, 0x0, 0x0,},
  958. /* unsigned clamp */
  959. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  960. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  961. };
  962. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  963. {
  964. /* S15.16 format */
  965. 0x00012A00, 0x00000000, 0x00019880,
  966. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  967. 0x00012A00, 0x00020480, 0x00000000,
  968. },
  969. /* signed bias */
  970. { 0xffc0, 0xfe00, 0xfe00,},
  971. { 0x0, 0x0, 0x0,},
  972. /* unsigned clamp */
  973. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  974. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  975. };
  976. if (!psde) {
  977. SDE_ERROR("invalid plane\n");
  978. return;
  979. }
  980. /* revert to kernel default if override not available */
  981. if (psde->csc_usr_ptr)
  982. psde->csc_ptr = psde->csc_usr_ptr;
  983. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  984. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  985. else
  986. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  987. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  988. psde->csc_ptr->csc_mv[0],
  989. psde->csc_ptr->csc_mv[1],
  990. psde->csc_ptr->csc_mv[2]);
  991. }
  992. static void sde_color_process_plane_setup(struct drm_plane *plane)
  993. {
  994. struct sde_plane *psde;
  995. struct sde_plane_state *pstate;
  996. uint32_t hue, saturation, value, contrast;
  997. struct drm_msm_memcol *memcol = NULL;
  998. struct drm_msm_3d_gamut *vig_gamut = NULL;
  999. struct drm_msm_igc_lut *igc = NULL;
  1000. struct drm_msm_pgc_lut *gc = NULL;
  1001. size_t memcol_sz = 0, size = 0;
  1002. struct sde_hw_cp_cfg hw_cfg = {};
  1003. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1004. psde = to_sde_plane(plane);
  1005. pstate = to_sde_plane_state(plane->state);
  1006. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1007. if (psde->pipe_hw->ops.setup_pa_hue)
  1008. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1009. saturation = (uint32_t) sde_plane_get_property(pstate,
  1010. PLANE_PROP_SATURATION_ADJUST);
  1011. if (psde->pipe_hw->ops.setup_pa_sat)
  1012. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1013. value = (uint32_t) sde_plane_get_property(pstate,
  1014. PLANE_PROP_VALUE_ADJUST);
  1015. if (psde->pipe_hw->ops.setup_pa_val)
  1016. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1017. contrast = (uint32_t) sde_plane_get_property(pstate,
  1018. PLANE_PROP_CONTRAST_ADJUST);
  1019. if (psde->pipe_hw->ops.setup_pa_cont)
  1020. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1021. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1022. /* Skin memory color setup */
  1023. memcol = msm_property_get_blob(&psde->property_info,
  1024. &pstate->property_state,
  1025. &memcol_sz,
  1026. PLANE_PROP_SKIN_COLOR);
  1027. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1028. MEMCOLOR_SKIN, memcol);
  1029. /* Sky memory color setup */
  1030. memcol = msm_property_get_blob(&psde->property_info,
  1031. &pstate->property_state,
  1032. &memcol_sz,
  1033. PLANE_PROP_SKY_COLOR);
  1034. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1035. MEMCOLOR_SKY, memcol);
  1036. /* Foliage memory color setup */
  1037. memcol = msm_property_get_blob(&psde->property_info,
  1038. &pstate->property_state,
  1039. &memcol_sz,
  1040. PLANE_PROP_FOLIAGE_COLOR);
  1041. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1042. MEMCOLOR_FOLIAGE, memcol);
  1043. }
  1044. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1045. psde->pipe_hw->ops.setup_vig_gamut) {
  1046. vig_gamut = msm_property_get_blob(&psde->property_info,
  1047. &pstate->property_state,
  1048. &size,
  1049. PLANE_PROP_VIG_GAMUT);
  1050. hw_cfg.last_feature = 0;
  1051. hw_cfg.ctl = ctl;
  1052. hw_cfg.len = sizeof(struct drm_msm_3d_gamut);
  1053. hw_cfg.payload = vig_gamut;
  1054. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1055. }
  1056. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1057. psde->pipe_hw->ops.setup_vig_igc) {
  1058. igc = msm_property_get_blob(&psde->property_info,
  1059. &pstate->property_state,
  1060. &size,
  1061. PLANE_PROP_VIG_IGC);
  1062. hw_cfg.last_feature = 0;
  1063. hw_cfg.ctl = ctl;
  1064. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1065. hw_cfg.payload = igc;
  1066. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1067. }
  1068. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1069. psde->pipe_hw->ops.setup_dma_igc) {
  1070. igc = msm_property_get_blob(&psde->property_info,
  1071. &pstate->property_state,
  1072. &size,
  1073. PLANE_PROP_DMA_IGC);
  1074. hw_cfg.last_feature = 0;
  1075. hw_cfg.ctl = ctl;
  1076. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1077. hw_cfg.payload = igc;
  1078. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1079. pstate->multirect_index);
  1080. }
  1081. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1082. psde->pipe_hw->ops.setup_dma_gc) {
  1083. gc = msm_property_get_blob(&psde->property_info,
  1084. &pstate->property_state,
  1085. &size,
  1086. PLANE_PROP_DMA_GC);
  1087. hw_cfg.last_feature = 0;
  1088. hw_cfg.ctl = ctl;
  1089. hw_cfg.len = sizeof(struct drm_msm_pgc_lut);
  1090. hw_cfg.payload = gc;
  1091. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1092. pstate->multirect_index);
  1093. }
  1094. }
  1095. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1096. struct sde_plane_state *pstate,
  1097. const struct sde_format *fmt, bool color_fill)
  1098. {
  1099. struct sde_hw_pixel_ext *pe;
  1100. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1101. const struct drm_format_info *info = NULL;
  1102. if (!psde || !fmt || !pstate) {
  1103. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1104. !psde, !fmt, !pstate);
  1105. return;
  1106. }
  1107. info = drm_format_info(fmt->base.pixel_format);
  1108. pe = &pstate->pixel_ext;
  1109. psde->pipe_cfg.horz_decimation =
  1110. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1111. psde->pipe_cfg.vert_decimation =
  1112. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1113. /* don't chroma subsample if decimating */
  1114. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1115. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1116. /* update scaler */
  1117. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1118. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1119. int rc = -EINVAL;
  1120. if (!color_fill && !psde->debugfs_default_scale)
  1121. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1122. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1123. _sde_plane_setup_scaler3_lut(psde, pstate);
  1124. if (rc || pstate->scaler_check_state !=
  1125. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1126. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1127. pstate->scaler_check_state,
  1128. psde->debugfs_default_scale, rc,
  1129. psde->pipe_cfg.src_rect.w,
  1130. psde->pipe_cfg.src_rect.h,
  1131. psde->pipe_cfg.dst_rect.w,
  1132. psde->pipe_cfg.dst_rect.h,
  1133. pstate->multirect_mode);
  1134. /* calculate default config for QSEED3 */
  1135. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1136. chroma_subsmpl_h, chroma_subsmpl_v);
  1137. }
  1138. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1139. color_fill || psde->debugfs_default_scale) {
  1140. uint32_t deci_dim, i;
  1141. /* calculate default configuration for QSEED2 */
  1142. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1143. SDE_DEBUG_PLANE(psde, "default config\n");
  1144. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1145. psde->pipe_cfg.horz_decimation);
  1146. _sde_plane_setup_scaler2(psde,
  1147. deci_dim,
  1148. psde->pipe_cfg.dst_rect.w,
  1149. pe->phase_step_x,
  1150. pe->horz_filter, fmt, chroma_subsmpl_h);
  1151. if (SDE_FORMAT_IS_YUV(fmt))
  1152. deci_dim &= ~0x1;
  1153. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1154. psde->pipe_cfg.dst_rect.w, deci_dim,
  1155. pe->phase_step_x,
  1156. pe->roi_w,
  1157. pe->num_ext_pxls_left,
  1158. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1159. chroma_subsmpl_h, 0);
  1160. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1161. psde->pipe_cfg.vert_decimation);
  1162. _sde_plane_setup_scaler2(psde,
  1163. deci_dim,
  1164. psde->pipe_cfg.dst_rect.h,
  1165. pe->phase_step_y,
  1166. pe->vert_filter, fmt, chroma_subsmpl_v);
  1167. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1168. psde->pipe_cfg.dst_rect.h, deci_dim,
  1169. pe->phase_step_y,
  1170. pe->roi_h,
  1171. pe->num_ext_pxls_top,
  1172. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1173. chroma_subsmpl_v, 1);
  1174. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1175. if (pe->num_ext_pxls_left[i] >= 0)
  1176. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1177. else
  1178. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1179. if (pe->num_ext_pxls_right[i] >= 0)
  1180. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1181. else
  1182. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1183. if (pe->num_ext_pxls_top[i] >= 0)
  1184. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1185. else
  1186. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1187. if (pe->num_ext_pxls_btm[i] >= 0)
  1188. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1189. else
  1190. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1191. }
  1192. }
  1193. if (psde->pipe_hw->ops.setup_pre_downscale)
  1194. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1195. &pstate->pre_down);
  1196. }
  1197. /**
  1198. * _sde_plane_color_fill - enables color fill on plane
  1199. * @psde: Pointer to SDE plane object
  1200. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1201. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1202. * Returns: 0 on success
  1203. */
  1204. static int _sde_plane_color_fill(struct sde_plane *psde,
  1205. uint32_t color, uint32_t alpha)
  1206. {
  1207. const struct sde_format *fmt;
  1208. const struct drm_plane *plane;
  1209. struct sde_plane_state *pstate;
  1210. bool blend_enable = true;
  1211. if (!psde || !psde->base.state) {
  1212. SDE_ERROR("invalid plane\n");
  1213. return -EINVAL;
  1214. }
  1215. if (!psde->pipe_hw) {
  1216. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1217. return -EINVAL;
  1218. }
  1219. plane = &psde->base;
  1220. pstate = to_sde_plane_state(plane->state);
  1221. SDE_DEBUG_PLANE(psde, "\n");
  1222. /*
  1223. * select fill format to match user property expectation,
  1224. * h/w only supports RGB variants
  1225. */
  1226. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1227. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1228. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1229. /* update sspp */
  1230. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1231. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1232. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1233. pstate->multirect_index);
  1234. /* override scaler/decimation if solid fill */
  1235. psde->pipe_cfg.src_rect.x = 0;
  1236. psde->pipe_cfg.src_rect.y = 0;
  1237. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1238. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1239. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1240. if (psde->pipe_hw->ops.setup_format)
  1241. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1242. fmt, blend_enable,
  1243. SDE_SSPP_SOLID_FILL,
  1244. pstate->multirect_index);
  1245. if (psde->pipe_hw->ops.setup_rects)
  1246. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1247. &psde->pipe_cfg,
  1248. pstate->multirect_index);
  1249. if (psde->pipe_hw->ops.setup_pe)
  1250. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1251. &pstate->pixel_ext);
  1252. if (psde->pipe_hw->ops.setup_scaler &&
  1253. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1254. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1255. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1256. &psde->pipe_cfg, &pstate->pixel_ext,
  1257. &pstate->scaler3_cfg);
  1258. }
  1259. }
  1260. return 0;
  1261. }
  1262. /**
  1263. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1264. * @plane: Pointer to drm plane
  1265. * @state: Pointer to drm plane state to be validated
  1266. * return: 0 if success; error code otherwise
  1267. */
  1268. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1269. struct drm_plane_state *state)
  1270. {
  1271. struct sde_plane *psde;
  1272. struct sde_plane_state *pstate, *old_pstate;
  1273. int ret = 0;
  1274. u32 rotation;
  1275. if (!plane || !state) {
  1276. SDE_ERROR("invalid plane/state\n");
  1277. return -EINVAL;
  1278. }
  1279. psde = to_sde_plane(plane);
  1280. pstate = to_sde_plane_state(state);
  1281. old_pstate = to_sde_plane_state(plane->state);
  1282. /* check inline rotation and simplify the transform */
  1283. rotation = drm_rotation_simplify(
  1284. state->rotation,
  1285. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1286. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1287. if ((rotation & DRM_MODE_ROTATE_180) ||
  1288. (rotation & DRM_MODE_ROTATE_270)) {
  1289. SDE_ERROR_PLANE(psde,
  1290. "invalid rotation transform must be simplified 0x%x\n",
  1291. rotation);
  1292. ret = -EINVAL;
  1293. goto exit;
  1294. }
  1295. if (rotation & DRM_MODE_ROTATE_90) {
  1296. struct msm_drm_private *priv = plane->dev->dev_private;
  1297. struct sde_kms *sde_kms;
  1298. const struct msm_format *msm_fmt;
  1299. const struct sde_format *fmt;
  1300. struct sde_rect src;
  1301. bool q16_data = true;
  1302. POPULATE_RECT(&src, state->src_x, state->src_y,
  1303. state->src_w, state->src_h, q16_data);
  1304. /*
  1305. * DRM framework expects rotation flag in counter-clockwise
  1306. * direction and the HW expects in clockwise direction.
  1307. * Flip the flags to match with HW.
  1308. */
  1309. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1310. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1311. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1312. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1313. !psde->pipe_sblk->in_rot_maxheight ||
  1314. !psde->pipe_sblk->in_rot_format_list ||
  1315. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1316. SDE_ERROR_PLANE(psde,
  1317. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1318. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1319. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1320. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1321. !psde->pipe_sblk->in_rot_format_list,
  1322. !psde->pipe_sblk->in_rot_maxheight,
  1323. psde->features);
  1324. ret = -EINVAL;
  1325. goto exit;
  1326. }
  1327. /* check for valid height */
  1328. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1329. SDE_ERROR_PLANE(psde,
  1330. "invalid height for inline rot:%d max:%d\n",
  1331. src.h, psde->pipe_sblk->in_rot_maxheight);
  1332. ret = -EINVAL;
  1333. goto exit;
  1334. }
  1335. if (!sde_plane_enabled(state))
  1336. goto exit;
  1337. /* check for valid formats supported by inline rot */
  1338. sde_kms = to_sde_kms(priv->kms);
  1339. msm_fmt = msm_framebuffer_format(state->fb);
  1340. fmt = to_sde_format(msm_fmt);
  1341. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1342. psde->pipe_sblk->in_rot_format_list);
  1343. }
  1344. exit:
  1345. pstate->rotation = rotation;
  1346. return ret;
  1347. }
  1348. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1349. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1350. {
  1351. struct sde_plane *psde;
  1352. struct msm_drm_private *priv;
  1353. struct sde_vbif_set_xin_halt_params halt_params;
  1354. if (!plane || !plane->dev) {
  1355. SDE_ERROR("invalid arguments\n");
  1356. return false;
  1357. }
  1358. psde = to_sde_plane(plane);
  1359. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1360. SDE_ERROR("invalid pipe reference\n");
  1361. return false;
  1362. }
  1363. priv = plane->dev->dev_private;
  1364. if (!priv || !priv->kms) {
  1365. SDE_ERROR("invalid KMS reference\n");
  1366. return false;
  1367. }
  1368. memset(&halt_params, 0, sizeof(halt_params));
  1369. halt_params.vbif_idx = VBIF_RT;
  1370. halt_params.xin_id = xin_id;
  1371. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1372. halt_params.forced_on = halt_forced_clk;
  1373. halt_params.enable = enable;
  1374. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1375. }
  1376. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1377. {
  1378. struct sde_plane *psde;
  1379. if (!plane) {
  1380. SDE_ERROR("invalid plane\n");
  1381. return;
  1382. }
  1383. psde = to_sde_plane(plane);
  1384. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1385. SDE_ERROR("invalid pipe reference\n");
  1386. return;
  1387. }
  1388. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1389. psde->xin_halt_forced_clk =
  1390. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1391. psde->xin_halt_forced_clk, enable);
  1392. }
  1393. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1394. struct drm_crtc *crtc)
  1395. {
  1396. struct sde_plane *psde;
  1397. if (!plane || !crtc) {
  1398. SDE_ERROR("invalid plane/crtc\n");
  1399. return;
  1400. }
  1401. psde = to_sde_plane(plane);
  1402. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1403. return;
  1404. /* do all VBIF programming for the sec-ui allowed SSPP */
  1405. _sde_plane_set_qos_remap(plane);
  1406. _sde_plane_set_ot_limit(plane, crtc);
  1407. }
  1408. /**
  1409. * sde_plane_rot_install_properties - install plane rotator properties
  1410. * @plane: Pointer to drm plane
  1411. * @catalog: Pointer to mdss configuration
  1412. * return: none
  1413. */
  1414. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1415. struct sde_mdss_cfg *catalog)
  1416. {
  1417. struct sde_plane *psde = to_sde_plane(plane);
  1418. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1419. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1420. int ret = 0;
  1421. if (!plane || !psde) {
  1422. SDE_ERROR("invalid plane\n");
  1423. return;
  1424. } else if (!catalog) {
  1425. SDE_ERROR("invalid catalog\n");
  1426. return;
  1427. }
  1428. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1429. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1430. ret = drm_plane_create_rotation_property(plane,
  1431. DRM_MODE_ROTATE_0, supported_rotations);
  1432. if (ret) {
  1433. DRM_ERROR("create rotation property failed: %d\n", ret);
  1434. return;
  1435. }
  1436. }
  1437. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1438. {
  1439. struct sde_plane_state *pstate;
  1440. if (!drm_state)
  1441. return;
  1442. pstate = to_sde_plane_state(drm_state);
  1443. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1444. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1445. }
  1446. /**
  1447. * multi_rect validate API allows to validate only R0 and R1 RECT
  1448. * passing for each plane. Client of this API must not pass multiple
  1449. * plane which are not sharing same XIN client. Such calls will fail
  1450. * even though kernel client is passing valid multirect configuration.
  1451. */
  1452. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1453. {
  1454. struct sde_plane_state *pstate[R_MAX];
  1455. const struct drm_plane_state *drm_state[R_MAX];
  1456. struct sde_rect src[R_MAX], dst[R_MAX];
  1457. struct sde_plane *sde_plane[R_MAX];
  1458. const struct sde_format *fmt[R_MAX];
  1459. int xin_id[R_MAX];
  1460. bool q16_data = true;
  1461. int i, j, buffer_lines, width_threshold[R_MAX];
  1462. unsigned int max_tile_height = 1;
  1463. bool parallel_fetch_qualified = true;
  1464. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1465. const struct msm_format *msm_fmt;
  1466. bool const_alpha_enable = true;
  1467. for (i = 0; i < R_MAX; i++) {
  1468. drm_state[i] = i ? plane->r1 : plane->r0;
  1469. if (!drm_state[i]) {
  1470. SDE_ERROR("drm plane state is NULL\n");
  1471. return -EINVAL;
  1472. }
  1473. pstate[i] = to_sde_plane_state(drm_state[i]);
  1474. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1475. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1476. for (j = 0; j < i; j++) {
  1477. if (xin_id[i] != xin_id[j]) {
  1478. SDE_ERROR_PLANE(sde_plane[i],
  1479. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1480. j, xin_id[j], i, xin_id[i]);
  1481. return -EINVAL;
  1482. }
  1483. }
  1484. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1485. if (!msm_fmt) {
  1486. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1487. return -EINVAL;
  1488. }
  1489. fmt[i] = to_sde_format(msm_fmt);
  1490. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1491. (fmt[i]->tile_height > max_tile_height))
  1492. max_tile_height = fmt[i]->tile_height;
  1493. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1494. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1495. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1496. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1497. drm_state[i]->crtc_h, !q16_data);
  1498. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1499. SDE_ERROR_PLANE(sde_plane[i],
  1500. "scaling is not supported in multirect mode\n");
  1501. return -EINVAL;
  1502. }
  1503. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1504. SDE_ERROR_PLANE(sde_plane[i],
  1505. "inline rotation is not supported in mulirect mode\n");
  1506. return -EINVAL;
  1507. }
  1508. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1509. SDE_ERROR_PLANE(sde_plane[i],
  1510. "Unsupported format for multirect mode\n");
  1511. return -EINVAL;
  1512. }
  1513. /**
  1514. * SSPP PD_MEM is split half - one for each RECT.
  1515. * Tiled formats need 5 lines of buffering while fetching
  1516. * whereas linear formats need only 2 lines.
  1517. * So we cannot support more than half of the supported SSPP
  1518. * width for tiled formats.
  1519. */
  1520. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1521. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1522. width_threshold[i] /= 2;
  1523. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1524. parallel_fetch_qualified = false;
  1525. if (sde_plane[i]->is_virtual)
  1526. mode = sde_plane_get_property(pstate[i],
  1527. PLANE_PROP_MULTIRECT_MODE);
  1528. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1529. const_alpha_enable = false;
  1530. }
  1531. buffer_lines = 2 * max_tile_height;
  1532. /**
  1533. * fallback to driver mode selection logic if client is using
  1534. * multirect plane without setting property.
  1535. *
  1536. * validate multirect mode configuration based on rectangle
  1537. */
  1538. switch (mode) {
  1539. case SDE_SSPP_MULTIRECT_NONE:
  1540. if (parallel_fetch_qualified)
  1541. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1542. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1543. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1544. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1545. else
  1546. SDE_ERROR(
  1547. "planes(%d - %d) multirect mode selection fail\n",
  1548. drm_state[R0]->plane->base.id,
  1549. drm_state[R1]->plane->base.id);
  1550. break;
  1551. case SDE_SSPP_MULTIRECT_PARALLEL:
  1552. if (!parallel_fetch_qualified) {
  1553. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1554. drm_state[R0]->plane->base.id,
  1555. width_threshold[R0], src[R0].w);
  1556. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1557. drm_state[R1]->plane->base.id,
  1558. width_threshold[R1], src[R1].w);
  1559. SDE_ERROR("parallel fetch not qualified\n");
  1560. mode = SDE_SSPP_MULTIRECT_NONE;
  1561. }
  1562. break;
  1563. case SDE_SSPP_MULTIRECT_TIME_MX:
  1564. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1565. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1566. SDE_ERROR(
  1567. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1568. buffer_lines, drm_state[R0]->plane->base.id,
  1569. dst[R0].y, dst[R0].h);
  1570. SDE_ERROR(
  1571. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1572. buffer_lines, drm_state[R1]->plane->base.id,
  1573. dst[R1].y, dst[R1].h);
  1574. SDE_ERROR("time multiplexed fetch not qualified\n");
  1575. mode = SDE_SSPP_MULTIRECT_NONE;
  1576. }
  1577. break;
  1578. default:
  1579. SDE_ERROR("bad mode:%d selection\n", mode);
  1580. mode = SDE_SSPP_MULTIRECT_NONE;
  1581. break;
  1582. }
  1583. for (i = 0; i < R_MAX; i++) {
  1584. pstate[i]->multirect_mode = mode;
  1585. pstate[i]->const_alpha_en = const_alpha_enable;
  1586. }
  1587. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1588. return -EINVAL;
  1589. if (sde_plane[R0]->is_virtual) {
  1590. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1591. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1592. } else {
  1593. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1594. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1595. }
  1596. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1597. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1598. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1599. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1600. return 0;
  1601. }
  1602. /**
  1603. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1604. * @plane: Pointer to drm plane structure
  1605. * @ctl: Pointer to hardware control driver
  1606. * @set: set if true else clear
  1607. */
  1608. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1609. bool set)
  1610. {
  1611. if (!plane || !ctl) {
  1612. SDE_ERROR("invalid parameters\n");
  1613. return;
  1614. }
  1615. if (!ctl->ops.update_bitmask_sspp) {
  1616. SDE_ERROR("invalid ops\n");
  1617. return;
  1618. }
  1619. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1620. }
  1621. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1622. struct drm_plane_state *new_state)
  1623. {
  1624. struct drm_framebuffer *fb = new_state->fb;
  1625. struct sde_plane *psde = to_sde_plane(plane);
  1626. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1627. struct sde_hw_fmt_layout layout;
  1628. struct msm_gem_address_space *aspace;
  1629. int ret;
  1630. if (!fb)
  1631. return 0;
  1632. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1633. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1634. if (ret) {
  1635. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1636. return ret;
  1637. }
  1638. /* cache aspace */
  1639. pstate->aspace = aspace;
  1640. /*
  1641. * when transitioning from secure to non-secure,
  1642. * plane->prepare_fb happens before the commit. In such case,
  1643. * defer the prepare_fb and handled it late, during the commit
  1644. * after attaching the domains as part of the transition
  1645. */
  1646. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1647. true : false;
  1648. if (pstate->defer_prepare_fb) {
  1649. SDE_EVT32(DRMID(plane), psde->pipe);
  1650. SDE_DEBUG_PLANE(psde,
  1651. "domain not attached, prepare_fb handled later\n");
  1652. return 0;
  1653. }
  1654. if (pstate->aspace && fb) {
  1655. ret = msm_framebuffer_prepare(fb,
  1656. pstate->aspace);
  1657. if (ret) {
  1658. SDE_ERROR("failed to prepare framebuffer\n");
  1659. return ret;
  1660. }
  1661. }
  1662. /* validate framebuffer layout before commit */
  1663. ret = sde_format_populate_layout(pstate->aspace,
  1664. fb, &layout);
  1665. if (ret) {
  1666. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1667. return ret;
  1668. }
  1669. return 0;
  1670. }
  1671. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1672. struct drm_plane_state *old_state)
  1673. {
  1674. struct sde_plane *psde = to_sde_plane(plane);
  1675. struct sde_plane_state *old_pstate;
  1676. if (!old_state || !old_state->fb || !plane)
  1677. return;
  1678. old_pstate = to_sde_plane_state(old_state);
  1679. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1680. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1681. }
  1682. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1683. struct drm_plane_state *state,
  1684. struct drm_plane_state *old_state)
  1685. {
  1686. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1687. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1688. struct drm_framebuffer *fb, *old_fb;
  1689. /* no need to check it again */
  1690. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1691. return;
  1692. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1693. || psde->is_error) {
  1694. SDE_DEBUG_PLANE(psde,
  1695. "enabling/disabling full modeset required\n");
  1696. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1697. } else if (to_sde_plane_state(old_state)->pending) {
  1698. SDE_DEBUG_PLANE(psde, "still pending\n");
  1699. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1700. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1701. pstate->multirect_mode != old_pstate->multirect_mode) {
  1702. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1703. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1704. } else if (state->src_w != old_state->src_w ||
  1705. state->src_h != old_state->src_h ||
  1706. state->src_x != old_state->src_x ||
  1707. state->src_y != old_state->src_y) {
  1708. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1709. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1710. } else if (state->crtc_w != old_state->crtc_w ||
  1711. state->crtc_h != old_state->crtc_h ||
  1712. state->crtc_x != old_state->crtc_x ||
  1713. state->crtc_y != old_state->crtc_y) {
  1714. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1715. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1716. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1717. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1718. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1719. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1720. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1721. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1722. } else if (pstate->rotation != old_pstate->rotation) {
  1723. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1724. pstate->rotation, old_pstate->rotation);
  1725. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1726. }
  1727. fb = state->fb;
  1728. old_fb = old_state->fb;
  1729. if (!fb || !old_fb) {
  1730. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1731. } else if ((fb->format->format != old_fb->format->format) ||
  1732. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1733. SDE_DEBUG_PLANE(psde, "format change\n");
  1734. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1735. } else {
  1736. uint64_t new_mod = fb->modifier;
  1737. uint64_t old_mod = old_fb->modifier;
  1738. uint32_t *new_pitches = fb->pitches;
  1739. uint32_t *old_pitches = old_fb->pitches;
  1740. uint32_t *new_offset = fb->offsets;
  1741. uint32_t *old_offset = old_fb->offsets;
  1742. int i;
  1743. if (new_mod != old_mod) {
  1744. SDE_DEBUG_PLANE(psde,
  1745. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1746. new_mod, old_mod);
  1747. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1748. SDE_PLANE_DIRTY_RECTS;
  1749. }
  1750. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1751. if (new_pitches[i] != old_pitches[i]) {
  1752. SDE_DEBUG_PLANE(psde,
  1753. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1754. i, old_pitches[i], new_pitches[i]);
  1755. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1756. break;
  1757. }
  1758. }
  1759. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1760. if (new_offset[i] != old_offset[i]) {
  1761. SDE_DEBUG_PLANE(psde,
  1762. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1763. i, old_offset[i], new_offset[i]);
  1764. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1765. SDE_PLANE_DIRTY_RECTS;
  1766. break;
  1767. }
  1768. }
  1769. }
  1770. }
  1771. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1772. unsigned long base_addr, u32 size)
  1773. {
  1774. int ret = -EINVAL;
  1775. u32 addr;
  1776. struct sde_plane *psde = to_sde_plane(plane);
  1777. if (!psde || !base_addr || !size) {
  1778. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1779. return ret;
  1780. }
  1781. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1782. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1783. is_sde_plane_virtual(plane));
  1784. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1785. ret = 0;
  1786. }
  1787. return ret;
  1788. }
  1789. static inline bool _sde_plane_is_pre_downscale_enabled(
  1790. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1791. {
  1792. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1793. }
  1794. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1795. struct sde_plane_state *pstate,
  1796. const struct sde_format *fmt,
  1797. uint32_t img_w, uint32_t img_h,
  1798. uint32_t src_w, uint32_t src_h,
  1799. uint32_t deci_w, uint32_t deci_h)
  1800. {
  1801. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1802. bool pre_down_en;
  1803. int i;
  1804. if (!psde || !pstate || !fmt) {
  1805. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1806. return -EINVAL;
  1807. }
  1808. if (psde->debugfs_default_scale ||
  1809. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1810. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1811. return 0;
  1812. pd_cfg = &pstate->pre_down;
  1813. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1814. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1815. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1816. uint32_t hor_req_pixels, hor_fetch_pixels;
  1817. uint32_t vert_req_pixels, vert_fetch_pixels;
  1818. uint32_t src_w_tmp, src_h_tmp;
  1819. uint32_t scaler_w, scaler_h;
  1820. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1821. bool rot;
  1822. /* re-use color plane 1's config for plane 2 */
  1823. if (i == 2)
  1824. continue;
  1825. if (pre_down_en) {
  1826. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1827. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1828. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1829. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1830. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1831. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1832. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1833. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1834. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1835. i, pre_down_ratio_x, pre_down_ratio_y);
  1836. }
  1837. src_w_tmp = src_w;
  1838. src_h_tmp = src_h;
  1839. /*
  1840. * For chroma plane, width is half for the following sub sampled
  1841. * formats. Except in case of decimation, where hardware avoids
  1842. * 1 line of decimation instead of downsampling.
  1843. */
  1844. if (i == 1) {
  1845. if (!deci_w &&
  1846. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1847. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1848. src_w_tmp >>= 1;
  1849. if (!deci_h &&
  1850. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1851. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1852. src_h_tmp >>= 1;
  1853. }
  1854. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1855. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1856. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1857. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1858. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1859. deci_w);
  1860. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1861. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1862. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1863. deci_h);
  1864. if ((hor_req_pixels != hor_fetch_pixels) ||
  1865. (hor_fetch_pixels > img_w) ||
  1866. (vert_req_pixels != vert_fetch_pixels) ||
  1867. (vert_fetch_pixels > img_h)) {
  1868. SDE_ERROR_PLANE(psde,
  1869. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1870. hor_req_pixels, vert_req_pixels,
  1871. hor_fetch_pixels, vert_fetch_pixels,
  1872. img_w, img_h);
  1873. return -EINVAL;
  1874. }
  1875. /*
  1876. * swap the scaler src width & height for inline-rotation 90
  1877. * comparison with Pixel-Extension, as PE is based on
  1878. * pre-rotation and QSEED is based on post-rotation
  1879. */
  1880. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1881. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1882. : pstate->scaler3_cfg.src_width[i];
  1883. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1884. : pstate->scaler3_cfg.src_height[i];
  1885. /*
  1886. * Alpha plane can only be scaled using bilinear or pixel
  1887. * repeat/drop, src_width and src_height are only specified
  1888. * for Y and UV plane
  1889. */
  1890. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1891. vert_req_pixels / pre_down_ratio_y !=
  1892. scaler_h)) {
  1893. SDE_ERROR_PLANE(psde,
  1894. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1895. i, pstate->pixel_ext.roi_w[i],
  1896. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1897. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1898. return -EINVAL;
  1899. }
  1900. /*
  1901. * SSPP fetch , unpack output and QSEED3 input lines need
  1902. * to match for Y plane
  1903. */
  1904. if (i == 0 &&
  1905. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1906. BIT(SDE_DRM_DEINTERLACE)) &&
  1907. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1908. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1909. SDE_ERROR_PLANE(psde,
  1910. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1911. i, pstate->pixel_ext.roi_w[i],
  1912. pstate->pixel_ext.roi_h[i],
  1913. pstate->scaler3_cfg.src_width[i],
  1914. pstate->scaler3_cfg.src_height[i],
  1915. src_w, src_h);
  1916. return -EINVAL;
  1917. }
  1918. }
  1919. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1920. return 0;
  1921. }
  1922. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1923. {
  1924. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1925. }
  1926. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1927. struct sde_plane_state *pstate, struct sde_rect *dst,
  1928. u32 src_w, u32 src_h)
  1929. {
  1930. int ret = 0;
  1931. u32 min_ratio_numer, min_ratio_denom;
  1932. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1933. bool pd_x;
  1934. bool pd_y;
  1935. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1936. return ret;
  1937. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1938. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1939. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1940. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1941. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  1942. SDE_ERROR_PLANE(psde,
  1943. "hw does not support pre-downscale X: 0x%x\n",
  1944. psde->features);
  1945. ret = -EINVAL;
  1946. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  1947. SDE_ERROR_PLANE(psde,
  1948. "hw does not support pre-downscale Y: 0x%x\n",
  1949. psde->features);
  1950. ret = -EINVAL;
  1951. } else if (!min_ratio_numer || !min_ratio_denom) {
  1952. SDE_ERROR_PLANE(psde,
  1953. "min downscale ratio not set! %u / %u\n",
  1954. min_ratio_numer, min_ratio_denom);
  1955. ret = -EINVAL;
  1956. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  1957. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  1958. min_ratio_denom))) {
  1959. SDE_ERROR_PLANE(psde,
  1960. "failed min downscale-x check %u->%u, %u/%u\n",
  1961. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  1962. ret = -EINVAL;
  1963. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  1964. min_ratio_denom))) {
  1965. SDE_ERROR_PLANE(psde,
  1966. "failed min downscale-y check %u->%u, %u/%u\n",
  1967. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  1968. ret = -EINVAL;
  1969. }
  1970. return ret;
  1971. }
  1972. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  1973. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  1974. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  1975. u32 *max_numer_h, u32 *max_denom_h)
  1976. {
  1977. bool rotated, has_predown, default_scale;
  1978. const struct sde_sspp_sub_blks *sblk;
  1979. struct sde_hw_inline_pre_downscale_cfg *pd;
  1980. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  1981. sblk = psde->pipe_sblk;
  1982. *max_numer_w = sblk->maxdwnscale;
  1983. *max_denom_w = 1;
  1984. *max_numer_h = sblk->maxdwnscale;
  1985. *max_denom_h = 1;
  1986. has_predown = _sde_plane_has_pre_downscale(psde);
  1987. if (has_predown)
  1988. pd = &pstate->pre_down;
  1989. default_scale = psde->debugfs_default_scale ||
  1990. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1991. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  1992. /**
  1993. * Inline rotation has different max vertical downscaling limits since
  1994. * the source-width becomes the scaler's pre-downscaled source-height.
  1995. **/
  1996. if (rotated) {
  1997. if (rt_client && has_predown) {
  1998. if (default_scale)
  1999. pd->pre_downscale_x_0 = (src_h >
  2000. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2001. *max_numer_h = pd->pre_downscale_x_0 ?
  2002. sblk->in_rot_maxdwnscale_rt_num :
  2003. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2004. *max_denom_h = pd->pre_downscale_x_0 ?
  2005. sblk->in_rot_maxdwnscale_rt_denom :
  2006. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2007. } else if (rt_client) {
  2008. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2009. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2010. } else {
  2011. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2012. }
  2013. }
  2014. }
  2015. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2016. struct sde_plane *psde, const struct sde_format *fmt,
  2017. struct sde_plane_state *pstate, struct sde_rect *src,
  2018. struct sde_rect *dst, u32 width, u32 height)
  2019. {
  2020. int ret = 0;
  2021. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2022. uint32_t scaler_src_w, scaler_src_h;
  2023. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2024. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2025. uint32_t max_upscale, max_linewidth;
  2026. bool inline_rotation, rt_client;
  2027. struct drm_crtc *crtc;
  2028. struct drm_crtc_state *new_cstate;
  2029. const struct sde_sspp_sub_blks *sblk;
  2030. if (!state || !state->state || !state->crtc) {
  2031. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2032. return -EINVAL;
  2033. }
  2034. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2035. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2036. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2037. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2038. /* with inline rotator, the source of the scaler is post-rotated */
  2039. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2040. if (inline_rotation) {
  2041. scaler_src_w = src_deci_h;
  2042. scaler_src_h = src_deci_w;
  2043. } else {
  2044. scaler_src_w = src_deci_w;
  2045. scaler_src_h = src_deci_h;
  2046. }
  2047. sblk = psde->pipe_sblk;
  2048. max_upscale = sblk->maxupscale;
  2049. if (inline_rotation)
  2050. max_linewidth = sblk->in_rot_maxheight;
  2051. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2052. max_linewidth = sblk->scaling_linewidth;
  2053. else
  2054. max_linewidth = sblk->maxlinewidth;
  2055. crtc = state->crtc;
  2056. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2057. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2058. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2059. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2060. &max_downscale_num_h, &max_downscale_denom_h);
  2061. /* decimation validation */
  2062. if ((deci_w || deci_h)
  2063. && ((deci_w > sblk->maxhdeciexp)
  2064. || (deci_h > sblk->maxvdeciexp))) {
  2065. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2066. ret = -EINVAL;
  2067. } else if ((deci_w || deci_h)
  2068. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2069. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2070. ret = -EINVAL;
  2071. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2072. ((src->w != dst->w) || (src->h != dst->h))) {
  2073. SDE_ERROR_PLANE(psde,
  2074. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2075. src->w, src->h, dst->w, dst->h);
  2076. ret = -EINVAL;
  2077. /* check scaler source width */
  2078. } else if (scaler_src_w > max_linewidth) {
  2079. SDE_ERROR_PLANE(psde,
  2080. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2081. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2082. ret = -E2BIG;
  2083. /* check max scaler capability */
  2084. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2085. ((scaler_src_h * max_upscale) < dst->h) ||
  2086. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2087. < scaler_src_w) ||
  2088. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2089. < scaler_src_h)) {
  2090. SDE_ERROR_PLANE(psde,
  2091. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2092. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2093. inline_rotation, max_downscale_num_w,
  2094. max_downscale_denom_w, max_downscale_num_h,
  2095. max_downscale_denom_h);
  2096. ret = -E2BIG;
  2097. /* check inline pre-downscale support */
  2098. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2099. pstate, dst, src_deci_w, src_deci_h)) {
  2100. ret = -EINVAL;
  2101. /* QSEED validation */
  2102. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2103. width, height, src->w, src->h,
  2104. deci_w, deci_h)) {
  2105. ret = -EINVAL;
  2106. }
  2107. return ret;
  2108. }
  2109. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2110. struct sde_plane_state *pstate, struct sde_rect *src,
  2111. const struct sde_format *fmt, int ret)
  2112. {
  2113. /* check excl rect configs */
  2114. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2115. struct sde_rect intersect;
  2116. /*
  2117. * Check exclusion rect against src rect.
  2118. * it must intersect with source rect.
  2119. */
  2120. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2121. if (intersect.w != pstate->excl_rect.w ||
  2122. intersect.h != pstate->excl_rect.h ||
  2123. SDE_FORMAT_IS_YUV(fmt)) {
  2124. SDE_ERROR_PLANE(psde,
  2125. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2126. pstate->excl_rect.x, pstate->excl_rect.y,
  2127. pstate->excl_rect.w, pstate->excl_rect.h,
  2128. src->x, src->y, src->w, src->h,
  2129. (char *)&fmt->base.pixel_format);
  2130. ret = -EINVAL;
  2131. }
  2132. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2133. pstate->excl_rect.x, pstate->excl_rect.y,
  2134. pstate->excl_rect.w, pstate->excl_rect.h);
  2135. }
  2136. return ret;
  2137. }
  2138. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2139. struct drm_plane_state *state)
  2140. {
  2141. struct sde_kms *sde_kms;
  2142. struct sde_splash_display *splash_display;
  2143. int i, j;
  2144. sde_kms = _sde_plane_get_kms(&psde->base);
  2145. if (!sde_kms || !state->crtc)
  2146. return 0;
  2147. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2148. splash_display = &sde_kms->splash_data.splash_display[i];
  2149. if (splash_display && splash_display->cont_splash_enabled &&
  2150. splash_display->encoder &&
  2151. state->crtc != splash_display->encoder->crtc) {
  2152. for (j = 0; j < MAX_DATA_PATH_PER_DSIPLAY; j++) {
  2153. if (splash_display->pipes[j].sspp ==
  2154. psde->pipe) {
  2155. SDE_ERROR_PLANE(psde,
  2156. "pipe:%d used in cont-splash on crtc:%d\n",
  2157. psde->pipe,
  2158. splash_display->encoder->crtc->base.id);
  2159. return -EINVAL;
  2160. }
  2161. }
  2162. }
  2163. }
  2164. return 0;
  2165. }
  2166. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2167. const struct sde_format *fmt,
  2168. struct sde_rect src, struct sde_rect dst,
  2169. u32 width, u32 height)
  2170. {
  2171. int ret = 0;
  2172. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2173. if (SDE_FORMAT_IS_YUV(fmt) &&
  2174. (!(psde->features & SDE_SSPP_SCALER) ||
  2175. !(psde->features & (BIT(SDE_SSPP_CSC)
  2176. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2177. SDE_ERROR_PLANE(psde,
  2178. "plane doesn't have scaler/csc for yuv\n");
  2179. ret = -EINVAL;
  2180. /* check src bounds */
  2181. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2182. src.w < min_src_size || src.h < min_src_size ||
  2183. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2184. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2185. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2186. src.x, src.y, src.w, src.h);
  2187. ret = -E2BIG;
  2188. /* valid yuv image */
  2189. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2190. (src.w & 0x1) || (src.h & 0x1))) {
  2191. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2192. src.x, src.y, src.w, src.h);
  2193. ret = -EINVAL;
  2194. /* min dst support */
  2195. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2196. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2197. dst.x, dst.y, dst.w, dst.h);
  2198. ret = -EINVAL;
  2199. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2200. !psde->catalog->ubwc_version) {
  2201. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2202. ret = -EINVAL;
  2203. }
  2204. return ret;
  2205. }
  2206. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2207. struct drm_plane_state *state)
  2208. {
  2209. int ret = 0;
  2210. struct sde_plane *psde;
  2211. struct sde_plane_state *pstate;
  2212. const struct msm_format *msm_fmt;
  2213. const struct sde_format *fmt;
  2214. struct sde_rect src, dst;
  2215. bool q16_data = true;
  2216. struct drm_framebuffer *fb;
  2217. u32 width;
  2218. u32 height;
  2219. psde = to_sde_plane(plane);
  2220. pstate = to_sde_plane_state(state);
  2221. if (!psde->pipe_sblk) {
  2222. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2223. return -EINVAL;
  2224. }
  2225. /* src values are in Q16 fixed point, convert to integer */
  2226. POPULATE_RECT(&src, state->src_x, state->src_y,
  2227. state->src_w, state->src_h, q16_data);
  2228. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2229. state->crtc_h, !q16_data);
  2230. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2231. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2232. if (!sde_plane_enabled(state))
  2233. goto modeset_update;
  2234. fb = state->fb;
  2235. width = fb ? state->fb->width : 0x0;
  2236. height = fb ? state->fb->height : 0x0;
  2237. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2238. plane->base.id,
  2239. pstate->rotation,
  2240. width, height,
  2241. fb ? (char *) &state->fb->format->format : 0x0,
  2242. fb ? state->fb->modifier : 0x0);
  2243. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2244. state->src_w >> 16, state->src_h >> 16,
  2245. state->src_x >> 16, state->src_y >> 16,
  2246. state->crtc_w, state->crtc_h,
  2247. state->crtc_x, state->crtc_y);
  2248. msm_fmt = msm_framebuffer_format(fb);
  2249. fmt = to_sde_format(msm_fmt);
  2250. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2251. height);
  2252. if (ret)
  2253. return ret;
  2254. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2255. &src, &dst, width, height);
  2256. if (ret)
  2257. return ret;
  2258. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2259. &src, fmt, ret);
  2260. if (ret)
  2261. return ret;
  2262. ret = _sde_plane_validate_shared_crtc(psde, state);
  2263. if (ret)
  2264. return ret;
  2265. pstate->const_alpha_en = fmt->alpha_enable &&
  2266. (SDE_DRM_BLEND_OP_OPAQUE !=
  2267. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2268. (pstate->stage != SDE_STAGE_0);
  2269. modeset_update:
  2270. if (!ret)
  2271. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2272. state, plane->state);
  2273. return ret;
  2274. }
  2275. static int sde_plane_atomic_check(struct drm_plane *plane,
  2276. struct drm_plane_state *state)
  2277. {
  2278. int ret = 0;
  2279. struct sde_plane *psde;
  2280. struct sde_plane_state *pstate;
  2281. if (!plane || !state) {
  2282. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2283. !plane, !state);
  2284. ret = -EINVAL;
  2285. goto exit;
  2286. }
  2287. psde = to_sde_plane(plane);
  2288. pstate = to_sde_plane_state(state);
  2289. SDE_DEBUG_PLANE(psde, "\n");
  2290. ret = sde_plane_rot_atomic_check(plane, state);
  2291. if (ret)
  2292. goto exit;
  2293. ret = sde_plane_sspp_atomic_check(plane, state);
  2294. exit:
  2295. return ret;
  2296. }
  2297. void sde_plane_flush(struct drm_plane *plane)
  2298. {
  2299. struct sde_plane *psde;
  2300. struct sde_plane_state *pstate;
  2301. if (!plane || !plane->state) {
  2302. SDE_ERROR("invalid plane\n");
  2303. return;
  2304. }
  2305. psde = to_sde_plane(plane);
  2306. pstate = to_sde_plane_state(plane->state);
  2307. /*
  2308. * These updates have to be done immediately before the plane flush
  2309. * timing, and may not be moved to the atomic_update/mode_set functions.
  2310. */
  2311. if (psde->is_error)
  2312. /* force white frame with 100% alpha pipe output on error */
  2313. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2314. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2315. /* force 100% alpha */
  2316. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2317. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2318. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2319. /* flag h/w flush complete */
  2320. if (plane->state)
  2321. pstate->pending = false;
  2322. }
  2323. /**
  2324. * sde_plane_set_error: enable/disable error condition
  2325. * @plane: pointer to drm_plane structure
  2326. */
  2327. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2328. {
  2329. struct sde_plane *psde;
  2330. if (!plane)
  2331. return;
  2332. psde = to_sde_plane(plane);
  2333. psde->is_error = error;
  2334. }
  2335. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2336. struct sde_plane_state *pstate, bool is_tp10)
  2337. {
  2338. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2339. if (!psde->pipe_hw->ops.setup_sys_cache ||
  2340. !(psde->perf_features & BIT(SDE_PERF_SSPP_SYS_CACHE)))
  2341. return;
  2342. SDE_DEBUG("features:0x%x rotation:0x%x\n",
  2343. psde->features, pstate->rotation);
  2344. pstate->sc_cfg.rd_en = false;
  2345. pstate->sc_cfg.rd_scid = 0x0;
  2346. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2347. SSPP_SYS_CACHE_SCID;
  2348. pstate->sc_cfg.type = SDE_SYS_CACHE_NONE;
  2349. if (pstate->rotation & DRM_MODE_ROTATE_90) {
  2350. if (is_tp10 && sc_cfg[SDE_SYS_CACHE_ROT].has_sys_cache) {
  2351. pstate->sc_cfg.rd_en = true;
  2352. pstate->sc_cfg.rd_scid =
  2353. sc_cfg[SDE_SYS_CACHE_ROT].llcc_scid;
  2354. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2355. SSPP_SYS_CACHE_SCID;
  2356. pstate->sc_cfg.type = SDE_SYS_CACHE_ROT;
  2357. }
  2358. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_WRITE &&
  2359. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2360. pstate->sc_cfg.rd_en = true;
  2361. pstate->sc_cfg.rd_scid =
  2362. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2363. pstate->sc_cfg.rd_noallocate = false;
  2364. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2365. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2366. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2367. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_READ &&
  2368. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2369. pstate->sc_cfg.rd_en = true;
  2370. pstate->sc_cfg.rd_scid =
  2371. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2372. pstate->sc_cfg.rd_noallocate = true;
  2373. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2374. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2375. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2376. }
  2377. SDE_EVT32(DRMID(&psde->base), pstate->sc_cfg.rd_scid,
  2378. pstate->sc_cfg.rd_en, pstate->sc_cfg.rd_noallocate);
  2379. psde->pipe_hw->ops.setup_sys_cache(
  2380. psde->pipe_hw, &pstate->sc_cfg);
  2381. }
  2382. void sde_plane_static_img_control(struct drm_plane *plane,
  2383. enum sde_crtc_cache_state state)
  2384. {
  2385. struct sde_plane *psde;
  2386. struct sde_plane_state *pstate;
  2387. if (!plane || !plane->state) {
  2388. SDE_ERROR("invalid plane\n");
  2389. return;
  2390. }
  2391. psde = to_sde_plane(plane);
  2392. pstate = to_sde_plane_state(plane->state);
  2393. pstate->static_cache_state = state;
  2394. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2395. _sde_plane_sspp_setup_sys_cache(psde, pstate, false);
  2396. }
  2397. static void _sde_plane_map_prop_to_dirty_bits(void)
  2398. {
  2399. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2400. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2401. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2402. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2403. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2404. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2405. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2406. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2407. plane_prop_array[PLANE_PROP_ZPOS] =
  2408. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2409. SDE_PLANE_DIRTY_RECTS;
  2410. plane_prop_array[PLANE_PROP_CSC_V1] =
  2411. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2412. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2413. SDE_PLANE_DIRTY_FORMAT;
  2414. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2415. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2416. SDE_PLANE_DIRTY_ALL;
  2417. /* no special action required */
  2418. plane_prop_array[PLANE_PROP_INFO] =
  2419. plane_prop_array[PLANE_PROP_ALPHA] =
  2420. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2421. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2422. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2423. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2424. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2425. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2426. SDE_PLANE_DIRTY_PERF;
  2427. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2428. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2429. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2430. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2431. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2432. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2433. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2434. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2435. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2436. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2437. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2438. SDE_PLANE_DIRTY_ALL;
  2439. }
  2440. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2441. struct sde_rect *src, struct sde_rect *dst)
  2442. {
  2443. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2444. u32 downscale = (src->h * 1000)/dst->h;
  2445. return (downscale > max_downscale) ? false : true;
  2446. }
  2447. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2448. struct sde_plane *psde, struct sde_plane_state *pstate,
  2449. struct sde_rect *src, struct sde_rect *dst)
  2450. {
  2451. struct sde_hw_pipe_uidle_cfg cfg;
  2452. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2453. u32 fal1_threshold_max = 15;
  2454. u32 line_time = sde_get_linetime(&crtc->mode,
  2455. sde_crtc->src_bpp, sde_crtc->target_bpp); /* nS */
  2456. u32 fal1_target_idle_time_ns =
  2457. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2458. u32 fal10_target_idle_time_ns =
  2459. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2460. u32 fal10_threshold =
  2461. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2462. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2463. fal1_target_idle_time_ns) {
  2464. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2465. cfg.fal10_threshold = fal10_threshold;
  2466. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2467. cfg.fal1_threshold = min(1 +
  2468. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2469. fal1_threshold_max);
  2470. cfg.fal_allowed_threshold = fal10_threshold +
  2471. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2472. } else {
  2473. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2474. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2475. fal1_target_idle_time_ns);
  2476. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2477. }
  2478. SDE_DEBUG_PLANE(psde,
  2479. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",
  2480. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2481. cfg.fal1_threshold, cfg.fal_allowed_threshold);
  2482. SDE_DEBUG_PLANE(psde,
  2483. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2484. line_time, fal1_target_idle_time_ns,
  2485. fal10_target_idle_time_ns,
  2486. psde->catalog->uidle_cfg.max_dwnscale);
  2487. SDE_EVT32_VERBOSE(cfg.enable,
  2488. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2489. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2490. psde->catalog->uidle_cfg.max_dwnscale);
  2491. psde->pipe_hw->ops.setup_uidle(
  2492. psde->pipe_hw, &cfg,
  2493. pstate->multirect_index);
  2494. }
  2495. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2496. struct sde_plane_state *pstate)
  2497. {
  2498. bool enable = false;
  2499. int mode = sde_plane_get_property(pstate,
  2500. PLANE_PROP_FB_TRANSLATION_MODE);
  2501. if ((mode == SDE_DRM_FB_SEC) ||
  2502. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2503. enable = true;
  2504. /* update secure session flag */
  2505. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2506. pstate->multirect_index,
  2507. enable);
  2508. }
  2509. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2510. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2511. {
  2512. const struct sde_format *fmt;
  2513. const struct msm_format *msm_fmt;
  2514. struct sde_plane *psde;
  2515. struct drm_plane_state *state;
  2516. struct sde_plane_state *pstate;
  2517. struct sde_rect src, dst;
  2518. const struct sde_rect *crtc_roi;
  2519. bool q16_data = true;
  2520. int idx;
  2521. psde = to_sde_plane(plane);
  2522. state = plane->state;
  2523. pstate = to_sde_plane_state(state);
  2524. msm_fmt = msm_framebuffer_format(fb);
  2525. if (!msm_fmt) {
  2526. SDE_ERROR("crtc%d plane%d: null format\n",
  2527. DRMID(crtc), DRMID(plane));
  2528. return;
  2529. }
  2530. fmt = to_sde_format(msm_fmt);
  2531. POPULATE_RECT(&src, state->src_x, state->src_y,
  2532. state->src_w, state->src_h, q16_data);
  2533. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2534. state->crtc_w, state->crtc_h, !q16_data);
  2535. SDE_DEBUG_PLANE(psde,
  2536. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2537. fb->base.id, src.x, src.y, src.w, src.h,
  2538. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2539. (char *)&fmt->base.pixel_format,
  2540. SDE_FORMAT_IS_UBWC(fmt));
  2541. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2542. BIT(SDE_DRM_DEINTERLACE)) {
  2543. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2544. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2545. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2546. src.h /= 2;
  2547. src.y = DIV_ROUND_UP(src.y, 2);
  2548. src.y &= ~0x1;
  2549. }
  2550. /*
  2551. * adjust layer mixer position of the sspp in the presence
  2552. * of a partial update to the active lm origin
  2553. */
  2554. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2555. dst.x -= crtc_roi->x;
  2556. dst.y -= crtc_roi->y;
  2557. /* check for UIDLE */
  2558. if (psde->pipe_hw->ops.setup_uidle)
  2559. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2560. psde->pipe_cfg.src_rect = src;
  2561. psde->pipe_cfg.dst_rect = dst;
  2562. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2563. /* check for color fill */
  2564. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2565. PLANE_PROP_COLOR_FILL);
  2566. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2567. /* skip remaining processing on color fill */
  2568. pstate->dirty = 0x0;
  2569. } else if (psde->pipe_hw->ops.setup_rects) {
  2570. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2571. &psde->pipe_cfg,
  2572. pstate->multirect_index);
  2573. }
  2574. if (psde->pipe_hw->ops.setup_pe &&
  2575. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2576. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2577. &pstate->pixel_ext);
  2578. /**
  2579. * when programmed in multirect mode, scalar block will be
  2580. * bypassed. Still we need to update alpha and bitwidth
  2581. * ONLY for RECT0
  2582. */
  2583. if (psde->pipe_hw->ops.setup_scaler &&
  2584. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2585. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2586. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2587. &psde->pipe_cfg, &pstate->pixel_ext,
  2588. &pstate->scaler3_cfg);
  2589. }
  2590. /* update excl rect */
  2591. if (psde->pipe_hw->ops.setup_excl_rect)
  2592. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2593. &pstate->excl_rect,
  2594. pstate->multirect_index);
  2595. /* enable multirect config of corresponding rect */
  2596. if (psde->pipe_hw->ops.update_multirect)
  2597. psde->pipe_hw->ops.update_multirect(
  2598. psde->pipe_hw,
  2599. true,
  2600. pstate->multirect_index,
  2601. pstate->multirect_mode);
  2602. }
  2603. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2604. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2605. {
  2606. uint32_t src_flags = 0;
  2607. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2608. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2609. src_flags |= SDE_SSPP_FLIP_LR;
  2610. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2611. src_flags |= SDE_SSPP_FLIP_UD;
  2612. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2613. src_flags |= SDE_SSPP_ROT_90;
  2614. /* update format */
  2615. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2616. pstate->const_alpha_en, src_flags,
  2617. pstate->multirect_index);
  2618. if (psde->pipe_hw->ops.setup_cdp) {
  2619. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2620. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2621. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2622. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2623. cdp_cfg->ubwc_meta_enable =
  2624. SDE_FORMAT_IS_UBWC(fmt);
  2625. cdp_cfg->tile_amortize_enable =
  2626. SDE_FORMAT_IS_UBWC(fmt) ||
  2627. SDE_FORMAT_IS_TILE(fmt);
  2628. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2629. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2630. pstate->multirect_index);
  2631. }
  2632. _sde_plane_sspp_setup_sys_cache(psde, pstate,
  2633. sde_format_is_tp10_ubwc(fmt));
  2634. /* update csc */
  2635. if (SDE_FORMAT_IS_YUV(fmt))
  2636. _sde_plane_setup_csc(psde);
  2637. else
  2638. psde->csc_ptr = 0;
  2639. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2640. uint32_t pma_mode = 0;
  2641. if (fmt->alpha_enable)
  2642. pma_mode = (uint32_t) sde_plane_get_property(
  2643. pstate, PLANE_PROP_INVERSE_PMA);
  2644. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2645. pstate->multirect_index, pma_mode);
  2646. }
  2647. if (psde->pipe_hw->ops.setup_dgm_csc)
  2648. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2649. pstate->multirect_index, psde->csc_usr_ptr);
  2650. }
  2651. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2652. {
  2653. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2654. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2655. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2656. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2657. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2658. &psde->sharp_cfg);
  2659. }
  2660. static void _sde_plane_update_properties(struct drm_plane *plane,
  2661. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2662. {
  2663. uint32_t nplanes;
  2664. const struct msm_format *msm_fmt;
  2665. const struct sde_format *fmt;
  2666. struct sde_plane *psde;
  2667. struct drm_plane_state *state;
  2668. struct sde_plane_state *pstate;
  2669. psde = to_sde_plane(plane);
  2670. state = plane->state;
  2671. pstate = to_sde_plane_state(state);
  2672. if (!pstate) {
  2673. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2674. return;
  2675. }
  2676. msm_fmt = msm_framebuffer_format(fb);
  2677. if (!msm_fmt) {
  2678. SDE_ERROR("crtc%d plane%d: null format\n",
  2679. DRMID(crtc), DRMID(plane));
  2680. return;
  2681. }
  2682. fmt = to_sde_format(msm_fmt);
  2683. nplanes = fmt->num_planes;
  2684. /* update secure session flag */
  2685. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2686. _sde_plane_update_secure_session(psde, pstate);
  2687. /* update roi config */
  2688. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2689. _sde_plane_update_roi_config(plane, crtc, fb);
  2690. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2691. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2692. psde->pipe_hw->ops.setup_format)
  2693. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2694. sde_color_process_plane_setup(plane);
  2695. /* update sharpening */
  2696. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2697. psde->pipe_hw->ops.setup_sharpening)
  2698. _sde_plane_update_sharpening(psde);
  2699. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2700. SDE_PLANE_DIRTY_FORMAT))
  2701. _sde_plane_set_qos_lut(plane, crtc, fb);
  2702. if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  2703. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2704. _sde_plane_set_ot_limit(plane, crtc);
  2705. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2706. _sde_plane_set_ts_prefill(plane, pstate);
  2707. }
  2708. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2709. _sde_plane_set_qos_remap(plane);
  2710. /* clear dirty */
  2711. pstate->dirty = 0x0;
  2712. }
  2713. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2714. struct drm_plane_state *old_state)
  2715. {
  2716. struct sde_plane *psde;
  2717. struct drm_plane_state *state;
  2718. struct sde_plane_state *pstate;
  2719. struct sde_plane_state *old_pstate;
  2720. struct drm_crtc *crtc;
  2721. struct drm_framebuffer *fb;
  2722. int idx;
  2723. int dirty_prop_flag;
  2724. bool is_rt;
  2725. if (!plane) {
  2726. SDE_ERROR("invalid plane\n");
  2727. return -EINVAL;
  2728. } else if (!plane->state) {
  2729. SDE_ERROR("invalid plane state\n");
  2730. return -EINVAL;
  2731. } else if (!old_state) {
  2732. SDE_ERROR("invalid old state\n");
  2733. return -EINVAL;
  2734. }
  2735. psde = to_sde_plane(plane);
  2736. state = plane->state;
  2737. pstate = to_sde_plane_state(state);
  2738. old_pstate = to_sde_plane_state(old_state);
  2739. crtc = state->crtc;
  2740. fb = state->fb;
  2741. if (!crtc || !fb) {
  2742. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2743. !crtc, !fb);
  2744. return -EINVAL;
  2745. }
  2746. SDE_DEBUG(
  2747. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2748. plane->base.id,
  2749. state->fb->width, state->fb->height,
  2750. (char *) &state->fb->format->format,
  2751. state->fb->modifier,
  2752. state->src_w >> 16, state->src_h >> 16,
  2753. state->src_x >> 16, state->src_y >> 16,
  2754. pstate->rotation,
  2755. state->crtc_w, state->crtc_h,
  2756. state->crtc_x, state->crtc_y);
  2757. /* force reprogramming of all the parameters, if the flag is set */
  2758. if (psde->revalidate) {
  2759. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2760. plane->base.id);
  2761. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2762. psde->revalidate = false;
  2763. }
  2764. /* determine what needs to be refreshed */
  2765. mutex_lock(&psde->property_info.property_lock);
  2766. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2767. &pstate->property_state)) >= 0) {
  2768. dirty_prop_flag = plane_prop_array[idx];
  2769. pstate->dirty |= dirty_prop_flag;
  2770. }
  2771. mutex_unlock(&psde->property_info.property_lock);
  2772. /**
  2773. * since plane_atomic_check is invoked before crtc_atomic_check
  2774. * in the commit sequence, all the parameters for updating the
  2775. * plane dirty flag will not be available during
  2776. * plane_atomic_check as some features params are updated
  2777. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2778. * before sspp update.
  2779. */
  2780. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2781. old_state);
  2782. /* re-program the output rects always if partial update roi changed */
  2783. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2784. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2785. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2786. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2787. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2788. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2789. if (is_rt != psde->is_rt_pipe) {
  2790. psde->is_rt_pipe = is_rt;
  2791. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2792. }
  2793. /* early out if nothing dirty */
  2794. if (!pstate->dirty)
  2795. return 0;
  2796. pstate->pending = true;
  2797. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2798. _sde_plane_update_properties(plane, crtc, fb);
  2799. return 0;
  2800. }
  2801. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2802. struct drm_plane_state *old_state)
  2803. {
  2804. struct sde_plane *psde;
  2805. struct drm_plane_state *state;
  2806. struct sde_plane_state *pstate;
  2807. u32 multirect_index = SDE_SSPP_RECT_0;
  2808. if (!plane) {
  2809. SDE_ERROR("invalid plane\n");
  2810. return;
  2811. } else if (!plane->state) {
  2812. SDE_ERROR("invalid plane state\n");
  2813. return;
  2814. } else if (!old_state) {
  2815. SDE_ERROR("invalid old state\n");
  2816. return;
  2817. }
  2818. psde = to_sde_plane(plane);
  2819. state = plane->state;
  2820. pstate = to_sde_plane_state(state);
  2821. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2822. pstate->multirect_mode);
  2823. pstate->pending = true;
  2824. if (is_sde_plane_virtual(plane))
  2825. multirect_index = SDE_SSPP_RECT_1;
  2826. /* disable multirect config of corresponding rect */
  2827. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2828. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2829. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2830. }
  2831. static void sde_plane_atomic_update(struct drm_plane *plane,
  2832. struct drm_plane_state *old_state)
  2833. {
  2834. struct sde_plane *psde;
  2835. struct drm_plane_state *state;
  2836. if (!plane) {
  2837. SDE_ERROR("invalid plane\n");
  2838. return;
  2839. } else if (!plane->state) {
  2840. SDE_ERROR("invalid plane state\n");
  2841. return;
  2842. }
  2843. psde = to_sde_plane(plane);
  2844. psde->is_error = false;
  2845. state = plane->state;
  2846. SDE_DEBUG_PLANE(psde, "\n");
  2847. if (!sde_plane_enabled(state)) {
  2848. _sde_plane_atomic_disable(plane, old_state);
  2849. } else {
  2850. int ret;
  2851. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2852. /* atomic_check should have ensured that this doesn't fail */
  2853. WARN_ON(ret < 0);
  2854. }
  2855. }
  2856. void sde_plane_restore(struct drm_plane *plane)
  2857. {
  2858. struct sde_plane *psde;
  2859. if (!plane || !plane->state) {
  2860. SDE_ERROR("invalid plane\n");
  2861. return;
  2862. }
  2863. psde = to_sde_plane(plane);
  2864. /*
  2865. * Revalidate is only true here if idle PC occurred and
  2866. * there is no plane state update in current commit cycle.
  2867. */
  2868. if (!psde->revalidate)
  2869. return;
  2870. SDE_DEBUG_PLANE(psde, "\n");
  2871. /* last plane state is same as current state */
  2872. sde_plane_atomic_update(plane, plane->state);
  2873. }
  2874. bool sde_plane_is_cache_required(struct drm_plane *plane,
  2875. enum sde_sys_cache_type type)
  2876. {
  2877. struct sde_plane_state *pstate;
  2878. if (!plane || !plane->state) {
  2879. SDE_ERROR("invalid plane\n");
  2880. return false;
  2881. }
  2882. pstate = to_sde_plane_state(plane->state);
  2883. /* check if llcc is required for the plane */
  2884. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  2885. return true;
  2886. else
  2887. return false;
  2888. }
  2889. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  2890. {
  2891. char feature_name[256];
  2892. if (psde->pipe_sblk->maxhdeciexp) {
  2893. msm_property_install_range(&psde->property_info,
  2894. "h_decimate", 0x0, 0,
  2895. psde->pipe_sblk->maxhdeciexp, 0,
  2896. PLANE_PROP_H_DECIMATE);
  2897. }
  2898. if (psde->pipe_sblk->maxvdeciexp) {
  2899. msm_property_install_range(&psde->property_info,
  2900. "v_decimate", 0x0, 0,
  2901. psde->pipe_sblk->maxvdeciexp, 0,
  2902. PLANE_PROP_V_DECIMATE);
  2903. }
  2904. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  2905. msm_property_install_range(
  2906. &psde->property_info, "scaler_v2",
  2907. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2908. msm_property_install_blob(&psde->property_info,
  2909. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  2910. msm_property_install_blob(&psde->property_info,
  2911. "lut_cir", 0,
  2912. PLANE_PROP_SCALER_LUT_CIR);
  2913. msm_property_install_blob(&psde->property_info,
  2914. "lut_sep", 0,
  2915. PLANE_PROP_SCALER_LUT_SEP);
  2916. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  2917. msm_property_install_range(
  2918. &psde->property_info, "scaler_v2",
  2919. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2920. msm_property_install_blob(&psde->property_info,
  2921. "lut_sep", 0,
  2922. PLANE_PROP_SCALER_LUT_SEP);
  2923. } else if (psde->features & SDE_SSPP_SCALER) {
  2924. msm_property_install_range(
  2925. &psde->property_info, "scaler_v1", 0x0,
  2926. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  2927. }
  2928. if (psde->features & BIT(SDE_SSPP_CSC) ||
  2929. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  2930. msm_property_install_volatile_range(
  2931. &psde->property_info, "csc_v1", 0x0,
  2932. 0, ~0, 0, PLANE_PROP_CSC_V1);
  2933. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  2934. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2935. "SDE_SSPP_HUE_V",
  2936. psde->pipe_sblk->hsic_blk.version >> 16);
  2937. msm_property_install_range(&psde->property_info,
  2938. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2939. PLANE_PROP_HUE_ADJUST);
  2940. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2941. "SDE_SSPP_SATURATION_V",
  2942. psde->pipe_sblk->hsic_blk.version >> 16);
  2943. msm_property_install_range(&psde->property_info,
  2944. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2945. PLANE_PROP_SATURATION_ADJUST);
  2946. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2947. "SDE_SSPP_VALUE_V",
  2948. psde->pipe_sblk->hsic_blk.version >> 16);
  2949. msm_property_install_range(&psde->property_info,
  2950. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2951. PLANE_PROP_VALUE_ADJUST);
  2952. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2953. "SDE_SSPP_CONTRAST_V",
  2954. psde->pipe_sblk->hsic_blk.version >> 16);
  2955. msm_property_install_range(&psde->property_info,
  2956. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2957. PLANE_PROP_CONTRAST_ADJUST);
  2958. }
  2959. }
  2960. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  2961. struct sde_kms_info *info)
  2962. {
  2963. char feature_name[256];
  2964. bool is_master = !psde->is_virtual;
  2965. if ((is_master &&
  2966. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  2967. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  2968. msm_property_install_range(&psde->property_info,
  2969. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  2970. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  2971. }
  2972. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  2973. msm_property_install_volatile_range(
  2974. &psde->property_info, "csc_dma_v1", 0x0,
  2975. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  2976. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  2977. }
  2978. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  2979. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2980. "SDE_SSPP_SKIN_COLOR_V",
  2981. psde->pipe_sblk->memcolor_blk.version >> 16);
  2982. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2983. PLANE_PROP_SKIN_COLOR);
  2984. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2985. "SDE_SSPP_SKY_COLOR_V",
  2986. psde->pipe_sblk->memcolor_blk.version >> 16);
  2987. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2988. PLANE_PROP_SKY_COLOR);
  2989. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2990. "SDE_SSPP_FOLIAGE_COLOR_V",
  2991. psde->pipe_sblk->memcolor_blk.version >> 16);
  2992. msm_property_install_blob(&psde->property_info, feature_name, 0,
  2993. PLANE_PROP_FOLIAGE_COLOR);
  2994. }
  2995. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  2996. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2997. "SDE_VIG_3D_LUT_GAMUT_V",
  2998. psde->pipe_sblk->gamut_blk.version >> 16);
  2999. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3000. PLANE_PROP_VIG_GAMUT);
  3001. }
  3002. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3003. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3004. "SDE_VIG_1D_LUT_IGC_V",
  3005. psde->pipe_sblk->igc_blk[0].version >> 16);
  3006. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3007. PLANE_PROP_VIG_IGC);
  3008. }
  3009. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3010. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3011. "SDE_DGM_1D_LUT_IGC_V",
  3012. psde->pipe_sblk->igc_blk[0].version >> 16);
  3013. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3014. PLANE_PROP_DMA_IGC);
  3015. }
  3016. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3017. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3018. "SDE_DGM_1D_LUT_GC_V",
  3019. psde->pipe_sblk->gc_blk[0].version >> 16);
  3020. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3021. PLANE_PROP_DMA_GC);
  3022. }
  3023. }
  3024. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3025. u32 master_plane_id, struct sde_kms_info *info,
  3026. struct sde_mdss_cfg *catalog)
  3027. {
  3028. bool is_master = !psde->is_virtual;
  3029. const struct sde_format_extended *format_list;
  3030. u32 index;
  3031. if (is_master) {
  3032. format_list = psde->pipe_sblk->format_list;
  3033. } else {
  3034. format_list = psde->pipe_sblk->virt_format_list;
  3035. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3036. master_plane_id);
  3037. }
  3038. if (format_list) {
  3039. sde_kms_info_start(info, "pixel_formats");
  3040. while (format_list->fourcc_format) {
  3041. sde_kms_info_append_format(info,
  3042. format_list->fourcc_format,
  3043. format_list->modifier);
  3044. ++format_list;
  3045. }
  3046. sde_kms_info_stop(info);
  3047. }
  3048. if (psde->pipe_hw && catalog->qseed_hw_version)
  3049. sde_kms_info_add_keyint(info, "scaler_step_ver",
  3050. catalog->qseed_hw_version);
  3051. sde_kms_info_add_keyint(info, "max_linewidth",
  3052. psde->pipe_sblk->maxlinewidth);
  3053. sde_kms_info_add_keyint(info, "max_upscale",
  3054. psde->pipe_sblk->maxupscale);
  3055. sde_kms_info_add_keyint(info, "max_downscale",
  3056. psde->pipe_sblk->maxdwnscale);
  3057. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3058. psde->pipe_sblk->maxhdeciexp);
  3059. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3060. psde->pipe_sblk->maxvdeciexp);
  3061. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3062. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3063. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3064. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3065. index = (master_plane_id == 0) ? 0 : 1;
  3066. if (catalog->has_demura &&
  3067. catalog->demura_supported[psde->pipe][index] != ~0x0) {
  3068. sde_kms_info_add_keyint(info, "demura_block", index);
  3069. sde_kms_info_add_keyint(info, "demura_pipe_id",
  3070. psde->pipe - SSPP_DMA0);
  3071. }
  3072. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3073. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3074. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3075. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3076. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3077. const struct sde_format_extended *inline_rot_fmt_list;
  3078. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3079. catalog->true_inline_rot_rev);
  3080. sde_kms_info_add_keyint(info,
  3081. "true_inline_dwnscale_rt",
  3082. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3083. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3084. sde_kms_info_add_keyint(info,
  3085. "true_inline_dwnscale_rt_numerator",
  3086. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3087. sde_kms_info_add_keyint(info,
  3088. "true_inline_dwnscale_rt_denominator",
  3089. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3090. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3091. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3092. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3093. psde->pipe_sblk->in_rot_maxheight);
  3094. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3095. if (inline_rot_fmt_list) {
  3096. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3097. while (inline_rot_fmt_list->fourcc_format) {
  3098. sde_kms_info_append_format(info,
  3099. inline_rot_fmt_list->fourcc_format,
  3100. inline_rot_fmt_list->modifier);
  3101. ++inline_rot_fmt_list;
  3102. }
  3103. sde_kms_info_stop(info);
  3104. }
  3105. }
  3106. }
  3107. /* helper to install properties which are common to planes and crtcs */
  3108. static void _sde_plane_install_properties(struct drm_plane *plane,
  3109. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3110. {
  3111. static const struct drm_prop_enum_list e_blend_op[] = {
  3112. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3113. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3114. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3115. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3116. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3117. };
  3118. static const struct drm_prop_enum_list e_src_config[] = {
  3119. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3120. };
  3121. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3122. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3123. {SDE_DRM_FB_SEC, "sec"},
  3124. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3125. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3126. };
  3127. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3128. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3129. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3130. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3131. };
  3132. struct sde_kms_info *info;
  3133. struct sde_plane *psde = to_sde_plane(plane);
  3134. bool is_master;
  3135. int zpos_max = 255;
  3136. int zpos_def = 0;
  3137. if (!plane || !psde) {
  3138. SDE_ERROR("invalid plane\n");
  3139. return;
  3140. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3141. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3142. !psde->pipe_hw, !psde->pipe_sblk);
  3143. return;
  3144. } else if (!catalog) {
  3145. SDE_ERROR("invalid catalog\n");
  3146. return;
  3147. }
  3148. psde->catalog = catalog;
  3149. is_master = !psde->is_virtual;
  3150. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3151. if (!info) {
  3152. SDE_ERROR("failed to allocate info memory\n");
  3153. return;
  3154. }
  3155. if (sde_is_custom_client()) {
  3156. if (catalog->mixer_count &&
  3157. catalog->mixer[0].sblk->maxblendstages) {
  3158. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3159. if (catalog->has_base_layer &&
  3160. (zpos_max > SDE_STAGE_MAX - 1))
  3161. zpos_max = SDE_STAGE_MAX - 1;
  3162. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3163. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3164. }
  3165. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3166. /* reserve zpos == 0 for primary planes */
  3167. zpos_def = drm_plane_index(plane) + 1;
  3168. }
  3169. msm_property_install_range(&psde->property_info, "zpos",
  3170. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3171. msm_property_install_range(&psde->property_info, "alpha",
  3172. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3173. /* linux default file descriptor range on each process */
  3174. msm_property_install_range(&psde->property_info, "input_fence",
  3175. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3176. if (is_master)
  3177. _sde_plane_install_master_only_properties(psde);
  3178. else
  3179. msm_property_install_enum(&psde->property_info,
  3180. "multirect_mode", 0x0, 0, e_multirect_mode,
  3181. ARRAY_SIZE(e_multirect_mode), 0,
  3182. PLANE_PROP_MULTIRECT_MODE);
  3183. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3184. msm_property_install_volatile_range(&psde->property_info,
  3185. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3186. sde_plane_rot_install_properties(plane, catalog);
  3187. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3188. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3189. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3190. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3191. PLANE_PROP_SRC_CONFIG);
  3192. if (psde->pipe_hw->ops.setup_solidfill)
  3193. msm_property_install_range(&psde->property_info, "color_fill",
  3194. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3195. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3196. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3197. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3198. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3199. msm_property_install_blob(&psde->property_info, "capabilities",
  3200. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3201. sde_kms_info_reset(info);
  3202. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3203. catalog);
  3204. _sde_plane_install_colorproc_properties(psde, info);
  3205. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3206. info->data, SDE_KMS_INFO_DATALEN(info),
  3207. PLANE_PROP_INFO);
  3208. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3209. 0x0, 0, e_fb_translation_mode,
  3210. ARRAY_SIZE(e_fb_translation_mode), 0,
  3211. PLANE_PROP_FB_TRANSLATION_MODE);
  3212. kfree(info);
  3213. }
  3214. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3215. void __user *usr_ptr)
  3216. {
  3217. struct sde_drm_csc_v1 csc_v1;
  3218. int i;
  3219. if (!psde) {
  3220. SDE_ERROR("invalid plane\n");
  3221. return;
  3222. }
  3223. psde->csc_usr_ptr = NULL;
  3224. if (!usr_ptr) {
  3225. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3226. return;
  3227. }
  3228. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3229. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3230. return;
  3231. }
  3232. /* populate from user space */
  3233. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3234. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3235. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3236. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3237. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3238. }
  3239. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3240. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3241. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3242. }
  3243. psde->csc_usr_ptr = &psde->csc_cfg;
  3244. }
  3245. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3246. struct sde_plane_state *pstate, void __user *usr)
  3247. {
  3248. struct sde_drm_scaler_v1 scale_v1;
  3249. struct sde_hw_pixel_ext *pe;
  3250. int i;
  3251. if (!psde || !pstate) {
  3252. SDE_ERROR("invalid argument(s)\n");
  3253. return;
  3254. }
  3255. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3256. if (!usr) {
  3257. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3258. return;
  3259. }
  3260. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3261. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3262. return;
  3263. }
  3264. /* force property to be dirty, even if the pointer didn't change */
  3265. msm_property_set_dirty(&psde->property_info,
  3266. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3267. /* populate from user space */
  3268. pe = &pstate->pixel_ext;
  3269. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3270. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3271. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3272. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3273. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3274. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3275. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3276. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3277. }
  3278. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3279. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3280. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3281. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3282. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3283. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3284. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3285. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3286. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3287. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3288. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3289. }
  3290. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3291. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3292. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3293. }
  3294. static void _sde_plane_clear_predownscale_settings(
  3295. struct sde_plane_state *pstate)
  3296. {
  3297. pstate->pre_down.pre_downscale_x_0 = 0;
  3298. pstate->pre_down.pre_downscale_x_1 = 0;
  3299. pstate->pre_down.pre_downscale_y_0 = 0;
  3300. pstate->pre_down.pre_downscale_y_1 = 0;
  3301. }
  3302. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3303. struct sde_plane_state *pstate, void __user *usr)
  3304. {
  3305. struct sde_drm_scaler_v2 scale_v2;
  3306. struct sde_hw_pixel_ext *pe;
  3307. int i;
  3308. struct sde_hw_scaler3_cfg *cfg;
  3309. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3310. if (!psde || !pstate) {
  3311. SDE_ERROR("invalid argument(s)\n");
  3312. return;
  3313. }
  3314. cfg = &pstate->scaler3_cfg;
  3315. pd_cfg = &pstate->pre_down;
  3316. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3317. if (!usr) {
  3318. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3319. cfg->enable = 0;
  3320. _sde_plane_clear_predownscale_settings(pstate);
  3321. goto end;
  3322. }
  3323. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3324. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3325. return;
  3326. }
  3327. /* detach/ignore user data if 'disabled' */
  3328. if (!scale_v2.enable) {
  3329. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3330. cfg->enable = 0;
  3331. _sde_plane_clear_predownscale_settings(pstate);
  3332. goto end;
  3333. }
  3334. /* populate from user space */
  3335. sde_set_scaler_v2(cfg, &scale_v2);
  3336. if (_sde_plane_has_pre_downscale(psde)) {
  3337. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3338. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3339. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3340. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3341. }
  3342. pe = &pstate->pixel_ext;
  3343. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3344. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3345. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3346. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3347. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3348. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3349. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3350. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3351. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3352. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3353. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3354. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3355. }
  3356. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3357. end:
  3358. /* force property to be dirty, even if the pointer didn't change */
  3359. msm_property_set_dirty(&psde->property_info,
  3360. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3361. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3362. cfg->src_width[0], cfg->src_height[0],
  3363. cfg->dst_width, cfg->dst_height);
  3364. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3365. }
  3366. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3367. struct sde_plane_state *pstate, void __user *usr_ptr)
  3368. {
  3369. struct drm_clip_rect excl_rect_v1;
  3370. if (!psde || !pstate) {
  3371. SDE_ERROR("invalid argument(s)\n");
  3372. return;
  3373. }
  3374. if (!usr_ptr) {
  3375. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3376. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3377. return;
  3378. }
  3379. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3380. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3381. return;
  3382. }
  3383. /* populate from user space */
  3384. pstate->excl_rect.x = excl_rect_v1.x1;
  3385. pstate->excl_rect.y = excl_rect_v1.y1;
  3386. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3387. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3388. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3389. pstate->excl_rect.x, pstate->excl_rect.y,
  3390. pstate->excl_rect.w, pstate->excl_rect.h);
  3391. }
  3392. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3393. struct drm_plane_state *state, struct drm_property *property,
  3394. uint64_t val)
  3395. {
  3396. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3397. struct sde_plane_state *pstate;
  3398. int idx, ret = -EINVAL;
  3399. SDE_DEBUG_PLANE(psde, "\n");
  3400. if (!plane) {
  3401. SDE_ERROR("invalid plane\n");
  3402. } else if (!state) {
  3403. SDE_ERROR_PLANE(psde, "invalid state\n");
  3404. } else {
  3405. pstate = to_sde_plane_state(state);
  3406. ret = msm_property_atomic_set(&psde->property_info,
  3407. &pstate->property_state, property, val);
  3408. if (!ret) {
  3409. idx = msm_property_index(&psde->property_info,
  3410. property);
  3411. switch (idx) {
  3412. case PLANE_PROP_INPUT_FENCE:
  3413. _sde_plane_set_input_fence(psde, pstate, val);
  3414. break;
  3415. case PLANE_PROP_CSC_V1:
  3416. case PLANE_PROP_CSC_DMA_V1:
  3417. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3418. break;
  3419. case PLANE_PROP_SCALER_V1:
  3420. _sde_plane_set_scaler_v1(psde, pstate,
  3421. (void *)(uintptr_t)val);
  3422. break;
  3423. case PLANE_PROP_SCALER_V2:
  3424. _sde_plane_set_scaler_v2(psde, pstate,
  3425. (void *)(uintptr_t)val);
  3426. break;
  3427. case PLANE_PROP_EXCL_RECT_V1:
  3428. _sde_plane_set_excl_rect_v1(psde, pstate,
  3429. (void *)(uintptr_t)val);
  3430. break;
  3431. default:
  3432. /* nothing to do */
  3433. break;
  3434. }
  3435. }
  3436. }
  3437. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3438. property->name, property->base.id, val, ret);
  3439. return ret;
  3440. }
  3441. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3442. const struct drm_plane_state *state,
  3443. struct drm_property *property, uint64_t *val)
  3444. {
  3445. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3446. struct sde_plane_state *pstate;
  3447. int ret = -EINVAL;
  3448. if (!plane) {
  3449. SDE_ERROR("invalid plane\n");
  3450. } else if (!state) {
  3451. SDE_ERROR("invalid state\n");
  3452. } else {
  3453. SDE_DEBUG_PLANE(psde, "\n");
  3454. pstate = to_sde_plane_state(state);
  3455. ret = msm_property_atomic_get(&psde->property_info,
  3456. &pstate->property_state, property, val);
  3457. }
  3458. return ret;
  3459. }
  3460. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3461. struct drm_plane_state *plane_state)
  3462. {
  3463. struct sde_plane *psde;
  3464. struct sde_plane_state *pstate;
  3465. struct drm_property *drm_prop;
  3466. enum msm_mdp_plane_property prop_idx;
  3467. if (!plane || !plane_state) {
  3468. SDE_ERROR("invalid params\n");
  3469. return -EINVAL;
  3470. }
  3471. psde = to_sde_plane(plane);
  3472. pstate = to_sde_plane_state(plane_state);
  3473. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3474. uint64_t val = pstate->property_values[prop_idx].value;
  3475. uint64_t def;
  3476. int ret;
  3477. drm_prop = msm_property_index_to_drm_property(
  3478. &psde->property_info, prop_idx);
  3479. if (!drm_prop) {
  3480. /* not all props will be installed, based on caps */
  3481. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3482. prop_idx);
  3483. continue;
  3484. }
  3485. def = msm_property_get_default(&psde->property_info, prop_idx);
  3486. if (val == def)
  3487. continue;
  3488. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3489. drm_prop->name, prop_idx, val, def);
  3490. ret = sde_plane_atomic_set_property(plane, plane_state,
  3491. drm_prop, def);
  3492. if (ret) {
  3493. SDE_ERROR_PLANE(psde,
  3494. "set property failed, idx %d ret %d\n",
  3495. prop_idx, ret);
  3496. continue;
  3497. }
  3498. }
  3499. return 0;
  3500. }
  3501. static void sde_plane_destroy(struct drm_plane *plane)
  3502. {
  3503. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3504. SDE_DEBUG_PLANE(psde, "\n");
  3505. if (psde) {
  3506. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3507. if (psde->blob_info)
  3508. drm_property_blob_put(psde->blob_info);
  3509. msm_property_destroy(&psde->property_info);
  3510. mutex_destroy(&psde->lock);
  3511. /* this will destroy the states as well */
  3512. drm_plane_cleanup(plane);
  3513. if (psde->pipe_hw)
  3514. sde_hw_sspp_destroy(psde->pipe_hw);
  3515. kfree(psde);
  3516. }
  3517. }
  3518. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3519. {
  3520. struct sde_plane_state *pstate;
  3521. if (!state) {
  3522. SDE_ERROR("invalid arg state %d\n", !state);
  3523. return;
  3524. }
  3525. pstate = to_sde_plane_state(state);
  3526. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3527. SDE_DRM_FB_SEC) {
  3528. /* remove ref count for frame buffers */
  3529. if (state->fb) {
  3530. drm_framebuffer_put(state->fb);
  3531. state->fb = NULL;
  3532. }
  3533. }
  3534. }
  3535. static void sde_plane_destroy_state(struct drm_plane *plane,
  3536. struct drm_plane_state *state)
  3537. {
  3538. struct sde_plane *psde;
  3539. struct sde_plane_state *pstate;
  3540. if (!plane || !state) {
  3541. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3542. !plane, !state);
  3543. return;
  3544. }
  3545. psde = to_sde_plane(plane);
  3546. pstate = to_sde_plane_state(state);
  3547. SDE_DEBUG_PLANE(psde, "\n");
  3548. /* remove ref count for frame buffers */
  3549. if (state->fb)
  3550. drm_framebuffer_put(state->fb);
  3551. /* remove ref count for fence */
  3552. if (pstate->input_fence)
  3553. sde_sync_put(pstate->input_fence);
  3554. /* destroy value helper */
  3555. msm_property_destroy_state(&psde->property_info, pstate,
  3556. &pstate->property_state);
  3557. }
  3558. static struct drm_plane_state *
  3559. sde_plane_duplicate_state(struct drm_plane *plane)
  3560. {
  3561. struct sde_plane *psde;
  3562. struct sde_plane_state *pstate;
  3563. struct sde_plane_state *old_state;
  3564. struct drm_property *drm_prop;
  3565. uint64_t input_fence_default;
  3566. if (!plane) {
  3567. SDE_ERROR("invalid plane\n");
  3568. return NULL;
  3569. } else if (!plane->state) {
  3570. SDE_ERROR("invalid plane state\n");
  3571. return NULL;
  3572. }
  3573. old_state = to_sde_plane_state(plane->state);
  3574. psde = to_sde_plane(plane);
  3575. pstate = msm_property_alloc_state(&psde->property_info);
  3576. if (!pstate) {
  3577. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3578. return NULL;
  3579. }
  3580. SDE_DEBUG_PLANE(psde, "\n");
  3581. /* duplicate value helper */
  3582. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3583. &pstate->property_state, pstate->property_values);
  3584. /* clear out any input fence */
  3585. pstate->input_fence = 0;
  3586. input_fence_default = msm_property_get_default(
  3587. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3588. drm_prop = msm_property_index_to_drm_property(
  3589. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3590. if (msm_property_atomic_set(&psde->property_info,
  3591. &pstate->property_state, drm_prop,
  3592. input_fence_default))
  3593. SDE_DEBUG_PLANE(psde,
  3594. "error clearing duplicated input fence\n");
  3595. pstate->dirty = 0x0;
  3596. pstate->pending = false;
  3597. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3598. /* reset layout offset */
  3599. if (pstate->layout_offset) {
  3600. if (pstate->layout_offset > 0)
  3601. pstate->base.crtc_x += pstate->layout_offset;
  3602. pstate->layout = SDE_LAYOUT_NONE;
  3603. pstate->layout_offset = 0;
  3604. }
  3605. return &pstate->base;
  3606. }
  3607. static void sde_plane_reset(struct drm_plane *plane)
  3608. {
  3609. struct sde_plane *psde;
  3610. struct sde_plane_state *pstate;
  3611. if (!plane) {
  3612. SDE_ERROR("invalid plane\n");
  3613. return;
  3614. }
  3615. psde = to_sde_plane(plane);
  3616. SDE_DEBUG_PLANE(psde, "\n");
  3617. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3618. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3619. return;
  3620. }
  3621. /* remove previous state, if present */
  3622. if (plane->state) {
  3623. sde_plane_destroy_state(plane, plane->state);
  3624. plane->state = 0;
  3625. }
  3626. pstate = msm_property_alloc_state(&psde->property_info);
  3627. if (!pstate) {
  3628. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3629. return;
  3630. }
  3631. /* reset value helper */
  3632. msm_property_reset_state(&psde->property_info, pstate,
  3633. &pstate->property_state,
  3634. pstate->property_values);
  3635. pstate->base.plane = plane;
  3636. plane->state = &pstate->base;
  3637. }
  3638. u32 sde_plane_get_ubwc_error(struct drm_plane *plane)
  3639. {
  3640. u32 ubwc_error = 0;
  3641. struct sde_plane *psde;
  3642. if (!plane) {
  3643. SDE_ERROR("invalid plane\n");
  3644. return 0;
  3645. }
  3646. psde = to_sde_plane(plane);
  3647. if (!psde->is_virtual && psde->pipe_hw->ops.get_ubwc_error)
  3648. ubwc_error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw);
  3649. return ubwc_error;
  3650. }
  3651. void sde_plane_clear_ubwc_error(struct drm_plane *plane)
  3652. {
  3653. struct sde_plane *psde;
  3654. if (!plane) {
  3655. SDE_ERROR("invalid plane\n");
  3656. return;
  3657. }
  3658. psde = to_sde_plane(plane);
  3659. if (psde->pipe_hw->ops.clear_ubwc_error)
  3660. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw);
  3661. }
  3662. #ifdef CONFIG_DEBUG_FS
  3663. static ssize_t _sde_plane_danger_read(struct file *file,
  3664. char __user *buff, size_t count, loff_t *ppos)
  3665. {
  3666. struct sde_kms *kms = file->private_data;
  3667. struct sde_mdss_cfg *cfg = kms->catalog;
  3668. int len = 0;
  3669. char buf[40] = {'\0'};
  3670. if (!cfg)
  3671. return -ENODEV;
  3672. if (*ppos)
  3673. return 0; /* the end */
  3674. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3675. if (len < 0 || len >= sizeof(buf))
  3676. return 0;
  3677. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3678. return -EFAULT;
  3679. *ppos += len; /* increase offset */
  3680. return len;
  3681. }
  3682. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3683. {
  3684. struct drm_plane *plane;
  3685. drm_for_each_plane(plane, kms->dev) {
  3686. if (plane->fb && plane->state) {
  3687. sde_plane_danger_signal_ctrl(plane, enable);
  3688. SDE_DEBUG("plane:%d img:%dx%d ",
  3689. plane->base.id, plane->fb->width,
  3690. plane->fb->height);
  3691. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3692. plane->state->src_x >> 16,
  3693. plane->state->src_y >> 16,
  3694. plane->state->src_w >> 16,
  3695. plane->state->src_h >> 16,
  3696. plane->state->crtc_x, plane->state->crtc_y,
  3697. plane->state->crtc_w, plane->state->crtc_h);
  3698. } else {
  3699. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3700. }
  3701. }
  3702. }
  3703. static ssize_t _sde_plane_danger_write(struct file *file,
  3704. const char __user *user_buf, size_t count, loff_t *ppos)
  3705. {
  3706. struct sde_kms *kms = file->private_data;
  3707. struct sde_mdss_cfg *cfg = kms->catalog;
  3708. int disable_panic;
  3709. char buf[10];
  3710. if (!cfg)
  3711. return -EFAULT;
  3712. if (count >= sizeof(buf))
  3713. return -EFAULT;
  3714. if (copy_from_user(buf, user_buf, count))
  3715. return -EFAULT;
  3716. buf[count] = 0; /* end of string */
  3717. if (kstrtoint(buf, 0, &disable_panic))
  3718. return -EFAULT;
  3719. if (disable_panic) {
  3720. /* Disable panic signal for all active pipes */
  3721. SDE_DEBUG("Disabling danger:\n");
  3722. _sde_plane_set_danger_state(kms, false);
  3723. kms->has_danger_ctrl = false;
  3724. } else {
  3725. /* Enable panic signal for all active pipes */
  3726. SDE_DEBUG("Enabling danger:\n");
  3727. kms->has_danger_ctrl = true;
  3728. _sde_plane_set_danger_state(kms, true);
  3729. }
  3730. return count;
  3731. }
  3732. static const struct file_operations sde_plane_danger_enable = {
  3733. .open = simple_open,
  3734. .read = _sde_plane_danger_read,
  3735. .write = _sde_plane_danger_write,
  3736. };
  3737. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3738. {
  3739. struct sde_plane *psde;
  3740. struct sde_kms *kms;
  3741. struct msm_drm_private *priv;
  3742. const struct sde_sspp_sub_blks *sblk = 0;
  3743. const struct sde_sspp_cfg *cfg = 0;
  3744. if (!plane || !plane->dev) {
  3745. SDE_ERROR("invalid arguments\n");
  3746. return -EINVAL;
  3747. }
  3748. priv = plane->dev->dev_private;
  3749. if (!priv || !priv->kms) {
  3750. SDE_ERROR("invalid KMS reference\n");
  3751. return -EINVAL;
  3752. }
  3753. kms = to_sde_kms(priv->kms);
  3754. psde = to_sde_plane(plane);
  3755. if (psde && psde->pipe_hw)
  3756. cfg = psde->pipe_hw->cap;
  3757. if (cfg)
  3758. sblk = cfg->sblk;
  3759. if (!sblk)
  3760. return 0;
  3761. /* create overall sub-directory for the pipe */
  3762. psde->debugfs_root =
  3763. debugfs_create_dir(psde->pipe_name,
  3764. plane->dev->primary->debugfs_root);
  3765. if (!psde->debugfs_root)
  3766. return -ENOMEM;
  3767. /* don't error check these */
  3768. debugfs_create_x32("features", 0400,
  3769. psde->debugfs_root, &psde->features);
  3770. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3771. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3772. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3773. debugfs_create_bool("default_scaling",
  3774. 0600,
  3775. psde->debugfs_root,
  3776. &psde->debugfs_default_scale);
  3777. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3778. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3779. 0600,
  3780. psde->debugfs_root,
  3781. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3782. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3783. 0600,
  3784. psde->debugfs_root,
  3785. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3786. debugfs_create_u32("in_rot_max_downscale_nrt",
  3787. 0600,
  3788. psde->debugfs_root,
  3789. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3790. debugfs_create_u32("in_rot_max_height",
  3791. 0600,
  3792. psde->debugfs_root,
  3793. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3794. }
  3795. debugfs_create_u32("xin_id",
  3796. 0400,
  3797. psde->debugfs_root,
  3798. (u32 *) &cfg->xin_id);
  3799. debugfs_create_x32("creq_vblank",
  3800. 0600,
  3801. psde->debugfs_root,
  3802. (u32 *) &sblk->creq_vblank);
  3803. debugfs_create_x32("danger_vblank",
  3804. 0600,
  3805. psde->debugfs_root,
  3806. (u32 *) &sblk->danger_vblank);
  3807. debugfs_create_file("disable_danger",
  3808. 0600,
  3809. psde->debugfs_root,
  3810. kms, &sde_plane_danger_enable);
  3811. return 0;
  3812. }
  3813. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3814. {
  3815. struct sde_plane *psde;
  3816. if (!plane)
  3817. return;
  3818. psde = to_sde_plane(plane);
  3819. debugfs_remove_recursive(psde->debugfs_root);
  3820. }
  3821. #else
  3822. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3823. {
  3824. return 0;
  3825. }
  3826. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3827. {
  3828. }
  3829. #endif
  3830. static int sde_plane_late_register(struct drm_plane *plane)
  3831. {
  3832. return _sde_plane_init_debugfs(plane);
  3833. }
  3834. static void sde_plane_early_unregister(struct drm_plane *plane)
  3835. {
  3836. _sde_plane_destroy_debugfs(plane);
  3837. }
  3838. static const struct drm_plane_funcs sde_plane_funcs = {
  3839. .update_plane = drm_atomic_helper_update_plane,
  3840. .disable_plane = drm_atomic_helper_disable_plane,
  3841. .destroy = sde_plane_destroy,
  3842. .atomic_set_property = sde_plane_atomic_set_property,
  3843. .atomic_get_property = sde_plane_atomic_get_property,
  3844. .reset = sde_plane_reset,
  3845. .atomic_duplicate_state = sde_plane_duplicate_state,
  3846. .atomic_destroy_state = sde_plane_destroy_state,
  3847. .late_register = sde_plane_late_register,
  3848. .early_unregister = sde_plane_early_unregister,
  3849. };
  3850. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  3851. .prepare_fb = sde_plane_prepare_fb,
  3852. .cleanup_fb = sde_plane_cleanup_fb,
  3853. .atomic_check = sde_plane_atomic_check,
  3854. .atomic_update = sde_plane_atomic_update,
  3855. };
  3856. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  3857. {
  3858. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  3859. }
  3860. bool is_sde_plane_virtual(struct drm_plane *plane)
  3861. {
  3862. return plane ? to_sde_plane(plane)->is_virtual : false;
  3863. }
  3864. /* initialize plane */
  3865. struct drm_plane *sde_plane_init(struct drm_device *dev,
  3866. uint32_t pipe, bool primary_plane,
  3867. unsigned long possible_crtcs, u32 master_plane_id)
  3868. {
  3869. struct drm_plane *plane = NULL, *master_plane = NULL;
  3870. const struct sde_format_extended *format_list;
  3871. struct sde_plane *psde;
  3872. struct msm_drm_private *priv;
  3873. struct sde_kms *kms;
  3874. enum drm_plane_type type;
  3875. int ret = -EINVAL;
  3876. if (!dev) {
  3877. SDE_ERROR("[%u]device is NULL\n", pipe);
  3878. goto exit;
  3879. }
  3880. priv = dev->dev_private;
  3881. if (!priv) {
  3882. SDE_ERROR("[%u]private data is NULL\n", pipe);
  3883. goto exit;
  3884. }
  3885. if (!priv->kms) {
  3886. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  3887. goto exit;
  3888. }
  3889. kms = to_sde_kms(priv->kms);
  3890. if (!kms->catalog) {
  3891. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  3892. goto exit;
  3893. }
  3894. /* create and zero local structure */
  3895. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  3896. if (!psde) {
  3897. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  3898. ret = -ENOMEM;
  3899. goto exit;
  3900. }
  3901. /* cache local stuff for later */
  3902. plane = &psde->base;
  3903. psde->pipe = pipe;
  3904. psde->is_virtual = (master_plane_id != 0);
  3905. INIT_LIST_HEAD(&psde->mplane_list);
  3906. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  3907. if (master_plane) {
  3908. struct sde_plane *mpsde = to_sde_plane(master_plane);
  3909. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  3910. }
  3911. /* initialize underlying h/w driver */
  3912. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog,
  3913. psde->is_virtual);
  3914. if (IS_ERR(psde->pipe_hw)) {
  3915. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  3916. ret = PTR_ERR(psde->pipe_hw);
  3917. goto clean_plane;
  3918. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  3919. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  3920. goto clean_sspp;
  3921. }
  3922. /* cache features mask for later */
  3923. psde->features = psde->pipe_hw->cap->features;
  3924. psde->perf_features = psde->pipe_hw->cap->perf_features;
  3925. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  3926. if (!psde->pipe_sblk) {
  3927. SDE_ERROR("[%u]invalid sblk\n", pipe);
  3928. goto clean_sspp;
  3929. }
  3930. if (psde->is_virtual)
  3931. format_list = psde->pipe_sblk->virt_format_list;
  3932. else
  3933. format_list = psde->pipe_sblk->format_list;
  3934. psde->nformats = sde_populate_formats(format_list,
  3935. psde->formats,
  3936. 0,
  3937. ARRAY_SIZE(psde->formats));
  3938. if (!psde->nformats) {
  3939. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  3940. goto clean_sspp;
  3941. }
  3942. if (psde->features & BIT(SDE_SSPP_CURSOR))
  3943. type = DRM_PLANE_TYPE_CURSOR;
  3944. else if (primary_plane)
  3945. type = DRM_PLANE_TYPE_PRIMARY;
  3946. else
  3947. type = DRM_PLANE_TYPE_OVERLAY;
  3948. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  3949. psde->formats, psde->nformats,
  3950. NULL, type, NULL);
  3951. if (ret)
  3952. goto clean_sspp;
  3953. /* Populate static array of plane property flags */
  3954. _sde_plane_map_prop_to_dirty_bits();
  3955. /* success! finalize initialization */
  3956. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  3957. msm_property_init(&psde->property_info, &plane->base, dev,
  3958. priv->plane_property, psde->property_data,
  3959. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  3960. sizeof(struct sde_plane_state));
  3961. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  3962. /* save user friendly pipe name for later */
  3963. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  3964. mutex_init(&psde->lock);
  3965. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  3966. pipe, plane->base.id, master_plane_id);
  3967. return plane;
  3968. clean_sspp:
  3969. if (psde && psde->pipe_hw)
  3970. sde_hw_sspp_destroy(psde->pipe_hw);
  3971. clean_plane:
  3972. kfree(psde);
  3973. exit:
  3974. return ERR_PTR(ret);
  3975. }