main.c 147 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214521552165217521852195220522152225223522452255226522752285229523052315232523352345235523652375238523952405241524252435244524552465247524852495250525152525253525452555256525752585259526052615262526352645265526652675268526952705271527252735274527552765277527852795280528152825283528452855286528752885289529052915292529352945295529652975298529953005301530253035304530553065307530853095310531153125313531453155316531753185319532053215322532353245325532653275328532953305331533253335334533553365337533853395340534153425343534453455346534753485349535053515352535353545355535653575358535953605361536253635364536553665367536853695370537153725373537453755376537753785379538053815382538353845385538653875388538953905391539253935394539553965397539853995400540154025403540454055406540754085409541054115412541354145415541654175418541954205421542254235424542554265427542854295430543154325433543454355436543754385439544054415442544354445445544654475448544954505451545254535454545554565457545854595460546154625463546454655466546754685469547054715472547354745475547654775478547954805481548254835484548554865487548854895490549154925493549454955496549754985499550055015502550355045505550655075508550955105511551255135514551555165517551855195520552155225523552455255526552755285529553055315532553355345535553655375538553955405541554255435544554555465547554855495550555155525553555455555556555755585559556055615562556355645565556655675568556955705571557255735574557555765577557855795580558155825583558455855586558755885589559055915592559355945595559655975598559956005601560256035604560556065607560856095610561156125613561456155616561756185619562056215622562356245625562656275628562956305631563256335634563556365637563856395640564156425643564456455646
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/thermal.h>
  20. #include <linux/version.h>
  21. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  22. #include <linux/panic_notifier.h>
  23. #endif
  24. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  25. #include <soc/qcom/minidump.h>
  26. #endif
  27. #include "cnss_plat_ipc_qmi.h"
  28. #include "cnss_utils.h"
  29. #include "main.h"
  30. #include "bus.h"
  31. #include "debug.h"
  32. #include "genl.h"
  33. #include "reg.h"
  34. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  35. #ifdef CONFIG_CNSS_HW_SECURE_SMEM
  36. #include <linux/soc/qcom/smem.h>
  37. #define PERISEC_SMEM_ID 651
  38. #define HW_WIFI_UID 0x508
  39. #else
  40. #include "smcinvoke.h"
  41. #include "smcinvoke_object.h"
  42. #include "IClientEnv.h"
  43. #define HW_STATE_UID 0x108
  44. #define HW_OP_GET_STATE 1
  45. #define HW_WIFI_UID 0x508
  46. #define FEATURE_NOT_SUPPORTED 12
  47. #define PERIPHERAL_NOT_FOUND 10
  48. #endif
  49. #endif
  50. #define CNSS_DUMP_FORMAT_VER 0x11
  51. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  52. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  53. #define CNSS_DUMP_NAME "CNSS_WLAN"
  54. #define CNSS_DUMP_DESC_SIZE 0x1000
  55. #define CNSS_DUMP_SEG_VER 0x1
  56. #define FILE_SYSTEM_READY 1
  57. #define FW_READY_TIMEOUT 20000
  58. #define FW_ASSERT_TIMEOUT 5000
  59. #define CNSS_EVENT_PENDING 2989
  60. #define POWER_RESET_MIN_DELAY_MS 100
  61. #define MAX_NAME_LEN 12
  62. #define CNSS_QUIRKS_DEFAULT 0
  63. #ifdef CONFIG_CNSS_EMULATION
  64. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  65. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  66. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  67. #else
  68. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  69. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  70. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  71. #endif
  72. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  73. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  74. #define CNSS_MIN_TIME_SYNC_PERIOD 2000
  75. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  76. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  77. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  78. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  79. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  80. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  81. #define CNSS_TIME_SYNC_PERIOD_INVALID 0xFFFFFFFF
  82. enum cnss_cal_db_op {
  83. CNSS_CAL_DB_UPLOAD,
  84. CNSS_CAL_DB_DOWNLOAD,
  85. CNSS_CAL_DB_INVALID_OP,
  86. };
  87. enum cnss_recovery_type {
  88. CNSS_WLAN_RECOVERY = 0x1,
  89. CNSS_PCSS_RECOVERY = 0x2,
  90. };
  91. #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV
  92. #define CNSS_MAX_DEV_NUM 2
  93. static struct cnss_plat_data *plat_env[CNSS_MAX_DEV_NUM];
  94. static int plat_env_count;
  95. #else
  96. static struct cnss_plat_data *plat_env;
  97. #endif
  98. static bool cnss_allow_driver_loading;
  99. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  100. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  101. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  102. };
  103. static struct cnss_fw_files FW_FILES_DEFAULT = {
  104. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  105. "utfbd.bin", "epping.bin", "evicted.bin"
  106. };
  107. struct cnss_driver_event {
  108. struct list_head list;
  109. enum cnss_driver_event_type type;
  110. bool sync;
  111. struct completion complete;
  112. int ret;
  113. void *data;
  114. };
  115. bool cnss_check_driver_loading_allowed(void)
  116. {
  117. return cnss_allow_driver_loading;
  118. }
  119. #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV
  120. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  121. struct cnss_plat_data *plat_priv)
  122. {
  123. cnss_pr_dbg("Set plat_priv at %d", plat_env_count);
  124. if (plat_priv) {
  125. plat_priv->plat_idx = plat_env_count;
  126. plat_env[plat_priv->plat_idx] = plat_priv;
  127. plat_env_count++;
  128. }
  129. }
  130. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device
  131. *plat_dev)
  132. {
  133. int i;
  134. if (!plat_dev)
  135. return NULL;
  136. for (i = 0; i < plat_env_count; i++) {
  137. if (plat_env[i]->plat_dev == plat_dev)
  138. return plat_env[i];
  139. }
  140. return NULL;
  141. }
  142. struct cnss_plat_data *cnss_get_first_plat_priv(struct platform_device
  143. *plat_dev)
  144. {
  145. int i;
  146. if (!plat_dev) {
  147. for (i = 0; i < plat_env_count; i++) {
  148. if (plat_env[i])
  149. return plat_env[i];
  150. }
  151. }
  152. return NULL;
  153. }
  154. static void cnss_clear_plat_priv(struct cnss_plat_data *plat_priv)
  155. {
  156. cnss_pr_dbg("Clear plat_priv at %d", plat_priv->plat_idx);
  157. plat_env[plat_priv->plat_idx] = NULL;
  158. plat_env_count--;
  159. }
  160. static int cnss_set_device_name(struct cnss_plat_data *plat_priv)
  161. {
  162. snprintf(plat_priv->device_name, sizeof(plat_priv->device_name),
  163. "wlan_%d", plat_priv->plat_idx);
  164. return 0;
  165. }
  166. static int cnss_plat_env_available(void)
  167. {
  168. int ret = 0;
  169. if (plat_env_count >= CNSS_MAX_DEV_NUM) {
  170. cnss_pr_err("ERROR: No space to store plat_priv\n");
  171. ret = -ENOMEM;
  172. }
  173. return ret;
  174. }
  175. int cnss_get_plat_env_count(void)
  176. {
  177. return plat_env_count;
  178. }
  179. struct cnss_plat_data *cnss_get_plat_env(int index)
  180. {
  181. return plat_env[index];
  182. }
  183. struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num)
  184. {
  185. int i;
  186. for (i = 0; i < plat_env_count; i++) {
  187. if (plat_env[i]->rc_num == rc_num)
  188. return plat_env[i];
  189. }
  190. return NULL;
  191. }
  192. static inline int
  193. cnss_get_qrtr_node_id(struct cnss_plat_data *plat_priv)
  194. {
  195. return of_property_read_u32(plat_priv->dev_node,
  196. "qcom,qrtr_node_id", &plat_priv->qrtr_node_id);
  197. }
  198. void cnss_get_qrtr_info(struct cnss_plat_data *plat_priv)
  199. {
  200. int ret = 0;
  201. ret = cnss_get_qrtr_node_id(plat_priv);
  202. if (ret) {
  203. cnss_pr_warn("Failed to find qrtr_node_id err=%d\n", ret);
  204. plat_priv->qrtr_node_id = 0;
  205. plat_priv->wlfw_service_instance_id = 0;
  206. } else {
  207. plat_priv->wlfw_service_instance_id = plat_priv->qrtr_node_id +
  208. QRTR_NODE_FW_ID_BASE;
  209. cnss_pr_dbg("service_instance_id=0x%x\n",
  210. plat_priv->wlfw_service_instance_id);
  211. }
  212. }
  213. static inline int
  214. cnss_get_pld_bus_ops_name(struct cnss_plat_data *plat_priv)
  215. {
  216. return of_property_read_string(plat_priv->plat_dev->dev.of_node,
  217. "qcom,pld_bus_ops_name",
  218. &plat_priv->pld_bus_ops_name);
  219. }
  220. #else
  221. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  222. struct cnss_plat_data *plat_priv)
  223. {
  224. plat_env = plat_priv;
  225. }
  226. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  227. {
  228. return plat_env;
  229. }
  230. static void cnss_clear_plat_priv(struct cnss_plat_data *plat_priv)
  231. {
  232. plat_env = NULL;
  233. }
  234. static int cnss_set_device_name(struct cnss_plat_data *plat_priv)
  235. {
  236. snprintf(plat_priv->device_name, sizeof(plat_priv->device_name),
  237. "wlan");
  238. return 0;
  239. }
  240. static int cnss_plat_env_available(void)
  241. {
  242. return 0;
  243. }
  244. struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num)
  245. {
  246. return cnss_bus_dev_to_plat_priv(NULL);
  247. }
  248. void cnss_get_qrtr_info(struct cnss_plat_data *plat_priv)
  249. {
  250. }
  251. static int
  252. cnss_get_pld_bus_ops_name(struct cnss_plat_data *plat_priv)
  253. {
  254. return 0;
  255. }
  256. #endif
  257. void cnss_get_sleep_clk_supported(struct cnss_plat_data *plat_priv)
  258. {
  259. plat_priv->sleep_clk = of_property_read_bool(plat_priv->dev_node,
  260. "qcom,sleep-clk-support");
  261. cnss_pr_dbg("qcom,sleep-clk-support is %d\n",
  262. plat_priv->sleep_clk);
  263. }
  264. void cnss_get_bwscal_info(struct cnss_plat_data *plat_priv)
  265. {
  266. plat_priv->no_bwscale = of_property_read_bool(plat_priv->dev_node,
  267. "qcom,no-bwscale");
  268. }
  269. static inline int
  270. cnss_get_rc_num(struct cnss_plat_data *plat_priv)
  271. {
  272. return of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  273. "qcom,wlan-rc-num", &plat_priv->rc_num);
  274. }
  275. bool cnss_is_dual_wlan_enabled(void)
  276. {
  277. return IS_ENABLED(CONFIG_CNSS_SUPPORT_DUAL_DEV);
  278. }
  279. /**
  280. * cnss_get_mem_seg_count - Get segment count of memory
  281. * @type: memory type
  282. * @seg: segment count
  283. *
  284. * Return: 0 on success, negative value on failure
  285. */
  286. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  287. {
  288. struct cnss_plat_data *plat_priv;
  289. plat_priv = cnss_get_plat_priv(NULL);
  290. if (!plat_priv)
  291. return -ENODEV;
  292. switch (type) {
  293. case CNSS_REMOTE_MEM_TYPE_FW:
  294. *seg = plat_priv->fw_mem_seg_len;
  295. break;
  296. case CNSS_REMOTE_MEM_TYPE_QDSS:
  297. *seg = plat_priv->qdss_mem_seg_len;
  298. break;
  299. default:
  300. return -EINVAL;
  301. }
  302. return 0;
  303. }
  304. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  305. /**
  306. * cnss_get_wifi_kobject -return wifi kobject
  307. * Return: Null, to maintain driver comnpatibilty
  308. */
  309. struct kobject *cnss_get_wifi_kobj(struct device *dev)
  310. {
  311. struct cnss_plat_data *plat_priv;
  312. plat_priv = cnss_get_plat_priv(NULL);
  313. if (!plat_priv)
  314. return NULL;
  315. return plat_priv->wifi_kobj;
  316. }
  317. EXPORT_SYMBOL(cnss_get_wifi_kobj);
  318. /**
  319. * cnss_get_mem_segment_info - Get memory info of different type
  320. * @type: memory type
  321. * @segment: array to save the segment info
  322. * @seg: segment count
  323. *
  324. * Return: 0 on success, negative value on failure
  325. */
  326. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  327. struct cnss_mem_segment segment[],
  328. u32 segment_count)
  329. {
  330. struct cnss_plat_data *plat_priv;
  331. u32 i;
  332. plat_priv = cnss_get_plat_priv(NULL);
  333. if (!plat_priv)
  334. return -ENODEV;
  335. switch (type) {
  336. case CNSS_REMOTE_MEM_TYPE_FW:
  337. if (segment_count > plat_priv->fw_mem_seg_len)
  338. segment_count = plat_priv->fw_mem_seg_len;
  339. for (i = 0; i < segment_count; i++) {
  340. segment[i].size = plat_priv->fw_mem[i].size;
  341. segment[i].va = plat_priv->fw_mem[i].va;
  342. segment[i].pa = plat_priv->fw_mem[i].pa;
  343. }
  344. break;
  345. case CNSS_REMOTE_MEM_TYPE_QDSS:
  346. if (segment_count > plat_priv->qdss_mem_seg_len)
  347. segment_count = plat_priv->qdss_mem_seg_len;
  348. for (i = 0; i < segment_count; i++) {
  349. segment[i].size = plat_priv->qdss_mem[i].size;
  350. segment[i].va = plat_priv->qdss_mem[i].va;
  351. segment[i].pa = plat_priv->qdss_mem[i].pa;
  352. }
  353. break;
  354. default:
  355. return -EINVAL;
  356. }
  357. return 0;
  358. }
  359. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  360. static int cnss_get_audio_iommu_domain(struct cnss_plat_data *plat_priv)
  361. {
  362. struct device_node *audio_ion_node;
  363. struct platform_device *audio_ion_pdev;
  364. audio_ion_node = of_find_compatible_node(NULL, NULL,
  365. "qcom,msm-audio-ion");
  366. if (!audio_ion_node) {
  367. cnss_pr_err("Unable to get Audio ion node");
  368. return -EINVAL;
  369. }
  370. audio_ion_pdev = of_find_device_by_node(audio_ion_node);
  371. of_node_put(audio_ion_node);
  372. if (!audio_ion_pdev) {
  373. cnss_pr_err("Unable to get Audio ion platform device");
  374. return -EINVAL;
  375. }
  376. plat_priv->audio_iommu_domain =
  377. iommu_get_domain_for_dev(&audio_ion_pdev->dev);
  378. put_device(&audio_ion_pdev->dev);
  379. if (!plat_priv->audio_iommu_domain) {
  380. cnss_pr_err("Unable to get Audio ion iommu domain");
  381. return -EINVAL;
  382. }
  383. return 0;
  384. }
  385. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  386. enum cnss_feature_v01 feature)
  387. {
  388. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  389. return -EINVAL;
  390. plat_priv->feature_list |= 1 << feature;
  391. return 0;
  392. }
  393. int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
  394. enum cnss_feature_v01 feature)
  395. {
  396. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  397. return -EINVAL;
  398. plat_priv->feature_list &= ~(1 << feature);
  399. return 0;
  400. }
  401. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  402. u64 *feature_list)
  403. {
  404. if (unlikely(!plat_priv))
  405. return -EINVAL;
  406. *feature_list = plat_priv->feature_list;
  407. return 0;
  408. }
  409. size_t cnss_get_platform_name(struct cnss_plat_data *plat_priv,
  410. char *buf, const size_t buf_len)
  411. {
  412. if (unlikely(!plat_priv || !buf || !buf_len))
  413. return 0;
  414. if (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  415. "platform-name-required")) {
  416. struct device_node *root;
  417. root = of_find_node_by_path("/");
  418. if (root) {
  419. const char *model;
  420. size_t model_len;
  421. model = of_get_property(root, "model", NULL);
  422. if (model) {
  423. model_len = strlcpy(buf, model, buf_len);
  424. cnss_pr_dbg("Platform name: %s (%zu)\n",
  425. buf, model_len);
  426. return model_len;
  427. }
  428. }
  429. }
  430. return 0;
  431. }
  432. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  433. {
  434. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  435. return;
  436. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  437. plat_priv->driver_state,
  438. atomic_read(&plat_priv->pm_count));
  439. pm_stay_awake(&plat_priv->plat_dev->dev);
  440. }
  441. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  442. {
  443. int r = atomic_dec_return(&plat_priv->pm_count);
  444. WARN_ON(r < 0);
  445. if (r != 0)
  446. return;
  447. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  448. plat_priv->driver_state,
  449. atomic_read(&plat_priv->pm_count));
  450. pm_relax(&plat_priv->plat_dev->dev);
  451. }
  452. int cnss_get_fw_files_for_target(struct device *dev,
  453. struct cnss_fw_files *pfw_files,
  454. u32 target_type, u32 target_version)
  455. {
  456. if (!pfw_files)
  457. return -ENODEV;
  458. switch (target_version) {
  459. case QCA6174_REV3_VERSION:
  460. case QCA6174_REV3_2_VERSION:
  461. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  462. break;
  463. default:
  464. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  465. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  466. target_type, target_version);
  467. break;
  468. }
  469. return 0;
  470. }
  471. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  472. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  473. {
  474. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  475. if (!plat_priv)
  476. return -ENODEV;
  477. if (!cap)
  478. return -EINVAL;
  479. *cap = plat_priv->cap;
  480. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  481. return 0;
  482. }
  483. EXPORT_SYMBOL(cnss_get_platform_cap);
  484. /**
  485. * cnss_get_fw_cap - Check whether FW supports specific capability or not
  486. * @dev: Device
  487. * @fw_cap: FW Capability which needs to be checked
  488. *
  489. * Return: TRUE if supported, FALSE on failure or if not supported
  490. */
  491. bool cnss_get_fw_cap(struct device *dev, enum cnss_fw_caps fw_cap)
  492. {
  493. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  494. bool is_supported = false;
  495. if (!plat_priv)
  496. return is_supported;
  497. if (!plat_priv->fw_caps)
  498. return is_supported;
  499. switch (fw_cap) {
  500. case CNSS_FW_CAP_DIRECT_LINK_SUPPORT:
  501. is_supported = !!(plat_priv->fw_caps &
  502. QMI_WLFW_DIRECT_LINK_SUPPORT_V01);
  503. break;
  504. case CNSS_FW_CAP_CALDB_SEG_DDR_SUPPORT:
  505. is_supported = !!(plat_priv->fw_caps &
  506. QMI_WLFW_CALDB_SEG_DDR_SUPPORT_V01);
  507. break;
  508. default:
  509. cnss_pr_err("Invalid FW Capability: 0x%x\n", fw_cap);
  510. }
  511. cnss_pr_dbg("FW Capability 0x%x is %s\n", fw_cap,
  512. is_supported ? "supported" : "not supported");
  513. return is_supported;
  514. }
  515. EXPORT_SYMBOL(cnss_get_fw_cap);
  516. /**
  517. * cnss_audio_is_direct_link_supported - Check whether Audio can be used for direct link support
  518. * @dev: Device
  519. *
  520. * Return: TRUE if supported, FALSE on failure or if not supported
  521. */
  522. bool cnss_audio_is_direct_link_supported(struct device *dev)
  523. {
  524. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  525. bool is_supported = false;
  526. if (!plat_priv) {
  527. cnss_pr_err("plat_priv not available to check audio direct link cap\n");
  528. return is_supported;
  529. }
  530. if (cnss_get_audio_iommu_domain(plat_priv) == 0)
  531. is_supported = true;
  532. return is_supported;
  533. }
  534. EXPORT_SYMBOL(cnss_audio_is_direct_link_supported);
  535. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  536. {
  537. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  538. if (!plat_priv)
  539. return;
  540. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  541. }
  542. EXPORT_SYMBOL(cnss_request_pm_qos);
  543. void cnss_remove_pm_qos(struct device *dev)
  544. {
  545. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  546. if (!plat_priv)
  547. return;
  548. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  549. }
  550. EXPORT_SYMBOL(cnss_remove_pm_qos);
  551. int cnss_wlan_enable(struct device *dev,
  552. struct cnss_wlan_enable_cfg *config,
  553. enum cnss_driver_mode mode,
  554. const char *host_version)
  555. {
  556. int ret = 0;
  557. struct cnss_plat_data *plat_priv;
  558. if (!dev) {
  559. cnss_pr_err("Invalid dev pointer\n");
  560. return -EINVAL;
  561. }
  562. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  563. if (!plat_priv)
  564. return -ENODEV;
  565. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  566. return 0;
  567. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  568. return 0;
  569. if (!config || !host_version) {
  570. cnss_pr_err("Invalid config or host_version pointer\n");
  571. return -EINVAL;
  572. }
  573. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  574. mode, config, host_version);
  575. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  576. goto skip_cfg;
  577. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  578. config->send_msi_ce = true;
  579. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  580. if (ret)
  581. goto out;
  582. skip_cfg:
  583. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  584. out:
  585. return ret;
  586. }
  587. EXPORT_SYMBOL(cnss_wlan_enable);
  588. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  589. {
  590. int ret = 0;
  591. struct cnss_plat_data *plat_priv;
  592. if (!dev) {
  593. cnss_pr_err("Invalid dev pointer\n");
  594. return -EINVAL;
  595. }
  596. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  597. if (!plat_priv)
  598. return -ENODEV;
  599. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  600. return 0;
  601. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  602. return 0;
  603. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  604. cnss_bus_free_qdss_mem(plat_priv);
  605. return ret;
  606. }
  607. EXPORT_SYMBOL(cnss_wlan_disable);
  608. #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
  609. int cnss_iommu_map(struct iommu_domain *domain,
  610. unsigned long iova, phys_addr_t paddr, size_t size, int prot)
  611. {
  612. return iommu_map(domain, iova, paddr, size, prot);
  613. }
  614. #else
  615. int cnss_iommu_map(struct iommu_domain *domain,
  616. unsigned long iova, phys_addr_t paddr, size_t size, int prot)
  617. {
  618. return iommu_map(domain, iova, paddr, size, prot, GFP_KERNEL);
  619. }
  620. #endif
  621. int cnss_audio_smmu_map(struct device *dev, phys_addr_t paddr,
  622. dma_addr_t iova, size_t size)
  623. {
  624. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  625. uint32_t page_offset;
  626. if (!plat_priv)
  627. return -ENODEV;
  628. if (!plat_priv->audio_iommu_domain)
  629. return -EINVAL;
  630. page_offset = iova & (PAGE_SIZE - 1);
  631. if (page_offset + size > PAGE_SIZE)
  632. size += PAGE_SIZE;
  633. iova -= page_offset;
  634. paddr -= page_offset;
  635. return cnss_iommu_map(plat_priv->audio_iommu_domain, iova, paddr,
  636. roundup(size, PAGE_SIZE), IOMMU_READ |
  637. IOMMU_WRITE | IOMMU_CACHE);
  638. }
  639. EXPORT_SYMBOL(cnss_audio_smmu_map);
  640. void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova, size_t size)
  641. {
  642. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  643. uint32_t page_offset;
  644. if (!plat_priv)
  645. return;
  646. if (!plat_priv->audio_iommu_domain)
  647. return;
  648. page_offset = iova & (PAGE_SIZE - 1);
  649. if (page_offset + size > PAGE_SIZE)
  650. size += PAGE_SIZE;
  651. iova -= page_offset;
  652. iommu_unmap(plat_priv->audio_iommu_domain, iova,
  653. roundup(size, PAGE_SIZE));
  654. }
  655. EXPORT_SYMBOL(cnss_audio_smmu_unmap);
  656. int cnss_get_fw_lpass_shared_mem(struct device *dev, dma_addr_t *iova,
  657. size_t *size)
  658. {
  659. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  660. uint8_t i;
  661. if (!plat_priv)
  662. return -EINVAL;
  663. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  664. if (plat_priv->fw_mem[i].type ==
  665. QMI_WLFW_MEM_LPASS_SHARED_V01) {
  666. *iova = plat_priv->fw_mem[i].pa;
  667. *size = plat_priv->fw_mem[i].size;
  668. return 0;
  669. }
  670. }
  671. return -EINVAL;
  672. }
  673. EXPORT_SYMBOL(cnss_get_fw_lpass_shared_mem);
  674. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  675. u32 data_len, u8 *output)
  676. {
  677. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  678. int ret = 0;
  679. if (!plat_priv) {
  680. cnss_pr_err("plat_priv is NULL!\n");
  681. return -EINVAL;
  682. }
  683. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  684. return 0;
  685. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  686. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  687. plat_priv->driver_state);
  688. ret = -EINVAL;
  689. goto out;
  690. }
  691. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  692. data_len, output);
  693. out:
  694. return ret;
  695. }
  696. EXPORT_SYMBOL(cnss_athdiag_read);
  697. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  698. u32 data_len, u8 *input)
  699. {
  700. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  701. int ret = 0;
  702. if (!plat_priv) {
  703. cnss_pr_err("plat_priv is NULL!\n");
  704. return -EINVAL;
  705. }
  706. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  707. return 0;
  708. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  709. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  710. plat_priv->driver_state);
  711. ret = -EINVAL;
  712. goto out;
  713. }
  714. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  715. data_len, input);
  716. out:
  717. return ret;
  718. }
  719. EXPORT_SYMBOL(cnss_athdiag_write);
  720. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  721. {
  722. struct cnss_plat_data *plat_priv;
  723. if (!dev) {
  724. cnss_pr_err("Invalid dev pointer\n");
  725. return -EINVAL;
  726. }
  727. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  728. if (!plat_priv)
  729. return -ENODEV;
  730. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  731. return 0;
  732. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  733. }
  734. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  735. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  736. {
  737. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  738. if (!plat_priv)
  739. return -EINVAL;
  740. if (!plat_priv->fw_pcie_gen_switch) {
  741. cnss_pr_err("Firmware does not support PCIe gen switch\n");
  742. return -EOPNOTSUPP;
  743. }
  744. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  745. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  746. return -EINVAL;
  747. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  748. plat_priv->pcie_gen_speed = pcie_gen_speed;
  749. return 0;
  750. }
  751. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  752. static bool cnss_is_aux_support_enabled(struct cnss_plat_data *plat_priv)
  753. {
  754. switch (plat_priv->device_id) {
  755. case PEACH_DEVICE_ID:
  756. if (!plat_priv->fw_aux_uc_support) {
  757. cnss_pr_dbg("FW does not support aux uc capability\n");
  758. return false;
  759. }
  760. break;
  761. default:
  762. cnss_pr_dbg("Host does not support aux uc capability\n");
  763. return false;
  764. }
  765. return true;
  766. }
  767. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  768. {
  769. int ret = 0;
  770. if (!plat_priv)
  771. return -ENODEV;
  772. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  773. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  774. if (ret)
  775. goto out;
  776. cnss_bus_load_tme_patch(plat_priv);
  777. cnss_wlfw_tme_patch_dnld_send_sync(plat_priv,
  778. WLFW_TME_LITE_PATCH_FILE_V01);
  779. if (plat_priv->hds_enabled)
  780. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  781. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  782. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  783. plat_priv->ctrl_params.bdf_type = CNSS_BDF_BIN;
  784. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  785. plat_priv->ctrl_params.bdf_type);
  786. if (ret)
  787. goto out;
  788. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  789. return 0;
  790. ret = cnss_bus_load_m3(plat_priv);
  791. if (ret)
  792. goto out;
  793. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  794. if (ret)
  795. goto out;
  796. if (cnss_is_aux_support_enabled(plat_priv)) {
  797. ret = cnss_bus_load_aux(plat_priv);
  798. if (ret)
  799. goto out;
  800. ret = cnss_wlfw_aux_dnld_send_sync(plat_priv);
  801. if (ret)
  802. goto out;
  803. }
  804. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  805. return 0;
  806. out:
  807. return ret;
  808. }
  809. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  810. {
  811. int ret = 0;
  812. if (!plat_priv->antenna) {
  813. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  814. if (ret)
  815. goto out;
  816. }
  817. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  818. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  819. if (ret)
  820. goto out;
  821. }
  822. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  823. if (ret)
  824. goto out;
  825. return 0;
  826. out:
  827. return ret;
  828. }
  829. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  830. {
  831. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  832. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  833. }
  834. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  835. {
  836. u32 i;
  837. int ret = 0;
  838. struct cnss_plat_ipc_daemon_config *cfg;
  839. ret = cnss_qmi_get_dms_mac(plat_priv);
  840. if (ret == 0 && plat_priv->dms.mac_valid)
  841. goto qmi_send;
  842. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  843. * Thus assert on failure to get MAC from DMS even after retries
  844. */
  845. if (plat_priv->use_nv_mac) {
  846. /* Check if Daemon says platform support DMS MAC provisioning */
  847. cfg = cnss_plat_ipc_qmi_daemon_config();
  848. if (cfg) {
  849. if (!cfg->dms_mac_addr_supported) {
  850. cnss_pr_err("DMS MAC address not supported\n");
  851. CNSS_ASSERT(0);
  852. return -EINVAL;
  853. }
  854. }
  855. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  856. if (plat_priv->dms.mac_valid)
  857. break;
  858. ret = cnss_qmi_get_dms_mac(plat_priv);
  859. if (ret == 0)
  860. break;
  861. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  862. }
  863. if (!plat_priv->dms.mac_valid) {
  864. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  865. CNSS_ASSERT(0);
  866. return -EINVAL;
  867. }
  868. }
  869. qmi_send:
  870. if (plat_priv->dms.mac_valid)
  871. ret =
  872. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  873. ARRAY_SIZE(plat_priv->dms.mac));
  874. return ret;
  875. }
  876. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  877. enum cnss_cal_db_op op, u32 *size)
  878. {
  879. int ret = 0;
  880. u32 timeout = cnss_get_timeout(plat_priv,
  881. CNSS_TIMEOUT_DAEMON_CONNECTION);
  882. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  883. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  884. if (op >= CNSS_CAL_DB_INVALID_OP)
  885. return -EINVAL;
  886. if (!plat_priv->cbc_file_download) {
  887. cnss_pr_info("CAL DB file not required as per BDF\n");
  888. return 0;
  889. }
  890. if (*size == 0) {
  891. cnss_pr_err("Invalid cal file size\n");
  892. return -EINVAL;
  893. }
  894. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  895. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  896. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  897. msecs_to_jiffies(timeout));
  898. if (!ret) {
  899. cnss_pr_err("Daemon not yet connected\n");
  900. CNSS_ASSERT(0);
  901. return ret;
  902. }
  903. }
  904. if (!plat_priv->cal_mem->va) {
  905. cnss_pr_err("CAL DB Memory not setup for FW\n");
  906. return -EINVAL;
  907. }
  908. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  909. if (op == CNSS_CAL_DB_DOWNLOAD) {
  910. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  911. ret = cnss_plat_ipc_qmi_file_download(client_id,
  912. CNSS_CAL_DB_FILE_NAME,
  913. plat_priv->cal_mem->va,
  914. size);
  915. } else {
  916. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  917. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  918. CNSS_CAL_DB_FILE_NAME,
  919. plat_priv->cal_mem->va,
  920. *size);
  921. }
  922. if (ret)
  923. cnss_pr_err("Cal DB file %s %s failure\n",
  924. CNSS_CAL_DB_FILE_NAME,
  925. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  926. else
  927. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  928. CNSS_CAL_DB_FILE_NAME,
  929. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  930. *size);
  931. return ret;
  932. }
  933. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  934. {
  935. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  936. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  937. return -EINVAL;
  938. }
  939. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  940. &plat_priv->cal_file_size);
  941. }
  942. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  943. u32 *cal_file_size)
  944. {
  945. /* To download pass the total size of cal DB mem allocated.
  946. * After cal file is download to mem, its size is updated in
  947. * return pointer
  948. */
  949. *cal_file_size = plat_priv->cal_mem->size;
  950. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  951. cal_file_size);
  952. }
  953. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  954. {
  955. int ret = 0;
  956. u32 cal_file_size = 0;
  957. if (!plat_priv)
  958. return -ENODEV;
  959. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  960. cnss_pr_err("Reboot is in progress, ignore FW ready\n");
  961. return -EINVAL;
  962. }
  963. cnss_pr_dbg("Processing FW Init Done..\n");
  964. del_timer(&plat_priv->fw_boot_timer);
  965. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  966. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  967. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  968. cnss_send_subsys_restart_level_msg(plat_priv);
  969. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  970. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  971. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  972. }
  973. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  974. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  975. CNSS_WALTEST);
  976. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  977. cnss_request_antenna_sharing(plat_priv);
  978. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  979. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  980. plat_priv->cal_time = jiffies;
  981. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  982. CNSS_CALIBRATION);
  983. } else {
  984. ret = cnss_setup_dms_mac(plat_priv);
  985. ret = cnss_bus_call_driver_probe(plat_priv);
  986. }
  987. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  988. goto out;
  989. else if (ret)
  990. goto shutdown;
  991. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  992. return 0;
  993. shutdown:
  994. cnss_bus_dev_shutdown(plat_priv);
  995. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  996. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  997. out:
  998. return ret;
  999. }
  1000. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  1001. {
  1002. switch (type) {
  1003. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1004. return "SERVER_ARRIVE";
  1005. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1006. return "SERVER_EXIT";
  1007. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1008. return "REQUEST_MEM";
  1009. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1010. return "FW_MEM_READY";
  1011. case CNSS_DRIVER_EVENT_FW_READY:
  1012. return "FW_READY";
  1013. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1014. return "COLD_BOOT_CAL_START";
  1015. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1016. return "COLD_BOOT_CAL_DONE";
  1017. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1018. return "REGISTER_DRIVER";
  1019. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1020. return "UNREGISTER_DRIVER";
  1021. case CNSS_DRIVER_EVENT_RECOVERY:
  1022. return "RECOVERY";
  1023. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1024. return "FORCE_FW_ASSERT";
  1025. case CNSS_DRIVER_EVENT_POWER_UP:
  1026. return "POWER_UP";
  1027. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1028. return "POWER_DOWN";
  1029. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1030. return "IDLE_RESTART";
  1031. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1032. return "IDLE_SHUTDOWN";
  1033. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1034. return "IMS_WFC_CALL_IND";
  1035. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1036. return "WLFW_TWC_CFG_IND";
  1037. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1038. return "QDSS_TRACE_REQ_MEM";
  1039. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1040. return "FW_MEM_FILE_SAVE";
  1041. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1042. return "QDSS_TRACE_FREE";
  1043. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1044. return "QDSS_TRACE_REQ_DATA";
  1045. case CNSS_DRIVER_EVENT_MAX:
  1046. return "EVENT_MAX";
  1047. }
  1048. return "UNKNOWN";
  1049. };
  1050. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  1051. enum cnss_driver_event_type type,
  1052. u32 flags, void *data)
  1053. {
  1054. struct cnss_driver_event *event;
  1055. unsigned long irq_flags;
  1056. int gfp = GFP_KERNEL;
  1057. int ret = 0;
  1058. if (!plat_priv)
  1059. return -ENODEV;
  1060. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  1061. cnss_driver_event_to_str(type), type,
  1062. flags ? "-sync" : "", plat_priv->driver_state, flags);
  1063. if (type >= CNSS_DRIVER_EVENT_MAX) {
  1064. cnss_pr_err("Invalid Event type: %d, can't post", type);
  1065. return -EINVAL;
  1066. }
  1067. if (in_interrupt() || irqs_disabled())
  1068. gfp = GFP_ATOMIC;
  1069. event = kzalloc(sizeof(*event), gfp);
  1070. if (!event)
  1071. return -ENOMEM;
  1072. cnss_pm_stay_awake(plat_priv);
  1073. event->type = type;
  1074. event->data = data;
  1075. init_completion(&event->complete);
  1076. event->ret = CNSS_EVENT_PENDING;
  1077. event->sync = !!(flags & CNSS_EVENT_SYNC);
  1078. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  1079. list_add_tail(&event->list, &plat_priv->event_list);
  1080. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  1081. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  1082. if (!(flags & CNSS_EVENT_SYNC))
  1083. goto out;
  1084. if (flags & CNSS_EVENT_UNKILLABLE)
  1085. wait_for_completion(&event->complete);
  1086. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  1087. ret = wait_for_completion_killable(&event->complete);
  1088. else
  1089. ret = wait_for_completion_interruptible(&event->complete);
  1090. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  1091. cnss_driver_event_to_str(type), type,
  1092. plat_priv->driver_state, ret, event->ret);
  1093. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  1094. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  1095. event->sync = false;
  1096. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  1097. ret = -EINTR;
  1098. goto out;
  1099. }
  1100. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  1101. ret = event->ret;
  1102. kfree(event);
  1103. out:
  1104. cnss_pm_relax(plat_priv);
  1105. return ret;
  1106. }
  1107. /**
  1108. * cnss_get_timeout - Get timeout for corresponding type.
  1109. * @plat_priv: Pointer to platform driver context.
  1110. * @cnss_timeout_type: Timeout type.
  1111. *
  1112. * Return: Timeout in milliseconds.
  1113. */
  1114. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  1115. enum cnss_timeout_type timeout_type)
  1116. {
  1117. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  1118. switch (timeout_type) {
  1119. case CNSS_TIMEOUT_QMI:
  1120. return qmi_timeout;
  1121. case CNSS_TIMEOUT_POWER_UP:
  1122. return (qmi_timeout << 2);
  1123. case CNSS_TIMEOUT_IDLE_RESTART:
  1124. /* In idle restart power up sequence, we have fw_boot_timer to
  1125. * handle FW initialization failure.
  1126. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  1127. * account for FW dump collection and FW re-initialization on
  1128. * retry.
  1129. */
  1130. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  1131. case CNSS_TIMEOUT_CALIBRATION:
  1132. /* Similar to mission mode, in CBC if FW init fails
  1133. * fw recovery is tried. Thus return 2x the CBC timeout.
  1134. */
  1135. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  1136. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  1137. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  1138. case CNSS_TIMEOUT_RDDM:
  1139. return CNSS_RDDM_TIMEOUT_MS;
  1140. case CNSS_TIMEOUT_RECOVERY:
  1141. return RECOVERY_TIMEOUT;
  1142. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  1143. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  1144. default:
  1145. return qmi_timeout;
  1146. }
  1147. }
  1148. unsigned int cnss_get_boot_timeout(struct device *dev)
  1149. {
  1150. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1151. if (!plat_priv) {
  1152. cnss_pr_err("plat_priv is NULL\n");
  1153. return 0;
  1154. }
  1155. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  1156. }
  1157. EXPORT_SYMBOL(cnss_get_boot_timeout);
  1158. int cnss_power_up(struct device *dev)
  1159. {
  1160. int ret = 0;
  1161. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1162. unsigned int timeout;
  1163. if (!plat_priv) {
  1164. cnss_pr_err("plat_priv is NULL\n");
  1165. return -ENODEV;
  1166. }
  1167. cnss_pr_dbg("Powering up device\n");
  1168. ret = cnss_driver_event_post(plat_priv,
  1169. CNSS_DRIVER_EVENT_POWER_UP,
  1170. CNSS_EVENT_SYNC, NULL);
  1171. if (ret)
  1172. goto out;
  1173. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1174. goto out;
  1175. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  1176. reinit_completion(&plat_priv->power_up_complete);
  1177. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  1178. msecs_to_jiffies(timeout));
  1179. if (!ret) {
  1180. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  1181. timeout);
  1182. ret = -EAGAIN;
  1183. goto out;
  1184. }
  1185. return 0;
  1186. out:
  1187. return ret;
  1188. }
  1189. EXPORT_SYMBOL(cnss_power_up);
  1190. int cnss_power_down(struct device *dev)
  1191. {
  1192. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1193. if (!plat_priv) {
  1194. cnss_pr_err("plat_priv is NULL\n");
  1195. return -ENODEV;
  1196. }
  1197. cnss_pr_dbg("Powering down device\n");
  1198. return cnss_driver_event_post(plat_priv,
  1199. CNSS_DRIVER_EVENT_POWER_DOWN,
  1200. CNSS_EVENT_SYNC, NULL);
  1201. }
  1202. EXPORT_SYMBOL(cnss_power_down);
  1203. int cnss_idle_restart(struct device *dev)
  1204. {
  1205. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1206. unsigned int timeout;
  1207. int ret = 0;
  1208. if (!plat_priv) {
  1209. cnss_pr_err("plat_priv is NULL\n");
  1210. return -ENODEV;
  1211. }
  1212. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  1213. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  1214. return -EBUSY;
  1215. }
  1216. cnss_pr_dbg("Doing idle restart\n");
  1217. reinit_completion(&plat_priv->power_up_complete);
  1218. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1219. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  1220. ret = -EINVAL;
  1221. goto out;
  1222. }
  1223. ret = cnss_driver_event_post(plat_priv,
  1224. CNSS_DRIVER_EVENT_IDLE_RESTART,
  1225. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  1226. if (ret == -EINTR && plat_priv->device_id != QCA6174_DEVICE_ID)
  1227. cnss_pr_err("Idle restart has been interrupted but device power up is still in progress");
  1228. else if (ret)
  1229. goto out;
  1230. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1231. ret = cnss_bus_call_driver_probe(plat_priv);
  1232. goto out;
  1233. }
  1234. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  1235. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  1236. msecs_to_jiffies(timeout));
  1237. if (plat_priv->power_up_error) {
  1238. ret = plat_priv->power_up_error;
  1239. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1240. cnss_pr_dbg("Power up error:%d, exiting\n",
  1241. plat_priv->power_up_error);
  1242. goto out;
  1243. }
  1244. if (!ret) {
  1245. /* This exception occurs after attempting retry of FW recovery.
  1246. * Thus we can safely power off the device.
  1247. */
  1248. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  1249. timeout);
  1250. ret = -ETIMEDOUT;
  1251. cnss_power_down(dev);
  1252. CNSS_ASSERT(0);
  1253. goto out;
  1254. }
  1255. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1256. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  1257. del_timer(&plat_priv->fw_boot_timer);
  1258. ret = -EINVAL;
  1259. goto out;
  1260. }
  1261. /* In non-DRV mode, remove MHI satellite configuration. Switching to
  1262. * non-DRV is supported only once after device reboots and before wifi
  1263. * is turned on. We do not allow switching back to DRV.
  1264. * To bring device back into DRV, user needs to reboot device.
  1265. */
  1266. if (test_bit(DISABLE_DRV, &plat_priv->ctrl_params.quirks)) {
  1267. cnss_pr_dbg("DRV is disabled\n");
  1268. cnss_bus_disable_mhi_satellite_cfg(plat_priv);
  1269. }
  1270. mutex_unlock(&plat_priv->driver_ops_lock);
  1271. return 0;
  1272. out:
  1273. mutex_unlock(&plat_priv->driver_ops_lock);
  1274. return ret;
  1275. }
  1276. EXPORT_SYMBOL(cnss_idle_restart);
  1277. int cnss_idle_shutdown(struct device *dev)
  1278. {
  1279. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1280. if (!plat_priv) {
  1281. cnss_pr_err("plat_priv is NULL\n");
  1282. return -ENODEV;
  1283. }
  1284. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  1285. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  1286. return -EAGAIN;
  1287. }
  1288. cnss_pr_dbg("Doing idle shutdown\n");
  1289. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) ||
  1290. test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) {
  1291. cnss_pr_dbg("Recovery in progress. Ignore IDLE Shutdown\n");
  1292. return -EBUSY;
  1293. }
  1294. return cnss_driver_event_post(plat_priv,
  1295. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  1296. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  1297. }
  1298. EXPORT_SYMBOL(cnss_idle_shutdown);
  1299. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  1300. {
  1301. int ret = 0;
  1302. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1303. if (ret < 0) {
  1304. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  1305. goto out;
  1306. }
  1307. ret = cnss_get_clk(plat_priv);
  1308. if (ret) {
  1309. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  1310. goto put_vreg;
  1311. }
  1312. ret = cnss_get_pinctrl(plat_priv);
  1313. if (ret) {
  1314. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  1315. goto put_clk;
  1316. }
  1317. return 0;
  1318. put_clk:
  1319. cnss_put_clk(plat_priv);
  1320. put_vreg:
  1321. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1322. out:
  1323. return ret;
  1324. }
  1325. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  1326. {
  1327. cnss_put_clk(plat_priv);
  1328. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1329. }
  1330. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1331. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  1332. unsigned long code,
  1333. void *ss_handle)
  1334. {
  1335. struct cnss_plat_data *plat_priv =
  1336. container_of(nb, struct cnss_plat_data, modem_nb);
  1337. struct cnss_esoc_info *esoc_info;
  1338. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  1339. if (!plat_priv)
  1340. return NOTIFY_DONE;
  1341. esoc_info = &plat_priv->esoc_info;
  1342. if (code == SUBSYS_AFTER_POWERUP)
  1343. esoc_info->modem_current_status = 1;
  1344. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  1345. esoc_info->modem_current_status = 0;
  1346. else
  1347. return NOTIFY_DONE;
  1348. if (!cnss_bus_call_driver_modem_status(plat_priv,
  1349. esoc_info->modem_current_status))
  1350. return NOTIFY_DONE;
  1351. return NOTIFY_OK;
  1352. }
  1353. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1354. {
  1355. int ret = 0;
  1356. struct device *dev;
  1357. struct cnss_esoc_info *esoc_info;
  1358. struct esoc_desc *esoc_desc;
  1359. const char *client_desc;
  1360. dev = &plat_priv->plat_dev->dev;
  1361. esoc_info = &plat_priv->esoc_info;
  1362. esoc_info->notify_modem_status =
  1363. of_property_read_bool(dev->of_node,
  1364. "qcom,notify-modem-status");
  1365. if (!esoc_info->notify_modem_status)
  1366. goto out;
  1367. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  1368. &client_desc);
  1369. if (ret) {
  1370. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  1371. } else {
  1372. esoc_desc = devm_register_esoc_client(dev, client_desc);
  1373. if (IS_ERR_OR_NULL(esoc_desc)) {
  1374. ret = PTR_RET(esoc_desc);
  1375. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  1376. ret);
  1377. goto out;
  1378. }
  1379. esoc_info->esoc_desc = esoc_desc;
  1380. }
  1381. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  1382. esoc_info->modem_current_status = 0;
  1383. esoc_info->modem_notify_handler =
  1384. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  1385. esoc_info->esoc_desc->name :
  1386. "modem", &plat_priv->modem_nb);
  1387. if (IS_ERR(esoc_info->modem_notify_handler)) {
  1388. ret = PTR_ERR(esoc_info->modem_notify_handler);
  1389. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  1390. ret);
  1391. goto unreg_esoc;
  1392. }
  1393. return 0;
  1394. unreg_esoc:
  1395. if (esoc_info->esoc_desc)
  1396. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1397. out:
  1398. return ret;
  1399. }
  1400. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1401. {
  1402. struct device *dev;
  1403. struct cnss_esoc_info *esoc_info;
  1404. dev = &plat_priv->plat_dev->dev;
  1405. esoc_info = &plat_priv->esoc_info;
  1406. if (esoc_info->notify_modem_status)
  1407. subsys_notif_unregister_notifier
  1408. (esoc_info->modem_notify_handler,
  1409. &plat_priv->modem_nb);
  1410. if (esoc_info->esoc_desc)
  1411. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1412. }
  1413. #else
  1414. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1415. {
  1416. return 0;
  1417. }
  1418. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1419. #endif
  1420. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1421. {
  1422. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1423. int ret = 0;
  1424. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1425. return 0;
  1426. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1427. if (ret)
  1428. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1429. ret);
  1430. return ret;
  1431. }
  1432. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1433. {
  1434. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1435. int ret = 0;
  1436. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1437. return 0;
  1438. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1439. if (ret)
  1440. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1441. ret);
  1442. return ret;
  1443. }
  1444. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1445. {
  1446. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1447. if (sol_gpio->dev_sol_gpio < 0)
  1448. return -EINVAL;
  1449. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1450. }
  1451. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1452. {
  1453. struct cnss_plat_data *plat_priv = data;
  1454. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1455. if (test_bit(CNSS_POWER_OFF, &plat_priv->driver_state)) {
  1456. cnss_pr_dbg("Ignore Dev SOL during device power off");
  1457. return IRQ_HANDLED;
  1458. }
  1459. sol_gpio->dev_sol_counter++;
  1460. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u, dev_sol_val: %d\n",
  1461. irq, sol_gpio->dev_sol_counter,
  1462. cnss_get_dev_sol_value(plat_priv));
  1463. /* Make sure abort current suspend */
  1464. cnss_pm_stay_awake(plat_priv);
  1465. cnss_pm_relax(plat_priv);
  1466. pm_system_wakeup();
  1467. cnss_bus_handle_dev_sol_irq(plat_priv);
  1468. return IRQ_HANDLED;
  1469. }
  1470. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1471. {
  1472. struct device *dev = &plat_priv->plat_dev->dev;
  1473. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1474. int ret = 0;
  1475. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1476. "wlan-dev-sol-gpio", 0);
  1477. if (sol_gpio->dev_sol_gpio < 0)
  1478. goto out;
  1479. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1480. sol_gpio->dev_sol_gpio);
  1481. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1482. if (ret) {
  1483. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1484. ret);
  1485. goto out;
  1486. }
  1487. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1488. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1489. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1490. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1491. if (ret) {
  1492. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1493. goto free_gpio;
  1494. }
  1495. return 0;
  1496. free_gpio:
  1497. gpio_free(sol_gpio->dev_sol_gpio);
  1498. out:
  1499. return ret;
  1500. }
  1501. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1502. {
  1503. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1504. if (sol_gpio->dev_sol_gpio < 0)
  1505. return;
  1506. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1507. gpio_free(sol_gpio->dev_sol_gpio);
  1508. }
  1509. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1510. {
  1511. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1512. if (sol_gpio->host_sol_gpio < 0)
  1513. return -EINVAL;
  1514. if (value)
  1515. cnss_pr_dbg("Assert host SOL GPIO\n");
  1516. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1517. return 0;
  1518. }
  1519. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1520. {
  1521. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1522. if (sol_gpio->host_sol_gpio < 0)
  1523. return -EINVAL;
  1524. return gpio_get_value(sol_gpio->host_sol_gpio);
  1525. }
  1526. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1527. {
  1528. struct device *dev = &plat_priv->plat_dev->dev;
  1529. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1530. int ret = 0;
  1531. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1532. "wlan-host-sol-gpio", 0);
  1533. if (sol_gpio->host_sol_gpio < 0)
  1534. goto out;
  1535. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1536. sol_gpio->host_sol_gpio);
  1537. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1538. if (ret) {
  1539. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1540. ret);
  1541. goto out;
  1542. }
  1543. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1544. return 0;
  1545. out:
  1546. return ret;
  1547. }
  1548. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1549. {
  1550. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1551. if (sol_gpio->host_sol_gpio < 0)
  1552. return;
  1553. gpio_free(sol_gpio->host_sol_gpio);
  1554. }
  1555. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1556. {
  1557. int ret;
  1558. ret = cnss_init_dev_sol_gpio(plat_priv);
  1559. if (ret)
  1560. goto out;
  1561. ret = cnss_init_host_sol_gpio(plat_priv);
  1562. if (ret)
  1563. goto deinit_dev_sol;
  1564. return 0;
  1565. deinit_dev_sol:
  1566. cnss_deinit_dev_sol_gpio(plat_priv);
  1567. out:
  1568. return ret;
  1569. }
  1570. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1571. {
  1572. cnss_deinit_host_sol_gpio(plat_priv);
  1573. cnss_deinit_dev_sol_gpio(plat_priv);
  1574. }
  1575. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1576. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1577. {
  1578. struct cnss_plat_data *plat_priv;
  1579. int ret = 0;
  1580. if (!subsys_desc->dev) {
  1581. cnss_pr_err("dev from subsys_desc is NULL\n");
  1582. return -ENODEV;
  1583. }
  1584. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1585. if (!plat_priv) {
  1586. cnss_pr_err("plat_priv is NULL\n");
  1587. return -ENODEV;
  1588. }
  1589. if (!plat_priv->driver_state) {
  1590. cnss_pr_dbg("subsys powerup is ignored\n");
  1591. return 0;
  1592. }
  1593. ret = cnss_bus_dev_powerup(plat_priv);
  1594. if (ret)
  1595. __pm_relax(plat_priv->recovery_ws);
  1596. return ret;
  1597. }
  1598. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1599. bool force_stop)
  1600. {
  1601. struct cnss_plat_data *plat_priv;
  1602. if (!subsys_desc->dev) {
  1603. cnss_pr_err("dev from subsys_desc is NULL\n");
  1604. return -ENODEV;
  1605. }
  1606. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1607. if (!plat_priv) {
  1608. cnss_pr_err("plat_priv is NULL\n");
  1609. return -ENODEV;
  1610. }
  1611. if (!plat_priv->driver_state) {
  1612. cnss_pr_dbg("subsys shutdown is ignored\n");
  1613. return 0;
  1614. }
  1615. return cnss_bus_dev_shutdown(plat_priv);
  1616. }
  1617. void cnss_device_crashed(struct device *dev)
  1618. {
  1619. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1620. struct cnss_subsys_info *subsys_info;
  1621. if (!plat_priv)
  1622. return;
  1623. subsys_info = &plat_priv->subsys_info;
  1624. if (subsys_info->subsys_device) {
  1625. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1626. subsys_set_crash_status(subsys_info->subsys_device, true);
  1627. subsystem_restart_dev(subsys_info->subsys_device);
  1628. }
  1629. }
  1630. EXPORT_SYMBOL(cnss_device_crashed);
  1631. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1632. {
  1633. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1634. if (!plat_priv) {
  1635. cnss_pr_err("plat_priv is NULL\n");
  1636. return;
  1637. }
  1638. cnss_bus_dev_crash_shutdown(plat_priv);
  1639. }
  1640. static int cnss_subsys_ramdump(int enable,
  1641. const struct subsys_desc *subsys_desc)
  1642. {
  1643. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1644. if (!plat_priv) {
  1645. cnss_pr_err("plat_priv is NULL\n");
  1646. return -ENODEV;
  1647. }
  1648. if (!enable)
  1649. return 0;
  1650. return cnss_bus_dev_ramdump(plat_priv);
  1651. }
  1652. static void cnss_recovery_work_handler(struct work_struct *work)
  1653. {
  1654. }
  1655. #else
  1656. void cnss_recovery_handler(struct cnss_plat_data *plat_priv)
  1657. {
  1658. int ret;
  1659. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1660. if (!plat_priv->recovery_enabled)
  1661. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1662. cnss_bus_dev_shutdown(plat_priv);
  1663. cnss_bus_dev_ramdump(plat_priv);
  1664. /* If recovery is triggered before Host driver registration,
  1665. * avoid device power up because eventually device will be
  1666. * power up as part of driver registration.
  1667. */
  1668. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state) ||
  1669. !test_bit(CNSS_DRIVER_REGISTERED, &plat_priv->driver_state)) {
  1670. cnss_pr_dbg("Host driver not registered yet, ignore Device Power Up, 0x%lx\n",
  1671. plat_priv->driver_state);
  1672. return;
  1673. }
  1674. msleep(POWER_RESET_MIN_DELAY_MS);
  1675. ret = cnss_bus_dev_powerup(plat_priv);
  1676. if (ret) {
  1677. __pm_relax(plat_priv->recovery_ws);
  1678. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1679. }
  1680. return;
  1681. }
  1682. static void cnss_recovery_work_handler(struct work_struct *work)
  1683. {
  1684. struct cnss_plat_data *plat_priv =
  1685. container_of(work, struct cnss_plat_data, recovery_work);
  1686. cnss_recovery_handler(plat_priv);
  1687. }
  1688. void cnss_device_crashed(struct device *dev)
  1689. {
  1690. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1691. if (!plat_priv)
  1692. return;
  1693. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1694. schedule_work(&plat_priv->recovery_work);
  1695. }
  1696. EXPORT_SYMBOL(cnss_device_crashed);
  1697. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1698. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1699. {
  1700. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1701. struct cnss_ramdump_info *ramdump_info;
  1702. if (!plat_priv)
  1703. return NULL;
  1704. ramdump_info = &plat_priv->ramdump_info;
  1705. *size = ramdump_info->ramdump_size;
  1706. return ramdump_info->ramdump_va;
  1707. }
  1708. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1709. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1710. {
  1711. switch (reason) {
  1712. case CNSS_REASON_DEFAULT:
  1713. return "DEFAULT";
  1714. case CNSS_REASON_LINK_DOWN:
  1715. return "LINK_DOWN";
  1716. case CNSS_REASON_RDDM:
  1717. return "RDDM";
  1718. case CNSS_REASON_TIMEOUT:
  1719. return "TIMEOUT";
  1720. }
  1721. return "UNKNOWN";
  1722. };
  1723. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1724. enum cnss_recovery_reason reason)
  1725. {
  1726. int ret;
  1727. plat_priv->recovery_count++;
  1728. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1729. goto self_recovery;
  1730. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1731. cnss_pr_dbg("Skip device recovery\n");
  1732. return 0;
  1733. }
  1734. /* FW recovery sequence has multiple steps and firmware load requires
  1735. * linux PM in awake state. Thus hold the cnss wake source until
  1736. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1737. * time taken in this process.
  1738. */
  1739. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1740. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1741. true);
  1742. switch (reason) {
  1743. case CNSS_REASON_LINK_DOWN:
  1744. if (!cnss_bus_check_link_status(plat_priv)) {
  1745. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1746. return 0;
  1747. }
  1748. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1749. &plat_priv->ctrl_params.quirks))
  1750. goto self_recovery;
  1751. if (!cnss_bus_recover_link_down(plat_priv)) {
  1752. /* clear recovery bit here to avoid skipping
  1753. * the recovery work for RDDM later
  1754. */
  1755. clear_bit(CNSS_DRIVER_RECOVERY,
  1756. &plat_priv->driver_state);
  1757. return 0;
  1758. }
  1759. break;
  1760. case CNSS_REASON_RDDM:
  1761. cnss_bus_collect_dump_info(plat_priv, false);
  1762. break;
  1763. case CNSS_REASON_DEFAULT:
  1764. case CNSS_REASON_TIMEOUT:
  1765. break;
  1766. default:
  1767. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1768. cnss_recovery_reason_to_str(reason), reason);
  1769. break;
  1770. }
  1771. cnss_bus_device_crashed(plat_priv);
  1772. return 0;
  1773. self_recovery:
  1774. cnss_pr_dbg("Going for self recovery\n");
  1775. cnss_bus_dev_shutdown(plat_priv);
  1776. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1777. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1778. &plat_priv->ctrl_params.quirks);
  1779. /* If link down self recovery is triggered before Host driver
  1780. * registration, avoid device power up because eventually device
  1781. * will be power up as part of driver registration.
  1782. */
  1783. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state) ||
  1784. !test_bit(CNSS_DRIVER_REGISTERED, &plat_priv->driver_state)) {
  1785. cnss_pr_dbg("Host driver not registered yet, ignore Device Power Up, 0x%lx\n",
  1786. plat_priv->driver_state);
  1787. return 0;
  1788. }
  1789. ret = cnss_bus_dev_powerup(plat_priv);
  1790. if (ret)
  1791. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1792. return 0;
  1793. }
  1794. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1795. void *data)
  1796. {
  1797. struct cnss_recovery_data *recovery_data = data;
  1798. int ret = 0;
  1799. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1800. cnss_recovery_reason_to_str(recovery_data->reason),
  1801. recovery_data->reason);
  1802. if (!plat_priv->driver_state) {
  1803. cnss_pr_err("Improper driver state, ignore recovery\n");
  1804. ret = -EINVAL;
  1805. goto out;
  1806. }
  1807. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1808. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1809. ret = -EINVAL;
  1810. goto out;
  1811. }
  1812. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1813. cnss_pr_err("Recovery is already in progress\n");
  1814. CNSS_ASSERT(0);
  1815. ret = -EINVAL;
  1816. goto out;
  1817. }
  1818. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1819. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1820. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1821. ret = -EINVAL;
  1822. goto out;
  1823. }
  1824. switch (plat_priv->device_id) {
  1825. case QCA6174_DEVICE_ID:
  1826. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1827. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1828. &plat_priv->driver_state)) {
  1829. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1830. ret = -EINVAL;
  1831. goto out;
  1832. }
  1833. break;
  1834. default:
  1835. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1836. set_bit(CNSS_FW_BOOT_RECOVERY,
  1837. &plat_priv->driver_state);
  1838. }
  1839. break;
  1840. }
  1841. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1842. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1843. out:
  1844. kfree(data);
  1845. return ret;
  1846. }
  1847. int cnss_self_recovery(struct device *dev,
  1848. enum cnss_recovery_reason reason)
  1849. {
  1850. cnss_schedule_recovery(dev, reason);
  1851. return 0;
  1852. }
  1853. EXPORT_SYMBOL(cnss_self_recovery);
  1854. void cnss_schedule_recovery(struct device *dev,
  1855. enum cnss_recovery_reason reason)
  1856. {
  1857. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1858. struct cnss_recovery_data *data;
  1859. int gfp = GFP_KERNEL;
  1860. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1861. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1862. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1863. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1864. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1865. return;
  1866. }
  1867. if (in_interrupt() || irqs_disabled())
  1868. gfp = GFP_ATOMIC;
  1869. data = kzalloc(sizeof(*data), gfp);
  1870. if (!data)
  1871. return;
  1872. data->reason = reason;
  1873. cnss_driver_event_post(plat_priv,
  1874. CNSS_DRIVER_EVENT_RECOVERY,
  1875. 0, data);
  1876. }
  1877. EXPORT_SYMBOL(cnss_schedule_recovery);
  1878. int cnss_force_fw_assert(struct device *dev)
  1879. {
  1880. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1881. if (!plat_priv) {
  1882. cnss_pr_err("plat_priv is NULL\n");
  1883. return -ENODEV;
  1884. }
  1885. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1886. cnss_pr_info("Forced FW assert is not supported\n");
  1887. return -EOPNOTSUPP;
  1888. }
  1889. if (cnss_bus_is_device_down(plat_priv)) {
  1890. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1891. return 0;
  1892. }
  1893. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1894. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1895. return 0;
  1896. }
  1897. if (in_interrupt() || irqs_disabled())
  1898. cnss_driver_event_post(plat_priv,
  1899. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1900. 0, NULL);
  1901. else
  1902. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1903. return 0;
  1904. }
  1905. EXPORT_SYMBOL(cnss_force_fw_assert);
  1906. int cnss_force_collect_rddm(struct device *dev)
  1907. {
  1908. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1909. unsigned int timeout;
  1910. int ret = 0;
  1911. if (!plat_priv) {
  1912. cnss_pr_err("plat_priv is NULL\n");
  1913. return -ENODEV;
  1914. }
  1915. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1916. cnss_pr_info("Force collect rddm is not supported\n");
  1917. return -EOPNOTSUPP;
  1918. }
  1919. if (cnss_bus_is_device_down(plat_priv)) {
  1920. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1921. goto wait_rddm;
  1922. }
  1923. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1924. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1925. goto wait_rddm;
  1926. }
  1927. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1928. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1929. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1930. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1931. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1932. return 0;
  1933. }
  1934. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1935. if (ret)
  1936. return ret;
  1937. wait_rddm:
  1938. reinit_completion(&plat_priv->rddm_complete);
  1939. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  1940. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  1941. msecs_to_jiffies(timeout));
  1942. if (!ret) {
  1943. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  1944. timeout);
  1945. ret = -ETIMEDOUT;
  1946. } else if (ret > 0) {
  1947. ret = 0;
  1948. }
  1949. return ret;
  1950. }
  1951. EXPORT_SYMBOL(cnss_force_collect_rddm);
  1952. int cnss_qmi_send_get(struct device *dev)
  1953. {
  1954. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1955. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1956. return 0;
  1957. return cnss_bus_qmi_send_get(plat_priv);
  1958. }
  1959. EXPORT_SYMBOL(cnss_qmi_send_get);
  1960. int cnss_qmi_send_put(struct device *dev)
  1961. {
  1962. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1963. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1964. return 0;
  1965. return cnss_bus_qmi_send_put(plat_priv);
  1966. }
  1967. EXPORT_SYMBOL(cnss_qmi_send_put);
  1968. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  1969. int cmd_len, void *cb_ctx,
  1970. int (*cb)(void *ctx, void *event, int event_len))
  1971. {
  1972. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1973. int ret;
  1974. if (!plat_priv)
  1975. return -ENODEV;
  1976. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1977. return -EINVAL;
  1978. plat_priv->get_info_cb = cb;
  1979. plat_priv->get_info_cb_ctx = cb_ctx;
  1980. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  1981. if (ret) {
  1982. plat_priv->get_info_cb = NULL;
  1983. plat_priv->get_info_cb_ctx = NULL;
  1984. }
  1985. return ret;
  1986. }
  1987. EXPORT_SYMBOL(cnss_qmi_send);
  1988. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  1989. {
  1990. int ret = 0;
  1991. u32 retry = 0, timeout;
  1992. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  1993. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  1994. goto out;
  1995. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1996. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  1997. goto out;
  1998. } else if (test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  1999. cnss_pr_dbg("Calibration deferred as WLAN device disabled\n");
  2000. goto out;
  2001. }
  2002. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  2003. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  2004. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2005. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  2006. CNSS_ASSERT(0);
  2007. return -EINVAL;
  2008. }
  2009. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  2010. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  2011. break;
  2012. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  2013. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  2014. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  2015. CNSS_ASSERT(0);
  2016. ret = -EINVAL;
  2017. goto mark_cal_fail;
  2018. }
  2019. }
  2020. switch (plat_priv->device_id) {
  2021. case QCA6290_DEVICE_ID:
  2022. case QCA6390_DEVICE_ID:
  2023. case QCA6490_DEVICE_ID:
  2024. case KIWI_DEVICE_ID:
  2025. case MANGO_DEVICE_ID:
  2026. case PEACH_DEVICE_ID:
  2027. break;
  2028. default:
  2029. cnss_pr_err("Not supported for device ID 0x%lx\n",
  2030. plat_priv->device_id);
  2031. ret = -EINVAL;
  2032. goto mark_cal_fail;
  2033. }
  2034. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  2035. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  2036. timeout = cnss_get_timeout(plat_priv,
  2037. CNSS_TIMEOUT_CALIBRATION);
  2038. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  2039. timeout / 1000);
  2040. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  2041. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  2042. msecs_to_jiffies(timeout));
  2043. }
  2044. reinit_completion(&plat_priv->cal_complete);
  2045. ret = cnss_bus_dev_powerup(plat_priv);
  2046. mark_cal_fail:
  2047. if (ret) {
  2048. complete(&plat_priv->cal_complete);
  2049. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  2050. /* Set CBC done in driver state to mark attempt and note error
  2051. * since calibration cannot be retried at boot.
  2052. */
  2053. plat_priv->cal_done = CNSS_CAL_FAILURE;
  2054. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  2055. if (plat_priv->device_id == QCA6174_DEVICE_ID ||
  2056. plat_priv->device_id == QCN7605_DEVICE_ID) {
  2057. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  2058. goto out;
  2059. cnss_pr_info("Schedule WLAN driver load\n");
  2060. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  2061. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  2062. 0);
  2063. }
  2064. }
  2065. out:
  2066. return ret;
  2067. }
  2068. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  2069. void *data)
  2070. {
  2071. struct cnss_cal_info *cal_info = data;
  2072. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  2073. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  2074. goto out;
  2075. switch (cal_info->cal_status) {
  2076. case CNSS_CAL_DONE:
  2077. cnss_pr_dbg("Calibration completed successfully\n");
  2078. plat_priv->cal_done = true;
  2079. break;
  2080. case CNSS_CAL_TIMEOUT:
  2081. case CNSS_CAL_FAILURE:
  2082. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  2083. cal_info->cal_status);
  2084. break;
  2085. default:
  2086. cnss_pr_err("Unknown calibration status: %u\n",
  2087. cal_info->cal_status);
  2088. break;
  2089. }
  2090. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  2091. cnss_bus_free_qdss_mem(plat_priv);
  2092. cnss_release_antenna_sharing(plat_priv);
  2093. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  2094. goto skip_shutdown;
  2095. cnss_bus_dev_shutdown(plat_priv);
  2096. msleep(POWER_RESET_MIN_DELAY_MS);
  2097. skip_shutdown:
  2098. complete(&plat_priv->cal_complete);
  2099. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  2100. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  2101. if (cal_info->cal_status == CNSS_CAL_DONE) {
  2102. cnss_cal_mem_upload_to_file(plat_priv);
  2103. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  2104. goto out;
  2105. cnss_pr_dbg("Schedule WLAN driver load\n");
  2106. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  2107. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  2108. 0);
  2109. }
  2110. out:
  2111. kfree(data);
  2112. return 0;
  2113. }
  2114. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  2115. {
  2116. int ret;
  2117. ret = cnss_bus_dev_powerup(plat_priv);
  2118. if (ret)
  2119. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  2120. return ret;
  2121. }
  2122. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  2123. {
  2124. cnss_bus_dev_shutdown(plat_priv);
  2125. return 0;
  2126. }
  2127. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  2128. {
  2129. int ret = 0;
  2130. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  2131. if (ret < 0)
  2132. return ret;
  2133. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  2134. }
  2135. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  2136. u32 mem_seg_len, u64 pa, u32 size)
  2137. {
  2138. int i = 0;
  2139. u64 offset = 0;
  2140. void *va = NULL;
  2141. u64 local_pa;
  2142. u32 local_size;
  2143. for (i = 0; i < mem_seg_len; i++) {
  2144. if (i == QMI_WLFW_MEM_LPASS_SHARED_V01)
  2145. continue;
  2146. local_pa = (u64)fw_mem[i].pa;
  2147. local_size = (u32)fw_mem[i].size;
  2148. if (pa == local_pa && size <= local_size) {
  2149. va = fw_mem[i].va;
  2150. break;
  2151. }
  2152. if (pa > local_pa &&
  2153. pa < local_pa + local_size &&
  2154. pa + size <= local_pa + local_size) {
  2155. offset = pa - local_pa;
  2156. va = fw_mem[i].va + offset;
  2157. break;
  2158. }
  2159. }
  2160. return va;
  2161. }
  2162. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  2163. void *data)
  2164. {
  2165. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  2166. struct cnss_fw_mem *fw_mem_seg;
  2167. int ret = 0L;
  2168. void *va = NULL;
  2169. u32 i, fw_mem_seg_len;
  2170. switch (event_data->mem_type) {
  2171. case QMI_WLFW_MEM_TYPE_DDR_V01:
  2172. if (!plat_priv->fw_mem_seg_len)
  2173. goto invalid_mem_save;
  2174. fw_mem_seg = plat_priv->fw_mem;
  2175. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  2176. break;
  2177. case QMI_WLFW_MEM_QDSS_V01:
  2178. if (!plat_priv->qdss_mem_seg_len)
  2179. goto invalid_mem_save;
  2180. fw_mem_seg = plat_priv->qdss_mem;
  2181. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  2182. break;
  2183. default:
  2184. goto invalid_mem_save;
  2185. }
  2186. for (i = 0; i < event_data->mem_seg_len; i++) {
  2187. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  2188. event_data->mem_seg[i].addr,
  2189. event_data->mem_seg[i].size);
  2190. if (!va) {
  2191. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  2192. &event_data->mem_seg[i].addr,
  2193. event_data->mem_type);
  2194. ret = -EINVAL;
  2195. break;
  2196. }
  2197. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  2198. event_data->file_name,
  2199. event_data->mem_seg[i].size);
  2200. if (ret < 0) {
  2201. cnss_pr_err("Fail to save fw mem data: %d\n",
  2202. ret);
  2203. break;
  2204. }
  2205. }
  2206. kfree(data);
  2207. return ret;
  2208. invalid_mem_save:
  2209. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  2210. event_data->mem_type);
  2211. kfree(data);
  2212. return -EINVAL;
  2213. }
  2214. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  2215. {
  2216. cnss_bus_free_qdss_mem(plat_priv);
  2217. return 0;
  2218. }
  2219. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  2220. void *data)
  2221. {
  2222. int ret = 0;
  2223. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  2224. if (!plat_priv)
  2225. return -ENODEV;
  2226. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  2227. event_data->total_size);
  2228. kfree(data);
  2229. return ret;
  2230. }
  2231. static void cnss_driver_event_work(struct work_struct *work)
  2232. {
  2233. struct cnss_plat_data *plat_priv =
  2234. container_of(work, struct cnss_plat_data, event_work);
  2235. struct cnss_driver_event *event;
  2236. unsigned long flags;
  2237. int ret = 0;
  2238. if (!plat_priv) {
  2239. cnss_pr_err("plat_priv is NULL!\n");
  2240. return;
  2241. }
  2242. cnss_pm_stay_awake(plat_priv);
  2243. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2244. while (!list_empty(&plat_priv->event_list)) {
  2245. event = list_first_entry(&plat_priv->event_list,
  2246. struct cnss_driver_event, list);
  2247. list_del(&event->list);
  2248. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2249. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  2250. cnss_driver_event_to_str(event->type),
  2251. event->sync ? "-sync" : "", event->type,
  2252. plat_priv->driver_state);
  2253. switch (event->type) {
  2254. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  2255. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  2256. break;
  2257. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  2258. ret = cnss_wlfw_server_exit(plat_priv);
  2259. break;
  2260. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  2261. ret = cnss_bus_alloc_fw_mem(plat_priv);
  2262. if (ret)
  2263. break;
  2264. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  2265. break;
  2266. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  2267. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  2268. break;
  2269. case CNSS_DRIVER_EVENT_FW_READY:
  2270. ret = cnss_fw_ready_hdlr(plat_priv);
  2271. break;
  2272. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  2273. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  2274. break;
  2275. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  2276. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  2277. event->data);
  2278. break;
  2279. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  2280. ret = cnss_bus_register_driver_hdlr(plat_priv,
  2281. event->data);
  2282. break;
  2283. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  2284. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  2285. break;
  2286. case CNSS_DRIVER_EVENT_RECOVERY:
  2287. ret = cnss_driver_recovery_hdlr(plat_priv,
  2288. event->data);
  2289. break;
  2290. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  2291. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  2292. break;
  2293. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  2294. set_bit(CNSS_DRIVER_IDLE_RESTART,
  2295. &plat_priv->driver_state);
  2296. fallthrough;
  2297. case CNSS_DRIVER_EVENT_POWER_UP:
  2298. ret = cnss_power_up_hdlr(plat_priv);
  2299. break;
  2300. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  2301. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  2302. &plat_priv->driver_state);
  2303. fallthrough;
  2304. case CNSS_DRIVER_EVENT_POWER_DOWN:
  2305. ret = cnss_power_down_hdlr(plat_priv);
  2306. break;
  2307. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  2308. ret = cnss_process_wfc_call_ind_event(plat_priv,
  2309. event->data);
  2310. break;
  2311. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  2312. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  2313. event->data);
  2314. break;
  2315. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  2316. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  2317. break;
  2318. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  2319. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  2320. event->data);
  2321. break;
  2322. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  2323. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  2324. break;
  2325. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  2326. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  2327. event->data);
  2328. break;
  2329. default:
  2330. cnss_pr_err("Invalid driver event type: %d",
  2331. event->type);
  2332. kfree(event);
  2333. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2334. continue;
  2335. }
  2336. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2337. if (event->sync) {
  2338. event->ret = ret;
  2339. complete(&event->complete);
  2340. continue;
  2341. }
  2342. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2343. kfree(event);
  2344. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2345. }
  2346. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2347. cnss_pm_relax(plat_priv);
  2348. }
  2349. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  2350. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2351. {
  2352. int ret = 0;
  2353. struct cnss_subsys_info *subsys_info;
  2354. subsys_info = &plat_priv->subsys_info;
  2355. subsys_info->subsys_desc.name = plat_priv->device_name;
  2356. subsys_info->subsys_desc.owner = THIS_MODULE;
  2357. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  2358. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  2359. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  2360. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  2361. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  2362. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  2363. if (IS_ERR(subsys_info->subsys_device)) {
  2364. ret = PTR_ERR(subsys_info->subsys_device);
  2365. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  2366. goto out;
  2367. }
  2368. subsys_info->subsys_handle =
  2369. subsystem_get(subsys_info->subsys_desc.name);
  2370. if (!subsys_info->subsys_handle) {
  2371. cnss_pr_err("Failed to get subsys_handle!\n");
  2372. ret = -EINVAL;
  2373. goto unregister_subsys;
  2374. } else if (IS_ERR(subsys_info->subsys_handle)) {
  2375. ret = PTR_ERR(subsys_info->subsys_handle);
  2376. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  2377. goto unregister_subsys;
  2378. }
  2379. return 0;
  2380. unregister_subsys:
  2381. subsys_unregister(subsys_info->subsys_device);
  2382. out:
  2383. return ret;
  2384. }
  2385. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2386. {
  2387. struct cnss_subsys_info *subsys_info;
  2388. subsys_info = &plat_priv->subsys_info;
  2389. subsystem_put(subsys_info->subsys_handle);
  2390. subsys_unregister(subsys_info->subsys_device);
  2391. }
  2392. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2393. {
  2394. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  2395. return create_ramdump_device(subsys_info->subsys_desc.name,
  2396. subsys_info->subsys_desc.dev);
  2397. }
  2398. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2399. void *ramdump_dev)
  2400. {
  2401. destroy_ramdump_device(ramdump_dev);
  2402. }
  2403. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2404. {
  2405. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2406. struct ramdump_segment segment;
  2407. memset(&segment, 0, sizeof(segment));
  2408. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  2409. segment.size = ramdump_info->ramdump_size;
  2410. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  2411. }
  2412. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2413. {
  2414. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2415. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2416. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2417. struct ramdump_segment *ramdump_segs, *s;
  2418. struct cnss_dump_meta_info meta_info = {0};
  2419. int i, ret = 0;
  2420. ramdump_segs = kcalloc(dump_data->nentries + 1,
  2421. sizeof(*ramdump_segs),
  2422. GFP_KERNEL);
  2423. if (!ramdump_segs)
  2424. return -ENOMEM;
  2425. s = ramdump_segs + 1;
  2426. for (i = 0; i < dump_data->nentries; i++) {
  2427. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2428. cnss_pr_err("Unsupported dump type: %d",
  2429. dump_seg->type);
  2430. continue;
  2431. }
  2432. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2433. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2434. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2435. }
  2436. meta_info.entry[dump_seg->type].entry_num++;
  2437. s->address = dump_seg->address;
  2438. s->v_address = (void __iomem *)dump_seg->v_address;
  2439. s->size = dump_seg->size;
  2440. s++;
  2441. dump_seg++;
  2442. }
  2443. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2444. meta_info.version = CNSS_RAMDUMP_VERSION;
  2445. meta_info.chipset = plat_priv->device_id;
  2446. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2447. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  2448. ramdump_segs->size = sizeof(meta_info);
  2449. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  2450. dump_data->nentries + 1);
  2451. kfree(ramdump_segs);
  2452. return ret;
  2453. }
  2454. #else
  2455. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  2456. void *data)
  2457. {
  2458. struct cnss_plat_data *plat_priv =
  2459. container_of(nb, struct cnss_plat_data, panic_nb);
  2460. cnss_bus_dev_crash_shutdown(plat_priv);
  2461. return NOTIFY_DONE;
  2462. }
  2463. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2464. {
  2465. int ret;
  2466. if (!plat_priv)
  2467. return -ENODEV;
  2468. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2469. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2470. &plat_priv->panic_nb);
  2471. if (ret) {
  2472. cnss_pr_err("Failed to register panic handler\n");
  2473. return -EINVAL;
  2474. }
  2475. return 0;
  2476. }
  2477. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2478. {
  2479. int ret;
  2480. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2481. &plat_priv->panic_nb);
  2482. if (ret)
  2483. cnss_pr_err("Failed to unregister panic handler\n");
  2484. }
  2485. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2486. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2487. {
  2488. return &plat_priv->plat_dev->dev;
  2489. }
  2490. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2491. void *ramdump_dev)
  2492. {
  2493. }
  2494. #endif
  2495. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2496. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2497. {
  2498. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2499. struct qcom_dump_segment segment;
  2500. struct list_head head;
  2501. INIT_LIST_HEAD(&head);
  2502. memset(&segment, 0, sizeof(segment));
  2503. segment.va = ramdump_info->ramdump_va;
  2504. segment.size = ramdump_info->ramdump_size;
  2505. list_add(&segment.node, &head);
  2506. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2507. }
  2508. #else
  2509. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2510. {
  2511. return 0;
  2512. }
  2513. /* Using completion event inside dynamically allocated ramdump_desc
  2514. * may result a race between freeing the event after setting it to
  2515. * complete inside dev coredump free callback and the thread that is
  2516. * waiting for completion.
  2517. */
  2518. DECLARE_COMPLETION(dump_done);
  2519. #define TIMEOUT_SAVE_DUMP_MS 30000
  2520. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2521. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2522. { \
  2523. if (class == ELFCLASS32) \
  2524. return sizeof(struct elf32_##__xhdr); \
  2525. else \
  2526. return sizeof(struct elf64_##__xhdr); \
  2527. }
  2528. SIZEOF_ELF_STRUCT(phdr)
  2529. SIZEOF_ELF_STRUCT(hdr)
  2530. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2531. do { \
  2532. if (class == ELFCLASS32) \
  2533. ((struct elf32_##__xhdr *)arg)->member = value; \
  2534. else \
  2535. ((struct elf64_##__xhdr *)arg)->member = value; \
  2536. } while (0)
  2537. #define set_ehdr_property(arg, class, member, value) \
  2538. set_xhdr_property(hdr, arg, class, member, value)
  2539. #define set_phdr_property(arg, class, member, value) \
  2540. set_xhdr_property(phdr, arg, class, member, value)
  2541. /* These replace qcom_ramdump driver APIs called from common API
  2542. * cnss_do_elf_dump() by the ones defined here.
  2543. */
  2544. #define qcom_dump_segment cnss_qcom_dump_segment
  2545. #define qcom_elf_dump cnss_qcom_elf_dump
  2546. #define dump_enabled cnss_dump_enabled
  2547. struct cnss_qcom_dump_segment {
  2548. struct list_head node;
  2549. dma_addr_t da;
  2550. void *va;
  2551. size_t size;
  2552. };
  2553. struct cnss_qcom_ramdump_desc {
  2554. void *data;
  2555. struct completion dump_done;
  2556. };
  2557. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2558. void *data, size_t datalen)
  2559. {
  2560. struct cnss_qcom_ramdump_desc *desc = data;
  2561. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2562. datalen);
  2563. }
  2564. static void cnss_qcom_devcd_freev(void *data)
  2565. {
  2566. struct cnss_qcom_ramdump_desc *desc = data;
  2567. cnss_pr_dbg("Free dump data for dev coredump\n");
  2568. complete(&dump_done);
  2569. vfree(desc->data);
  2570. kfree(desc);
  2571. }
  2572. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2573. gfp_t gfp)
  2574. {
  2575. struct cnss_qcom_ramdump_desc *desc;
  2576. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2577. int ret;
  2578. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2579. if (!desc)
  2580. return -ENOMEM;
  2581. desc->data = data;
  2582. reinit_completion(&dump_done);
  2583. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2584. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2585. ret = wait_for_completion_timeout(&dump_done,
  2586. msecs_to_jiffies(timeout));
  2587. if (!ret)
  2588. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2589. timeout);
  2590. return ret ? 0 : -ETIMEDOUT;
  2591. }
  2592. /* Since the elf32 and elf64 identification is identical apart from
  2593. * the class, use elf32 by default.
  2594. */
  2595. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2596. {
  2597. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2598. ehdr->e_ident[EI_CLASS] = class;
  2599. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2600. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2601. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2602. }
  2603. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2604. unsigned char class)
  2605. {
  2606. struct cnss_qcom_dump_segment *segment;
  2607. void *phdr, *ehdr;
  2608. size_t data_size, offset;
  2609. int phnum = 0;
  2610. void *data;
  2611. void __iomem *ptr;
  2612. if (!segs || list_empty(segs))
  2613. return -EINVAL;
  2614. data_size = sizeof_elf_hdr(class);
  2615. list_for_each_entry(segment, segs, node) {
  2616. data_size += sizeof_elf_phdr(class) + segment->size;
  2617. phnum++;
  2618. }
  2619. data = vmalloc(data_size);
  2620. if (!data)
  2621. return -ENOMEM;
  2622. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2623. ehdr = data;
  2624. memset(ehdr, 0, sizeof_elf_hdr(class));
  2625. init_elf_identification(ehdr, class);
  2626. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2627. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2628. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2629. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2630. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2631. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2632. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2633. phdr = data + sizeof_elf_hdr(class);
  2634. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2635. list_for_each_entry(segment, segs, node) {
  2636. memset(phdr, 0, sizeof_elf_phdr(class));
  2637. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2638. set_phdr_property(phdr, class, p_offset, offset);
  2639. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2640. set_phdr_property(phdr, class, p_paddr, segment->da);
  2641. set_phdr_property(phdr, class, p_filesz, segment->size);
  2642. set_phdr_property(phdr, class, p_memsz, segment->size);
  2643. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2644. set_phdr_property(phdr, class, p_align, 0);
  2645. if (segment->va) {
  2646. memcpy(data + offset, segment->va, segment->size);
  2647. } else {
  2648. ptr = devm_ioremap(dev, segment->da, segment->size);
  2649. if (!ptr) {
  2650. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2651. &segment->da, segment->size);
  2652. memset(data + offset, 0xff, segment->size);
  2653. } else {
  2654. memcpy_fromio(data + offset, ptr,
  2655. segment->size);
  2656. }
  2657. }
  2658. offset += segment->size;
  2659. phdr += sizeof_elf_phdr(class);
  2660. }
  2661. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2662. }
  2663. /* Saving dump to file system is always needed in this case. */
  2664. static bool cnss_dump_enabled(void)
  2665. {
  2666. return true;
  2667. }
  2668. #endif /* CONFIG_QCOM_RAMDUMP */
  2669. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2670. {
  2671. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2672. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2673. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2674. struct qcom_dump_segment *seg;
  2675. struct cnss_dump_meta_info meta_info = {0};
  2676. struct list_head head;
  2677. int i, ret = 0;
  2678. if (!dump_enabled()) {
  2679. cnss_pr_info("Dump collection is not enabled\n");
  2680. return ret;
  2681. }
  2682. INIT_LIST_HEAD(&head);
  2683. for (i = 0; i < dump_data->nentries; i++) {
  2684. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2685. cnss_pr_err("Unsupported dump type: %d",
  2686. dump_seg->type);
  2687. continue;
  2688. }
  2689. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2690. if (!seg) {
  2691. cnss_pr_err("%s: Failed to allocate mem for seg %d\n",
  2692. __func__, i);
  2693. continue;
  2694. }
  2695. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2696. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2697. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2698. }
  2699. meta_info.entry[dump_seg->type].entry_num++;
  2700. seg->da = dump_seg->address;
  2701. seg->va = dump_seg->v_address;
  2702. seg->size = dump_seg->size;
  2703. list_add_tail(&seg->node, &head);
  2704. dump_seg++;
  2705. }
  2706. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2707. if (!seg) {
  2708. cnss_pr_err("%s: Failed to allocate mem for elf ramdump seg\n",
  2709. __func__);
  2710. goto skip_elf_dump;
  2711. }
  2712. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2713. meta_info.version = CNSS_RAMDUMP_VERSION;
  2714. meta_info.chipset = plat_priv->device_id;
  2715. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2716. seg->va = &meta_info;
  2717. seg->size = sizeof(meta_info);
  2718. list_add(&seg->node, &head);
  2719. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2720. skip_elf_dump:
  2721. while (!list_empty(&head)) {
  2722. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2723. list_del(&seg->node);
  2724. kfree(seg);
  2725. }
  2726. return ret;
  2727. }
  2728. #ifdef CONFIG_CNSS2_SSR_DRIVER_DUMP
  2729. /**
  2730. * cnss_host_ramdump_dev_release() - callback function for device release
  2731. * @dev: device to be released
  2732. *
  2733. * Return: None
  2734. */
  2735. static void cnss_host_ramdump_dev_release(struct device *dev)
  2736. {
  2737. cnss_pr_dbg("free host ramdump device\n");
  2738. kfree(dev);
  2739. }
  2740. int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
  2741. struct cnss_ssr_driver_dump_entry *ssr_entry,
  2742. size_t num_entries_loaded)
  2743. {
  2744. struct qcom_dump_segment *seg;
  2745. struct cnss_host_dump_meta_info meta_info = {0};
  2746. struct list_head head;
  2747. int dev_ret = 0;
  2748. struct device *new_device;
  2749. static const char * const wlan_str[] = {
  2750. [CNSS_HOST_WLAN_LOGS] = "wlan_logs",
  2751. [CNSS_HOST_HTC_CREDIT] = "htc_credit",
  2752. [CNSS_HOST_WMI_TX_CMP] = "wmi_tx_cmp",
  2753. [CNSS_HOST_WMI_COMMAND_LOG] = "wmi_command_log",
  2754. [CNSS_HOST_WMI_EVENT_LOG] = "wmi_event_log",
  2755. [CNSS_HOST_WMI_RX_EVENT] = "wmi_rx_event",
  2756. [CNSS_HOST_HAL_SOC] = "hal_soc",
  2757. [CNSS_HOST_GWLAN_LOGGING] = "gwlan_logging",
  2758. [CNSS_HOST_WMI_DEBUG_LOG_INFO] = "wmi_debug_log_info",
  2759. [CNSS_HOST_HTC_CREDIT_IDX] = "htc_credit_history_idx",
  2760. [CNSS_HOST_HTC_CREDIT_LEN] = "htc_credit_history_length",
  2761. [CNSS_HOST_WMI_TX_CMP_IDX] = "wmi_tx_cmp_idx",
  2762. [CNSS_HOST_WMI_COMMAND_LOG_IDX] = "wmi_command_log_idx",
  2763. [CNSS_HOST_WMI_EVENT_LOG_IDX] = "wmi_event_log_idx",
  2764. [CNSS_HOST_WMI_RX_EVENT_IDX] = "wmi_rx_event_idx",
  2765. [CNSS_HOST_HIF_CE_DESC_HISTORY_BUFF] = "hif_ce_desc_history_buff",
  2766. [CNSS_HOST_HANG_EVENT_DATA] = "hang_event_data",
  2767. [CNSS_HOST_CE_DESC_HIST] = "hif_ce_desc_hist",
  2768. [CNSS_HOST_CE_COUNT_MAX] = "hif_ce_count_max",
  2769. [CNSS_HOST_CE_HISTORY_MAX] = "hif_ce_history_max",
  2770. [CNSS_HOST_ONLY_FOR_CRIT_CE] = "hif_ce_only_for_crit",
  2771. [CNSS_HOST_HIF_EVENT_HISTORY] = "hif_event_history",
  2772. [CNSS_HOST_HIF_EVENT_HIST_MAX] = "hif_event_hist_max",
  2773. [CNSS_HOST_DP_WBM_DESC_REL] = "wbm_desc_rel_ring",
  2774. [CNSS_HOST_DP_WBM_DESC_REL_HANDLE] = "wbm_desc_rel_ring_handle",
  2775. [CNSS_HOST_DP_TCL_CMD] = "tcl_cmd_ring",
  2776. [CNSS_HOST_DP_TCL_CMD_HANDLE] = "tcl_cmd_ring_handle",
  2777. [CNSS_HOST_DP_TCL_STATUS] = "tcl_status_ring",
  2778. [CNSS_HOST_DP_TCL_STATUS_HANDLE] = "tcl_status_ring_handle",
  2779. [CNSS_HOST_DP_REO_REINJ] = "reo_reinject_ring",
  2780. [CNSS_HOST_DP_REO_REINJ_HANDLE] = "reo_reinject_ring_handle",
  2781. [CNSS_HOST_DP_RX_REL] = "rx_rel_ring",
  2782. [CNSS_HOST_DP_RX_REL_HANDLE] = "rx_rel_ring_handle",
  2783. [CNSS_HOST_DP_REO_EXP] = "reo_exception_ring",
  2784. [CNSS_HOST_DP_REO_EXP_HANDLE] = "reo_exception_ring_handle",
  2785. [CNSS_HOST_DP_REO_CMD] = "reo_cmd_ring",
  2786. [CNSS_HOST_DP_REO_CMD_HANDLE] = "reo_cmd_ring_handle",
  2787. [CNSS_HOST_DP_REO_STATUS] = "reo_status_ring",
  2788. [CNSS_HOST_DP_REO_STATUS_HANDLE] = "reo_status_ring_handle",
  2789. [CNSS_HOST_DP_TCL_DATA_0] = "tcl_data_ring_0",
  2790. [CNSS_HOST_DP_TCL_DATA_0_HANDLE] = "tcl_data_ring_0_handle",
  2791. [CNSS_HOST_DP_TX_COMP_0] = "tx_comp_ring_0",
  2792. [CNSS_HOST_DP_TX_COMP_0_HANDLE] = "tx_comp_ring_0_handle",
  2793. [CNSS_HOST_DP_TCL_DATA_1] = "tcl_data_ring_1",
  2794. [CNSS_HOST_DP_TCL_DATA_1_HANDLE] = "tcl_data_ring_1_handle",
  2795. [CNSS_HOST_DP_TX_COMP_1] = "tx_comp_ring_1",
  2796. [CNSS_HOST_DP_TX_COMP_1_HANDLE] = "tx_comp_ring_1_handle",
  2797. [CNSS_HOST_DP_TCL_DATA_2] = "tcl_data_ring_2",
  2798. [CNSS_HOST_DP_TCL_DATA_2_HANDLE] = "tcl_data_ring_2_handle",
  2799. [CNSS_HOST_DP_TX_COMP_2] = "tx_comp_ring_2",
  2800. [CNSS_HOST_DP_TX_COMP_2_HANDLE] = "tx_comp_ring_2_handle",
  2801. [CNSS_HOST_DP_REO_DST_0] = "reo_dest_ring_0",
  2802. [CNSS_HOST_DP_REO_DST_0_HANDLE] = "reo_dest_ring_0_handle",
  2803. [CNSS_HOST_DP_REO_DST_1] = "reo_dest_ring_1",
  2804. [CNSS_HOST_DP_REO_DST_1_HANDLE] = "reo_dest_ring_1_handle",
  2805. [CNSS_HOST_DP_REO_DST_2] = "reo_dest_ring_2",
  2806. [CNSS_HOST_DP_REO_DST_2_HANDLE] = "reo_dest_ring_2_handle",
  2807. [CNSS_HOST_DP_REO_DST_3] = "reo_dest_ring_3",
  2808. [CNSS_HOST_DP_REO_DST_3_HANDLE] = "reo_dest_ring_3_handle",
  2809. [CNSS_HOST_DP_REO_DST_4] = "reo_dest_ring_4",
  2810. [CNSS_HOST_DP_REO_DST_4_HANDLE] = "reo_dest_ring_4_handle",
  2811. [CNSS_HOST_DP_REO_DST_5] = "reo_dest_ring_5",
  2812. [CNSS_HOST_DP_REO_DST_5_HANDLE] = "reo_dest_ring_5_handle",
  2813. [CNSS_HOST_DP_REO_DST_6] = "reo_dest_ring_6",
  2814. [CNSS_HOST_DP_REO_DST_6_HANDLE] = "reo_dest_ring_6_handle",
  2815. [CNSS_HOST_DP_REO_DST_7] = "reo_dest_ring_7",
  2816. [CNSS_HOST_DP_REO_DST_7_HANDLE] = "reo_dest_ring_7_handle",
  2817. [CNSS_HOST_DP_PDEV_0] = "dp_pdev_0",
  2818. [CNSS_HOST_DP_WLAN_CFG_CTX] = "wlan_cfg_ctx",
  2819. [CNSS_HOST_DP_SOC] = "dp_soc",
  2820. [CNSS_HOST_HAL_RX_FST] = "hal_rx_fst",
  2821. [CNSS_HOST_DP_FISA] = "dp_fisa",
  2822. [CNSS_HOST_DP_FISA_HW_FSE_TABLE] = "dp_fisa_hw_fse_table",
  2823. [CNSS_HOST_DP_FISA_SW_FSE_TABLE] = "dp_fisa_sw_fse_table",
  2824. [CNSS_HOST_HIF] = "hif",
  2825. [CNSS_HOST_QDF_NBUF_HIST] = "qdf_nbuf_history",
  2826. [CNSS_HOST_TCL_WBM_MAP] = "tcl_wbm_map_array",
  2827. [CNSS_HOST_RX_MAC_BUF_RING_0] = "rx_mac_buf_ring_0",
  2828. [CNSS_HOST_RX_MAC_BUF_RING_0_HANDLE] = "rx_mac_buf_ring_0_handle",
  2829. [CNSS_HOST_RX_MAC_BUF_RING_1] = "rx_mac_buf_ring_1",
  2830. [CNSS_HOST_RX_MAC_BUF_RING_1_HANDLE] = "rx_mac_buf_ring_1_handle",
  2831. [CNSS_HOST_RX_REFILL_0] = "rx_refill_buf_ring_0",
  2832. [CNSS_HOST_RX_REFILL_0_HANDLE] = "rx_refill_buf_ring_0_handle",
  2833. [CNSS_HOST_CE_0] = "ce_0",
  2834. [CNSS_HOST_CE_0_SRC_RING] = "ce_0_src_ring",
  2835. [CNSS_HOST_CE_0_SRC_RING_CTX] = "ce_0_src_ring_ctx",
  2836. [CNSS_HOST_CE_1] = "ce_1",
  2837. [CNSS_HOST_CE_1_STATUS_RING] = "ce_1_status_ring",
  2838. [CNSS_HOST_CE_1_STATUS_RING_CTX] = "ce_1_status_ring_ctx",
  2839. [CNSS_HOST_CE_1_DEST_RING] = "ce_1_dest_ring",
  2840. [CNSS_HOST_CE_1_DEST_RING_CTX] = "ce_1_dest_ring_ctx",
  2841. [CNSS_HOST_CE_2] = "ce_2",
  2842. [CNSS_HOST_CE_2_STATUS_RING] = "ce_2_status_ring",
  2843. [CNSS_HOST_CE_2_STATUS_RING_CTX] = "ce_2_status_ring_ctx",
  2844. [CNSS_HOST_CE_2_DEST_RING] = "ce_2_dest_ring",
  2845. [CNSS_HOST_CE_2_DEST_RING_CTX] = "ce_2_dest_ring_ctx",
  2846. [CNSS_HOST_CE_3] = "ce_3",
  2847. [CNSS_HOST_CE_3_SRC_RING] = "ce_3_src_ring",
  2848. [CNSS_HOST_CE_3_SRC_RING_CTX] = "ce_3_src_ring_ctx",
  2849. [CNSS_HOST_CE_4] = "ce_4",
  2850. [CNSS_HOST_CE_4_SRC_RING] = "ce_4_src_ring",
  2851. [CNSS_HOST_CE_4_SRC_RING_CTX] = "ce_4_src_ring_ctx",
  2852. [CNSS_HOST_CE_5] = "ce_5",
  2853. [CNSS_HOST_CE_6] = "ce_6",
  2854. [CNSS_HOST_CE_7] = "ce_7",
  2855. [CNSS_HOST_CE_7_STATUS_RING] = "ce_7_status_ring",
  2856. [CNSS_HOST_CE_7_STATUS_RING_CTX] = "ce_7_status_ring_ctx",
  2857. [CNSS_HOST_CE_7_DEST_RING] = "ce_7_dest_ring",
  2858. [CNSS_HOST_CE_7_DEST_RING_CTX] = "ce_7_dest_ring_ctx",
  2859. [CNSS_HOST_CE_8] = "ce_8",
  2860. [CNSS_HOST_DP_TCL_DATA_3] = "tcl_data_ring_3",
  2861. [CNSS_HOST_DP_TCL_DATA_3_HANDLE] = "tcl_data_ring_3_handle",
  2862. [CNSS_HOST_DP_TX_COMP_3] = "tx_comp_ring_3",
  2863. [CNSS_HOST_DP_TX_COMP_3_HANDLE] = "tx_comp_ring_3_handle"
  2864. };
  2865. int i;
  2866. int ret = 0;
  2867. enum cnss_host_dump_type j;
  2868. if (!dump_enabled()) {
  2869. cnss_pr_info("Dump collection is not enabled\n");
  2870. return ret;
  2871. }
  2872. new_device = kcalloc(1, sizeof(*new_device), GFP_KERNEL);
  2873. if (!new_device) {
  2874. cnss_pr_err("Failed to alloc device mem\n");
  2875. return -ENOMEM;
  2876. }
  2877. new_device->release = cnss_host_ramdump_dev_release;
  2878. device_initialize(new_device);
  2879. dev_set_name(new_device, "wlan_driver");
  2880. dev_ret = device_add(new_device);
  2881. if (dev_ret) {
  2882. cnss_pr_err("Failed to add new device\n");
  2883. goto put_device;
  2884. }
  2885. INIT_LIST_HEAD(&head);
  2886. for (i = 0; i < num_entries_loaded; i++) {
  2887. /* If region name registered by driver is not present in
  2888. * wlan_str. type for that entry will not be set, but entry will
  2889. * be added. Which will result in entry type being 0. Currently
  2890. * entry type 0 is for wlan_logs, which will result in parsing
  2891. * issue for wlan_logs as parsing is done based upon type field.
  2892. * So initialize type with -1(Invalid) to avoid such issues.
  2893. */
  2894. meta_info.entry[i].type = -1;
  2895. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2896. if (!seg) {
  2897. cnss_pr_err("Failed to alloc seg entry %d\n", i);
  2898. continue;
  2899. }
  2900. seg->va = ssr_entry[i].buffer_pointer;
  2901. seg->da = (dma_addr_t)ssr_entry[i].buffer_pointer;
  2902. seg->size = ssr_entry[i].buffer_size;
  2903. for (j = 0; j < CNSS_HOST_DUMP_TYPE_MAX; j++) {
  2904. if (strcmp(ssr_entry[i].region_name, wlan_str[j]) == 0) {
  2905. meta_info.entry[i].type = j;
  2906. }
  2907. }
  2908. meta_info.entry[i].entry_start = i + 1;
  2909. meta_info.entry[i].entry_num++;
  2910. list_add_tail(&seg->node, &head);
  2911. }
  2912. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2913. if (!seg) {
  2914. cnss_pr_err("%s: Failed to allocate mem for host dump seg\n",
  2915. __func__);
  2916. goto skip_host_dump;
  2917. }
  2918. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2919. meta_info.version = CNSS_RAMDUMP_VERSION;
  2920. meta_info.chipset = plat_priv->device_id;
  2921. meta_info.total_entries = num_entries_loaded;
  2922. seg->va = &meta_info;
  2923. seg->da = (dma_addr_t)&meta_info;
  2924. seg->size = sizeof(meta_info);
  2925. list_add(&seg->node, &head);
  2926. ret = qcom_elf_dump(&head, new_device, ELF_CLASS);
  2927. skip_host_dump:
  2928. while (!list_empty(&head)) {
  2929. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2930. list_del(&seg->node);
  2931. kfree(seg);
  2932. }
  2933. device_del(new_device);
  2934. put_device:
  2935. put_device(new_device);
  2936. cnss_pr_dbg("host ramdump result %d\n", ret);
  2937. return ret;
  2938. }
  2939. #endif
  2940. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  2941. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2942. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  2943. {
  2944. struct cnss_ramdump_info *ramdump_info;
  2945. struct msm_dump_entry dump_entry;
  2946. ramdump_info = &plat_priv->ramdump_info;
  2947. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  2948. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  2949. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  2950. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  2951. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  2952. sizeof(ramdump_info->dump_data.name));
  2953. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2954. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  2955. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2956. &dump_entry);
  2957. }
  2958. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  2959. {
  2960. int ret = 0;
  2961. struct device *dev;
  2962. struct cnss_ramdump_info *ramdump_info;
  2963. u32 ramdump_size = 0;
  2964. dev = &plat_priv->plat_dev->dev;
  2965. ramdump_info = &plat_priv->ramdump_info;
  2966. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  2967. /* dt type: legacy or converged */
  2968. ret = of_property_read_u32(dev->of_node,
  2969. "qcom,wlan-ramdump-dynamic",
  2970. &ramdump_size);
  2971. } else {
  2972. ret = of_property_read_u32(plat_priv->dev_node,
  2973. "qcom,wlan-ramdump-dynamic",
  2974. &ramdump_size);
  2975. }
  2976. if (ret == 0) {
  2977. ramdump_info->ramdump_va =
  2978. dma_alloc_coherent(dev, ramdump_size,
  2979. &ramdump_info->ramdump_pa,
  2980. GFP_KERNEL);
  2981. if (ramdump_info->ramdump_va)
  2982. ramdump_info->ramdump_size = ramdump_size;
  2983. }
  2984. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  2985. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  2986. if (ramdump_info->ramdump_size == 0) {
  2987. cnss_pr_info("Ramdump will not be collected");
  2988. goto out;
  2989. }
  2990. ret = cnss_init_dump_entry(plat_priv);
  2991. if (ret) {
  2992. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  2993. goto free_ramdump;
  2994. }
  2995. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2996. if (!ramdump_info->ramdump_dev) {
  2997. cnss_pr_err("Failed to create ramdump device!");
  2998. ret = -ENOMEM;
  2999. goto free_ramdump;
  3000. }
  3001. return 0;
  3002. free_ramdump:
  3003. dma_free_coherent(dev, ramdump_info->ramdump_size,
  3004. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  3005. out:
  3006. return ret;
  3007. }
  3008. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  3009. {
  3010. struct device *dev;
  3011. struct cnss_ramdump_info *ramdump_info;
  3012. dev = &plat_priv->plat_dev->dev;
  3013. ramdump_info = &plat_priv->ramdump_info;
  3014. if (ramdump_info->ramdump_dev)
  3015. cnss_destroy_ramdump_device(plat_priv,
  3016. ramdump_info->ramdump_dev);
  3017. if (ramdump_info->ramdump_va)
  3018. dma_free_coherent(dev, ramdump_info->ramdump_size,
  3019. ramdump_info->ramdump_va,
  3020. ramdump_info->ramdump_pa);
  3021. }
  3022. /**
  3023. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  3024. * @ret: Error returned by msm_dump_data_register_nominidump
  3025. *
  3026. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  3027. * ignore failure.
  3028. *
  3029. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  3030. */
  3031. static int cnss_ignore_dump_data_reg_fail(int ret)
  3032. {
  3033. return ret;
  3034. }
  3035. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  3036. {
  3037. int ret = 0;
  3038. struct cnss_ramdump_info_v2 *info_v2;
  3039. struct cnss_dump_data *dump_data;
  3040. struct msm_dump_entry dump_entry;
  3041. struct device *dev = &plat_priv->plat_dev->dev;
  3042. u32 ramdump_size = 0;
  3043. info_v2 = &plat_priv->ramdump_info_v2;
  3044. dump_data = &info_v2->dump_data;
  3045. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  3046. /* dt type: legacy or converged */
  3047. ret = of_property_read_u32(dev->of_node,
  3048. "qcom,wlan-ramdump-dynamic",
  3049. &ramdump_size);
  3050. } else {
  3051. ret = of_property_read_u32(plat_priv->dev_node,
  3052. "qcom,wlan-ramdump-dynamic",
  3053. &ramdump_size);
  3054. }
  3055. if (ret == 0)
  3056. info_v2->ramdump_size = ramdump_size;
  3057. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  3058. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  3059. if (!info_v2->dump_data_vaddr)
  3060. return -ENOMEM;
  3061. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  3062. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  3063. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  3064. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  3065. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  3066. sizeof(dump_data->name));
  3067. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3068. dump_entry.addr = virt_to_phys(dump_data);
  3069. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  3070. &dump_entry);
  3071. if (ret) {
  3072. ret = cnss_ignore_dump_data_reg_fail(ret);
  3073. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  3074. ret ? "Error" : "Ignoring", ret);
  3075. goto free_ramdump;
  3076. }
  3077. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  3078. if (!info_v2->ramdump_dev) {
  3079. cnss_pr_err("Failed to create ramdump device!\n");
  3080. ret = -ENOMEM;
  3081. goto free_ramdump;
  3082. }
  3083. return 0;
  3084. free_ramdump:
  3085. kfree(info_v2->dump_data_vaddr);
  3086. info_v2->dump_data_vaddr = NULL;
  3087. return ret;
  3088. }
  3089. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  3090. {
  3091. struct cnss_ramdump_info_v2 *info_v2;
  3092. info_v2 = &plat_priv->ramdump_info_v2;
  3093. if (info_v2->ramdump_dev)
  3094. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  3095. kfree(info_v2->dump_data_vaddr);
  3096. info_v2->dump_data_vaddr = NULL;
  3097. info_v2->dump_data_valid = false;
  3098. }
  3099. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  3100. {
  3101. int ret = 0;
  3102. switch (plat_priv->device_id) {
  3103. case QCA6174_DEVICE_ID:
  3104. ret = cnss_register_ramdump_v1(plat_priv);
  3105. break;
  3106. case QCA6290_DEVICE_ID:
  3107. case QCA6390_DEVICE_ID:
  3108. case QCN7605_DEVICE_ID:
  3109. case QCA6490_DEVICE_ID:
  3110. case KIWI_DEVICE_ID:
  3111. case MANGO_DEVICE_ID:
  3112. case PEACH_DEVICE_ID:
  3113. ret = cnss_register_ramdump_v2(plat_priv);
  3114. break;
  3115. default:
  3116. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  3117. ret = -ENODEV;
  3118. break;
  3119. }
  3120. return ret;
  3121. }
  3122. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  3123. {
  3124. switch (plat_priv->device_id) {
  3125. case QCA6174_DEVICE_ID:
  3126. cnss_unregister_ramdump_v1(plat_priv);
  3127. break;
  3128. case QCA6290_DEVICE_ID:
  3129. case QCA6390_DEVICE_ID:
  3130. case QCN7605_DEVICE_ID:
  3131. case QCA6490_DEVICE_ID:
  3132. case KIWI_DEVICE_ID:
  3133. case MANGO_DEVICE_ID:
  3134. case PEACH_DEVICE_ID:
  3135. cnss_unregister_ramdump_v2(plat_priv);
  3136. break;
  3137. default:
  3138. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  3139. break;
  3140. }
  3141. }
  3142. #else
  3143. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  3144. {
  3145. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  3146. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  3147. struct device *dev = &plat_priv->plat_dev->dev;
  3148. u32 ramdump_size = 0;
  3149. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  3150. &ramdump_size) == 0)
  3151. info_v2->ramdump_size = ramdump_size;
  3152. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  3153. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  3154. if (!info_v2->dump_data_vaddr)
  3155. return -ENOMEM;
  3156. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  3157. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  3158. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  3159. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  3160. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  3161. sizeof(dump_data->name));
  3162. info_v2->ramdump_dev = dev;
  3163. return 0;
  3164. }
  3165. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  3166. {
  3167. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  3168. info_v2->ramdump_dev = NULL;
  3169. kfree(info_v2->dump_data_vaddr);
  3170. info_v2->dump_data_vaddr = NULL;
  3171. info_v2->dump_data_valid = false;
  3172. }
  3173. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  3174. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  3175. phys_addr_t *pa, unsigned long attrs)
  3176. {
  3177. struct sg_table sgt;
  3178. int ret;
  3179. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  3180. if (ret) {
  3181. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  3182. va, &dma, size, attrs);
  3183. return -EINVAL;
  3184. }
  3185. *pa = page_to_phys(sg_page(sgt.sgl));
  3186. sg_free_table(&sgt);
  3187. return 0;
  3188. }
  3189. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  3190. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  3191. enum cnss_fw_dump_type type, int seg_no,
  3192. void *va, phys_addr_t pa, size_t size)
  3193. {
  3194. struct md_region md_entry;
  3195. int ret;
  3196. switch (type) {
  3197. case CNSS_FW_IMAGE:
  3198. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  3199. seg_no);
  3200. break;
  3201. case CNSS_FW_RDDM:
  3202. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  3203. seg_no);
  3204. break;
  3205. case CNSS_FW_REMOTE_HEAP:
  3206. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  3207. seg_no);
  3208. break;
  3209. default:
  3210. cnss_pr_err("Unknown dump type ID: %d\n", type);
  3211. return -EINVAL;
  3212. }
  3213. md_entry.phys_addr = pa;
  3214. md_entry.virt_addr = (uintptr_t)va;
  3215. md_entry.size = size;
  3216. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3217. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  3218. md_entry.name, va, &pa, size);
  3219. ret = msm_minidump_add_region(&md_entry);
  3220. if (ret < 0)
  3221. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  3222. return ret;
  3223. }
  3224. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  3225. enum cnss_fw_dump_type type, int seg_no,
  3226. void *va, phys_addr_t pa, size_t size)
  3227. {
  3228. struct md_region md_entry;
  3229. int ret;
  3230. switch (type) {
  3231. case CNSS_FW_IMAGE:
  3232. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  3233. seg_no);
  3234. break;
  3235. case CNSS_FW_RDDM:
  3236. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  3237. seg_no);
  3238. break;
  3239. case CNSS_FW_REMOTE_HEAP:
  3240. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  3241. seg_no);
  3242. break;
  3243. default:
  3244. cnss_pr_err("Unknown dump type ID: %d\n", type);
  3245. return -EINVAL;
  3246. }
  3247. md_entry.phys_addr = pa;
  3248. md_entry.virt_addr = (uintptr_t)va;
  3249. md_entry.size = size;
  3250. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3251. cnss_pr_vdbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  3252. md_entry.name, va, &pa, size);
  3253. ret = msm_minidump_remove_region(&md_entry);
  3254. if (ret)
  3255. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  3256. ret);
  3257. return ret;
  3258. }
  3259. #else
  3260. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  3261. enum cnss_fw_dump_type type, int seg_no,
  3262. void *va, phys_addr_t pa, size_t size)
  3263. {
  3264. char name[MAX_NAME_LEN];
  3265. switch (type) {
  3266. case CNSS_FW_IMAGE:
  3267. snprintf(name, MAX_NAME_LEN, "FBC_%X", seg_no);
  3268. break;
  3269. case CNSS_FW_RDDM:
  3270. snprintf(name, MAX_NAME_LEN, "RDDM_%X", seg_no);
  3271. break;
  3272. case CNSS_FW_REMOTE_HEAP:
  3273. snprintf(name, MAX_NAME_LEN, "RHEAP_%X", seg_no);
  3274. break;
  3275. default:
  3276. cnss_pr_err("Unknown dump type ID: %d\n", type);
  3277. return -EINVAL;
  3278. }
  3279. cnss_pr_dbg("Dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  3280. name, va, &pa, size);
  3281. return 0;
  3282. }
  3283. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  3284. enum cnss_fw_dump_type type, int seg_no,
  3285. void *va, phys_addr_t pa, size_t size)
  3286. {
  3287. return 0;
  3288. }
  3289. #endif /* CONFIG_QCOM_MINIDUMP */
  3290. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  3291. const struct firmware **fw_entry,
  3292. const char *filename)
  3293. {
  3294. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  3295. return request_firmware_direct(fw_entry, filename,
  3296. &plat_priv->plat_dev->dev);
  3297. else
  3298. return firmware_request_nowarn(fw_entry, filename,
  3299. &plat_priv->plat_dev->dev);
  3300. }
  3301. #if IS_ENABLED(CONFIG_INTERCONNECT)
  3302. /**
  3303. * cnss_register_bus_scale() - Setup interconnect voting data
  3304. * @plat_priv: Platform data structure
  3305. *
  3306. * For different interconnect path configured in device tree setup voting data
  3307. * for list of bandwidth requirements.
  3308. *
  3309. * Result: 0 for success. -EINVAL if not configured
  3310. */
  3311. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  3312. {
  3313. int ret = -EINVAL;
  3314. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  3315. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  3316. struct device *dev = &plat_priv->plat_dev->dev;
  3317. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  3318. ret = of_property_read_u32(dev->of_node,
  3319. "qcom,icc-path-count",
  3320. &plat_priv->icc.path_count);
  3321. if (ret) {
  3322. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  3323. return 0;
  3324. }
  3325. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  3326. "qcom,bus-bw-cfg-count",
  3327. &plat_priv->icc.bus_bw_cfg_count);
  3328. if (ret) {
  3329. cnss_pr_err("Failed to get Bus BW Config table size\n");
  3330. goto cleanup;
  3331. }
  3332. cfg_arr_size = plat_priv->icc.path_count *
  3333. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  3334. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  3335. if (!cfg_arr) {
  3336. cnss_pr_err("Failed to alloc cfg table mem\n");
  3337. ret = -ENOMEM;
  3338. goto cleanup;
  3339. }
  3340. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  3341. "qcom,bus-bw-cfg", cfg_arr,
  3342. cfg_arr_size);
  3343. if (ret) {
  3344. cnss_pr_err("Invalid Bus BW Config Table\n");
  3345. goto cleanup;
  3346. }
  3347. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  3348. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  3349. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  3350. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  3351. GFP_KERNEL);
  3352. if (!bus_bw_info) {
  3353. ret = -ENOMEM;
  3354. goto out;
  3355. }
  3356. ret = of_property_read_string_index(dev->of_node,
  3357. "interconnect-names", idx,
  3358. &bus_bw_info->icc_name);
  3359. if (ret)
  3360. goto out;
  3361. bus_bw_info->icc_path =
  3362. of_icc_get(&plat_priv->plat_dev->dev,
  3363. bus_bw_info->icc_name);
  3364. if (IS_ERR(bus_bw_info->icc_path)) {
  3365. ret = PTR_ERR(bus_bw_info->icc_path);
  3366. if (ret != -EPROBE_DEFER) {
  3367. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  3368. bus_bw_info->icc_name, ret);
  3369. goto out;
  3370. }
  3371. }
  3372. bus_bw_info->cfg_table =
  3373. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  3374. sizeof(*bus_bw_info->cfg_table),
  3375. GFP_KERNEL);
  3376. if (!bus_bw_info->cfg_table) {
  3377. ret = -ENOMEM;
  3378. goto out;
  3379. }
  3380. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  3381. bus_bw_info->icc_name);
  3382. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  3383. CNSS_ICC_VOTE_MAX);
  3384. i < plat_priv->icc.bus_bw_cfg_count;
  3385. i++, j += 2) {
  3386. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  3387. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  3388. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  3389. i, bus_bw_info->cfg_table[i].avg_bw,
  3390. bus_bw_info->cfg_table[i].peak_bw);
  3391. }
  3392. list_add_tail(&bus_bw_info->list,
  3393. &plat_priv->icc.list_head);
  3394. }
  3395. kfree(cfg_arr);
  3396. return 0;
  3397. out:
  3398. list_for_each_entry_safe(bus_bw_info, tmp,
  3399. &plat_priv->icc.list_head, list) {
  3400. list_del(&bus_bw_info->list);
  3401. }
  3402. cleanup:
  3403. kfree(cfg_arr);
  3404. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  3405. return ret;
  3406. }
  3407. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  3408. {
  3409. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  3410. list_for_each_entry_safe(bus_bw_info, tmp,
  3411. &plat_priv->icc.list_head, list) {
  3412. list_del(&bus_bw_info->list);
  3413. if (bus_bw_info->icc_path)
  3414. icc_put(bus_bw_info->icc_path);
  3415. }
  3416. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  3417. }
  3418. #else
  3419. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  3420. {
  3421. return 0;
  3422. }
  3423. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  3424. #endif /* CONFIG_INTERCONNECT */
  3425. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  3426. {
  3427. struct cnss_plat_data *plat_priv = cb_ctx;
  3428. if (!plat_priv) {
  3429. cnss_pr_err("%s: Invalid context\n", __func__);
  3430. return;
  3431. }
  3432. if (status) {
  3433. cnss_pr_info("CNSS Daemon connected\n");
  3434. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  3435. complete(&plat_priv->daemon_connected);
  3436. } else {
  3437. cnss_pr_info("CNSS Daemon disconnected\n");
  3438. reinit_completion(&plat_priv->daemon_connected);
  3439. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  3440. }
  3441. }
  3442. static ssize_t enable_hds_store(struct device *dev,
  3443. struct device_attribute *attr,
  3444. const char *buf, size_t count)
  3445. {
  3446. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3447. unsigned int enable_hds = 0;
  3448. if (!plat_priv)
  3449. return -ENODEV;
  3450. if (sscanf(buf, "%du", &enable_hds) != 1) {
  3451. cnss_pr_err("Invalid enable_hds sysfs command\n");
  3452. return -EINVAL;
  3453. }
  3454. if (enable_hds)
  3455. plat_priv->hds_enabled = true;
  3456. else
  3457. plat_priv->hds_enabled = false;
  3458. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  3459. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  3460. return count;
  3461. }
  3462. static ssize_t recovery_show(struct device *dev,
  3463. struct device_attribute *attr,
  3464. char *buf)
  3465. {
  3466. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3467. u32 buf_size = PAGE_SIZE;
  3468. u32 curr_len = 0;
  3469. u32 buf_written = 0;
  3470. if (!plat_priv)
  3471. return -ENODEV;
  3472. buf_written = scnprintf(buf, buf_size,
  3473. "Usage: echo [recovery_bitmap] > /sys/kernel/cnss/recovery\n"
  3474. "BIT0 -- wlan fw recovery\n"
  3475. "BIT1 -- wlan pcss recovery\n"
  3476. "---------------------------------\n");
  3477. curr_len += buf_written;
  3478. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  3479. "WLAN recovery %s[%d]\n",
  3480. plat_priv->recovery_enabled ? "Enabled" : "Disabled",
  3481. plat_priv->recovery_enabled);
  3482. curr_len += buf_written;
  3483. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  3484. "WLAN PCSS recovery %s[%d]\n",
  3485. plat_priv->recovery_pcss_enabled ? "Enabled" : "Disabled",
  3486. plat_priv->recovery_pcss_enabled);
  3487. curr_len += buf_written;
  3488. /*
  3489. * Now size of curr_len is not over page size for sure,
  3490. * later if new item or none-fixed size item added, need
  3491. * add check to make sure curr_len is not over page size.
  3492. */
  3493. return curr_len;
  3494. }
  3495. static ssize_t tme_opt_file_download_show(struct device *dev,
  3496. struct device_attribute *attr, char *buf)
  3497. {
  3498. u32 buf_size = PAGE_SIZE;
  3499. u32 curr_len = 0;
  3500. u32 buf_written = 0;
  3501. buf_written = scnprintf(buf, buf_size,
  3502. "Usage: echo [file_type] > /sys/kernel/cnss/tme_opt_file_download\n"
  3503. "file_type = sec -- For OEM_FUSE file\n"
  3504. "file_type = rpr -- For RPR file\n"
  3505. "file_type = dpr -- For DPR file\n");
  3506. curr_len += buf_written;
  3507. return curr_len;
  3508. }
  3509. static ssize_t time_sync_period_show(struct device *dev,
  3510. struct device_attribute *attr,
  3511. char *buf)
  3512. {
  3513. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3514. return scnprintf(buf, PAGE_SIZE, "%u ms\n",
  3515. plat_priv->ctrl_params.time_sync_period);
  3516. }
  3517. /**
  3518. * cnss_get_min_time_sync_period_by_vote() - Get minimum time sync period
  3519. * @plat_priv: Platform data structure
  3520. *
  3521. * Result: return minimum time sync period present in vote from wlan and sys
  3522. */
  3523. uint32_t cnss_get_min_time_sync_period_by_vote(struct cnss_plat_data *plat_priv)
  3524. {
  3525. unsigned int i, min_time_sync_period = CNSS_TIME_SYNC_PERIOD_INVALID;
  3526. unsigned int time_sync_period;
  3527. for (i = 0; i < TIME_SYNC_VOTE_MAX; i++) {
  3528. time_sync_period = plat_priv->ctrl_params.time_sync_period_vote[i];
  3529. if (min_time_sync_period > time_sync_period)
  3530. min_time_sync_period = time_sync_period;
  3531. }
  3532. return min_time_sync_period;
  3533. }
  3534. static ssize_t time_sync_period_store(struct device *dev,
  3535. struct device_attribute *attr,
  3536. const char *buf, size_t count)
  3537. {
  3538. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3539. unsigned int time_sync_period = 0;
  3540. if (!plat_priv)
  3541. return -ENODEV;
  3542. if (sscanf(buf, "%du", &time_sync_period) != 1) {
  3543. cnss_pr_err("Invalid time sync sysfs command\n");
  3544. return -EINVAL;
  3545. }
  3546. if (time_sync_period < CNSS_MIN_TIME_SYNC_PERIOD) {
  3547. cnss_pr_err("Invalid time sync value\n");
  3548. return -EINVAL;
  3549. }
  3550. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_CNSS] =
  3551. time_sync_period;
  3552. time_sync_period = cnss_get_min_time_sync_period_by_vote(plat_priv);
  3553. if (time_sync_period == CNSS_TIME_SYNC_PERIOD_INVALID) {
  3554. cnss_pr_err("Invalid min time sync value\n");
  3555. return -EINVAL;
  3556. }
  3557. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  3558. return count;
  3559. }
  3560. /**
  3561. * cnss_update_time_sync_period() - Set time sync period given by driver
  3562. * @dev: device structure
  3563. * @time_sync_period: time sync period value
  3564. *
  3565. * Update time sync period vote of driver and set minimum of time sync period
  3566. * from stored vote through wlan and sys config
  3567. * Result: return 0 for success, error in case of invalid value and no dev
  3568. */
  3569. int cnss_update_time_sync_period(struct device *dev, uint32_t time_sync_period)
  3570. {
  3571. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  3572. if (!plat_priv)
  3573. return -ENODEV;
  3574. if (time_sync_period < CNSS_MIN_TIME_SYNC_PERIOD) {
  3575. cnss_pr_err("Invalid time sync value\n");
  3576. return -EINVAL;
  3577. }
  3578. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_WLAN] =
  3579. time_sync_period;
  3580. time_sync_period = cnss_get_min_time_sync_period_by_vote(plat_priv);
  3581. if (time_sync_period == CNSS_TIME_SYNC_PERIOD_INVALID) {
  3582. cnss_pr_err("Invalid min time sync value\n");
  3583. return -EINVAL;
  3584. }
  3585. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  3586. return 0;
  3587. }
  3588. EXPORT_SYMBOL(cnss_update_time_sync_period);
  3589. /**
  3590. * cnss_reset_time_sync_period() - Reset time sync period
  3591. * @dev: device structure
  3592. *
  3593. * Update time sync period vote of driver as invalid
  3594. * and reset minimum of time sync period from
  3595. * stored vote through wlan and sys config
  3596. * Result: return 0 for success, error in case of no dev
  3597. */
  3598. int cnss_reset_time_sync_period(struct device *dev)
  3599. {
  3600. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  3601. unsigned int time_sync_period = 0;
  3602. if (!plat_priv)
  3603. return -ENODEV;
  3604. /* Driver vote is set to invalid in case of reset
  3605. * In this case, only vote valid to check is sys config
  3606. */
  3607. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_WLAN] =
  3608. CNSS_TIME_SYNC_PERIOD_INVALID;
  3609. time_sync_period = cnss_get_min_time_sync_period_by_vote(plat_priv);
  3610. if (time_sync_period == CNSS_TIME_SYNC_PERIOD_INVALID) {
  3611. cnss_pr_err("Invalid min time sync value\n");
  3612. return -EINVAL;
  3613. }
  3614. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  3615. return 0;
  3616. }
  3617. EXPORT_SYMBOL(cnss_reset_time_sync_period);
  3618. static ssize_t recovery_store(struct device *dev,
  3619. struct device_attribute *attr,
  3620. const char *buf, size_t count)
  3621. {
  3622. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3623. unsigned int recovery = 0;
  3624. if (!plat_priv)
  3625. return -ENODEV;
  3626. if (sscanf(buf, "%du", &recovery) != 1) {
  3627. cnss_pr_err("Invalid recovery sysfs command\n");
  3628. return -EINVAL;
  3629. }
  3630. plat_priv->recovery_enabled = !!(recovery & CNSS_WLAN_RECOVERY);
  3631. plat_priv->recovery_pcss_enabled = !!(recovery & CNSS_PCSS_RECOVERY);
  3632. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  3633. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  3634. cnss_pr_dbg("%s PCSS recovery, count is %zu\n",
  3635. plat_priv->recovery_pcss_enabled ? "Enable" : "Disable", count);
  3636. cnss_send_subsys_restart_level_msg(plat_priv);
  3637. return count;
  3638. }
  3639. static ssize_t shutdown_store(struct device *dev,
  3640. struct device_attribute *attr,
  3641. const char *buf, size_t count)
  3642. {
  3643. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3644. cnss_pr_dbg("Received shutdown notification\n");
  3645. if (plat_priv) {
  3646. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3647. cnss_bus_update_status(plat_priv, CNSS_SYS_REBOOT);
  3648. del_timer(&plat_priv->fw_boot_timer);
  3649. complete_all(&plat_priv->power_up_complete);
  3650. complete_all(&plat_priv->cal_complete);
  3651. cnss_pr_dbg("Shutdown notification handled\n");
  3652. }
  3653. return count;
  3654. }
  3655. static ssize_t fs_ready_store(struct device *dev,
  3656. struct device_attribute *attr,
  3657. const char *buf, size_t count)
  3658. {
  3659. int fs_ready = 0;
  3660. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3661. if (sscanf(buf, "%du", &fs_ready) != 1)
  3662. return -EINVAL;
  3663. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  3664. fs_ready, count);
  3665. if (!plat_priv) {
  3666. cnss_pr_err("plat_priv is NULL\n");
  3667. return count;
  3668. }
  3669. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  3670. cnss_pr_dbg("QMI is bypassed\n");
  3671. return count;
  3672. }
  3673. set_bit(CNSS_FS_READY, &plat_priv->driver_state);
  3674. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  3675. cnss_driver_event_post(plat_priv,
  3676. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  3677. 0, NULL);
  3678. }
  3679. return count;
  3680. }
  3681. static ssize_t qdss_trace_start_store(struct device *dev,
  3682. struct device_attribute *attr,
  3683. const char *buf, size_t count)
  3684. {
  3685. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3686. wlfw_qdss_trace_start(plat_priv);
  3687. cnss_pr_dbg("Received QDSS start command\n");
  3688. return count;
  3689. }
  3690. static ssize_t qdss_trace_stop_store(struct device *dev,
  3691. struct device_attribute *attr,
  3692. const char *buf, size_t count)
  3693. {
  3694. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3695. u32 option = 0;
  3696. if (sscanf(buf, "%du", &option) != 1)
  3697. return -EINVAL;
  3698. wlfw_qdss_trace_stop(plat_priv, option);
  3699. cnss_pr_dbg("Received QDSS stop command\n");
  3700. return count;
  3701. }
  3702. static ssize_t qdss_conf_download_store(struct device *dev,
  3703. struct device_attribute *attr,
  3704. const char *buf, size_t count)
  3705. {
  3706. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3707. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  3708. cnss_pr_dbg("Received QDSS download config command\n");
  3709. return count;
  3710. }
  3711. static ssize_t tme_opt_file_download_store(struct device *dev,
  3712. struct device_attribute *attr,
  3713. const char *buf, size_t count)
  3714. {
  3715. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3716. char cmd[5];
  3717. if (sscanf(buf, "%s", cmd) != 1)
  3718. return -EINVAL;
  3719. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  3720. cnss_pr_err("Firmware is not ready yet\n");
  3721. return 0;
  3722. }
  3723. if (plat_priv->device_id == PEACH_DEVICE_ID &&
  3724. cnss_bus_runtime_pm_get_sync(plat_priv) < 0)
  3725. goto runtime_pm_put;
  3726. if (strcmp(cmd, "sec") == 0) {
  3727. cnss_bus_load_tme_opt_file(plat_priv, WLFW_TME_LITE_OEM_FUSE_FILE_V01);
  3728. cnss_wlfw_tme_opt_file_dnld_send_sync(plat_priv, WLFW_TME_LITE_OEM_FUSE_FILE_V01);
  3729. } else if (strcmp(cmd, "rpr") == 0) {
  3730. cnss_bus_load_tme_opt_file(plat_priv, WLFW_TME_LITE_RPR_FILE_V01);
  3731. cnss_wlfw_tme_opt_file_dnld_send_sync(plat_priv, WLFW_TME_LITE_RPR_FILE_V01);
  3732. } else if (strcmp(cmd, "dpr") == 0) {
  3733. cnss_bus_load_tme_opt_file(plat_priv, WLFW_TME_LITE_DPR_FILE_V01);
  3734. cnss_wlfw_tme_opt_file_dnld_send_sync(plat_priv, WLFW_TME_LITE_DPR_FILE_V01);
  3735. }
  3736. cnss_pr_dbg("Received tme_opt_file_download indication cmd: %s\n", cmd);
  3737. runtime_pm_put:
  3738. if (plat_priv->device_id == PEACH_DEVICE_ID)
  3739. cnss_bus_runtime_pm_put(plat_priv);
  3740. return count;
  3741. }
  3742. static ssize_t hw_trace_override_store(struct device *dev,
  3743. struct device_attribute *attr,
  3744. const char *buf, size_t count)
  3745. {
  3746. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3747. int tmp = 0;
  3748. if (sscanf(buf, "%du", &tmp) != 1)
  3749. return -EINVAL;
  3750. plat_priv->hw_trc_override = tmp;
  3751. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  3752. return count;
  3753. }
  3754. static ssize_t charger_mode_store(struct device *dev,
  3755. struct device_attribute *attr,
  3756. const char *buf, size_t count)
  3757. {
  3758. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3759. int tmp = 0;
  3760. if (sscanf(buf, "%du", &tmp) != 1)
  3761. return -EINVAL;
  3762. plat_priv->charger_mode = tmp;
  3763. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  3764. return count;
  3765. }
  3766. static DEVICE_ATTR_WO(fs_ready);
  3767. static DEVICE_ATTR_WO(shutdown);
  3768. static DEVICE_ATTR_RW(recovery);
  3769. static DEVICE_ATTR_WO(enable_hds);
  3770. static DEVICE_ATTR_WO(qdss_trace_start);
  3771. static DEVICE_ATTR_WO(qdss_trace_stop);
  3772. static DEVICE_ATTR_WO(qdss_conf_download);
  3773. static DEVICE_ATTR_RW(tme_opt_file_download);
  3774. static DEVICE_ATTR_WO(hw_trace_override);
  3775. static DEVICE_ATTR_WO(charger_mode);
  3776. static DEVICE_ATTR_RW(time_sync_period);
  3777. static struct attribute *cnss_attrs[] = {
  3778. &dev_attr_fs_ready.attr,
  3779. &dev_attr_shutdown.attr,
  3780. &dev_attr_recovery.attr,
  3781. &dev_attr_enable_hds.attr,
  3782. &dev_attr_qdss_trace_start.attr,
  3783. &dev_attr_qdss_trace_stop.attr,
  3784. &dev_attr_qdss_conf_download.attr,
  3785. &dev_attr_tme_opt_file_download.attr,
  3786. &dev_attr_hw_trace_override.attr,
  3787. &dev_attr_charger_mode.attr,
  3788. &dev_attr_time_sync_period.attr,
  3789. NULL,
  3790. };
  3791. static struct attribute_group cnss_attr_group = {
  3792. .attrs = cnss_attrs,
  3793. };
  3794. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  3795. {
  3796. struct device *dev = &plat_priv->plat_dev->dev;
  3797. int ret;
  3798. char cnss_name[CNSS_FS_NAME_SIZE];
  3799. char shutdown_name[32];
  3800. if (cnss_is_dual_wlan_enabled()) {
  3801. snprintf(cnss_name, CNSS_FS_NAME_SIZE,
  3802. CNSS_FS_NAME "_%d", plat_priv->plat_idx);
  3803. snprintf(shutdown_name, sizeof(shutdown_name),
  3804. "shutdown_wlan_%d", plat_priv->plat_idx);
  3805. } else {
  3806. snprintf(cnss_name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME);
  3807. snprintf(shutdown_name, sizeof(shutdown_name),
  3808. "shutdown_wlan");
  3809. }
  3810. ret = sysfs_create_link(kernel_kobj, &dev->kobj, cnss_name);
  3811. if (ret) {
  3812. cnss_pr_err("Failed to create cnss link, err = %d\n",
  3813. ret);
  3814. goto out;
  3815. }
  3816. /* This is only for backward compatibility. */
  3817. ret = sysfs_create_link(kernel_kobj, &dev->kobj, shutdown_name);
  3818. if (ret) {
  3819. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  3820. ret);
  3821. goto rm_cnss_link;
  3822. }
  3823. return 0;
  3824. rm_cnss_link:
  3825. sysfs_remove_link(kernel_kobj, cnss_name);
  3826. out:
  3827. return ret;
  3828. }
  3829. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  3830. {
  3831. char cnss_name[CNSS_FS_NAME_SIZE];
  3832. char shutdown_name[32];
  3833. if (cnss_is_dual_wlan_enabled()) {
  3834. snprintf(cnss_name, CNSS_FS_NAME_SIZE,
  3835. CNSS_FS_NAME "_%d", plat_priv->plat_idx);
  3836. snprintf(shutdown_name, sizeof(shutdown_name),
  3837. "shutdown_wlan_%d", plat_priv->plat_idx);
  3838. } else {
  3839. snprintf(cnss_name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME);
  3840. snprintf(shutdown_name, sizeof(shutdown_name),
  3841. "shutdown_wlan");
  3842. }
  3843. sysfs_remove_link(kernel_kobj, shutdown_name);
  3844. sysfs_remove_link(kernel_kobj, cnss_name);
  3845. }
  3846. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  3847. {
  3848. int ret = 0;
  3849. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  3850. &cnss_attr_group);
  3851. if (ret) {
  3852. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  3853. ret);
  3854. goto out;
  3855. }
  3856. cnss_create_sysfs_link(plat_priv);
  3857. return 0;
  3858. out:
  3859. return ret;
  3860. }
  3861. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 2, 0))
  3862. union cnss_device_group_devres {
  3863. const struct attribute_group *group;
  3864. };
  3865. static void devm_cnss_group_remove(struct device *dev, void *res)
  3866. {
  3867. union cnss_device_group_devres *devres = res;
  3868. const struct attribute_group *group = devres->group;
  3869. cnss_pr_dbg("%s: removing group %p\n", __func__, group);
  3870. sysfs_remove_group(&dev->kobj, group);
  3871. }
  3872. static int devm_cnss_group_match(struct device *dev, void *res, void *data)
  3873. {
  3874. return ((union cnss_device_group_devres *)res) == data;
  3875. }
  3876. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  3877. {
  3878. cnss_remove_sysfs_link(plat_priv);
  3879. WARN_ON(devres_release(&plat_priv->plat_dev->dev,
  3880. devm_cnss_group_remove, devm_cnss_group_match,
  3881. (void *)&cnss_attr_group));
  3882. }
  3883. #else
  3884. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  3885. {
  3886. cnss_remove_sysfs_link(plat_priv);
  3887. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  3888. }
  3889. #endif
  3890. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  3891. {
  3892. spin_lock_init(&plat_priv->event_lock);
  3893. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  3894. WQ_UNBOUND, 1);
  3895. if (!plat_priv->event_wq) {
  3896. cnss_pr_err("Failed to create event workqueue!\n");
  3897. return -EFAULT;
  3898. }
  3899. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  3900. INIT_LIST_HEAD(&plat_priv->event_list);
  3901. return 0;
  3902. }
  3903. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  3904. {
  3905. destroy_workqueue(plat_priv->event_wq);
  3906. }
  3907. static int cnss_reboot_notifier(struct notifier_block *nb,
  3908. unsigned long action,
  3909. void *data)
  3910. {
  3911. struct cnss_plat_data *plat_priv =
  3912. container_of(nb, struct cnss_plat_data, reboot_nb);
  3913. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3914. cnss_bus_update_status(plat_priv, CNSS_SYS_REBOOT);
  3915. del_timer(&plat_priv->fw_boot_timer);
  3916. complete_all(&plat_priv->power_up_complete);
  3917. complete_all(&plat_priv->cal_complete);
  3918. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  3919. return NOTIFY_DONE;
  3920. }
  3921. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  3922. #ifdef CONFIG_CNSS_HW_SECURE_SMEM
  3923. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3924. {
  3925. uint32_t *peripheralStateInfo = NULL;
  3926. size_t size = 0;
  3927. /* Once this flag is set, secure peripheral feature
  3928. * will not be supported till next reboot
  3929. */
  3930. if (plat_priv->sec_peri_feature_disable)
  3931. return 0;
  3932. peripheralStateInfo = qcom_smem_get(QCOM_SMEM_HOST_ANY, PERISEC_SMEM_ID, &size);
  3933. if (IS_ERR_OR_NULL(peripheralStateInfo)) {
  3934. if (PTR_ERR(peripheralStateInfo) != -ENOENT)
  3935. CNSS_ASSERT(0);
  3936. cnss_pr_dbg("Secure HW feature not enabled. ret = %d\n",
  3937. PTR_ERR(peripheralStateInfo));
  3938. plat_priv->sec_peri_feature_disable = true;
  3939. return 0;
  3940. }
  3941. cnss_pr_dbg("Secure HW state: %d\n", *peripheralStateInfo);
  3942. if ((*peripheralStateInfo >> (HW_WIFI_UID - 0x500)) & 0x1)
  3943. set_bit(CNSS_WLAN_HW_DISABLED,
  3944. &plat_priv->driver_state);
  3945. else
  3946. clear_bit(CNSS_WLAN_HW_DISABLED,
  3947. &plat_priv->driver_state);
  3948. return 0;
  3949. }
  3950. #else
  3951. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3952. {
  3953. struct Object client_env;
  3954. struct Object app_object;
  3955. u32 wifi_uid = HW_WIFI_UID;
  3956. union ObjectArg obj_arg[2] = {{{0, 0}}};
  3957. int ret;
  3958. u8 state = 0;
  3959. /* Once this flag is set, secure peripheral feature
  3960. * will not be supported till next reboot
  3961. */
  3962. if (plat_priv->sec_peri_feature_disable)
  3963. return 0;
  3964. /* get rootObj */
  3965. ret = get_client_env_object(&client_env);
  3966. if (ret) {
  3967. cnss_pr_dbg("Failed to get client_env_object, ret: %d\n", ret);
  3968. goto end;
  3969. }
  3970. ret = IClientEnv_open(client_env, HW_STATE_UID, &app_object);
  3971. if (ret) {
  3972. cnss_pr_dbg("Failed to get app_object, ret: %d\n", ret);
  3973. if (ret == FEATURE_NOT_SUPPORTED) {
  3974. ret = 0; /* Do not Assert */
  3975. plat_priv->sec_peri_feature_disable = true;
  3976. cnss_pr_dbg("Secure HW feature not supported\n");
  3977. }
  3978. goto exit_release_clientenv;
  3979. }
  3980. obj_arg[0].b = (struct ObjectBuf) {&wifi_uid, sizeof(u32)};
  3981. obj_arg[1].b = (struct ObjectBuf) {&state, sizeof(u8)};
  3982. ret = Object_invoke(app_object, HW_OP_GET_STATE, obj_arg,
  3983. ObjectCounts_pack(1, 1, 0, 0));
  3984. cnss_pr_dbg("SMC invoke ret: %d state: %d\n", ret, state);
  3985. if (ret) {
  3986. if (ret == PERIPHERAL_NOT_FOUND) {
  3987. ret = 0; /* Do not Assert */
  3988. plat_priv->sec_peri_feature_disable = true;
  3989. cnss_pr_dbg("Secure HW mode is not updated. Peripheral not found\n");
  3990. }
  3991. goto exit_release_app_obj;
  3992. }
  3993. if (state == 1)
  3994. set_bit(CNSS_WLAN_HW_DISABLED,
  3995. &plat_priv->driver_state);
  3996. else
  3997. clear_bit(CNSS_WLAN_HW_DISABLED,
  3998. &plat_priv->driver_state);
  3999. exit_release_app_obj:
  4000. Object_release(app_object);
  4001. exit_release_clientenv:
  4002. Object_release(client_env);
  4003. end:
  4004. if (ret) {
  4005. cnss_pr_err("Unable to get HW disable status\n");
  4006. CNSS_ASSERT(0);
  4007. }
  4008. return ret;
  4009. }
  4010. #endif
  4011. #else
  4012. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  4013. {
  4014. return 0;
  4015. }
  4016. #endif
  4017. #ifdef CONFIG_DISABLE_CNSS_SRAM_DUMP
  4018. static void cnss_sram_dump_init(struct cnss_plat_data *plat_priv)
  4019. {
  4020. }
  4021. #else
  4022. static void cnss_sram_dump_init(struct cnss_plat_data *plat_priv)
  4023. {
  4024. if (plat_priv->device_id == QCA6490_DEVICE_ID &&
  4025. cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01)
  4026. plat_priv->sram_dump = kcalloc(SRAM_DUMP_SIZE, 1, GFP_KERNEL);
  4027. }
  4028. #endif
  4029. #if IS_ENABLED(CONFIG_WCNSS_MEM_PRE_ALLOC)
  4030. static void cnss_initialize_mem_pool(unsigned long device_id)
  4031. {
  4032. cnss_initialize_prealloc_pool(device_id);
  4033. }
  4034. static void cnss_deinitialize_mem_pool(void)
  4035. {
  4036. cnss_deinitialize_prealloc_pool();
  4037. }
  4038. #else
  4039. static void cnss_initialize_mem_pool(unsigned long device_id)
  4040. {
  4041. }
  4042. static void cnss_deinitialize_mem_pool(void)
  4043. {
  4044. }
  4045. #endif
  4046. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  4047. {
  4048. int ret;
  4049. ret = cnss_init_sol_gpio(plat_priv);
  4050. if (ret)
  4051. return ret;
  4052. timer_setup(&plat_priv->fw_boot_timer,
  4053. cnss_bus_fw_boot_timeout_hdlr, 0);
  4054. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  4055. if (ret)
  4056. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  4057. ret);
  4058. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  4059. init_completion(&plat_priv->power_up_complete);
  4060. init_completion(&plat_priv->cal_complete);
  4061. init_completion(&plat_priv->rddm_complete);
  4062. init_completion(&plat_priv->recovery_complete);
  4063. init_completion(&plat_priv->daemon_connected);
  4064. mutex_init(&plat_priv->dev_lock);
  4065. mutex_init(&plat_priv->driver_ops_lock);
  4066. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  4067. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  4068. if (ret)
  4069. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  4070. ret);
  4071. plat_priv->recovery_ws =
  4072. wakeup_source_register(&plat_priv->plat_dev->dev,
  4073. "CNSS_FW_RECOVERY");
  4074. if (!plat_priv->recovery_ws)
  4075. cnss_pr_err("Failed to setup FW recovery wake source\n");
  4076. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  4077. cnss_daemon_connection_update_cb,
  4078. plat_priv);
  4079. if (ret)
  4080. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  4081. ret);
  4082. cnss_sram_dump_init(plat_priv);
  4083. if (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4084. "qcom,rc-ep-short-channel"))
  4085. cnss_set_feature_list(plat_priv, CNSS_RC_EP_ULTRASHORT_CHANNEL_V01);
  4086. if (plat_priv->device_id == PEACH_DEVICE_ID)
  4087. cnss_set_feature_list(plat_priv, CNSS_AUX_UC_SUPPORT_V01);
  4088. return 0;
  4089. }
  4090. #ifdef CONFIG_DISABLE_CNSS_SRAM_DUMP
  4091. static void cnss_sram_dump_deinit(struct cnss_plat_data *plat_priv)
  4092. {
  4093. }
  4094. #else
  4095. static void cnss_sram_dump_deinit(struct cnss_plat_data *plat_priv)
  4096. {
  4097. if (plat_priv->device_id == QCA6490_DEVICE_ID &&
  4098. cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01)
  4099. kfree(plat_priv->sram_dump);
  4100. }
  4101. #endif
  4102. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  4103. {
  4104. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  4105. plat_priv);
  4106. complete_all(&plat_priv->recovery_complete);
  4107. complete_all(&plat_priv->rddm_complete);
  4108. complete_all(&plat_priv->cal_complete);
  4109. complete_all(&plat_priv->power_up_complete);
  4110. complete_all(&plat_priv->daemon_connected);
  4111. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  4112. unregister_reboot_notifier(&plat_priv->reboot_nb);
  4113. del_timer(&plat_priv->fw_boot_timer);
  4114. wakeup_source_unregister(plat_priv->recovery_ws);
  4115. cnss_deinit_sol_gpio(plat_priv);
  4116. cnss_sram_dump_deinit(plat_priv);
  4117. kfree(plat_priv->on_chip_pmic_board_ids);
  4118. }
  4119. static void cnss_init_time_sync_period_default(struct cnss_plat_data *plat_priv)
  4120. {
  4121. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_WLAN] =
  4122. CNSS_TIME_SYNC_PERIOD_INVALID;
  4123. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_CNSS] =
  4124. CNSS_TIME_SYNC_PERIOD_DEFAULT;
  4125. }
  4126. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  4127. {
  4128. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  4129. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  4130. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4131. "qcom,wlan-cbc-enabled");
  4132. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  4133. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  4134. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  4135. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  4136. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  4137. cnss_init_time_sync_period_default(plat_priv);
  4138. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  4139. * enabled by default
  4140. */
  4141. plat_priv->adsp_pc_enabled = true;
  4142. }
  4143. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  4144. {
  4145. struct device *dev = &plat_priv->plat_dev->dev;
  4146. plat_priv->use_pm_domain =
  4147. of_property_read_bool(dev->of_node, "use-pm-domain");
  4148. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  4149. }
  4150. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  4151. {
  4152. struct device *dev = &plat_priv->plat_dev->dev;
  4153. plat_priv->set_wlaon_pwr_ctrl =
  4154. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  4155. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  4156. plat_priv->set_wlaon_pwr_ctrl);
  4157. }
  4158. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  4159. {
  4160. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4161. "qcom,converged-dt") ||
  4162. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4163. "qcom,same-dt-multi-dev") ||
  4164. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4165. "qcom,multi-wlan-exchg"));
  4166. }
  4167. static const struct platform_device_id cnss_platform_id_table[] = {
  4168. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  4169. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  4170. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  4171. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  4172. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  4173. { .name = "mango", .driver_data = MANGO_DEVICE_ID, },
  4174. { .name = "peach", .driver_data = PEACH_DEVICE_ID, },
  4175. { .name = "qcaconv", .driver_data = 0, },
  4176. { },
  4177. };
  4178. static const struct of_device_id cnss_of_match_table[] = {
  4179. {
  4180. .compatible = "qcom,cnss",
  4181. .data = (void *)&cnss_platform_id_table[0]},
  4182. {
  4183. .compatible = "qcom,cnss-qca6290",
  4184. .data = (void *)&cnss_platform_id_table[1]},
  4185. {
  4186. .compatible = "qcom,cnss-qca6390",
  4187. .data = (void *)&cnss_platform_id_table[2]},
  4188. {
  4189. .compatible = "qcom,cnss-qca6490",
  4190. .data = (void *)&cnss_platform_id_table[3]},
  4191. {
  4192. .compatible = "qcom,cnss-kiwi",
  4193. .data = (void *)&cnss_platform_id_table[4]},
  4194. {
  4195. .compatible = "qcom,cnss-mango",
  4196. .data = (void *)&cnss_platform_id_table[5]},
  4197. {
  4198. .compatible = "qcom,cnss-peach",
  4199. .data = (void *)&cnss_platform_id_table[6]},
  4200. {
  4201. .compatible = "qcom,cnss-qca-converged",
  4202. .data = (void *)&cnss_platform_id_table[7]},
  4203. { },
  4204. };
  4205. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  4206. static inline bool
  4207. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  4208. {
  4209. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4210. "use-nv-mac");
  4211. }
  4212. static int cnss_get_dev_cfg_node(struct cnss_plat_data *plat_priv)
  4213. {
  4214. struct device_node *child;
  4215. u32 id, i;
  4216. int id_n, device_identifier_gpio, ret;
  4217. u8 gpio_value;
  4218. if (plat_priv->dt_type != CNSS_DTT_CONVERGED)
  4219. return 0;
  4220. /* Parses the wlan_sw_ctrl gpio which is used to identify device */
  4221. ret = cnss_get_wlan_sw_ctrl(plat_priv);
  4222. if (ret) {
  4223. cnss_pr_dbg("Failed to parse wlan_sw_ctrl gpio, error:%d", ret);
  4224. return ret;
  4225. }
  4226. device_identifier_gpio = plat_priv->pinctrl_info.wlan_sw_ctrl_gpio;
  4227. gpio_value = gpio_get_value(device_identifier_gpio);
  4228. cnss_pr_dbg("Value of Device Identifier GPIO: %d\n", gpio_value);
  4229. for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node,
  4230. child) {
  4231. if (strcmp(child->name, "chip_cfg"))
  4232. continue;
  4233. id_n = of_property_count_u32_elems(child, "supported-ids");
  4234. if (id_n <= 0) {
  4235. cnss_pr_err("Device id is NOT set\n");
  4236. return -EINVAL;
  4237. }
  4238. for (i = 0; i < id_n; i++) {
  4239. ret = of_property_read_u32_index(child,
  4240. "supported-ids",
  4241. i, &id);
  4242. if (ret) {
  4243. cnss_pr_err("Failed to read supported ids\n");
  4244. return -EINVAL;
  4245. }
  4246. if (gpio_value && id == QCA6490_DEVICE_ID) {
  4247. plat_priv->plat_dev->dev.of_node = child;
  4248. plat_priv->device_id = QCA6490_DEVICE_ID;
  4249. cnss_utils_update_device_type(CNSS_HSP_DEVICE_TYPE);
  4250. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  4251. child->name, i, id);
  4252. return 0;
  4253. } else if (!gpio_value && id == KIWI_DEVICE_ID) {
  4254. plat_priv->plat_dev->dev.of_node = child;
  4255. plat_priv->device_id = KIWI_DEVICE_ID;
  4256. cnss_utils_update_device_type(CNSS_HMT_DEVICE_TYPE);
  4257. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  4258. child->name, i, id);
  4259. return 0;
  4260. }
  4261. }
  4262. }
  4263. return -EINVAL;
  4264. }
  4265. static inline u32
  4266. cnss_dt_type(struct cnss_plat_data *plat_priv)
  4267. {
  4268. bool is_converged_dt = of_property_read_bool(
  4269. plat_priv->plat_dev->dev.of_node, "qcom,converged-dt");
  4270. bool is_multi_wlan_xchg;
  4271. if (is_converged_dt)
  4272. return CNSS_DTT_CONVERGED;
  4273. is_multi_wlan_xchg = of_property_read_bool(
  4274. plat_priv->plat_dev->dev.of_node, "qcom,multi-wlan-exchg");
  4275. if (is_multi_wlan_xchg)
  4276. return CNSS_DTT_MULTIEXCHG;
  4277. return CNSS_DTT_LEGACY;
  4278. }
  4279. static int cnss_wlan_device_init(struct cnss_plat_data *plat_priv)
  4280. {
  4281. int ret = 0;
  4282. int retry = 0;
  4283. if (test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  4284. return 0;
  4285. retry:
  4286. ret = cnss_power_on_device(plat_priv, true);
  4287. if (ret)
  4288. goto end;
  4289. ret = cnss_bus_init(plat_priv);
  4290. if (ret) {
  4291. if ((ret != -EPROBE_DEFER) &&
  4292. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  4293. cnss_power_off_device(plat_priv);
  4294. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  4295. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  4296. goto retry;
  4297. }
  4298. goto power_off;
  4299. }
  4300. return 0;
  4301. power_off:
  4302. cnss_power_off_device(plat_priv);
  4303. end:
  4304. return ret;
  4305. }
  4306. int cnss_wlan_hw_enable(void)
  4307. {
  4308. struct cnss_plat_data *plat_priv;
  4309. int ret = 0;
  4310. if (cnss_is_dual_wlan_enabled())
  4311. plat_priv = cnss_get_first_plat_priv(NULL);
  4312. else
  4313. plat_priv = cnss_get_plat_priv(NULL);
  4314. if (!plat_priv)
  4315. return -ENODEV;
  4316. clear_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state);
  4317. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  4318. goto register_driver;
  4319. ret = cnss_wlan_device_init(plat_priv);
  4320. if (ret) {
  4321. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state))
  4322. CNSS_ASSERT(0);
  4323. return ret;
  4324. }
  4325. if (test_bit(CNSS_FS_READY, &plat_priv->driver_state))
  4326. cnss_driver_event_post(plat_priv,
  4327. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  4328. 0, NULL);
  4329. register_driver:
  4330. if (plat_priv->driver_ops)
  4331. ret = cnss_wlan_register_driver(plat_priv->driver_ops);
  4332. return ret;
  4333. }
  4334. EXPORT_SYMBOL(cnss_wlan_hw_enable);
  4335. int cnss_set_wfc_mode(struct device *dev, struct cnss_wfc_cfg cfg)
  4336. {
  4337. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  4338. int ret = 0;
  4339. if (!plat_priv)
  4340. return -ENODEV;
  4341. /* If IMS server is connected, return success without QMI send */
  4342. if (test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  4343. cnss_pr_dbg("Ignore host request as IMS server is connected");
  4344. return ret;
  4345. }
  4346. ret = cnss_wlfw_send_host_wfc_call_status(plat_priv, cfg);
  4347. return ret;
  4348. }
  4349. EXPORT_SYMBOL(cnss_set_wfc_mode);
  4350. static int cnss_tcdev_get_max_state(struct thermal_cooling_device *tcdev,
  4351. unsigned long *thermal_state)
  4352. {
  4353. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4354. if (!tcdev || !tcdev->devdata) {
  4355. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  4356. return -EINVAL;
  4357. }
  4358. cnss_tcdev = tcdev->devdata;
  4359. *thermal_state = cnss_tcdev->max_thermal_state;
  4360. return 0;
  4361. }
  4362. static int cnss_tcdev_get_cur_state(struct thermal_cooling_device *tcdev,
  4363. unsigned long *thermal_state)
  4364. {
  4365. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4366. if (!tcdev || !tcdev->devdata) {
  4367. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  4368. return -EINVAL;
  4369. }
  4370. cnss_tcdev = tcdev->devdata;
  4371. *thermal_state = cnss_tcdev->curr_thermal_state;
  4372. return 0;
  4373. }
  4374. static int cnss_tcdev_set_cur_state(struct thermal_cooling_device *tcdev,
  4375. unsigned long thermal_state)
  4376. {
  4377. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4378. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  4379. int ret = 0;
  4380. if (!tcdev || !tcdev->devdata) {
  4381. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  4382. return -EINVAL;
  4383. }
  4384. cnss_tcdev = tcdev->devdata;
  4385. if (thermal_state > cnss_tcdev->max_thermal_state)
  4386. return -EINVAL;
  4387. cnss_pr_vdbg("Cooling device set current state: %ld,for cdev id %d",
  4388. thermal_state, cnss_tcdev->tcdev_id);
  4389. mutex_lock(&plat_priv->tcdev_lock);
  4390. ret = cnss_bus_set_therm_cdev_state(plat_priv,
  4391. thermal_state,
  4392. cnss_tcdev->tcdev_id);
  4393. if (!ret)
  4394. cnss_tcdev->curr_thermal_state = thermal_state;
  4395. mutex_unlock(&plat_priv->tcdev_lock);
  4396. if (ret) {
  4397. cnss_pr_err("Setting Current Thermal State Failed: %d,for cdev id %d",
  4398. ret, cnss_tcdev->tcdev_id);
  4399. return ret;
  4400. }
  4401. return 0;
  4402. }
  4403. static struct thermal_cooling_device_ops cnss_cooling_ops = {
  4404. .get_max_state = cnss_tcdev_get_max_state,
  4405. .get_cur_state = cnss_tcdev_get_cur_state,
  4406. .set_cur_state = cnss_tcdev_set_cur_state,
  4407. };
  4408. int cnss_thermal_cdev_register(struct device *dev, unsigned long max_state,
  4409. int tcdev_id)
  4410. {
  4411. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  4412. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4413. char cdev_node_name[THERMAL_NAME_LENGTH] = "";
  4414. struct device_node *dev_node;
  4415. int ret = 0;
  4416. if (!priv) {
  4417. cnss_pr_err("Platform driver is not initialized!\n");
  4418. return -ENODEV;
  4419. }
  4420. cnss_tcdev = kzalloc(sizeof(*cnss_tcdev), GFP_KERNEL);
  4421. if (!cnss_tcdev) {
  4422. cnss_pr_err("Failed to allocate cnss_tcdev object!\n");
  4423. return -ENOMEM;
  4424. }
  4425. cnss_tcdev->tcdev_id = tcdev_id;
  4426. cnss_tcdev->max_thermal_state = max_state;
  4427. snprintf(cdev_node_name, THERMAL_NAME_LENGTH,
  4428. "qcom,cnss_cdev%d", tcdev_id);
  4429. dev_node = of_find_node_by_name(NULL, cdev_node_name);
  4430. if (!dev_node) {
  4431. cnss_pr_err("Failed to get cooling device node\n");
  4432. kfree(cnss_tcdev);
  4433. return -EINVAL;
  4434. }
  4435. cnss_pr_dbg("tcdev node->name=%s\n", dev_node->name);
  4436. if (of_find_property(dev_node, "#cooling-cells", NULL)) {
  4437. cnss_tcdev->tcdev = thermal_of_cooling_device_register(dev_node,
  4438. cdev_node_name,
  4439. cnss_tcdev,
  4440. &cnss_cooling_ops);
  4441. if (IS_ERR_OR_NULL(cnss_tcdev->tcdev)) {
  4442. ret = PTR_ERR(cnss_tcdev->tcdev);
  4443. cnss_pr_err("Cooling device register failed: %d, for cdev id %d\n",
  4444. ret, cnss_tcdev->tcdev_id);
  4445. kfree(cnss_tcdev);
  4446. } else {
  4447. cnss_pr_dbg("Cooling device registered for cdev id %d",
  4448. cnss_tcdev->tcdev_id);
  4449. mutex_lock(&priv->tcdev_lock);
  4450. list_add(&cnss_tcdev->tcdev_list,
  4451. &priv->cnss_tcdev_list);
  4452. mutex_unlock(&priv->tcdev_lock);
  4453. }
  4454. } else {
  4455. cnss_pr_dbg("Cooling device registration not supported");
  4456. kfree(cnss_tcdev);
  4457. ret = -EOPNOTSUPP;
  4458. }
  4459. return ret;
  4460. }
  4461. EXPORT_SYMBOL(cnss_thermal_cdev_register);
  4462. void cnss_thermal_cdev_unregister(struct device *dev, int tcdev_id)
  4463. {
  4464. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  4465. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4466. if (!priv) {
  4467. cnss_pr_err("Platform driver is not initialized!\n");
  4468. return;
  4469. }
  4470. mutex_lock(&priv->tcdev_lock);
  4471. while (!list_empty(&priv->cnss_tcdev_list)) {
  4472. cnss_tcdev = list_first_entry(&priv->cnss_tcdev_list,
  4473. struct cnss_thermal_cdev,
  4474. tcdev_list);
  4475. thermal_cooling_device_unregister(cnss_tcdev->tcdev);
  4476. list_del(&cnss_tcdev->tcdev_list);
  4477. kfree(cnss_tcdev);
  4478. }
  4479. mutex_unlock(&priv->tcdev_lock);
  4480. }
  4481. EXPORT_SYMBOL(cnss_thermal_cdev_unregister);
  4482. int cnss_get_curr_therm_cdev_state(struct device *dev,
  4483. unsigned long *thermal_state,
  4484. int tcdev_id)
  4485. {
  4486. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  4487. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4488. if (!priv) {
  4489. cnss_pr_err("Platform driver is not initialized!\n");
  4490. return -ENODEV;
  4491. }
  4492. mutex_lock(&priv->tcdev_lock);
  4493. list_for_each_entry(cnss_tcdev, &priv->cnss_tcdev_list, tcdev_list) {
  4494. if (cnss_tcdev->tcdev_id != tcdev_id)
  4495. continue;
  4496. *thermal_state = cnss_tcdev->curr_thermal_state;
  4497. mutex_unlock(&priv->tcdev_lock);
  4498. cnss_pr_dbg("Cooling device current state: %ld, for cdev id %d",
  4499. cnss_tcdev->curr_thermal_state, tcdev_id);
  4500. return 0;
  4501. }
  4502. mutex_unlock(&priv->tcdev_lock);
  4503. cnss_pr_dbg("Cooling device ID not found: %d", tcdev_id);
  4504. return -EINVAL;
  4505. }
  4506. EXPORT_SYMBOL(cnss_get_curr_therm_cdev_state);
  4507. static int cnss_probe(struct platform_device *plat_dev)
  4508. {
  4509. int ret = 0;
  4510. struct cnss_plat_data *plat_priv;
  4511. const struct of_device_id *of_id;
  4512. const struct platform_device_id *device_id;
  4513. if (cnss_get_plat_priv(plat_dev)) {
  4514. cnss_pr_err("Driver is already initialized!\n");
  4515. ret = -EEXIST;
  4516. goto out;
  4517. }
  4518. ret = cnss_plat_env_available();
  4519. if (ret)
  4520. goto out;
  4521. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  4522. if (!of_id || !of_id->data) {
  4523. cnss_pr_err("Failed to find of match device!\n");
  4524. ret = -ENODEV;
  4525. goto out;
  4526. }
  4527. device_id = of_id->data;
  4528. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  4529. GFP_KERNEL);
  4530. if (!plat_priv) {
  4531. ret = -ENOMEM;
  4532. goto out;
  4533. }
  4534. plat_priv->plat_dev = plat_dev;
  4535. plat_priv->dev_node = NULL;
  4536. plat_priv->device_id = device_id->driver_data;
  4537. plat_priv->dt_type = cnss_dt_type(plat_priv);
  4538. cnss_pr_dbg("Probing platform driver from dt type: %d\n",
  4539. plat_priv->dt_type);
  4540. plat_priv->use_fw_path_with_prefix =
  4541. cnss_use_fw_path_with_prefix(plat_priv);
  4542. ret = cnss_get_dev_cfg_node(plat_priv);
  4543. if (ret) {
  4544. cnss_pr_err("Failed to get device cfg node, err = %d\n", ret);
  4545. goto reset_plat_dev;
  4546. }
  4547. cnss_initialize_mem_pool(plat_priv->device_id);
  4548. ret = cnss_get_pld_bus_ops_name(plat_priv);
  4549. if (ret)
  4550. cnss_pr_vdbg("Failed to find bus ops name, err = %d\n",
  4551. ret);
  4552. ret = cnss_get_rc_num(plat_priv);
  4553. if (ret)
  4554. cnss_pr_err("Failed to find PCIe RC number, err = %d\n", ret);
  4555. cnss_pr_dbg("rc_num=%d\n", plat_priv->rc_num);
  4556. plat_priv->bus_type = cnss_get_bus_type(plat_priv);
  4557. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  4558. cnss_set_plat_priv(plat_dev, plat_priv);
  4559. cnss_set_device_name(plat_priv);
  4560. platform_set_drvdata(plat_dev, plat_priv);
  4561. INIT_LIST_HEAD(&plat_priv->vreg_list);
  4562. INIT_LIST_HEAD(&plat_priv->clk_list);
  4563. cnss_get_pm_domain_info(plat_priv);
  4564. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  4565. cnss_power_misc_params_init(plat_priv);
  4566. cnss_get_tcs_info(plat_priv);
  4567. cnss_get_cpr_info(plat_priv);
  4568. cnss_aop_interface_init(plat_priv);
  4569. cnss_init_control_params(plat_priv);
  4570. ret = cnss_get_resources(plat_priv);
  4571. if (ret)
  4572. goto reset_ctx;
  4573. ret = cnss_register_esoc(plat_priv);
  4574. if (ret)
  4575. goto free_res;
  4576. ret = cnss_register_bus_scale(plat_priv);
  4577. if (ret)
  4578. goto unreg_esoc;
  4579. ret = cnss_create_sysfs(plat_priv);
  4580. if (ret)
  4581. goto unreg_bus_scale;
  4582. ret = cnss_event_work_init(plat_priv);
  4583. if (ret)
  4584. goto remove_sysfs;
  4585. ret = cnss_dms_init(plat_priv);
  4586. if (ret)
  4587. goto deinit_event_work;
  4588. ret = cnss_debugfs_create(plat_priv);
  4589. if (ret)
  4590. goto deinit_dms;
  4591. ret = cnss_misc_init(plat_priv);
  4592. if (ret)
  4593. goto destroy_debugfs;
  4594. ret = cnss_wlan_hw_disable_check(plat_priv);
  4595. if (ret)
  4596. goto deinit_misc;
  4597. /* Make sure all platform related init are done before
  4598. * device power on and bus init.
  4599. */
  4600. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  4601. ret = cnss_wlan_device_init(plat_priv);
  4602. if (ret)
  4603. goto deinit_misc;
  4604. } else {
  4605. cnss_pr_info("WLAN HW Disabled. Defer PCI enumeration\n");
  4606. }
  4607. cnss_register_coex_service(plat_priv);
  4608. cnss_register_ims_service(plat_priv);
  4609. mutex_init(&plat_priv->tcdev_lock);
  4610. INIT_LIST_HEAD(&plat_priv->cnss_tcdev_list);
  4611. cnss_pr_info("Platform driver probed successfully.\n");
  4612. return 0;
  4613. deinit_misc:
  4614. cnss_misc_deinit(plat_priv);
  4615. destroy_debugfs:
  4616. cnss_debugfs_destroy(plat_priv);
  4617. deinit_dms:
  4618. cnss_dms_deinit(plat_priv);
  4619. deinit_event_work:
  4620. cnss_event_work_deinit(plat_priv);
  4621. remove_sysfs:
  4622. cnss_remove_sysfs(plat_priv);
  4623. unreg_bus_scale:
  4624. cnss_unregister_bus_scale(plat_priv);
  4625. unreg_esoc:
  4626. cnss_unregister_esoc(plat_priv);
  4627. free_res:
  4628. cnss_put_resources(plat_priv);
  4629. reset_ctx:
  4630. cnss_aop_interface_deinit(plat_priv);
  4631. platform_set_drvdata(plat_dev, NULL);
  4632. cnss_deinitialize_mem_pool();
  4633. reset_plat_dev:
  4634. cnss_clear_plat_priv(plat_priv);
  4635. out:
  4636. return ret;
  4637. }
  4638. static int cnss_remove(struct platform_device *plat_dev)
  4639. {
  4640. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  4641. plat_priv->audio_iommu_domain = NULL;
  4642. cnss_genl_exit();
  4643. cnss_unregister_ims_service(plat_priv);
  4644. cnss_unregister_coex_service(plat_priv);
  4645. cnss_bus_deinit(plat_priv);
  4646. cnss_misc_deinit(plat_priv);
  4647. cnss_debugfs_destroy(plat_priv);
  4648. cnss_dms_deinit(plat_priv);
  4649. cnss_qmi_deinit(plat_priv);
  4650. cnss_event_work_deinit(plat_priv);
  4651. cnss_cancel_dms_work();
  4652. cnss_remove_sysfs(plat_priv);
  4653. cnss_unregister_bus_scale(plat_priv);
  4654. cnss_unregister_esoc(plat_priv);
  4655. cnss_put_resources(plat_priv);
  4656. cnss_aop_interface_deinit(plat_priv);
  4657. cnss_deinitialize_mem_pool();
  4658. platform_set_drvdata(plat_dev, NULL);
  4659. cnss_clear_plat_priv(plat_priv);
  4660. return 0;
  4661. }
  4662. static struct platform_driver cnss_platform_driver = {
  4663. .probe = cnss_probe,
  4664. .remove = cnss_remove,
  4665. .driver = {
  4666. .name = "cnss2",
  4667. .of_match_table = cnss_of_match_table,
  4668. #ifdef CONFIG_CNSS_ASYNC
  4669. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  4670. #endif
  4671. },
  4672. };
  4673. static bool cnss_check_compatible_node(void)
  4674. {
  4675. struct device_node *dn = NULL;
  4676. for_each_matching_node(dn, cnss_of_match_table) {
  4677. if (of_device_is_available(dn)) {
  4678. cnss_allow_driver_loading = true;
  4679. return true;
  4680. }
  4681. }
  4682. return false;
  4683. }
  4684. /**
  4685. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  4686. *
  4687. * Valid device tree node means a node with "compatible" property from the
  4688. * device match table and "status" property is not disabled.
  4689. *
  4690. * Return: true if valid device tree node found, false if not found
  4691. */
  4692. static bool cnss_is_valid_dt_node_found(void)
  4693. {
  4694. struct device_node *dn = NULL;
  4695. for_each_matching_node(dn, cnss_of_match_table) {
  4696. if (of_device_is_available(dn))
  4697. break;
  4698. }
  4699. if (dn)
  4700. return true;
  4701. return false;
  4702. }
  4703. static int __init cnss_initialize(void)
  4704. {
  4705. int ret = 0;
  4706. if (!cnss_is_valid_dt_node_found())
  4707. return -ENODEV;
  4708. if (!cnss_check_compatible_node())
  4709. return ret;
  4710. cnss_debug_init();
  4711. ret = platform_driver_register(&cnss_platform_driver);
  4712. if (ret)
  4713. cnss_debug_deinit();
  4714. ret = cnss_genl_init();
  4715. if (ret < 0)
  4716. cnss_pr_err("CNSS genl init failed %d\n", ret);
  4717. return ret;
  4718. }
  4719. static void __exit cnss_exit(void)
  4720. {
  4721. cnss_genl_exit();
  4722. platform_driver_unregister(&cnss_platform_driver);
  4723. cnss_debug_deinit();
  4724. }
  4725. module_init(cnss_initialize);
  4726. module_exit(cnss_exit);
  4727. MODULE_LICENSE("GPL v2");
  4728. MODULE_DESCRIPTION("CNSS2 Platform Driver");