a615488cf4
Hal layer changes to handle Umac post reset and post reset complete events from firmware. Change-Id: Ib25427930aab25650731c87b38e2ef7e47ae98d9 CRs-Fixed: 3267222
575 خطوط
17 KiB
C
575 خطوط
17 KiB
C
/*
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* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_GENERIC_API_H_
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#define _HAL_GENERIC_API_H_
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#include <hal_rx.h>
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#define SRNG_ENABLE_BIT 0x40
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#define SRNG_IDLE_STATE_BIT 0x80
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/**
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* hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value
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* from stats enum to radiotap enum
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* @he_gi: HE GI value used in stats
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* @he_ltf: HE LTF value used in stats
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*
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* Return: void
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*/
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static inline void hal_get_radiotap_he_gi_ltf(uint16_t *he_gi, uint16_t *he_ltf)
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{
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switch (*he_gi) {
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case HE_GI_0_8:
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*he_gi = HE_GI_RADIOTAP_0_8;
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break;
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case HE_GI_1_6:
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*he_gi = HE_GI_RADIOTAP_1_6;
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break;
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case HE_GI_3_2:
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*he_gi = HE_GI_RADIOTAP_3_2;
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break;
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default:
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*he_gi = HE_GI_RADIOTAP_RESERVED;
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}
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switch (*he_ltf) {
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case HE_LTF_1_X:
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*he_ltf = HE_LTF_RADIOTAP_1_X;
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break;
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case HE_LTF_2_X:
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*he_ltf = HE_LTF_RADIOTAP_2_X;
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break;
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case HE_LTF_4_X:
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*he_ltf = HE_LTF_RADIOTAP_4_X;
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break;
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default:
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*he_ltf = HE_LTF_RADIOTAP_UNKNOWN;
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}
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}
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/* channel number to freq conversion */
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#define CHANNEL_NUM_14 14
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#define CHANNEL_NUM_15 15
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#define CHANNEL_NUM_27 27
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#define CHANNEL_NUM_35 35
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#define CHANNEL_NUM_182 182
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#define CHANNEL_NUM_197 197
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#define CHANNEL_FREQ_2484 2484
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#define CHANNEL_FREQ_2407 2407
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#define CHANNEL_FREQ_2512 2512
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#define CHANNEL_FREQ_5000 5000
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#define CHANNEL_FREQ_5950 5950
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#define CHANNEL_FREQ_4000 4000
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#define CHANNEL_FREQ_5150 5150
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#define CHANNEL_FREQ_5920 5920
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#define CHANNEL_FREQ_5935 5935
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#define FREQ_MULTIPLIER_CONST_5MHZ 5
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#define FREQ_MULTIPLIER_CONST_20MHZ 20
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/**
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* hal_rx_radiotap_num_to_freq() - Get frequency from chan number
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* @chan_num - Input channel number
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* @center_freq - Input Channel Center frequency
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*
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* Return - Channel frequency in Mhz
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*/
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static inline uint16_t
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hal_rx_radiotap_num_to_freq(uint16_t chan_num, qdf_freq_t center_freq)
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{
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if (center_freq > CHANNEL_FREQ_5920 && center_freq < CHANNEL_FREQ_5950)
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return CHANNEL_FREQ_5935;
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if (center_freq < CHANNEL_FREQ_5950) {
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if (chan_num == CHANNEL_NUM_14)
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return CHANNEL_FREQ_2484;
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if (chan_num < CHANNEL_NUM_14)
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return CHANNEL_FREQ_2407 +
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(chan_num * FREQ_MULTIPLIER_CONST_5MHZ);
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if (chan_num < CHANNEL_NUM_27)
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return CHANNEL_FREQ_2512 +
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((chan_num - CHANNEL_NUM_15) *
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FREQ_MULTIPLIER_CONST_20MHZ);
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if (chan_num > CHANNEL_NUM_182 &&
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chan_num < CHANNEL_NUM_197)
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return ((chan_num * FREQ_MULTIPLIER_CONST_5MHZ) +
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CHANNEL_FREQ_4000);
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return CHANNEL_FREQ_5000 +
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(chan_num * FREQ_MULTIPLIER_CONST_5MHZ);
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} else {
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return CHANNEL_FREQ_5950 +
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(chan_num * FREQ_MULTIPLIER_CONST_5MHZ);
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}
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}
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/**
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* hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring
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* @hal_soc: Opaque HAL SOC handle
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* @hal_ring: Source ring pointer
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* @headp: Head Pointer
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* @tailp: Tail Pointer
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* @ring: Ring type
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*
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* Return: Update tail pointer and head pointer in arguments.
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*/
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static inline
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void hal_get_hw_hptp_generic(struct hal_soc *hal_soc,
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hal_ring_handle_t hal_ring_hdl,
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uint32_t *headp, uint32_t *tailp,
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uint8_t ring)
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{
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struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
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struct hal_hw_srng_config *ring_config;
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enum hal_ring_type ring_type = (enum hal_ring_type)ring;
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if (!hal_soc || !srng) {
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QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR,
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"%s: Context is Null", __func__);
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return;
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}
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ring_config = HAL_SRNG_CONFIG(hal_soc, ring_type);
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if (!ring_config->lmac_ring) {
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if (srng->ring_dir == HAL_SRNG_SRC_RING) {
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*headp = SRNG_SRC_REG_READ(srng, HP);
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*tailp = SRNG_SRC_REG_READ(srng, TP);
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} else {
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*headp = SRNG_DST_REG_READ(srng, HP);
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*tailp = SRNG_DST_REG_READ(srng, TP);
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}
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}
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}
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#if defined(WBM_IDLE_LSB_WRITE_CONFIRM_WAR)
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/**
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* hal_wbm_idle_lsb_write_confirm() - Check and update WBM_IDLE_LINK ring LSB
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* @srng: srng handle
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*
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* Return: None
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*/
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static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng)
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{
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if (srng->ring_id == HAL_SRNG_WBM_IDLE_LINK) {
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while (SRNG_SRC_REG_READ(srng, BASE_LSB) !=
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((unsigned int)srng->ring_base_paddr & 0xffffffff))
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SRNG_SRC_REG_WRITE(srng, BASE_LSB,
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srng->ring_base_paddr &
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0xffffffff);
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}
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}
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#else
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static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng)
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{
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}
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#endif
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#ifdef DP_UMAC_HW_RESET_SUPPORT
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/**
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* hal_srng_src_hw_write_cons_prefetch_timer() - Write cons prefetch timer reg
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* @srng: srng handle
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* @value: value to set
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*
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* Return: None
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*/
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static inline
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void hal_srng_src_hw_write_cons_prefetch_timer(struct hal_srng *srng,
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uint32_t value)
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{
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SRNG_SRC_REG_WRITE(srng, CONSUMER_PREFETCH_TIMER, value);
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}
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/**
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* hal_srng_hw_disable_generic - Private function to disable SRNG
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* source ring HW
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* @hal_soc: HAL SOC handle
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* @srng: SRNG ring pointer
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*/
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static inline
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void hal_srng_hw_disable_generic(struct hal_soc *hal, struct hal_srng *srng)
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{
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uint32_t reg_val = 0;
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if (srng->ring_dir == HAL_SRNG_DST_RING) {
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reg_val = SRNG_DST_REG_READ(srng, MISC) & ~(SRNG_ENABLE_BIT);
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SRNG_DST_REG_WRITE(srng, MISC, reg_val);
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} else {
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reg_val = SRNG_SRC_REG_READ(srng, MISC) & ~(SRNG_ENABLE_BIT);
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SRNG_SRC_REG_WRITE(srng, MISC, reg_val);
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srng->prefetch_timer =
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SRNG_SRC_REG_READ(srng, CONSUMER_PREFETCH_TIMER);
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hal_srng_src_hw_write_cons_prefetch_timer(srng, 0);
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}
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}
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#else
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static inline
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void hal_srng_hw_disable_generic(struct hal_soc *hal, struct hal_srng *srng)
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{
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}
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static inline
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void hal_srng_src_hw_write_cons_prefetch_timer(struct hal_srng *srng,
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uint32_t value)
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{
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}
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#endif
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/**
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* hal_srng_src_hw_init - Private function to initialize SRNG
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* source ring HW
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* @hal_soc: HAL SOC handle
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* @srng: SRNG ring pointer
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* @idle_check: Check if ring is idle
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*/
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static inline
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void hal_srng_src_hw_init_generic(struct hal_soc *hal,
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struct hal_srng *srng, bool idle_check)
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{
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uint32_t reg_val = 0;
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uint64_t tp_addr = 0;
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if (idle_check) {
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reg_val = SRNG_SRC_REG_READ(srng, MISC);
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if (!(reg_val & SRNG_IDLE_STATE_BIT)) {
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hal_err("ring_id %d not in idle state", srng->ring_id);
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qdf_assert_always(0);
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}
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hal_srng_src_hw_write_cons_prefetch_timer(srng,
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srng->prefetch_timer);
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}
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hal_debug("hw_init srng %d", srng->ring_id);
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if (srng->flags & HAL_SRNG_MSI_INTR) {
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SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB,
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srng->msi_addr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR),
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(uint64_t)(srng->msi_addr) >> 32) |
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SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB,
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MSI1_ENABLE), 1);
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SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
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SRNG_SRC_REG_WRITE(srng, MSI1_DATA,
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qdf_cpu_to_le32(srng->msi_data));
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}
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SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
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hal_wbm_idle_lsb_write_confirm(srng);
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reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
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((uint64_t)(srng->ring_base_paddr) >> 32)) |
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SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE),
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srng->entry_size * srng->num_entries);
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SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val);
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reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size);
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SRNG_SRC_REG_WRITE(srng, ID, reg_val);
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/**
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* Interrupt setup:
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* Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE
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* if level mode is required
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*/
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reg_val = 0;
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/*
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* WAR - Hawkeye v1 has a hardware bug which requires timer value to be
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* programmed in terms of 1us resolution instead of 8us resolution as
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* given in MLD.
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*/
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if (srng->intr_timer_thres_us) {
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reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0,
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INTERRUPT_TIMER_THRESHOLD),
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srng->intr_timer_thres_us);
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/* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */
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}
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if (srng->intr_batch_cntr_thres_entries) {
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reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0,
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BATCH_COUNTER_THRESHOLD),
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srng->intr_batch_cntr_thres_entries *
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srng->entry_size);
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}
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SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val);
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reg_val = 0;
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if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) {
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reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1,
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LOW_THRESHOLD), srng->u.src_ring.low_threshold);
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}
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SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val);
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/* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should
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* remain 0 to avoid some WBM stability issues. Remote head/tail
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* pointers are not required since this ring is completely managed
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* by WBM HW
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*/
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reg_val = 0;
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if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) {
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tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
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((unsigned long)(srng->u.src_ring.tp_addr) -
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(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
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SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff);
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SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32);
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} else {
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reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1);
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}
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/* Initilaize head and tail pointers to indicate ring is empty */
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SRNG_SRC_REG_WRITE(srng, HP, 0);
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SRNG_SRC_REG_WRITE(srng, TP, 0);
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*(srng->u.src_ring.tp_addr) = 0;
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reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ?
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SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) |
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((srng->flags & HAL_SRNG_RING_PTR_SWAP) ?
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SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) |
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((srng->flags & HAL_SRNG_MSI_SWAP) ?
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SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0);
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/* Loop count is not used for SRC rings */
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reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1);
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/*
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* reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1);
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* todo: update fw_api and replace with above line
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* (when SRNG_ENABLE field for the MISC register is available in fw_api)
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* (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC)
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*/
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reg_val |= SRNG_ENABLE_BIT;
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SRNG_SRC_REG_WRITE(srng, MISC, reg_val);
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}
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#ifdef WLAN_FEATURE_NEAR_FULL_IRQ
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/**
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* hal_srng_dst_msi2_setup() - Configure MSI2 register for a SRNG
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* @srng: SRNG handle
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*
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* Return: None
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*/
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static inline void hal_srng_dst_msi2_setup(struct hal_srng *srng)
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{
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uint32_t reg_val = 0;
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if (srng->u.dst_ring.nf_irq_support) {
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SRNG_DST_REG_WRITE(srng, MSI2_BASE_LSB,
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srng->msi2_addr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_DST_FLD(MSI2_BASE_MSB, ADDR),
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(uint64_t)(srng->msi2_addr) >> 32) |
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SRNG_SM(SRNG_DST_FLD(MSI2_BASE_MSB,
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MSI2_ENABLE), 1);
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SRNG_DST_REG_WRITE(srng, MSI2_BASE_MSB, reg_val);
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SRNG_DST_REG_WRITE(srng, MSI2_DATA,
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qdf_cpu_to_le32(srng->msi2_data));
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}
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}
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/**
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* hal_srng_dst_near_full_int_setup() - Configure near-full params for SRNG
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* @srng: SRNG handle
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*
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* Return: None
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*/
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static inline void hal_srng_dst_near_full_int_setup(struct hal_srng *srng)
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{
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uint32_t reg_val = 0;
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if (srng->u.dst_ring.nf_irq_support) {
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if (srng->intr_timer_thres_us) {
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reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT2_SETUP,
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INTERRUPT2_TIMER_THRESHOLD),
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srng->intr_timer_thres_us >> 3);
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}
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reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT2_SETUP,
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HIGH_THRESHOLD),
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srng->u.dst_ring.high_thresh *
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srng->entry_size);
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}
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SRNG_DST_REG_WRITE(srng, PRODUCER_INT2_SETUP, reg_val);
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}
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#else
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static inline void hal_srng_dst_msi2_setup(struct hal_srng *srng)
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{
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}
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static inline void hal_srng_dst_near_full_int_setup(struct hal_srng *srng)
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{
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}
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#endif
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/**
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* hal_srng_dst_hw_init - Private function to initialize SRNG
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* destination ring HW
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* @hal_soc: HAL SOC handle
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* @srng: SRNG ring pointer
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* @idle_check: Check if ring is idle
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*/
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static inline
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void hal_srng_dst_hw_init_generic(struct hal_soc *hal,
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struct hal_srng *srng, bool idle_check)
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{
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uint32_t reg_val = 0;
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uint64_t hp_addr = 0;
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if (idle_check) {
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reg_val = SRNG_DST_REG_READ(srng, MISC);
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if (!(reg_val & SRNG_IDLE_STATE_BIT)) {
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hal_err("ring_id %d not in idle state", srng->ring_id);
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qdf_assert_always(0);
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}
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}
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hal_debug("hw_init srng %d", srng->ring_id);
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if (srng->flags & HAL_SRNG_MSI_INTR) {
|
|
SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB,
|
|
srng->msi_addr & 0xffffffff);
|
|
reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR),
|
|
(uint64_t)(srng->msi_addr) >> 32) |
|
|
SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB,
|
|
MSI1_ENABLE), 1);
|
|
SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
|
|
SRNG_DST_REG_WRITE(srng, MSI1_DATA,
|
|
qdf_cpu_to_le32(srng->msi_data));
|
|
|
|
hal_srng_dst_msi2_setup(srng);
|
|
}
|
|
|
|
SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
|
|
reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
|
|
((uint64_t)(srng->ring_base_paddr) >> 32)) |
|
|
SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE),
|
|
srng->entry_size * srng->num_entries);
|
|
SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val);
|
|
|
|
reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) |
|
|
SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size);
|
|
SRNG_DST_REG_WRITE(srng, ID, reg_val);
|
|
|
|
|
|
/**
|
|
* Interrupt setup:
|
|
* Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE
|
|
* if level mode is required
|
|
*/
|
|
reg_val = 0;
|
|
if (srng->intr_timer_thres_us) {
|
|
reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP,
|
|
INTERRUPT_TIMER_THRESHOLD),
|
|
srng->intr_timer_thres_us >> 3);
|
|
}
|
|
|
|
if (srng->intr_batch_cntr_thres_entries) {
|
|
reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP,
|
|
BATCH_COUNTER_THRESHOLD),
|
|
srng->intr_batch_cntr_thres_entries *
|
|
srng->entry_size);
|
|
}
|
|
|
|
SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val);
|
|
|
|
/**
|
|
* Near-Full Interrupt setup:
|
|
* Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE
|
|
* if level mode is required
|
|
*/
|
|
hal_srng_dst_near_full_int_setup(srng);
|
|
|
|
hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
|
|
((unsigned long)(srng->u.dst_ring.hp_addr) -
|
|
(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
|
|
SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff);
|
|
SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32);
|
|
|
|
/* Initilaize head and tail pointers to indicate ring is empty */
|
|
SRNG_DST_REG_WRITE(srng, HP, 0);
|
|
SRNG_DST_REG_WRITE(srng, TP, 0);
|
|
*(srng->u.dst_ring.hp_addr) = 0;
|
|
|
|
reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ?
|
|
SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) |
|
|
((srng->flags & HAL_SRNG_RING_PTR_SWAP) ?
|
|
SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) |
|
|
((srng->flags & HAL_SRNG_MSI_SWAP) ?
|
|
SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0);
|
|
|
|
/*
|
|
* reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1);
|
|
* todo: update fw_api and replace with above line
|
|
* (when SRNG_ENABLE field for the MISC register is available in fw_api)
|
|
* (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC)
|
|
*/
|
|
reg_val |= 0x40;
|
|
|
|
SRNG_DST_REG_WRITE(srng, MISC, reg_val);
|
|
|
|
}
|
|
|
|
/**
|
|
* hal_srng_hw_reg_offset_init_generic() - Initialize the HW srng reg offset
|
|
* @hal_soc: HAL Soc handle
|
|
*
|
|
* Return: None
|
|
*/
|
|
static inline void hal_srng_hw_reg_offset_init_generic(struct hal_soc *hal_soc)
|
|
{
|
|
int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
|
|
|
|
/* dst */
|
|
hw_reg_offset[DST_HP] = REG_OFFSET(DST, HP);
|
|
hw_reg_offset[DST_TP] = REG_OFFSET(DST, TP);
|
|
hw_reg_offset[DST_ID] = REG_OFFSET(DST, ID);
|
|
hw_reg_offset[DST_MISC] = REG_OFFSET(DST, MISC);
|
|
hw_reg_offset[DST_HP_ADDR_LSB] = REG_OFFSET(DST, HP_ADDR_LSB);
|
|
hw_reg_offset[DST_HP_ADDR_MSB] = REG_OFFSET(DST, HP_ADDR_MSB);
|
|
hw_reg_offset[DST_MSI1_BASE_LSB] = REG_OFFSET(DST, MSI1_BASE_LSB);
|
|
hw_reg_offset[DST_MSI1_BASE_MSB] = REG_OFFSET(DST, MSI1_BASE_MSB);
|
|
hw_reg_offset[DST_MSI1_DATA] = REG_OFFSET(DST, MSI1_DATA);
|
|
hw_reg_offset[DST_BASE_LSB] = REG_OFFSET(DST, BASE_LSB);
|
|
hw_reg_offset[DST_BASE_MSB] = REG_OFFSET(DST, BASE_MSB);
|
|
hw_reg_offset[DST_PRODUCER_INT_SETUP] =
|
|
REG_OFFSET(DST, PRODUCER_INT_SETUP);
|
|
|
|
/* src */
|
|
hw_reg_offset[SRC_HP] = REG_OFFSET(SRC, HP);
|
|
hw_reg_offset[SRC_TP] = REG_OFFSET(SRC, TP);
|
|
hw_reg_offset[SRC_ID] = REG_OFFSET(SRC, ID);
|
|
hw_reg_offset[SRC_MISC] = REG_OFFSET(SRC, MISC);
|
|
hw_reg_offset[SRC_TP_ADDR_LSB] = REG_OFFSET(SRC, TP_ADDR_LSB);
|
|
hw_reg_offset[SRC_TP_ADDR_MSB] = REG_OFFSET(SRC, TP_ADDR_MSB);
|
|
hw_reg_offset[SRC_MSI1_BASE_LSB] = REG_OFFSET(SRC, MSI1_BASE_LSB);
|
|
hw_reg_offset[SRC_MSI1_BASE_MSB] = REG_OFFSET(SRC, MSI1_BASE_MSB);
|
|
hw_reg_offset[SRC_MSI1_DATA] = REG_OFFSET(SRC, MSI1_DATA);
|
|
hw_reg_offset[SRC_BASE_LSB] = REG_OFFSET(SRC, BASE_LSB);
|
|
hw_reg_offset[SRC_BASE_MSB] = REG_OFFSET(SRC, BASE_MSB);
|
|
hw_reg_offset[SRC_CONSUMER_INT_SETUP_IX0] =
|
|
REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0);
|
|
hw_reg_offset[SRC_CONSUMER_INT_SETUP_IX1] =
|
|
REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1);
|
|
#ifdef DP_UMAC_HW_RESET_SUPPORT
|
|
hw_reg_offset[SRC_CONSUMER_PREFETCH_TIMER] =
|
|
REG_OFFSET(SRC, CONSUMER_PREFETCH_TIMER);
|
|
#endif
|
|
}
|
|
|
|
#endif /* HAL_GENERIC_API_H_ */
|