main.c 149 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/thermal.h>
  20. #include <linux/version.h>
  21. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  22. #include <linux/panic_notifier.h>
  23. #endif
  24. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  25. #include <soc/qcom/minidump.h>
  26. #endif
  27. #include "cnss_plat_ipc_qmi.h"
  28. #include "cnss_utils.h"
  29. #include "main.h"
  30. #include "bus.h"
  31. #include "debug.h"
  32. #include "genl.h"
  33. #include "reg.h"
  34. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  35. #ifdef CONFIG_CNSS_HW_SECURE_SMEM
  36. #include <linux/soc/qcom/smem.h>
  37. #define PERISEC_SMEM_ID 651
  38. #define HW_WIFI_UID 0x508
  39. #else
  40. #include "smcinvoke.h"
  41. #include "smcinvoke_object.h"
  42. #include "IClientEnv.h"
  43. #define HW_STATE_UID 0x108
  44. #define HW_OP_GET_STATE 1
  45. #define HW_WIFI_UID 0x508
  46. #define FEATURE_NOT_SUPPORTED 12
  47. #define PERIPHERAL_NOT_FOUND 10
  48. #endif
  49. #endif
  50. #define CNSS_DUMP_FORMAT_VER 0x11
  51. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  52. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  53. #define CNSS_DUMP_NAME "CNSS_WLAN"
  54. #define CNSS_DUMP_DESC_SIZE 0x1000
  55. #define CNSS_DUMP_SEG_VER 0x1
  56. #define FILE_SYSTEM_READY 1
  57. #define FW_READY_TIMEOUT 20000
  58. #define FW_ASSERT_TIMEOUT 5000
  59. #define CNSS_EVENT_PENDING 2989
  60. #define POWER_RESET_MIN_DELAY_MS 100
  61. #define MAX_NAME_LEN 12
  62. #define CNSS_QUIRKS_DEFAULT 0
  63. #ifdef CONFIG_CNSS_EMULATION
  64. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  65. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  66. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  67. #else
  68. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  69. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  70. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  71. #endif
  72. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  73. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  74. #define CNSS_MIN_TIME_SYNC_PERIOD 2000
  75. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  76. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  77. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  78. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  79. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  80. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  81. #define CNSS_TIME_SYNC_PERIOD_INVALID 0xFFFFFFFF
  82. enum cnss_cal_db_op {
  83. CNSS_CAL_DB_UPLOAD,
  84. CNSS_CAL_DB_DOWNLOAD,
  85. CNSS_CAL_DB_INVALID_OP,
  86. };
  87. enum cnss_recovery_type {
  88. CNSS_WLAN_RECOVERY = 0x1,
  89. CNSS_PCSS_RECOVERY = 0x2,
  90. };
  91. #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV
  92. #define CNSS_MAX_DEV_NUM 2
  93. static struct cnss_plat_data *plat_env[CNSS_MAX_DEV_NUM];
  94. static atomic_t plat_env_count;
  95. #else
  96. static struct cnss_plat_data *plat_env;
  97. #endif
  98. static bool cnss_allow_driver_loading;
  99. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  100. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  101. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  102. };
  103. static struct cnss_fw_files FW_FILES_DEFAULT = {
  104. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  105. "utfbd.bin", "epping.bin", "evicted.bin"
  106. };
  107. struct cnss_driver_event {
  108. struct list_head list;
  109. enum cnss_driver_event_type type;
  110. bool sync;
  111. struct completion complete;
  112. int ret;
  113. void *data;
  114. };
  115. bool cnss_check_driver_loading_allowed(void)
  116. {
  117. return cnss_allow_driver_loading;
  118. }
  119. #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV
  120. static void cnss_init_plat_env_count(void)
  121. {
  122. atomic_set(&plat_env_count, 0);
  123. }
  124. static void cnss_inc_plat_env_count(void)
  125. {
  126. atomic_inc(&plat_env_count);
  127. }
  128. static void cnss_dec_plat_env_count(void)
  129. {
  130. atomic_dec(&plat_env_count);
  131. }
  132. static int cnss_get_plat_env_count(void)
  133. {
  134. return atomic_read(&plat_env_count);
  135. }
  136. int cnss_get_max_plat_env_count(void)
  137. {
  138. return CNSS_MAX_DEV_NUM;
  139. }
  140. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  141. struct cnss_plat_data *plat_priv)
  142. {
  143. int env_count = cnss_get_plat_env_count();
  144. cnss_pr_dbg("Set plat_priv at %d", env_count);
  145. if (plat_priv) {
  146. plat_priv->plat_idx = env_count;
  147. plat_env[plat_priv->plat_idx] = plat_priv;
  148. cnss_inc_plat_env_count();
  149. }
  150. }
  151. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device
  152. *plat_dev)
  153. {
  154. int i;
  155. if (!plat_dev)
  156. return NULL;
  157. for (i = 0; i < CNSS_MAX_DEV_NUM; i++) {
  158. if (plat_env[i] && plat_env[i]->plat_dev == plat_dev)
  159. return plat_env[i];
  160. }
  161. return NULL;
  162. }
  163. struct cnss_plat_data *cnss_get_first_plat_priv(struct platform_device
  164. *plat_dev)
  165. {
  166. int i;
  167. if (!plat_dev) {
  168. for (i = 0; i < CNSS_MAX_DEV_NUM; i++) {
  169. if (plat_env[i])
  170. return plat_env[i];
  171. }
  172. }
  173. return NULL;
  174. }
  175. static void cnss_clear_plat_priv(struct cnss_plat_data *plat_priv)
  176. {
  177. cnss_pr_dbg("Clear plat_priv at %d", plat_priv->plat_idx);
  178. plat_env[plat_priv->plat_idx] = NULL;
  179. cnss_dec_plat_env_count();
  180. }
  181. static int cnss_set_device_name(struct cnss_plat_data *plat_priv)
  182. {
  183. snprintf(plat_priv->device_name, sizeof(plat_priv->device_name),
  184. "wlan_%d", plat_priv->plat_idx);
  185. return 0;
  186. }
  187. static int cnss_plat_env_available(void)
  188. {
  189. int ret = 0;
  190. int env_count = cnss_get_plat_env_count();
  191. if (env_count >= CNSS_MAX_DEV_NUM) {
  192. cnss_pr_err("ERROR: No space to store plat_priv\n");
  193. ret = -ENOMEM;
  194. }
  195. return ret;
  196. }
  197. struct cnss_plat_data *cnss_get_plat_env(int index)
  198. {
  199. return plat_env[index];
  200. }
  201. struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num)
  202. {
  203. int i;
  204. for (i = 0; i < CNSS_MAX_DEV_NUM; i++) {
  205. if (plat_env[i] && plat_env[i]->rc_num == rc_num)
  206. return plat_env[i];
  207. }
  208. return NULL;
  209. }
  210. static inline int
  211. cnss_get_qrtr_node_id(struct cnss_plat_data *plat_priv)
  212. {
  213. return of_property_read_u32(plat_priv->dev_node,
  214. "qcom,qrtr_node_id", &plat_priv->qrtr_node_id);
  215. }
  216. void cnss_get_qrtr_info(struct cnss_plat_data *plat_priv)
  217. {
  218. int ret = 0;
  219. ret = cnss_get_qrtr_node_id(plat_priv);
  220. if (ret) {
  221. cnss_pr_warn("Failed to find qrtr_node_id err=%d\n", ret);
  222. plat_priv->qrtr_node_id = 0;
  223. plat_priv->wlfw_service_instance_id = 0;
  224. } else {
  225. plat_priv->wlfw_service_instance_id = plat_priv->qrtr_node_id +
  226. QRTR_NODE_FW_ID_BASE;
  227. cnss_pr_dbg("service_instance_id=0x%x\n",
  228. plat_priv->wlfw_service_instance_id);
  229. }
  230. }
  231. static inline int
  232. cnss_get_pld_bus_ops_name(struct cnss_plat_data *plat_priv)
  233. {
  234. return of_property_read_string(plat_priv->plat_dev->dev.of_node,
  235. "qcom,pld_bus_ops_name",
  236. &plat_priv->pld_bus_ops_name);
  237. }
  238. #else
  239. static void cnss_init_plat_env_count(void)
  240. {
  241. }
  242. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  243. struct cnss_plat_data *plat_priv)
  244. {
  245. plat_env = plat_priv;
  246. }
  247. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  248. {
  249. return plat_env;
  250. }
  251. static void cnss_clear_plat_priv(struct cnss_plat_data *plat_priv)
  252. {
  253. plat_env = NULL;
  254. }
  255. static int cnss_set_device_name(struct cnss_plat_data *plat_priv)
  256. {
  257. snprintf(plat_priv->device_name, sizeof(plat_priv->device_name),
  258. "wlan");
  259. return 0;
  260. }
  261. static int cnss_plat_env_available(void)
  262. {
  263. return 0;
  264. }
  265. struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num)
  266. {
  267. return cnss_bus_dev_to_plat_priv(NULL);
  268. }
  269. void cnss_get_qrtr_info(struct cnss_plat_data *plat_priv)
  270. {
  271. }
  272. static int
  273. cnss_get_pld_bus_ops_name(struct cnss_plat_data *plat_priv)
  274. {
  275. return 0;
  276. }
  277. #endif
  278. void cnss_get_sleep_clk_supported(struct cnss_plat_data *plat_priv)
  279. {
  280. plat_priv->sleep_clk = of_property_read_bool(plat_priv->dev_node,
  281. "qcom,sleep-clk-support");
  282. cnss_pr_dbg("qcom,sleep-clk-support is %d\n",
  283. plat_priv->sleep_clk);
  284. }
  285. void cnss_get_bwscal_info(struct cnss_plat_data *plat_priv)
  286. {
  287. plat_priv->no_bwscale = of_property_read_bool(plat_priv->dev_node,
  288. "qcom,no-bwscale");
  289. }
  290. static inline int
  291. cnss_get_rc_num(struct cnss_plat_data *plat_priv)
  292. {
  293. return of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  294. "qcom,wlan-rc-num", &plat_priv->rc_num);
  295. }
  296. bool cnss_is_dual_wlan_enabled(void)
  297. {
  298. return IS_ENABLED(CONFIG_CNSS_SUPPORT_DUAL_DEV);
  299. }
  300. /**
  301. * cnss_get_mem_seg_count - Get segment count of memory
  302. * @type: memory type
  303. * @seg: segment count
  304. *
  305. * Return: 0 on success, negative value on failure
  306. */
  307. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  308. {
  309. struct cnss_plat_data *plat_priv;
  310. plat_priv = cnss_get_plat_priv(NULL);
  311. if (!plat_priv)
  312. return -ENODEV;
  313. switch (type) {
  314. case CNSS_REMOTE_MEM_TYPE_FW:
  315. *seg = plat_priv->fw_mem_seg_len;
  316. break;
  317. case CNSS_REMOTE_MEM_TYPE_QDSS:
  318. *seg = plat_priv->qdss_mem_seg_len;
  319. break;
  320. default:
  321. return -EINVAL;
  322. }
  323. return 0;
  324. }
  325. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  326. /**
  327. * cnss_get_wifi_kobject -return wifi kobject
  328. * Return: Null, to maintain driver comnpatibilty
  329. */
  330. struct kobject *cnss_get_wifi_kobj(struct device *dev)
  331. {
  332. struct cnss_plat_data *plat_priv;
  333. plat_priv = cnss_get_plat_priv(NULL);
  334. if (!plat_priv)
  335. return NULL;
  336. return plat_priv->wifi_kobj;
  337. }
  338. EXPORT_SYMBOL(cnss_get_wifi_kobj);
  339. /**
  340. * cnss_get_mem_segment_info - Get memory info of different type
  341. * @type: memory type
  342. * @segment: array to save the segment info
  343. * @seg: segment count
  344. *
  345. * Return: 0 on success, negative value on failure
  346. */
  347. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  348. struct cnss_mem_segment segment[],
  349. u32 segment_count)
  350. {
  351. struct cnss_plat_data *plat_priv;
  352. u32 i;
  353. plat_priv = cnss_get_plat_priv(NULL);
  354. if (!plat_priv)
  355. return -ENODEV;
  356. switch (type) {
  357. case CNSS_REMOTE_MEM_TYPE_FW:
  358. if (segment_count > plat_priv->fw_mem_seg_len)
  359. segment_count = plat_priv->fw_mem_seg_len;
  360. for (i = 0; i < segment_count; i++) {
  361. segment[i].size = plat_priv->fw_mem[i].size;
  362. segment[i].va = plat_priv->fw_mem[i].va;
  363. segment[i].pa = plat_priv->fw_mem[i].pa;
  364. }
  365. break;
  366. case CNSS_REMOTE_MEM_TYPE_QDSS:
  367. if (segment_count > plat_priv->qdss_mem_seg_len)
  368. segment_count = plat_priv->qdss_mem_seg_len;
  369. for (i = 0; i < segment_count; i++) {
  370. segment[i].size = plat_priv->qdss_mem[i].size;
  371. segment[i].va = plat_priv->qdss_mem[i].va;
  372. segment[i].pa = plat_priv->qdss_mem[i].pa;
  373. }
  374. break;
  375. default:
  376. return -EINVAL;
  377. }
  378. return 0;
  379. }
  380. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  381. static int cnss_get_audio_iommu_domain(struct cnss_plat_data *plat_priv)
  382. {
  383. struct device_node *audio_ion_node;
  384. struct platform_device *audio_ion_pdev;
  385. audio_ion_node = of_find_compatible_node(NULL, NULL,
  386. "qcom,msm-audio-ion");
  387. if (!audio_ion_node) {
  388. cnss_pr_err("Unable to get Audio ion node");
  389. return -EINVAL;
  390. }
  391. audio_ion_pdev = of_find_device_by_node(audio_ion_node);
  392. of_node_put(audio_ion_node);
  393. if (!audio_ion_pdev) {
  394. cnss_pr_err("Unable to get Audio ion platform device");
  395. return -EINVAL;
  396. }
  397. plat_priv->audio_iommu_domain =
  398. iommu_get_domain_for_dev(&audio_ion_pdev->dev);
  399. put_device(&audio_ion_pdev->dev);
  400. if (!plat_priv->audio_iommu_domain) {
  401. cnss_pr_err("Unable to get Audio ion iommu domain");
  402. return -EINVAL;
  403. }
  404. return 0;
  405. }
  406. bool cnss_get_audio_shared_iommu_group_cap(struct device *dev)
  407. {
  408. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  409. struct device_node *audio_ion_node;
  410. struct device_node *cnss_iommu_group_node;
  411. struct device_node *audio_iommu_group_node;
  412. if (!plat_priv)
  413. return false;
  414. audio_ion_node = of_find_compatible_node(NULL, NULL,
  415. "qcom,msm-audio-ion");
  416. if (!audio_ion_node) {
  417. cnss_pr_err("Unable to get Audio ion node");
  418. return false;
  419. }
  420. audio_iommu_group_node = of_parse_phandle(audio_ion_node,
  421. "qcom,iommu-group", 0);
  422. of_node_put(audio_ion_node);
  423. if (!audio_iommu_group_node) {
  424. cnss_pr_err("Unable to get audio iommu group phandle");
  425. return false;
  426. }
  427. of_node_put(audio_iommu_group_node);
  428. cnss_iommu_group_node = of_parse_phandle(dev->of_node,
  429. "qcom,iommu-group", 0);
  430. if (!cnss_iommu_group_node) {
  431. cnss_pr_err("Unable to get cnss iommu group phandle");
  432. return false;
  433. }
  434. of_node_put(cnss_iommu_group_node);
  435. if (cnss_iommu_group_node == audio_iommu_group_node) {
  436. plat_priv->is_audio_shared_iommu_group = true;
  437. cnss_pr_info("CNSS and Audio share IOMMU group");
  438. } else {
  439. cnss_pr_info("CNSS and Audio do not share IOMMU group");
  440. }
  441. return plat_priv->is_audio_shared_iommu_group;
  442. }
  443. EXPORT_SYMBOL(cnss_get_audio_shared_iommu_group_cap);
  444. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  445. enum cnss_feature_v01 feature)
  446. {
  447. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  448. return -EINVAL;
  449. plat_priv->feature_list |= 1 << feature;
  450. return 0;
  451. }
  452. int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
  453. enum cnss_feature_v01 feature)
  454. {
  455. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  456. return -EINVAL;
  457. plat_priv->feature_list &= ~(1 << feature);
  458. return 0;
  459. }
  460. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  461. u64 *feature_list)
  462. {
  463. if (unlikely(!plat_priv))
  464. return -EINVAL;
  465. *feature_list = plat_priv->feature_list;
  466. return 0;
  467. }
  468. size_t cnss_get_platform_name(struct cnss_plat_data *plat_priv,
  469. char *buf, const size_t buf_len)
  470. {
  471. if (unlikely(!plat_priv || !buf || !buf_len))
  472. return 0;
  473. if (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  474. "platform-name-required")) {
  475. struct device_node *root;
  476. root = of_find_node_by_path("/");
  477. if (root) {
  478. const char *model;
  479. size_t model_len;
  480. model = of_get_property(root, "model", NULL);
  481. if (model) {
  482. model_len = strlcpy(buf, model, buf_len);
  483. cnss_pr_dbg("Platform name: %s (%zu)\n",
  484. buf, model_len);
  485. return model_len;
  486. }
  487. }
  488. }
  489. return 0;
  490. }
  491. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  492. {
  493. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  494. return;
  495. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  496. plat_priv->driver_state,
  497. atomic_read(&plat_priv->pm_count));
  498. pm_stay_awake(&plat_priv->plat_dev->dev);
  499. }
  500. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  501. {
  502. int r = atomic_dec_return(&plat_priv->pm_count);
  503. WARN_ON(r < 0);
  504. if (r != 0)
  505. return;
  506. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  507. plat_priv->driver_state,
  508. atomic_read(&plat_priv->pm_count));
  509. pm_relax(&plat_priv->plat_dev->dev);
  510. }
  511. int cnss_get_fw_files_for_target(struct device *dev,
  512. struct cnss_fw_files *pfw_files,
  513. u32 target_type, u32 target_version)
  514. {
  515. if (!pfw_files)
  516. return -ENODEV;
  517. switch (target_version) {
  518. case QCA6174_REV3_VERSION:
  519. case QCA6174_REV3_2_VERSION:
  520. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  521. break;
  522. default:
  523. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  524. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  525. target_type, target_version);
  526. break;
  527. }
  528. return 0;
  529. }
  530. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  531. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  532. {
  533. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  534. if (!plat_priv)
  535. return -ENODEV;
  536. if (!cap)
  537. return -EINVAL;
  538. *cap = plat_priv->cap;
  539. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  540. return 0;
  541. }
  542. EXPORT_SYMBOL(cnss_get_platform_cap);
  543. /**
  544. * cnss_get_fw_cap - Check whether FW supports specific capability or not
  545. * @dev: Device
  546. * @fw_cap: FW Capability which needs to be checked
  547. *
  548. * Return: TRUE if supported, FALSE on failure or if not supported
  549. */
  550. bool cnss_get_fw_cap(struct device *dev, enum cnss_fw_caps fw_cap)
  551. {
  552. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  553. bool is_supported = false;
  554. if (!plat_priv)
  555. return is_supported;
  556. if (!plat_priv->fw_caps)
  557. return is_supported;
  558. switch (fw_cap) {
  559. case CNSS_FW_CAP_DIRECT_LINK_SUPPORT:
  560. is_supported = !!(plat_priv->fw_caps &
  561. QMI_WLFW_DIRECT_LINK_SUPPORT_V01);
  562. break;
  563. case CNSS_FW_CAP_CALDB_SEG_DDR_SUPPORT:
  564. is_supported = !!(plat_priv->fw_caps &
  565. QMI_WLFW_CALDB_SEG_DDR_SUPPORT_V01);
  566. break;
  567. default:
  568. cnss_pr_err("Invalid FW Capability: 0x%x\n", fw_cap);
  569. }
  570. cnss_pr_dbg("FW Capability 0x%x is %s\n", fw_cap,
  571. is_supported ? "supported" : "not supported");
  572. return is_supported;
  573. }
  574. EXPORT_SYMBOL(cnss_get_fw_cap);
  575. /**
  576. * cnss_audio_is_direct_link_supported - Check whether Audio can be used for direct link support
  577. * @dev: Device
  578. *
  579. * Return: TRUE if supported, FALSE on failure or if not supported
  580. */
  581. bool cnss_audio_is_direct_link_supported(struct device *dev)
  582. {
  583. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  584. bool is_supported = false;
  585. if (!plat_priv) {
  586. cnss_pr_err("plat_priv not available to check audio direct link cap\n");
  587. return is_supported;
  588. }
  589. if (cnss_get_audio_iommu_domain(plat_priv) == 0)
  590. is_supported = true;
  591. return is_supported;
  592. }
  593. EXPORT_SYMBOL(cnss_audio_is_direct_link_supported);
  594. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  595. {
  596. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  597. if (!plat_priv)
  598. return;
  599. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  600. }
  601. EXPORT_SYMBOL(cnss_request_pm_qos);
  602. void cnss_remove_pm_qos(struct device *dev)
  603. {
  604. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  605. if (!plat_priv)
  606. return;
  607. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  608. }
  609. EXPORT_SYMBOL(cnss_remove_pm_qos);
  610. int cnss_wlan_enable(struct device *dev,
  611. struct cnss_wlan_enable_cfg *config,
  612. enum cnss_driver_mode mode,
  613. const char *host_version)
  614. {
  615. int ret = 0;
  616. struct cnss_plat_data *plat_priv;
  617. if (!dev) {
  618. cnss_pr_err("Invalid dev pointer\n");
  619. return -EINVAL;
  620. }
  621. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  622. if (!plat_priv)
  623. return -ENODEV;
  624. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  625. return 0;
  626. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  627. return 0;
  628. if (!config || !host_version) {
  629. cnss_pr_err("Invalid config or host_version pointer\n");
  630. return -EINVAL;
  631. }
  632. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  633. mode, config, host_version);
  634. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  635. goto skip_cfg;
  636. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  637. config->send_msi_ce = true;
  638. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  639. if (ret)
  640. goto out;
  641. skip_cfg:
  642. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  643. out:
  644. return ret;
  645. }
  646. EXPORT_SYMBOL(cnss_wlan_enable);
  647. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  648. {
  649. int ret = 0;
  650. struct cnss_plat_data *plat_priv;
  651. if (!dev) {
  652. cnss_pr_err("Invalid dev pointer\n");
  653. return -EINVAL;
  654. }
  655. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  656. if (!plat_priv)
  657. return -ENODEV;
  658. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  659. return 0;
  660. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  661. return 0;
  662. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  663. cnss_bus_free_qdss_mem(plat_priv);
  664. return ret;
  665. }
  666. EXPORT_SYMBOL(cnss_wlan_disable);
  667. #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
  668. int cnss_iommu_map(struct iommu_domain *domain,
  669. unsigned long iova, phys_addr_t paddr, size_t size, int prot)
  670. {
  671. return iommu_map(domain, iova, paddr, size, prot);
  672. }
  673. #else
  674. int cnss_iommu_map(struct iommu_domain *domain,
  675. unsigned long iova, phys_addr_t paddr, size_t size, int prot)
  676. {
  677. return iommu_map(domain, iova, paddr, size, prot, GFP_KERNEL);
  678. }
  679. #endif
  680. int cnss_audio_smmu_map(struct device *dev, phys_addr_t paddr,
  681. dma_addr_t iova, size_t size)
  682. {
  683. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  684. uint32_t page_offset;
  685. if (!plat_priv)
  686. return -ENODEV;
  687. if (!plat_priv->audio_iommu_domain)
  688. return -EINVAL;
  689. if (plat_priv->is_audio_shared_iommu_group)
  690. return 0;
  691. page_offset = iova & (PAGE_SIZE - 1);
  692. if (page_offset + size > PAGE_SIZE)
  693. size += PAGE_SIZE;
  694. iova -= page_offset;
  695. paddr -= page_offset;
  696. return cnss_iommu_map(plat_priv->audio_iommu_domain, iova, paddr,
  697. roundup(size, PAGE_SIZE), IOMMU_READ |
  698. IOMMU_WRITE | IOMMU_CACHE);
  699. }
  700. EXPORT_SYMBOL(cnss_audio_smmu_map);
  701. void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova, size_t size)
  702. {
  703. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  704. uint32_t page_offset;
  705. if (!plat_priv || !plat_priv->audio_iommu_domain ||
  706. plat_priv->is_audio_shared_iommu_group)
  707. return;
  708. page_offset = iova & (PAGE_SIZE - 1);
  709. if (page_offset + size > PAGE_SIZE)
  710. size += PAGE_SIZE;
  711. iova -= page_offset;
  712. iommu_unmap(plat_priv->audio_iommu_domain, iova,
  713. roundup(size, PAGE_SIZE));
  714. }
  715. EXPORT_SYMBOL(cnss_audio_smmu_unmap);
  716. int cnss_get_fw_lpass_shared_mem(struct device *dev, dma_addr_t *iova,
  717. size_t *size)
  718. {
  719. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  720. uint8_t i;
  721. if (!plat_priv)
  722. return -EINVAL;
  723. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  724. if (plat_priv->fw_mem[i].type ==
  725. QMI_WLFW_MEM_LPASS_SHARED_V01) {
  726. *iova = plat_priv->fw_mem[i].pa;
  727. *size = plat_priv->fw_mem[i].size;
  728. return 0;
  729. }
  730. }
  731. return -EINVAL;
  732. }
  733. EXPORT_SYMBOL(cnss_get_fw_lpass_shared_mem);
  734. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  735. u32 data_len, u8 *output)
  736. {
  737. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  738. int ret = 0;
  739. if (!plat_priv) {
  740. cnss_pr_err("plat_priv is NULL!\n");
  741. return -EINVAL;
  742. }
  743. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  744. return 0;
  745. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  746. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  747. plat_priv->driver_state);
  748. ret = -EINVAL;
  749. goto out;
  750. }
  751. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  752. data_len, output);
  753. out:
  754. return ret;
  755. }
  756. EXPORT_SYMBOL(cnss_athdiag_read);
  757. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  758. u32 data_len, u8 *input)
  759. {
  760. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  761. int ret = 0;
  762. if (!plat_priv) {
  763. cnss_pr_err("plat_priv is NULL!\n");
  764. return -EINVAL;
  765. }
  766. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  767. return 0;
  768. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  769. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  770. plat_priv->driver_state);
  771. ret = -EINVAL;
  772. goto out;
  773. }
  774. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  775. data_len, input);
  776. out:
  777. return ret;
  778. }
  779. EXPORT_SYMBOL(cnss_athdiag_write);
  780. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  781. {
  782. struct cnss_plat_data *plat_priv;
  783. if (!dev) {
  784. cnss_pr_err("Invalid dev pointer\n");
  785. return -EINVAL;
  786. }
  787. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  788. if (!plat_priv)
  789. return -ENODEV;
  790. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  791. return 0;
  792. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  793. }
  794. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  795. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  796. {
  797. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  798. if (!plat_priv)
  799. return -EINVAL;
  800. if (!plat_priv->fw_pcie_gen_switch) {
  801. cnss_pr_err("Firmware does not support PCIe gen switch\n");
  802. return -EOPNOTSUPP;
  803. }
  804. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  805. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  806. return -EINVAL;
  807. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  808. plat_priv->pcie_gen_speed = pcie_gen_speed;
  809. return 0;
  810. }
  811. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  812. static bool cnss_is_aux_support_enabled(struct cnss_plat_data *plat_priv)
  813. {
  814. switch (plat_priv->device_id) {
  815. case PEACH_DEVICE_ID:
  816. if (!plat_priv->fw_aux_uc_support) {
  817. cnss_pr_dbg("FW does not support aux uc capability\n");
  818. return false;
  819. }
  820. break;
  821. default:
  822. cnss_pr_dbg("Host does not support aux uc capability\n");
  823. return false;
  824. }
  825. return true;
  826. }
  827. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  828. {
  829. int ret = 0;
  830. if (!plat_priv)
  831. return -ENODEV;
  832. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  833. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  834. if (ret)
  835. goto out;
  836. cnss_bus_load_tme_patch(plat_priv);
  837. cnss_wlfw_tme_patch_dnld_send_sync(plat_priv,
  838. WLFW_TME_LITE_PATCH_FILE_V01);
  839. if (plat_priv->hds_enabled)
  840. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  841. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  842. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  843. plat_priv->ctrl_params.bdf_type = CNSS_BDF_BIN;
  844. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  845. plat_priv->ctrl_params.bdf_type);
  846. if (ret)
  847. goto out;
  848. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  849. return 0;
  850. ret = cnss_bus_load_m3(plat_priv);
  851. if (ret)
  852. goto out;
  853. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  854. if (ret)
  855. goto out;
  856. if (cnss_is_aux_support_enabled(plat_priv)) {
  857. ret = cnss_bus_load_aux(plat_priv);
  858. if (ret)
  859. goto out;
  860. ret = cnss_wlfw_aux_dnld_send_sync(plat_priv);
  861. if (ret)
  862. goto out;
  863. }
  864. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  865. return 0;
  866. out:
  867. return ret;
  868. }
  869. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  870. {
  871. int ret = 0;
  872. if (!plat_priv->antenna) {
  873. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  874. if (ret)
  875. goto out;
  876. }
  877. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  878. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  879. if (ret)
  880. goto out;
  881. }
  882. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  883. if (ret)
  884. goto out;
  885. return 0;
  886. out:
  887. return ret;
  888. }
  889. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  890. {
  891. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  892. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  893. }
  894. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  895. {
  896. u32 i;
  897. int ret = 0;
  898. struct cnss_plat_ipc_daemon_config *cfg;
  899. ret = cnss_qmi_get_dms_mac(plat_priv);
  900. if (ret == 0 && plat_priv->dms.mac_valid)
  901. goto qmi_send;
  902. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  903. * Thus assert on failure to get MAC from DMS even after retries
  904. */
  905. if (plat_priv->use_nv_mac) {
  906. /* Check if Daemon says platform support DMS MAC provisioning */
  907. cfg = cnss_plat_ipc_qmi_daemon_config();
  908. if (cfg) {
  909. if (!cfg->dms_mac_addr_supported) {
  910. cnss_pr_err("DMS MAC address not supported\n");
  911. CNSS_ASSERT(0);
  912. return -EINVAL;
  913. }
  914. }
  915. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  916. if (plat_priv->dms.mac_valid)
  917. break;
  918. ret = cnss_qmi_get_dms_mac(plat_priv);
  919. if (ret == 0)
  920. break;
  921. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  922. }
  923. if (!plat_priv->dms.mac_valid) {
  924. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  925. CNSS_ASSERT(0);
  926. return -EINVAL;
  927. }
  928. }
  929. qmi_send:
  930. if (plat_priv->dms.mac_valid)
  931. ret =
  932. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  933. ARRAY_SIZE(plat_priv->dms.mac));
  934. return ret;
  935. }
  936. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  937. enum cnss_cal_db_op op, u32 *size)
  938. {
  939. int ret = 0;
  940. u32 timeout = cnss_get_timeout(plat_priv,
  941. CNSS_TIMEOUT_DAEMON_CONNECTION);
  942. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  943. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  944. if (op >= CNSS_CAL_DB_INVALID_OP)
  945. return -EINVAL;
  946. if (!plat_priv->cbc_file_download) {
  947. cnss_pr_info("CAL DB file not required as per BDF\n");
  948. return 0;
  949. }
  950. if (*size == 0) {
  951. cnss_pr_err("Invalid cal file size\n");
  952. return -EINVAL;
  953. }
  954. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  955. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  956. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  957. msecs_to_jiffies(timeout));
  958. if (!ret) {
  959. cnss_pr_err("Daemon not yet connected\n");
  960. CNSS_ASSERT(0);
  961. return ret;
  962. }
  963. }
  964. if (!plat_priv->cal_mem->va) {
  965. cnss_pr_err("CAL DB Memory not setup for FW\n");
  966. return -EINVAL;
  967. }
  968. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  969. if (op == CNSS_CAL_DB_DOWNLOAD) {
  970. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  971. ret = cnss_plat_ipc_qmi_file_download(client_id,
  972. CNSS_CAL_DB_FILE_NAME,
  973. plat_priv->cal_mem->va,
  974. size);
  975. } else {
  976. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  977. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  978. CNSS_CAL_DB_FILE_NAME,
  979. plat_priv->cal_mem->va,
  980. *size);
  981. }
  982. if (ret)
  983. cnss_pr_err("Cal DB file %s %s failure\n",
  984. CNSS_CAL_DB_FILE_NAME,
  985. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  986. else
  987. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  988. CNSS_CAL_DB_FILE_NAME,
  989. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  990. *size);
  991. return ret;
  992. }
  993. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  994. {
  995. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  996. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  997. return -EINVAL;
  998. }
  999. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  1000. &plat_priv->cal_file_size);
  1001. }
  1002. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  1003. u32 *cal_file_size)
  1004. {
  1005. /* To download pass the total size of cal DB mem allocated.
  1006. * After cal file is download to mem, its size is updated in
  1007. * return pointer
  1008. */
  1009. *cal_file_size = plat_priv->cal_mem->size;
  1010. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  1011. cal_file_size);
  1012. }
  1013. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  1014. {
  1015. int ret = 0;
  1016. u32 cal_file_size = 0;
  1017. if (!plat_priv)
  1018. return -ENODEV;
  1019. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1020. cnss_pr_err("Reboot is in progress, ignore FW ready\n");
  1021. return -EINVAL;
  1022. }
  1023. cnss_pr_dbg("Processing FW Init Done..\n");
  1024. del_timer(&plat_priv->fw_boot_timer);
  1025. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  1026. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  1027. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  1028. cnss_send_subsys_restart_level_msg(plat_priv);
  1029. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  1030. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  1031. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1032. }
  1033. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  1034. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  1035. CNSS_WALTEST);
  1036. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1037. cnss_request_antenna_sharing(plat_priv);
  1038. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  1039. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  1040. plat_priv->cal_time = jiffies;
  1041. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  1042. CNSS_CALIBRATION);
  1043. } else {
  1044. ret = cnss_setup_dms_mac(plat_priv);
  1045. ret = cnss_bus_call_driver_probe(plat_priv);
  1046. }
  1047. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1048. goto out;
  1049. else if (ret)
  1050. goto shutdown;
  1051. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  1052. return 0;
  1053. shutdown:
  1054. cnss_bus_dev_shutdown(plat_priv);
  1055. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  1056. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  1057. out:
  1058. return ret;
  1059. }
  1060. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  1061. {
  1062. switch (type) {
  1063. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1064. return "SERVER_ARRIVE";
  1065. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1066. return "SERVER_EXIT";
  1067. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1068. return "REQUEST_MEM";
  1069. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1070. return "FW_MEM_READY";
  1071. case CNSS_DRIVER_EVENT_FW_READY:
  1072. return "FW_READY";
  1073. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1074. return "COLD_BOOT_CAL_START";
  1075. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1076. return "COLD_BOOT_CAL_DONE";
  1077. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1078. return "REGISTER_DRIVER";
  1079. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1080. return "UNREGISTER_DRIVER";
  1081. case CNSS_DRIVER_EVENT_RECOVERY:
  1082. return "RECOVERY";
  1083. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1084. return "FORCE_FW_ASSERT";
  1085. case CNSS_DRIVER_EVENT_POWER_UP:
  1086. return "POWER_UP";
  1087. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1088. return "POWER_DOWN";
  1089. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1090. return "IDLE_RESTART";
  1091. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1092. return "IDLE_SHUTDOWN";
  1093. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1094. return "IMS_WFC_CALL_IND";
  1095. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1096. return "WLFW_TWC_CFG_IND";
  1097. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1098. return "QDSS_TRACE_REQ_MEM";
  1099. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1100. return "FW_MEM_FILE_SAVE";
  1101. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1102. return "QDSS_TRACE_FREE";
  1103. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1104. return "QDSS_TRACE_REQ_DATA";
  1105. case CNSS_DRIVER_EVENT_MAX:
  1106. return "EVENT_MAX";
  1107. }
  1108. return "UNKNOWN";
  1109. };
  1110. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  1111. enum cnss_driver_event_type type,
  1112. u32 flags, void *data)
  1113. {
  1114. struct cnss_driver_event *event;
  1115. unsigned long irq_flags;
  1116. int gfp = GFP_KERNEL;
  1117. int ret = 0;
  1118. if (!plat_priv)
  1119. return -ENODEV;
  1120. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  1121. cnss_driver_event_to_str(type), type,
  1122. flags ? "-sync" : "", plat_priv->driver_state, flags);
  1123. if (type >= CNSS_DRIVER_EVENT_MAX) {
  1124. cnss_pr_err("Invalid Event type: %d, can't post", type);
  1125. return -EINVAL;
  1126. }
  1127. if (in_interrupt() || irqs_disabled())
  1128. gfp = GFP_ATOMIC;
  1129. event = kzalloc(sizeof(*event), gfp);
  1130. if (!event)
  1131. return -ENOMEM;
  1132. cnss_pm_stay_awake(plat_priv);
  1133. event->type = type;
  1134. event->data = data;
  1135. init_completion(&event->complete);
  1136. event->ret = CNSS_EVENT_PENDING;
  1137. event->sync = !!(flags & CNSS_EVENT_SYNC);
  1138. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  1139. list_add_tail(&event->list, &plat_priv->event_list);
  1140. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  1141. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  1142. if (!(flags & CNSS_EVENT_SYNC))
  1143. goto out;
  1144. if (flags & CNSS_EVENT_UNKILLABLE)
  1145. wait_for_completion(&event->complete);
  1146. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  1147. ret = wait_for_completion_killable(&event->complete);
  1148. else
  1149. ret = wait_for_completion_interruptible(&event->complete);
  1150. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  1151. cnss_driver_event_to_str(type), type,
  1152. plat_priv->driver_state, ret, event->ret);
  1153. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  1154. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  1155. event->sync = false;
  1156. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  1157. ret = -EINTR;
  1158. goto out;
  1159. }
  1160. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  1161. ret = event->ret;
  1162. kfree(event);
  1163. out:
  1164. cnss_pm_relax(plat_priv);
  1165. return ret;
  1166. }
  1167. /**
  1168. * cnss_get_timeout - Get timeout for corresponding type.
  1169. * @plat_priv: Pointer to platform driver context.
  1170. * @cnss_timeout_type: Timeout type.
  1171. *
  1172. * Return: Timeout in milliseconds.
  1173. */
  1174. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  1175. enum cnss_timeout_type timeout_type)
  1176. {
  1177. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  1178. switch (timeout_type) {
  1179. case CNSS_TIMEOUT_QMI:
  1180. return qmi_timeout;
  1181. case CNSS_TIMEOUT_POWER_UP:
  1182. return (qmi_timeout << 2);
  1183. case CNSS_TIMEOUT_IDLE_RESTART:
  1184. /* In idle restart power up sequence, we have fw_boot_timer to
  1185. * handle FW initialization failure.
  1186. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  1187. * account for FW dump collection and FW re-initialization on
  1188. * retry.
  1189. */
  1190. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  1191. case CNSS_TIMEOUT_CALIBRATION:
  1192. /* Similar to mission mode, in CBC if FW init fails
  1193. * fw recovery is tried. Thus return 2x the CBC timeout.
  1194. */
  1195. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  1196. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  1197. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  1198. case CNSS_TIMEOUT_RDDM:
  1199. return CNSS_RDDM_TIMEOUT_MS;
  1200. case CNSS_TIMEOUT_RECOVERY:
  1201. return RECOVERY_TIMEOUT;
  1202. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  1203. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  1204. default:
  1205. return qmi_timeout;
  1206. }
  1207. }
  1208. unsigned int cnss_get_boot_timeout(struct device *dev)
  1209. {
  1210. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1211. if (!plat_priv) {
  1212. cnss_pr_err("plat_priv is NULL\n");
  1213. return 0;
  1214. }
  1215. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  1216. }
  1217. EXPORT_SYMBOL(cnss_get_boot_timeout);
  1218. int cnss_power_up(struct device *dev)
  1219. {
  1220. int ret = 0;
  1221. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1222. unsigned int timeout;
  1223. if (!plat_priv) {
  1224. cnss_pr_err("plat_priv is NULL\n");
  1225. return -ENODEV;
  1226. }
  1227. cnss_pr_dbg("Powering up device\n");
  1228. ret = cnss_driver_event_post(plat_priv,
  1229. CNSS_DRIVER_EVENT_POWER_UP,
  1230. CNSS_EVENT_SYNC, NULL);
  1231. if (ret)
  1232. goto out;
  1233. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1234. goto out;
  1235. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  1236. reinit_completion(&plat_priv->power_up_complete);
  1237. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  1238. msecs_to_jiffies(timeout));
  1239. if (!ret) {
  1240. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  1241. timeout);
  1242. ret = -EAGAIN;
  1243. goto out;
  1244. }
  1245. return 0;
  1246. out:
  1247. return ret;
  1248. }
  1249. EXPORT_SYMBOL(cnss_power_up);
  1250. int cnss_power_down(struct device *dev)
  1251. {
  1252. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1253. if (!plat_priv) {
  1254. cnss_pr_err("plat_priv is NULL\n");
  1255. return -ENODEV;
  1256. }
  1257. cnss_pr_dbg("Powering down device\n");
  1258. return cnss_driver_event_post(plat_priv,
  1259. CNSS_DRIVER_EVENT_POWER_DOWN,
  1260. CNSS_EVENT_SYNC, NULL);
  1261. }
  1262. EXPORT_SYMBOL(cnss_power_down);
  1263. int cnss_idle_restart(struct device *dev)
  1264. {
  1265. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1266. unsigned int timeout;
  1267. int ret = 0;
  1268. if (!plat_priv) {
  1269. cnss_pr_err("plat_priv is NULL\n");
  1270. return -ENODEV;
  1271. }
  1272. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  1273. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  1274. return -EBUSY;
  1275. }
  1276. cnss_pr_dbg("Doing idle restart\n");
  1277. reinit_completion(&plat_priv->power_up_complete);
  1278. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1279. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  1280. ret = -EINVAL;
  1281. goto out;
  1282. }
  1283. ret = cnss_driver_event_post(plat_priv,
  1284. CNSS_DRIVER_EVENT_IDLE_RESTART,
  1285. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  1286. if (ret == -EINTR && plat_priv->device_id != QCA6174_DEVICE_ID)
  1287. cnss_pr_err("Idle restart has been interrupted but device power up is still in progress");
  1288. else if (ret)
  1289. goto out;
  1290. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1291. ret = cnss_bus_call_driver_probe(plat_priv);
  1292. goto out;
  1293. }
  1294. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  1295. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  1296. msecs_to_jiffies(timeout));
  1297. if (plat_priv->power_up_error) {
  1298. ret = plat_priv->power_up_error;
  1299. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1300. cnss_pr_dbg("Power up error:%d, exiting\n",
  1301. plat_priv->power_up_error);
  1302. goto out;
  1303. }
  1304. if (!ret) {
  1305. /* This exception occurs after attempting retry of FW recovery.
  1306. * Thus we can safely power off the device.
  1307. */
  1308. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  1309. timeout);
  1310. ret = -ETIMEDOUT;
  1311. cnss_power_down(dev);
  1312. CNSS_ASSERT(0);
  1313. goto out;
  1314. }
  1315. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1316. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  1317. del_timer(&plat_priv->fw_boot_timer);
  1318. ret = -EINVAL;
  1319. goto out;
  1320. }
  1321. /* In non-DRV mode, remove MHI satellite configuration. Switching to
  1322. * non-DRV is supported only once after device reboots and before wifi
  1323. * is turned on. We do not allow switching back to DRV.
  1324. * To bring device back into DRV, user needs to reboot device.
  1325. */
  1326. if (test_bit(DISABLE_DRV, &plat_priv->ctrl_params.quirks)) {
  1327. cnss_pr_dbg("DRV is disabled\n");
  1328. cnss_bus_disable_mhi_satellite_cfg(plat_priv);
  1329. }
  1330. mutex_unlock(&plat_priv->driver_ops_lock);
  1331. return 0;
  1332. out:
  1333. mutex_unlock(&plat_priv->driver_ops_lock);
  1334. return ret;
  1335. }
  1336. EXPORT_SYMBOL(cnss_idle_restart);
  1337. int cnss_idle_shutdown(struct device *dev)
  1338. {
  1339. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1340. if (!plat_priv) {
  1341. cnss_pr_err("plat_priv is NULL\n");
  1342. return -ENODEV;
  1343. }
  1344. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  1345. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  1346. return -EAGAIN;
  1347. }
  1348. cnss_pr_dbg("Doing idle shutdown\n");
  1349. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) ||
  1350. test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) {
  1351. cnss_pr_dbg("Recovery in progress. Ignore IDLE Shutdown\n");
  1352. return -EBUSY;
  1353. }
  1354. return cnss_driver_event_post(plat_priv,
  1355. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  1356. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  1357. }
  1358. EXPORT_SYMBOL(cnss_idle_shutdown);
  1359. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  1360. {
  1361. int ret = 0;
  1362. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1363. if (ret < 0) {
  1364. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  1365. goto out;
  1366. }
  1367. ret = cnss_get_clk(plat_priv);
  1368. if (ret) {
  1369. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  1370. goto put_vreg;
  1371. }
  1372. ret = cnss_get_pinctrl(plat_priv);
  1373. if (ret) {
  1374. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  1375. goto put_clk;
  1376. }
  1377. return 0;
  1378. put_clk:
  1379. cnss_put_clk(plat_priv);
  1380. put_vreg:
  1381. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1382. out:
  1383. return ret;
  1384. }
  1385. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  1386. {
  1387. cnss_put_clk(plat_priv);
  1388. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1389. }
  1390. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1391. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  1392. unsigned long code,
  1393. void *ss_handle)
  1394. {
  1395. struct cnss_plat_data *plat_priv =
  1396. container_of(nb, struct cnss_plat_data, modem_nb);
  1397. struct cnss_esoc_info *esoc_info;
  1398. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  1399. if (!plat_priv)
  1400. return NOTIFY_DONE;
  1401. esoc_info = &plat_priv->esoc_info;
  1402. if (code == SUBSYS_AFTER_POWERUP)
  1403. esoc_info->modem_current_status = 1;
  1404. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  1405. esoc_info->modem_current_status = 0;
  1406. else
  1407. return NOTIFY_DONE;
  1408. if (!cnss_bus_call_driver_modem_status(plat_priv,
  1409. esoc_info->modem_current_status))
  1410. return NOTIFY_DONE;
  1411. return NOTIFY_OK;
  1412. }
  1413. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1414. {
  1415. int ret = 0;
  1416. struct device *dev;
  1417. struct cnss_esoc_info *esoc_info;
  1418. struct esoc_desc *esoc_desc;
  1419. const char *client_desc;
  1420. dev = &plat_priv->plat_dev->dev;
  1421. esoc_info = &plat_priv->esoc_info;
  1422. esoc_info->notify_modem_status =
  1423. of_property_read_bool(dev->of_node,
  1424. "qcom,notify-modem-status");
  1425. if (!esoc_info->notify_modem_status)
  1426. goto out;
  1427. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  1428. &client_desc);
  1429. if (ret) {
  1430. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  1431. } else {
  1432. esoc_desc = devm_register_esoc_client(dev, client_desc);
  1433. if (IS_ERR_OR_NULL(esoc_desc)) {
  1434. ret = PTR_RET(esoc_desc);
  1435. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  1436. ret);
  1437. goto out;
  1438. }
  1439. esoc_info->esoc_desc = esoc_desc;
  1440. }
  1441. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  1442. esoc_info->modem_current_status = 0;
  1443. esoc_info->modem_notify_handler =
  1444. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  1445. esoc_info->esoc_desc->name :
  1446. "modem", &plat_priv->modem_nb);
  1447. if (IS_ERR(esoc_info->modem_notify_handler)) {
  1448. ret = PTR_ERR(esoc_info->modem_notify_handler);
  1449. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  1450. ret);
  1451. goto unreg_esoc;
  1452. }
  1453. return 0;
  1454. unreg_esoc:
  1455. if (esoc_info->esoc_desc)
  1456. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1457. out:
  1458. return ret;
  1459. }
  1460. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1461. {
  1462. struct device *dev;
  1463. struct cnss_esoc_info *esoc_info;
  1464. dev = &plat_priv->plat_dev->dev;
  1465. esoc_info = &plat_priv->esoc_info;
  1466. if (esoc_info->notify_modem_status)
  1467. subsys_notif_unregister_notifier
  1468. (esoc_info->modem_notify_handler,
  1469. &plat_priv->modem_nb);
  1470. if (esoc_info->esoc_desc)
  1471. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1472. }
  1473. #else
  1474. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1475. {
  1476. return 0;
  1477. }
  1478. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1479. #endif
  1480. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1481. {
  1482. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1483. int ret = 0;
  1484. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1485. return 0;
  1486. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1487. if (ret)
  1488. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1489. ret);
  1490. return ret;
  1491. }
  1492. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1493. {
  1494. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1495. int ret = 0;
  1496. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1497. return 0;
  1498. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1499. if (ret)
  1500. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1501. ret);
  1502. return ret;
  1503. }
  1504. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1505. {
  1506. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1507. if (sol_gpio->dev_sol_gpio < 0)
  1508. return -EINVAL;
  1509. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1510. }
  1511. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1512. {
  1513. struct cnss_plat_data *plat_priv = data;
  1514. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1515. if (test_bit(CNSS_POWER_OFF, &plat_priv->driver_state)) {
  1516. cnss_pr_dbg("Ignore Dev SOL during device power off");
  1517. return IRQ_HANDLED;
  1518. }
  1519. sol_gpio->dev_sol_counter++;
  1520. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u, dev_sol_val: %d\n",
  1521. irq, sol_gpio->dev_sol_counter,
  1522. cnss_get_dev_sol_value(plat_priv));
  1523. /* Make sure abort current suspend */
  1524. cnss_pm_stay_awake(plat_priv);
  1525. cnss_pm_relax(plat_priv);
  1526. pm_system_wakeup();
  1527. cnss_bus_handle_dev_sol_irq(plat_priv);
  1528. return IRQ_HANDLED;
  1529. }
  1530. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1531. {
  1532. struct device *dev = &plat_priv->plat_dev->dev;
  1533. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1534. int ret = 0;
  1535. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1536. "wlan-dev-sol-gpio", 0);
  1537. if (sol_gpio->dev_sol_gpio < 0)
  1538. goto out;
  1539. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1540. sol_gpio->dev_sol_gpio);
  1541. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1542. if (ret) {
  1543. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1544. ret);
  1545. goto out;
  1546. }
  1547. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1548. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1549. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1550. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1551. if (ret) {
  1552. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1553. goto free_gpio;
  1554. }
  1555. return 0;
  1556. free_gpio:
  1557. gpio_free(sol_gpio->dev_sol_gpio);
  1558. out:
  1559. return ret;
  1560. }
  1561. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1562. {
  1563. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1564. if (sol_gpio->dev_sol_gpio < 0)
  1565. return;
  1566. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1567. gpio_free(sol_gpio->dev_sol_gpio);
  1568. }
  1569. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1570. {
  1571. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1572. if (sol_gpio->host_sol_gpio < 0)
  1573. return -EINVAL;
  1574. if (value)
  1575. cnss_pr_dbg("Assert host SOL GPIO\n");
  1576. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1577. return 0;
  1578. }
  1579. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1580. {
  1581. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1582. if (sol_gpio->host_sol_gpio < 0)
  1583. return -EINVAL;
  1584. return gpio_get_value(sol_gpio->host_sol_gpio);
  1585. }
  1586. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1587. {
  1588. struct device *dev = &plat_priv->plat_dev->dev;
  1589. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1590. int ret = 0;
  1591. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1592. "wlan-host-sol-gpio", 0);
  1593. if (sol_gpio->host_sol_gpio < 0)
  1594. goto out;
  1595. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1596. sol_gpio->host_sol_gpio);
  1597. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1598. if (ret) {
  1599. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1600. ret);
  1601. goto out;
  1602. }
  1603. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1604. return 0;
  1605. out:
  1606. return ret;
  1607. }
  1608. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1609. {
  1610. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1611. if (sol_gpio->host_sol_gpio < 0)
  1612. return;
  1613. gpio_free(sol_gpio->host_sol_gpio);
  1614. }
  1615. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1616. {
  1617. int ret;
  1618. ret = cnss_init_dev_sol_gpio(plat_priv);
  1619. if (ret)
  1620. goto out;
  1621. ret = cnss_init_host_sol_gpio(plat_priv);
  1622. if (ret)
  1623. goto deinit_dev_sol;
  1624. return 0;
  1625. deinit_dev_sol:
  1626. cnss_deinit_dev_sol_gpio(plat_priv);
  1627. out:
  1628. return ret;
  1629. }
  1630. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1631. {
  1632. cnss_deinit_host_sol_gpio(plat_priv);
  1633. cnss_deinit_dev_sol_gpio(plat_priv);
  1634. }
  1635. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1636. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1637. {
  1638. struct cnss_plat_data *plat_priv;
  1639. int ret = 0;
  1640. if (!subsys_desc->dev) {
  1641. cnss_pr_err("dev from subsys_desc is NULL\n");
  1642. return -ENODEV;
  1643. }
  1644. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1645. if (!plat_priv) {
  1646. cnss_pr_err("plat_priv is NULL\n");
  1647. return -ENODEV;
  1648. }
  1649. if (!plat_priv->driver_state) {
  1650. cnss_pr_dbg("subsys powerup is ignored\n");
  1651. return 0;
  1652. }
  1653. ret = cnss_bus_dev_powerup(plat_priv);
  1654. if (ret)
  1655. __pm_relax(plat_priv->recovery_ws);
  1656. return ret;
  1657. }
  1658. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1659. bool force_stop)
  1660. {
  1661. struct cnss_plat_data *plat_priv;
  1662. if (!subsys_desc->dev) {
  1663. cnss_pr_err("dev from subsys_desc is NULL\n");
  1664. return -ENODEV;
  1665. }
  1666. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1667. if (!plat_priv) {
  1668. cnss_pr_err("plat_priv is NULL\n");
  1669. return -ENODEV;
  1670. }
  1671. if (!plat_priv->driver_state) {
  1672. cnss_pr_dbg("subsys shutdown is ignored\n");
  1673. return 0;
  1674. }
  1675. return cnss_bus_dev_shutdown(plat_priv);
  1676. }
  1677. void cnss_device_crashed(struct device *dev)
  1678. {
  1679. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1680. struct cnss_subsys_info *subsys_info;
  1681. if (!plat_priv)
  1682. return;
  1683. subsys_info = &plat_priv->subsys_info;
  1684. if (subsys_info->subsys_device) {
  1685. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1686. subsys_set_crash_status(subsys_info->subsys_device, true);
  1687. subsystem_restart_dev(subsys_info->subsys_device);
  1688. }
  1689. }
  1690. EXPORT_SYMBOL(cnss_device_crashed);
  1691. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1692. {
  1693. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1694. if (!plat_priv) {
  1695. cnss_pr_err("plat_priv is NULL\n");
  1696. return;
  1697. }
  1698. cnss_bus_dev_crash_shutdown(plat_priv);
  1699. }
  1700. static int cnss_subsys_ramdump(int enable,
  1701. const struct subsys_desc *subsys_desc)
  1702. {
  1703. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1704. if (!plat_priv) {
  1705. cnss_pr_err("plat_priv is NULL\n");
  1706. return -ENODEV;
  1707. }
  1708. if (!enable)
  1709. return 0;
  1710. return cnss_bus_dev_ramdump(plat_priv);
  1711. }
  1712. static void cnss_recovery_work_handler(struct work_struct *work)
  1713. {
  1714. }
  1715. #else
  1716. void cnss_recovery_handler(struct cnss_plat_data *plat_priv)
  1717. {
  1718. int ret;
  1719. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1720. if (!plat_priv->recovery_enabled)
  1721. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1722. cnss_bus_dev_shutdown(plat_priv);
  1723. cnss_bus_dev_ramdump(plat_priv);
  1724. /* If recovery is triggered before Host driver registration,
  1725. * avoid device power up because eventually device will be
  1726. * power up as part of driver registration.
  1727. */
  1728. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state) ||
  1729. !test_bit(CNSS_DRIVER_REGISTERED, &plat_priv->driver_state)) {
  1730. cnss_pr_dbg("Host driver not registered yet, ignore Device Power Up, 0x%lx\n",
  1731. plat_priv->driver_state);
  1732. return;
  1733. }
  1734. msleep(POWER_RESET_MIN_DELAY_MS);
  1735. ret = cnss_bus_dev_powerup(plat_priv);
  1736. if (ret) {
  1737. __pm_relax(plat_priv->recovery_ws);
  1738. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1739. }
  1740. return;
  1741. }
  1742. static void cnss_recovery_work_handler(struct work_struct *work)
  1743. {
  1744. struct cnss_plat_data *plat_priv =
  1745. container_of(work, struct cnss_plat_data, recovery_work);
  1746. cnss_recovery_handler(plat_priv);
  1747. }
  1748. void cnss_device_crashed(struct device *dev)
  1749. {
  1750. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1751. if (!plat_priv)
  1752. return;
  1753. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1754. schedule_work(&plat_priv->recovery_work);
  1755. }
  1756. EXPORT_SYMBOL(cnss_device_crashed);
  1757. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1758. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1759. {
  1760. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1761. struct cnss_ramdump_info *ramdump_info;
  1762. if (!plat_priv)
  1763. return NULL;
  1764. ramdump_info = &plat_priv->ramdump_info;
  1765. *size = ramdump_info->ramdump_size;
  1766. return ramdump_info->ramdump_va;
  1767. }
  1768. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1769. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1770. {
  1771. switch (reason) {
  1772. case CNSS_REASON_DEFAULT:
  1773. return "DEFAULT";
  1774. case CNSS_REASON_LINK_DOWN:
  1775. return "LINK_DOWN";
  1776. case CNSS_REASON_RDDM:
  1777. return "RDDM";
  1778. case CNSS_REASON_TIMEOUT:
  1779. return "TIMEOUT";
  1780. }
  1781. return "UNKNOWN";
  1782. };
  1783. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1784. enum cnss_recovery_reason reason)
  1785. {
  1786. int ret;
  1787. plat_priv->recovery_count++;
  1788. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1789. goto self_recovery;
  1790. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1791. cnss_pr_dbg("Skip device recovery\n");
  1792. return 0;
  1793. }
  1794. /* FW recovery sequence has multiple steps and firmware load requires
  1795. * linux PM in awake state. Thus hold the cnss wake source until
  1796. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1797. * time taken in this process.
  1798. */
  1799. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1800. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1801. true);
  1802. switch (reason) {
  1803. case CNSS_REASON_LINK_DOWN:
  1804. if (!cnss_bus_check_link_status(plat_priv)) {
  1805. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1806. return 0;
  1807. }
  1808. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1809. &plat_priv->ctrl_params.quirks))
  1810. goto self_recovery;
  1811. if (!cnss_bus_recover_link_down(plat_priv)) {
  1812. /* clear recovery bit here to avoid skipping
  1813. * the recovery work for RDDM later
  1814. */
  1815. clear_bit(CNSS_DRIVER_RECOVERY,
  1816. &plat_priv->driver_state);
  1817. return 0;
  1818. }
  1819. break;
  1820. case CNSS_REASON_RDDM:
  1821. cnss_bus_collect_dump_info(plat_priv, false);
  1822. break;
  1823. case CNSS_REASON_DEFAULT:
  1824. case CNSS_REASON_TIMEOUT:
  1825. break;
  1826. default:
  1827. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1828. cnss_recovery_reason_to_str(reason), reason);
  1829. break;
  1830. }
  1831. cnss_bus_device_crashed(plat_priv);
  1832. return 0;
  1833. self_recovery:
  1834. cnss_pr_dbg("Going for self recovery\n");
  1835. cnss_bus_dev_shutdown(plat_priv);
  1836. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1837. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1838. &plat_priv->ctrl_params.quirks);
  1839. /* If link down self recovery is triggered before Host driver
  1840. * registration, avoid device power up because eventually device
  1841. * will be power up as part of driver registration.
  1842. */
  1843. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state) ||
  1844. !test_bit(CNSS_DRIVER_REGISTERED, &plat_priv->driver_state)) {
  1845. cnss_pr_dbg("Host driver not registered yet, ignore Device Power Up, 0x%lx\n",
  1846. plat_priv->driver_state);
  1847. return 0;
  1848. }
  1849. ret = cnss_bus_dev_powerup(plat_priv);
  1850. if (ret)
  1851. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1852. return 0;
  1853. }
  1854. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1855. void *data)
  1856. {
  1857. struct cnss_recovery_data *recovery_data = data;
  1858. int ret = 0;
  1859. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1860. cnss_recovery_reason_to_str(recovery_data->reason),
  1861. recovery_data->reason);
  1862. if (!plat_priv->driver_state) {
  1863. cnss_pr_err("Improper driver state, ignore recovery\n");
  1864. ret = -EINVAL;
  1865. goto out;
  1866. }
  1867. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1868. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1869. ret = -EINVAL;
  1870. goto out;
  1871. }
  1872. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1873. cnss_pr_err("Recovery is already in progress\n");
  1874. CNSS_ASSERT(0);
  1875. ret = -EINVAL;
  1876. goto out;
  1877. }
  1878. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1879. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1880. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1881. ret = -EINVAL;
  1882. goto out;
  1883. }
  1884. switch (plat_priv->device_id) {
  1885. case QCA6174_DEVICE_ID:
  1886. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1887. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1888. &plat_priv->driver_state)) {
  1889. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1890. ret = -EINVAL;
  1891. goto out;
  1892. }
  1893. break;
  1894. default:
  1895. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1896. set_bit(CNSS_FW_BOOT_RECOVERY,
  1897. &plat_priv->driver_state);
  1898. }
  1899. break;
  1900. }
  1901. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1902. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1903. out:
  1904. kfree(data);
  1905. return ret;
  1906. }
  1907. int cnss_self_recovery(struct device *dev,
  1908. enum cnss_recovery_reason reason)
  1909. {
  1910. cnss_schedule_recovery(dev, reason);
  1911. return 0;
  1912. }
  1913. EXPORT_SYMBOL(cnss_self_recovery);
  1914. void cnss_schedule_recovery(struct device *dev,
  1915. enum cnss_recovery_reason reason)
  1916. {
  1917. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1918. struct cnss_recovery_data *data;
  1919. int gfp = GFP_KERNEL;
  1920. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1921. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1922. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1923. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1924. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1925. return;
  1926. }
  1927. if (in_interrupt() || irqs_disabled())
  1928. gfp = GFP_ATOMIC;
  1929. data = kzalloc(sizeof(*data), gfp);
  1930. if (!data)
  1931. return;
  1932. data->reason = reason;
  1933. cnss_driver_event_post(plat_priv,
  1934. CNSS_DRIVER_EVENT_RECOVERY,
  1935. 0, data);
  1936. }
  1937. EXPORT_SYMBOL(cnss_schedule_recovery);
  1938. int cnss_force_fw_assert(struct device *dev)
  1939. {
  1940. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1941. if (!plat_priv) {
  1942. cnss_pr_err("plat_priv is NULL\n");
  1943. return -ENODEV;
  1944. }
  1945. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1946. cnss_pr_info("Forced FW assert is not supported\n");
  1947. return -EOPNOTSUPP;
  1948. }
  1949. if (cnss_bus_is_device_down(plat_priv)) {
  1950. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1951. return 0;
  1952. }
  1953. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1954. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1955. return 0;
  1956. }
  1957. if (in_interrupt() || irqs_disabled())
  1958. cnss_driver_event_post(plat_priv,
  1959. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1960. 0, NULL);
  1961. else
  1962. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1963. return 0;
  1964. }
  1965. EXPORT_SYMBOL(cnss_force_fw_assert);
  1966. int cnss_force_collect_rddm(struct device *dev)
  1967. {
  1968. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1969. unsigned int timeout;
  1970. int ret = 0;
  1971. if (!plat_priv) {
  1972. cnss_pr_err("plat_priv is NULL\n");
  1973. return -ENODEV;
  1974. }
  1975. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1976. cnss_pr_info("Force collect rddm is not supported\n");
  1977. return -EOPNOTSUPP;
  1978. }
  1979. if (cnss_bus_is_device_down(plat_priv)) {
  1980. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1981. goto wait_rddm;
  1982. }
  1983. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1984. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1985. goto wait_rddm;
  1986. }
  1987. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1988. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1989. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1990. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1991. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1992. return 0;
  1993. }
  1994. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1995. if (ret)
  1996. return ret;
  1997. wait_rddm:
  1998. reinit_completion(&plat_priv->rddm_complete);
  1999. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  2000. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  2001. msecs_to_jiffies(timeout));
  2002. if (!ret) {
  2003. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  2004. timeout);
  2005. ret = -ETIMEDOUT;
  2006. } else if (ret > 0) {
  2007. ret = 0;
  2008. }
  2009. return ret;
  2010. }
  2011. EXPORT_SYMBOL(cnss_force_collect_rddm);
  2012. int cnss_qmi_send_get(struct device *dev)
  2013. {
  2014. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  2015. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  2016. return 0;
  2017. return cnss_bus_qmi_send_get(plat_priv);
  2018. }
  2019. EXPORT_SYMBOL(cnss_qmi_send_get);
  2020. int cnss_qmi_send_put(struct device *dev)
  2021. {
  2022. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  2023. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  2024. return 0;
  2025. return cnss_bus_qmi_send_put(plat_priv);
  2026. }
  2027. EXPORT_SYMBOL(cnss_qmi_send_put);
  2028. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  2029. int cmd_len, void *cb_ctx,
  2030. int (*cb)(void *ctx, void *event, int event_len))
  2031. {
  2032. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  2033. int ret;
  2034. if (!plat_priv)
  2035. return -ENODEV;
  2036. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  2037. return -EINVAL;
  2038. plat_priv->get_info_cb = cb;
  2039. plat_priv->get_info_cb_ctx = cb_ctx;
  2040. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  2041. if (ret) {
  2042. plat_priv->get_info_cb = NULL;
  2043. plat_priv->get_info_cb_ctx = NULL;
  2044. }
  2045. return ret;
  2046. }
  2047. EXPORT_SYMBOL(cnss_qmi_send);
  2048. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  2049. {
  2050. int ret = 0;
  2051. u32 retry = 0, timeout;
  2052. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  2053. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  2054. goto out;
  2055. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  2056. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  2057. goto out;
  2058. } else if (test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  2059. cnss_pr_dbg("Calibration deferred as WLAN device disabled\n");
  2060. goto out;
  2061. }
  2062. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  2063. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  2064. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2065. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  2066. CNSS_ASSERT(0);
  2067. return -EINVAL;
  2068. }
  2069. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  2070. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  2071. break;
  2072. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  2073. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  2074. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  2075. CNSS_ASSERT(0);
  2076. ret = -EINVAL;
  2077. goto mark_cal_fail;
  2078. }
  2079. }
  2080. switch (plat_priv->device_id) {
  2081. case QCA6290_DEVICE_ID:
  2082. case QCA6390_DEVICE_ID:
  2083. case QCA6490_DEVICE_ID:
  2084. case KIWI_DEVICE_ID:
  2085. case MANGO_DEVICE_ID:
  2086. case PEACH_DEVICE_ID:
  2087. break;
  2088. default:
  2089. cnss_pr_err("Not supported for device ID 0x%lx\n",
  2090. plat_priv->device_id);
  2091. ret = -EINVAL;
  2092. goto mark_cal_fail;
  2093. }
  2094. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  2095. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  2096. timeout = cnss_get_timeout(plat_priv,
  2097. CNSS_TIMEOUT_CALIBRATION);
  2098. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  2099. timeout / 1000);
  2100. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  2101. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  2102. msecs_to_jiffies(timeout));
  2103. }
  2104. reinit_completion(&plat_priv->cal_complete);
  2105. ret = cnss_bus_dev_powerup(plat_priv);
  2106. mark_cal_fail:
  2107. if (ret) {
  2108. complete(&plat_priv->cal_complete);
  2109. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  2110. /* Set CBC done in driver state to mark attempt and note error
  2111. * since calibration cannot be retried at boot.
  2112. */
  2113. plat_priv->cal_done = CNSS_CAL_FAILURE;
  2114. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  2115. if (plat_priv->device_id == QCA6174_DEVICE_ID ||
  2116. plat_priv->device_id == QCN7605_DEVICE_ID) {
  2117. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  2118. goto out;
  2119. cnss_pr_info("Schedule WLAN driver load\n");
  2120. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  2121. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  2122. 0);
  2123. }
  2124. }
  2125. out:
  2126. return ret;
  2127. }
  2128. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  2129. void *data)
  2130. {
  2131. struct cnss_cal_info *cal_info = data;
  2132. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  2133. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  2134. goto out;
  2135. switch (cal_info->cal_status) {
  2136. case CNSS_CAL_DONE:
  2137. cnss_pr_dbg("Calibration completed successfully\n");
  2138. plat_priv->cal_done = true;
  2139. break;
  2140. case CNSS_CAL_TIMEOUT:
  2141. case CNSS_CAL_FAILURE:
  2142. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  2143. cal_info->cal_status);
  2144. break;
  2145. default:
  2146. cnss_pr_err("Unknown calibration status: %u\n",
  2147. cal_info->cal_status);
  2148. break;
  2149. }
  2150. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  2151. cnss_bus_free_qdss_mem(plat_priv);
  2152. cnss_release_antenna_sharing(plat_priv);
  2153. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  2154. goto skip_shutdown;
  2155. cnss_bus_dev_shutdown(plat_priv);
  2156. msleep(POWER_RESET_MIN_DELAY_MS);
  2157. skip_shutdown:
  2158. complete(&plat_priv->cal_complete);
  2159. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  2160. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  2161. if (cal_info->cal_status == CNSS_CAL_DONE) {
  2162. cnss_cal_mem_upload_to_file(plat_priv);
  2163. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  2164. goto out;
  2165. cnss_pr_dbg("Schedule WLAN driver load\n");
  2166. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  2167. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  2168. 0);
  2169. }
  2170. out:
  2171. kfree(data);
  2172. return 0;
  2173. }
  2174. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  2175. {
  2176. int ret;
  2177. ret = cnss_bus_dev_powerup(plat_priv);
  2178. if (ret)
  2179. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  2180. return ret;
  2181. }
  2182. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  2183. {
  2184. cnss_bus_dev_shutdown(plat_priv);
  2185. return 0;
  2186. }
  2187. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  2188. {
  2189. int ret = 0;
  2190. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  2191. if (ret < 0)
  2192. return ret;
  2193. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  2194. }
  2195. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  2196. u32 mem_seg_len, u64 pa, u32 size)
  2197. {
  2198. int i = 0;
  2199. u64 offset = 0;
  2200. void *va = NULL;
  2201. u64 local_pa;
  2202. u32 local_size;
  2203. for (i = 0; i < mem_seg_len; i++) {
  2204. if (i == QMI_WLFW_MEM_LPASS_SHARED_V01)
  2205. continue;
  2206. local_pa = (u64)fw_mem[i].pa;
  2207. local_size = (u32)fw_mem[i].size;
  2208. if (pa == local_pa && size <= local_size) {
  2209. va = fw_mem[i].va;
  2210. break;
  2211. }
  2212. if (pa > local_pa &&
  2213. pa < local_pa + local_size &&
  2214. pa + size <= local_pa + local_size) {
  2215. offset = pa - local_pa;
  2216. va = fw_mem[i].va + offset;
  2217. break;
  2218. }
  2219. }
  2220. return va;
  2221. }
  2222. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  2223. void *data)
  2224. {
  2225. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  2226. struct cnss_fw_mem *fw_mem_seg;
  2227. int ret = 0L;
  2228. void *va = NULL;
  2229. u32 i, fw_mem_seg_len;
  2230. switch (event_data->mem_type) {
  2231. case QMI_WLFW_MEM_TYPE_DDR_V01:
  2232. if (!plat_priv->fw_mem_seg_len)
  2233. goto invalid_mem_save;
  2234. fw_mem_seg = plat_priv->fw_mem;
  2235. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  2236. break;
  2237. case QMI_WLFW_MEM_QDSS_V01:
  2238. if (!plat_priv->qdss_mem_seg_len)
  2239. goto invalid_mem_save;
  2240. fw_mem_seg = plat_priv->qdss_mem;
  2241. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  2242. break;
  2243. default:
  2244. goto invalid_mem_save;
  2245. }
  2246. for (i = 0; i < event_data->mem_seg_len; i++) {
  2247. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  2248. event_data->mem_seg[i].addr,
  2249. event_data->mem_seg[i].size);
  2250. if (!va) {
  2251. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  2252. &event_data->mem_seg[i].addr,
  2253. event_data->mem_type);
  2254. ret = -EINVAL;
  2255. break;
  2256. }
  2257. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  2258. event_data->file_name,
  2259. event_data->mem_seg[i].size);
  2260. if (ret < 0) {
  2261. cnss_pr_err("Fail to save fw mem data: %d\n",
  2262. ret);
  2263. break;
  2264. }
  2265. }
  2266. kfree(data);
  2267. return ret;
  2268. invalid_mem_save:
  2269. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  2270. event_data->mem_type);
  2271. kfree(data);
  2272. return -EINVAL;
  2273. }
  2274. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  2275. {
  2276. cnss_bus_free_qdss_mem(plat_priv);
  2277. return 0;
  2278. }
  2279. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  2280. void *data)
  2281. {
  2282. int ret = 0;
  2283. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  2284. if (!plat_priv)
  2285. return -ENODEV;
  2286. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  2287. event_data->total_size);
  2288. kfree(data);
  2289. return ret;
  2290. }
  2291. static void cnss_driver_event_work(struct work_struct *work)
  2292. {
  2293. struct cnss_plat_data *plat_priv =
  2294. container_of(work, struct cnss_plat_data, event_work);
  2295. struct cnss_driver_event *event;
  2296. unsigned long flags;
  2297. int ret = 0;
  2298. if (!plat_priv) {
  2299. cnss_pr_err("plat_priv is NULL!\n");
  2300. return;
  2301. }
  2302. cnss_pm_stay_awake(plat_priv);
  2303. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2304. while (!list_empty(&plat_priv->event_list)) {
  2305. event = list_first_entry(&plat_priv->event_list,
  2306. struct cnss_driver_event, list);
  2307. list_del(&event->list);
  2308. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2309. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  2310. cnss_driver_event_to_str(event->type),
  2311. event->sync ? "-sync" : "", event->type,
  2312. plat_priv->driver_state);
  2313. switch (event->type) {
  2314. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  2315. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  2316. break;
  2317. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  2318. ret = cnss_wlfw_server_exit(plat_priv);
  2319. break;
  2320. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  2321. ret = cnss_bus_alloc_fw_mem(plat_priv);
  2322. if (ret)
  2323. break;
  2324. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  2325. break;
  2326. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  2327. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  2328. break;
  2329. case CNSS_DRIVER_EVENT_FW_READY:
  2330. ret = cnss_fw_ready_hdlr(plat_priv);
  2331. break;
  2332. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  2333. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  2334. break;
  2335. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  2336. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  2337. event->data);
  2338. break;
  2339. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  2340. ret = cnss_bus_register_driver_hdlr(plat_priv,
  2341. event->data);
  2342. break;
  2343. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  2344. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  2345. break;
  2346. case CNSS_DRIVER_EVENT_RECOVERY:
  2347. ret = cnss_driver_recovery_hdlr(plat_priv,
  2348. event->data);
  2349. break;
  2350. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  2351. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  2352. break;
  2353. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  2354. set_bit(CNSS_DRIVER_IDLE_RESTART,
  2355. &plat_priv->driver_state);
  2356. fallthrough;
  2357. case CNSS_DRIVER_EVENT_POWER_UP:
  2358. ret = cnss_power_up_hdlr(plat_priv);
  2359. break;
  2360. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  2361. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  2362. &plat_priv->driver_state);
  2363. fallthrough;
  2364. case CNSS_DRIVER_EVENT_POWER_DOWN:
  2365. ret = cnss_power_down_hdlr(plat_priv);
  2366. break;
  2367. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  2368. ret = cnss_process_wfc_call_ind_event(plat_priv,
  2369. event->data);
  2370. break;
  2371. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  2372. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  2373. event->data);
  2374. break;
  2375. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  2376. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  2377. break;
  2378. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  2379. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  2380. event->data);
  2381. break;
  2382. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  2383. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  2384. break;
  2385. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  2386. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  2387. event->data);
  2388. break;
  2389. default:
  2390. cnss_pr_err("Invalid driver event type: %d",
  2391. event->type);
  2392. kfree(event);
  2393. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2394. continue;
  2395. }
  2396. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2397. if (event->sync) {
  2398. event->ret = ret;
  2399. complete(&event->complete);
  2400. continue;
  2401. }
  2402. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2403. kfree(event);
  2404. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2405. }
  2406. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2407. cnss_pm_relax(plat_priv);
  2408. }
  2409. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  2410. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2411. {
  2412. int ret = 0;
  2413. struct cnss_subsys_info *subsys_info;
  2414. subsys_info = &plat_priv->subsys_info;
  2415. subsys_info->subsys_desc.name = plat_priv->device_name;
  2416. subsys_info->subsys_desc.owner = THIS_MODULE;
  2417. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  2418. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  2419. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  2420. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  2421. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  2422. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  2423. if (IS_ERR(subsys_info->subsys_device)) {
  2424. ret = PTR_ERR(subsys_info->subsys_device);
  2425. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  2426. goto out;
  2427. }
  2428. subsys_info->subsys_handle =
  2429. subsystem_get(subsys_info->subsys_desc.name);
  2430. if (!subsys_info->subsys_handle) {
  2431. cnss_pr_err("Failed to get subsys_handle!\n");
  2432. ret = -EINVAL;
  2433. goto unregister_subsys;
  2434. } else if (IS_ERR(subsys_info->subsys_handle)) {
  2435. ret = PTR_ERR(subsys_info->subsys_handle);
  2436. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  2437. goto unregister_subsys;
  2438. }
  2439. return 0;
  2440. unregister_subsys:
  2441. subsys_unregister(subsys_info->subsys_device);
  2442. out:
  2443. return ret;
  2444. }
  2445. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2446. {
  2447. struct cnss_subsys_info *subsys_info;
  2448. subsys_info = &plat_priv->subsys_info;
  2449. subsystem_put(subsys_info->subsys_handle);
  2450. subsys_unregister(subsys_info->subsys_device);
  2451. }
  2452. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2453. {
  2454. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  2455. return create_ramdump_device(subsys_info->subsys_desc.name,
  2456. subsys_info->subsys_desc.dev);
  2457. }
  2458. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2459. void *ramdump_dev)
  2460. {
  2461. destroy_ramdump_device(ramdump_dev);
  2462. }
  2463. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2464. {
  2465. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2466. struct ramdump_segment segment;
  2467. memset(&segment, 0, sizeof(segment));
  2468. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  2469. segment.size = ramdump_info->ramdump_size;
  2470. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  2471. }
  2472. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2473. {
  2474. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2475. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2476. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2477. struct ramdump_segment *ramdump_segs, *s;
  2478. struct cnss_dump_meta_info meta_info = {0};
  2479. int i, ret = 0;
  2480. ramdump_segs = kcalloc(dump_data->nentries + 1,
  2481. sizeof(*ramdump_segs),
  2482. GFP_KERNEL);
  2483. if (!ramdump_segs)
  2484. return -ENOMEM;
  2485. s = ramdump_segs + 1;
  2486. for (i = 0; i < dump_data->nentries; i++) {
  2487. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2488. cnss_pr_err("Unsupported dump type: %d",
  2489. dump_seg->type);
  2490. continue;
  2491. }
  2492. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2493. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2494. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2495. }
  2496. meta_info.entry[dump_seg->type].entry_num++;
  2497. s->address = dump_seg->address;
  2498. s->v_address = (void __iomem *)dump_seg->v_address;
  2499. s->size = dump_seg->size;
  2500. s++;
  2501. dump_seg++;
  2502. }
  2503. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2504. meta_info.version = CNSS_RAMDUMP_VERSION;
  2505. meta_info.chipset = plat_priv->device_id;
  2506. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2507. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  2508. ramdump_segs->size = sizeof(meta_info);
  2509. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  2510. dump_data->nentries + 1);
  2511. kfree(ramdump_segs);
  2512. return ret;
  2513. }
  2514. #else
  2515. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  2516. void *data)
  2517. {
  2518. struct cnss_plat_data *plat_priv =
  2519. container_of(nb, struct cnss_plat_data, panic_nb);
  2520. cnss_bus_dev_crash_shutdown(plat_priv);
  2521. return NOTIFY_DONE;
  2522. }
  2523. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2524. {
  2525. int ret;
  2526. if (!plat_priv)
  2527. return -ENODEV;
  2528. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2529. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2530. &plat_priv->panic_nb);
  2531. if (ret) {
  2532. cnss_pr_err("Failed to register panic handler\n");
  2533. return -EINVAL;
  2534. }
  2535. return 0;
  2536. }
  2537. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2538. {
  2539. int ret;
  2540. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2541. &plat_priv->panic_nb);
  2542. if (ret)
  2543. cnss_pr_err("Failed to unregister panic handler\n");
  2544. }
  2545. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2546. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2547. {
  2548. return &plat_priv->plat_dev->dev;
  2549. }
  2550. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2551. void *ramdump_dev)
  2552. {
  2553. }
  2554. #endif
  2555. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2556. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2557. {
  2558. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2559. struct qcom_dump_segment segment;
  2560. struct list_head head;
  2561. INIT_LIST_HEAD(&head);
  2562. memset(&segment, 0, sizeof(segment));
  2563. segment.va = ramdump_info->ramdump_va;
  2564. segment.size = ramdump_info->ramdump_size;
  2565. list_add(&segment.node, &head);
  2566. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2567. }
  2568. #else
  2569. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2570. {
  2571. return 0;
  2572. }
  2573. /* Using completion event inside dynamically allocated ramdump_desc
  2574. * may result a race between freeing the event after setting it to
  2575. * complete inside dev coredump free callback and the thread that is
  2576. * waiting for completion.
  2577. */
  2578. DECLARE_COMPLETION(dump_done);
  2579. #define TIMEOUT_SAVE_DUMP_MS 30000
  2580. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2581. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2582. { \
  2583. if (class == ELFCLASS32) \
  2584. return sizeof(struct elf32_##__xhdr); \
  2585. else \
  2586. return sizeof(struct elf64_##__xhdr); \
  2587. }
  2588. SIZEOF_ELF_STRUCT(phdr)
  2589. SIZEOF_ELF_STRUCT(hdr)
  2590. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2591. do { \
  2592. if (class == ELFCLASS32) \
  2593. ((struct elf32_##__xhdr *)arg)->member = value; \
  2594. else \
  2595. ((struct elf64_##__xhdr *)arg)->member = value; \
  2596. } while (0)
  2597. #define set_ehdr_property(arg, class, member, value) \
  2598. set_xhdr_property(hdr, arg, class, member, value)
  2599. #define set_phdr_property(arg, class, member, value) \
  2600. set_xhdr_property(phdr, arg, class, member, value)
  2601. /* These replace qcom_ramdump driver APIs called from common API
  2602. * cnss_do_elf_dump() by the ones defined here.
  2603. */
  2604. #define qcom_dump_segment cnss_qcom_dump_segment
  2605. #define qcom_elf_dump cnss_qcom_elf_dump
  2606. #define dump_enabled cnss_dump_enabled
  2607. struct cnss_qcom_dump_segment {
  2608. struct list_head node;
  2609. dma_addr_t da;
  2610. void *va;
  2611. size_t size;
  2612. };
  2613. struct cnss_qcom_ramdump_desc {
  2614. void *data;
  2615. struct completion dump_done;
  2616. };
  2617. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2618. void *data, size_t datalen)
  2619. {
  2620. struct cnss_qcom_ramdump_desc *desc = data;
  2621. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2622. datalen);
  2623. }
  2624. static void cnss_qcom_devcd_freev(void *data)
  2625. {
  2626. struct cnss_qcom_ramdump_desc *desc = data;
  2627. cnss_pr_dbg("Free dump data for dev coredump\n");
  2628. complete(&dump_done);
  2629. vfree(desc->data);
  2630. kfree(desc);
  2631. }
  2632. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2633. gfp_t gfp)
  2634. {
  2635. struct cnss_qcom_ramdump_desc *desc;
  2636. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2637. int ret;
  2638. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2639. if (!desc)
  2640. return -ENOMEM;
  2641. desc->data = data;
  2642. reinit_completion(&dump_done);
  2643. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2644. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2645. ret = wait_for_completion_timeout(&dump_done,
  2646. msecs_to_jiffies(timeout));
  2647. if (!ret)
  2648. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2649. timeout);
  2650. return ret ? 0 : -ETIMEDOUT;
  2651. }
  2652. /* Since the elf32 and elf64 identification is identical apart from
  2653. * the class, use elf32 by default.
  2654. */
  2655. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2656. {
  2657. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2658. ehdr->e_ident[EI_CLASS] = class;
  2659. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2660. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2661. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2662. }
  2663. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2664. unsigned char class)
  2665. {
  2666. struct cnss_qcom_dump_segment *segment;
  2667. void *phdr, *ehdr;
  2668. size_t data_size, offset;
  2669. int phnum = 0;
  2670. void *data;
  2671. void __iomem *ptr;
  2672. if (!segs || list_empty(segs))
  2673. return -EINVAL;
  2674. data_size = sizeof_elf_hdr(class);
  2675. list_for_each_entry(segment, segs, node) {
  2676. data_size += sizeof_elf_phdr(class) + segment->size;
  2677. phnum++;
  2678. }
  2679. data = vmalloc(data_size);
  2680. if (!data)
  2681. return -ENOMEM;
  2682. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2683. ehdr = data;
  2684. memset(ehdr, 0, sizeof_elf_hdr(class));
  2685. init_elf_identification(ehdr, class);
  2686. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2687. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2688. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2689. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2690. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2691. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2692. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2693. phdr = data + sizeof_elf_hdr(class);
  2694. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2695. list_for_each_entry(segment, segs, node) {
  2696. memset(phdr, 0, sizeof_elf_phdr(class));
  2697. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2698. set_phdr_property(phdr, class, p_offset, offset);
  2699. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2700. set_phdr_property(phdr, class, p_paddr, segment->da);
  2701. set_phdr_property(phdr, class, p_filesz, segment->size);
  2702. set_phdr_property(phdr, class, p_memsz, segment->size);
  2703. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2704. set_phdr_property(phdr, class, p_align, 0);
  2705. if (segment->va) {
  2706. memcpy(data + offset, segment->va, segment->size);
  2707. } else {
  2708. ptr = devm_ioremap(dev, segment->da, segment->size);
  2709. if (!ptr) {
  2710. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2711. &segment->da, segment->size);
  2712. memset(data + offset, 0xff, segment->size);
  2713. } else {
  2714. memcpy_fromio(data + offset, ptr,
  2715. segment->size);
  2716. }
  2717. }
  2718. offset += segment->size;
  2719. phdr += sizeof_elf_phdr(class);
  2720. }
  2721. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2722. }
  2723. /* Saving dump to file system is always needed in this case. */
  2724. static bool cnss_dump_enabled(void)
  2725. {
  2726. return true;
  2727. }
  2728. #endif /* CONFIG_QCOM_RAMDUMP */
  2729. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2730. {
  2731. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2732. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2733. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2734. struct qcom_dump_segment *seg;
  2735. struct cnss_dump_meta_info meta_info = {0};
  2736. struct list_head head;
  2737. int i, ret = 0;
  2738. if (!dump_enabled()) {
  2739. cnss_pr_info("Dump collection is not enabled\n");
  2740. return ret;
  2741. }
  2742. INIT_LIST_HEAD(&head);
  2743. for (i = 0; i < dump_data->nentries; i++) {
  2744. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2745. cnss_pr_err("Unsupported dump type: %d",
  2746. dump_seg->type);
  2747. continue;
  2748. }
  2749. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2750. if (!seg) {
  2751. cnss_pr_err("%s: Failed to allocate mem for seg %d\n",
  2752. __func__, i);
  2753. continue;
  2754. }
  2755. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2756. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2757. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2758. }
  2759. meta_info.entry[dump_seg->type].entry_num++;
  2760. seg->da = dump_seg->address;
  2761. seg->va = dump_seg->v_address;
  2762. seg->size = dump_seg->size;
  2763. list_add_tail(&seg->node, &head);
  2764. dump_seg++;
  2765. }
  2766. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2767. if (!seg) {
  2768. cnss_pr_err("%s: Failed to allocate mem for elf ramdump seg\n",
  2769. __func__);
  2770. goto skip_elf_dump;
  2771. }
  2772. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2773. meta_info.version = CNSS_RAMDUMP_VERSION;
  2774. meta_info.chipset = plat_priv->device_id;
  2775. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2776. seg->va = &meta_info;
  2777. seg->size = sizeof(meta_info);
  2778. list_add(&seg->node, &head);
  2779. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2780. skip_elf_dump:
  2781. while (!list_empty(&head)) {
  2782. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2783. list_del(&seg->node);
  2784. kfree(seg);
  2785. }
  2786. return ret;
  2787. }
  2788. #ifdef CONFIG_CNSS2_SSR_DRIVER_DUMP
  2789. /**
  2790. * cnss_host_ramdump_dev_release() - callback function for device release
  2791. * @dev: device to be released
  2792. *
  2793. * Return: None
  2794. */
  2795. static void cnss_host_ramdump_dev_release(struct device *dev)
  2796. {
  2797. cnss_pr_dbg("free host ramdump device\n");
  2798. kfree(dev);
  2799. }
  2800. int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
  2801. struct cnss_ssr_driver_dump_entry *ssr_entry,
  2802. size_t num_entries_loaded)
  2803. {
  2804. struct qcom_dump_segment *seg;
  2805. struct cnss_host_dump_meta_info meta_info = {0};
  2806. struct list_head head;
  2807. int dev_ret = 0;
  2808. struct device *new_device;
  2809. static const char * const wlan_str[] = {
  2810. [CNSS_HOST_WLAN_LOGS] = "wlan_logs",
  2811. [CNSS_HOST_HTC_CREDIT] = "htc_credit",
  2812. [CNSS_HOST_WMI_TX_CMP] = "wmi_tx_cmp",
  2813. [CNSS_HOST_WMI_COMMAND_LOG] = "wmi_command_log",
  2814. [CNSS_HOST_WMI_EVENT_LOG] = "wmi_event_log",
  2815. [CNSS_HOST_WMI_RX_EVENT] = "wmi_rx_event",
  2816. [CNSS_HOST_HAL_SOC] = "hal_soc",
  2817. [CNSS_HOST_GWLAN_LOGGING] = "gwlan_logging",
  2818. [CNSS_HOST_WMI_DEBUG_LOG_INFO] = "wmi_debug_log_info",
  2819. [CNSS_HOST_HTC_CREDIT_IDX] = "htc_credit_history_idx",
  2820. [CNSS_HOST_HTC_CREDIT_LEN] = "htc_credit_history_length",
  2821. [CNSS_HOST_WMI_TX_CMP_IDX] = "wmi_tx_cmp_idx",
  2822. [CNSS_HOST_WMI_COMMAND_LOG_IDX] = "wmi_command_log_idx",
  2823. [CNSS_HOST_WMI_EVENT_LOG_IDX] = "wmi_event_log_idx",
  2824. [CNSS_HOST_WMI_RX_EVENT_IDX] = "wmi_rx_event_idx",
  2825. [CNSS_HOST_HIF_CE_DESC_HISTORY_BUFF] = "hif_ce_desc_history_buff",
  2826. [CNSS_HOST_HANG_EVENT_DATA] = "hang_event_data",
  2827. [CNSS_HOST_CE_DESC_HIST] = "hif_ce_desc_hist",
  2828. [CNSS_HOST_CE_COUNT_MAX] = "hif_ce_count_max",
  2829. [CNSS_HOST_CE_HISTORY_MAX] = "hif_ce_history_max",
  2830. [CNSS_HOST_ONLY_FOR_CRIT_CE] = "hif_ce_only_for_crit",
  2831. [CNSS_HOST_HIF_EVENT_HISTORY] = "hif_event_history",
  2832. [CNSS_HOST_HIF_EVENT_HIST_MAX] = "hif_event_hist_max",
  2833. [CNSS_HOST_DP_WBM_DESC_REL] = "wbm_desc_rel_ring",
  2834. [CNSS_HOST_DP_WBM_DESC_REL_HANDLE] = "wbm_desc_rel_ring_handle",
  2835. [CNSS_HOST_DP_TCL_CMD] = "tcl_cmd_ring",
  2836. [CNSS_HOST_DP_TCL_CMD_HANDLE] = "tcl_cmd_ring_handle",
  2837. [CNSS_HOST_DP_TCL_STATUS] = "tcl_status_ring",
  2838. [CNSS_HOST_DP_TCL_STATUS_HANDLE] = "tcl_status_ring_handle",
  2839. [CNSS_HOST_DP_REO_REINJ] = "reo_reinject_ring",
  2840. [CNSS_HOST_DP_REO_REINJ_HANDLE] = "reo_reinject_ring_handle",
  2841. [CNSS_HOST_DP_RX_REL] = "rx_rel_ring",
  2842. [CNSS_HOST_DP_RX_REL_HANDLE] = "rx_rel_ring_handle",
  2843. [CNSS_HOST_DP_REO_EXP] = "reo_exception_ring",
  2844. [CNSS_HOST_DP_REO_EXP_HANDLE] = "reo_exception_ring_handle",
  2845. [CNSS_HOST_DP_REO_CMD] = "reo_cmd_ring",
  2846. [CNSS_HOST_DP_REO_CMD_HANDLE] = "reo_cmd_ring_handle",
  2847. [CNSS_HOST_DP_REO_STATUS] = "reo_status_ring",
  2848. [CNSS_HOST_DP_REO_STATUS_HANDLE] = "reo_status_ring_handle",
  2849. [CNSS_HOST_DP_TCL_DATA_0] = "tcl_data_ring_0",
  2850. [CNSS_HOST_DP_TCL_DATA_0_HANDLE] = "tcl_data_ring_0_handle",
  2851. [CNSS_HOST_DP_TX_COMP_0] = "tx_comp_ring_0",
  2852. [CNSS_HOST_DP_TX_COMP_0_HANDLE] = "tx_comp_ring_0_handle",
  2853. [CNSS_HOST_DP_TCL_DATA_1] = "tcl_data_ring_1",
  2854. [CNSS_HOST_DP_TCL_DATA_1_HANDLE] = "tcl_data_ring_1_handle",
  2855. [CNSS_HOST_DP_TX_COMP_1] = "tx_comp_ring_1",
  2856. [CNSS_HOST_DP_TX_COMP_1_HANDLE] = "tx_comp_ring_1_handle",
  2857. [CNSS_HOST_DP_TCL_DATA_2] = "tcl_data_ring_2",
  2858. [CNSS_HOST_DP_TCL_DATA_2_HANDLE] = "tcl_data_ring_2_handle",
  2859. [CNSS_HOST_DP_TX_COMP_2] = "tx_comp_ring_2",
  2860. [CNSS_HOST_DP_TX_COMP_2_HANDLE] = "tx_comp_ring_2_handle",
  2861. [CNSS_HOST_DP_REO_DST_0] = "reo_dest_ring_0",
  2862. [CNSS_HOST_DP_REO_DST_0_HANDLE] = "reo_dest_ring_0_handle",
  2863. [CNSS_HOST_DP_REO_DST_1] = "reo_dest_ring_1",
  2864. [CNSS_HOST_DP_REO_DST_1_HANDLE] = "reo_dest_ring_1_handle",
  2865. [CNSS_HOST_DP_REO_DST_2] = "reo_dest_ring_2",
  2866. [CNSS_HOST_DP_REO_DST_2_HANDLE] = "reo_dest_ring_2_handle",
  2867. [CNSS_HOST_DP_REO_DST_3] = "reo_dest_ring_3",
  2868. [CNSS_HOST_DP_REO_DST_3_HANDLE] = "reo_dest_ring_3_handle",
  2869. [CNSS_HOST_DP_REO_DST_4] = "reo_dest_ring_4",
  2870. [CNSS_HOST_DP_REO_DST_4_HANDLE] = "reo_dest_ring_4_handle",
  2871. [CNSS_HOST_DP_REO_DST_5] = "reo_dest_ring_5",
  2872. [CNSS_HOST_DP_REO_DST_5_HANDLE] = "reo_dest_ring_5_handle",
  2873. [CNSS_HOST_DP_REO_DST_6] = "reo_dest_ring_6",
  2874. [CNSS_HOST_DP_REO_DST_6_HANDLE] = "reo_dest_ring_6_handle",
  2875. [CNSS_HOST_DP_REO_DST_7] = "reo_dest_ring_7",
  2876. [CNSS_HOST_DP_REO_DST_7_HANDLE] = "reo_dest_ring_7_handle",
  2877. [CNSS_HOST_DP_PDEV_0] = "dp_pdev_0",
  2878. [CNSS_HOST_DP_WLAN_CFG_CTX] = "wlan_cfg_ctx",
  2879. [CNSS_HOST_DP_SOC] = "dp_soc",
  2880. [CNSS_HOST_HAL_RX_FST] = "hal_rx_fst",
  2881. [CNSS_HOST_DP_FISA] = "dp_fisa",
  2882. [CNSS_HOST_DP_FISA_HW_FSE_TABLE] = "dp_fisa_hw_fse_table",
  2883. [CNSS_HOST_DP_FISA_SW_FSE_TABLE] = "dp_fisa_sw_fse_table",
  2884. [CNSS_HOST_HIF] = "hif",
  2885. [CNSS_HOST_QDF_NBUF_HIST] = "qdf_nbuf_history",
  2886. [CNSS_HOST_TCL_WBM_MAP] = "tcl_wbm_map_array",
  2887. [CNSS_HOST_RX_MAC_BUF_RING_0] = "rx_mac_buf_ring_0",
  2888. [CNSS_HOST_RX_MAC_BUF_RING_0_HANDLE] = "rx_mac_buf_ring_0_handle",
  2889. [CNSS_HOST_RX_MAC_BUF_RING_1] = "rx_mac_buf_ring_1",
  2890. [CNSS_HOST_RX_MAC_BUF_RING_1_HANDLE] = "rx_mac_buf_ring_1_handle",
  2891. [CNSS_HOST_RX_REFILL_0] = "rx_refill_buf_ring_0",
  2892. [CNSS_HOST_RX_REFILL_0_HANDLE] = "rx_refill_buf_ring_0_handle",
  2893. [CNSS_HOST_CE_0] = "ce_0",
  2894. [CNSS_HOST_CE_0_SRC_RING] = "ce_0_src_ring",
  2895. [CNSS_HOST_CE_0_SRC_RING_CTX] = "ce_0_src_ring_ctx",
  2896. [CNSS_HOST_CE_1] = "ce_1",
  2897. [CNSS_HOST_CE_1_STATUS_RING] = "ce_1_status_ring",
  2898. [CNSS_HOST_CE_1_STATUS_RING_CTX] = "ce_1_status_ring_ctx",
  2899. [CNSS_HOST_CE_1_DEST_RING] = "ce_1_dest_ring",
  2900. [CNSS_HOST_CE_1_DEST_RING_CTX] = "ce_1_dest_ring_ctx",
  2901. [CNSS_HOST_CE_2] = "ce_2",
  2902. [CNSS_HOST_CE_2_STATUS_RING] = "ce_2_status_ring",
  2903. [CNSS_HOST_CE_2_STATUS_RING_CTX] = "ce_2_status_ring_ctx",
  2904. [CNSS_HOST_CE_2_DEST_RING] = "ce_2_dest_ring",
  2905. [CNSS_HOST_CE_2_DEST_RING_CTX] = "ce_2_dest_ring_ctx",
  2906. [CNSS_HOST_CE_3] = "ce_3",
  2907. [CNSS_HOST_CE_3_SRC_RING] = "ce_3_src_ring",
  2908. [CNSS_HOST_CE_3_SRC_RING_CTX] = "ce_3_src_ring_ctx",
  2909. [CNSS_HOST_CE_4] = "ce_4",
  2910. [CNSS_HOST_CE_4_SRC_RING] = "ce_4_src_ring",
  2911. [CNSS_HOST_CE_4_SRC_RING_CTX] = "ce_4_src_ring_ctx",
  2912. [CNSS_HOST_CE_5] = "ce_5",
  2913. [CNSS_HOST_CE_6] = "ce_6",
  2914. [CNSS_HOST_CE_7] = "ce_7",
  2915. [CNSS_HOST_CE_7_STATUS_RING] = "ce_7_status_ring",
  2916. [CNSS_HOST_CE_7_STATUS_RING_CTX] = "ce_7_status_ring_ctx",
  2917. [CNSS_HOST_CE_7_DEST_RING] = "ce_7_dest_ring",
  2918. [CNSS_HOST_CE_7_DEST_RING_CTX] = "ce_7_dest_ring_ctx",
  2919. [CNSS_HOST_CE_8] = "ce_8",
  2920. [CNSS_HOST_DP_TCL_DATA_3] = "tcl_data_ring_3",
  2921. [CNSS_HOST_DP_TCL_DATA_3_HANDLE] = "tcl_data_ring_3_handle",
  2922. [CNSS_HOST_DP_TX_COMP_3] = "tx_comp_ring_3",
  2923. [CNSS_HOST_DP_TX_COMP_3_HANDLE] = "tx_comp_ring_3_handle"
  2924. };
  2925. int i;
  2926. int ret = 0;
  2927. enum cnss_host_dump_type j;
  2928. if (!dump_enabled()) {
  2929. cnss_pr_info("Dump collection is not enabled\n");
  2930. return ret;
  2931. }
  2932. new_device = kcalloc(1, sizeof(*new_device), GFP_KERNEL);
  2933. if (!new_device) {
  2934. cnss_pr_err("Failed to alloc device mem\n");
  2935. return -ENOMEM;
  2936. }
  2937. new_device->release = cnss_host_ramdump_dev_release;
  2938. device_initialize(new_device);
  2939. dev_set_name(new_device, "wlan_driver");
  2940. dev_ret = device_add(new_device);
  2941. if (dev_ret) {
  2942. cnss_pr_err("Failed to add new device\n");
  2943. goto put_device;
  2944. }
  2945. INIT_LIST_HEAD(&head);
  2946. for (i = 0; i < num_entries_loaded; i++) {
  2947. /* If region name registered by driver is not present in
  2948. * wlan_str. type for that entry will not be set, but entry will
  2949. * be added. Which will result in entry type being 0. Currently
  2950. * entry type 0 is for wlan_logs, which will result in parsing
  2951. * issue for wlan_logs as parsing is done based upon type field.
  2952. * So initialize type with -1(Invalid) to avoid such issues.
  2953. */
  2954. meta_info.entry[i].type = -1;
  2955. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2956. if (!seg) {
  2957. cnss_pr_err("Failed to alloc seg entry %d\n", i);
  2958. continue;
  2959. }
  2960. seg->va = ssr_entry[i].buffer_pointer;
  2961. seg->da = (dma_addr_t)ssr_entry[i].buffer_pointer;
  2962. seg->size = ssr_entry[i].buffer_size;
  2963. for (j = 0; j < CNSS_HOST_DUMP_TYPE_MAX; j++) {
  2964. if (strcmp(ssr_entry[i].region_name, wlan_str[j]) == 0) {
  2965. meta_info.entry[i].type = j;
  2966. }
  2967. }
  2968. meta_info.entry[i].entry_start = i + 1;
  2969. meta_info.entry[i].entry_num++;
  2970. list_add_tail(&seg->node, &head);
  2971. }
  2972. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2973. if (!seg) {
  2974. cnss_pr_err("%s: Failed to allocate mem for host dump seg\n",
  2975. __func__);
  2976. goto skip_host_dump;
  2977. }
  2978. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2979. meta_info.version = CNSS_RAMDUMP_VERSION;
  2980. meta_info.chipset = plat_priv->device_id;
  2981. meta_info.total_entries = num_entries_loaded;
  2982. seg->va = &meta_info;
  2983. seg->da = (dma_addr_t)&meta_info;
  2984. seg->size = sizeof(meta_info);
  2985. list_add(&seg->node, &head);
  2986. ret = qcom_elf_dump(&head, new_device, ELF_CLASS);
  2987. skip_host_dump:
  2988. while (!list_empty(&head)) {
  2989. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2990. list_del(&seg->node);
  2991. kfree(seg);
  2992. }
  2993. device_del(new_device);
  2994. put_device:
  2995. put_device(new_device);
  2996. cnss_pr_dbg("host ramdump result %d\n", ret);
  2997. return ret;
  2998. }
  2999. #endif
  3000. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  3001. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  3002. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  3003. {
  3004. struct cnss_ramdump_info *ramdump_info;
  3005. struct msm_dump_entry dump_entry;
  3006. ramdump_info = &plat_priv->ramdump_info;
  3007. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  3008. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  3009. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  3010. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  3011. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  3012. sizeof(ramdump_info->dump_data.name));
  3013. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3014. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  3015. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  3016. &dump_entry);
  3017. }
  3018. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  3019. {
  3020. int ret = 0;
  3021. struct device *dev;
  3022. struct cnss_ramdump_info *ramdump_info;
  3023. u32 ramdump_size = 0;
  3024. dev = &plat_priv->plat_dev->dev;
  3025. ramdump_info = &plat_priv->ramdump_info;
  3026. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  3027. /* dt type: legacy or converged */
  3028. ret = of_property_read_u32(dev->of_node,
  3029. "qcom,wlan-ramdump-dynamic",
  3030. &ramdump_size);
  3031. } else {
  3032. ret = of_property_read_u32(plat_priv->dev_node,
  3033. "qcom,wlan-ramdump-dynamic",
  3034. &ramdump_size);
  3035. }
  3036. if (ret == 0) {
  3037. ramdump_info->ramdump_va =
  3038. dma_alloc_coherent(dev, ramdump_size,
  3039. &ramdump_info->ramdump_pa,
  3040. GFP_KERNEL);
  3041. if (ramdump_info->ramdump_va)
  3042. ramdump_info->ramdump_size = ramdump_size;
  3043. }
  3044. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  3045. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  3046. if (ramdump_info->ramdump_size == 0) {
  3047. cnss_pr_info("Ramdump will not be collected");
  3048. goto out;
  3049. }
  3050. ret = cnss_init_dump_entry(plat_priv);
  3051. if (ret) {
  3052. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  3053. goto free_ramdump;
  3054. }
  3055. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  3056. if (!ramdump_info->ramdump_dev) {
  3057. cnss_pr_err("Failed to create ramdump device!");
  3058. ret = -ENOMEM;
  3059. goto free_ramdump;
  3060. }
  3061. return 0;
  3062. free_ramdump:
  3063. dma_free_coherent(dev, ramdump_info->ramdump_size,
  3064. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  3065. out:
  3066. return ret;
  3067. }
  3068. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  3069. {
  3070. struct device *dev;
  3071. struct cnss_ramdump_info *ramdump_info;
  3072. dev = &plat_priv->plat_dev->dev;
  3073. ramdump_info = &plat_priv->ramdump_info;
  3074. if (ramdump_info->ramdump_dev)
  3075. cnss_destroy_ramdump_device(plat_priv,
  3076. ramdump_info->ramdump_dev);
  3077. if (ramdump_info->ramdump_va)
  3078. dma_free_coherent(dev, ramdump_info->ramdump_size,
  3079. ramdump_info->ramdump_va,
  3080. ramdump_info->ramdump_pa);
  3081. }
  3082. /**
  3083. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  3084. * @ret: Error returned by msm_dump_data_register_nominidump
  3085. *
  3086. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  3087. * ignore failure.
  3088. *
  3089. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  3090. */
  3091. static int cnss_ignore_dump_data_reg_fail(int ret)
  3092. {
  3093. return ret;
  3094. }
  3095. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  3096. {
  3097. int ret = 0;
  3098. struct cnss_ramdump_info_v2 *info_v2;
  3099. struct cnss_dump_data *dump_data;
  3100. struct msm_dump_entry dump_entry;
  3101. struct device *dev = &plat_priv->plat_dev->dev;
  3102. u32 ramdump_size = 0;
  3103. info_v2 = &plat_priv->ramdump_info_v2;
  3104. dump_data = &info_v2->dump_data;
  3105. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  3106. /* dt type: legacy or converged */
  3107. ret = of_property_read_u32(dev->of_node,
  3108. "qcom,wlan-ramdump-dynamic",
  3109. &ramdump_size);
  3110. } else {
  3111. ret = of_property_read_u32(plat_priv->dev_node,
  3112. "qcom,wlan-ramdump-dynamic",
  3113. &ramdump_size);
  3114. }
  3115. if (ret == 0)
  3116. info_v2->ramdump_size = ramdump_size;
  3117. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  3118. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  3119. if (!info_v2->dump_data_vaddr)
  3120. return -ENOMEM;
  3121. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  3122. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  3123. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  3124. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  3125. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  3126. sizeof(dump_data->name));
  3127. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3128. dump_entry.addr = virt_to_phys(dump_data);
  3129. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  3130. &dump_entry);
  3131. if (ret) {
  3132. ret = cnss_ignore_dump_data_reg_fail(ret);
  3133. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  3134. ret ? "Error" : "Ignoring", ret);
  3135. goto free_ramdump;
  3136. }
  3137. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  3138. if (!info_v2->ramdump_dev) {
  3139. cnss_pr_err("Failed to create ramdump device!\n");
  3140. ret = -ENOMEM;
  3141. goto free_ramdump;
  3142. }
  3143. return 0;
  3144. free_ramdump:
  3145. kfree(info_v2->dump_data_vaddr);
  3146. info_v2->dump_data_vaddr = NULL;
  3147. return ret;
  3148. }
  3149. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  3150. {
  3151. struct cnss_ramdump_info_v2 *info_v2;
  3152. info_v2 = &plat_priv->ramdump_info_v2;
  3153. if (info_v2->ramdump_dev)
  3154. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  3155. kfree(info_v2->dump_data_vaddr);
  3156. info_v2->dump_data_vaddr = NULL;
  3157. info_v2->dump_data_valid = false;
  3158. }
  3159. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  3160. {
  3161. int ret = 0;
  3162. switch (plat_priv->device_id) {
  3163. case QCA6174_DEVICE_ID:
  3164. ret = cnss_register_ramdump_v1(plat_priv);
  3165. break;
  3166. case QCA6290_DEVICE_ID:
  3167. case QCA6390_DEVICE_ID:
  3168. case QCN7605_DEVICE_ID:
  3169. case QCA6490_DEVICE_ID:
  3170. case KIWI_DEVICE_ID:
  3171. case MANGO_DEVICE_ID:
  3172. case PEACH_DEVICE_ID:
  3173. ret = cnss_register_ramdump_v2(plat_priv);
  3174. break;
  3175. default:
  3176. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  3177. ret = -ENODEV;
  3178. break;
  3179. }
  3180. return ret;
  3181. }
  3182. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  3183. {
  3184. switch (plat_priv->device_id) {
  3185. case QCA6174_DEVICE_ID:
  3186. cnss_unregister_ramdump_v1(plat_priv);
  3187. break;
  3188. case QCA6290_DEVICE_ID:
  3189. case QCA6390_DEVICE_ID:
  3190. case QCN7605_DEVICE_ID:
  3191. case QCA6490_DEVICE_ID:
  3192. case KIWI_DEVICE_ID:
  3193. case MANGO_DEVICE_ID:
  3194. case PEACH_DEVICE_ID:
  3195. cnss_unregister_ramdump_v2(plat_priv);
  3196. break;
  3197. default:
  3198. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  3199. break;
  3200. }
  3201. }
  3202. #else
  3203. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  3204. {
  3205. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  3206. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  3207. struct device *dev = &plat_priv->plat_dev->dev;
  3208. u32 ramdump_size = 0;
  3209. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  3210. &ramdump_size) == 0)
  3211. info_v2->ramdump_size = ramdump_size;
  3212. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  3213. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  3214. if (!info_v2->dump_data_vaddr)
  3215. return -ENOMEM;
  3216. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  3217. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  3218. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  3219. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  3220. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  3221. sizeof(dump_data->name));
  3222. info_v2->ramdump_dev = dev;
  3223. return 0;
  3224. }
  3225. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  3226. {
  3227. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  3228. info_v2->ramdump_dev = NULL;
  3229. kfree(info_v2->dump_data_vaddr);
  3230. info_v2->dump_data_vaddr = NULL;
  3231. info_v2->dump_data_valid = false;
  3232. }
  3233. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  3234. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  3235. phys_addr_t *pa, unsigned long attrs)
  3236. {
  3237. struct sg_table sgt;
  3238. int ret;
  3239. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  3240. if (ret) {
  3241. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  3242. va, &dma, size, attrs);
  3243. return -EINVAL;
  3244. }
  3245. *pa = page_to_phys(sg_page(sgt.sgl));
  3246. sg_free_table(&sgt);
  3247. return 0;
  3248. }
  3249. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  3250. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  3251. enum cnss_fw_dump_type type, int seg_no,
  3252. void *va, phys_addr_t pa, size_t size)
  3253. {
  3254. struct md_region md_entry;
  3255. int ret;
  3256. switch (type) {
  3257. case CNSS_FW_IMAGE:
  3258. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  3259. seg_no);
  3260. break;
  3261. case CNSS_FW_RDDM:
  3262. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  3263. seg_no);
  3264. break;
  3265. case CNSS_FW_REMOTE_HEAP:
  3266. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  3267. seg_no);
  3268. break;
  3269. default:
  3270. cnss_pr_err("Unknown dump type ID: %d\n", type);
  3271. return -EINVAL;
  3272. }
  3273. md_entry.phys_addr = pa;
  3274. md_entry.virt_addr = (uintptr_t)va;
  3275. md_entry.size = size;
  3276. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3277. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  3278. md_entry.name, va, &pa, size);
  3279. ret = msm_minidump_add_region(&md_entry);
  3280. if (ret < 0)
  3281. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  3282. return ret;
  3283. }
  3284. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  3285. enum cnss_fw_dump_type type, int seg_no,
  3286. void *va, phys_addr_t pa, size_t size)
  3287. {
  3288. struct md_region md_entry;
  3289. int ret;
  3290. switch (type) {
  3291. case CNSS_FW_IMAGE:
  3292. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  3293. seg_no);
  3294. break;
  3295. case CNSS_FW_RDDM:
  3296. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  3297. seg_no);
  3298. break;
  3299. case CNSS_FW_REMOTE_HEAP:
  3300. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  3301. seg_no);
  3302. break;
  3303. default:
  3304. cnss_pr_err("Unknown dump type ID: %d\n", type);
  3305. return -EINVAL;
  3306. }
  3307. md_entry.phys_addr = pa;
  3308. md_entry.virt_addr = (uintptr_t)va;
  3309. md_entry.size = size;
  3310. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3311. cnss_pr_vdbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  3312. md_entry.name, va, &pa, size);
  3313. ret = msm_minidump_remove_region(&md_entry);
  3314. if (ret)
  3315. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  3316. ret);
  3317. return ret;
  3318. }
  3319. #else
  3320. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  3321. enum cnss_fw_dump_type type, int seg_no,
  3322. void *va, phys_addr_t pa, size_t size)
  3323. {
  3324. char name[MAX_NAME_LEN];
  3325. switch (type) {
  3326. case CNSS_FW_IMAGE:
  3327. snprintf(name, MAX_NAME_LEN, "FBC_%X", seg_no);
  3328. break;
  3329. case CNSS_FW_RDDM:
  3330. snprintf(name, MAX_NAME_LEN, "RDDM_%X", seg_no);
  3331. break;
  3332. case CNSS_FW_REMOTE_HEAP:
  3333. snprintf(name, MAX_NAME_LEN, "RHEAP_%X", seg_no);
  3334. break;
  3335. default:
  3336. cnss_pr_err("Unknown dump type ID: %d\n", type);
  3337. return -EINVAL;
  3338. }
  3339. cnss_pr_dbg("Dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  3340. name, va, &pa, size);
  3341. return 0;
  3342. }
  3343. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  3344. enum cnss_fw_dump_type type, int seg_no,
  3345. void *va, phys_addr_t pa, size_t size)
  3346. {
  3347. return 0;
  3348. }
  3349. #endif /* CONFIG_QCOM_MINIDUMP */
  3350. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  3351. const struct firmware **fw_entry,
  3352. const char *filename)
  3353. {
  3354. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  3355. return request_firmware_direct(fw_entry, filename,
  3356. &plat_priv->plat_dev->dev);
  3357. else
  3358. return firmware_request_nowarn(fw_entry, filename,
  3359. &plat_priv->plat_dev->dev);
  3360. }
  3361. #if IS_ENABLED(CONFIG_INTERCONNECT)
  3362. /**
  3363. * cnss_register_bus_scale() - Setup interconnect voting data
  3364. * @plat_priv: Platform data structure
  3365. *
  3366. * For different interconnect path configured in device tree setup voting data
  3367. * for list of bandwidth requirements.
  3368. *
  3369. * Result: 0 for success. -EINVAL if not configured
  3370. */
  3371. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  3372. {
  3373. int ret = -EINVAL;
  3374. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  3375. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  3376. struct device *dev = &plat_priv->plat_dev->dev;
  3377. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  3378. ret = of_property_read_u32(dev->of_node,
  3379. "qcom,icc-path-count",
  3380. &plat_priv->icc.path_count);
  3381. if (ret) {
  3382. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  3383. return 0;
  3384. }
  3385. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  3386. "qcom,bus-bw-cfg-count",
  3387. &plat_priv->icc.bus_bw_cfg_count);
  3388. if (ret) {
  3389. cnss_pr_err("Failed to get Bus BW Config table size\n");
  3390. goto cleanup;
  3391. }
  3392. cfg_arr_size = plat_priv->icc.path_count *
  3393. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  3394. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  3395. if (!cfg_arr) {
  3396. cnss_pr_err("Failed to alloc cfg table mem\n");
  3397. ret = -ENOMEM;
  3398. goto cleanup;
  3399. }
  3400. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  3401. "qcom,bus-bw-cfg", cfg_arr,
  3402. cfg_arr_size);
  3403. if (ret) {
  3404. cnss_pr_err("Invalid Bus BW Config Table\n");
  3405. goto cleanup;
  3406. }
  3407. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  3408. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  3409. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  3410. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  3411. GFP_KERNEL);
  3412. if (!bus_bw_info) {
  3413. ret = -ENOMEM;
  3414. goto out;
  3415. }
  3416. ret = of_property_read_string_index(dev->of_node,
  3417. "interconnect-names", idx,
  3418. &bus_bw_info->icc_name);
  3419. if (ret)
  3420. goto out;
  3421. bus_bw_info->icc_path =
  3422. of_icc_get(&plat_priv->plat_dev->dev,
  3423. bus_bw_info->icc_name);
  3424. if (IS_ERR(bus_bw_info->icc_path)) {
  3425. ret = PTR_ERR(bus_bw_info->icc_path);
  3426. if (ret != -EPROBE_DEFER) {
  3427. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  3428. bus_bw_info->icc_name, ret);
  3429. goto out;
  3430. }
  3431. }
  3432. bus_bw_info->cfg_table =
  3433. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  3434. sizeof(*bus_bw_info->cfg_table),
  3435. GFP_KERNEL);
  3436. if (!bus_bw_info->cfg_table) {
  3437. ret = -ENOMEM;
  3438. goto out;
  3439. }
  3440. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  3441. bus_bw_info->icc_name);
  3442. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  3443. CNSS_ICC_VOTE_MAX);
  3444. i < plat_priv->icc.bus_bw_cfg_count;
  3445. i++, j += 2) {
  3446. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  3447. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  3448. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  3449. i, bus_bw_info->cfg_table[i].avg_bw,
  3450. bus_bw_info->cfg_table[i].peak_bw);
  3451. }
  3452. list_add_tail(&bus_bw_info->list,
  3453. &plat_priv->icc.list_head);
  3454. }
  3455. kfree(cfg_arr);
  3456. return 0;
  3457. out:
  3458. list_for_each_entry_safe(bus_bw_info, tmp,
  3459. &plat_priv->icc.list_head, list) {
  3460. list_del(&bus_bw_info->list);
  3461. }
  3462. cleanup:
  3463. kfree(cfg_arr);
  3464. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  3465. return ret;
  3466. }
  3467. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  3468. {
  3469. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  3470. list_for_each_entry_safe(bus_bw_info, tmp,
  3471. &plat_priv->icc.list_head, list) {
  3472. list_del(&bus_bw_info->list);
  3473. if (bus_bw_info->icc_path)
  3474. icc_put(bus_bw_info->icc_path);
  3475. }
  3476. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  3477. }
  3478. #else
  3479. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  3480. {
  3481. return 0;
  3482. }
  3483. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  3484. #endif /* CONFIG_INTERCONNECT */
  3485. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  3486. {
  3487. struct cnss_plat_data *plat_priv = cb_ctx;
  3488. if (!plat_priv) {
  3489. cnss_pr_err("%s: Invalid context\n", __func__);
  3490. return;
  3491. }
  3492. if (status) {
  3493. cnss_pr_info("CNSS Daemon connected\n");
  3494. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  3495. complete(&plat_priv->daemon_connected);
  3496. } else {
  3497. cnss_pr_info("CNSS Daemon disconnected\n");
  3498. reinit_completion(&plat_priv->daemon_connected);
  3499. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  3500. }
  3501. }
  3502. static ssize_t enable_hds_store(struct device *dev,
  3503. struct device_attribute *attr,
  3504. const char *buf, size_t count)
  3505. {
  3506. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3507. unsigned int enable_hds = 0;
  3508. if (!plat_priv)
  3509. return -ENODEV;
  3510. if (sscanf(buf, "%du", &enable_hds) != 1) {
  3511. cnss_pr_err("Invalid enable_hds sysfs command\n");
  3512. return -EINVAL;
  3513. }
  3514. if (enable_hds)
  3515. plat_priv->hds_enabled = true;
  3516. else
  3517. plat_priv->hds_enabled = false;
  3518. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  3519. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  3520. return count;
  3521. }
  3522. static ssize_t recovery_show(struct device *dev,
  3523. struct device_attribute *attr,
  3524. char *buf)
  3525. {
  3526. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3527. u32 buf_size = PAGE_SIZE;
  3528. u32 curr_len = 0;
  3529. u32 buf_written = 0;
  3530. if (!plat_priv)
  3531. return -ENODEV;
  3532. buf_written = scnprintf(buf, buf_size,
  3533. "Usage: echo [recovery_bitmap] > /sys/kernel/cnss/recovery\n"
  3534. "BIT0 -- wlan fw recovery\n"
  3535. "BIT1 -- wlan pcss recovery\n"
  3536. "---------------------------------\n");
  3537. curr_len += buf_written;
  3538. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  3539. "WLAN recovery %s[%d]\n",
  3540. plat_priv->recovery_enabled ? "Enabled" : "Disabled",
  3541. plat_priv->recovery_enabled);
  3542. curr_len += buf_written;
  3543. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  3544. "WLAN PCSS recovery %s[%d]\n",
  3545. plat_priv->recovery_pcss_enabled ? "Enabled" : "Disabled",
  3546. plat_priv->recovery_pcss_enabled);
  3547. curr_len += buf_written;
  3548. /*
  3549. * Now size of curr_len is not over page size for sure,
  3550. * later if new item or none-fixed size item added, need
  3551. * add check to make sure curr_len is not over page size.
  3552. */
  3553. return curr_len;
  3554. }
  3555. static ssize_t tme_opt_file_download_show(struct device *dev,
  3556. struct device_attribute *attr, char *buf)
  3557. {
  3558. u32 buf_size = PAGE_SIZE;
  3559. u32 curr_len = 0;
  3560. u32 buf_written = 0;
  3561. buf_written = scnprintf(buf, buf_size,
  3562. "Usage: echo [file_type] > /sys/kernel/cnss/tme_opt_file_download\n"
  3563. "file_type = sec -- For OEM_FUSE file\n"
  3564. "file_type = rpr -- For RPR file\n"
  3565. "file_type = dpr -- For DPR file\n");
  3566. curr_len += buf_written;
  3567. return curr_len;
  3568. }
  3569. static ssize_t time_sync_period_show(struct device *dev,
  3570. struct device_attribute *attr,
  3571. char *buf)
  3572. {
  3573. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3574. return scnprintf(buf, PAGE_SIZE, "%u ms\n",
  3575. plat_priv->ctrl_params.time_sync_period);
  3576. }
  3577. /**
  3578. * cnss_get_min_time_sync_period_by_vote() - Get minimum time sync period
  3579. * @plat_priv: Platform data structure
  3580. *
  3581. * Result: return minimum time sync period present in vote from wlan and sys
  3582. */
  3583. uint32_t cnss_get_min_time_sync_period_by_vote(struct cnss_plat_data *plat_priv)
  3584. {
  3585. unsigned int i, min_time_sync_period = CNSS_TIME_SYNC_PERIOD_INVALID;
  3586. unsigned int time_sync_period;
  3587. for (i = 0; i < TIME_SYNC_VOTE_MAX; i++) {
  3588. time_sync_period = plat_priv->ctrl_params.time_sync_period_vote[i];
  3589. if (min_time_sync_period > time_sync_period)
  3590. min_time_sync_period = time_sync_period;
  3591. }
  3592. return min_time_sync_period;
  3593. }
  3594. static ssize_t time_sync_period_store(struct device *dev,
  3595. struct device_attribute *attr,
  3596. const char *buf, size_t count)
  3597. {
  3598. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3599. unsigned int time_sync_period = 0;
  3600. if (!plat_priv)
  3601. return -ENODEV;
  3602. if (sscanf(buf, "%du", &time_sync_period) != 1) {
  3603. cnss_pr_err("Invalid time sync sysfs command\n");
  3604. return -EINVAL;
  3605. }
  3606. if (time_sync_period < CNSS_MIN_TIME_SYNC_PERIOD) {
  3607. cnss_pr_err("Invalid time sync value\n");
  3608. return -EINVAL;
  3609. }
  3610. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_CNSS] =
  3611. time_sync_period;
  3612. time_sync_period = cnss_get_min_time_sync_period_by_vote(plat_priv);
  3613. if (time_sync_period == CNSS_TIME_SYNC_PERIOD_INVALID) {
  3614. cnss_pr_err("Invalid min time sync value\n");
  3615. return -EINVAL;
  3616. }
  3617. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  3618. return count;
  3619. }
  3620. /**
  3621. * cnss_update_time_sync_period() - Set time sync period given by driver
  3622. * @dev: device structure
  3623. * @time_sync_period: time sync period value
  3624. *
  3625. * Update time sync period vote of driver and set minimum of time sync period
  3626. * from stored vote through wlan and sys config
  3627. * Result: return 0 for success, error in case of invalid value and no dev
  3628. */
  3629. int cnss_update_time_sync_period(struct device *dev, uint32_t time_sync_period)
  3630. {
  3631. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  3632. if (!plat_priv)
  3633. return -ENODEV;
  3634. if (time_sync_period < CNSS_MIN_TIME_SYNC_PERIOD) {
  3635. cnss_pr_err("Invalid time sync value\n");
  3636. return -EINVAL;
  3637. }
  3638. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_WLAN] =
  3639. time_sync_period;
  3640. time_sync_period = cnss_get_min_time_sync_period_by_vote(plat_priv);
  3641. if (time_sync_period == CNSS_TIME_SYNC_PERIOD_INVALID) {
  3642. cnss_pr_err("Invalid min time sync value\n");
  3643. return -EINVAL;
  3644. }
  3645. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  3646. return 0;
  3647. }
  3648. EXPORT_SYMBOL(cnss_update_time_sync_period);
  3649. /**
  3650. * cnss_reset_time_sync_period() - Reset time sync period
  3651. * @dev: device structure
  3652. *
  3653. * Update time sync period vote of driver as invalid
  3654. * and reset minimum of time sync period from
  3655. * stored vote through wlan and sys config
  3656. * Result: return 0 for success, error in case of no dev
  3657. */
  3658. int cnss_reset_time_sync_period(struct device *dev)
  3659. {
  3660. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  3661. unsigned int time_sync_period = 0;
  3662. if (!plat_priv)
  3663. return -ENODEV;
  3664. /* Driver vote is set to invalid in case of reset
  3665. * In this case, only vote valid to check is sys config
  3666. */
  3667. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_WLAN] =
  3668. CNSS_TIME_SYNC_PERIOD_INVALID;
  3669. time_sync_period = cnss_get_min_time_sync_period_by_vote(plat_priv);
  3670. if (time_sync_period == CNSS_TIME_SYNC_PERIOD_INVALID) {
  3671. cnss_pr_err("Invalid min time sync value\n");
  3672. return -EINVAL;
  3673. }
  3674. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  3675. return 0;
  3676. }
  3677. EXPORT_SYMBOL(cnss_reset_time_sync_period);
  3678. static ssize_t recovery_store(struct device *dev,
  3679. struct device_attribute *attr,
  3680. const char *buf, size_t count)
  3681. {
  3682. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3683. unsigned int recovery = 0;
  3684. if (!plat_priv)
  3685. return -ENODEV;
  3686. if (sscanf(buf, "%du", &recovery) != 1) {
  3687. cnss_pr_err("Invalid recovery sysfs command\n");
  3688. return -EINVAL;
  3689. }
  3690. plat_priv->recovery_enabled = !!(recovery & CNSS_WLAN_RECOVERY);
  3691. plat_priv->recovery_pcss_enabled = !!(recovery & CNSS_PCSS_RECOVERY);
  3692. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  3693. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  3694. cnss_pr_dbg("%s PCSS recovery, count is %zu\n",
  3695. plat_priv->recovery_pcss_enabled ? "Enable" : "Disable", count);
  3696. cnss_send_subsys_restart_level_msg(plat_priv);
  3697. return count;
  3698. }
  3699. static ssize_t shutdown_store(struct device *dev,
  3700. struct device_attribute *attr,
  3701. const char *buf, size_t count)
  3702. {
  3703. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3704. cnss_pr_dbg("Received shutdown notification\n");
  3705. if (plat_priv) {
  3706. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3707. cnss_bus_update_status(plat_priv, CNSS_SYS_REBOOT);
  3708. del_timer(&plat_priv->fw_boot_timer);
  3709. complete_all(&plat_priv->power_up_complete);
  3710. complete_all(&plat_priv->cal_complete);
  3711. cnss_pr_dbg("Shutdown notification handled\n");
  3712. }
  3713. return count;
  3714. }
  3715. static ssize_t fs_ready_store(struct device *dev,
  3716. struct device_attribute *attr,
  3717. const char *buf, size_t count)
  3718. {
  3719. int fs_ready = 0;
  3720. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3721. if (sscanf(buf, "%du", &fs_ready) != 1)
  3722. return -EINVAL;
  3723. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  3724. fs_ready, count);
  3725. if (!plat_priv) {
  3726. cnss_pr_err("plat_priv is NULL\n");
  3727. return count;
  3728. }
  3729. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  3730. cnss_pr_dbg("QMI is bypassed\n");
  3731. return count;
  3732. }
  3733. set_bit(CNSS_FS_READY, &plat_priv->driver_state);
  3734. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  3735. cnss_driver_event_post(plat_priv,
  3736. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  3737. 0, NULL);
  3738. }
  3739. return count;
  3740. }
  3741. static ssize_t qdss_trace_start_store(struct device *dev,
  3742. struct device_attribute *attr,
  3743. const char *buf, size_t count)
  3744. {
  3745. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3746. wlfw_qdss_trace_start(plat_priv);
  3747. cnss_pr_dbg("Received QDSS start command\n");
  3748. return count;
  3749. }
  3750. static ssize_t qdss_trace_stop_store(struct device *dev,
  3751. struct device_attribute *attr,
  3752. const char *buf, size_t count)
  3753. {
  3754. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3755. u32 option = 0;
  3756. if (sscanf(buf, "%du", &option) != 1)
  3757. return -EINVAL;
  3758. wlfw_qdss_trace_stop(plat_priv, option);
  3759. cnss_pr_dbg("Received QDSS stop command\n");
  3760. return count;
  3761. }
  3762. static ssize_t qdss_conf_download_store(struct device *dev,
  3763. struct device_attribute *attr,
  3764. const char *buf, size_t count)
  3765. {
  3766. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3767. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  3768. cnss_pr_dbg("Received QDSS download config command\n");
  3769. return count;
  3770. }
  3771. static ssize_t tme_opt_file_download_store(struct device *dev,
  3772. struct device_attribute *attr,
  3773. const char *buf, size_t count)
  3774. {
  3775. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3776. char cmd[5];
  3777. if (sscanf(buf, "%s", cmd) != 1)
  3778. return -EINVAL;
  3779. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  3780. cnss_pr_err("Firmware is not ready yet\n");
  3781. return 0;
  3782. }
  3783. if (plat_priv->device_id == PEACH_DEVICE_ID &&
  3784. cnss_bus_runtime_pm_get_sync(plat_priv) < 0)
  3785. goto runtime_pm_put;
  3786. if (strcmp(cmd, "sec") == 0) {
  3787. cnss_bus_load_tme_opt_file(plat_priv, WLFW_TME_LITE_OEM_FUSE_FILE_V01);
  3788. cnss_wlfw_tme_opt_file_dnld_send_sync(plat_priv, WLFW_TME_LITE_OEM_FUSE_FILE_V01);
  3789. } else if (strcmp(cmd, "rpr") == 0) {
  3790. cnss_bus_load_tme_opt_file(plat_priv, WLFW_TME_LITE_RPR_FILE_V01);
  3791. cnss_wlfw_tme_opt_file_dnld_send_sync(plat_priv, WLFW_TME_LITE_RPR_FILE_V01);
  3792. } else if (strcmp(cmd, "dpr") == 0) {
  3793. cnss_bus_load_tme_opt_file(plat_priv, WLFW_TME_LITE_DPR_FILE_V01);
  3794. cnss_wlfw_tme_opt_file_dnld_send_sync(plat_priv, WLFW_TME_LITE_DPR_FILE_V01);
  3795. }
  3796. cnss_pr_dbg("Received tme_opt_file_download indication cmd: %s\n", cmd);
  3797. runtime_pm_put:
  3798. if (plat_priv->device_id == PEACH_DEVICE_ID)
  3799. cnss_bus_runtime_pm_put(plat_priv);
  3800. return count;
  3801. }
  3802. static ssize_t hw_trace_override_store(struct device *dev,
  3803. struct device_attribute *attr,
  3804. const char *buf, size_t count)
  3805. {
  3806. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3807. int tmp = 0;
  3808. if (sscanf(buf, "%du", &tmp) != 1)
  3809. return -EINVAL;
  3810. plat_priv->hw_trc_override = tmp;
  3811. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  3812. return count;
  3813. }
  3814. static ssize_t charger_mode_store(struct device *dev,
  3815. struct device_attribute *attr,
  3816. const char *buf, size_t count)
  3817. {
  3818. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3819. int tmp = 0;
  3820. if (sscanf(buf, "%du", &tmp) != 1)
  3821. return -EINVAL;
  3822. plat_priv->charger_mode = tmp;
  3823. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  3824. return count;
  3825. }
  3826. static DEVICE_ATTR_WO(fs_ready);
  3827. static DEVICE_ATTR_WO(shutdown);
  3828. static DEVICE_ATTR_RW(recovery);
  3829. static DEVICE_ATTR_WO(enable_hds);
  3830. static DEVICE_ATTR_WO(qdss_trace_start);
  3831. static DEVICE_ATTR_WO(qdss_trace_stop);
  3832. static DEVICE_ATTR_WO(qdss_conf_download);
  3833. static DEVICE_ATTR_RW(tme_opt_file_download);
  3834. static DEVICE_ATTR_WO(hw_trace_override);
  3835. static DEVICE_ATTR_WO(charger_mode);
  3836. static DEVICE_ATTR_RW(time_sync_period);
  3837. static struct attribute *cnss_attrs[] = {
  3838. &dev_attr_fs_ready.attr,
  3839. &dev_attr_shutdown.attr,
  3840. &dev_attr_recovery.attr,
  3841. &dev_attr_enable_hds.attr,
  3842. &dev_attr_qdss_trace_start.attr,
  3843. &dev_attr_qdss_trace_stop.attr,
  3844. &dev_attr_qdss_conf_download.attr,
  3845. &dev_attr_tme_opt_file_download.attr,
  3846. &dev_attr_hw_trace_override.attr,
  3847. &dev_attr_charger_mode.attr,
  3848. &dev_attr_time_sync_period.attr,
  3849. NULL,
  3850. };
  3851. static struct attribute_group cnss_attr_group = {
  3852. .attrs = cnss_attrs,
  3853. };
  3854. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  3855. {
  3856. struct device *dev = &plat_priv->plat_dev->dev;
  3857. int ret;
  3858. char cnss_name[CNSS_FS_NAME_SIZE];
  3859. char shutdown_name[32];
  3860. if (cnss_is_dual_wlan_enabled()) {
  3861. snprintf(cnss_name, CNSS_FS_NAME_SIZE,
  3862. CNSS_FS_NAME "_%d", plat_priv->plat_idx);
  3863. snprintf(shutdown_name, sizeof(shutdown_name),
  3864. "shutdown_wlan_%d", plat_priv->plat_idx);
  3865. } else {
  3866. snprintf(cnss_name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME);
  3867. snprintf(shutdown_name, sizeof(shutdown_name),
  3868. "shutdown_wlan");
  3869. }
  3870. ret = sysfs_create_link(kernel_kobj, &dev->kobj, cnss_name);
  3871. if (ret) {
  3872. cnss_pr_err("Failed to create cnss link, err = %d\n",
  3873. ret);
  3874. goto out;
  3875. }
  3876. /* This is only for backward compatibility. */
  3877. ret = sysfs_create_link(kernel_kobj, &dev->kobj, shutdown_name);
  3878. if (ret) {
  3879. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  3880. ret);
  3881. goto rm_cnss_link;
  3882. }
  3883. return 0;
  3884. rm_cnss_link:
  3885. sysfs_remove_link(kernel_kobj, cnss_name);
  3886. out:
  3887. return ret;
  3888. }
  3889. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  3890. {
  3891. char cnss_name[CNSS_FS_NAME_SIZE];
  3892. char shutdown_name[32];
  3893. if (cnss_is_dual_wlan_enabled()) {
  3894. snprintf(cnss_name, CNSS_FS_NAME_SIZE,
  3895. CNSS_FS_NAME "_%d", plat_priv->plat_idx);
  3896. snprintf(shutdown_name, sizeof(shutdown_name),
  3897. "shutdown_wlan_%d", plat_priv->plat_idx);
  3898. } else {
  3899. snprintf(cnss_name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME);
  3900. snprintf(shutdown_name, sizeof(shutdown_name),
  3901. "shutdown_wlan");
  3902. }
  3903. sysfs_remove_link(kernel_kobj, shutdown_name);
  3904. sysfs_remove_link(kernel_kobj, cnss_name);
  3905. }
  3906. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  3907. {
  3908. int ret = 0;
  3909. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  3910. &cnss_attr_group);
  3911. if (ret) {
  3912. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  3913. ret);
  3914. goto out;
  3915. }
  3916. cnss_create_sysfs_link(plat_priv);
  3917. return 0;
  3918. out:
  3919. return ret;
  3920. }
  3921. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 2, 0))
  3922. union cnss_device_group_devres {
  3923. const struct attribute_group *group;
  3924. };
  3925. static void devm_cnss_group_remove(struct device *dev, void *res)
  3926. {
  3927. union cnss_device_group_devres *devres = res;
  3928. const struct attribute_group *group = devres->group;
  3929. cnss_pr_dbg("%s: removing group %p\n", __func__, group);
  3930. sysfs_remove_group(&dev->kobj, group);
  3931. }
  3932. static int devm_cnss_group_match(struct device *dev, void *res, void *data)
  3933. {
  3934. return ((union cnss_device_group_devres *)res) == data;
  3935. }
  3936. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  3937. {
  3938. cnss_remove_sysfs_link(plat_priv);
  3939. WARN_ON(devres_release(&plat_priv->plat_dev->dev,
  3940. devm_cnss_group_remove, devm_cnss_group_match,
  3941. (void *)&cnss_attr_group));
  3942. }
  3943. #else
  3944. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  3945. {
  3946. cnss_remove_sysfs_link(plat_priv);
  3947. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  3948. }
  3949. #endif
  3950. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  3951. {
  3952. spin_lock_init(&plat_priv->event_lock);
  3953. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  3954. WQ_UNBOUND, 1);
  3955. if (!plat_priv->event_wq) {
  3956. cnss_pr_err("Failed to create event workqueue!\n");
  3957. return -EFAULT;
  3958. }
  3959. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  3960. INIT_LIST_HEAD(&plat_priv->event_list);
  3961. return 0;
  3962. }
  3963. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  3964. {
  3965. destroy_workqueue(plat_priv->event_wq);
  3966. }
  3967. static int cnss_reboot_notifier(struct notifier_block *nb,
  3968. unsigned long action,
  3969. void *data)
  3970. {
  3971. struct cnss_plat_data *plat_priv =
  3972. container_of(nb, struct cnss_plat_data, reboot_nb);
  3973. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3974. cnss_bus_update_status(plat_priv, CNSS_SYS_REBOOT);
  3975. del_timer(&plat_priv->fw_boot_timer);
  3976. complete_all(&plat_priv->power_up_complete);
  3977. complete_all(&plat_priv->cal_complete);
  3978. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  3979. return NOTIFY_DONE;
  3980. }
  3981. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  3982. #ifdef CONFIG_CNSS_HW_SECURE_SMEM
  3983. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3984. {
  3985. uint32_t *peripheralStateInfo = NULL;
  3986. size_t size = 0;
  3987. /* Once this flag is set, secure peripheral feature
  3988. * will not be supported till next reboot
  3989. */
  3990. if (plat_priv->sec_peri_feature_disable)
  3991. return 0;
  3992. peripheralStateInfo = qcom_smem_get(QCOM_SMEM_HOST_ANY, PERISEC_SMEM_ID, &size);
  3993. if (IS_ERR_OR_NULL(peripheralStateInfo)) {
  3994. if (PTR_ERR(peripheralStateInfo) != -ENOENT &&
  3995. PTR_ERR(peripheralStateInfo) != -ENODEV)
  3996. CNSS_ASSERT(0);
  3997. cnss_pr_dbg("Secure HW feature not enabled. ret = %d\n",
  3998. PTR_ERR(peripheralStateInfo));
  3999. plat_priv->sec_peri_feature_disable = true;
  4000. return 0;
  4001. }
  4002. cnss_pr_dbg("Secure HW state: %d\n", *peripheralStateInfo);
  4003. if ((*peripheralStateInfo >> (HW_WIFI_UID - 0x500)) & 0x1)
  4004. set_bit(CNSS_WLAN_HW_DISABLED,
  4005. &plat_priv->driver_state);
  4006. else
  4007. clear_bit(CNSS_WLAN_HW_DISABLED,
  4008. &plat_priv->driver_state);
  4009. return 0;
  4010. }
  4011. #else
  4012. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  4013. {
  4014. struct Object client_env;
  4015. struct Object app_object;
  4016. u32 wifi_uid = HW_WIFI_UID;
  4017. union ObjectArg obj_arg[2] = {{{0, 0}}};
  4018. int ret;
  4019. u8 state = 0;
  4020. /* Once this flag is set, secure peripheral feature
  4021. * will not be supported till next reboot
  4022. */
  4023. if (plat_priv->sec_peri_feature_disable)
  4024. return 0;
  4025. /* get rootObj */
  4026. ret = get_client_env_object(&client_env);
  4027. if (ret) {
  4028. cnss_pr_dbg("Failed to get client_env_object, ret: %d\n", ret);
  4029. goto end;
  4030. }
  4031. ret = IClientEnv_open(client_env, HW_STATE_UID, &app_object);
  4032. if (ret) {
  4033. cnss_pr_dbg("Failed to get app_object, ret: %d\n", ret);
  4034. if (ret == FEATURE_NOT_SUPPORTED) {
  4035. ret = 0; /* Do not Assert */
  4036. plat_priv->sec_peri_feature_disable = true;
  4037. cnss_pr_dbg("Secure HW feature not supported\n");
  4038. }
  4039. goto exit_release_clientenv;
  4040. }
  4041. obj_arg[0].b = (struct ObjectBuf) {&wifi_uid, sizeof(u32)};
  4042. obj_arg[1].b = (struct ObjectBuf) {&state, sizeof(u8)};
  4043. ret = Object_invoke(app_object, HW_OP_GET_STATE, obj_arg,
  4044. ObjectCounts_pack(1, 1, 0, 0));
  4045. cnss_pr_dbg("SMC invoke ret: %d state: %d\n", ret, state);
  4046. if (ret) {
  4047. if (ret == PERIPHERAL_NOT_FOUND) {
  4048. ret = 0; /* Do not Assert */
  4049. plat_priv->sec_peri_feature_disable = true;
  4050. cnss_pr_dbg("Secure HW mode is not updated. Peripheral not found\n");
  4051. }
  4052. goto exit_release_app_obj;
  4053. }
  4054. if (state == 1)
  4055. set_bit(CNSS_WLAN_HW_DISABLED,
  4056. &plat_priv->driver_state);
  4057. else
  4058. clear_bit(CNSS_WLAN_HW_DISABLED,
  4059. &plat_priv->driver_state);
  4060. exit_release_app_obj:
  4061. Object_release(app_object);
  4062. exit_release_clientenv:
  4063. Object_release(client_env);
  4064. end:
  4065. if (ret) {
  4066. cnss_pr_err("Unable to get HW disable status\n");
  4067. CNSS_ASSERT(0);
  4068. }
  4069. return ret;
  4070. }
  4071. #endif
  4072. #else
  4073. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  4074. {
  4075. return 0;
  4076. }
  4077. #endif
  4078. #ifdef CONFIG_DISABLE_CNSS_SRAM_DUMP
  4079. static void cnss_sram_dump_init(struct cnss_plat_data *plat_priv)
  4080. {
  4081. }
  4082. #else
  4083. static void cnss_sram_dump_init(struct cnss_plat_data *plat_priv)
  4084. {
  4085. if (plat_priv->device_id == QCA6490_DEVICE_ID &&
  4086. cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01)
  4087. plat_priv->sram_dump = kcalloc(SRAM_DUMP_SIZE, 1, GFP_KERNEL);
  4088. }
  4089. #endif
  4090. #if IS_ENABLED(CONFIG_WCNSS_MEM_PRE_ALLOC)
  4091. static void cnss_initialize_mem_pool(unsigned long device_id)
  4092. {
  4093. cnss_initialize_prealloc_pool(device_id);
  4094. }
  4095. static void cnss_deinitialize_mem_pool(void)
  4096. {
  4097. cnss_deinitialize_prealloc_pool();
  4098. }
  4099. #else
  4100. static void cnss_initialize_mem_pool(unsigned long device_id)
  4101. {
  4102. }
  4103. static void cnss_deinitialize_mem_pool(void)
  4104. {
  4105. }
  4106. #endif
  4107. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  4108. {
  4109. int ret;
  4110. ret = cnss_init_sol_gpio(plat_priv);
  4111. if (ret)
  4112. return ret;
  4113. timer_setup(&plat_priv->fw_boot_timer,
  4114. cnss_bus_fw_boot_timeout_hdlr, 0);
  4115. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  4116. if (ret)
  4117. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  4118. ret);
  4119. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  4120. init_completion(&plat_priv->power_up_complete);
  4121. init_completion(&plat_priv->cal_complete);
  4122. init_completion(&plat_priv->rddm_complete);
  4123. init_completion(&plat_priv->recovery_complete);
  4124. init_completion(&plat_priv->daemon_connected);
  4125. mutex_init(&plat_priv->dev_lock);
  4126. mutex_init(&plat_priv->driver_ops_lock);
  4127. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  4128. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  4129. if (ret)
  4130. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  4131. ret);
  4132. plat_priv->recovery_ws =
  4133. wakeup_source_register(&plat_priv->plat_dev->dev,
  4134. "CNSS_FW_RECOVERY");
  4135. if (!plat_priv->recovery_ws)
  4136. cnss_pr_err("Failed to setup FW recovery wake source\n");
  4137. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  4138. cnss_daemon_connection_update_cb,
  4139. plat_priv);
  4140. if (ret)
  4141. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  4142. ret);
  4143. cnss_sram_dump_init(plat_priv);
  4144. if (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4145. "qcom,rc-ep-short-channel"))
  4146. cnss_set_feature_list(plat_priv, CNSS_RC_EP_ULTRASHORT_CHANNEL_V01);
  4147. if (plat_priv->device_id == PEACH_DEVICE_ID)
  4148. cnss_set_feature_list(plat_priv, CNSS_AUX_UC_SUPPORT_V01);
  4149. return 0;
  4150. }
  4151. #ifdef CONFIG_DISABLE_CNSS_SRAM_DUMP
  4152. static void cnss_sram_dump_deinit(struct cnss_plat_data *plat_priv)
  4153. {
  4154. }
  4155. #else
  4156. static void cnss_sram_dump_deinit(struct cnss_plat_data *plat_priv)
  4157. {
  4158. if (plat_priv->device_id == QCA6490_DEVICE_ID &&
  4159. cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01)
  4160. kfree(plat_priv->sram_dump);
  4161. }
  4162. #endif
  4163. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  4164. {
  4165. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  4166. plat_priv);
  4167. complete_all(&plat_priv->recovery_complete);
  4168. complete_all(&plat_priv->rddm_complete);
  4169. complete_all(&plat_priv->cal_complete);
  4170. complete_all(&plat_priv->power_up_complete);
  4171. complete_all(&plat_priv->daemon_connected);
  4172. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  4173. unregister_reboot_notifier(&plat_priv->reboot_nb);
  4174. del_timer(&plat_priv->fw_boot_timer);
  4175. wakeup_source_unregister(plat_priv->recovery_ws);
  4176. cnss_deinit_sol_gpio(plat_priv);
  4177. cnss_sram_dump_deinit(plat_priv);
  4178. kfree(plat_priv->on_chip_pmic_board_ids);
  4179. }
  4180. static void cnss_init_time_sync_period_default(struct cnss_plat_data *plat_priv)
  4181. {
  4182. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_WLAN] =
  4183. CNSS_TIME_SYNC_PERIOD_INVALID;
  4184. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_CNSS] =
  4185. CNSS_TIME_SYNC_PERIOD_DEFAULT;
  4186. }
  4187. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  4188. {
  4189. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  4190. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  4191. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4192. "qcom,wlan-cbc-enabled");
  4193. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  4194. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  4195. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  4196. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  4197. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  4198. cnss_init_time_sync_period_default(plat_priv);
  4199. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  4200. * enabled by default
  4201. */
  4202. plat_priv->adsp_pc_enabled = true;
  4203. }
  4204. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  4205. {
  4206. struct device *dev = &plat_priv->plat_dev->dev;
  4207. plat_priv->use_pm_domain =
  4208. of_property_read_bool(dev->of_node, "use-pm-domain");
  4209. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  4210. }
  4211. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  4212. {
  4213. struct device *dev = &plat_priv->plat_dev->dev;
  4214. plat_priv->set_wlaon_pwr_ctrl =
  4215. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  4216. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  4217. plat_priv->set_wlaon_pwr_ctrl);
  4218. }
  4219. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  4220. {
  4221. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4222. "qcom,converged-dt") ||
  4223. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4224. "qcom,same-dt-multi-dev") ||
  4225. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4226. "qcom,multi-wlan-exchg"));
  4227. }
  4228. static const struct platform_device_id cnss_platform_id_table[] = {
  4229. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  4230. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  4231. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  4232. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  4233. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  4234. { .name = "mango", .driver_data = MANGO_DEVICE_ID, },
  4235. { .name = "peach", .driver_data = PEACH_DEVICE_ID, },
  4236. { .name = "qcaconv", .driver_data = 0, },
  4237. { },
  4238. };
  4239. static const struct of_device_id cnss_of_match_table[] = {
  4240. {
  4241. .compatible = "qcom,cnss",
  4242. .data = (void *)&cnss_platform_id_table[0]},
  4243. {
  4244. .compatible = "qcom,cnss-qca6290",
  4245. .data = (void *)&cnss_platform_id_table[1]},
  4246. {
  4247. .compatible = "qcom,cnss-qca6390",
  4248. .data = (void *)&cnss_platform_id_table[2]},
  4249. {
  4250. .compatible = "qcom,cnss-qca6490",
  4251. .data = (void *)&cnss_platform_id_table[3]},
  4252. {
  4253. .compatible = "qcom,cnss-kiwi",
  4254. .data = (void *)&cnss_platform_id_table[4]},
  4255. {
  4256. .compatible = "qcom,cnss-mango",
  4257. .data = (void *)&cnss_platform_id_table[5]},
  4258. {
  4259. .compatible = "qcom,cnss-peach",
  4260. .data = (void *)&cnss_platform_id_table[6]},
  4261. {
  4262. .compatible = "qcom,cnss-qca-converged",
  4263. .data = (void *)&cnss_platform_id_table[7]},
  4264. { },
  4265. };
  4266. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  4267. static inline bool
  4268. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  4269. {
  4270. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4271. "use-nv-mac");
  4272. }
  4273. static int cnss_get_dev_cfg_node(struct cnss_plat_data *plat_priv)
  4274. {
  4275. struct device_node *child;
  4276. u32 id, i;
  4277. int id_n, device_identifier_gpio, ret;
  4278. u8 gpio_value;
  4279. if (plat_priv->dt_type != CNSS_DTT_CONVERGED)
  4280. return 0;
  4281. /* Parses the wlan_sw_ctrl gpio which is used to identify device */
  4282. ret = cnss_get_wlan_sw_ctrl(plat_priv);
  4283. if (ret) {
  4284. cnss_pr_dbg("Failed to parse wlan_sw_ctrl gpio, error:%d", ret);
  4285. return ret;
  4286. }
  4287. device_identifier_gpio = plat_priv->pinctrl_info.wlan_sw_ctrl_gpio;
  4288. gpio_value = gpio_get_value(device_identifier_gpio);
  4289. cnss_pr_dbg("Value of Device Identifier GPIO: %d\n", gpio_value);
  4290. for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node,
  4291. child) {
  4292. if (strcmp(child->name, "chip_cfg"))
  4293. continue;
  4294. id_n = of_property_count_u32_elems(child, "supported-ids");
  4295. if (id_n <= 0) {
  4296. cnss_pr_err("Device id is NOT set\n");
  4297. return -EINVAL;
  4298. }
  4299. for (i = 0; i < id_n; i++) {
  4300. ret = of_property_read_u32_index(child,
  4301. "supported-ids",
  4302. i, &id);
  4303. if (ret) {
  4304. cnss_pr_err("Failed to read supported ids\n");
  4305. return -EINVAL;
  4306. }
  4307. if (gpio_value && id == QCA6490_DEVICE_ID) {
  4308. plat_priv->plat_dev->dev.of_node = child;
  4309. plat_priv->device_id = QCA6490_DEVICE_ID;
  4310. cnss_utils_update_device_type(CNSS_HSP_DEVICE_TYPE);
  4311. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  4312. child->name, i, id);
  4313. return 0;
  4314. } else if (!gpio_value && id == KIWI_DEVICE_ID) {
  4315. plat_priv->plat_dev->dev.of_node = child;
  4316. plat_priv->device_id = KIWI_DEVICE_ID;
  4317. cnss_utils_update_device_type(CNSS_HMT_DEVICE_TYPE);
  4318. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  4319. child->name, i, id);
  4320. return 0;
  4321. }
  4322. }
  4323. }
  4324. return -EINVAL;
  4325. }
  4326. static inline u32
  4327. cnss_dt_type(struct cnss_plat_data *plat_priv)
  4328. {
  4329. bool is_converged_dt = of_property_read_bool(
  4330. plat_priv->plat_dev->dev.of_node, "qcom,converged-dt");
  4331. bool is_multi_wlan_xchg;
  4332. if (is_converged_dt)
  4333. return CNSS_DTT_CONVERGED;
  4334. is_multi_wlan_xchg = of_property_read_bool(
  4335. plat_priv->plat_dev->dev.of_node, "qcom,multi-wlan-exchg");
  4336. if (is_multi_wlan_xchg)
  4337. return CNSS_DTT_MULTIEXCHG;
  4338. return CNSS_DTT_LEGACY;
  4339. }
  4340. static int cnss_wlan_device_init(struct cnss_plat_data *plat_priv)
  4341. {
  4342. int ret = 0;
  4343. int retry = 0;
  4344. if (test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  4345. return 0;
  4346. retry:
  4347. ret = cnss_power_on_device(plat_priv, true);
  4348. if (ret)
  4349. goto end;
  4350. ret = cnss_bus_init(plat_priv);
  4351. if (ret) {
  4352. if ((ret != -EPROBE_DEFER) &&
  4353. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  4354. cnss_power_off_device(plat_priv);
  4355. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  4356. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  4357. goto retry;
  4358. }
  4359. goto power_off;
  4360. }
  4361. return 0;
  4362. power_off:
  4363. cnss_power_off_device(plat_priv);
  4364. end:
  4365. return ret;
  4366. }
  4367. int cnss_wlan_hw_enable(void)
  4368. {
  4369. struct cnss_plat_data *plat_priv;
  4370. int ret = 0;
  4371. if (cnss_is_dual_wlan_enabled())
  4372. plat_priv = cnss_get_first_plat_priv(NULL);
  4373. else
  4374. plat_priv = cnss_get_plat_priv(NULL);
  4375. if (!plat_priv)
  4376. return -ENODEV;
  4377. clear_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state);
  4378. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  4379. goto register_driver;
  4380. ret = cnss_wlan_device_init(plat_priv);
  4381. if (ret) {
  4382. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state))
  4383. CNSS_ASSERT(0);
  4384. return ret;
  4385. }
  4386. if (test_bit(CNSS_FS_READY, &plat_priv->driver_state))
  4387. cnss_driver_event_post(plat_priv,
  4388. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  4389. 0, NULL);
  4390. register_driver:
  4391. if (plat_priv->driver_ops)
  4392. ret = cnss_wlan_register_driver(plat_priv->driver_ops);
  4393. return ret;
  4394. }
  4395. EXPORT_SYMBOL(cnss_wlan_hw_enable);
  4396. int cnss_set_wfc_mode(struct device *dev, struct cnss_wfc_cfg cfg)
  4397. {
  4398. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  4399. int ret = 0;
  4400. if (!plat_priv)
  4401. return -ENODEV;
  4402. /* If IMS server is connected, return success without QMI send */
  4403. if (test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  4404. cnss_pr_dbg("Ignore host request as IMS server is connected");
  4405. return ret;
  4406. }
  4407. ret = cnss_wlfw_send_host_wfc_call_status(plat_priv, cfg);
  4408. return ret;
  4409. }
  4410. EXPORT_SYMBOL(cnss_set_wfc_mode);
  4411. static int cnss_tcdev_get_max_state(struct thermal_cooling_device *tcdev,
  4412. unsigned long *thermal_state)
  4413. {
  4414. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4415. if (!tcdev || !tcdev->devdata) {
  4416. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  4417. return -EINVAL;
  4418. }
  4419. cnss_tcdev = tcdev->devdata;
  4420. *thermal_state = cnss_tcdev->max_thermal_state;
  4421. return 0;
  4422. }
  4423. static int cnss_tcdev_get_cur_state(struct thermal_cooling_device *tcdev,
  4424. unsigned long *thermal_state)
  4425. {
  4426. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4427. if (!tcdev || !tcdev->devdata) {
  4428. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  4429. return -EINVAL;
  4430. }
  4431. cnss_tcdev = tcdev->devdata;
  4432. *thermal_state = cnss_tcdev->curr_thermal_state;
  4433. return 0;
  4434. }
  4435. static int cnss_tcdev_set_cur_state(struct thermal_cooling_device *tcdev,
  4436. unsigned long thermal_state)
  4437. {
  4438. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4439. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  4440. int ret = 0;
  4441. if (!tcdev || !tcdev->devdata) {
  4442. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  4443. return -EINVAL;
  4444. }
  4445. cnss_tcdev = tcdev->devdata;
  4446. if (thermal_state > cnss_tcdev->max_thermal_state)
  4447. return -EINVAL;
  4448. cnss_pr_vdbg("Cooling device set current state: %ld,for cdev id %d",
  4449. thermal_state, cnss_tcdev->tcdev_id);
  4450. mutex_lock(&plat_priv->tcdev_lock);
  4451. ret = cnss_bus_set_therm_cdev_state(plat_priv,
  4452. thermal_state,
  4453. cnss_tcdev->tcdev_id);
  4454. if (!ret)
  4455. cnss_tcdev->curr_thermal_state = thermal_state;
  4456. mutex_unlock(&plat_priv->tcdev_lock);
  4457. if (ret) {
  4458. cnss_pr_err("Setting Current Thermal State Failed: %d,for cdev id %d",
  4459. ret, cnss_tcdev->tcdev_id);
  4460. return ret;
  4461. }
  4462. return 0;
  4463. }
  4464. static struct thermal_cooling_device_ops cnss_cooling_ops = {
  4465. .get_max_state = cnss_tcdev_get_max_state,
  4466. .get_cur_state = cnss_tcdev_get_cur_state,
  4467. .set_cur_state = cnss_tcdev_set_cur_state,
  4468. };
  4469. int cnss_thermal_cdev_register(struct device *dev, unsigned long max_state,
  4470. int tcdev_id)
  4471. {
  4472. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  4473. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4474. char cdev_node_name[THERMAL_NAME_LENGTH] = "";
  4475. struct device_node *dev_node;
  4476. int ret = 0;
  4477. if (!priv) {
  4478. cnss_pr_err("Platform driver is not initialized!\n");
  4479. return -ENODEV;
  4480. }
  4481. cnss_tcdev = kzalloc(sizeof(*cnss_tcdev), GFP_KERNEL);
  4482. if (!cnss_tcdev) {
  4483. cnss_pr_err("Failed to allocate cnss_tcdev object!\n");
  4484. return -ENOMEM;
  4485. }
  4486. cnss_tcdev->tcdev_id = tcdev_id;
  4487. cnss_tcdev->max_thermal_state = max_state;
  4488. snprintf(cdev_node_name, THERMAL_NAME_LENGTH,
  4489. "qcom,cnss_cdev%d", tcdev_id);
  4490. dev_node = of_find_node_by_name(NULL, cdev_node_name);
  4491. if (!dev_node) {
  4492. cnss_pr_err("Failed to get cooling device node\n");
  4493. kfree(cnss_tcdev);
  4494. return -EINVAL;
  4495. }
  4496. cnss_pr_dbg("tcdev node->name=%s\n", dev_node->name);
  4497. if (of_find_property(dev_node, "#cooling-cells", NULL)) {
  4498. cnss_tcdev->tcdev = thermal_of_cooling_device_register(dev_node,
  4499. cdev_node_name,
  4500. cnss_tcdev,
  4501. &cnss_cooling_ops);
  4502. if (IS_ERR_OR_NULL(cnss_tcdev->tcdev)) {
  4503. ret = PTR_ERR(cnss_tcdev->tcdev);
  4504. cnss_pr_err("Cooling device register failed: %d, for cdev id %d\n",
  4505. ret, cnss_tcdev->tcdev_id);
  4506. kfree(cnss_tcdev);
  4507. } else {
  4508. cnss_pr_dbg("Cooling device registered for cdev id %d",
  4509. cnss_tcdev->tcdev_id);
  4510. mutex_lock(&priv->tcdev_lock);
  4511. list_add(&cnss_tcdev->tcdev_list,
  4512. &priv->cnss_tcdev_list);
  4513. mutex_unlock(&priv->tcdev_lock);
  4514. }
  4515. } else {
  4516. cnss_pr_dbg("Cooling device registration not supported");
  4517. kfree(cnss_tcdev);
  4518. ret = -EOPNOTSUPP;
  4519. }
  4520. return ret;
  4521. }
  4522. EXPORT_SYMBOL(cnss_thermal_cdev_register);
  4523. void cnss_thermal_cdev_unregister(struct device *dev, int tcdev_id)
  4524. {
  4525. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  4526. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4527. if (!priv) {
  4528. cnss_pr_err("Platform driver is not initialized!\n");
  4529. return;
  4530. }
  4531. mutex_lock(&priv->tcdev_lock);
  4532. while (!list_empty(&priv->cnss_tcdev_list)) {
  4533. cnss_tcdev = list_first_entry(&priv->cnss_tcdev_list,
  4534. struct cnss_thermal_cdev,
  4535. tcdev_list);
  4536. thermal_cooling_device_unregister(cnss_tcdev->tcdev);
  4537. list_del(&cnss_tcdev->tcdev_list);
  4538. kfree(cnss_tcdev);
  4539. }
  4540. mutex_unlock(&priv->tcdev_lock);
  4541. }
  4542. EXPORT_SYMBOL(cnss_thermal_cdev_unregister);
  4543. int cnss_get_curr_therm_cdev_state(struct device *dev,
  4544. unsigned long *thermal_state,
  4545. int tcdev_id)
  4546. {
  4547. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  4548. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4549. if (!priv) {
  4550. cnss_pr_err("Platform driver is not initialized!\n");
  4551. return -ENODEV;
  4552. }
  4553. mutex_lock(&priv->tcdev_lock);
  4554. list_for_each_entry(cnss_tcdev, &priv->cnss_tcdev_list, tcdev_list) {
  4555. if (cnss_tcdev->tcdev_id != tcdev_id)
  4556. continue;
  4557. *thermal_state = cnss_tcdev->curr_thermal_state;
  4558. mutex_unlock(&priv->tcdev_lock);
  4559. cnss_pr_dbg("Cooling device current state: %ld, for cdev id %d",
  4560. cnss_tcdev->curr_thermal_state, tcdev_id);
  4561. return 0;
  4562. }
  4563. mutex_unlock(&priv->tcdev_lock);
  4564. cnss_pr_dbg("Cooling device ID not found: %d", tcdev_id);
  4565. return -EINVAL;
  4566. }
  4567. EXPORT_SYMBOL(cnss_get_curr_therm_cdev_state);
  4568. static int cnss_probe(struct platform_device *plat_dev)
  4569. {
  4570. int ret = 0;
  4571. struct cnss_plat_data *plat_priv;
  4572. const struct of_device_id *of_id;
  4573. const struct platform_device_id *device_id;
  4574. if (cnss_get_plat_priv(plat_dev)) {
  4575. cnss_pr_err("Driver is already initialized!\n");
  4576. ret = -EEXIST;
  4577. goto out;
  4578. }
  4579. ret = cnss_plat_env_available();
  4580. if (ret)
  4581. goto out;
  4582. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  4583. if (!of_id || !of_id->data) {
  4584. cnss_pr_err("Failed to find of match device!\n");
  4585. ret = -ENODEV;
  4586. goto out;
  4587. }
  4588. device_id = of_id->data;
  4589. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  4590. GFP_KERNEL);
  4591. if (!plat_priv) {
  4592. ret = -ENOMEM;
  4593. goto out;
  4594. }
  4595. plat_priv->plat_dev = plat_dev;
  4596. plat_priv->dev_node = NULL;
  4597. plat_priv->device_id = device_id->driver_data;
  4598. plat_priv->dt_type = cnss_dt_type(plat_priv);
  4599. cnss_pr_dbg("Probing platform driver from dt type: %d\n",
  4600. plat_priv->dt_type);
  4601. plat_priv->use_fw_path_with_prefix =
  4602. cnss_use_fw_path_with_prefix(plat_priv);
  4603. ret = cnss_get_dev_cfg_node(plat_priv);
  4604. if (ret) {
  4605. cnss_pr_err("Failed to get device cfg node, err = %d\n", ret);
  4606. goto reset_plat_dev;
  4607. }
  4608. cnss_initialize_mem_pool(plat_priv->device_id);
  4609. ret = cnss_get_pld_bus_ops_name(plat_priv);
  4610. if (ret)
  4611. cnss_pr_vdbg("Failed to find bus ops name, err = %d\n",
  4612. ret);
  4613. ret = cnss_get_rc_num(plat_priv);
  4614. if (ret)
  4615. cnss_pr_err("Failed to find PCIe RC number, err = %d\n", ret);
  4616. cnss_pr_dbg("rc_num=%d\n", plat_priv->rc_num);
  4617. plat_priv->bus_type = cnss_get_bus_type(plat_priv);
  4618. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  4619. cnss_set_plat_priv(plat_dev, plat_priv);
  4620. cnss_set_device_name(plat_priv);
  4621. platform_set_drvdata(plat_dev, plat_priv);
  4622. INIT_LIST_HEAD(&plat_priv->vreg_list);
  4623. INIT_LIST_HEAD(&plat_priv->clk_list);
  4624. cnss_get_pm_domain_info(plat_priv);
  4625. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  4626. cnss_power_misc_params_init(plat_priv);
  4627. cnss_get_tcs_info(plat_priv);
  4628. cnss_get_cpr_info(plat_priv);
  4629. cnss_aop_interface_init(plat_priv);
  4630. cnss_init_control_params(plat_priv);
  4631. ret = cnss_get_resources(plat_priv);
  4632. if (ret)
  4633. goto reset_ctx;
  4634. ret = cnss_register_esoc(plat_priv);
  4635. if (ret)
  4636. goto free_res;
  4637. ret = cnss_register_bus_scale(plat_priv);
  4638. if (ret)
  4639. goto unreg_esoc;
  4640. ret = cnss_create_sysfs(plat_priv);
  4641. if (ret)
  4642. goto unreg_bus_scale;
  4643. ret = cnss_event_work_init(plat_priv);
  4644. if (ret)
  4645. goto remove_sysfs;
  4646. ret = cnss_dms_init(plat_priv);
  4647. if (ret)
  4648. goto deinit_event_work;
  4649. ret = cnss_debugfs_create(plat_priv);
  4650. if (ret)
  4651. goto deinit_dms;
  4652. ret = cnss_misc_init(plat_priv);
  4653. if (ret)
  4654. goto destroy_debugfs;
  4655. ret = cnss_wlan_hw_disable_check(plat_priv);
  4656. if (ret)
  4657. goto deinit_misc;
  4658. /* Make sure all platform related init are done before
  4659. * device power on and bus init.
  4660. */
  4661. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  4662. ret = cnss_wlan_device_init(plat_priv);
  4663. if (ret)
  4664. goto deinit_misc;
  4665. } else {
  4666. cnss_pr_info("WLAN HW Disabled. Defer PCI enumeration\n");
  4667. }
  4668. cnss_register_coex_service(plat_priv);
  4669. cnss_register_ims_service(plat_priv);
  4670. mutex_init(&plat_priv->tcdev_lock);
  4671. INIT_LIST_HEAD(&plat_priv->cnss_tcdev_list);
  4672. cnss_pr_info("Platform driver probed successfully.\n");
  4673. return 0;
  4674. deinit_misc:
  4675. cnss_misc_deinit(plat_priv);
  4676. destroy_debugfs:
  4677. cnss_debugfs_destroy(plat_priv);
  4678. deinit_dms:
  4679. cnss_dms_deinit(plat_priv);
  4680. deinit_event_work:
  4681. cnss_event_work_deinit(plat_priv);
  4682. remove_sysfs:
  4683. cnss_remove_sysfs(plat_priv);
  4684. unreg_bus_scale:
  4685. cnss_unregister_bus_scale(plat_priv);
  4686. unreg_esoc:
  4687. cnss_unregister_esoc(plat_priv);
  4688. free_res:
  4689. cnss_put_resources(plat_priv);
  4690. reset_ctx:
  4691. cnss_aop_interface_deinit(plat_priv);
  4692. platform_set_drvdata(plat_dev, NULL);
  4693. cnss_deinitialize_mem_pool();
  4694. reset_plat_dev:
  4695. cnss_clear_plat_priv(plat_priv);
  4696. out:
  4697. return ret;
  4698. }
  4699. static int cnss_remove(struct platform_device *plat_dev)
  4700. {
  4701. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  4702. plat_priv->audio_iommu_domain = NULL;
  4703. cnss_genl_exit();
  4704. cnss_unregister_ims_service(plat_priv);
  4705. cnss_unregister_coex_service(plat_priv);
  4706. cnss_bus_deinit(plat_priv);
  4707. cnss_misc_deinit(plat_priv);
  4708. cnss_debugfs_destroy(plat_priv);
  4709. cnss_dms_deinit(plat_priv);
  4710. cnss_qmi_deinit(plat_priv);
  4711. cnss_event_work_deinit(plat_priv);
  4712. cnss_cancel_dms_work();
  4713. cnss_remove_sysfs(plat_priv);
  4714. cnss_unregister_bus_scale(plat_priv);
  4715. cnss_unregister_esoc(plat_priv);
  4716. cnss_put_resources(plat_priv);
  4717. cnss_aop_interface_deinit(plat_priv);
  4718. cnss_deinitialize_mem_pool();
  4719. platform_set_drvdata(plat_dev, NULL);
  4720. cnss_clear_plat_priv(plat_priv);
  4721. return 0;
  4722. }
  4723. static struct platform_driver cnss_platform_driver = {
  4724. .probe = cnss_probe,
  4725. .remove = cnss_remove,
  4726. .driver = {
  4727. .name = "cnss2",
  4728. .of_match_table = cnss_of_match_table,
  4729. #ifdef CONFIG_CNSS_ASYNC
  4730. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  4731. #endif
  4732. },
  4733. };
  4734. static bool cnss_check_compatible_node(void)
  4735. {
  4736. struct device_node *dn = NULL;
  4737. for_each_matching_node(dn, cnss_of_match_table) {
  4738. if (of_device_is_available(dn)) {
  4739. cnss_allow_driver_loading = true;
  4740. return true;
  4741. }
  4742. }
  4743. return false;
  4744. }
  4745. /**
  4746. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  4747. *
  4748. * Valid device tree node means a node with "compatible" property from the
  4749. * device match table and "status" property is not disabled.
  4750. *
  4751. * Return: true if valid device tree node found, false if not found
  4752. */
  4753. static bool cnss_is_valid_dt_node_found(void)
  4754. {
  4755. struct device_node *dn = NULL;
  4756. for_each_matching_node(dn, cnss_of_match_table) {
  4757. if (of_device_is_available(dn))
  4758. break;
  4759. }
  4760. if (dn)
  4761. return true;
  4762. return false;
  4763. }
  4764. static int __init cnss_initialize(void)
  4765. {
  4766. int ret = 0;
  4767. if (!cnss_is_valid_dt_node_found())
  4768. return -ENODEV;
  4769. if (!cnss_check_compatible_node())
  4770. return ret;
  4771. cnss_debug_init();
  4772. ret = platform_driver_register(&cnss_platform_driver);
  4773. if (ret)
  4774. cnss_debug_deinit();
  4775. ret = cnss_genl_init();
  4776. if (ret < 0)
  4777. cnss_pr_err("CNSS genl init failed %d\n", ret);
  4778. cnss_init_plat_env_count();
  4779. return ret;
  4780. }
  4781. static void __exit cnss_exit(void)
  4782. {
  4783. cnss_genl_exit();
  4784. platform_driver_unregister(&cnss_platform_driver);
  4785. cnss_debug_deinit();
  4786. }
  4787. module_init(cnss_initialize);
  4788. module_exit(cnss_exit);
  4789. MODULE_LICENSE("GPL v2");
  4790. MODULE_DESCRIPTION("CNSS2 Platform Driver");