sde_rotator_base.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012, 2015-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "%s: " fmt, __func__
  6. #include <linux/errno.h>
  7. #include <linux/file.h>
  8. #include <linux/spinlock.h>
  9. #include <linux/types.h>
  10. #include <linux/major.h>
  11. #include <linux/debugfs.h>
  12. #include <linux/clk.h>
  13. #include <linux/slab.h>
  14. #include <linux/io.h>
  15. #include <linux/iopoll.h>
  16. #include <linux/msm-bus.h>
  17. #include <linux/msm-bus-board.h>
  18. #include <linux/regulator/consumer.h>
  19. #define CREATE_TRACE_POINTS
  20. #include "sde_rotator_base.h"
  21. #include "sde_rotator_util.h"
  22. #include "sde_rotator_trace.h"
  23. #include "sde_rotator_debug.h"
  24. #include "sde_rotator_dev.h"
  25. #include "sde_rotator_vbif.h"
  26. static inline u64 fudge_factor(u64 val, u32 numer, u32 denom)
  27. {
  28. u64 result = (val * (u64)numer);
  29. do_div(result, denom);
  30. return result;
  31. }
  32. static inline u64 apply_fudge_factor(u64 val,
  33. struct sde_mult_factor *factor)
  34. {
  35. return fudge_factor(val, factor->numer, factor->denom);
  36. }
  37. static inline u64 apply_inverse_fudge_factor(u64 val,
  38. struct sde_mult_factor *factor)
  39. {
  40. return fudge_factor(val, factor->denom, factor->numer);
  41. }
  42. static inline bool validate_comp_ratio(struct sde_mult_factor *factor)
  43. {
  44. return factor->numer && factor->denom;
  45. }
  46. u32 sde_apply_comp_ratio_factor(u32 quota,
  47. struct sde_mdp_format_params *fmt,
  48. struct sde_mult_factor *factor)
  49. {
  50. struct sde_rot_data_type *mdata = sde_rot_get_mdata();
  51. if (!mdata || !test_bit(SDE_QOS_OVERHEAD_FACTOR,
  52. mdata->sde_qos_map))
  53. return quota;
  54. /* apply compression ratio, only for compressed formats */
  55. if (sde_mdp_is_ubwc_format(fmt) &&
  56. validate_comp_ratio(factor))
  57. quota = apply_inverse_fudge_factor(quota, factor);
  58. return quota;
  59. }
  60. #define RES_1080p (1088*1920)
  61. #define RES_UHD (3840*2160)
  62. #define RES_WQXGA (2560*1600)
  63. #define XIN_HALT_TIMEOUT_US 0x4000
  64. static int sde_mdp_wait_for_xin_halt(u32 xin_id)
  65. {
  66. void __iomem *vbif_base;
  67. u32 status;
  68. struct sde_rot_data_type *mdata = sde_rot_get_mdata();
  69. u32 idle_mask = BIT(xin_id);
  70. int rc;
  71. vbif_base = mdata->vbif_nrt_io.base;
  72. rc = readl_poll_timeout(vbif_base + MMSS_VBIF_XIN_HALT_CTRL1,
  73. status, (status & idle_mask),
  74. 1000, XIN_HALT_TIMEOUT_US);
  75. if (rc == -ETIMEDOUT) {
  76. SDEROT_ERR("VBIF client %d not halting. TIMEDOUT.\n",
  77. xin_id);
  78. } else {
  79. SDEROT_DBG("VBIF client %d is halted\n", xin_id);
  80. }
  81. return rc;
  82. }
  83. /**
  84. * force_on_xin_clk() - enable/disable the force-on for the pipe clock
  85. * @bit_off: offset of the bit to enable/disable the force-on.
  86. * @reg_off: register offset for the clock control.
  87. * @enable: boolean to indicate if the force-on of the clock needs to be
  88. * enabled or disabled.
  89. *
  90. * This function returns:
  91. * true - if the clock is forced-on by this function
  92. * false - if the clock was already forced on
  93. * It is the caller responsibility to check if this function is forcing
  94. * the clock on; if so, it will need to remove the force of the clock,
  95. * otherwise it should avoid to remove the force-on.
  96. * Clocks must be on when calling this function.
  97. */
  98. static bool force_on_xin_clk(u32 bit_off, u32 clk_ctl_reg_off, bool enable)
  99. {
  100. u32 val;
  101. u32 force_on_mask;
  102. struct sde_rot_data_type *mdata = sde_rot_get_mdata();
  103. bool clk_forced_on = false;
  104. force_on_mask = BIT(bit_off);
  105. val = readl_relaxed(mdata->mdp_base + clk_ctl_reg_off);
  106. clk_forced_on = !(force_on_mask & val);
  107. if (enable)
  108. val |= force_on_mask;
  109. else
  110. val &= ~force_on_mask;
  111. writel_relaxed(val, mdata->mdp_base + clk_ctl_reg_off);
  112. return clk_forced_on;
  113. }
  114. void vbif_lock(struct platform_device *parent_pdev)
  115. {
  116. if (!parent_pdev)
  117. return;
  118. mdp_vbif_lock(parent_pdev, true);
  119. }
  120. void vbif_unlock(struct platform_device *parent_pdev)
  121. {
  122. if (!parent_pdev)
  123. return;
  124. mdp_vbif_lock(parent_pdev, false);
  125. }
  126. void sde_mdp_halt_vbif_xin(struct sde_mdp_vbif_halt_params *params)
  127. {
  128. struct sde_rot_data_type *mdata = sde_rot_get_mdata();
  129. u32 reg_val;
  130. bool forced_on;
  131. int rc = 0;
  132. if (!mdata || !params || !params->reg_off_mdp_clk_ctrl) {
  133. SDEROT_ERR("null input parameter\n");
  134. return;
  135. }
  136. if (!mdata->parent_pdev &&
  137. params->xin_id > MMSS_VBIF_NRT_VBIF_CLK_FORCE_CTRL0_XIN1) {
  138. SDEROT_ERR("xin_id:%d exceed max limit\n", params->xin_id);
  139. return;
  140. }
  141. forced_on = force_on_xin_clk(params->bit_off_mdp_clk_ctrl,
  142. params->reg_off_mdp_clk_ctrl, true);
  143. vbif_lock(mdata->parent_pdev);
  144. SDEROT_EVTLOG(forced_on, params->xin_id);
  145. reg_val = SDE_VBIF_READ(mdata, MMSS_VBIF_XIN_HALT_CTRL0);
  146. SDE_VBIF_WRITE(mdata, MMSS_VBIF_XIN_HALT_CTRL0,
  147. reg_val | BIT(params->xin_id));
  148. /* this is a polling operation */
  149. rc = sde_mdp_wait_for_xin_halt(params->xin_id);
  150. if (rc == -ETIMEDOUT)
  151. params->xin_timeout = BIT(params->xin_id);
  152. reg_val = SDE_VBIF_READ(mdata, MMSS_VBIF_XIN_HALT_CTRL0);
  153. SDE_VBIF_WRITE(mdata, MMSS_VBIF_XIN_HALT_CTRL0,
  154. reg_val & ~BIT(params->xin_id));
  155. vbif_unlock(mdata->parent_pdev);
  156. if (forced_on)
  157. force_on_xin_clk(params->bit_off_mdp_clk_ctrl,
  158. params->reg_off_mdp_clk_ctrl, false);
  159. }
  160. u32 sde_mdp_get_ot_limit(u32 width, u32 height, u32 pixfmt, u32 fps, u32 is_rd)
  161. {
  162. struct sde_rot_data_type *mdata = sde_rot_get_mdata();
  163. struct sde_mdp_format_params *fmt;
  164. u32 ot_lim;
  165. u32 is_yuv;
  166. u64 res;
  167. ot_lim = (is_rd) ? mdata->default_ot_rd_limit :
  168. mdata->default_ot_wr_limit;
  169. /*
  170. * If default ot is not set from dt,
  171. * then do not configure it.
  172. */
  173. if (ot_lim == 0)
  174. goto exit;
  175. /* Modify the limits if the target and the use case requires it */
  176. if (false == test_bit(SDE_QOS_OTLIM, mdata->sde_qos_map))
  177. goto exit;
  178. width = min_t(u32, width, SDE_ROT_MAX_IMG_WIDTH);
  179. height = min_t(u32, height, SDE_ROT_MAX_IMG_HEIGHT);
  180. res = width * height;
  181. res = res * fps;
  182. fmt = sde_get_format_params(pixfmt);
  183. if (!fmt) {
  184. SDEROT_WARN("invalid format %8.8x\n", pixfmt);
  185. goto exit;
  186. }
  187. is_yuv = sde_mdp_is_yuv_format(fmt);
  188. SDEROT_DBG("w:%d h:%d fps:%d pixfmt:%8.8x yuv:%d res:%llu rd:%d\n",
  189. width, height, fps, pixfmt, is_yuv, res, is_rd);
  190. /*
  191. * If (total_source_pixels <= 62208000 && YUV) -> RD/WROT=2 //1080p30
  192. * If (total_source_pixels <= 124416000 && YUV) -> RD/WROT=4 //1080p60
  193. * If (total_source_pixels <= 2160p && YUV && FPS <= 30) -> RD/WROT = 32
  194. */
  195. switch (mdata->mdss_version) {
  196. case SDE_MDP_HW_REV_540:
  197. if (is_yuv) {
  198. if (res <= (RES_1080p * 30))
  199. ot_lim = 2;
  200. else if (res <= (RES_1080p * 60))
  201. ot_lim = 4;
  202. else if (res <= (RES_WQXGA * 60))
  203. ot_lim = 4;
  204. else if (res <= (RES_UHD * 30))
  205. ot_lim = 8;
  206. } else if (fmt->bpp == 4 && res <= (RES_WQXGA * 60)) {
  207. ot_lim = 16;
  208. }
  209. break;
  210. default:
  211. if (is_yuv) {
  212. if (res <= (RES_1080p * 30))
  213. ot_lim = 2;
  214. else if (res <= (RES_1080p * 60))
  215. ot_lim = 4;
  216. }
  217. break;
  218. }
  219. exit:
  220. SDEROT_DBG("ot_lim=%d\n", ot_lim);
  221. return ot_lim;
  222. }
  223. static u32 get_ot_limit(u32 reg_off, u32 bit_off,
  224. struct sde_mdp_set_ot_params *params)
  225. {
  226. struct sde_rot_data_type *mdata = sde_rot_get_mdata();
  227. u32 ot_lim;
  228. u32 val;
  229. ot_lim = sde_mdp_get_ot_limit(
  230. params->width, params->height,
  231. params->fmt, params->fps,
  232. params->reg_off_vbif_lim_conf == MMSS_VBIF_RD_LIM_CONF);
  233. /*
  234. * If default ot is not set from dt,
  235. * then do not configure it.
  236. */
  237. if (ot_lim == 0)
  238. goto exit;
  239. val = SDE_VBIF_READ(mdata, reg_off);
  240. val &= (0xFF << bit_off);
  241. val = val >> bit_off;
  242. SDEROT_EVTLOG(val, ot_lim);
  243. if (val == ot_lim)
  244. ot_lim = 0;
  245. exit:
  246. SDEROT_DBG("ot_lim=%d\n", ot_lim);
  247. SDEROT_EVTLOG(params->width, params->height, params->fmt, params->fps,
  248. ot_lim);
  249. return ot_lim;
  250. }
  251. void sde_mdp_set_ot_limit(struct sde_mdp_set_ot_params *params)
  252. {
  253. struct sde_rot_data_type *mdata = sde_rot_get_mdata();
  254. u32 ot_lim;
  255. u32 reg_off_vbif_lim_conf = ((params->xin_id / mdata->npriority_lvl)
  256. * mdata->npriority_lvl)
  257. + params->reg_off_vbif_lim_conf;
  258. u32 bit_off_vbif_lim_conf = (params->xin_id % mdata->npriority_lvl) * 8;
  259. u32 reg_val;
  260. u32 sts;
  261. bool forced_on;
  262. vbif_lock(mdata->parent_pdev);
  263. ot_lim = get_ot_limit(
  264. reg_off_vbif_lim_conf,
  265. bit_off_vbif_lim_conf,
  266. params) & 0xFF;
  267. if (ot_lim == 0)
  268. goto exit;
  269. if (params->rotsts_base && params->rotsts_busy_mask) {
  270. sts = readl_relaxed(params->rotsts_base);
  271. if (sts & params->rotsts_busy_mask) {
  272. SDEROT_ERR(
  273. "Rotator still busy, should not modify VBIF\n");
  274. SDEROT_EVTLOG_TOUT_HANDLER(
  275. "rot", "vbif_dbg_bus", "panic");
  276. }
  277. }
  278. trace_rot_perf_set_ot(params->num, params->xin_id, ot_lim);
  279. forced_on = force_on_xin_clk(params->bit_off_mdp_clk_ctrl,
  280. params->reg_off_mdp_clk_ctrl, true);
  281. reg_val = SDE_VBIF_READ(mdata, reg_off_vbif_lim_conf);
  282. reg_val &= ~(0xFF << bit_off_vbif_lim_conf);
  283. reg_val |= (ot_lim) << bit_off_vbif_lim_conf;
  284. SDE_VBIF_WRITE(mdata, reg_off_vbif_lim_conf, reg_val);
  285. reg_val = SDE_VBIF_READ(mdata, MMSS_VBIF_XIN_HALT_CTRL0);
  286. SDE_VBIF_WRITE(mdata, MMSS_VBIF_XIN_HALT_CTRL0,
  287. reg_val | BIT(params->xin_id));
  288. /* this is a polling operation */
  289. sde_mdp_wait_for_xin_halt(params->xin_id);
  290. reg_val = SDE_VBIF_READ(mdata, MMSS_VBIF_XIN_HALT_CTRL0);
  291. SDE_VBIF_WRITE(mdata, MMSS_VBIF_XIN_HALT_CTRL0,
  292. reg_val & ~BIT(params->xin_id));
  293. if (forced_on)
  294. force_on_xin_clk(params->bit_off_mdp_clk_ctrl,
  295. params->reg_off_mdp_clk_ctrl, false);
  296. SDEROT_EVTLOG(params->num, params->xin_id, ot_lim);
  297. exit:
  298. vbif_unlock(mdata->parent_pdev);
  299. return;
  300. }
  301. /*
  302. * sde_mdp_set_vbif_memtype - set memtype output for the given xin port
  303. * @mdata: pointer to global rotator data
  304. * @xin_id: xin identifier
  305. * @memtype: memtype output configuration
  306. * return: none
  307. */
  308. static void sde_mdp_set_vbif_memtype(struct sde_rot_data_type *mdata,
  309. u32 xin_id, u32 memtype)
  310. {
  311. u32 reg_off;
  312. u32 bit_off;
  313. u32 reg_val;
  314. /*
  315. * Assume 4 bits per bit field, 8 fields per 32-bit register.
  316. */
  317. if (xin_id >= 8)
  318. return;
  319. reg_off = MMSS_VBIF_NRT_VBIF_OUT_AXI_AMEMTYPE_CONF0;
  320. bit_off = (xin_id & 0x7) * 4;
  321. reg_val = SDE_VBIF_READ(mdata, reg_off);
  322. reg_val &= ~(0x7 << bit_off);
  323. reg_val |= (memtype & 0x7) << bit_off;
  324. SDE_VBIF_WRITE(mdata, reg_off, reg_val);
  325. }
  326. /*
  327. * sde_mdp_init_vbif - initialize static vbif configuration
  328. * return: 0 if success; error code otherwise
  329. */
  330. int sde_mdp_init_vbif(void)
  331. {
  332. struct sde_rot_data_type *mdata = sde_rot_get_mdata();
  333. int i;
  334. if (!mdata)
  335. return -EINVAL;
  336. if (mdata->vbif_memtype_count && mdata->vbif_memtype) {
  337. for (i = 0; i < mdata->vbif_memtype_count; i++)
  338. sde_mdp_set_vbif_memtype(mdata, i,
  339. mdata->vbif_memtype[i]);
  340. SDEROT_DBG("amemtype=0x%x\n", SDE_VBIF_READ(mdata,
  341. MMSS_VBIF_NRT_VBIF_OUT_AXI_AMEMTYPE_CONF0));
  342. }
  343. return 0;
  344. }
  345. struct reg_bus_client *sde_reg_bus_vote_client_create(char *client_name)
  346. {
  347. struct reg_bus_client *client;
  348. struct sde_rot_data_type *sde_res = sde_rot_get_mdata();
  349. static u32 id;
  350. if (client_name == NULL) {
  351. SDEROT_ERR("client name is null\n");
  352. return ERR_PTR(-EINVAL);
  353. }
  354. client = kzalloc(sizeof(struct reg_bus_client), GFP_KERNEL);
  355. if (!client)
  356. return ERR_PTR(-ENOMEM);
  357. mutex_lock(&sde_res->reg_bus_lock);
  358. strlcpy(client->name, client_name, MAX_CLIENT_NAME_LEN);
  359. client->usecase_ndx = VOTE_INDEX_DISABLE;
  360. client->id = id;
  361. SDEROT_DBG("bus vote client %s created:%pK id :%d\n", client_name,
  362. client, id);
  363. id++;
  364. list_add(&client->list, &sde_res->reg_bus_clist);
  365. mutex_unlock(&sde_res->reg_bus_lock);
  366. return client;
  367. }
  368. void sde_reg_bus_vote_client_destroy(struct reg_bus_client *client)
  369. {
  370. struct sde_rot_data_type *sde_res = sde_rot_get_mdata();
  371. if (!client) {
  372. SDEROT_ERR("reg bus vote: invalid client handle\n");
  373. } else {
  374. SDEROT_DBG("bus vote client %s destroyed:%pK id:%u\n",
  375. client->name, client, client->id);
  376. mutex_lock(&sde_res->reg_bus_lock);
  377. list_del_init(&client->list);
  378. mutex_unlock(&sde_res->reg_bus_lock);
  379. kfree(client);
  380. }
  381. }
  382. int sde_update_reg_bus_vote(struct reg_bus_client *bus_client, u32 usecase_ndx)
  383. {
  384. int ret = 0;
  385. bool changed = false;
  386. u32 max_usecase_ndx = VOTE_INDEX_DISABLE;
  387. struct reg_bus_client *client, *temp_client;
  388. struct sde_rot_data_type *sde_res = sde_rot_get_mdata();
  389. if (!sde_res || !sde_res->reg_bus_hdl || !bus_client)
  390. return 0;
  391. mutex_lock(&sde_res->reg_bus_lock);
  392. bus_client->usecase_ndx = usecase_ndx;
  393. list_for_each_entry_safe(client, temp_client, &sde_res->reg_bus_clist,
  394. list) {
  395. if (client->usecase_ndx < VOTE_INDEX_MAX &&
  396. client->usecase_ndx > max_usecase_ndx)
  397. max_usecase_ndx = client->usecase_ndx;
  398. }
  399. if (sde_res->reg_bus_usecase_ndx != max_usecase_ndx) {
  400. changed = true;
  401. sde_res->reg_bus_usecase_ndx = max_usecase_ndx;
  402. }
  403. SDEROT_DBG(
  404. "%pS: changed=%d current idx=%d request client %s id:%u idx:%d\n",
  405. __builtin_return_address(0), changed, max_usecase_ndx,
  406. bus_client->name, bus_client->id, usecase_ndx);
  407. if (changed)
  408. ret = msm_bus_scale_client_update_request(sde_res->reg_bus_hdl,
  409. max_usecase_ndx);
  410. mutex_unlock(&sde_res->reg_bus_lock);
  411. return ret;
  412. }
  413. static int sde_mdp_parse_dt_handler(struct platform_device *pdev,
  414. char *prop_name, u32 *offsets, int len)
  415. {
  416. int rc;
  417. rc = of_property_read_u32_array(pdev->dev.of_node, prop_name,
  418. offsets, len);
  419. if (rc) {
  420. SDEROT_DBG("Error from prop %s : u32 array read\n", prop_name);
  421. return -EINVAL;
  422. }
  423. return 0;
  424. }
  425. static int sde_mdp_parse_dt_prop_len(struct platform_device *pdev,
  426. char *prop_name)
  427. {
  428. int len = 0;
  429. of_find_property(pdev->dev.of_node, prop_name, &len);
  430. if (len < 1) {
  431. SDEROT_INFO("prop %s : doesn't exist in device tree\n",
  432. prop_name);
  433. return 0;
  434. }
  435. len = len/sizeof(u32);
  436. return len;
  437. }
  438. static void sde_mdp_parse_vbif_memtype(struct platform_device *pdev,
  439. struct sde_rot_data_type *mdata)
  440. {
  441. int rc;
  442. mdata->vbif_memtype_count = sde_mdp_parse_dt_prop_len(pdev,
  443. "qcom,mdss-rot-vbif-memtype");
  444. mdata->vbif_memtype = kcalloc(mdata->vbif_memtype_count,
  445. sizeof(u32), GFP_KERNEL);
  446. if (!mdata->vbif_memtype || !mdata->vbif_memtype_count) {
  447. mdata->vbif_memtype_count = 0;
  448. return;
  449. }
  450. rc = sde_mdp_parse_dt_handler(pdev,
  451. "qcom,mdss-rot-vbif-memtype", mdata->vbif_memtype,
  452. mdata->vbif_memtype_count);
  453. if (rc) {
  454. SDEROT_DBG("vbif memtype not found\n");
  455. kfree(mdata->vbif_memtype);
  456. mdata->vbif_memtype = NULL;
  457. mdata->vbif_memtype_count = 0;
  458. return;
  459. }
  460. }
  461. static void sde_mdp_parse_vbif_qos(struct platform_device *pdev,
  462. struct sde_rot_data_type *mdata)
  463. {
  464. int rc;
  465. mdata->vbif_rt_qos = NULL;
  466. mdata->npriority_lvl = sde_mdp_parse_dt_prop_len(pdev,
  467. "qcom,mdss-rot-vbif-qos-setting");
  468. mdata->vbif_nrt_qos = kcalloc(mdata->npriority_lvl,
  469. sizeof(u32), GFP_KERNEL);
  470. if (!mdata->vbif_nrt_qos || !mdata->npriority_lvl) {
  471. mdata->npriority_lvl = 0;
  472. return;
  473. }
  474. rc = sde_mdp_parse_dt_handler(pdev,
  475. "qcom,mdss-rot-vbif-qos-setting", mdata->vbif_nrt_qos,
  476. mdata->npriority_lvl);
  477. if (rc) {
  478. SDEROT_DBG("vbif setting not found\n");
  479. kfree(mdata->vbif_nrt_qos);
  480. mdata->vbif_nrt_qos = NULL;
  481. mdata->npriority_lvl = 0;
  482. return;
  483. }
  484. }
  485. static void sde_mdp_parse_vbif_xin_id(struct platform_device *pdev,
  486. struct sde_rot_data_type *mdata)
  487. {
  488. mdata->vbif_xin_id[XIN_SSPP] = XIN_SSPP;
  489. mdata->vbif_xin_id[XIN_WRITEBACK] = XIN_WRITEBACK;
  490. sde_mdp_parse_dt_handler(pdev, "qcom,mdss-rot-xin-id",
  491. mdata->vbif_xin_id, MAX_XIN);
  492. }
  493. static void sde_mdp_parse_cdp_setting(struct platform_device *pdev,
  494. struct sde_rot_data_type *mdata)
  495. {
  496. int rc;
  497. u32 len, data[SDE_ROT_OP_MAX] = {0};
  498. len = sde_mdp_parse_dt_prop_len(pdev,
  499. "qcom,mdss-rot-cdp-setting");
  500. if (len == SDE_ROT_OP_MAX) {
  501. rc = sde_mdp_parse_dt_handler(pdev,
  502. "qcom,mdss-rot-cdp-setting", data, len);
  503. if (rc) {
  504. SDEROT_ERR("invalid CDP setting\n");
  505. goto end;
  506. }
  507. set_bit(SDE_QOS_CDP, mdata->sde_qos_map);
  508. mdata->enable_cdp[SDE_ROT_RD] = data[SDE_ROT_RD];
  509. mdata->enable_cdp[SDE_ROT_WR] = data[SDE_ROT_WR];
  510. return;
  511. }
  512. end:
  513. clear_bit(SDE_QOS_CDP, mdata->sde_qos_map);
  514. }
  515. static void sde_mdp_parse_rot_lut_setting(struct platform_device *pdev,
  516. struct sde_rot_data_type *mdata)
  517. {
  518. int rc;
  519. u32 len, data[4];
  520. len = sde_mdp_parse_dt_prop_len(pdev, "qcom,mdss-rot-qos-lut");
  521. if (len == 4) {
  522. rc = sde_mdp_parse_dt_handler(pdev,
  523. "qcom,mdss-rot-qos-lut", data, len);
  524. if (!rc) {
  525. mdata->lut_cfg[SDE_ROT_RD].creq_lut_0 = data[0];
  526. mdata->lut_cfg[SDE_ROT_RD].creq_lut_1 = data[1];
  527. mdata->lut_cfg[SDE_ROT_WR].creq_lut_0 = data[2];
  528. mdata->lut_cfg[SDE_ROT_WR].creq_lut_1 = data[3];
  529. set_bit(SDE_QOS_LUT, mdata->sde_qos_map);
  530. } else {
  531. SDEROT_DBG("qos lut setting not found\n");
  532. }
  533. }
  534. len = sde_mdp_parse_dt_prop_len(pdev, "qcom,mdss-rot-danger-lut");
  535. if (len == SDE_ROT_OP_MAX) {
  536. rc = sde_mdp_parse_dt_handler(pdev,
  537. "qcom,mdss-rot-danger-lut", data, len);
  538. if (!rc) {
  539. mdata->lut_cfg[SDE_ROT_RD].danger_lut
  540. = data[SDE_ROT_RD];
  541. mdata->lut_cfg[SDE_ROT_WR].danger_lut
  542. = data[SDE_ROT_WR];
  543. set_bit(SDE_QOS_DANGER_LUT, mdata->sde_qos_map);
  544. } else {
  545. SDEROT_DBG("danger lut setting not found\n");
  546. }
  547. }
  548. len = sde_mdp_parse_dt_prop_len(pdev, "qcom,mdss-rot-safe-lut");
  549. if (len == SDE_ROT_OP_MAX) {
  550. rc = sde_mdp_parse_dt_handler(pdev,
  551. "qcom,mdss-rot-safe-lut", data, len);
  552. if (!rc) {
  553. mdata->lut_cfg[SDE_ROT_RD].safe_lut = data[SDE_ROT_RD];
  554. mdata->lut_cfg[SDE_ROT_WR].safe_lut = data[SDE_ROT_WR];
  555. set_bit(SDE_QOS_SAFE_LUT, mdata->sde_qos_map);
  556. } else {
  557. SDEROT_DBG("safe lut setting not found\n");
  558. }
  559. }
  560. }
  561. static void sde_mdp_parse_inline_rot_lut_setting(struct platform_device *pdev,
  562. struct sde_rot_data_type *mdata)
  563. {
  564. int rc;
  565. u32 len, data[4];
  566. len = sde_mdp_parse_dt_prop_len(pdev, "qcom,mdss-inline-rot-qos-lut");
  567. if (len == 4) {
  568. rc = sde_mdp_parse_dt_handler(pdev,
  569. "qcom,mdss-inline-rot-qos-lut", data, len);
  570. if (!rc) {
  571. mdata->inline_lut_cfg[SDE_ROT_RD].creq_lut_0 = data[0];
  572. mdata->inline_lut_cfg[SDE_ROT_RD].creq_lut_1 = data[1];
  573. mdata->inline_lut_cfg[SDE_ROT_WR].creq_lut_0 = data[2];
  574. mdata->inline_lut_cfg[SDE_ROT_WR].creq_lut_1 = data[3];
  575. set_bit(SDE_INLINE_QOS_LUT, mdata->sde_inline_qos_map);
  576. } else {
  577. SDEROT_DBG("inline qos lut setting not found\n");
  578. }
  579. }
  580. len = sde_mdp_parse_dt_prop_len(pdev,
  581. "qcom,mdss-inline-rot-danger-lut");
  582. if (len == SDE_ROT_OP_MAX) {
  583. rc = sde_mdp_parse_dt_handler(pdev,
  584. "qcom,mdss-inline-rot-danger-lut", data, len);
  585. if (!rc) {
  586. mdata->inline_lut_cfg[SDE_ROT_RD].danger_lut
  587. = data[SDE_ROT_RD];
  588. mdata->inline_lut_cfg[SDE_ROT_WR].danger_lut
  589. = data[SDE_ROT_WR];
  590. set_bit(SDE_INLINE_QOS_DANGER_LUT,
  591. mdata->sde_inline_qos_map);
  592. } else {
  593. SDEROT_DBG("inline danger lut setting not found\n");
  594. }
  595. }
  596. len = sde_mdp_parse_dt_prop_len(pdev, "qcom,mdss-inline-rot-safe-lut");
  597. if (len == SDE_ROT_OP_MAX) {
  598. rc = sde_mdp_parse_dt_handler(pdev,
  599. "qcom,mdss-inline-rot-safe-lut", data, len);
  600. if (!rc) {
  601. mdata->inline_lut_cfg[SDE_ROT_RD].safe_lut
  602. = data[SDE_ROT_RD];
  603. mdata->inline_lut_cfg[SDE_ROT_WR].safe_lut
  604. = data[SDE_ROT_WR];
  605. set_bit(SDE_INLINE_QOS_SAFE_LUT,
  606. mdata->sde_inline_qos_map);
  607. } else {
  608. SDEROT_DBG("inline safe lut setting not found\n");
  609. }
  610. }
  611. }
  612. static void sde_mdp_parse_rt_rotator(struct device_node *np)
  613. {
  614. struct sde_rot_data_type *mdata = sde_rot_get_mdata();
  615. struct platform_device *pdev;
  616. struct of_phandle_args phargs;
  617. int rc = 0;
  618. rc = of_parse_phandle_with_args(np,
  619. "qcom,mdss-rot-parent", "#list-cells", 0, &phargs);
  620. if (rc)
  621. return;
  622. if (!phargs.np || !phargs.args_count) {
  623. SDEROT_ERR("invalid args\n");
  624. return;
  625. }
  626. pdev = of_find_device_by_node(phargs.np);
  627. if (pdev) {
  628. mdata->parent_pdev = pdev;
  629. } else {
  630. mdata->parent_pdev = NULL;
  631. SDEROT_ERR("Parent mdp node not available\n");
  632. }
  633. of_node_put(phargs.np);
  634. }
  635. static int sde_mdp_parse_dt_misc(struct platform_device *pdev,
  636. struct sde_rot_data_type *mdata)
  637. {
  638. int rc;
  639. u32 data;
  640. rc = of_property_read_u32(pdev->dev.of_node, "qcom,mdss-rot-block-size",
  641. &data);
  642. mdata->rot_block_size = (!rc ? data : 128);
  643. rc = of_property_read_u32(pdev->dev.of_node,
  644. "qcom,mdss-default-ot-rd-limit", &data);
  645. mdata->default_ot_rd_limit = (!rc ? data : 0);
  646. rc = of_property_read_u32(pdev->dev.of_node,
  647. "qcom,mdss-default-ot-wr-limit", &data);
  648. mdata->default_ot_wr_limit = (!rc ? data : 0);
  649. rc = of_property_read_u32(pdev->dev.of_node,
  650. "qcom,mdss-highest-bank-bit", &(mdata->highest_bank_bit));
  651. if (rc)
  652. SDEROT_DBG(
  653. "Could not read optional property: highest bank bit\n");
  654. sde_mdp_parse_cdp_setting(pdev, mdata);
  655. sde_mdp_parse_vbif_qos(pdev, mdata);
  656. sde_mdp_parse_vbif_xin_id(pdev, mdata);
  657. sde_mdp_parse_vbif_memtype(pdev, mdata);
  658. sde_mdp_parse_rot_lut_setting(pdev, mdata);
  659. sde_mdp_parse_inline_rot_lut_setting(pdev, mdata);
  660. rc = of_property_read_u32(pdev->dev.of_node,
  661. "qcom,mdss-rot-qos-cpu-mask", &data);
  662. mdata->rot_pm_qos_cpu_mask = (!rc ? data : 0);
  663. rc = of_property_read_u32(pdev->dev.of_node,
  664. "qcom,mdss-rot-qos-cpu-dma-latency", &data);
  665. mdata->rot_pm_qos_cpu_dma_latency = (!rc ? data : 0);
  666. mdata->mdp_base = mdata->sde_io.base + SDE_MDP_OFFSET;
  667. return 0;
  668. }
  669. static void sde_mdp_destroy_dt_misc(struct platform_device *pdev,
  670. struct sde_rot_data_type *mdata)
  671. {
  672. kfree(mdata->vbif_memtype);
  673. mdata->vbif_memtype = NULL;
  674. kfree(mdata->vbif_rt_qos);
  675. mdata->vbif_rt_qos = NULL;
  676. kfree(mdata->vbif_nrt_qos);
  677. mdata->vbif_nrt_qos = NULL;
  678. }
  679. #define MDP_REG_BUS_VECTOR_ENTRY(ab_val, ib_val) \
  680. { \
  681. .src = MSM_BUS_MASTER_AMPSS_M0, \
  682. .dst = MSM_BUS_SLAVE_DISPLAY_CFG, \
  683. .ab = (ab_val), \
  684. .ib = (ib_val), \
  685. }
  686. #define BUS_VOTE_19_MHZ 153600000
  687. #define BUS_VOTE_40_MHZ 320000000
  688. #define BUS_VOTE_80_MHZ 640000000
  689. #ifdef CONFIG_QCOM_BUS_SCALING
  690. static struct msm_bus_vectors mdp_reg_bus_vectors[] = {
  691. MDP_REG_BUS_VECTOR_ENTRY(0, 0),
  692. MDP_REG_BUS_VECTOR_ENTRY(0, BUS_VOTE_19_MHZ),
  693. MDP_REG_BUS_VECTOR_ENTRY(0, BUS_VOTE_40_MHZ),
  694. MDP_REG_BUS_VECTOR_ENTRY(0, BUS_VOTE_80_MHZ),
  695. };
  696. static struct msm_bus_paths mdp_reg_bus_usecases[ARRAY_SIZE(
  697. mdp_reg_bus_vectors)];
  698. static struct msm_bus_scale_pdata mdp_reg_bus_scale_table = {
  699. .usecase = mdp_reg_bus_usecases,
  700. .num_usecases = ARRAY_SIZE(mdp_reg_bus_usecases),
  701. .name = "sde_reg",
  702. .active_only = true,
  703. };
  704. static int sde_mdp_bus_scale_register(struct sde_rot_data_type *mdata)
  705. {
  706. struct msm_bus_scale_pdata *reg_bus_pdata;
  707. int i;
  708. if (!mdata->reg_bus_hdl) {
  709. reg_bus_pdata = &mdp_reg_bus_scale_table;
  710. for (i = 0; i < reg_bus_pdata->num_usecases; i++) {
  711. mdp_reg_bus_usecases[i].num_paths = 1;
  712. mdp_reg_bus_usecases[i].vectors =
  713. &mdp_reg_bus_vectors[i];
  714. }
  715. mdata->reg_bus_hdl =
  716. msm_bus_scale_register_client(reg_bus_pdata);
  717. if (!mdata->reg_bus_hdl) {
  718. /* Continue without reg_bus scaling */
  719. SDEROT_WARN("reg_bus_client register failed\n");
  720. } else
  721. SDEROT_DBG("register reg_bus_hdl=%x\n",
  722. mdata->reg_bus_hdl);
  723. }
  724. return 0;
  725. }
  726. #else
  727. static inline int sde_mdp_bus_scale_register(struct sde_rot_data_type *mdata)
  728. {
  729. return 0;
  730. }
  731. #endif
  732. static void sde_mdp_bus_scale_unregister(struct sde_rot_data_type *mdata)
  733. {
  734. SDEROT_DBG("unregister reg_bus_hdl=%x\n", mdata->reg_bus_hdl);
  735. if (mdata->reg_bus_hdl) {
  736. msm_bus_scale_unregister_client(mdata->reg_bus_hdl);
  737. mdata->reg_bus_hdl = 0;
  738. }
  739. }
  740. static struct sde_rot_data_type *sde_rot_res;
  741. struct sde_rot_data_type *sde_rot_get_mdata(void)
  742. {
  743. return sde_rot_res;
  744. }
  745. /*
  746. * sde_rotator_base_init - initialize base rotator data/resource
  747. */
  748. int sde_rotator_base_init(struct sde_rot_data_type **pmdata,
  749. struct platform_device *pdev,
  750. const void *drvdata)
  751. {
  752. int rc;
  753. struct sde_rot_data_type *mdata;
  754. /* if probe deferral happened, return early*/
  755. if (sde_rot_res) {
  756. SDEROT_ERR("Rotator data already initialized, skip init\n");
  757. return 0;
  758. }
  759. mdata = devm_kzalloc(&pdev->dev, sizeof(*mdata), GFP_KERNEL);
  760. if (mdata == NULL)
  761. return -ENOMEM;
  762. mdata->pdev = pdev;
  763. sde_rot_res = mdata;
  764. mutex_init(&mdata->reg_bus_lock);
  765. INIT_LIST_HEAD(&mdata->reg_bus_clist);
  766. rc = sde_rot_ioremap_byname(pdev, &mdata->sde_io, "mdp_phys");
  767. if (rc) {
  768. SDEROT_ERR("unable to map SDE base\n");
  769. goto probe_done;
  770. }
  771. SDEROT_DBG("SDE ROT HW Base addr=0x%x len=0x%x\n",
  772. (int) (unsigned long) mdata->sde_io.base,
  773. mdata->sde_io.len);
  774. rc = sde_rot_ioremap_byname(pdev, &mdata->vbif_nrt_io, "rot_vbif_phys");
  775. if (rc) {
  776. SDEROT_ERR("unable to map SDE ROT VBIF base\n");
  777. goto probe_done;
  778. }
  779. SDEROT_DBG("SDE ROT VBIF HW Base addr=%pK len=0x%x\n",
  780. mdata->vbif_nrt_io.base, mdata->vbif_nrt_io.len);
  781. sde_mdp_parse_rt_rotator(pdev->dev.of_node);
  782. rc = sde_mdp_parse_dt_misc(pdev, mdata);
  783. if (rc) {
  784. SDEROT_ERR("Error in device tree : misc\n");
  785. goto probe_done;
  786. }
  787. rc = sde_mdp_bus_scale_register(mdata);
  788. if (rc) {
  789. SDEROT_ERR("unable to register bus scaling\n");
  790. goto probe_done;
  791. }
  792. rc = sde_smmu_init(&pdev->dev);
  793. if (rc) {
  794. SDEROT_ERR("sde smmu init failed %d\n", rc);
  795. goto probe_done;
  796. }
  797. *pmdata = mdata;
  798. return 0;
  799. probe_done:
  800. return rc;
  801. }
  802. /*
  803. * sde_rotator_base_destroy - clean up base rotator data/resource
  804. */
  805. void sde_rotator_base_destroy(struct sde_rot_data_type *mdata)
  806. {
  807. struct platform_device *pdev;
  808. if (!mdata || !mdata->pdev)
  809. return;
  810. pdev = mdata->pdev;
  811. sde_rot_res = NULL;
  812. sde_mdp_bus_scale_unregister(mdata);
  813. sde_mdp_destroy_dt_misc(pdev, mdata);
  814. sde_rot_iounmap(&mdata->vbif_nrt_io);
  815. sde_rot_iounmap(&mdata->sde_io);
  816. devm_kfree(&pdev->dev, mdata);
  817. }