wcd938x.c 94 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #define WCD938X_DRV_NAME "wcd938x_codec"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VARIANT_ENTRY_SIZE 32
  27. #define WCD938X_VERSION_1_0 1
  28. #define WCD938X_VERSION_ENTRY_SIZE 32
  29. #define EAR_RX_PATH_AUX 1
  30. #define ADC_MODE_VAL_HIFI 0x01
  31. #define ADC_MODE_VAL_LO_HIF 0x02
  32. #define ADC_MODE_VAL_NORMAL 0x03
  33. #define ADC_MODE_VAL_LP 0x05
  34. #define ADC_MODE_VAL_ULP1 0x09
  35. #define ADC_MODE_VAL_ULP2 0x0B
  36. enum {
  37. WCD9380 = 0,
  38. WCD9385 = 5,
  39. };
  40. enum {
  41. CODEC_TX = 0,
  42. CODEC_RX,
  43. };
  44. enum {
  45. WCD_ADC1 = 0,
  46. WCD_ADC2,
  47. WCD_ADC3,
  48. WCD_ADC4,
  49. ALLOW_BUCK_DISABLE,
  50. HPH_COMP_DELAY,
  51. HPH_PA_DELAY,
  52. };
  53. enum {
  54. ADC_MODE_INVALID = 0,
  55. ADC_MODE_HIFI,
  56. ADC_MODE_LO_HIF,
  57. ADC_MODE_NORMAL,
  58. ADC_MODE_LP,
  59. ADC_MODE_ULP1,
  60. ADC_MODE_ULP2,
  61. };
  62. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  63. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  64. static int wcd938x_handle_post_irq(void *data);
  65. static int wcd938x_reset(struct device *dev);
  66. static int wcd938x_reset_low(struct device *dev);
  67. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  68. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  86. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  87. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  88. };
  89. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  90. .name = "wcd938x",
  91. .irqs = wcd938x_irqs,
  92. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  93. .num_regs = 3,
  94. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  95. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  96. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  97. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  98. .use_ack = 1,
  99. .runtime_pm = false,
  100. .handle_post_irq = wcd938x_handle_post_irq,
  101. .irq_drv_data = NULL,
  102. };
  103. static int wcd938x_handle_post_irq(void *data)
  104. {
  105. struct wcd938x_priv *wcd938x = data;
  106. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  107. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  108. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  109. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  110. wcd938x->tx_swr_dev->slave_irq_pending =
  111. ((sts1 || sts2 || sts3) ? true : false);
  112. return IRQ_HANDLED;
  113. }
  114. static int wcd938x_init_reg(struct snd_soc_component *component)
  115. {
  116. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  117. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  118. /* 1 msec delay as per HW requirement */
  119. usleep_range(1000, 1010);
  120. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  121. /* 1 msec delay as per HW requirement */
  122. usleep_range(1000, 1010);
  123. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  124. 0x10, 0x00);
  125. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  126. 0xF0, 0x80);
  127. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  128. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  129. /* 10 msec delay as per HW requirement */
  130. usleep_range(10000, 10010);
  131. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  132. snd_soc_component_update_bits(component,
  133. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  134. 0xF0, 0x00);
  135. snd_soc_component_update_bits(component,
  136. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  137. 0x1F, 0x15);
  138. snd_soc_component_update_bits(component,
  139. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  140. 0x1F, 0x15);
  141. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  142. 0xC0, 0x80);
  143. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  144. 0x02, 0x02);
  145. snd_soc_component_update_bits(component,
  146. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  147. 0xFF, 0x14);
  148. snd_soc_component_update_bits(component,
  149. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  150. 0x1F, 0x08);
  151. snd_soc_component_update_bits(component,
  152. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  153. snd_soc_component_update_bits(component,
  154. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  155. snd_soc_component_update_bits(component,
  156. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  157. snd_soc_component_update_bits(component,
  158. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  159. snd_soc_component_update_bits(component,
  160. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  161. return 0;
  162. }
  163. static int wcd938x_set_port_params(struct snd_soc_component *component,
  164. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  165. u8 *ch_mask, u32 *ch_rate,
  166. u8 *port_type, u8 path)
  167. {
  168. int i, j;
  169. u8 num_ports = 0;
  170. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  171. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  172. switch (path) {
  173. case CODEC_RX:
  174. map = &wcd938x->rx_port_mapping;
  175. num_ports = wcd938x->num_rx_ports;
  176. break;
  177. case CODEC_TX:
  178. map = &wcd938x->tx_port_mapping;
  179. num_ports = wcd938x->num_tx_ports;
  180. break;
  181. default:
  182. dev_err(component->dev, "%s Invalid path selected %u\n",
  183. __func__, path);
  184. return -EINVAL;
  185. }
  186. for (i = 0; i <= num_ports; i++) {
  187. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  188. if ((*map)[i][j].slave_port_type == slv_prt_type)
  189. goto found;
  190. }
  191. }
  192. found:
  193. if (i > num_ports || j == MAX_CH_PER_PORT) {
  194. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  195. __func__, slv_prt_type);
  196. return -EINVAL;
  197. }
  198. *port_id = i;
  199. *num_ch = (*map)[i][j].num_ch;
  200. *ch_mask = (*map)[i][j].ch_mask;
  201. *ch_rate = (*map)[i][j].ch_rate;
  202. *port_type = (*map)[i][j].master_port_type;
  203. return 0;
  204. }
  205. static int wcd938x_parse_port_mapping(struct device *dev,
  206. char *prop, u8 path)
  207. {
  208. u32 *dt_array, map_size, map_length;
  209. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  210. u32 slave_port_type, master_port_type;
  211. u32 i, ch_iter = 0;
  212. int ret = 0;
  213. u8 *num_ports = NULL;
  214. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  215. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  216. switch (path) {
  217. case CODEC_RX:
  218. map = &wcd938x->rx_port_mapping;
  219. num_ports = &wcd938x->num_rx_ports;
  220. break;
  221. case CODEC_TX:
  222. map = &wcd938x->tx_port_mapping;
  223. num_ports = &wcd938x->num_tx_ports;
  224. break;
  225. default:
  226. dev_err(dev, "%s Invalid path selected %u\n",
  227. __func__, path);
  228. return -EINVAL;
  229. }
  230. if (!of_find_property(dev->of_node, prop,
  231. &map_size)) {
  232. dev_err(dev, "missing port mapping prop %s\n", prop);
  233. ret = -EINVAL;
  234. goto err_port_map;
  235. }
  236. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  237. dt_array = kzalloc(map_size, GFP_KERNEL);
  238. if (!dt_array) {
  239. ret = -ENOMEM;
  240. goto err_alloc;
  241. }
  242. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  243. NUM_SWRS_DT_PARAMS * map_length);
  244. if (ret) {
  245. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  246. __func__, prop);
  247. goto err_pdata_fail;
  248. }
  249. for (i = 0; i < map_length; i++) {
  250. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  251. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  252. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  253. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  254. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  255. if (port_num != old_port_num)
  256. ch_iter = 0;
  257. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  258. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  259. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  260. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  261. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  262. old_port_num = port_num;
  263. }
  264. *num_ports = port_num;
  265. kfree(dt_array);
  266. return 0;
  267. err_pdata_fail:
  268. kfree(dt_array);
  269. err_alloc:
  270. err_port_map:
  271. return ret;
  272. }
  273. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  274. u8 slv_port_type, u8 enable)
  275. {
  276. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  277. u8 port_id, num_ch, ch_mask, port_type;
  278. u32 ch_rate;
  279. u8 num_port = 1;
  280. int ret = 0;
  281. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  282. &num_ch, &ch_mask, &ch_rate,
  283. &port_type, CODEC_TX);
  284. if (ret)
  285. return ret;
  286. if (enable)
  287. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  288. num_port, &ch_mask, &ch_rate,
  289. &num_ch, &port_type);
  290. else
  291. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  292. num_port, &ch_mask, &port_type);
  293. return ret;
  294. }
  295. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  296. u8 slv_port_type, u8 enable)
  297. {
  298. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  299. u8 port_id, num_ch, ch_mask, port_type;
  300. u32 ch_rate;
  301. u8 num_port = 1;
  302. int ret = 0;
  303. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  304. &num_ch, &ch_mask, &ch_rate,
  305. &port_type, CODEC_RX);
  306. if (ret)
  307. return ret;
  308. if (enable)
  309. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  310. num_port, &ch_mask, &ch_rate,
  311. &num_ch, &port_type);
  312. else
  313. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  314. num_port, &ch_mask, &port_type);
  315. return ret;
  316. }
  317. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  318. {
  319. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  320. if (wcd938x->rx_clk_cnt == 0) {
  321. snd_soc_component_update_bits(component,
  322. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  323. snd_soc_component_update_bits(component,
  324. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  325. snd_soc_component_update_bits(component,
  326. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  327. snd_soc_component_update_bits(component,
  328. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  329. snd_soc_component_update_bits(component,
  330. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  331. snd_soc_component_update_bits(component,
  332. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  333. snd_soc_component_update_bits(component,
  334. WCD938X_AUX_AUXPA, 0x10, 0x10);
  335. }
  336. wcd938x->rx_clk_cnt++;
  337. return 0;
  338. }
  339. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  340. {
  341. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  342. wcd938x->rx_clk_cnt--;
  343. if (wcd938x->rx_clk_cnt == 0) {
  344. snd_soc_component_update_bits(component,
  345. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  346. snd_soc_component_update_bits(component,
  347. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  348. snd_soc_component_update_bits(component,
  349. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  350. snd_soc_component_update_bits(component,
  351. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  352. snd_soc_component_update_bits(component,
  353. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  354. }
  355. return 0;
  356. }
  357. /*
  358. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  359. * @component: handle to snd_soc_component *
  360. *
  361. * return wcd938x_mbhc handle or error code in case of failure
  362. */
  363. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  364. {
  365. struct wcd938x_priv *wcd938x;
  366. if (!component) {
  367. pr_err("%s: Invalid params, NULL component\n", __func__);
  368. return NULL;
  369. }
  370. wcd938x = snd_soc_component_get_drvdata(component);
  371. if (!wcd938x) {
  372. pr_err("%s: wcd938x is NULL\n", __func__);
  373. return NULL;
  374. }
  375. return wcd938x->mbhc;
  376. }
  377. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  378. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  379. struct snd_kcontrol *kcontrol,
  380. int event)
  381. {
  382. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  383. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  384. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  385. w->name, event);
  386. switch (event) {
  387. case SND_SOC_DAPM_PRE_PMU:
  388. wcd938x_rx_clk_enable(component);
  389. snd_soc_component_update_bits(component,
  390. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  391. snd_soc_component_update_bits(component,
  392. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  393. snd_soc_component_update_bits(component,
  394. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  395. break;
  396. case SND_SOC_DAPM_POST_PMU:
  397. snd_soc_component_update_bits(component,
  398. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  399. if (wcd938x->comp1_enable) {
  400. snd_soc_component_update_bits(component,
  401. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  402. /* 5msec compander delay as per HW requirement */
  403. if (!wcd938x->comp2_enable ||
  404. (snd_soc_component_read32(component,
  405. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  406. usleep_range(5000, 5010);
  407. snd_soc_component_update_bits(component,
  408. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  409. } else {
  410. snd_soc_component_update_bits(component,
  411. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  412. 0x02, 0x00);
  413. snd_soc_component_update_bits(component,
  414. WCD938X_HPH_L_EN, 0x20, 0x20);
  415. }
  416. break;
  417. case SND_SOC_DAPM_POST_PMD:
  418. snd_soc_component_update_bits(component,
  419. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  420. 0x0F, 0x01);
  421. break;
  422. }
  423. return 0;
  424. }
  425. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  426. struct snd_kcontrol *kcontrol,
  427. int event)
  428. {
  429. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  430. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  431. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  432. w->name, event);
  433. switch (event) {
  434. case SND_SOC_DAPM_PRE_PMU:
  435. wcd938x_rx_clk_enable(component);
  436. snd_soc_component_update_bits(component,
  437. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  438. snd_soc_component_update_bits(component,
  439. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  440. snd_soc_component_update_bits(component,
  441. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  442. break;
  443. case SND_SOC_DAPM_POST_PMU:
  444. snd_soc_component_update_bits(component,
  445. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  446. if (wcd938x->comp2_enable) {
  447. snd_soc_component_update_bits(component,
  448. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  449. /* 5msec compander delay as per HW requirement */
  450. if (!wcd938x->comp1_enable ||
  451. (snd_soc_component_read32(component,
  452. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  453. usleep_range(5000, 5010);
  454. snd_soc_component_update_bits(component,
  455. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  456. } else {
  457. snd_soc_component_update_bits(component,
  458. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  459. 0x01, 0x00);
  460. snd_soc_component_update_bits(component,
  461. WCD938X_HPH_R_EN, 0x20, 0x20);
  462. }
  463. break;
  464. case SND_SOC_DAPM_POST_PMD:
  465. snd_soc_component_update_bits(component,
  466. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  467. 0x0F, 0x01);
  468. break;
  469. }
  470. return 0;
  471. }
  472. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  473. struct snd_kcontrol *kcontrol,
  474. int event)
  475. {
  476. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  477. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  478. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  479. w->name, event);
  480. switch (event) {
  481. case SND_SOC_DAPM_PRE_PMU:
  482. wcd938x_rx_clk_enable(component);
  483. snd_soc_component_update_bits(component,
  484. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  485. snd_soc_component_update_bits(component,
  486. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  487. snd_soc_component_update_bits(component,
  488. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  489. /* 5 msec delay as per HW requirement */
  490. usleep_range(5000, 5010);
  491. if (wcd938x->flyback_cur_det_disable == 0)
  492. snd_soc_component_update_bits(component,
  493. WCD938X_FLYBACK_EN,
  494. 0x04, 0x00);
  495. wcd938x->flyback_cur_det_disable++;
  496. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  497. WCD_CLSH_EVENT_PRE_DAC,
  498. WCD_CLSH_STATE_EAR,
  499. wcd938x->hph_mode);
  500. break;
  501. case SND_SOC_DAPM_POST_PMD:
  502. break;
  503. };
  504. return 0;
  505. }
  506. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  507. struct snd_kcontrol *kcontrol,
  508. int event)
  509. {
  510. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  511. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  512. int ret = 0;
  513. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  514. w->name, event);
  515. switch (event) {
  516. case SND_SOC_DAPM_PRE_PMU:
  517. wcd938x_rx_clk_enable(component);
  518. snd_soc_component_update_bits(component,
  519. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  520. snd_soc_component_update_bits(component,
  521. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  522. snd_soc_component_update_bits(component,
  523. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  524. if (wcd938x->flyback_cur_det_disable == 0)
  525. snd_soc_component_update_bits(component,
  526. WCD938X_FLYBACK_EN,
  527. 0x04, 0x00);
  528. wcd938x->flyback_cur_det_disable++;
  529. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  530. WCD_CLSH_EVENT_PRE_DAC,
  531. WCD_CLSH_STATE_AUX,
  532. wcd938x->hph_mode);
  533. break;
  534. case SND_SOC_DAPM_POST_PMD:
  535. snd_soc_component_update_bits(component,
  536. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  537. break;
  538. };
  539. return ret;
  540. }
  541. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  542. struct snd_kcontrol *kcontrol,
  543. int event)
  544. {
  545. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  546. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  547. int ret = 0;
  548. int hph_mode = wcd938x->hph_mode;
  549. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  550. w->name, event);
  551. switch (event) {
  552. case SND_SOC_DAPM_PRE_PMU:
  553. if (wcd938x->update_wcd_event)
  554. wcd938x->update_wcd_event(wcd938x->handle,
  555. WCD_BOLERO_EVT_RX_MUTE,
  556. (WCD_RX2 << 0x10 | 0x1));
  557. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  558. wcd938x->rx_swr_dev->dev_num,
  559. true);
  560. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  561. WCD_CLSH_EVENT_PRE_DAC,
  562. WCD_CLSH_STATE_HPHR,
  563. hph_mode);
  564. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  565. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  566. 0x10, 0x10);
  567. wcd_clsh_set_hph_mode(component, hph_mode);
  568. /* 100 usec delay as per HW requirement */
  569. usleep_range(100, 110);
  570. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  571. snd_soc_component_update_bits(component,
  572. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  573. break;
  574. case SND_SOC_DAPM_POST_PMU:
  575. /*
  576. * 7ms sleep is required if compander is enabled as per
  577. * HW requirement. If compander is disabled, then
  578. * 20ms delay is required.
  579. */
  580. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  581. if (!wcd938x->comp2_enable)
  582. usleep_range(20000, 20100);
  583. else
  584. usleep_range(7000, 7100);
  585. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  586. }
  587. snd_soc_component_update_bits(component,
  588. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  589. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  590. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  591. snd_soc_component_update_bits(component,
  592. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  593. if (wcd938x->update_wcd_event)
  594. wcd938x->update_wcd_event(wcd938x->handle,
  595. WCD_BOLERO_EVT_RX_MUTE,
  596. (WCD_RX2 << 0x10));
  597. wcd_enable_irq(&wcd938x->irq_info,
  598. WCD938X_IRQ_HPHR_PDM_WD_INT);
  599. break;
  600. case SND_SOC_DAPM_PRE_PMD:
  601. wcd_disable_irq(&wcd938x->irq_info,
  602. WCD938X_IRQ_HPHR_PDM_WD_INT);
  603. if (wcd938x->update_wcd_event)
  604. wcd938x->update_wcd_event(wcd938x->handle,
  605. WCD_BOLERO_EVT_RX_MUTE,
  606. (WCD_RX2 << 0x10 | 0x1));
  607. if (wcd938x->update_wcd_event)
  608. wcd938x->update_wcd_event(wcd938x->handle,
  609. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  610. (WCD_RX2 << 0x10));
  611. /* 7 msec delay as per HW requirement */
  612. usleep_range(7000, 7100);
  613. if (wcd938x->update_wcd_event)
  614. wcd938x->update_wcd_event(wcd938x->handle,
  615. WCD_BOLERO_EVT_RX_MUTE,
  616. (WCD_RX2 << 0x10 | 0x0));
  617. /* 20 msec delay as per HW requirement */
  618. usleep_range(21000, 21100);
  619. if (wcd938x->update_wcd_event)
  620. wcd938x->update_wcd_event(wcd938x->handle,
  621. WCD_BOLERO_EVT_RX_MUTE,
  622. (WCD_RX2 << 0x10 | 0x1));
  623. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  624. 0x40, 0x00);
  625. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  626. WCD_EVENT_PRE_HPHR_PA_OFF,
  627. &wcd938x->mbhc->wcd_mbhc);
  628. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  629. break;
  630. case SND_SOC_DAPM_POST_PMD:
  631. /*
  632. * 7ms sleep is required if compander is enabled as per
  633. * HW requirement. If compander is disabled, then
  634. * 20ms delay is required.
  635. */
  636. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  637. if (!wcd938x->comp2_enable)
  638. usleep_range(20000, 20100);
  639. else
  640. usleep_range(7000, 7100);
  641. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  642. }
  643. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  644. WCD_EVENT_POST_HPHR_PA_OFF,
  645. &wcd938x->mbhc->wcd_mbhc);
  646. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  647. 0x10, 0x00);
  648. /* 20 msec delay as per HW requirement */
  649. usleep_range(20000, 20100);
  650. snd_soc_component_update_bits(component,
  651. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  652. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  653. WCD_CLSH_EVENT_POST_PA,
  654. WCD_CLSH_STATE_HPHR,
  655. hph_mode);
  656. break;
  657. };
  658. return ret;
  659. }
  660. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  661. struct snd_kcontrol *kcontrol,
  662. int event)
  663. {
  664. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  665. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  666. int ret = 0;
  667. int hph_mode = wcd938x->hph_mode;
  668. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  669. w->name, event);
  670. switch (event) {
  671. case SND_SOC_DAPM_PRE_PMU:
  672. if (wcd938x->update_wcd_event)
  673. wcd938x->update_wcd_event(wcd938x->handle,
  674. WCD_BOLERO_EVT_RX_MUTE,
  675. (WCD_RX1 << 0x10 | 0x01));
  676. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  677. wcd938x->rx_swr_dev->dev_num,
  678. true);
  679. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  680. WCD_CLSH_EVENT_PRE_DAC,
  681. WCD_CLSH_STATE_HPHL,
  682. hph_mode);
  683. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  684. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  685. 0x20, 0x20);
  686. wcd_clsh_set_hph_mode(component, hph_mode);
  687. /* 100 usec delay as per HW requirement */
  688. usleep_range(100, 110);
  689. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  690. snd_soc_component_update_bits(component,
  691. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  692. break;
  693. case SND_SOC_DAPM_POST_PMU:
  694. /*
  695. * 7ms sleep is required if compander is enabled as per
  696. * HW requirement. If compander is disabled, then
  697. * 20ms delay is required.
  698. */
  699. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  700. if (!wcd938x->comp1_enable)
  701. usleep_range(20000, 20100);
  702. else
  703. usleep_range(7000, 7100);
  704. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  705. }
  706. snd_soc_component_update_bits(component,
  707. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  708. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  709. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  710. snd_soc_component_update_bits(component,
  711. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  712. if (wcd938x->update_wcd_event)
  713. wcd938x->update_wcd_event(wcd938x->handle,
  714. WCD_BOLERO_EVT_RX_MUTE,
  715. (WCD_RX1 << 0x10));
  716. wcd_enable_irq(&wcd938x->irq_info,
  717. WCD938X_IRQ_HPHL_PDM_WD_INT);
  718. break;
  719. case SND_SOC_DAPM_PRE_PMD:
  720. wcd_disable_irq(&wcd938x->irq_info,
  721. WCD938X_IRQ_HPHL_PDM_WD_INT);
  722. if (wcd938x->update_wcd_event)
  723. wcd938x->update_wcd_event(wcd938x->handle,
  724. WCD_BOLERO_EVT_RX_MUTE,
  725. (WCD_RX1 << 0x10 | 0x1));
  726. if (wcd938x->update_wcd_event)
  727. wcd938x->update_wcd_event(wcd938x->handle,
  728. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  729. (WCD_RX1 << 0x10));
  730. /* 7 msec delay as per HW requirement */
  731. usleep_range(7000, 7100);
  732. if (wcd938x->update_wcd_event)
  733. wcd938x->update_wcd_event(wcd938x->handle,
  734. WCD_BOLERO_EVT_RX_MUTE,
  735. (WCD_RX1 << 0x10 | 0x0));
  736. /* 20 msec delay as per HW requirement */
  737. usleep_range(21000, 21100);
  738. if (wcd938x->update_wcd_event)
  739. wcd938x->update_wcd_event(wcd938x->handle,
  740. WCD_BOLERO_EVT_RX_MUTE,
  741. (WCD_RX1 << 0x10 | 0x1));
  742. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  743. 0x80, 0x00);
  744. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  745. WCD_EVENT_PRE_HPHL_PA_OFF,
  746. &wcd938x->mbhc->wcd_mbhc);
  747. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  748. break;
  749. case SND_SOC_DAPM_POST_PMD:
  750. /*
  751. * 7ms sleep is required if compander is enabled as per
  752. * HW requirement. If compander is disabled, then
  753. * 20ms delay is required.
  754. */
  755. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  756. if (!wcd938x->comp1_enable)
  757. usleep_range(21000, 21100);
  758. else
  759. usleep_range(7000, 7100);
  760. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  761. }
  762. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  763. WCD_EVENT_POST_HPHL_PA_OFF,
  764. &wcd938x->mbhc->wcd_mbhc);
  765. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  766. 0x20, 0x00);
  767. /* 20 msec delay as per HW requirement */
  768. usleep_range(21000, 21100);
  769. snd_soc_component_update_bits(component,
  770. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  771. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  772. WCD_CLSH_EVENT_POST_PA,
  773. WCD_CLSH_STATE_HPHL,
  774. hph_mode);
  775. break;
  776. };
  777. return ret;
  778. }
  779. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  780. struct snd_kcontrol *kcontrol,
  781. int event)
  782. {
  783. struct snd_soc_component *component =
  784. snd_soc_dapm_to_component(w->dapm);
  785. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  786. int hph_mode = wcd938x->hph_mode;
  787. int ret = 0;
  788. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  789. w->name, event);
  790. switch (event) {
  791. case SND_SOC_DAPM_PRE_PMU:
  792. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  793. wcd938x->rx_swr_dev->dev_num,
  794. true);
  795. snd_soc_component_update_bits(component,
  796. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  797. break;
  798. case SND_SOC_DAPM_POST_PMU:
  799. /* 1 msec delay as per HW requirement */
  800. usleep_range(1000, 1010);
  801. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  802. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  803. snd_soc_component_update_bits(component,
  804. WCD938X_ANA_RX_SUPPLIES,
  805. 0x02, 0x02);
  806. if (wcd938x->update_wcd_event)
  807. wcd938x->update_wcd_event(wcd938x->handle,
  808. WCD_BOLERO_EVT_RX_MUTE,
  809. (WCD_RX3 << 0x10));
  810. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  811. break;
  812. case SND_SOC_DAPM_PRE_PMD:
  813. wcd_disable_irq(&wcd938x->irq_info,
  814. WCD938X_IRQ_AUX_PDM_WD_INT);
  815. if (wcd938x->update_wcd_event)
  816. wcd938x->update_wcd_event(wcd938x->handle,
  817. WCD_BOLERO_EVT_RX_MUTE,
  818. (WCD_RX3 << 0x10 | 0x1));
  819. break;
  820. case SND_SOC_DAPM_POST_PMD:
  821. /* 1 msec delay as per HW requirement */
  822. usleep_range(1000, 1010);
  823. snd_soc_component_update_bits(component,
  824. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  825. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  826. WCD_CLSH_EVENT_POST_PA,
  827. WCD_CLSH_STATE_AUX,
  828. hph_mode);
  829. wcd938x->flyback_cur_det_disable--;
  830. if (wcd938x->flyback_cur_det_disable == 0)
  831. snd_soc_component_update_bits(component,
  832. WCD938X_FLYBACK_EN,
  833. 0x04, 0x04);
  834. break;
  835. };
  836. return ret;
  837. }
  838. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  839. struct snd_kcontrol *kcontrol,
  840. int event)
  841. {
  842. struct snd_soc_component *component =
  843. snd_soc_dapm_to_component(w->dapm);
  844. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  845. int hph_mode = wcd938x->hph_mode;
  846. int ret = 0;
  847. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  848. w->name, event);
  849. switch (event) {
  850. case SND_SOC_DAPM_PRE_PMU:
  851. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  852. wcd938x->rx_swr_dev->dev_num,
  853. true);
  854. /*
  855. * Enable watchdog interrupt for HPHL or AUX
  856. * depending on mux value
  857. */
  858. wcd938x->ear_rx_path =
  859. snd_soc_component_read32(
  860. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  861. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  862. snd_soc_component_update_bits(component,
  863. WCD938X_DIGITAL_PDM_WD_CTL2,
  864. 0x05, 0x05);
  865. else
  866. snd_soc_component_update_bits(component,
  867. WCD938X_DIGITAL_PDM_WD_CTL0,
  868. 0x17, 0x13);
  869. break;
  870. case SND_SOC_DAPM_POST_PMU:
  871. /* 6 msec delay as per HW requirement */
  872. usleep_range(6000, 6010);
  873. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  874. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  875. snd_soc_component_update_bits(component,
  876. WCD938X_ANA_RX_SUPPLIES,
  877. 0x02, 0x02);
  878. if (wcd938x->update_wcd_event)
  879. wcd938x->update_wcd_event(wcd938x->handle,
  880. WCD_BOLERO_EVT_RX_MUTE,
  881. (WCD_RX1 << 0x10));
  882. break;
  883. case SND_SOC_DAPM_PRE_PMD:
  884. if (wcd938x->update_wcd_event)
  885. wcd938x->update_wcd_event(wcd938x->handle,
  886. WCD_BOLERO_EVT_RX_MUTE,
  887. (WCD_RX1 << 0x10 | 0x1));
  888. break;
  889. case SND_SOC_DAPM_POST_PMD:
  890. /* 7 msec delay as per HW requirement */
  891. usleep_range(7000, 7010);
  892. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  893. snd_soc_component_update_bits(component,
  894. WCD938X_DIGITAL_PDM_WD_CTL2,
  895. 0x05, 0x00);
  896. else
  897. snd_soc_component_update_bits(component,
  898. WCD938X_DIGITAL_PDM_WD_CTL0,
  899. 0x17, 0x00);
  900. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  901. WCD_CLSH_EVENT_POST_PA,
  902. WCD_CLSH_STATE_EAR,
  903. hph_mode);
  904. wcd938x->flyback_cur_det_disable--;
  905. if (wcd938x->flyback_cur_det_disable == 0)
  906. snd_soc_component_update_bits(component,
  907. WCD938X_FLYBACK_EN,
  908. 0x04, 0x04);
  909. break;
  910. };
  911. return ret;
  912. }
  913. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  914. struct snd_kcontrol *kcontrol,
  915. int event)
  916. {
  917. struct snd_soc_component *component =
  918. snd_soc_dapm_to_component(w->dapm);
  919. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  920. int mode = wcd938x->hph_mode;
  921. int ret = 0;
  922. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  923. w->name, event);
  924. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  925. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  926. wcd938x_rx_connect_port(component, CLSH,
  927. SND_SOC_DAPM_EVENT_ON(event));
  928. }
  929. if (SND_SOC_DAPM_EVENT_OFF(event))
  930. ret = swr_slvdev_datapath_control(
  931. wcd938x->rx_swr_dev,
  932. wcd938x->rx_swr_dev->dev_num,
  933. false);
  934. return ret;
  935. }
  936. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  937. struct snd_kcontrol *kcontrol,
  938. int event)
  939. {
  940. struct snd_soc_component *component =
  941. snd_soc_dapm_to_component(w->dapm);
  942. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  943. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  944. w->name, event);
  945. switch (event) {
  946. case SND_SOC_DAPM_PRE_PMU:
  947. wcd938x_rx_connect_port(component, HPH_L, true);
  948. if (wcd938x->comp1_enable)
  949. wcd938x_rx_connect_port(component, COMP_L, true);
  950. break;
  951. case SND_SOC_DAPM_POST_PMD:
  952. wcd938x_rx_connect_port(component, HPH_L, false);
  953. if (wcd938x->comp1_enable)
  954. wcd938x_rx_connect_port(component, COMP_L, false);
  955. wcd938x_rx_clk_disable(component);
  956. snd_soc_component_update_bits(component,
  957. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  958. 0x01, 0x00);
  959. break;
  960. };
  961. return 0;
  962. }
  963. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  964. struct snd_kcontrol *kcontrol, int event)
  965. {
  966. struct snd_soc_component *component =
  967. snd_soc_dapm_to_component(w->dapm);
  968. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  969. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  970. w->name, event);
  971. switch (event) {
  972. case SND_SOC_DAPM_PRE_PMU:
  973. wcd938x_rx_connect_port(component, HPH_R, true);
  974. if (wcd938x->comp2_enable)
  975. wcd938x_rx_connect_port(component, COMP_R, true);
  976. break;
  977. case SND_SOC_DAPM_POST_PMD:
  978. wcd938x_rx_connect_port(component, HPH_R, false);
  979. if (wcd938x->comp2_enable)
  980. wcd938x_rx_connect_port(component, COMP_R, false);
  981. wcd938x_rx_clk_disable(component);
  982. snd_soc_component_update_bits(component,
  983. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  984. 0x02, 0x00);
  985. break;
  986. };
  987. return 0;
  988. }
  989. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  990. struct snd_kcontrol *kcontrol,
  991. int event)
  992. {
  993. struct snd_soc_component *component =
  994. snd_soc_dapm_to_component(w->dapm);
  995. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  996. w->name, event);
  997. switch (event) {
  998. case SND_SOC_DAPM_PRE_PMU:
  999. wcd938x_rx_connect_port(component, LO, true);
  1000. break;
  1001. case SND_SOC_DAPM_POST_PMD:
  1002. wcd938x_rx_connect_port(component, LO, false);
  1003. /* 6 msec delay as per HW requirement */
  1004. usleep_range(6000, 6010);
  1005. wcd938x_rx_clk_disable(component);
  1006. snd_soc_component_update_bits(component,
  1007. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1008. break;
  1009. }
  1010. return 0;
  1011. }
  1012. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1013. struct snd_kcontrol *kcontrol,
  1014. int event)
  1015. {
  1016. struct snd_soc_component *component =
  1017. snd_soc_dapm_to_component(w->dapm);
  1018. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1019. u16 dmic_clk_reg, dmic_clk_en_reg;
  1020. s32 *dmic_clk_cnt;
  1021. u8 dmic_ctl_shift = 0;
  1022. u8 dmic_clk_shift = 0;
  1023. u8 dmic_clk_mask = 0;
  1024. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1025. w->name, event);
  1026. switch (w->shift) {
  1027. case 0:
  1028. case 1:
  1029. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1030. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1031. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1032. dmic_clk_mask = 0x0F;
  1033. dmic_clk_shift = 0x00;
  1034. dmic_ctl_shift = 0x00;
  1035. break;
  1036. case 2:
  1037. case 3:
  1038. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1039. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1040. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1041. dmic_clk_mask = 0xF0;
  1042. dmic_clk_shift = 0x04;
  1043. dmic_ctl_shift = 0x01;
  1044. break;
  1045. case 4:
  1046. case 5:
  1047. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1048. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1049. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1050. dmic_clk_mask = 0x0F;
  1051. dmic_clk_shift = 0x00;
  1052. dmic_ctl_shift = 0x02;
  1053. break;
  1054. case 6:
  1055. case 7:
  1056. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1057. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1058. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1059. dmic_clk_mask = 0xF0;
  1060. dmic_clk_shift = 0x04;
  1061. dmic_ctl_shift = 0x03;
  1062. break;
  1063. default:
  1064. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1065. __func__);
  1066. return -EINVAL;
  1067. };
  1068. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1069. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1070. switch (event) {
  1071. case SND_SOC_DAPM_PRE_PMU:
  1072. snd_soc_component_update_bits(component,
  1073. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1074. (0x01 << dmic_ctl_shift), 0x00);
  1075. /* 250us sleep as per HW requirement */
  1076. usleep_range(250, 260);
  1077. /* Setting DMIC clock rate to 2.4MHz */
  1078. snd_soc_component_update_bits(component,
  1079. dmic_clk_reg, dmic_clk_mask,
  1080. (0x03 << dmic_clk_shift));
  1081. snd_soc_component_update_bits(component,
  1082. dmic_clk_en_reg, 0x08, 0x08);
  1083. /* enable clock scaling */
  1084. snd_soc_component_update_bits(component,
  1085. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1086. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1087. break;
  1088. case SND_SOC_DAPM_POST_PMD:
  1089. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1090. snd_soc_component_update_bits(component,
  1091. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1092. (0x01 << dmic_ctl_shift),
  1093. (0x01 << dmic_ctl_shift));
  1094. snd_soc_component_update_bits(component,
  1095. dmic_clk_en_reg, 0x08, 0x00);
  1096. break;
  1097. };
  1098. return 0;
  1099. }
  1100. /*
  1101. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1102. * @micb_mv: micbias in mv
  1103. *
  1104. * return register value converted
  1105. */
  1106. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1107. {
  1108. /* min micbias voltage is 1V and maximum is 2.85V */
  1109. if (micb_mv < 1000 || micb_mv > 2850) {
  1110. pr_err("%s: unsupported micbias voltage\n", __func__);
  1111. return -EINVAL;
  1112. }
  1113. return (micb_mv - 1000) / 50;
  1114. }
  1115. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1116. /*
  1117. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1118. * @component: handle to snd_soc_component *
  1119. * @req_volt: micbias voltage to be set
  1120. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1121. *
  1122. * return 0 if adjustment is success or error code in case of failure
  1123. */
  1124. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1125. int req_volt, int micb_num)
  1126. {
  1127. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1128. int cur_vout_ctl, req_vout_ctl;
  1129. int micb_reg, micb_val, micb_en;
  1130. int ret = 0;
  1131. switch (micb_num) {
  1132. case MIC_BIAS_1:
  1133. micb_reg = WCD938X_ANA_MICB1;
  1134. break;
  1135. case MIC_BIAS_2:
  1136. micb_reg = WCD938X_ANA_MICB2;
  1137. break;
  1138. case MIC_BIAS_3:
  1139. micb_reg = WCD938X_ANA_MICB3;
  1140. break;
  1141. case MIC_BIAS_4:
  1142. micb_reg = WCD938X_ANA_MICB4;
  1143. break;
  1144. default:
  1145. return -EINVAL;
  1146. }
  1147. mutex_lock(&wcd938x->micb_lock);
  1148. /*
  1149. * If requested micbias voltage is same as current micbias
  1150. * voltage, then just return. Otherwise, adjust voltage as
  1151. * per requested value. If micbias is already enabled, then
  1152. * to avoid slow micbias ramp-up or down enable pull-up
  1153. * momentarily, change the micbias value and then re-enable
  1154. * micbias.
  1155. */
  1156. micb_val = snd_soc_component_read32(component, micb_reg);
  1157. micb_en = (micb_val & 0xC0) >> 6;
  1158. cur_vout_ctl = micb_val & 0x3F;
  1159. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1160. if (req_vout_ctl < 0) {
  1161. ret = -EINVAL;
  1162. goto exit;
  1163. }
  1164. if (cur_vout_ctl == req_vout_ctl) {
  1165. ret = 0;
  1166. goto exit;
  1167. }
  1168. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1169. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1170. req_volt, micb_en);
  1171. if (micb_en == 0x1)
  1172. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1173. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1174. if (micb_en == 0x1) {
  1175. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1176. /*
  1177. * Add 2ms delay as per HW requirement after enabling
  1178. * micbias
  1179. */
  1180. usleep_range(2000, 2100);
  1181. }
  1182. exit:
  1183. mutex_unlock(&wcd938x->micb_lock);
  1184. return ret;
  1185. }
  1186. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1187. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1188. struct snd_kcontrol *kcontrol,
  1189. int event)
  1190. {
  1191. struct snd_soc_component *component =
  1192. snd_soc_dapm_to_component(w->dapm);
  1193. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1194. int ret = 0;
  1195. switch (event) {
  1196. case SND_SOC_DAPM_PRE_PMU:
  1197. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1198. wcd938x->tx_swr_dev->dev_num,
  1199. true);
  1200. break;
  1201. case SND_SOC_DAPM_POST_PMD:
  1202. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1203. wcd938x->tx_swr_dev->dev_num,
  1204. false);
  1205. break;
  1206. };
  1207. return ret;
  1208. }
  1209. static int wcd938x_get_adc_mode(int val)
  1210. {
  1211. int ret = 0;
  1212. switch (val) {
  1213. case ADC_MODE_INVALID:
  1214. ret = ADC_MODE_VAL_NORMAL;
  1215. break;
  1216. case ADC_MODE_HIFI:
  1217. ret = ADC_MODE_VAL_HIFI;
  1218. break;
  1219. case ADC_MODE_LO_HIF:
  1220. ret = ADC_MODE_VAL_LO_HIF;
  1221. break;
  1222. case ADC_MODE_NORMAL:
  1223. ret = ADC_MODE_VAL_NORMAL;
  1224. break;
  1225. case ADC_MODE_LP:
  1226. ret = ADC_MODE_VAL_LP;
  1227. break;
  1228. case ADC_MODE_ULP1:
  1229. ret = ADC_MODE_VAL_ULP1;
  1230. break;
  1231. case ADC_MODE_ULP2:
  1232. ret = ADC_MODE_VAL_ULP2;
  1233. break;
  1234. default:
  1235. ret = -EINVAL;
  1236. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1237. break;
  1238. }
  1239. return ret;
  1240. }
  1241. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1242. struct snd_kcontrol *kcontrol,
  1243. int event){
  1244. int mode;
  1245. struct snd_soc_component *component =
  1246. snd_soc_dapm_to_component(w->dapm);
  1247. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1248. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1249. w->name, event);
  1250. switch (event) {
  1251. case SND_SOC_DAPM_PRE_PMU:
  1252. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1253. if (mode < 0) {
  1254. dev_info(component->dev,
  1255. "%s: invalid mode, setting to normal mode\n",
  1256. __func__);
  1257. mode = ADC_MODE_VAL_NORMAL;
  1258. }
  1259. snd_soc_component_update_bits(component,
  1260. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1261. snd_soc_component_update_bits(component,
  1262. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1263. snd_soc_component_update_bits(component,
  1264. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1265. switch (w->shift) {
  1266. case 0:
  1267. snd_soc_component_update_bits(component,
  1268. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1269. mode);
  1270. break;
  1271. case 1:
  1272. snd_soc_component_update_bits(component,
  1273. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1274. mode << 4);
  1275. break;
  1276. case 2:
  1277. snd_soc_component_update_bits(component,
  1278. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1279. mode);
  1280. break;
  1281. case 3:
  1282. snd_soc_component_update_bits(component,
  1283. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1284. mode << 4);
  1285. break;
  1286. default:
  1287. break;
  1288. }
  1289. set_bit(w->shift, &wcd938x->status_mask);
  1290. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1291. break;
  1292. case SND_SOC_DAPM_POST_PMD:
  1293. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1294. snd_soc_component_update_bits(component,
  1295. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1296. clear_bit(w->shift, &wcd938x->status_mask);
  1297. break;
  1298. };
  1299. return 0;
  1300. }
  1301. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1302. int channel, int mode)
  1303. {
  1304. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1305. int ret = 0;
  1306. switch (channel) {
  1307. case 0:
  1308. reg = WCD938X_ANA_TX_CH2;
  1309. mask = 0x40;
  1310. break;
  1311. case 1:
  1312. reg = WCD938X_ANA_TX_CH2;
  1313. mask = 0x20;
  1314. break;
  1315. case 2:
  1316. reg = WCD938X_ANA_TX_CH4;
  1317. mask = 0x40;
  1318. break;
  1319. case 3:
  1320. reg = WCD938X_ANA_TX_CH4;
  1321. mask = 0x20;
  1322. break;
  1323. default:
  1324. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1325. ret = -EINVAL;
  1326. break;
  1327. }
  1328. if (!mode)
  1329. val = 0x00;
  1330. else
  1331. val = mask;
  1332. if (!ret)
  1333. snd_soc_component_update_bits(component, reg, mask, val);
  1334. return ret;
  1335. }
  1336. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1337. struct snd_kcontrol *kcontrol, int event)
  1338. {
  1339. struct snd_soc_component *component =
  1340. snd_soc_dapm_to_component(w->dapm);
  1341. int ret = 0;
  1342. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1343. w->name, event);
  1344. switch (event) {
  1345. case SND_SOC_DAPM_PRE_PMU:
  1346. snd_soc_component_update_bits(component,
  1347. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1348. snd_soc_component_update_bits(component,
  1349. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1350. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1351. snd_soc_component_update_bits(component,
  1352. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1353. snd_soc_component_update_bits(component,
  1354. WCD938X_ANA_TX_CH1, 0x80, 0x80);
  1355. snd_soc_component_update_bits(component,
  1356. WCD938X_ANA_TX_CH2, 0x80, 0x80);
  1357. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1358. break;
  1359. case SND_SOC_DAPM_POST_PMD:
  1360. snd_soc_component_update_bits(component,
  1361. WCD938X_ANA_TX_CH1, 0x80, 0x00);
  1362. snd_soc_component_update_bits(component,
  1363. WCD938X_ANA_TX_CH2, 0x80, 0x00);
  1364. snd_soc_component_update_bits(component,
  1365. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1366. snd_soc_component_update_bits(component,
  1367. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1368. snd_soc_component_update_bits(component,
  1369. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1370. break;
  1371. };
  1372. return ret;
  1373. }
  1374. int wcd938x_micbias_control(struct snd_soc_component *component,
  1375. int micb_num, int req, bool is_dapm)
  1376. {
  1377. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1378. int micb_index = micb_num - 1;
  1379. u16 micb_reg;
  1380. int pre_off_event = 0, post_off_event = 0;
  1381. int post_on_event = 0, post_dapm_off = 0;
  1382. int post_dapm_on = 0;
  1383. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1384. dev_err(component->dev,
  1385. "%s: Invalid micbias index, micb_ind:%d\n",
  1386. __func__, micb_index);
  1387. return -EINVAL;
  1388. }
  1389. if (NULL == wcd938x) {
  1390. dev_err(component->dev,
  1391. "%s: wcd938x private data is NULL\n", __func__);
  1392. return -EINVAL;
  1393. }
  1394. switch (micb_num) {
  1395. case MIC_BIAS_1:
  1396. micb_reg = WCD938X_ANA_MICB1;
  1397. break;
  1398. case MIC_BIAS_2:
  1399. micb_reg = WCD938X_ANA_MICB2;
  1400. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1401. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1402. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1403. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1404. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1405. break;
  1406. case MIC_BIAS_3:
  1407. micb_reg = WCD938X_ANA_MICB3;
  1408. break;
  1409. case MIC_BIAS_4:
  1410. micb_reg = WCD938X_ANA_MICB4;
  1411. break;
  1412. default:
  1413. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1414. __func__, micb_num);
  1415. return -EINVAL;
  1416. };
  1417. mutex_lock(&wcd938x->micb_lock);
  1418. switch (req) {
  1419. case MICB_PULLUP_ENABLE:
  1420. wcd938x->pullup_ref[micb_index]++;
  1421. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1422. (wcd938x->micb_ref[micb_index] == 0))
  1423. snd_soc_component_update_bits(component, micb_reg,
  1424. 0xC0, 0x80);
  1425. break;
  1426. case MICB_PULLUP_DISABLE:
  1427. if (wcd938x->pullup_ref[micb_index] > 0)
  1428. wcd938x->pullup_ref[micb_index]--;
  1429. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1430. (wcd938x->micb_ref[micb_index] == 0))
  1431. snd_soc_component_update_bits(component, micb_reg,
  1432. 0xC0, 0x00);
  1433. break;
  1434. case MICB_ENABLE:
  1435. wcd938x->micb_ref[micb_index]++;
  1436. if (wcd938x->micb_ref[micb_index] == 1) {
  1437. snd_soc_component_update_bits(component,
  1438. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1439. snd_soc_component_update_bits(component,
  1440. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1441. snd_soc_component_update_bits(component,
  1442. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1443. snd_soc_component_update_bits(component,
  1444. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1445. snd_soc_component_update_bits(component,
  1446. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1447. snd_soc_component_update_bits(component,
  1448. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1449. snd_soc_component_update_bits(component,
  1450. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1451. snd_soc_component_update_bits(component,
  1452. micb_reg, 0xC0, 0x40);
  1453. if (post_on_event)
  1454. blocking_notifier_call_chain(
  1455. &wcd938x->mbhc->notifier,
  1456. post_on_event,
  1457. &wcd938x->mbhc->wcd_mbhc);
  1458. }
  1459. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1460. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1461. post_dapm_on,
  1462. &wcd938x->mbhc->wcd_mbhc);
  1463. break;
  1464. case MICB_DISABLE:
  1465. if (wcd938x->micb_ref[micb_index] > 0)
  1466. wcd938x->micb_ref[micb_index]--;
  1467. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1468. (wcd938x->pullup_ref[micb_index] > 0))
  1469. snd_soc_component_update_bits(component, micb_reg,
  1470. 0xC0, 0x80);
  1471. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1472. (wcd938x->pullup_ref[micb_index] == 0)) {
  1473. if (pre_off_event && wcd938x->mbhc)
  1474. blocking_notifier_call_chain(
  1475. &wcd938x->mbhc->notifier,
  1476. pre_off_event,
  1477. &wcd938x->mbhc->wcd_mbhc);
  1478. snd_soc_component_update_bits(component, micb_reg,
  1479. 0xC0, 0x00);
  1480. if (post_off_event && wcd938x->mbhc)
  1481. blocking_notifier_call_chain(
  1482. &wcd938x->mbhc->notifier,
  1483. post_off_event,
  1484. &wcd938x->mbhc->wcd_mbhc);
  1485. }
  1486. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1487. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1488. post_dapm_off,
  1489. &wcd938x->mbhc->wcd_mbhc);
  1490. break;
  1491. };
  1492. dev_dbg(component->dev,
  1493. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1494. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1495. wcd938x->pullup_ref[micb_index]);
  1496. mutex_unlock(&wcd938x->micb_lock);
  1497. return 0;
  1498. }
  1499. EXPORT_SYMBOL(wcd938x_micbias_control);
  1500. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1501. {
  1502. int ret = 0;
  1503. uint8_t devnum = 0;
  1504. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1505. if (ret) {
  1506. dev_err(&swr_dev->dev,
  1507. "%s get devnum %d for dev addr %lx failed\n",
  1508. __func__, devnum, swr_dev->addr);
  1509. swr_remove_device(swr_dev);
  1510. return ret;
  1511. }
  1512. swr_dev->dev_num = devnum;
  1513. return 0;
  1514. }
  1515. static int wcd938x_event_notify(struct notifier_block *block,
  1516. unsigned long val,
  1517. void *data)
  1518. {
  1519. u16 event = (val & 0xffff);
  1520. int ret = 0;
  1521. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1522. struct snd_soc_component *component = wcd938x->component;
  1523. struct wcd_mbhc *mbhc;
  1524. switch (event) {
  1525. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1526. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1527. snd_soc_component_update_bits(component,
  1528. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1529. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1530. }
  1531. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1532. snd_soc_component_update_bits(component,
  1533. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1534. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1535. }
  1536. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1537. snd_soc_component_update_bits(component,
  1538. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1539. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1540. }
  1541. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1542. snd_soc_component_update_bits(component,
  1543. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1544. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1545. }
  1546. break;
  1547. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1548. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1549. 0xC0, 0x00);
  1550. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1551. 0x80, 0x00);
  1552. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1553. 0x80, 0x00);
  1554. break;
  1555. case BOLERO_WCD_EVT_SSR_DOWN:
  1556. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1557. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1558. wcd938x_reset_low(wcd938x->dev);
  1559. break;
  1560. case BOLERO_WCD_EVT_SSR_UP:
  1561. wcd938x_reset(wcd938x->dev);
  1562. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1563. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1564. wcd938x_init_reg(component);
  1565. regcache_mark_dirty(wcd938x->regmap);
  1566. regcache_sync(wcd938x->regmap);
  1567. /* Initialize MBHC module */
  1568. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1569. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1570. if (ret) {
  1571. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1572. __func__);
  1573. } else {
  1574. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1575. }
  1576. break;
  1577. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1578. snd_soc_component_update_bits(component,
  1579. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1580. ((val >> 0x10) << 0x01));
  1581. break;
  1582. default:
  1583. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1584. break;
  1585. }
  1586. return 0;
  1587. }
  1588. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1589. int event)
  1590. {
  1591. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1592. int micb_num;
  1593. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1594. __func__, w->name, event);
  1595. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1596. micb_num = MIC_BIAS_1;
  1597. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1598. micb_num = MIC_BIAS_2;
  1599. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1600. micb_num = MIC_BIAS_3;
  1601. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1602. micb_num = MIC_BIAS_4;
  1603. else
  1604. return -EINVAL;
  1605. switch (event) {
  1606. case SND_SOC_DAPM_PRE_PMU:
  1607. wcd938x_micbias_control(component, micb_num,
  1608. MICB_ENABLE, true);
  1609. break;
  1610. case SND_SOC_DAPM_POST_PMU:
  1611. /* 1 msec delay as per HW requirement */
  1612. usleep_range(1000, 1100);
  1613. break;
  1614. case SND_SOC_DAPM_POST_PMD:
  1615. wcd938x_micbias_control(component, micb_num,
  1616. MICB_DISABLE, true);
  1617. break;
  1618. };
  1619. return 0;
  1620. }
  1621. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1622. struct snd_kcontrol *kcontrol,
  1623. int event)
  1624. {
  1625. return __wcd938x_codec_enable_micbias(w, event);
  1626. }
  1627. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1628. int event)
  1629. {
  1630. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1631. int micb_num;
  1632. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1633. __func__, w->name, event);
  1634. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1635. micb_num = MIC_BIAS_1;
  1636. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1637. micb_num = MIC_BIAS_2;
  1638. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1639. micb_num = MIC_BIAS_3;
  1640. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1641. micb_num = MIC_BIAS_4;
  1642. else
  1643. return -EINVAL;
  1644. switch (event) {
  1645. case SND_SOC_DAPM_PRE_PMU:
  1646. wcd938x_micbias_control(component, micb_num,
  1647. MICB_PULLUP_ENABLE, true);
  1648. break;
  1649. case SND_SOC_DAPM_POST_PMU:
  1650. /* 1 msec delay as per HW requirement */
  1651. usleep_range(1000, 1100);
  1652. break;
  1653. case SND_SOC_DAPM_POST_PMD:
  1654. wcd938x_micbias_control(component, micb_num,
  1655. MICB_PULLUP_DISABLE, true);
  1656. break;
  1657. };
  1658. return 0;
  1659. }
  1660. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1661. struct snd_kcontrol *kcontrol,
  1662. int event)
  1663. {
  1664. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1665. }
  1666. static inline int wcd938x_tx_path_get(const char *wname,
  1667. unsigned int *path_num)
  1668. {
  1669. int ret = 0;
  1670. char *widget_name = NULL;
  1671. char *w_name = NULL;
  1672. char *path_num_char = NULL;
  1673. char *path_name = NULL;
  1674. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1675. if (!widget_name)
  1676. return -EINVAL;
  1677. w_name = widget_name;
  1678. path_name = strsep(&widget_name, " ");
  1679. if (!path_name) {
  1680. pr_err("%s: Invalid widget name = %s\n",
  1681. __func__, widget_name);
  1682. ret = -EINVAL;
  1683. goto err;
  1684. }
  1685. path_num_char = strpbrk(path_name, "0123");
  1686. if (!path_num_char) {
  1687. pr_err("%s: tx path index not found\n",
  1688. __func__);
  1689. ret = -EINVAL;
  1690. goto err;
  1691. }
  1692. ret = kstrtouint(path_num_char, 10, path_num);
  1693. if (ret < 0)
  1694. pr_err("%s: Invalid tx path = %s\n",
  1695. __func__, w_name);
  1696. err:
  1697. kfree(w_name);
  1698. return ret;
  1699. }
  1700. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1701. struct snd_ctl_elem_value *ucontrol)
  1702. {
  1703. struct snd_soc_component *component =
  1704. snd_soc_kcontrol_component(kcontrol);
  1705. struct wcd938x_priv *wcd938x = NULL;
  1706. int ret = 0;
  1707. unsigned int path = 0;
  1708. if (!component)
  1709. return -EINVAL;
  1710. wcd938x = snd_soc_component_get_drvdata(component);
  1711. if (!wcd938x)
  1712. return -EINVAL;
  1713. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1714. if (ret < 0)
  1715. return ret;
  1716. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1717. return 0;
  1718. }
  1719. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1720. struct snd_ctl_elem_value *ucontrol)
  1721. {
  1722. struct snd_soc_component *component =
  1723. snd_soc_kcontrol_component(kcontrol);
  1724. struct wcd938x_priv *wcd938x = NULL;
  1725. u32 mode_val;
  1726. unsigned int path = 0;
  1727. int ret = 0;
  1728. if (!component)
  1729. return -EINVAL;
  1730. wcd938x = snd_soc_component_get_drvdata(component);
  1731. if (!wcd938x)
  1732. return -EINVAL;
  1733. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1734. if (ret)
  1735. return ret;
  1736. mode_val = ucontrol->value.enumerated.item[0];
  1737. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1738. wcd938x->tx_mode[path] = mode_val;
  1739. return 0;
  1740. }
  1741. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1742. struct snd_ctl_elem_value *ucontrol)
  1743. {
  1744. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1745. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1746. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1747. return 0;
  1748. }
  1749. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1750. struct snd_ctl_elem_value *ucontrol)
  1751. {
  1752. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1753. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1754. u32 mode_val;
  1755. mode_val = ucontrol->value.enumerated.item[0];
  1756. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1757. if (mode_val == 0) {
  1758. dev_info(component->dev,
  1759. "%s:Invalid HPH Mode, default to class_AB\n",
  1760. __func__);
  1761. mode_val = 3; /* enum will be updated later */
  1762. }
  1763. wcd938x->hph_mode = mode_val;
  1764. return 0;
  1765. }
  1766. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1767. struct snd_ctl_elem_value *ucontrol)
  1768. {
  1769. struct snd_soc_component *component =
  1770. snd_soc_kcontrol_component(kcontrol);
  1771. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1772. bool hphr;
  1773. struct soc_multi_mixer_control *mc;
  1774. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1775. hphr = mc->shift;
  1776. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1777. wcd938x->comp1_enable;
  1778. return 0;
  1779. }
  1780. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1781. struct snd_ctl_elem_value *ucontrol)
  1782. {
  1783. struct snd_soc_component *component =
  1784. snd_soc_kcontrol_component(kcontrol);
  1785. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1786. int value = ucontrol->value.integer.value[0];
  1787. bool hphr;
  1788. struct soc_multi_mixer_control *mc;
  1789. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1790. hphr = mc->shift;
  1791. if (hphr)
  1792. wcd938x->comp2_enable = value;
  1793. else
  1794. wcd938x->comp1_enable = value;
  1795. return 0;
  1796. }
  1797. static const char * const tx_mode_mux_text_wcd9380[] = {
  1798. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1799. };
  1800. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  1801. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  1802. tx_mode_mux_text_wcd9380);
  1803. static const char * const tx_mode_mux_text[] = {
  1804. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1805. "ADC_ULP1", "ADC_ULP2",
  1806. };
  1807. static const struct soc_enum tx_mode_mux_enum =
  1808. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  1809. tx_mode_mux_text);
  1810. static const char * const rx_hph_mode_mux_text[] = {
  1811. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1812. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  1813. };
  1814. static const struct soc_enum rx_hph_mode_mux_enum =
  1815. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1816. rx_hph_mode_mux_text);
  1817. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  1818. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  1819. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1820. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  1821. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1822. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  1823. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1824. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  1825. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1826. };
  1827. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  1828. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  1829. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1830. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  1831. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1832. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  1833. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1834. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  1835. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1836. };
  1837. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  1838. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1839. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1840. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1841. wcd938x_get_compander, wcd938x_set_compander),
  1842. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1843. wcd938x_get_compander, wcd938x_set_compander),
  1844. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  1845. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  1846. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  1847. analog_gain),
  1848. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  1849. analog_gain),
  1850. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  1851. analog_gain),
  1852. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  1853. analog_gain),
  1854. };
  1855. static const struct snd_kcontrol_new adc1_switch[] = {
  1856. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1857. };
  1858. static const struct snd_kcontrol_new adc2_switch[] = {
  1859. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1860. };
  1861. static const struct snd_kcontrol_new adc3_switch[] = {
  1862. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1863. };
  1864. static const struct snd_kcontrol_new adc4_switch[] = {
  1865. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1866. };
  1867. static const struct snd_kcontrol_new dmic1_switch[] = {
  1868. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1869. };
  1870. static const struct snd_kcontrol_new dmic2_switch[] = {
  1871. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1872. };
  1873. static const struct snd_kcontrol_new dmic3_switch[] = {
  1874. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1875. };
  1876. static const struct snd_kcontrol_new dmic4_switch[] = {
  1877. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1878. };
  1879. static const struct snd_kcontrol_new dmic5_switch[] = {
  1880. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1881. };
  1882. static const struct snd_kcontrol_new dmic6_switch[] = {
  1883. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1884. };
  1885. static const struct snd_kcontrol_new dmic7_switch[] = {
  1886. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1887. };
  1888. static const struct snd_kcontrol_new dmic8_switch[] = {
  1889. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1890. };
  1891. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1892. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1893. };
  1894. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1895. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1896. };
  1897. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1898. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1899. };
  1900. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1901. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1902. };
  1903. static const char * const adc2_mux_text[] = {
  1904. "INP2", "INP3"
  1905. };
  1906. static const struct soc_enum adc2_enum =
  1907. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  1908. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1909. static const struct snd_kcontrol_new tx_adc2_mux =
  1910. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1911. static const char * const adc3_mux_text[] = {
  1912. "INP4", "INP6"
  1913. };
  1914. static const struct soc_enum adc3_enum =
  1915. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  1916. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  1917. static const struct snd_kcontrol_new tx_adc3_mux =
  1918. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  1919. static const char * const adc4_mux_text[] = {
  1920. "INP5", "INP7"
  1921. };
  1922. static const struct soc_enum adc4_enum =
  1923. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  1924. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  1925. static const struct snd_kcontrol_new tx_adc4_mux =
  1926. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  1927. static const char * const rdac3_mux_text[] = {
  1928. "RX1", "RX3"
  1929. };
  1930. static const char * const hdr12_mux_text[] = {
  1931. "NO_HDR12", "HDR12"
  1932. };
  1933. static const struct soc_enum hdr12_enum =
  1934. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  1935. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  1936. static const struct snd_kcontrol_new tx_hdr12_mux =
  1937. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  1938. static const char * const hdr34_mux_text[] = {
  1939. "NO_HDR34", "HDR34"
  1940. };
  1941. static const struct soc_enum hdr34_enum =
  1942. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  1943. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  1944. static const struct snd_kcontrol_new tx_hdr34_mux =
  1945. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  1946. static const struct soc_enum rdac3_enum =
  1947. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1948. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1949. static const struct snd_kcontrol_new rx_rdac3_mux =
  1950. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1951. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  1952. /*input widgets*/
  1953. SND_SOC_DAPM_INPUT("AMIC1"),
  1954. SND_SOC_DAPM_INPUT("AMIC2"),
  1955. SND_SOC_DAPM_INPUT("AMIC3"),
  1956. SND_SOC_DAPM_INPUT("AMIC4"),
  1957. SND_SOC_DAPM_INPUT("AMIC5"),
  1958. SND_SOC_DAPM_INPUT("AMIC6"),
  1959. SND_SOC_DAPM_INPUT("AMIC7"),
  1960. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1961. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1962. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1963. /*tx widgets*/
  1964. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1965. wcd938x_codec_enable_adc,
  1966. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1967. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1968. wcd938x_codec_enable_adc,
  1969. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1970. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1971. wcd938x_codec_enable_adc,
  1972. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1973. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  1974. wcd938x_codec_enable_adc,
  1975. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1976. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1977. wcd938x_codec_enable_dmic,
  1978. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1979. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1980. wcd938x_codec_enable_dmic,
  1981. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1982. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1983. wcd938x_codec_enable_dmic,
  1984. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1985. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1986. wcd938x_codec_enable_dmic,
  1987. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1988. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1989. wcd938x_codec_enable_dmic,
  1990. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1991. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1992. wcd938x_codec_enable_dmic,
  1993. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1994. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  1995. wcd938x_codec_enable_dmic,
  1996. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1997. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  1998. wcd938x_codec_enable_dmic,
  1999. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2000. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2001. NULL, 0, wcd938x_enable_req,
  2002. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2003. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2004. NULL, 0, wcd938x_enable_req,
  2005. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2006. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2007. NULL, 0, wcd938x_enable_req,
  2008. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2009. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2010. NULL, 0, wcd938x_enable_req,
  2011. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2012. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2013. &tx_adc2_mux),
  2014. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2015. &tx_adc3_mux),
  2016. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2017. &tx_adc4_mux),
  2018. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2019. &tx_hdr12_mux),
  2020. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2021. &tx_hdr34_mux),
  2022. /*tx mixers*/
  2023. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2024. adc1_switch, ARRAY_SIZE(adc1_switch),
  2025. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2026. SND_SOC_DAPM_POST_PMD),
  2027. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2028. adc2_switch, ARRAY_SIZE(adc2_switch),
  2029. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2030. SND_SOC_DAPM_POST_PMD),
  2031. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2032. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2033. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2034. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2035. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2036. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2037. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2038. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2039. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2040. SND_SOC_DAPM_POST_PMD),
  2041. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2042. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2043. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2044. SND_SOC_DAPM_POST_PMD),
  2045. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2046. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2047. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2048. SND_SOC_DAPM_POST_PMD),
  2049. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2050. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2051. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2052. SND_SOC_DAPM_POST_PMD),
  2053. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2054. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2055. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2056. SND_SOC_DAPM_POST_PMD),
  2057. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2058. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2059. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2060. SND_SOC_DAPM_POST_PMD),
  2061. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2062. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2063. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2064. SND_SOC_DAPM_POST_PMD),
  2065. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2066. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2067. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2068. SND_SOC_DAPM_POST_PMD),
  2069. /* micbias widgets*/
  2070. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2071. wcd938x_codec_enable_micbias,
  2072. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2073. SND_SOC_DAPM_POST_PMD),
  2074. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2075. wcd938x_codec_enable_micbias,
  2076. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2077. SND_SOC_DAPM_POST_PMD),
  2078. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2079. wcd938x_codec_enable_micbias,
  2080. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2081. SND_SOC_DAPM_POST_PMD),
  2082. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2083. wcd938x_codec_enable_micbias,
  2084. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2085. SND_SOC_DAPM_POST_PMD),
  2086. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2087. wcd938x_enable_clsh,
  2088. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2089. /*rx widgets*/
  2090. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2091. wcd938x_codec_enable_ear_pa,
  2092. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2093. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2094. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2095. wcd938x_codec_enable_aux_pa,
  2096. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2097. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2098. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2099. wcd938x_codec_enable_hphl_pa,
  2100. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2101. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2102. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2103. wcd938x_codec_enable_hphr_pa,
  2104. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2105. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2106. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2107. wcd938x_codec_hphl_dac_event,
  2108. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2109. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2110. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2111. wcd938x_codec_hphr_dac_event,
  2112. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2113. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2114. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2115. wcd938x_codec_ear_dac_event,
  2116. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2117. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2118. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2119. wcd938x_codec_aux_dac_event,
  2120. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2121. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2122. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2123. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2124. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2125. SND_SOC_DAPM_POST_PMD),
  2126. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2127. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2128. SND_SOC_DAPM_POST_PMD),
  2129. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2130. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2131. SND_SOC_DAPM_POST_PMD),
  2132. /* rx mixer widgets*/
  2133. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2134. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2135. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2136. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2137. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2138. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2139. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2140. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2141. /*output widgets tx*/
  2142. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2143. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2144. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2145. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  2146. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2147. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2148. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2149. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2150. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2151. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2152. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  2153. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  2154. /*output widgets rx*/
  2155. SND_SOC_DAPM_OUTPUT("EAR"),
  2156. SND_SOC_DAPM_OUTPUT("AUX"),
  2157. SND_SOC_DAPM_OUTPUT("HPHL"),
  2158. SND_SOC_DAPM_OUTPUT("HPHR"),
  2159. /* micbias pull up widgets*/
  2160. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2161. wcd938x_codec_enable_micbias_pullup,
  2162. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2163. SND_SOC_DAPM_POST_PMD),
  2164. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2165. wcd938x_codec_enable_micbias_pullup,
  2166. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2167. SND_SOC_DAPM_POST_PMD),
  2168. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2169. wcd938x_codec_enable_micbias_pullup,
  2170. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2171. SND_SOC_DAPM_POST_PMD),
  2172. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2173. wcd938x_codec_enable_micbias_pullup,
  2174. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2175. SND_SOC_DAPM_POST_PMD),
  2176. };
  2177. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2178. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  2179. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2180. {"ADC1 REQ", NULL, "ADC1"},
  2181. {"ADC1", NULL, "AMIC1"},
  2182. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  2183. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2184. {"ADC2 REQ", NULL, "ADC2"},
  2185. {"ADC2", NULL, "HDR12 MUX"},
  2186. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2187. {"HDR12 MUX", "HDR12", "AMIC1"},
  2188. {"ADC2 MUX", "INP3", "AMIC3"},
  2189. {"ADC2 MUX", "INP2", "AMIC2"},
  2190. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2191. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2192. {"ADC3 REQ", NULL, "ADC3"},
  2193. {"ADC3", NULL, "HDR34 MUX"},
  2194. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2195. {"HDR34 MUX", "HDR34", "AMIC5"},
  2196. {"ADC3 MUX", "INP4", "AMIC4"},
  2197. {"ADC3 MUX", "INP6", "AMIC6"},
  2198. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  2199. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2200. {"ADC4 REQ", NULL, "ADC4"},
  2201. {"ADC4", NULL, "ADC4 MUX"},
  2202. {"ADC4 MUX", "INP5", "AMIC5"},
  2203. {"ADC4 MUX", "INP7", "AMIC7"},
  2204. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2205. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2206. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2207. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2208. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2209. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2210. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2211. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2212. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2213. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2214. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2215. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2216. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  2217. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2218. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  2219. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2220. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2221. {"RX1", NULL, "IN1_HPHL"},
  2222. {"RDAC1", NULL, "RX1"},
  2223. {"HPHL_RDAC", "Switch", "RDAC1"},
  2224. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2225. {"HPHL", NULL, "HPHL PGA"},
  2226. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2227. {"RX2", NULL, "IN2_HPHR"},
  2228. {"RDAC2", NULL, "RX2"},
  2229. {"HPHR_RDAC", "Switch", "RDAC2"},
  2230. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2231. {"HPHR", NULL, "HPHR PGA"},
  2232. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2233. {"RX3", NULL, "IN3_AUX"},
  2234. {"RDAC4", NULL, "RX3"},
  2235. {"AUX_RDAC", "Switch", "RDAC4"},
  2236. {"AUX PGA", NULL, "AUX_RDAC"},
  2237. {"AUX", NULL, "AUX PGA"},
  2238. {"RDAC3_MUX", "RX3", "RX3"},
  2239. {"RDAC3_MUX", "RX1", "RX1"},
  2240. {"RDAC3", NULL, "RDAC3_MUX"},
  2241. {"EAR_RDAC", "Switch", "RDAC3"},
  2242. {"EAR PGA", NULL, "EAR_RDAC"},
  2243. {"EAR", NULL, "EAR PGA"},
  2244. };
  2245. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2246. void *file_private_data,
  2247. struct file *file,
  2248. char __user *buf, size_t count,
  2249. loff_t pos)
  2250. {
  2251. struct wcd938x_priv *priv;
  2252. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2253. int len = 0;
  2254. priv = (struct wcd938x_priv *) entry->private_data;
  2255. if (!priv) {
  2256. pr_err("%s: wcd938x priv is null\n", __func__);
  2257. return -EINVAL;
  2258. }
  2259. switch (priv->version) {
  2260. case WCD938X_VERSION_1_0:
  2261. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2262. break;
  2263. default:
  2264. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2265. }
  2266. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2267. }
  2268. static struct snd_info_entry_ops wcd938x_info_ops = {
  2269. .read = wcd938x_version_read,
  2270. };
  2271. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2272. void *file_private_data,
  2273. struct file *file,
  2274. char __user *buf, size_t count,
  2275. loff_t pos)
  2276. {
  2277. struct wcd938x_priv *priv;
  2278. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2279. int len = 0;
  2280. priv = (struct wcd938x_priv *) entry->private_data;
  2281. if (!priv) {
  2282. pr_err("%s: wcd938x priv is null\n", __func__);
  2283. return -EINVAL;
  2284. }
  2285. switch (priv->variant) {
  2286. case WCD9380:
  2287. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2288. break;
  2289. case WCD9385:
  2290. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2291. break;
  2292. default:
  2293. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2294. }
  2295. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2296. }
  2297. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2298. .read = wcd938x_variant_read,
  2299. };
  2300. /*
  2301. * wcd938x_info_create_codec_entry - creates wcd938x module
  2302. * @codec_root: The parent directory
  2303. * @component: component instance
  2304. *
  2305. * Creates wcd938x module, variant and version entry under the given
  2306. * parent directory.
  2307. *
  2308. * Return: 0 on success or negative error code on failure.
  2309. */
  2310. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2311. struct snd_soc_component *component)
  2312. {
  2313. struct snd_info_entry *version_entry;
  2314. struct snd_info_entry *variant_entry;
  2315. struct wcd938x_priv *priv;
  2316. struct snd_soc_card *card;
  2317. if (!codec_root || !component)
  2318. return -EINVAL;
  2319. priv = snd_soc_component_get_drvdata(component);
  2320. if (priv->entry) {
  2321. dev_dbg(priv->dev,
  2322. "%s:wcd938x module already created\n", __func__);
  2323. return 0;
  2324. }
  2325. card = component->card;
  2326. priv->entry = snd_info_create_subdir(codec_root->module,
  2327. "wcd938x", codec_root);
  2328. if (!priv->entry) {
  2329. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2330. __func__);
  2331. return -ENOMEM;
  2332. }
  2333. version_entry = snd_info_create_card_entry(card->snd_card,
  2334. "version",
  2335. priv->entry);
  2336. if (!version_entry) {
  2337. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2338. __func__);
  2339. return -ENOMEM;
  2340. }
  2341. version_entry->private_data = priv;
  2342. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2343. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2344. version_entry->c.ops = &wcd938x_info_ops;
  2345. if (snd_info_register(version_entry) < 0) {
  2346. snd_info_free_entry(version_entry);
  2347. return -ENOMEM;
  2348. }
  2349. priv->version_entry = version_entry;
  2350. variant_entry = snd_info_create_card_entry(card->snd_card,
  2351. "variant",
  2352. priv->entry);
  2353. if (!variant_entry) {
  2354. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  2355. __func__);
  2356. return -ENOMEM;
  2357. }
  2358. variant_entry->private_data = priv;
  2359. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  2360. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2361. variant_entry->c.ops = &wcd938x_variant_ops;
  2362. if (snd_info_register(variant_entry) < 0) {
  2363. snd_info_free_entry(variant_entry);
  2364. return -ENOMEM;
  2365. }
  2366. priv->variant_entry = variant_entry;
  2367. return 0;
  2368. }
  2369. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2370. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2371. {
  2372. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2373. struct snd_soc_dapm_context *dapm =
  2374. snd_soc_component_get_dapm(component);
  2375. int variant;
  2376. int ret = -EINVAL;
  2377. dev_info(component->dev, "%s()\n", __func__);
  2378. wcd938x = snd_soc_component_get_drvdata(component);
  2379. if (!wcd938x)
  2380. return -EINVAL;
  2381. wcd938x->component = component;
  2382. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2383. variant = (snd_soc_component_read32(component,
  2384. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2385. wcd938x->variant = variant;
  2386. wcd938x->fw_data = devm_kzalloc(component->dev,
  2387. sizeof(*(wcd938x->fw_data)),
  2388. GFP_KERNEL);
  2389. if (!wcd938x->fw_data) {
  2390. dev_err(component->dev, "Failed to allocate fw_data\n");
  2391. ret = -ENOMEM;
  2392. goto err;
  2393. }
  2394. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2395. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2396. WCD9XXX_CODEC_HWDEP_NODE, component);
  2397. if (ret < 0) {
  2398. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2399. goto err_hwdep;
  2400. }
  2401. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2402. if (ret) {
  2403. pr_err("%s: mbhc initialization failed\n", __func__);
  2404. goto err_hwdep;
  2405. }
  2406. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2407. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2408. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2409. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2410. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2411. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2412. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2413. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2414. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2415. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2416. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2417. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2418. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2419. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2420. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2421. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2422. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2423. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2424. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2425. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2426. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2427. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2428. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2429. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2430. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2431. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2432. snd_soc_dapm_sync(dapm);
  2433. wcd_cls_h_init(&wcd938x->clsh_info);
  2434. wcd938x_init_reg(component);
  2435. if (wcd938x->variant == WCD9380) {
  2436. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  2437. ARRAY_SIZE(wcd9380_snd_controls));
  2438. if (ret < 0) {
  2439. dev_err(component->dev,
  2440. "%s: Failed to add snd ctrls for variant: %d\n",
  2441. __func__, wcd938x->variant);
  2442. goto err_hwdep;
  2443. }
  2444. }
  2445. if (wcd938x->variant == WCD9385) {
  2446. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  2447. ARRAY_SIZE(wcd9385_snd_controls));
  2448. if (ret < 0) {
  2449. dev_err(component->dev,
  2450. "%s: Failed to add snd ctrls for variant: %d\n",
  2451. __func__, wcd938x->variant);
  2452. goto err_hwdep;
  2453. }
  2454. }
  2455. wcd938x->version = WCD938X_VERSION_1_0;
  2456. /* Register event notifier */
  2457. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2458. if (wcd938x->register_notifier) {
  2459. ret = wcd938x->register_notifier(wcd938x->handle,
  2460. &wcd938x->nblock,
  2461. true);
  2462. if (ret) {
  2463. dev_err(component->dev,
  2464. "%s: Failed to register notifier %d\n",
  2465. __func__, ret);
  2466. return ret;
  2467. }
  2468. }
  2469. return ret;
  2470. err_hwdep:
  2471. wcd938x->fw_data = NULL;
  2472. err:
  2473. return ret;
  2474. }
  2475. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2476. {
  2477. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2478. if (!wcd938x) {
  2479. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2480. __func__);
  2481. return;
  2482. }
  2483. if (wcd938x->register_notifier)
  2484. wcd938x->register_notifier(wcd938x->handle,
  2485. &wcd938x->nblock,
  2486. false);
  2487. }
  2488. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2489. .name = WCD938X_DRV_NAME,
  2490. .probe = wcd938x_soc_codec_probe,
  2491. .remove = wcd938x_soc_codec_remove,
  2492. .controls = wcd938x_snd_controls,
  2493. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2494. .dapm_widgets = wcd938x_dapm_widgets,
  2495. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2496. .dapm_routes = wcd938x_audio_map,
  2497. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2498. };
  2499. static int wcd938x_reset(struct device *dev)
  2500. {
  2501. struct wcd938x_priv *wcd938x = NULL;
  2502. int rc = 0;
  2503. int value = 0;
  2504. if (!dev)
  2505. return -ENODEV;
  2506. wcd938x = dev_get_drvdata(dev);
  2507. if (!wcd938x)
  2508. return -EINVAL;
  2509. if (!wcd938x->rst_np) {
  2510. dev_err(dev, "%s: reset gpio device node not specified\n",
  2511. __func__);
  2512. return -EINVAL;
  2513. }
  2514. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2515. if (value > 0)
  2516. return 0;
  2517. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2518. if (rc) {
  2519. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2520. __func__);
  2521. return rc;
  2522. }
  2523. /* 20us sleep required after pulling the reset gpio to LOW */
  2524. usleep_range(20, 30);
  2525. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2526. if (rc) {
  2527. dev_err(dev, "%s: wcd active state request fail!\n",
  2528. __func__);
  2529. return rc;
  2530. }
  2531. /* 20us sleep required after pulling the reset gpio to HIGH */
  2532. usleep_range(20, 30);
  2533. return rc;
  2534. }
  2535. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2536. u32 *val)
  2537. {
  2538. int rc = 0;
  2539. rc = of_property_read_u32(dev->of_node, name, val);
  2540. if (rc)
  2541. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2542. __func__, name, dev->of_node->full_name);
  2543. return rc;
  2544. }
  2545. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2546. struct wcd938x_micbias_setting *mb)
  2547. {
  2548. u32 prop_val = 0;
  2549. int rc = 0;
  2550. /* MB1 */
  2551. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2552. NULL)) {
  2553. rc = wcd938x_read_of_property_u32(dev,
  2554. "qcom,cdc-micbias1-mv",
  2555. &prop_val);
  2556. if (!rc)
  2557. mb->micb1_mv = prop_val;
  2558. } else {
  2559. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2560. __func__);
  2561. }
  2562. /* MB2 */
  2563. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2564. NULL)) {
  2565. rc = wcd938x_read_of_property_u32(dev,
  2566. "qcom,cdc-micbias2-mv",
  2567. &prop_val);
  2568. if (!rc)
  2569. mb->micb2_mv = prop_val;
  2570. } else {
  2571. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2572. __func__);
  2573. }
  2574. /* MB3 */
  2575. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2576. NULL)) {
  2577. rc = wcd938x_read_of_property_u32(dev,
  2578. "qcom,cdc-micbias3-mv",
  2579. &prop_val);
  2580. if (!rc)
  2581. mb->micb3_mv = prop_val;
  2582. } else {
  2583. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2584. __func__);
  2585. }
  2586. }
  2587. static int wcd938x_reset_low(struct device *dev)
  2588. {
  2589. struct wcd938x_priv *wcd938x = NULL;
  2590. int rc = 0;
  2591. if (!dev)
  2592. return -ENODEV;
  2593. wcd938x = dev_get_drvdata(dev);
  2594. if (!wcd938x)
  2595. return -EINVAL;
  2596. if (!wcd938x->rst_np) {
  2597. dev_err(dev, "%s: reset gpio device node not specified\n",
  2598. __func__);
  2599. return -EINVAL;
  2600. }
  2601. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2602. if (rc) {
  2603. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2604. __func__);
  2605. return rc;
  2606. }
  2607. /* 20us sleep required after pulling the reset gpio to LOW */
  2608. usleep_range(20, 30);
  2609. return rc;
  2610. }
  2611. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2612. {
  2613. struct wcd938x_pdata *pdata = NULL;
  2614. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2615. GFP_KERNEL);
  2616. if (!pdata)
  2617. return NULL;
  2618. pdata->rst_np = of_parse_phandle(dev->of_node,
  2619. "qcom,wcd-rst-gpio-node", 0);
  2620. if (!pdata->rst_np) {
  2621. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2622. __func__, "qcom,wcd-rst-gpio-node",
  2623. dev->of_node->full_name);
  2624. return NULL;
  2625. }
  2626. /* Parse power supplies */
  2627. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2628. &pdata->num_supplies);
  2629. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2630. dev_err(dev, "%s: no power supplies defined for codec\n",
  2631. __func__);
  2632. return NULL;
  2633. }
  2634. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2635. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2636. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2637. return pdata;
  2638. }
  2639. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  2640. {
  2641. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2642. __func__, irq);
  2643. return IRQ_HANDLED;
  2644. }
  2645. static int wcd938x_bind(struct device *dev)
  2646. {
  2647. int ret = 0, i = 0;
  2648. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2649. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2650. /*
  2651. * Add 5msec delay to provide sufficient time for
  2652. * soundwire auto enumeration of slave devices as
  2653. * as per HW requirement.
  2654. */
  2655. usleep_range(5000, 5010);
  2656. ret = component_bind_all(dev, wcd938x);
  2657. if (ret) {
  2658. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2659. __func__, ret);
  2660. return ret;
  2661. }
  2662. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2663. if (!wcd938x->rx_swr_dev) {
  2664. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2665. __func__);
  2666. ret = -ENODEV;
  2667. goto err;
  2668. }
  2669. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2670. if (!wcd938x->tx_swr_dev) {
  2671. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2672. __func__);
  2673. ret = -ENODEV;
  2674. goto err;
  2675. }
  2676. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2677. &wcd938x_regmap_config);
  2678. if (!wcd938x->regmap) {
  2679. dev_err(dev, "%s: Regmap init failed\n",
  2680. __func__);
  2681. goto err;
  2682. }
  2683. /* Set all interupts as edge triggered */
  2684. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2685. regmap_write(wcd938x->regmap,
  2686. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2687. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2688. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2689. wcd938x->irq_info.codec_name = "WCD938X";
  2690. wcd938x->irq_info.regmap = wcd938x->regmap;
  2691. wcd938x->irq_info.dev = dev;
  2692. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2693. if (ret) {
  2694. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2695. __func__, ret);
  2696. goto err;
  2697. }
  2698. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2699. /* Request for watchdog interrupt */
  2700. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  2701. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2702. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  2703. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2704. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  2705. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  2706. /* Disable watchdog interrupt for HPH and AUX */
  2707. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  2708. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  2709. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  2710. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2711. NULL, 0);
  2712. if (ret) {
  2713. dev_err(dev, "%s: Codec registration failed\n",
  2714. __func__);
  2715. goto err_irq;
  2716. }
  2717. return ret;
  2718. err_irq:
  2719. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2720. err:
  2721. component_unbind_all(dev, wcd938x);
  2722. return ret;
  2723. }
  2724. static void wcd938x_unbind(struct device *dev)
  2725. {
  2726. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2727. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  2728. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  2729. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  2730. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2731. snd_soc_unregister_component(dev);
  2732. component_unbind_all(dev, wcd938x);
  2733. }
  2734. static const struct of_device_id wcd938x_dt_match[] = {
  2735. { .compatible = "qcom,wcd938x-codec" },
  2736. {}
  2737. };
  2738. static const struct component_master_ops wcd938x_comp_ops = {
  2739. .bind = wcd938x_bind,
  2740. .unbind = wcd938x_unbind,
  2741. };
  2742. static int wcd938x_compare_of(struct device *dev, void *data)
  2743. {
  2744. return dev->of_node == data;
  2745. }
  2746. static void wcd938x_release_of(struct device *dev, void *data)
  2747. {
  2748. of_node_put(data);
  2749. }
  2750. static int wcd938x_add_slave_components(struct device *dev,
  2751. struct component_match **matchptr)
  2752. {
  2753. struct device_node *np, *rx_node, *tx_node;
  2754. np = dev->of_node;
  2755. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2756. if (!rx_node) {
  2757. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2758. return -ENODEV;
  2759. }
  2760. of_node_get(rx_node);
  2761. component_match_add_release(dev, matchptr,
  2762. wcd938x_release_of,
  2763. wcd938x_compare_of,
  2764. rx_node);
  2765. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2766. if (!tx_node) {
  2767. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2768. return -ENODEV;
  2769. }
  2770. of_node_get(tx_node);
  2771. component_match_add_release(dev, matchptr,
  2772. wcd938x_release_of,
  2773. wcd938x_compare_of,
  2774. tx_node);
  2775. return 0;
  2776. }
  2777. static int wcd938x_wakeup(void *handle, bool enable)
  2778. {
  2779. struct wcd938x_priv *priv;
  2780. if (!handle) {
  2781. pr_err("%s: NULL handle\n", __func__);
  2782. return -EINVAL;
  2783. }
  2784. priv = (struct wcd938x_priv *)handle;
  2785. if (!priv->tx_swr_dev) {
  2786. pr_err("%s: tx swr dev is NULL\n", __func__);
  2787. return -EINVAL;
  2788. }
  2789. if (enable)
  2790. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2791. else
  2792. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2793. }
  2794. static int wcd938x_probe(struct platform_device *pdev)
  2795. {
  2796. struct component_match *match = NULL;
  2797. struct wcd938x_priv *wcd938x = NULL;
  2798. struct wcd938x_pdata *pdata = NULL;
  2799. struct wcd_ctrl_platform_data *plat_data = NULL;
  2800. struct device *dev = &pdev->dev;
  2801. int ret;
  2802. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  2803. GFP_KERNEL);
  2804. if (!wcd938x)
  2805. return -ENOMEM;
  2806. dev_set_drvdata(dev, wcd938x);
  2807. wcd938x->dev = dev;
  2808. pdata = wcd938x_populate_dt_data(dev);
  2809. if (!pdata) {
  2810. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2811. return -EINVAL;
  2812. }
  2813. dev->platform_data = pdata;
  2814. wcd938x->rst_np = pdata->rst_np;
  2815. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  2816. pdata->regulator, pdata->num_supplies);
  2817. if (!wcd938x->supplies) {
  2818. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2819. __func__);
  2820. return ret;
  2821. }
  2822. plat_data = dev_get_platdata(dev->parent);
  2823. if (!plat_data) {
  2824. dev_err(dev, "%s: platform data from parent is NULL\n",
  2825. __func__);
  2826. return -EINVAL;
  2827. }
  2828. wcd938x->handle = (void *)plat_data->handle;
  2829. if (!wcd938x->handle) {
  2830. dev_err(dev, "%s: handle is NULL\n", __func__);
  2831. return -EINVAL;
  2832. }
  2833. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  2834. if (!wcd938x->update_wcd_event) {
  2835. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2836. __func__);
  2837. return -EINVAL;
  2838. }
  2839. wcd938x->register_notifier = plat_data->register_notifier;
  2840. if (!wcd938x->register_notifier) {
  2841. dev_err(dev, "%s: register_notifier api is null!\n",
  2842. __func__);
  2843. return -EINVAL;
  2844. }
  2845. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  2846. pdata->regulator,
  2847. pdata->num_supplies);
  2848. if (ret) {
  2849. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2850. __func__);
  2851. return ret;
  2852. }
  2853. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  2854. CODEC_RX);
  2855. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  2856. CODEC_TX);
  2857. if (ret) {
  2858. dev_err(dev, "Failed to read port mapping\n");
  2859. goto err;
  2860. }
  2861. mutex_init(&wcd938x->micb_lock);
  2862. ret = wcd938x_add_slave_components(dev, &match);
  2863. if (ret)
  2864. goto err_lock_init;
  2865. wcd938x_reset(dev);
  2866. wcd938x->wakeup = wcd938x_wakeup;
  2867. return component_master_add_with_match(dev,
  2868. &wcd938x_comp_ops, match);
  2869. err_lock_init:
  2870. mutex_destroy(&wcd938x->micb_lock);
  2871. err:
  2872. return ret;
  2873. }
  2874. static int wcd938x_remove(struct platform_device *pdev)
  2875. {
  2876. struct wcd938x_priv *wcd938x = NULL;
  2877. wcd938x = platform_get_drvdata(pdev);
  2878. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  2879. mutex_destroy(&wcd938x->micb_lock);
  2880. dev_set_drvdata(&pdev->dev, NULL);
  2881. return 0;
  2882. }
  2883. #ifdef CONFIG_PM_SLEEP
  2884. static int wcd938x_suspend(struct device *dev)
  2885. {
  2886. return 0;
  2887. }
  2888. static int wcd938x_resume(struct device *dev)
  2889. {
  2890. return 0;
  2891. }
  2892. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  2893. SET_SYSTEM_SLEEP_PM_OPS(
  2894. wcd938x_suspend,
  2895. wcd938x_resume
  2896. )
  2897. };
  2898. #endif
  2899. static struct platform_driver wcd938x_codec_driver = {
  2900. .probe = wcd938x_probe,
  2901. .remove = wcd938x_remove,
  2902. .driver = {
  2903. .name = "wcd938x_codec",
  2904. .owner = THIS_MODULE,
  2905. .of_match_table = of_match_ptr(wcd938x_dt_match),
  2906. #ifdef CONFIG_PM_SLEEP
  2907. .pm = &wcd938x_dev_pm_ops,
  2908. #endif
  2909. .suppress_bind_attrs = true,
  2910. },
  2911. };
  2912. module_platform_driver(wcd938x_codec_driver);
  2913. MODULE_DESCRIPTION("WCD938X Codec driver");
  2914. MODULE_LICENSE("GPL v2");